diff --git a/misc/STM32H743.svd b/misc/STM32H743.svd new file mode 100644 index 0000000..a01959f --- /dev/null +++ b/misc/STM32H743.svd @@ -0,0 +1,105057 @@ + + + + STM32H743 + 1.4 + STM32H743 + + CM7 + r0p1 + little + true + true + 4 + false + + + + 8 + + 32 + + 0x20 + 0x0 + 0xFFFFFFFF + + + COMP1 + COMP1 + COMP1 + 0x58003800 + + 0x0 + 0x400 + registers + + + COMP + COMP1 and COMP2 + 137 + + + + SR + SR + Comparator status register + 0x0 + 0x20 + read-only + 0x00000000 + + + C1VAL + COMP channel 1 output status + bit + 0 + 1 + + + C2VAL + COMP channel 2 output status + bit + 1 + 1 + + + C1IF + COMP channel 1 Interrupt + Flag + 16 + 1 + + + C2IF + COMP channel 2 Interrupt + Flag + 17 + 1 + + + + + ICFR + ICFR + Comparator interrupt clear flag + register + 0x4 + 0x20 + write-only + 0x00000000 + + + CC1IF + Clear COMP channel 1 Interrupt + Flag + 16 + 1 + + + CC2IF + Clear COMP channel 2 Interrupt + Flag + 17 + 1 + + + + + OR + OR + Comparator option register + 0x8 + 0x20 + read-write + 0x00000000 + + + AFOP + Selection of source for alternate + function of output ports + 0 + 11 + + + OR + Option Register + 11 + 21 + + + + + CFGR1 + CFGR1 + Comparator configuration register + 1 + 0xC + 0x20 + read-write + 0x00000000 + + + EN + COMP channel 1 enable bit + 0 + 1 + + + BRGEN + Scaler bridge enable + 1 + 1 + + + SCALEN + Voltage scaler enable bit + 2 + 1 + + + POLARITY + COMP channel 1 polarity selection + bit + 3 + 1 + + + ITEN + COMP channel 1 interrupt + enable + 6 + 1 + + + HYST + COMP channel 1 hysteresis selection + bits + 8 + 2 + + + PWRMODE + Power Mode of the COMP channel + 1 + 12 + 2 + + + INMSEL + COMP channel 1 inverting input selection + field + 16 + 3 + + + INPSEL + COMP channel 1 non-inverting input + selection bit + 20 + 1 + + + BLANKING + COMP channel 1 blanking source selection + bits + 24 + 4 + + + LOCK + Lock bit + 31 + 1 + + + + + CFGR2 + CFGR2 + Comparator configuration register + 2 + 0x10 + 0x20 + read-write + 0x00000000 + + + EN + COMP channel 1 enable bit + 0 + 1 + + + BRGEN + Scaler bridge enable + 1 + 1 + + + SCALEN + Voltage scaler enable bit + 2 + 1 + + + POLARITY + COMP channel 1 polarity selection + bit + 3 + 1 + + + WINMODE + Window comparator mode selection + bit + 4 + 1 + + + ITEN + COMP channel 1 interrupt + enable + 6 + 1 + + + HYST + COMP channel 1 hysteresis selection + bits + 8 + 2 + + + PWRMODE + Power Mode of the COMP channel + 1 + 12 + 2 + + + INMSEL + COMP channel 1 inverting input selection + field + 16 + 3 + + + INPSEL + COMP channel 1 non-inverting input + selection bit + 20 + 1 + + + BLANKING + COMP channel 1 blanking source selection + bits + 24 + 4 + + + LOCK + Lock bit + 31 + 1 + + + + + + + CRS + CRS + CRS + 0x40008400 + + 0x0 + 0x400 + registers + + + CRS + Clock Recovery System globa + 144 + + + + CR + CR + CRS control register + 0x0 + 0x20 + 0x00002000 + + + SYNCOKIE + SYNC event OK interrupt + enable + 0 + 1 + read-write + + + SYNCWARNIE + SYNC warning interrupt + enable + 1 + 1 + read-write + + + ERRIE + Synchronization or trimming error + interrupt enable + 2 + 1 + read-write + + + ESYNCIE + Expected SYNC interrupt + enable + 3 + 1 + read-write + + + CEN + Frequency error counter enable This bit + enables the oscillator clock for the frequency error + counter. When this bit is set, the CRS_CFGR register + is write-protected and cannot be + modified. + 5 + 1 + read-write + + + AUTOTRIMEN + Automatic trimming enable This bit + enables the automatic hardware adjustment of TRIM + bits according to the measured frequency error + between two SYNC events. If this bit is set, the TRIM + bits are read-only. The TRIM value can be adjusted by + hardware by one or two steps at a time, depending on + the measured frequency error value. Refer to + Section7.3.4: Frequency error evaluation and + automatic trimming for more details. + 6 + 1 + read-write + + + SWSYNC + Generate software SYNC event This bit is + set by software in order to generate a software SYNC + event. It is automatically cleared by + hardware. + 7 + 1 + read-only + + + TRIM + HSI48 oscillator smooth trimming These + bits provide a user-programmable trimming value to + the HSI48 oscillator. They can be programmed to + adjust to variations in voltage and temperature that + influence the frequency of the HSI48. The default + value is 32, which corresponds to the middle of the + trimming interval. The trimming step is around 67 kHz + between two consecutive TRIM steps. A higher TRIM + value corresponds to a higher output frequency. When + the AUTOTRIMEN bit is set, this field is controlled + by hardware and is read-only. + 8 + 6 + read-write + + + + + CFGR + CFGR + This register can be written only when the + frequency error counter is disabled (CEN bit is cleared + in CRS_CR). When the counter is enabled, this register is + write-protected. + 0x4 + 0x20 + read-write + 0x2022BB7F + + + RELOAD + Counter reload value RELOAD is the value + to be loaded in the frequency error counter with each + SYNC event. Refer to Section7.3.3: Frequency error + measurement for more details about counter + behavior. + 0 + 16 + + + FELIM + Frequency error limit FELIM contains the + value to be used to evaluate the captured frequency + error value latched in the FECAP[15:0] bits of the + CRS_ISR register. Refer to Section7.3.4: Frequency + error evaluation and automatic trimming for more + details about FECAP evaluation. + 16 + 8 + + + SYNCDIV + SYNC divider These bits are set and + cleared by software to control the division factor of + the SYNC signal. + 24 + 3 + + + SYNCSRC + SYNC signal source selection These bits + are set and cleared by software to select the SYNC + signal source. Note: When using USB LPM (Link Power + Management) and the device is in Sleep mode, the + periodic USB SOF will not be generated by the host. + No SYNC signal will therefore be provided to the CRS + to calibrate the HSI48 on the run. To guarantee the + required clock precision after waking up from Sleep + mode, the LSE or reference clock on the GPIOs should + be used as SYNC signal. + 28 + 2 + + + SYNCPOL + SYNC polarity selection This bit is set + and cleared by software to select the input polarity + for the SYNC signal source. + 31 + 1 + + + + + ISR + ISR + CRS interrupt and status + register + 0x8 + 0x20 + read-only + 0x00000000 + + + SYNCOKF + SYNC event OK flag This flag is set by + hardware when the measured frequency error is smaller + than FELIM * 3. This means that either no adjustment + of the TRIM value is needed or that an adjustment by + one trimming step is enough to compensate the + frequency error. An interrupt is generated if the + SYNCOKIE bit is set in the CRS_CR register. It is + cleared by software by setting the SYNCOKC bit in the + CRS_ICR register. + 0 + 1 + + + SYNCWARNF + SYNC warning flag This flag is set by + hardware when the measured frequency error is greater + than or equal to FELIM * 3, but smaller than FELIM * + 128. This means that to compensate the frequency + error, the TRIM value must be adjusted by two steps + or more. An interrupt is generated if the SYNCWARNIE + bit is set in the CRS_CR register. It is cleared by + software by setting the SYNCWARNC bit in the CRS_ICR + register. + 1 + 1 + + + ERRF + Error flag This flag is set by hardware + in case of any synchronization or trimming error. It + is the logical OR of the TRIMOVF, SYNCMISS and + SYNCERR bits. An interrupt is generated if the ERRIE + bit is set in the CRS_CR register. It is cleared by + software in reaction to setting the ERRC bit in the + CRS_ICR register, which clears the TRIMOVF, SYNCMISS + and SYNCERR bits. + 2 + 1 + + + ESYNCF + Expected SYNC flag This flag is set by + hardware when the frequency error counter reached a + zero value. An interrupt is generated if the ESYNCIE + bit is set in the CRS_CR register. It is cleared by + software by setting the ESYNCC bit in the CRS_ICR + register. + 3 + 1 + + + SYNCERR + SYNC error This flag is set by hardware + when the SYNC pulse arrives before the ESYNC event + and the measured frequency error is greater than or + equal to FELIM * 128. This means that the frequency + error is too big (internal frequency too low) to be + compensated by adjusting the TRIM value, and that + some other action should be taken. An interrupt is + generated if the ERRIE bit is set in the CRS_CR + register. It is cleared by software by setting the + ERRC bit in the CRS_ICR register. + 8 + 1 + + + SYNCMISS + SYNC missed This flag is set by hardware + when the frequency error counter reached value FELIM + * 128 and no SYNC was detected, meaning either that a + SYNC pulse was missed or that the frequency error is + too big (internal frequency too high) to be + compensated by adjusting the TRIM value, and that + some other action should be taken. At this point, the + frequency error counter is stopped (waiting for a + next SYNC) and an interrupt is generated if the ERRIE + bit is set in the CRS_CR register. It is cleared by + software by setting the ERRC bit in the CRS_ICR + register. + 9 + 1 + + + TRIMOVF + Trimming overflow or underflow This flag + is set by hardware when the automatic trimming tries + to over- or under-flow the TRIM value. An interrupt + is generated if the ERRIE bit is set in the CRS_CR + register. It is cleared by software by setting the + ERRC bit in the CRS_ICR register. + 10 + 1 + + + FEDIR + Frequency error direction FEDIR is the + counting direction of the frequency error counter + latched in the time of the last SYNC event. It shows + whether the actual frequency is below or above the + target. + 15 + 1 + + + FECAP + Frequency error capture FECAP is the + frequency error counter value latched in the time of + the last SYNC event. Refer to Section7.3.4: Frequency + error evaluation and automatic trimming for more + details about FECAP usage. + 16 + 16 + + + + + ICR + ICR + CRS interrupt flag clear + register + 0xC + 0x20 + read-write + 0x00000000 + + + SYNCOKC + SYNC event OK clear flag Writing 1 to + this bit clears the SYNCOKF flag in the CRS_ISR + register. + 0 + 1 + + + SYNCWARNC + SYNC warning clear flag Writing 1 to + this bit clears the SYNCWARNF flag in the CRS_ISR + register. + 1 + 1 + + + ERRC + Error clear flag Writing 1 to this bit + clears TRIMOVF, SYNCMISS and SYNCERR bits and + consequently also the ERRF flag in the CRS_ISR + register. + 2 + 1 + + + ESYNCC + Expected SYNC clear flag Writing 1 to + this bit clears the ESYNCF flag in the CRS_ISR + register. + 3 + 1 + + + + + + + DAC + DAC + DAC + 0x40007400 + + 0x0 + 0x400 + registers + + + + CR + CR + DAC control register + 0x0 + 0x20 + read-write + 0x00000000 + + + EN1 + DAC channel1 enable This bit is set and + cleared by software to enable/disable DAC + channel1. + 0 + 1 + + + TEN1 + DAC channel1 trigger + enable + 1 + 1 + + + TSEL1 + DAC channel1 trigger selection These + bits select the external event used to trigger DAC + channel1. Note: Only used if bit TEN1 = 1 (DAC + channel1 trigger enabled). + 2 + 3 + + + WAVE1 + DAC channel1 noise/triangle wave + generation enable These bits are set and cleared by + software. Note: Only used if bit TEN1 = 1 (DAC + channel1 trigger enabled). + 6 + 2 + + + MAMP1 + DAC channel1 mask/amplitude selector + These bits are written by software to select mask in + wave generation mode or amplitude in triangle + generation mode. = 1011: Unmask bits[11:0] of LFSR/ + triangle amplitude equal to 4095 + 8 + 4 + + + DMAEN1 + DAC channel1 DMA enable This bit is set + and cleared by software. + 12 + 1 + + + DMAUDRIE1 + DAC channel1 DMA Underrun Interrupt + enable This bit is set and cleared by + software. + 13 + 1 + + + CEN1 + DAC Channel 1 calibration enable This + bit is set and cleared by software to enable/disable + DAC channel 1 calibration, it can be written only if + bit EN1=0 into DAC_CR (the calibration mode can be + entered/exit only when the DAC channel is disabled) + Otherwise, the write operation is + ignored. + 14 + 1 + + + EN2 + DAC channel2 enable This bit is set and + cleared by software to enable/disable DAC + channel2. + 16 + 1 + + + TEN2 + DAC channel2 trigger + enable + 17 + 1 + + + TSEL2 + DAC channel2 trigger selection These + bits select the external event used to trigger DAC + channel2 Note: Only used if bit TEN2 = 1 (DAC + channel2 trigger enabled). + 18 + 3 + + + WAVE2 + DAC channel2 noise/triangle wave + generation enable These bits are set/reset by + software. 1x: Triangle wave generation enabled Note: + Only used if bit TEN2 = 1 (DAC channel2 trigger + enabled) + 22 + 2 + + + MAMP2 + DAC channel2 mask/amplitude selector + These bits are written by software to select mask in + wave generation mode or amplitude in triangle + generation mode. = 1011: Unmask bits[11:0] of LFSR/ + triangle amplitude equal to 4095 + 24 + 4 + + + DMAEN2 + DAC channel2 DMA enable This bit is set + and cleared by software. + 28 + 1 + + + DMAUDRIE2 + DAC channel2 DMA underrun interrupt + enable This bit is set and cleared by + software. + 29 + 1 + + + CEN2 + DAC Channel 2 calibration enable This + bit is set and cleared by software to enable/disable + DAC channel 2 calibration, it can be written only if + bit EN2=0 into DAC_CR (the calibration mode can be + entered/exit only when the DAC channel is disabled) + Otherwise, the write operation is + ignored. + 30 + 1 + + + + + SWTRGR + SWTRGR + DAC software trigger register + 0x4 + 0x20 + write-only + 0x00000000 + + + SWTRIG1 + DAC channel1 software trigger This bit + is set by software to trigger the DAC in software + trigger mode. Note: This bit is cleared by hardware + (one APB1 clock cycle later) once the DAC_DHR1 + register value has been loaded into the DAC_DOR1 + register. + 0 + 1 + + + SWTRIG2 + DAC channel2 software trigger This bit + is set by software to trigger the DAC in software + trigger mode. Note: This bit is cleared by hardware + (one APB1 clock cycle later) once the DAC_DHR2 + register value has been loaded into the DAC_DOR2 + register. + 1 + 1 + + + + + DHR12R1 + DHR12R1 + DAC channel1 12-bit right-aligned data + holding register + 0x8 + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 12-bit right-aligned data + These bits are written by software which specifies + 12-bit data for DAC channel1. + 0 + 12 + + + + + DHR12L1 + DHR12L1 + DAC channel1 12-bit left aligned data + holding register + 0xC + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 12-bit left-aligned data + These bits are written by software which specifies + 12-bit data for DAC channel1. + 4 + 12 + + + + + DHR8R1 + DHR8R1 + DAC channel1 8-bit right aligned data + holding register + 0x10 + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 8-bit right-aligned data + These bits are written by software which specifies + 8-bit data for DAC channel1. + 0 + 8 + + + + + DHR12R2 + DHR12R2 + DAC channel2 12-bit right aligned data + holding register + 0x14 + 0x20 + read-write + 0x00000000 + + + DACC2DHR + DAC channel2 12-bit right-aligned data + These bits are written by software which specifies + 12-bit data for DAC channel2. + 0 + 12 + + + + + DHR12L2 + DHR12L2 + DAC channel2 12-bit left aligned data + holding register + 0x18 + 0x20 + read-write + 0x00000000 + + + DACC2DHR + DAC channel2 12-bit left-aligned data + These bits are written by software which specify + 12-bit data for DAC channel2. + 4 + 12 + + + + + DHR8R2 + DHR8R2 + DAC channel2 8-bit right-aligned data + holding register + 0x1C + 0x20 + read-write + 0x00000000 + + + DACC2DHR + DAC channel2 8-bit right-aligned data + These bits are written by software which specifies + 8-bit data for DAC channel2. + 0 + 8 + + + + + DHR12RD + DHR12RD + Dual DAC 12-bit right-aligned data holding + register + 0x20 + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 12-bit right-aligned data + These bits are written by software which specifies + 12-bit data for DAC channel1. + 0 + 12 + + + DACC2DHR + DAC channel2 12-bit right-aligned data + These bits are written by software which specifies + 12-bit data for DAC channel2. + 16 + 12 + + + + + DHR12LD + DHR12LD + DUAL DAC 12-bit left aligned data holding + register + 0x24 + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 12-bit left-aligned data + These bits are written by software which specifies + 12-bit data for DAC channel1. + 4 + 12 + + + DACC2DHR + DAC channel2 12-bit left-aligned data + These bits are written by software which specifies + 12-bit data for DAC channel2. + 20 + 12 + + + + + DHR8RD + DHR8RD + DUAL DAC 8-bit right aligned data holding + register + 0x28 + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 8-bit right-aligned data + These bits are written by software which specifies + 8-bit data for DAC channel1. + 0 + 8 + + + DACC2DHR + DAC channel2 8-bit right-aligned data + These bits are written by software which specifies + 8-bit data for DAC channel2. + 8 + 8 + + + + + DOR1 + DOR1 + DAC channel1 data output + register + 0x2C + 0x20 + read-only + 0x00000000 + + + DACC1DOR + DAC channel1 data output These bits are + read-only, they contain data output for DAC + channel1. + 0 + 12 + + + + + DOR2 + DOR2 + DAC channel2 data output + register + 0x30 + 0x20 + read-only + 0x00000000 + + + DACC2DOR + DAC channel2 data output These bits are + read-only, they contain data output for DAC + channel2. + 0 + 12 + + + + + SR + SR + DAC status register + 0x34 + 0x20 + 0x00000000 + + + DMAUDR1 + DAC channel1 DMA underrun flag This bit + is set by hardware and cleared by software (by + writing it to 1). + 13 + 1 + read-write + + + CAL_FLAG1 + DAC Channel 1 calibration offset status + This bit is set and cleared by hardware + 14 + 1 + read-only + + + BWST1 + DAC Channel 1 busy writing sample time + flag This bit is systematically set just after Sample + & Hold mode enable and is set each time the + software writes the register DAC_SHSR1, It is cleared + by hardware when the write operation of DAC_SHSR1 is + complete. (It takes about 3LSI periods of + synchronization). + 15 + 1 + read-only + + + DMAUDR2 + DAC channel2 DMA underrun flag This bit + is set by hardware and cleared by software (by + writing it to 1). + 29 + 1 + read-write + + + CAL_FLAG2 + DAC Channel 2 calibration offset status + This bit is set and cleared by hardware + 30 + 1 + read-only + + + BWST2 + DAC Channel 2 busy writing sample time + flag This bit is systematically set just after Sample + & Hold mode enable and is set each time the + software writes the register DAC_SHSR2, It is cleared + by hardware when the write operation of DAC_SHSR2 is + complete. (It takes about 3 LSI periods of + synchronization). + 31 + 1 + read-only + + + + + CCR + CCR + DAC calibration control + register + 0x38 + 0x20 + read-write + 0x00000000 + + + OTRIM1 + DAC Channel 1 offset trimming + value + 0 + 5 + + + OTRIM2 + DAC Channel 2 offset trimming + value + 16 + 5 + + + + + MCR + MCR + DAC mode control register + 0x3C + 0x20 + read-write + 0x00000000 + + + MODE1 + DAC Channel 1 mode These bits can be + written only when the DAC is disabled and not in the + calibration mode (when bit EN1=0 and bit CEN1 =0 in + the DAC_CR register). If EN1=1 or CEN1 =1 the write + operation is ignored. They can be set and cleared by + software to select the DAC Channel 1 mode: DAC + Channel 1 in normal Mode DAC Channel 1 in sample + & hold mode + 0 + 3 + + + MODE2 + DAC Channel 2 mode These bits can be + written only when the DAC is disabled and not in the + calibration mode (when bit EN2=0 and bit CEN2 =0 in + the DAC_CR register). If EN2=1 or CEN2 =1 the write + operation is ignored. They can be set and cleared by + software to select the DAC Channel 2 mode: DAC + Channel 2 in normal Mode DAC Channel 2 in sample + & hold mode + 16 + 3 + + + + + SHSR1 + SHSR1 + DAC Sample and Hold sample time register + 1 + 0x40 + 0x20 + read-write + 0x00000000 + + + TSAMPLE1 + DAC Channel 1 sample Time (only valid in + sample & hold mode) These bits can be written + when the DAC channel1 is disabled or also during + normal operation. in the latter case, the write can + be done only when BWSTx of DAC_SR register is low, If + BWSTx=1, the write operation is + ignored. + 0 + 10 + + + + + SHSR2 + SHSR2 + DAC Sample and Hold sample time register + 2 + 0x44 + 0x20 + read-write + 0x00000000 + + + TSAMPLE2 + DAC Channel 2 sample Time (only valid in + sample & hold mode) These bits can be written + when the DAC channel2 is disabled or also during + normal operation. in the latter case, the write can + be done only when BWSTx of DAC_SR register is low, if + BWSTx=1, the write operation is + ignored. + 0 + 10 + + + + + SHHR + SHHR + DAC Sample and Hold hold time + register + 0x48 + 0x20 + read-write + 0x00010001 + + + THOLD1 + DAC Channel 1 hold Time (only valid in + sample & hold mode) Hold time= (THOLD[9:0]) x + T LSI + 0 + 10 + + + THOLD2 + DAC Channel 2 hold time (only valid in + sample & hold mode). Hold time= (THOLD[9:0]) + x T LSI + 16 + 10 + + + + + SHRR + SHRR + DAC Sample and Hold refresh time + register + 0x4C + 0x20 + read-write + 0x00010001 + + + TREFRESH1 + DAC Channel 1 refresh Time (only valid + in sample & hold mode) Refresh time= + (TREFRESH[7:0]) x T LSI + 0 + 8 + + + TREFRESH2 + DAC Channel 2 refresh Time (only valid + in sample & hold mode) Refresh time= + (TREFRESH[7:0]) x T LSI + 16 + 8 + + + + + + + BDMA + BDMA + BDMA + 0x58025400 + + 0x0 + 0x400 + registers + + + BDMA_CH1 + BDMA channel 1 interrupt + 129 + + + BDMA_CH2 + BDMA channel 2 interrupt + 130 + + + BDMA_CH3 + BDMA channel 3 interrupt + 131 + + + BDMA_CH4 + BDMA channel 4 interrupt + 132 + + + BDMA_CH5 + BDMA channel 5 interrupt + 133 + + + BDMA_CH6 + BDMA channel 6 interrupt + 134 + + + BDMA_CH7 + BDMA channel 7 interrupt + 135 + + + BDMA_CH8 + BDMA channel 8 interrupt + 136 + + + + ISR + ISR + DMA interrupt status register + 0x0 + 0x20 + read-only + 0x00000000 + + + GIF1 + Channel x global interrupt flag (x = + 1..8) This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCR register. + 0 + 1 + + + TCIF1 + Channel x transfer complete flag (x = + 1..8) This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCR register. + 1 + 1 + + + HTIF1 + Channel x half transfer flag (x = 1..8) + This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCR register. + 2 + 1 + + + TEIF1 + Channel x transfer error flag (x = 1..8) + This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCR register. + 3 + 1 + + + GIF2 + Channel x global interrupt flag (x = + 1..8) This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCR register. + 4 + 1 + + + TCIF2 + Channel x transfer complete flag (x = + 1..8) This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCR register. + 5 + 1 + + + HTIF2 + Channel x half transfer flag (x = 1..8) + This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCR register. + 6 + 1 + + + TEIF2 + Channel x transfer error flag (x = 1..8) + This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCR register. + 7 + 1 + + + GIF3 + Channel x global interrupt flag (x = + 1..8) This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCR register. + 8 + 1 + + + TCIF3 + Channel x transfer complete flag (x = + 1..8) This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCR register. + 9 + 1 + + + HTIF3 + Channel x half transfer flag (x = 1..8) + This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCR register. + 10 + 1 + + + TEIF3 + Channel x transfer error flag (x = 1..8) + This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCR register. + 11 + 1 + + + GIF4 + Channel x global interrupt flag (x = + 1..8) This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCR register. + 12 + 1 + + + TCIF4 + Channel x transfer complete flag (x = + 1..8) This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCR register. + 13 + 1 + + + HTIF4 + Channel x half transfer flag (x = 1..8) + This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCR register. + 14 + 1 + + + TEIF4 + Channel x transfer error flag (x = 1..8) + This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCR register. + 15 + 1 + + + GIF5 + Channel x global interrupt flag (x = + 1..8) This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCR register. + 16 + 1 + + + TCIF5 + Channel x transfer complete flag (x = + 1..8) This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCR register. + 17 + 1 + + + HTIF5 + Channel x half transfer flag (x = 1..8) + This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCR register. + 18 + 1 + + + TEIF5 + Channel x transfer error flag (x = 1..8) + This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCR register. + 19 + 1 + + + GIF6 + Channel x global interrupt flag (x = + 1..8) This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCR register. + 20 + 1 + + + TCIF6 + Channel x transfer complete flag (x = + 1..8) This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCR register. + 21 + 1 + + + HTIF6 + Channel x half transfer flag (x = 1..8) + This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCR register. + 22 + 1 + + + TEIF6 + Channel x transfer error flag (x = 1..8) + This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCR register. + 23 + 1 + + + GIF7 + Channel x global interrupt flag (x = + 1..8) This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCR register. + 24 + 1 + + + TCIF7 + Channel x transfer complete flag (x = + 1..8) This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCR register. + 25 + 1 + + + HTIF7 + Channel x half transfer flag (x = 1..8) + This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCR register. + 26 + 1 + + + TEIF7 + Channel x transfer error flag (x = 1..8) + This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCR register. + 27 + 1 + + + GIF8 + Channel x global interrupt flag (x = + 1..8) This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCR register. + 28 + 1 + + + TCIF8 + Channel x transfer complete flag (x = + 1..8) This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCR register. + 29 + 1 + + + HTIF8 + Channel x half transfer flag (x = 1..8) + This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCR register. + 30 + 1 + + + TEIF8 + Channel x transfer error flag (x = 1..8) + This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCR register. + 31 + 1 + + + + + IFCR + IFCR + DMA interrupt flag clear + register + 0x4 + 0x20 + write-only + 0x00000000 + + + CGIF1 + Channel x global interrupt clear This + bit is set and cleared by software. + 0 + 1 + + + CTCIF1 + Channel x transfer complete clear This + bit is set and cleared by software. + 1 + 1 + + + CHTIF1 + Channel x half transfer clear This bit + is set and cleared by software. + 2 + 1 + + + CTEIF1 + Channel x transfer error clear This bit + is set and cleared by software. + 3 + 1 + + + CGIF2 + Channel x global interrupt clear This + bit is set and cleared by software. + 4 + 1 + + + CTCIF2 + Channel x transfer complete clear This + bit is set and cleared by software. + 5 + 1 + + + CHTIF2 + Channel x half transfer clear This bit + is set and cleared by software. + 6 + 1 + + + CTEIF2 + Channel x transfer error clear This bit + is set and cleared by software. + 7 + 1 + + + CGIF3 + Channel x global interrupt clear This + bit is set and cleared by software. + 8 + 1 + + + CTCIF3 + Channel x transfer complete clear This + bit is set and cleared by software. + 9 + 1 + + + CHTIF3 + Channel x half transfer clear This bit + is set and cleared by software. + 10 + 1 + + + CTEIF3 + Channel x transfer error clear This bit + is set and cleared by software. + 11 + 1 + + + CGIF4 + Channel x global interrupt clear This + bit is set and cleared by software. + 12 + 1 + + + CTCIF4 + Channel x transfer complete clear This + bit is set and cleared by software. + 13 + 1 + + + CHTIF4 + Channel x half transfer clear This bit + is set and cleared by software. + 14 + 1 + + + CTEIF4 + Channel x transfer error clear This bit + is set and cleared by software. + 15 + 1 + + + CGIF5 + Channel x global interrupt clear This + bit is set and cleared by software. + 16 + 1 + + + CTCIF5 + Channel x transfer complete clear This + bit is set and cleared by software. + 17 + 1 + + + CHTIF5 + Channel x half transfer clear This bit + is set and cleared by software. + 18 + 1 + + + CTEIF5 + Channel x transfer error clear This bit + is set and cleared by software. + 19 + 1 + + + CGIF6 + Channel x global interrupt clear This + bit is set and cleared by software. + 20 + 1 + + + CTCIF6 + Channel x transfer complete clear This + bit is set and cleared by software. + 21 + 1 + + + CHTIF6 + Channel x half transfer clear This bit + is set and cleared by software. + 22 + 1 + + + CTEIF6 + Channel x transfer error clear This bit + is set and cleared by software. + 23 + 1 + + + CGIF7 + Channel x global interrupt clear This + bit is set and cleared by software. + 24 + 1 + + + CTCIF7 + Channel x transfer complete clear This + bit is set and cleared by software. + 25 + 1 + + + CHTIF7 + Channel x half transfer clear This bit + is set and cleared by software. + 26 + 1 + + + CTEIF7 + Channel x transfer error clear This bit + is set and cleared by software. + 27 + 1 + + + CGIF8 + Channel x global interrupt clear This + bit is set and cleared by software. + 28 + 1 + + + CTCIF8 + Channel x transfer complete clear This + bit is set and cleared by software. + 29 + 1 + + + CHTIF8 + Channel x half transfer clear This bit + is set and cleared by software. + 30 + 1 + + + CTEIF8 + Channel x transfer error clear This bit + is set and cleared by software. + 31 + 1 + + + + + CCR1 + CCR1 + DMA channel x configuration + register + 0x8 + 0x20 + read-write + 0x00000000 + + + EN + Channel enable This bit is set and + cleared by software. + 0 + 1 + + + TCIE + Transfer complete interrupt enable This + bit is set and cleared by software. + 1 + 1 + + + HTIE + Half transfer interrupt enable This bit + is set and cleared by software. + 2 + 1 + + + TEIE + Transfer error interrupt enable This bit + is set and cleared by software. + 3 + 1 + + + DIR + Data transfer direction This bit is set + and cleared by software. + 4 + 1 + + + CIRC + Circular mode This bit is set and + cleared by software. + 5 + 1 + + + PINC + Peripheral increment mode This bit is + set and cleared by software. + 6 + 1 + + + MINC + Memory increment mode This bit is set + and cleared by software. + 7 + 1 + + + PSIZE + Peripheral size These bits are set and + cleared by software. + 8 + 2 + + + MSIZE + Memory size These bits are set and + cleared by software. + 10 + 2 + + + PL + Channel priority level These bits are + set and cleared by software. + 12 + 2 + + + MEM2MEM + Memory to memory mode This bit is set + and cleared by software. + 14 + 1 + + + + + CNDTR1 + CNDTR1 + DMA channel x number of data + register + 0xC + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer Number of + data to be transferred (0 up to 65535). This register + can only be written when the channel is disabled. + Once the channel is enabled, this register is + read-only, indicating the remaining bytes to be + transmitted. This register decrements after each DMA + transfer. Once the transfer is completed, this + register can either stay at zero or be reloaded + automatically by the value previously programmed if + the channel is configured in auto-reload mode. If + this register is zero, no transaction can be served + whether the channel is enabled or not. + 0 + 16 + + + + + CPAR1 + CPAR1 + This register must not be written when the + channel is enabled. + 0x10 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address Base address of the + peripheral data register from/to which the data will + be read/written. When PSIZE is 01 (16-bit), the PA[0] + bit is ignored. Access is automatically aligned to a + half-word address. When PSIZE is 10 (32-bit), PA[1:0] + are ignored. Access is automatically aligned to a + word address. + 0 + 32 + + + + + CMAR1 + CMAR1 + This register must not be written when the + channel is enabled. + 0x14 + 0x20 + read-write + 0x00000000 + + + MA + Memory address Base address of the + memory area from/to which the data will be + read/written. When MSIZE is 01 (16-bit), the MA[0] + bit is ignored. Access is automatically aligned to a + half-word address. When MSIZE is 10 (32-bit), MA[1:0] + are ignored. Access is automatically aligned to a + word address. + 0 + 32 + + + + + CCR2 + CCR2 + DMA channel x configuration + register + 0x1C + 0x20 + read-write + 0x00000000 + + + EN + Channel enable This bit is set and + cleared by software. + 0 + 1 + + + TCIE + Transfer complete interrupt enable This + bit is set and cleared by software. + 1 + 1 + + + HTIE + Half transfer interrupt enable This bit + is set and cleared by software. + 2 + 1 + + + TEIE + Transfer error interrupt enable This bit + is set and cleared by software. + 3 + 1 + + + DIR + Data transfer direction This bit is set + and cleared by software. + 4 + 1 + + + CIRC + Circular mode This bit is set and + cleared by software. + 5 + 1 + + + PINC + Peripheral increment mode This bit is + set and cleared by software. + 6 + 1 + + + MINC + Memory increment mode This bit is set + and cleared by software. + 7 + 1 + + + PSIZE + Peripheral size These bits are set and + cleared by software. + 8 + 2 + + + MSIZE + Memory size These bits are set and + cleared by software. + 10 + 2 + + + PL + Channel priority level These bits are + set and cleared by software. + 12 + 2 + + + MEM2MEM + Memory to memory mode This bit is set + and cleared by software. + 14 + 1 + + + + + CNDTR2 + CNDTR2 + DMA channel x number of data + register + 0x20 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer Number of + data to be transferred (0 up to 65535). This register + can only be written when the channel is disabled. + Once the channel is enabled, this register is + read-only, indicating the remaining bytes to be + transmitted. This register decrements after each DMA + transfer. Once the transfer is completed, this + register can either stay at zero or be reloaded + automatically by the value previously programmed if + the channel is configured in auto-reload mode. If + this register is zero, no transaction can be served + whether the channel is enabled or not. + 0 + 16 + + + + + CPAR2 + CPAR2 + This register must not be written when the + channel is enabled. + 0x24 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address Base address of the + peripheral data register from/to which the data will + be read/written. When PSIZE is 01 (16-bit), the PA[0] + bit is ignored. Access is automatically aligned to a + half-word address. When PSIZE is 10 (32-bit), PA[1:0] + are ignored. Access is automatically aligned to a + word address. + 0 + 32 + + + + + CMAR2 + CMAR2 + This register must not be written when the + channel is enabled. + 0x28 + 0x20 + read-write + 0x00000000 + + + MA + Memory address Base address of the + memory area from/to which the data will be + read/written. When MSIZE is 01 (16-bit), the MA[0] + bit is ignored. Access is automatically aligned to a + half-word address. When MSIZE is 10 (32-bit), MA[1:0] + are ignored. Access is automatically aligned to a + word address. + 0 + 32 + + + + + CCR3 + CCR3 + DMA channel x configuration + register + 0x30 + 0x20 + read-write + 0x00000000 + + + EN + Channel enable This bit is set and + cleared by software. + 0 + 1 + + + TCIE + Transfer complete interrupt enable This + bit is set and cleared by software. + 1 + 1 + + + HTIE + Half transfer interrupt enable This bit + is set and cleared by software. + 2 + 1 + + + TEIE + Transfer error interrupt enable This bit + is set and cleared by software. + 3 + 1 + + + DIR + Data transfer direction This bit is set + and cleared by software. + 4 + 1 + + + CIRC + Circular mode This bit is set and + cleared by software. + 5 + 1 + + + PINC + Peripheral increment mode This bit is + set and cleared by software. + 6 + 1 + + + MINC + Memory increment mode This bit is set + and cleared by software. + 7 + 1 + + + PSIZE + Peripheral size These bits are set and + cleared by software. + 8 + 2 + + + MSIZE + Memory size These bits are set and + cleared by software. + 10 + 2 + + + PL + Channel priority level These bits are + set and cleared by software. + 12 + 2 + + + MEM2MEM + Memory to memory mode This bit is set + and cleared by software. + 14 + 1 + + + + + CNDTR3 + CNDTR3 + DMA channel x number of data + register + 0x34 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer Number of + data to be transferred (0 up to 65535). This register + can only be written when the channel is disabled. + Once the channel is enabled, this register is + read-only, indicating the remaining bytes to be + transmitted. This register decrements after each DMA + transfer. Once the transfer is completed, this + register can either stay at zero or be reloaded + automatically by the value previously programmed if + the channel is configured in auto-reload mode. If + this register is zero, no transaction can be served + whether the channel is enabled or not. + 0 + 16 + + + + + CPAR3 + CPAR3 + This register must not be written when the + channel is enabled. + 0x38 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address Base address of the + peripheral data register from/to which the data will + be read/written. When PSIZE is 01 (16-bit), the PA[0] + bit is ignored. Access is automatically aligned to a + half-word address. When PSIZE is 10 (32-bit), PA[1:0] + are ignored. Access is automatically aligned to a + word address. + 0 + 32 + + + + + CMAR3 + CMAR3 + This register must not be written when the + channel is enabled. + 0x3C + 0x20 + read-write + 0x00000000 + + + MA + Memory address Base address of the + memory area from/to which the data will be + read/written. When MSIZE is 01 (16-bit), the MA[0] + bit is ignored. Access is automatically aligned to a + half-word address. When MSIZE is 10 (32-bit), MA[1:0] + are ignored. Access is automatically aligned to a + word address. + 0 + 32 + + + + + CCR4 + CCR4 + DMA channel x configuration + register + 0x44 + 0x20 + read-write + 0x00000000 + + + EN + Channel enable This bit is set and + cleared by software. + 0 + 1 + + + TCIE + Transfer complete interrupt enable This + bit is set and cleared by software. + 1 + 1 + + + HTIE + Half transfer interrupt enable This bit + is set and cleared by software. + 2 + 1 + + + TEIE + Transfer error interrupt enable This bit + is set and cleared by software. + 3 + 1 + + + DIR + Data transfer direction This bit is set + and cleared by software. + 4 + 1 + + + CIRC + Circular mode This bit is set and + cleared by software. + 5 + 1 + + + PINC + Peripheral increment mode This bit is + set and cleared by software. + 6 + 1 + + + MINC + Memory increment mode This bit is set + and cleared by software. + 7 + 1 + + + PSIZE + Peripheral size These bits are set and + cleared by software. + 8 + 2 + + + MSIZE + Memory size These bits are set and + cleared by software. + 10 + 2 + + + PL + Channel priority level These bits are + set and cleared by software. + 12 + 2 + + + MEM2MEM + Memory to memory mode This bit is set + and cleared by software. + 14 + 1 + + + + + CNDTR4 + CNDTR4 + DMA channel x number of data + register + 0x48 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer Number of + data to be transferred (0 up to 65535). This register + can only be written when the channel is disabled. + Once the channel is enabled, this register is + read-only, indicating the remaining bytes to be + transmitted. This register decrements after each DMA + transfer. Once the transfer is completed, this + register can either stay at zero or be reloaded + automatically by the value previously programmed if + the channel is configured in auto-reload mode. If + this register is zero, no transaction can be served + whether the channel is enabled or not. + 0 + 16 + + + + + CPAR4 + CPAR4 + This register must not be written when the + channel is enabled. + 0x4C + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address Base address of the + peripheral data register from/to which the data will + be read/written. When PSIZE is 01 (16-bit), the PA[0] + bit is ignored. Access is automatically aligned to a + half-word address. When PSIZE is 10 (32-bit), PA[1:0] + are ignored. Access is automatically aligned to a + word address. + 0 + 32 + + + + + CMAR4 + CMAR4 + This register must not be written when the + channel is enabled. + 0x50 + 0x20 + read-write + 0x00000000 + + + MA + Memory address Base address of the + memory area from/to which the data will be + read/written. When MSIZE is 01 (16-bit), the MA[0] + bit is ignored. Access is automatically aligned to a + half-word address. When MSIZE is 10 (32-bit), MA[1:0] + are ignored. Access is automatically aligned to a + word address. + 0 + 32 + + + + + CCR5 + CCR5 + DMA channel x configuration + register + 0x58 + 0x20 + read-write + 0x00000000 + + + EN + Channel enable This bit is set and + cleared by software. + 0 + 1 + + + TCIE + Transfer complete interrupt enable This + bit is set and cleared by software. + 1 + 1 + + + HTIE + Half transfer interrupt enable This bit + is set and cleared by software. + 2 + 1 + + + TEIE + Transfer error interrupt enable This bit + is set and cleared by software. + 3 + 1 + + + DIR + Data transfer direction This bit is set + and cleared by software. + 4 + 1 + + + CIRC + Circular mode This bit is set and + cleared by software. + 5 + 1 + + + PINC + Peripheral increment mode This bit is + set and cleared by software. + 6 + 1 + + + MINC + Memory increment mode This bit is set + and cleared by software. + 7 + 1 + + + PSIZE + Peripheral size These bits are set and + cleared by software. + 8 + 2 + + + MSIZE + Memory size These bits are set and + cleared by software. + 10 + 2 + + + PL + Channel priority level These bits are + set and cleared by software. + 12 + 2 + + + MEM2MEM + Memory to memory mode This bit is set + and cleared by software. + 14 + 1 + + + + + CNDTR5 + CNDTR5 + DMA channel x number of data + register + 0x5C + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer Number of + data to be transferred (0 up to 65535). This register + can only be written when the channel is disabled. + Once the channel is enabled, this register is + read-only, indicating the remaining bytes to be + transmitted. This register decrements after each DMA + transfer. Once the transfer is completed, this + register can either stay at zero or be reloaded + automatically by the value previously programmed if + the channel is configured in auto-reload mode. If + this register is zero, no transaction can be served + whether the channel is enabled or not. + 0 + 16 + + + + + CPAR5 + CPAR5 + This register must not be written when the + channel is enabled. + 0x60 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address Base address of the + peripheral data register from/to which the data will + be read/written. When PSIZE is 01 (16-bit), the PA[0] + bit is ignored. Access is automatically aligned to a + half-word address. When PSIZE is 10 (32-bit), PA[1:0] + are ignored. Access is automatically aligned to a + word address. + 0 + 32 + + + + + CMAR5 + CMAR5 + This register must not be written when the + channel is enabled. + 0x64 + 0x20 + read-write + 0x00000000 + + + MA + Memory address Base address of the + memory area from/to which the data will be + read/written. When MSIZE is 01 (16-bit), the MA[0] + bit is ignored. Access is automatically aligned to a + half-word address. When MSIZE is 10 (32-bit), MA[1:0] + are ignored. Access is automatically aligned to a + word address. + 0 + 32 + + + + + CCR6 + CCR6 + DMA channel x configuration + register + 0x6C + 0x20 + read-write + 0x00000000 + + + EN + Channel enable This bit is set and + cleared by software. + 0 + 1 + + + TCIE + Transfer complete interrupt enable This + bit is set and cleared by software. + 1 + 1 + + + HTIE + Half transfer interrupt enable This bit + is set and cleared by software. + 2 + 1 + + + TEIE + Transfer error interrupt enable This bit + is set and cleared by software. + 3 + 1 + + + DIR + Data transfer direction This bit is set + and cleared by software. + 4 + 1 + + + CIRC + Circular mode This bit is set and + cleared by software. + 5 + 1 + + + PINC + Peripheral increment mode This bit is + set and cleared by software. + 6 + 1 + + + MINC + Memory increment mode This bit is set + and cleared by software. + 7 + 1 + + + PSIZE + Peripheral size These bits are set and + cleared by software. + 8 + 2 + + + MSIZE + Memory size These bits are set and + cleared by software. + 10 + 2 + + + PL + Channel priority level These bits are + set and cleared by software. + 12 + 2 + + + MEM2MEM + Memory to memory mode This bit is set + and cleared by software. + 14 + 1 + + + + + CNDTR6 + CNDTR6 + DMA channel x number of data + register + 0x70 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer Number of + data to be transferred (0 up to 65535). This register + can only be written when the channel is disabled. + Once the channel is enabled, this register is + read-only, indicating the remaining bytes to be + transmitted. This register decrements after each DMA + transfer. Once the transfer is completed, this + register can either stay at zero or be reloaded + automatically by the value previously programmed if + the channel is configured in auto-reload mode. If + this register is zero, no transaction can be served + whether the channel is enabled or not. + 0 + 16 + + + + + CPAR6 + CPAR6 + This register must not be written when the + channel is enabled. + 0x74 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address Base address of the + peripheral data register from/to which the data will + be read/written. When PSIZE is 01 (16-bit), the PA[0] + bit is ignored. Access is automatically aligned to a + half-word address. When PSIZE is 10 (32-bit), PA[1:0] + are ignored. Access is automatically aligned to a + word address. + 0 + 32 + + + + + CMAR6 + CMAR6 + This register must not be written when the + channel is enabled. + 0x78 + 0x20 + read-write + 0x00000000 + + + MA + Memory address Base address of the + memory area from/to which the data will be + read/written. When MSIZE is 01 (16-bit), the MA[0] + bit is ignored. Access is automatically aligned to a + half-word address. When MSIZE is 10 (32-bit), MA[1:0] + are ignored. Access is automatically aligned to a + word address. + 0 + 32 + + + + + CCR7 + CCR7 + DMA channel x configuration + register + 0x80 + 0x20 + read-write + 0x00000000 + + + EN + Channel enable This bit is set and + cleared by software. + 0 + 1 + + + TCIE + Transfer complete interrupt enable This + bit is set and cleared by software. + 1 + 1 + + + HTIE + Half transfer interrupt enable This bit + is set and cleared by software. + 2 + 1 + + + TEIE + Transfer error interrupt enable This bit + is set and cleared by software. + 3 + 1 + + + DIR + Data transfer direction This bit is set + and cleared by software. + 4 + 1 + + + CIRC + Circular mode This bit is set and + cleared by software. + 5 + 1 + + + PINC + Peripheral increment mode This bit is + set and cleared by software. + 6 + 1 + + + MINC + Memory increment mode This bit is set + and cleared by software. + 7 + 1 + + + PSIZE + Peripheral size These bits are set and + cleared by software. + 8 + 2 + + + MSIZE + Memory size These bits are set and + cleared by software. + 10 + 2 + + + PL + Channel priority level These bits are + set and cleared by software. + 12 + 2 + + + MEM2MEM + Memory to memory mode This bit is set + and cleared by software. + 14 + 1 + + + + + CNDTR7 + CNDTR7 + DMA channel x number of data + register + 0x84 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer Number of + data to be transferred (0 up to 65535). This register + can only be written when the channel is disabled. + Once the channel is enabled, this register is + read-only, indicating the remaining bytes to be + transmitted. This register decrements after each DMA + transfer. Once the transfer is completed, this + register can either stay at zero or be reloaded + automatically by the value previously programmed if + the channel is configured in auto-reload mode. If + this register is zero, no transaction can be served + whether the channel is enabled or not. + 0 + 16 + + + + + CPAR7 + CPAR7 + This register must not be written when the + channel is enabled. + 0x88 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address Base address of the + peripheral data register from/to which the data will + be read/written. When PSIZE is 01 (16-bit), the PA[0] + bit is ignored. Access is automatically aligned to a + half-word address. When PSIZE is 10 (32-bit), PA[1:0] + are ignored. Access is automatically aligned to a + word address. + 0 + 32 + + + + + CMAR7 + CMAR7 + This register must not be written when the + channel is enabled. + 0x8C + 0x20 + read-write + 0x00000000 + + + MA + Memory address Base address of the + memory area from/to which the data will be + read/written. When MSIZE is 01 (16-bit), the MA[0] + bit is ignored. Access is automatically aligned to a + half-word address. When MSIZE is 10 (32-bit), MA[1:0] + are ignored. Access is automatically aligned to a + word address. + 0 + 32 + + + + + CCR8 + CCR8 + DMA channel x configuration + register + 0x94 + 0x20 + read-write + 0x00000000 + + + EN + Channel enable This bit is set and + cleared by software. + 0 + 1 + + + TCIE + Transfer complete interrupt enable This + bit is set and cleared by software. + 1 + 1 + + + HTIE + Half transfer interrupt enable This bit + is set and cleared by software. + 2 + 1 + + + TEIE + Transfer error interrupt enable This bit + is set and cleared by software. + 3 + 1 + + + DIR + Data transfer direction This bit is set + and cleared by software. + 4 + 1 + + + CIRC + Circular mode This bit is set and + cleared by software. + 5 + 1 + + + PINC + Peripheral increment mode This bit is + set and cleared by software. + 6 + 1 + + + MINC + Memory increment mode This bit is set + and cleared by software. + 7 + 1 + + + PSIZE + Peripheral size These bits are set and + cleared by software. + 8 + 2 + + + MSIZE + Memory size These bits are set and + cleared by software. + 10 + 2 + + + PL + Channel priority level These bits are + set and cleared by software. + 12 + 2 + + + MEM2MEM + Memory to memory mode This bit is set + and cleared by software. + 14 + 1 + + + + + CNDTR8 + CNDTR8 + DMA channel x number of data + register + 0x98 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer Number of + data to be transferred (0 up to 65535). This register + can only be written when the channel is disabled. + Once the channel is enabled, this register is + read-only, indicating the remaining bytes to be + transmitted. This register decrements after each DMA + transfer. Once the transfer is completed, this + register can either stay at zero or be reloaded + automatically by the value previously programmed if + the channel is configured in auto-reload mode. If + this register is zero, no transaction can be served + whether the channel is enabled or not. + 0 + 16 + + + + + CPAR8 + CPAR8 + This register must not be written when the + channel is enabled. + 0x9C + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address Base address of the + peripheral data register from/to which the data will + be read/written. When PSIZE is 01 (16-bit), the PA[0] + bit is ignored. Access is automatically aligned to a + half-word address. When PSIZE is 10 (32-bit), PA[1:0] + are ignored. Access is automatically aligned to a + word address. + 0 + 32 + + + + + CMAR8 + CMAR8 + This register must not be written when the + channel is enabled. + 0xA0 + 0x20 + read-write + 0x00000000 + + + MA + Memory address Base address of the + memory area from/to which the data will be + read/written. When MSIZE is 01 (16-bit), the MA[0] + bit is ignored. Access is automatically aligned to a + half-word address. When MSIZE is 10 (32-bit), MA[1:0] + are ignored. Access is automatically aligned to a + word address. + 0 + 32 + + + + + + + DMA2D + DMA2D + DMA2D + 0x52001000 + + 0x0 + 0x400 + registers + + + DMA2D + DMA2D global interrupt + 90 + + + + CR + CR + DMA2D control register + 0x0 + 0x20 + read-write + 0x00000000 + + + START + Start This bit can be used to launch the + DMA2D according to the parameters loaded in the + various configuration registers + 0 + 1 + + + SUSP + Suspend This bit can be used to suspend + the current transfer. This bit is set and reset by + software. It is automatically reset by hardware when + the START bit is reset. + 1 + 1 + + + ABORT + Abort This bit can be used to abort the + current transfer. This bit is set by software and is + automatically reset by hardware when the START bit is + reset. + 2 + 1 + + + TEIE + Transfer error interrupt enable This bit + is set and cleared by software. + 8 + 1 + + + TCIE + Transfer complete interrupt enable This + bit is set and cleared by software. + 9 + 1 + + + TWIE + Transfer watermark interrupt enable This + bit is set and cleared by software. + 10 + 1 + + + CAEIE + CLUT access error interrupt enable This + bit is set and cleared by software. + 11 + 1 + + + CTCIE + CLUT transfer complete interrupt enable + This bit is set and cleared by + software. + 12 + 1 + + + CEIE + Configuration Error Interrupt Enable + This bit is set and cleared by + software. + 13 + 1 + + + MODE + DMA2D mode This bit is set and cleared + by software. It cannot be modified while a transfer + is ongoing. + 16 + 2 + + + + + ISR + ISR + DMA2D Interrupt Status + Register + 0x4 + 0x20 + read-only + 0x00000000 + + + TEIF + Transfer error interrupt flag This bit + is set when an error occurs during a DMA transfer + (data transfer or automatic CLUT + loading). + 0 + 1 + + + TCIF + Transfer complete interrupt flag This + bit is set when a DMA2D transfer operation is + complete (data transfer only). + 1 + 1 + + + TWIF + Transfer watermark interrupt flag This + bit is set when the last pixel of the watermarked + line has been transferred. + 2 + 1 + + + CAEIF + CLUT access error interrupt flag This + bit is set when the CPU accesses the CLUT while the + CLUT is being automatically copied from a system + memory to the internal DMA2D. + 3 + 1 + + + CTCIF + CLUT transfer complete interrupt flag + This bit is set when the CLUT copy from a system + memory area to the internal DMA2D memory is + complete. + 4 + 1 + + + CEIF + Configuration error interrupt flag This + bit is set when the START bit of DMA2D_CR, + DMA2DFGPFCCR or DMA2D_BGPFCCR is set and a wrong + configuration has been programmed. + 5 + 1 + + + + + IFCR + IFCR + DMA2D interrupt flag clear + register + 0x8 + 0x20 + read-write + 0x00000000 + + + CTEIF + Clear Transfer error interrupt flag + Programming this bit to 1 clears the TEIF flag in the + DMA2D_ISR register + 0 + 1 + + + CTCIF + Clear transfer complete interrupt flag + Programming this bit to 1 clears the TCIF flag in the + DMA2D_ISR register + 1 + 1 + + + CTWIF + Clear transfer watermark interrupt flag + Programming this bit to 1 clears the TWIF flag in the + DMA2D_ISR register + 2 + 1 + + + CAECIF + Clear CLUT access error interrupt flag + Programming this bit to 1 clears the CAEIF flag in + the DMA2D_ISR register + 3 + 1 + + + CCTCIF + Clear CLUT transfer complete interrupt + flag Programming this bit to 1 clears the CTCIF flag + in the DMA2D_ISR register + 4 + 1 + + + CCEIF + Clear configuration error interrupt flag + Programming this bit to 1 clears the CEIF flag in the + DMA2D_ISR register + 5 + 1 + + + + + FGMAR + FGMAR + DMA2D foreground memory address + register + 0xC + 0x20 + read-write + 0x00000000 + + + MA + Memory address Address of the data used + for the foreground image. This register can only be + written when data transfers are disabled. Once the + data transfer has started, this register is + read-only. The address alignment must match the image + format selected e.g. a 32-bit per pixel format must + be 32-bit aligned, a 16-bit per pixel format must be + 16-bit aligned and a 4-bit per pixel format must be + 8-bit aligned. + 0 + 32 + + + + + FGOR + FGOR + DMA2D foreground offset + register + 0x10 + 0x20 + read-write + 0x00000000 + + + LO + Line offset Line offset used for the + foreground expressed in pixel. This value is used to + generate the address. It is added at the end of each + line to determine the starting address of the next + line. These bits can only be written when data + transfers are disabled. Once a data transfer has + started, they become read-only. If the image format + is 4-bit per pixel, the line offset must be + even. + 0 + 14 + + + + + BGMAR + BGMAR + DMA2D background memory address + register + 0x14 + 0x20 + read-write + 0x00000000 + + + MA + Memory address Address of the data used + for the background image. This register can only be + written when data transfers are disabled. Once a data + transfer has started, this register is read-only. The + address alignment must match the image format + selected e.g. a 32-bit per pixel format must be + 32-bit aligned, a 16-bit per pixel format must be + 16-bit aligned and a 4-bit per pixel format must be + 8-bit aligned. + 0 + 32 + + + + + BGOR + BGOR + DMA2D background offset + register + 0x18 + 0x20 + read-write + 0x00000000 + + + LO + Line offset Line offset used for the + background image (expressed in pixel). This value is + used for the address generation. It is added at the + end of each line to determine the starting address of + the next line. These bits can only be written when + data transfers are disabled. Once data transfer has + started, they become read-only. If the image format + is 4-bit per pixel, the line offset must be + even. + 0 + 14 + + + + + FGPFCCR + FGPFCCR + DMA2D foreground PFC control + register + 0x1C + 0x20 + read-write + 0x00000000 + + + CM + Color mode These bits defines the color + format of the foreground image. They can only be + written when data transfers are disabled. Once the + transfer has started, they are read-only. others: + meaningless + 0 + 4 + + + CCM + CLUT color mode This bit defines the + color format of the CLUT. It can only be written when + the transfer is disabled. Once the CLUT transfer has + started, this bit is read-only. + 4 + 1 + + + START + Start This bit can be set to start the + automatic loading of the CLUT. It is automatically + reset: ** at the end of the transfer ** when the + transfer is aborted by the user application by + setting the ABORT bit in DMA2D_CR ** when a transfer + error occurs ** when the transfer has not started due + to a configuration error or another transfer + operation already ongoing (data transfer or automatic + background CLUT transfer). + 5 + 1 + + + CS + CLUT size These bits define the size of + the CLUT used for the foreground image. Once the CLUT + transfer has started, this field is read-only. The + number of CLUT entries is equal to CS[7:0] + + 1. + 8 + 8 + + + AM + Alpha mode These bits select the alpha + channel value to be used for the foreground image. + They can only be written data the transfer are + disabled. Once the transfer has started, they become + read-only. other configurations are + meaningless + 16 + 2 + + + CSS + Chroma Sub-Sampling These bits define + the chroma sub-sampling mode for YCbCr color mode. + Once the transfer has started, these bits are + read-only. others: meaningless + 18 + 2 + + + AI + Alpha Inverted This bit inverts the + alpha value. Once the transfer has started, this bit + is read-only. + 20 + 1 + + + RBS + Red Blue Swap This bit allows to swap + the R & B to support BGR or ABGR color + formats. Once the transfer has started, this bit is + read-only. + 21 + 1 + + + ALPHA + Alpha value These bits define a fixed + alpha channel value which can replace the original + alpha value or be multiplied by the original alpha + value according to the alpha mode selected through + the AM[1:0] bits. These bits can only be written when + data transfers are disabled. Once a transfer has + started, they become read-only. + 24 + 8 + + + + + FGCOLR + FGCOLR + DMA2D foreground color + register + 0x20 + 0x20 + read-write + 0x00000000 + + + BLUE + Blue Value These bits defines the blue + value for the A4 or A8 mode of the foreground image. + They can only be written when data transfers are + disabled. Once the transfer has started, They are + read-only. + 0 + 8 + + + GREEN + Green Value These bits defines the green + value for the A4 or A8 mode of the foreground image. + They can only be written when data transfers are + disabled. Once the transfer has started, They are + read-only. + 8 + 8 + + + RED + Red Value These bits defines the red + value for the A4 or A8 mode of the foreground image. + They can only be written when data transfers are + disabled. Once the transfer has started, they are + read-only. + 16 + 8 + + + + + BGPFCCR + BGPFCCR + DMA2D background PFC control + register + 0x24 + 0x20 + read-write + 0x00000000 + + + CM + Color mode These bits define the color + format of the foreground image. These bits can only + be written when data transfers are disabled. Once the + transfer has started, they are read-only. others: + meaningless + 0 + 4 + + + CCM + CLUT Color mode These bits define the + color format of the CLUT. This register can only be + written when the transfer is disabled. Once the CLUT + transfer has started, this bit is + read-only. + 4 + 1 + + + START + Start This bit is set to start the + automatic loading of the CLUT. This bit is + automatically reset: ** at the end of the transfer ** + when the transfer is aborted by the user application + by setting the ABORT bit in the DMA2D_CR ** when a + transfer error occurs ** when the transfer has not + started due to a configuration error or another + transfer operation already on going (data transfer or + automatic BackGround CLUT transfer). + 5 + 1 + + + CS + CLUT size These bits define the size of + the CLUT used for the BG. Once the CLUT transfer has + started, this field is read-only. The number of CLUT + entries is equal to CS[7:0] + 1. + 8 + 8 + + + AM + Alpha mode These bits define which alpha + channel value to be used for the background image. + These bits can only be written when data transfers + are disabled. Once the transfer has started, they are + read-only. others: meaningless + 16 + 2 + + + AI + Alpha Inverted This bit inverts the + alpha value. Once the transfer has started, this bit + is read-only. + 20 + 1 + + + RBS + Red Blue Swap This bit allows to swap + the R & B to support BGR or ABGR color + formats. Once the transfer has started, this bit is + read-only. + 21 + 1 + + + ALPHA + Alpha value These bits define a fixed + alpha channel value which can replace the original + alpha value or be multiplied with the original alpha + value according to the alpha mode selected with bits + AM[1: 0]. These bits can only be written when data + transfers are disabled. Once the transfer has + started, they are read-only. + 24 + 8 + + + + + BGCOLR + BGCOLR + DMA2D background color + register + 0x28 + 0x20 + read-write + 0x00000000 + + + BLUE + Blue Value These bits define the blue + value for the A4 or A8 mode of the background. These + bits can only be written when data transfers are + disabled. Once the transfer has started, they are + read-only. + 0 + 8 + + + GREEN + Green Value These bits define the green + value for the A4 or A8 mode of the background. These + bits can only be written when data transfers are + disabled. Once the transfer has started, they are + read-only. + 8 + 8 + + + RED + Red Value These bits define the red + value for the A4 or A8 mode of the background. These + bits can only be written when data transfers are + disabled. Once the transfer has started, they are + read-only. + 16 + 8 + + + + + FGCMAR + FGCMAR + DMA2D foreground CLUT memory address + register + 0x2C + 0x20 + read-write + 0x00000000 + + + MA + Memory Address Address of the data used + for the CLUT address dedicated to the foreground + image. This register can only be written when no + transfer is ongoing. Once the CLUT transfer has + started, this register is read-only. If the + foreground CLUT format is 32-bit, the address must be + 32-bit aligned. + 0 + 32 + + + + + BGCMAR + BGCMAR + DMA2D background CLUT memory address + register + 0x30 + 0x20 + read-write + 0x00000000 + + + MA + Memory address Address of the data used + for the CLUT address dedicated to the background + image. This register can only be written when no + transfer is on going. Once the CLUT transfer has + started, this register is read-only. If the + background CLUT format is 32-bit, the address must be + 32-bit aligned. + 0 + 32 + + + + + OPFCCR + OPFCCR + DMA2D output PFC control + register + 0x34 + 0x20 + read-write + 0x00000000 + + + CM + Color mode These bits define the color + format of the output image. These bits can only be + written when data transfers are disabled. Once the + transfer has started, they are read-only. others: + meaningless + 0 + 3 + + + AI + Alpha Inverted This bit inverts the + alpha value. Once the transfer has started, this bit + is read-only. + 20 + 1 + + + RBS + Red Blue Swap This bit allows to swap + the R & B to support BGR or ABGR color + formats. Once the transfer has started, this bit is + read-only. + 21 + 1 + + + + + OCOLR + OCOLR + DMA2D output color register + 0x38 + 0x20 + read-write + 0x00000000 + + + BLUE + Blue Value These bits define the blue + value of the output image. These bits can only be + written when data transfers are disabled. Once the + transfer has started, they are + read-only. + 0 + 8 + + + GREEN + Green Value These bits define the green + value of the output image. These bits can only be + written when data transfers are disabled. Once the + transfer has started, they are + read-only. + 8 + 8 + + + RED + Red Value These bits define the red + value of the output image. These bits can only be + written when data transfers are disabled. Once the + transfer has started, they are + read-only. + 16 + 8 + + + ALPHA + Alpha Channel Value These bits define + the alpha channel of the output color. These bits can + only be written when data transfers are disabled. + Once the transfer has started, they are + read-only. + 24 + 8 + + + + + OMAR + OMAR + DMA2D output memory address + register + 0x3C + 0x20 + read-write + 0x00000000 + + + MA + Memory Address Address of the data used + for the output FIFO. These bits can only be written + when data transfers are disabled. Once the transfer + has started, they are read-only. The address + alignment must match the image format selected e.g. a + 32-bit per pixel format must be 32-bit aligned and a + 16-bit per pixel format must be 16-bit + aligned. + 0 + 32 + + + + + OOR + OOR + DMA2D output offset register + 0x40 + 0x20 + read-write + 0x00000000 + + + LO + Line Offset Line offset used for the + output (expressed in pixels). This value is used for + the address generation. It is added at the end of + each line to determine the starting address of the + next line. These bits can only be written when data + transfers are disabled. Once the transfer has + started, they are read-only. + 0 + 14 + + + + + NLR + NLR + DMA2D number of line register + 0x44 + 0x20 + read-write + 0x00000000 + + + NL + Number of lines Number of lines of the + area to be transferred. These bits can only be + written when data transfers are disabled. Once the + transfer has started, they are + read-only. + 0 + 16 + + + PL + Pixel per lines Number of pixels per + lines of the area to be transferred. These bits can + only be written when data transfers are disabled. + Once the transfer has started, they are read-only. If + any of the input image format is 4-bit per pixel, + pixel per lines must be even. + 16 + 14 + + + + + LWR + LWR + DMA2D line watermark register + 0x48 + 0x20 + read-write + 0x00000000 + + + LW + Line watermark These bits allow to + configure the line watermark for interrupt + generation. An interrupt is raised when the last + pixel of the watermarked line has been transferred. + These bits can only be written when data transfers + are disabled. Once the transfer has started, they are + read-only. + 0 + 16 + + + + + AMTCR + AMTCR + DMA2D AXI master timer configuration + register + 0x4C + 0x20 + read-write + 0x00000000 + + + EN + Enable Enables the dead time + functionality. + 0 + 1 + + + DT + Dead Time Dead time value in the AXI + clock cycle inserted between two consecutive accesses + on the AXI master port. These bits represent the + minimum guaranteed number of cycles between two + consecutive AXI accesses. + 8 + 8 + + + + + + + DMAMUX2 + DMAMUX + DMAMUX + 0x58025800 + + 0x0 + 0x400 + registers + + + DMAMUX2_OVR + DMAMUX2 overrun interrupt + 128 + + + + C0CR + C0CR + DMAMux - DMA request line multiplexer + channel x control register + 0x0 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line + selected + 0 + 8 + + + SOIE + Interrupt enable at synchronization + event overrun + 8 + 1 + + + EGE + Event generation + enable/disable + 9 + 1 + + + SE + Synchronous operating mode + enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector + Defines the synchronization event on the selected + synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward + Defines the number of DMA requests forwarded before + output event is generated. In synchronous mode, it + also defines the number of DMA requests to forward + after a synchronization event, then stop forwarding. + The actual number of DMA requests forwarded is + NBREQ+1. Note: This field can only be written when + both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input + selected + 24 + 5 + + + + + C1CR + C1CR + DMAMux - DMA request line multiplexer + channel x control register + 0x4 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line + selected + 0 + 8 + + + SOIE + Interrupt enable at synchronization + event overrun + 8 + 1 + + + EGE + Event generation + enable/disable + 9 + 1 + + + SE + Synchronous operating mode + enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector + Defines the synchronization event on the selected + synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward + Defines the number of DMA requests forwarded before + output event is generated. In synchronous mode, it + also defines the number of DMA requests to forward + after a synchronization event, then stop forwarding. + The actual number of DMA requests forwarded is + NBREQ+1. Note: This field can only be written when + both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input + selected + 24 + 5 + + + + + C2CR + C2CR + DMAMux - DMA request line multiplexer + channel x control register + 0x8 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line + selected + 0 + 8 + + + SOIE + Interrupt enable at synchronization + event overrun + 8 + 1 + + + EGE + Event generation + enable/disable + 9 + 1 + + + SE + Synchronous operating mode + enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector + Defines the synchronization event on the selected + synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward + Defines the number of DMA requests forwarded before + output event is generated. In synchronous mode, it + also defines the number of DMA requests to forward + after a synchronization event, then stop forwarding. + The actual number of DMA requests forwarded is + NBREQ+1. Note: This field can only be written when + both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input + selected + 24 + 5 + + + + + C3CR + C3CR + DMAMux - DMA request line multiplexer + channel x control register + 0xC + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line + selected + 0 + 8 + + + SOIE + Interrupt enable at synchronization + event overrun + 8 + 1 + + + EGE + Event generation + enable/disable + 9 + 1 + + + SE + Synchronous operating mode + enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector + Defines the synchronization event on the selected + synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward + Defines the number of DMA requests forwarded before + output event is generated. In synchronous mode, it + also defines the number of DMA requests to forward + after a synchronization event, then stop forwarding. + The actual number of DMA requests forwarded is + NBREQ+1. Note: This field can only be written when + both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input + selected + 24 + 5 + + + + + C4CR + C4CR + DMAMux - DMA request line multiplexer + channel x control register + 0x10 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line + selected + 0 + 8 + + + SOIE + Interrupt enable at synchronization + event overrun + 8 + 1 + + + EGE + Event generation + enable/disable + 9 + 1 + + + SE + Synchronous operating mode + enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector + Defines the synchronization event on the selected + synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward + Defines the number of DMA requests forwarded before + output event is generated. In synchronous mode, it + also defines the number of DMA requests to forward + after a synchronization event, then stop forwarding. + The actual number of DMA requests forwarded is + NBREQ+1. Note: This field can only be written when + both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input + selected + 24 + 5 + + + + + C5CR + C5CR + DMAMux - DMA request line multiplexer + channel x control register + 0x14 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line + selected + 0 + 8 + + + SOIE + Interrupt enable at synchronization + event overrun + 8 + 1 + + + EGE + Event generation + enable/disable + 9 + 1 + + + SE + Synchronous operating mode + enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector + Defines the synchronization event on the selected + synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward + Defines the number of DMA requests forwarded before + output event is generated. In synchronous mode, it + also defines the number of DMA requests to forward + after a synchronization event, then stop forwarding. + The actual number of DMA requests forwarded is + NBREQ+1. Note: This field can only be written when + both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input + selected + 24 + 5 + + + + + C6CR + C6CR + DMAMux - DMA request line multiplexer + channel x control register + 0x18 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line + selected + 0 + 8 + + + SOIE + Interrupt enable at synchronization + event overrun + 8 + 1 + + + EGE + Event generation + enable/disable + 9 + 1 + + + SE + Synchronous operating mode + enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector + Defines the synchronization event on the selected + synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward + Defines the number of DMA requests forwarded before + output event is generated. In synchronous mode, it + also defines the number of DMA requests to forward + after a synchronization event, then stop forwarding. + The actual number of DMA requests forwarded is + NBREQ+1. Note: This field can only be written when + both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input + selected + 24 + 5 + + + + + C7CR + C7CR + DMAMux - DMA request line multiplexer + channel x control register + 0x1C + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line + selected + 0 + 8 + + + SOIE + Interrupt enable at synchronization + event overrun + 8 + 1 + + + EGE + Event generation + enable/disable + 9 + 1 + + + SE + Synchronous operating mode + enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector + Defines the synchronization event on the selected + synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward + Defines the number of DMA requests forwarded before + output event is generated. In synchronous mode, it + also defines the number of DMA requests to forward + after a synchronization event, then stop forwarding. + The actual number of DMA requests forwarded is + NBREQ+1. Note: This field can only be written when + both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input + selected + 24 + 5 + + + + + RG0CR + RG0CR + DMAMux - DMA request generator channel x + control register + 0x100 + 0x20 + read-write + 0x00000000 + + + SIG_ID + DMA request trigger input + selected + 0 + 5 + + + OIE + Interrupt enable at trigger event + overrun + 8 + 1 + + + GE + DMA request generator channel + enable/disable + 16 + 1 + + + GPOL + DMA request generator trigger event type + selection Defines the trigger event on the selected + DMA request trigger input + 17 + 2 + + + GNBREQ + Number of DMA requests to generate + Defines the number of DMA requests generated after a + trigger event, then stop generating. The actual + number of generated DMA requests is GNBREQ+1. Note: + This field can only be written when GE bit is + reset. + 19 + 5 + + + + + RG1CR + RG1CR + DMAMux - DMA request generator channel x + control register + 0x104 + 0x20 + read-write + 0x00000000 + + + SIG_ID + DMA request trigger input + selected + 0 + 5 + + + OIE + Interrupt enable at trigger event + overrun + 8 + 1 + + + GE + DMA request generator channel + enable/disable + 16 + 1 + + + GPOL + DMA request generator trigger event type + selection Defines the trigger event on the selected + DMA request trigger input + 17 + 2 + + + GNBREQ + Number of DMA requests to generate + Defines the number of DMA requests generated after a + trigger event, then stop generating. The actual + number of generated DMA requests is GNBREQ+1. Note: + This field can only be written when GE bit is + reset. + 19 + 5 + + + + + RG2CR + RG2CR + DMAMux - DMA request generator channel x + control register + 0x108 + 0x20 + read-write + 0x00000000 + + + SIG_ID + DMA request trigger input + selected + 0 + 5 + + + OIE + Interrupt enable at trigger event + overrun + 8 + 1 + + + GE + DMA request generator channel + enable/disable + 16 + 1 + + + GPOL + DMA request generator trigger event type + selection Defines the trigger event on the selected + DMA request trigger input + 17 + 2 + + + GNBREQ + Number of DMA requests to generate + Defines the number of DMA requests generated after a + trigger event, then stop generating. The actual + number of generated DMA requests is GNBREQ+1. Note: + This field can only be written when GE bit is + reset. + 19 + 5 + + + + + RG3CR + RG3CR + DMAMux - DMA request generator channel x + control register + 0x10C + 0x20 + read-write + 0x00000000 + + + SIG_ID + DMA request trigger input + selected + 0 + 5 + + + OIE + Interrupt enable at trigger event + overrun + 8 + 1 + + + GE + DMA request generator channel + enable/disable + 16 + 1 + + + GPOL + DMA request generator trigger event type + selection Defines the trigger event on the selected + DMA request trigger input + 17 + 2 + + + GNBREQ + Number of DMA requests to generate + Defines the number of DMA requests generated after a + trigger event, then stop generating. The actual + number of generated DMA requests is GNBREQ+1. Note: + This field can only be written when GE bit is + reset. + 19 + 5 + + + + + RG4CR + RG4CR + DMAMux - DMA request generator channel x + control register + 0x110 + 0x20 + read-write + 0x00000000 + + + SIG_ID + DMA request trigger input + selected + 0 + 5 + + + OIE + Interrupt enable at trigger event + overrun + 8 + 1 + + + GE + DMA request generator channel + enable/disable + 16 + 1 + + + GPOL + DMA request generator trigger event type + selection Defines the trigger event on the selected + DMA request trigger input + 17 + 2 + + + GNBREQ + Number of DMA requests to generate + Defines the number of DMA requests generated after a + trigger event, then stop generating. The actual + number of generated DMA requests is GNBREQ+1. Note: + This field can only be written when GE bit is + reset. + 19 + 5 + + + + + RG5CR + RG5CR + DMAMux - DMA request generator channel x + control register + 0x114 + 0x20 + read-write + 0x00000000 + + + SIG_ID + DMA request trigger input + selected + 0 + 5 + + + OIE + Interrupt enable at trigger event + overrun + 8 + 1 + + + GE + DMA request generator channel + enable/disable + 16 + 1 + + + GPOL + DMA request generator trigger event type + selection Defines the trigger event on the selected + DMA request trigger input + 17 + 2 + + + GNBREQ + Number of DMA requests to generate + Defines the number of DMA requests generated after a + trigger event, then stop generating. The actual + number of generated DMA requests is GNBREQ+1. Note: + This field can only be written when GE bit is + reset. + 19 + 5 + + + + + RG6CR + RG6CR + DMAMux - DMA request generator channel x + control register + 0x118 + 0x20 + read-write + 0x00000000 + + + SIG_ID + DMA request trigger input + selected + 0 + 5 + + + OIE + Interrupt enable at trigger event + overrun + 8 + 1 + + + GE + DMA request generator channel + enable/disable + 16 + 1 + + + GPOL + DMA request generator trigger event type + selection Defines the trigger event on the selected + DMA request trigger input + 17 + 2 + + + GNBREQ + Number of DMA requests to generate + Defines the number of DMA requests generated after a + trigger event, then stop generating. The actual + number of generated DMA requests is GNBREQ+1. Note: + This field can only be written when GE bit is + reset. + 19 + 5 + + + + + RG7CR + RG7CR + DMAMux - DMA request generator channel x + control register + 0x11C + 0x20 + read-write + 0x00000000 + + + SIG_ID + DMA request trigger input + selected + 0 + 5 + + + OIE + Interrupt enable at trigger event + overrun + 8 + 1 + + + GE + DMA request generator channel + enable/disable + 16 + 1 + + + GPOL + DMA request generator trigger event type + selection Defines the trigger event on the selected + DMA request trigger input + 17 + 2 + + + GNBREQ + Number of DMA requests to generate + Defines the number of DMA requests generated after a + trigger event, then stop generating. The actual + number of generated DMA requests is GNBREQ+1. Note: + This field can only be written when GE bit is + reset. + 19 + 5 + + + + + RGSR + RGSR + DMAMux - DMA request generator status + register + 0x140 + 0x20 + read-only + 0x00000000 + + + OF + Trigger event overrun flag The flag is + set when a trigger event occurs on DMA request + generator channel x, while the DMA request generator + counter value is lower than GNBREQ. The flag is + cleared by writing 1 to the corresponding COFx bit in + DMAMUX_RGCFR register. + 0 + 8 + + + + + RGCFR + RGCFR + DMAMux - DMA request generator clear flag + register + 0x144 + 0x20 + write-only + 0x00000000 + + + COF + Clear trigger event overrun flag Upon + setting, this bit clears the corresponding overrun + flag OFx in the DMAMUX_RGCSR register. + 0 + 8 + + + + + CSR + CSR + DMAMUX request line multiplexer interrupt + channel status register + 0x80 + 0x20 + read-only + 0x00000000 + + + SOF + Synchronization overrun event + flag + 0 + 16 + + + + + CFR + CFR + DMAMUX request line multiplexer interrupt + clear flag register + 0x84 + 0x20 + write-only + 0x00000000 + + + CSOF + Clear synchronization overrun event + flag + 0 + 16 + + + + + + + FMC + FMC + FMC + 0x52004000 + + 0x0 + 0x400 + registers + + + FMC + FMC global interrupt + 48 + + + + BCR1 + BCR1 + This register contains the control + information of each memory bank, used for SRAMs, PSRAM + and NOR Flash memories. + 0x0 + 0x20 + read-write + 0x000030DB + + + MBKEN + Memory bank enable bit This bit enables + the memory bank. After reset Bank1 is enabled, all + others are disabled. Accessing a disabled bank causes + an ERROR on AXI bus. + 0 + 1 + + + MUXEN + Address/data multiplexing enable bit + When this bit is set, the address and data values are + multiplexed on the data bus, valid only with NOR and + PSRAM memories: + 1 + 1 + + + MTYP + Memory type These bits define the type + of external memory attached to the corresponding + memory bank: + 2 + 2 + + + MWID + Memory data bus width Defines the + external memory device width, valid for all type of + memories. + 4 + 2 + + + FACCEN + Flash access enable This bit enables NOR + Flash memory access operations. + 6 + 1 + + + BURSTEN + Burst enable bit This bit + enables/disables synchronous accesses during read + operations. It is valid only for synchronous memories + operating in Burst mode: + 8 + 1 + + + WAITPOL + Wait signal polarity bit This bit + defines the polarity of the wait signal from memory + used for either in synchronous or asynchronous + mode: + 9 + 1 + + + WAITCFG + Wait timing configuration The NWAIT + signal indicates whether the data from the memory are + valid or if a wait state must be inserted when + accessing the memory in synchronous mode. This + configuration bit determines if NWAIT is asserted by + the memory one clock cycle before the wait state or + during the wait state: + 11 + 1 + + + WREN + Write enable bit This bit indicates + whether write operations are enabled/disabled in the + bank by the FMC: + 12 + 1 + + + WAITEN + Wait enable bit This bit + enables/disables wait-state insertion via the NWAIT + signal when accessing the memory in synchronous + mode. + 13 + 1 + + + EXTMOD + Extended mode enable. This bit enables + the FMC to program the write timings for asynchronous + accesses inside the FMC_BWTR register, thus resulting + in different timings for read and write operations. + Note: When the extended mode is disabled, the FMC can + operate in Mode1 or Mode2 as follows: ** Mode 1 is + the default mode when the SRAM/PSRAM memory type is + selected (MTYP =0x0 or 0x01) ** Mode 2 is the default + mode when the NOR memory type is selected (MTYP = + 0x10). + 14 + 1 + + + ASYNCWAIT + Wait signal during asynchronous + transfers This bit enables/disables the FMC to use + the wait signal even during an asynchronous + protocol. + 15 + 1 + + + CPSIZE + CRAM Page Size These are used for + Cellular RAM 1.5 which does not allow burst access to + cross the address boundaries between pages. When + these bits are configured, the FMC controller splits + automatically the burst access when the memory page + size is reached (refer to memory datasheet for page + size). Other configuration: reserved. + 16 + 3 + + + CBURSTRW + Write burst enable For PSRAM (CRAM) + operating in Burst mode, the bit enables synchronous + accesses during write operations. The enable bit for + synchronous read accesses is the BURSTEN bit in the + FMC_BCRx register. + 19 + 1 + + + CCLKEN + Continuous Clock Enable This bit enables + the FMC_CLK clock output to external memory devices. + Note: The CCLKEN bit of the FMC_BCR2..4 registers is + dont care. It is only enabled through the FMC_BCR1 + register. Bank 1 must be configured in synchronous + mode to generate the FMC_CLK continuous clock. If + CCLKEN bit is set, the FMC_CLK clock ratio is + specified by CLKDIV value in the FMC_BTR1 register. + CLKDIV in FMC_BWTR1 is dont care. If the synchronous + mode is used and CCLKEN bit is set, the synchronous + memories connected to other banks than Bank 1 are + clocked by the same clock (the CLKDIV value in the + FMC_BTR2..4 and FMC_BWTR2..4 registers for other + banks has no effect.) + 20 + 1 + + + WFDIS + Write FIFO Disable This bit disables the + Write FIFO used by the FMC controller. Note: The + WFDIS bit of the FMC_BCR2..4 registers is dont care. + It is only enabled through the FMC_BCR1 + register. + 21 + 1 + + + BMAP + FMC bank mapping These bits allows + different to remap SDRAM bank2 or swap the FMC + NOR/PSRAM and SDRAM banks.Refer to Table 10 for Note: + The BMAP bits of the FMC_BCR2..4 registers are dont + care. It is only enabled through the FMC_BCR1 + register. + 24 + 2 + + + FMCEN + FMC controller Enable This bit + enables/disables the FMC controller. Note: The FMCEN + bit of the FMC_BCR2..4 registers is dont care. It is + only enabled through the FMC_BCR1 + register. + 31 + 1 + + + + + BTR1 + BTR1 + This register contains the control + information of each memory bank, used for SRAMs, PSRAM + and NOR Flash memories.If the EXTMOD bit is set in the + FMC_BCRx register, then this register is partitioned for + write and read access, that is, 2 registers are + available: one to configure read accesses (this register) + and one to configure write accesses (FMC_BWTRx + registers). + 0x4 + 0x20 + read-write + 0x0FFFFFFF + + + ADDSET + Address setup phase duration These bits + are written by software to define the duration of the + address setup phase (refer to Figure81 to Figure93), + used in SRAMs, ROMs and asynchronous NOR Flash: For + each access mode address setup phase duration, please + refer to the respective figure (refer to Figure81 to + Figure93). Note: In synchronous accesses, this value + is dont care. In Muxed mode or Mode D, the minimum + value for ADDSET is 1. + 0 + 4 + + + ADDHLD + Address-hold phase duration These bits + are written by software to define the duration of the + address hold phase (refer to Figure81 to Figure93), + used in mode D or multiplexed accesses: For each + access mode address-hold phase duration, please refer + to the respective figure (Figure81 to Figure93). + Note: In synchronous accesses, this value is not + used, the address hold phase is always 1 memory clock + period duration. + 4 + 4 + + + DATAST + Data-phase duration These bits are + written by software to define the duration of the + data phase (refer to Figure81 to Figure93), used in + asynchronous accesses: For each memory type and + access mode data-phase duration, please refer to the + respective figure (Figure81 to Figure93). Example: + Mode1, write access, DATAST=1: Data-phase duration= + DATAST+1 = 2 KCK_FMC clock cycles. Note: In + synchronous accesses, this value is dont + care. + 8 + 8 + + + BUSTURN + Bus turnaround phase duration These bits + are written by software to add a delay at the end of + a write-to-read or read-to write transaction. The + programmed bus turnaround delay is inserted between + an asynchronous read (in muxed or mode D) or write + transaction and any other asynchronous /synchronous + read/write from/to a static bank. If a read operation + is performed, the bank can be the same or a different + one, whereas it must be different in case of write + operation to the bank, except in muxed mode or mode + D. In some cases, whatever the programmed BUSTRUN + values, the bus turnaround delay is fixed as follows: + The bus turnaround delay is not inserted between two + consecutive asynchronous write transfers to the same + static memory bank except in muxed mode and mode D. + There is a bus turnaround delay of 1 FMC clock cycle + between: Two consecutive asynchronous read transfers + to the same static memory bank except for modes muxed + and D. An asynchronous read to an asynchronous or + synchronous write to any static bank or dynamic bank + except in modes muxed and D mode. There is a bus + turnaround delay of 2 FMC clock cycle between: Two + consecutive synchronous write operations (in Burst or + Single mode) to the same bank. A synchronous write + (burst or single) access and an asynchronous write or + read transfer to or from static memory bank (the bank + can be the same or a different one in case of a read + operation. Two consecutive synchronous read + operations (in Burst or Single mode) followed by any + synchronous/asynchronous read or write from/to + another static memory bank. There is a bus turnaround + delay of 3 FMC clock cycle between: Two consecutive + synchronous write operations (in Burst or Single + mode) to different static banks. A synchronous write + access (in Burst or Single mode) and a synchronous + read from the same or a different bank. The bus + turnaround delay allows to match the minimum time + between consecutive transactions (tEHEL from NEx high + to NEx low) and the maximum time required by the + memory to free the data bus after a read access + (tEHQZ): (BUSTRUN + 1) KCK_FMC period ≥ + tEHELmin and (BUSTRUN + 2)KCK_FMC period ≥ + tEHQZmax if EXTMOD = 0 (BUSTRUN + 2)KCK_FMC period + ≥ max (tEHELmin, tEHQZmax) if EXTMOD = 126. + ... + 16 + 4 + + + CLKDIV + Clock divide ratio (for FMC_CLK signal) + These bits define the period of FMC_CLK clock output + signal, expressed in number of KCK_FMC cycles: In + asynchronous NOR Flash, SRAM or PSRAM accesses, this + value is dont care. Note: Refer to Section20.6.5: + Synchronous transactions for FMC_CLK divider ratio + formula) + 20 + 4 + + + DATLAT + Data latency for synchronous memory For + synchronous access with read write burst mode enabled + these bits define the number of memory clock + cycles + 24 + 4 + + + ACCMOD + Access mode These bits specify the + asynchronous access modes as shown in the timing + diagrams. They are taken into account only when the + EXTMOD bit in the FMC_BCRx register is + 1. + 28 + 2 + + + + + BCR2 + BCR2 + This register contains the control + information of each memory bank, used for SRAMs, PSRAM + and NOR Flash memories. + 0x8 + 0x20 + read-write + 0x000030D2 + + + MBKEN + Memory bank enable bit This bit enables + the memory bank. After reset Bank1 is enabled, all + others are disabled. Accessing a disabled bank causes + an ERROR on AXI bus. + 0 + 1 + + + MUXEN + Address/data multiplexing enable bit + When this bit is set, the address and data values are + multiplexed on the data bus, valid only with NOR and + PSRAM memories: + 1 + 1 + + + MTYP + Memory type These bits define the type + of external memory attached to the corresponding + memory bank: + 2 + 2 + + + MWID + Memory data bus width Defines the + external memory device width, valid for all type of + memories. + 4 + 2 + + + FACCEN + Flash access enable This bit enables NOR + Flash memory access operations. + 6 + 1 + + + BURSTEN + Burst enable bit This bit + enables/disables synchronous accesses during read + operations. It is valid only for synchronous memories + operating in Burst mode: + 8 + 1 + + + WAITPOL + Wait signal polarity bit This bit + defines the polarity of the wait signal from memory + used for either in synchronous or asynchronous + mode: + 9 + 1 + + + WAITCFG + Wait timing configuration The NWAIT + signal indicates whether the data from the memory are + valid or if a wait state must be inserted when + accessing the memory in synchronous mode. This + configuration bit determines if NWAIT is asserted by + the memory one clock cycle before the wait state or + during the wait state: + 11 + 1 + + + WREN + Write enable bit This bit indicates + whether write operations are enabled/disabled in the + bank by the FMC: + 12 + 1 + + + WAITEN + Wait enable bit This bit + enables/disables wait-state insertion via the NWAIT + signal when accessing the memory in synchronous + mode. + 13 + 1 + + + EXTMOD + Extended mode enable. This bit enables + the FMC to program the write timings for asynchronous + accesses inside the FMC_BWTR register, thus resulting + in different timings for read and write operations. + Note: When the extended mode is disabled, the FMC can + operate in Mode1 or Mode2 as follows: ** Mode 1 is + the default mode when the SRAM/PSRAM memory type is + selected (MTYP =0x0 or 0x01) ** Mode 2 is the default + mode when the NOR memory type is selected (MTYP = + 0x10). + 14 + 1 + + + ASYNCWAIT + Wait signal during asynchronous + transfers This bit enables/disables the FMC to use + the wait signal even during an asynchronous + protocol. + 15 + 1 + + + CPSIZE + CRAM Page Size These are used for + Cellular RAM 1.5 which does not allow burst access to + cross the address boundaries between pages. When + these bits are configured, the FMC controller splits + automatically the burst access when the memory page + size is reached (refer to memory datasheet for page + size). Other configuration: reserved. + 16 + 3 + + + CBURSTRW + Write burst enable For PSRAM (CRAM) + operating in Burst mode, the bit enables synchronous + accesses during write operations. The enable bit for + synchronous read accesses is the BURSTEN bit in the + FMC_BCRx register. + 19 + 1 + + + CCLKEN + Continuous Clock Enable This bit enables + the FMC_CLK clock output to external memory devices. + Note: The CCLKEN bit of the FMC_BCR2..4 registers is + dont care. It is only enabled through the FMC_BCR1 + register. Bank 1 must be configured in synchronous + mode to generate the FMC_CLK continuous clock. If + CCLKEN bit is set, the FMC_CLK clock ratio is + specified by CLKDIV value in the FMC_BTR1 register. + CLKDIV in FMC_BWTR1 is dont care. If the synchronous + mode is used and CCLKEN bit is set, the synchronous + memories connected to other banks than Bank 1 are + clocked by the same clock (the CLKDIV value in the + FMC_BTR2..4 and FMC_BWTR2..4 registers for other + banks has no effect.) + 20 + 1 + + + WFDIS + Write FIFO Disable This bit disables the + Write FIFO used by the FMC controller. Note: The + WFDIS bit of the FMC_BCR2..4 registers is dont care. + It is only enabled through the FMC_BCR1 + register. + 21 + 1 + + + BMAP + FMC bank mapping These bits allows + different to remap SDRAM bank2 or swap the FMC + NOR/PSRAM and SDRAM banks.Refer to Table 10 for Note: + The BMAP bits of the FMC_BCR2..4 registers are dont + care. It is only enabled through the FMC_BCR1 + register. + 24 + 2 + + + FMCEN + FMC controller Enable This bit + enables/disables the FMC controller. Note: The FMCEN + bit of the FMC_BCR2..4 registers is dont care. It is + only enabled through the FMC_BCR1 + register. + 31 + 1 + + + + + BTR2 + BTR2 + This register contains the control + information of each memory bank, used for SRAMs, PSRAM + and NOR Flash memories.If the EXTMOD bit is set in the + FMC_BCRx register, then this register is partitioned for + write and read access, that is, 2 registers are + available: one to configure read accesses (this register) + and one to configure write accesses (FMC_BWTRx + registers). + 0xC + 0x20 + read-write + 0x0FFFFFFF + + + ADDSET + Address setup phase duration These bits + are written by software to define the duration of the + address setup phase (refer to Figure81 to Figure93), + used in SRAMs, ROMs and asynchronous NOR Flash: For + each access mode address setup phase duration, please + refer to the respective figure (refer to Figure81 to + Figure93). Note: In synchronous accesses, this value + is dont care. In Muxed mode or Mode D, the minimum + value for ADDSET is 1. + 0 + 4 + + + ADDHLD + Address-hold phase duration These bits + are written by software to define the duration of the + address hold phase (refer to Figure81 to Figure93), + used in mode D or multiplexed accesses: For each + access mode address-hold phase duration, please refer + to the respective figure (Figure81 to Figure93). + Note: In synchronous accesses, this value is not + used, the address hold phase is always 1 memory clock + period duration. + 4 + 4 + + + DATAST + Data-phase duration These bits are + written by software to define the duration of the + data phase (refer to Figure81 to Figure93), used in + asynchronous accesses: For each memory type and + access mode data-phase duration, please refer to the + respective figure (Figure81 to Figure93). Example: + Mode1, write access, DATAST=1: Data-phase duration= + DATAST+1 = 2 KCK_FMC clock cycles. Note: In + synchronous accesses, this value is dont + care. + 8 + 8 + + + BUSTURN + Bus turnaround phase duration These bits + are written by software to add a delay at the end of + a write-to-read or read-to write transaction. The + programmed bus turnaround delay is inserted between + an asynchronous read (in muxed or mode D) or write + transaction and any other asynchronous /synchronous + read/write from/to a static bank. If a read operation + is performed, the bank can be the same or a different + one, whereas it must be different in case of write + operation to the bank, except in muxed mode or mode + D. In some cases, whatever the programmed BUSTRUN + values, the bus turnaround delay is fixed as follows: + The bus turnaround delay is not inserted between two + consecutive asynchronous write transfers to the same + static memory bank except in muxed mode and mode D. + There is a bus turnaround delay of 1 FMC clock cycle + between: Two consecutive asynchronous read transfers + to the same static memory bank except for modes muxed + and D. An asynchronous read to an asynchronous or + synchronous write to any static bank or dynamic bank + except in modes muxed and D mode. There is a bus + turnaround delay of 2 FMC clock cycle between: Two + consecutive synchronous write operations (in Burst or + Single mode) to the same bank. A synchronous write + (burst or single) access and an asynchronous write or + read transfer to or from static memory bank (the bank + can be the same or a different one in case of a read + operation. Two consecutive synchronous read + operations (in Burst or Single mode) followed by any + synchronous/asynchronous read or write from/to + another static memory bank. There is a bus turnaround + delay of 3 FMC clock cycle between: Two consecutive + synchronous write operations (in Burst or Single + mode) to different static banks. A synchronous write + access (in Burst or Single mode) and a synchronous + read from the same or a different bank. The bus + turnaround delay allows to match the minimum time + between consecutive transactions (tEHEL from NEx high + to NEx low) and the maximum time required by the + memory to free the data bus after a read access + (tEHQZ): (BUSTRUN + 1) KCK_FMC period ≥ + tEHELmin and (BUSTRUN + 2)KCK_FMC period ≥ + tEHQZmax if EXTMOD = 0 (BUSTRUN + 2)KCK_FMC period + ≥ max (tEHELmin, tEHQZmax) if EXTMOD = 1. + ... + 16 + 4 + + + CLKDIV + Clock divide ratio (for FMC_CLK signal) + These bits define the period of FMC_CLK clock output + signal, expressed in number of KCK_FMC cycles: In + asynchronous NOR Flash, SRAM or PSRAM accesses, this + value is dont care. Note: Refer to Section20.6.5: + Synchronous transactions for FMC_CLK divider ratio + formula) + 20 + 4 + + + DATLAT + Data latency for synchronous memory For + synchronous access with read write burst mode enabled + these bits define the number of memory clock + cycles + 24 + 4 + + + ACCMOD + Access mode These bits specify the + asynchronous access modes as shown in the timing + diagrams. They are taken into account only when the + EXTMOD bit in the FMC_BCRx register is + 1. + 28 + 2 + + + + + BCR3 + BCR3 + This register contains the control + information of each memory bank, used for SRAMs, PSRAM + and NOR Flash memories. + 0x10 + 0x20 + read-write + 0x000030D2 + + + MBKEN + Memory bank enable bit This bit enables + the memory bank. After reset Bank1 is enabled, all + others are disabled. Accessing a disabled bank causes + an ERROR on AXI bus. + 0 + 1 + + + MUXEN + Address/data multiplexing enable bit + When this bit is set, the address and data values are + multiplexed on the data bus, valid only with NOR and + PSRAM memories: + 1 + 1 + + + MTYP + Memory type These bits define the type + of external memory attached to the corresponding + memory bank: + 2 + 2 + + + MWID + Memory data bus width Defines the + external memory device width, valid for all type of + memories. + 4 + 2 + + + FACCEN + Flash access enable This bit enables NOR + Flash memory access operations. + 6 + 1 + + + BURSTEN + Burst enable bit This bit + enables/disables synchronous accesses during read + operations. It is valid only for synchronous memories + operating in Burst mode: + 8 + 1 + + + WAITPOL + Wait signal polarity bit This bit + defines the polarity of the wait signal from memory + used for either in synchronous or asynchronous + mode: + 9 + 1 + + + WAITCFG + Wait timing configuration The NWAIT + signal indicates whether the data from the memory are + valid or if a wait state must be inserted when + accessing the memory in synchronous mode. This + configuration bit determines if NWAIT is asserted by + the memory one clock cycle before the wait state or + during the wait state: + 11 + 1 + + + WREN + Write enable bit This bit indicates + whether write operations are enabled/disabled in the + bank by the FMC: + 12 + 1 + + + WAITEN + Wait enable bit This bit + enables/disables wait-state insertion via the NWAIT + signal when accessing the memory in synchronous + mode. + 13 + 1 + + + EXTMOD + Extended mode enable. This bit enables + the FMC to program the write timings for asynchronous + accesses inside the FMC_BWTR register, thus resulting + in different timings for read and write operations. + Note: When the extended mode is disabled, the FMC can + operate in Mode1 or Mode2 as follows: ** Mode 1 is + the default mode when the SRAM/PSRAM memory type is + selected (MTYP =0x0 or 0x01) ** Mode 2 is the default + mode when the NOR memory type is selected (MTYP = + 0x10). + 14 + 1 + + + ASYNCWAIT + Wait signal during asynchronous + transfers This bit enables/disables the FMC to use + the wait signal even during an asynchronous + protocol. + 15 + 1 + + + CPSIZE + CRAM Page Size These are used for + Cellular RAM 1.5 which does not allow burst access to + cross the address boundaries between pages. When + these bits are configured, the FMC controller splits + automatically the burst access when the memory page + size is reached (refer to memory datasheet for page + size). Other configuration: reserved. + 16 + 3 + + + CBURSTRW + Write burst enable For PSRAM (CRAM) + operating in Burst mode, the bit enables synchronous + accesses during write operations. The enable bit for + synchronous read accesses is the BURSTEN bit in the + FMC_BCRx register. + 19 + 1 + + + CCLKEN + Continuous Clock Enable This bit enables + the FMC_CLK clock output to external memory devices. + Note: The CCLKEN bit of the FMC_BCR2..4 registers is + dont care. It is only enabled through the FMC_BCR1 + register. Bank 1 must be configured in synchronous + mode to generate the FMC_CLK continuous clock. If + CCLKEN bit is set, the FMC_CLK clock ratio is + specified by CLKDIV value in the FMC_BTR1 register. + CLKDIV in FMC_BWTR1 is dont care. If the synchronous + mode is used and CCLKEN bit is set, the synchronous + memories connected to other banks than Bank 1 are + clocked by the same clock (the CLKDIV value in the + FMC_BTR2..4 and FMC_BWTR2..4 registers for other + banks has no effect.) + 20 + 1 + + + WFDIS + Write FIFO Disable This bit disables the + Write FIFO used by the FMC controller. Note: The + WFDIS bit of the FMC_BCR2..4 registers is dont care. + It is only enabled through the FMC_BCR1 + register. + 21 + 1 + + + BMAP + FMC bank mapping These bits allows + different to remap SDRAM bank2 or swap the FMC + NOR/PSRAM and SDRAM banks.Refer to Table 10 for Note: + The BMAP bits of the FMC_BCR2..4 registers are dont + care. It is only enabled through the FMC_BCR1 + register. + 24 + 2 + + + FMCEN + FMC controller Enable This bit + enables/disables the FMC controller. Note: The FMCEN + bit of the FMC_BCR2..4 registers is dont care. It is + only enabled through the FMC_BCR1 + register. + 31 + 1 + + + + + BTR3 + BTR3 + This register contains the control + information of each memory bank, used for SRAMs, PSRAM + and NOR Flash memories.If the EXTMOD bit is set in the + FMC_BCRx register, then this register is partitioned for + write and read access, that is, 2 registers are + available: one to configure read accesses (this register) + and one to configure write accesses (FMC_BWTRx + registers). + 0x14 + 0x20 + read-write + 0x0FFFFFFF + + + ADDSET + Address setup phase duration These bits + are written by software to define the duration of the + address setup phase (refer to Figure81 to Figure93), + used in SRAMs, ROMs and asynchronous NOR Flash: For + each access mode address setup phase duration, please + refer to the respective figure (refer to Figure81 to + Figure93). Note: In synchronous accesses, this value + is dont care. In Muxed mode or Mode D, the minimum + value for ADDSET is 1. + 0 + 4 + + + ADDHLD + Address-hold phase duration These bits + are written by software to define the duration of the + address hold phase (refer to Figure81 to Figure93), + used in mode D or multiplexed accesses: For each + access mode address-hold phase duration, please refer + to the respective figure (Figure81 to Figure93). + Note: In synchronous accesses, this value is not + used, the address hold phase is always 1 memory clock + period duration. + 4 + 4 + + + DATAST + Data-phase duration These bits are + written by software to define the duration of the + data phase (refer to Figure81 to Figure93), used in + asynchronous accesses: For each memory type and + access mode data-phase duration, please refer to the + respective figure (Figure81 to Figure93). Example: + Mode1, write access, DATAST=1: Data-phase duration= + DATAST+1 = 2 KCK_FMC clock cycles. Note: In + synchronous accesses, this value is dont + care. + 8 + 8 + + + BUSTURN + Bus turnaround phase duration These bits + are written by software to add a delay at the end of + a write-to-read or read-to write transaction. The + programmed bus turnaround delay is inserted between + an asynchronous read (in muxed or mode D) or write + transaction and any other asynchronous /synchronous + read/write from/to a static bank. If a read operation + is performed, the bank can be the same or a different + one, whereas it must be different in case of write + operation to the bank, except in muxed mode or mode + D. In some cases, whatever the programmed BUSTRUN + values, the bus turnaround delay is fixed as follows: + The bus turnaround delay is not inserted between two + consecutive asynchronous write transfers to the same + static memory bank except in muxed mode and mode D. + There is a bus turnaround delay of 1 FMC clock cycle + between: Two consecutive asynchronous read transfers + to the same static memory bank except for modes muxed + and D. An asynchronous read to an asynchronous or + synchronous write to any static bank or dynamic bank + except in modes muxed and D mode. There is a bus + turnaround delay of 2 FMC clock cycle between: Two + consecutive synchronous write operations (in Burst or + Single mode) to the same bank. A synchronous write + (burst or single) access and an asynchronous write or + read transfer to or from static memory bank (the bank + can be the same or a different one in case of a read + operation. Two consecutive synchronous read + operations (in Burst or Single mode) followed by any + synchronous/asynchronous read or write from/to + another static memory bank. There is a bus turnaround + delay of 3 FMC clock cycle between: Two consecutive + synchronous write operations (in Burst or Single + mode) to different static banks. A synchronous write + access (in Burst or Single mode) and a synchronous + read from the same or a different bank. The bus + turnaround delay allows to match the minimum time + between consecutive transactions (tEHEL from NEx high + to NEx low) and the maximum time required by the + memory to free the data bus after a read access + (tEHQZ): (BUSTRUN + 1) KCK_FMC period ≥ + tEHELmin and (BUSTRUN + 2)KCK_FMC period ≥ + tEHQZmax if EXTMOD = 0 (BUSTRUN + 2)KCK_FMC period + ≥ max (tEHELmin, tEHQZmax) if EXTMOD =1. + ... + 16 + 4 + + + CLKDIV + Clock divide ratio (for FMC_CLK signal) + These bits define the period of FMC_CLK clock output + signal, expressed in number of KCK_FMC cycles: In + asynchronous NOR Flash, SRAM or PSRAM accesses, this + value is dont care. Note: Refer to Section20.6.5: + Synchronous transactions for FMC_CLK divider ratio + formula) + 20 + 4 + + + DATLAT + Data latency for synchronous memory For + synchronous access with read write burst mode enabled + these bits define the number of memory clock + cycles + 24 + 4 + + + ACCMOD + Access mode These bits specify the + asynchronous access modes as shown in the timing + diagrams. They are taken into account only when the + EXTMOD bit in the FMC_BCRx register is + 1. + 28 + 2 + + + + + BCR4 + BCR4 + This register contains the control + information of each memory bank, used for SRAMs, PSRAM + and NOR Flash memories. + 0x18 + 0x20 + read-write + 0x000030D2 + + + MBKEN + Memory bank enable bit This bit enables + the memory bank. After reset Bank1 is enabled, all + others are disabled. Accessing a disabled bank causes + an ERROR on AXI bus. + 0 + 1 + + + MUXEN + Address/data multiplexing enable bit + When this bit is set, the address and data values are + multiplexed on the data bus, valid only with NOR and + PSRAM memories: + 1 + 1 + + + MTYP + Memory type These bits define the type + of external memory attached to the corresponding + memory bank: + 2 + 2 + + + MWID + Memory data bus width Defines the + external memory device width, valid for all type of + memories. + 4 + 2 + + + FACCEN + Flash access enable This bit enables NOR + Flash memory access operations. + 6 + 1 + + + BURSTEN + Burst enable bit This bit + enables/disables synchronous accesses during read + operations. It is valid only for synchronous memories + operating in Burst mode: + 8 + 1 + + + WAITPOL + Wait signal polarity bit This bit + defines the polarity of the wait signal from memory + used for either in synchronous or asynchronous + mode: + 9 + 1 + + + WAITCFG + Wait timing configuration The NWAIT + signal indicates whether the data from the memory are + valid or if a wait state must be inserted when + accessing the memory in synchronous mode. This + configuration bit determines if NWAIT is asserted by + the memory one clock cycle before the wait state or + during the wait state: + 11 + 1 + + + WREN + Write enable bit This bit indicates + whether write operations are enabled/disabled in the + bank by the FMC: + 12 + 1 + + + WAITEN + Wait enable bit This bit + enables/disables wait-state insertion via the NWAIT + signal when accessing the memory in synchronous + mode. + 13 + 1 + + + EXTMOD + Extended mode enable. This bit enables + the FMC to program the write timings for asynchronous + accesses inside the FMC_BWTR register, thus resulting + in different timings for read and write operations. + Note: When the extended mode is disabled, the FMC can + operate in Mode1 or Mode2 as follows: ** Mode 1 is + the default mode when the SRAM/PSRAM memory type is + selected (MTYP =0x0 or 0x01) ** Mode 2 is the default + mode when the NOR memory type is selected (MTYP = + 0x10). + 14 + 1 + + + ASYNCWAIT + Wait signal during asynchronous + transfers This bit enables/disables the FMC to use + the wait signal even during an asynchronous + protocol. + 15 + 1 + + + CPSIZE + CRAM Page Size These are used for + Cellular RAM 1.5 which does not allow burst access to + cross the address boundaries between pages. When + these bits are configured, the FMC controller splits + automatically the burst access when the memory page + size is reached (refer to memory datasheet for page + size). Other configuration: reserved. + 16 + 3 + + + CBURSTRW + Write burst enable For PSRAM (CRAM) + operating in Burst mode, the bit enables synchronous + accesses during write operations. The enable bit for + synchronous read accesses is the BURSTEN bit in the + FMC_BCRx register. + 19 + 1 + + + CCLKEN + Continuous Clock Enable This bit enables + the FMC_CLK clock output to external memory devices. + Note: The CCLKEN bit of the FMC_BCR2..4 registers is + dont care. It is only enabled through the FMC_BCR1 + register. Bank 1 must be configured in synchronous + mode to generate the FMC_CLK continuous clock. If + CCLKEN bit is set, the FMC_CLK clock ratio is + specified by CLKDIV value in the FMC_BTR1 register. + CLKDIV in FMC_BWTR1 is dont care. If the synchronous + mode is used and CCLKEN bit is set, the synchronous + memories connected to other banks than Bank 1 are + clocked by the same clock (the CLKDIV value in the + FMC_BTR2..4 and FMC_BWTR2..4 registers for other + banks has no effect.) + 20 + 1 + + + WFDIS + Write FIFO Disable This bit disables the + Write FIFO used by the FMC controller. Note: The + WFDIS bit of the FMC_BCR2..4 registers is dont care. + It is only enabled through the FMC_BCR1 + register. + 21 + 1 + + + BMAP + FMC bank mapping These bits allows + different to remap SDRAM bank2 or swap the FMC + NOR/PSRAM and SDRAM banks.Refer to Table 10 for Note: + The BMAP bits of the FMC_BCR2..4 registers are dont + care. It is only enabled through the FMC_BCR1 + register. + 24 + 2 + + + FMCEN + FMC controller Enable This bit + enables/disables the FMC controller. Note: The FMCEN + bit of the FMC_BCR2..4 registers is dont care. It is + only enabled through the FMC_BCR1 + register. + 31 + 1 + + + + + BTR4 + BTR4 + This register contains the control + information of each memory bank, used for SRAMs, PSRAM + and NOR Flash memories.If the EXTMOD bit is set in the + FMC_BCRx register, then this register is partitioned for + write and read access, that is, 2 registers are + available: one to configure read accesses (this register) + and one to configure write accesses (FMC_BWTRx + registers). + 0x1C + 0x20 + read-write + 0x0FFFFFFF + + + ADDSET + Address setup phase duration These bits + are written by software to define the duration of the + address setup phase (refer to Figure81 to Figure93), + used in SRAMs, ROMs and asynchronous NOR Flash: For + each access mode address setup phase duration, please + refer to the respective figure (refer to Figure81 to + Figure93). Note: In synchronous accesses, this value + is dont care. In Muxed mode or Mode D, the minimum + value for ADDSET is 1. + 0 + 4 + + + ADDHLD + Address-hold phase duration These bits + are written by software to define the duration of the + address hold phase (refer to Figure81 to Figure93), + used in mode D or multiplexed accesses: For each + access mode address-hold phase duration, please refer + to the respective figure (Figure81 to Figure93). + Note: In synchronous accesses, this value is not + used, the address hold phase is always 1 memory clock + period duration. + 4 + 4 + + + DATAST + Data-phase duration These bits are + written by software to define the duration of the + data phase (refer to Figure81 to Figure93), used in + asynchronous accesses: For each memory type and + access mode data-phase duration, please refer to the + respective figure (Figure81 to Figure93). Example: + Mode1, write access, DATAST=1: Data-phase duration= + DATAST+1 = 2 KCK_FMC clock cycles. Note: In + synchronous accesses, this value is dont + care. + 8 + 8 + + + BUSTURN + Bus turnaround phase duration These bits + are written by software to add a delay at the end of + a write-to-read or read-to write transaction. The + programmed bus turnaround delay is inserted between + an asynchronous read (in muxed or mode D) or write + transaction and any other asynchronous /synchronous + read/write from/to a static bank. If a read operation + is performed, the bank can be the same or a different + one, whereas it must be different in case of write + operation to the bank, except in muxed mode or mode + D. In some cases, whatever the programmed BUSTRUN + values, the bus turnaround delay is fixed as follows: + The bus turnaround delay is not inserted between two + consecutive asynchronous write transfers to the same + static memory bank except in muxed mode and mode D. + There is a bus turnaround delay of 1 FMC clock cycle + between: Two consecutive asynchronous read transfers + to the same static memory bank except for modes muxed + and D. An asynchronous read to an asynchronous or + synchronous write to any static bank or dynamic bank + except in modes muxed and D mode. There is a bus + turnaround delay of 2 FMC clock cycle between: Two + consecutive synchronous write operations (in Burst or + Single mode) to the same bank. A synchronous write + (burst or single) access and an asynchronous write or + read transfer to or from static memory bank (the bank + can be the same or a different one in case of a read + operation. Two consecutive synchronous read + operations (in Burst or Single mode) followed by any + synchronous/asynchronous read or write from/to + another static memory bank. There is a bus turnaround + delay of 3 FMC clock cycle between: Two consecutive + synchronous write operations (in Burst or Single + mode) to different static banks. A synchronous write + access (in Burst or Single mode) and a synchronous + read from the same or a different bank. The bus + turnaround delay allows to match the minimum time + between consecutive transactions (tEHEL from NEx high + to NEx low) and the maximum time required by the + memory to free the data bus after a read access + (tEHQZ): (BUSTRUN + 1) KCK_FMC period ≥ + tEHELmin and (BUSTRUN + 2)KCK_FMC period ≥ + tEHQZmax if EXTMOD = 0 (BUSTRUN + 2)KCK_FMC period + ≥ max (tEHELmin, tEHQZmax) if EXTMOD =1. + ... + 16 + 4 + + + CLKDIV + Clock divide ratio (for FMC_CLK signal) + These bits define the period of FMC_CLK clock output + signal, expressed in number of KCK_FMC cycles: In + asynchronous NOR Flash, SRAM or PSRAM accesses, this + value is dont care. Note: Refer to Section20.6.5: + Synchronous transactions for FMC_CLK divider ratio + formula) + 20 + 4 + + + DATLAT + Data latency for synchronous memory For + synchronous access with read write burst mode enabled + these bits define the number of memory clock + cycles + 24 + 4 + + + ACCMOD + Access mode These bits specify the + asynchronous access modes as shown in the timing + diagrams. They are taken into account only when the + EXTMOD bit in the FMC_BCRx register is + 1. + 28 + 2 + + + + + PCR + PCR + NAND Flash control registers + 0x80 + 0x20 + read-write + 0x00000018 + + + PWAITEN + Wait feature enable bit. This bit + enables the Wait feature for the NAND Flash memory + bank: + 1 + 1 + + + PBKEN + NAND Flash memory bank enable bit. This + bit enables the memory bank. Accessing a disabled + memory bank causes an ERROR on AXI bus + 2 + 1 + + + PWID + Data bus width. These bits define the + external memory device width. + 4 + 2 + + + ECCEN + ECC computation logic enable + bit + 6 + 1 + + + TCLR + CLE to RE delay. These bits set time + from CLE low to RE low in number of KCK_FMC clock + cycles. The time is give by the following formula: + t_clr = (TCLR + SET + 2) TKCK_FMC where TKCK_FMC is + the KCK_FMC clock period Note: Set is MEMSET or + ATTSET according to the addressed + space. + 9 + 4 + + + TAR + ALE to RE delay. These bits set time + from ALE low to RE low in number of KCK_FMC clock + cycles. Time is: t_ar = (TAR + SET + 2) TKCK_FMC + where TKCK_FMC is the FMC clock period Note: Set is + MEMSET or ATTSET according to the addressed + space. + 13 + 4 + + + ECCPS + ECC page size. These bits define the + page size for the extended ECC: + 17 + 3 + + + + + SR + SR + This register contains information about the + FIFO status and interrupt. The FMC features a FIFO that + is used when writing to memories to transfer up to 16 + words of data.This is used to quickly write to the FIFO + and free the AXI bus for transactions to peripherals + other than the FMC, while the FMC is draining its FIFO + into the memory. One of these register bits indicates the + status of the FIFO, for ECC purposes.The ECC is + calculated while the data are written to the memory. To + read the correct ECC, the software must consequently wait + until the FIFO is empty. + 0x84 + 0x20 + 0x00000040 + + + IRS + Interrupt rising edge status The flag is + set by hardware and reset by software. Note: If this + bit is written by software to 1 it will be + set. + 0 + 1 + read-write + + + ILS + Interrupt high-level status The flag is + set by hardware and reset by software. + 1 + 1 + read-write + + + IFS + Interrupt falling edge status The flag + is set by hardware and reset by software. Note: If + this bit is written by software to 1 it will be + set. + 2 + 1 + read-write + + + IREN + Interrupt rising edge detection enable + bit + 3 + 1 + read-write + + + ILEN + Interrupt high-level detection enable + bit + 4 + 1 + read-write + + + IFEN + Interrupt falling edge detection enable + bit + 5 + 1 + read-write + + + FEMPT + FIFO empty. Read-only bit that provides + the status of the FIFO + 6 + 1 + read-only + + + + + PMEM + PMEM + The FMC_PMEM read/write register contains + the timing information for NAND Flash memory bank. This + information is used to access either the common memory + space of the NAND Flash for command, address write access + and data read/write access. + 0x88 + 0x20 + read-write + 0xFCFCFCFC + + + MEMSET + Common memory x setup time These bits + define the number of KCK_FMC (+1) clock cycles to set + up the address before the command assertion (NWE, + NOE), for NAND Flash read or write access to common + memory space: + 0 + 8 + + + MEMWAIT + Common memory wait time These bits + define the minimum number of KCK_FMC (+1) clock + cycles to assert the command (NWE, NOE), for NAND + Flash read or write access to common memory space. + The duration of command assertion is extended if the + wait signal (NWAIT) is active (low) at the end of the + programmed value of KCK_FMC: + 8 + 8 + + + MEMHOLD + Common memory hold time These bits + define the number of KCK_FMC clock cycles for write + accesses and KCK_FMC+1 clock cycles for read accesses + during which the address is held (and data for write + accesses) after the command is de-asserted (NWE, + NOE), for NAND Flash read or write access to common + memory space: + 16 + 8 + + + MEMHIZ + Common memory x data bus Hi-Z time These + bits define the number of KCK_FMC clock cycles during + which the data bus is kept Hi-Z after the start of a + NAND Flash write access to common memory space. This + is only valid for write transactions: + 24 + 8 + + + + + PATT + PATT + The FMC_PATT read/write register contains + the timing information for NAND Flash memory bank. It is + used for 8-bit accesses to the attribute memory space of + the NAND Flash for the last address write access if the + timing must differ from that of previous accesses (for + Ready/Busy management, refer to Section20.8.5: NAND Flash + prewait feature). + 0x8C + 0x20 + read-write + 0xFCFCFCFC + + + ATTSET + Attribute memory setup time These bits + define the number of KCK_FMC (+1) clock cycles to set + up address before the command assertion (NWE, NOE), + for NAND Flash read or write access to attribute + memory space: + 0 + 8 + + + ATTWAIT + Attribute memory wait time These bits + define the minimum number of x KCK_FMC (+1) clock + cycles to assert the command (NWE, NOE), for NAND + Flash read or write access to attribute memory space. + The duration for command assertion is extended if the + wait signal (NWAIT) is active (low) at the end of the + programmed value of KCK_FMC: + 8 + 8 + + + ATTHOLD + Attribute memory hold time These bits + define the number of KCK_FMC clock cycles during + which the address is held (and data for write access) + after the command de-assertion (NWE, NOE), for NAND + Flash read or write access to attribute memory + space: + 16 + 8 + + + ATTHIZ + Attribute memory data bus Hi-Z time + These bits define the number of KCK_FMC clock cycles + during which the data bus is kept in Hi-Z after the + start of a NAND Flash write access to attribute + memory space on socket. Only valid for writ + transaction: + 24 + 8 + + + + + ECCR + ECCR + This register contain the current error + correction code value computed by the ECC computation + modules of the FMC NAND controller. When the CPU + reads/writes the data from a NAND Flash memory page at + the correct address (refer to Section20.8.6: Computation + of the error correction code (ECC) in NAND Flash memory), + the data read/written from/to the NAND Flash memory are + processed automatically by the ECC computation module. + When X bytes have been read (according to the ECCPS field + in the FMC_PCR registers), the CPU must read the computed + ECC value from the FMC_ECC registers. It then verifies if + these computed parity data are the same as the parity + value recorded in the spare area, to determine whether a + page is valid, and, to correct it otherwise. The FMC_ECCR + register should be cleared after being read by setting + the ECCEN bit to 0. To compute a new data block, the + ECCEN bit must be set to 1. + 0x94 + 0x20 + read-only + 0x00000000 + + + ECC + ECC result This field contains the value + computed by the ECC computation logic. Table167 + describes the contents of these bit + fields. + 0 + 32 + + + + + BWTR1 + BWTR1 + This register contains the control + information of each memory bank. It is used for SRAMs, + PSRAMs and NOR Flash memories. When the EXTMOD bit is set + in the FMC_BCRx register, then this register is active + for write access. + 0x104 + 0x20 + read-write + 0x0FFFFFFF + + + ADDSET + Address setup phase duration. These bits + are written by software to define the duration of the + address setup phase in KCK_FMC cycles (refer to + Figure81 to Figure93), used in asynchronous accesses: + ... Note: In synchronous accesses, this value is not + used, the address setup phase is always 1 Flash clock + period duration. In muxed mode, the minimum ADDSET + value is 1. + 0 + 4 + + + ADDHLD + Address-hold phase duration. These bits + are written by software to define the duration of the + address hold phase (refer to Figure81 to Figure93), + used in asynchronous multiplexed accesses: ... Note: + In synchronous NOR Flash accesses, this value is not + used, the address hold phase is always 1 Flash clock + period duration. + 4 + 4 + + + DATAST + Data-phase duration. These bits are + written by software to define the duration of the + data phase (refer to Figure81 to Figure93), used in + asynchronous SRAM, PSRAM and NOR Flash memory + accesses: + 8 + 8 + + + BUSTURN + Bus turnaround phase duration These bits + are written by software to add a delay at the end of + a write transaction to match the minimum time between + consecutive transactions (tEHEL from ENx high to ENx + low): (BUSTRUN + 1) KCK_FMC period ≥ + tEHELmin. The programmed bus turnaround delay is + inserted between a an asynchronous write transfer and + any other asynchronous /synchronous read or write + transfer to or from a static bank. If a read + operation is performed, the bank can be the same or a + different one, whereas it must be different in case + of write operation to the bank, except in muxed mode + or mode D. In some cases, whatever the programmed + BUSTRUN values, the bus turnaround delay is fixed as + follows: The bus turnaround delay is not inserted + between two consecutive asynchronous write transfers + to the same static memory bank except for muxed mode + and mode D. There is a bus turnaround delay of 2 FMC + clock cycle between: Two consecutive synchronous + write operations (in Burst or Single mode) to the + same bank A synchronous write transfer ((in Burst or + Single mode) and an asynchronous write or read + transfer to or from static memory bank. There is a + bus turnaround delay of 3 FMC clock cycle between: + Two consecutive synchronous write operations (in + Burst or Single mode) to different static banks. A + synchronous write transfer (in Burst or Single mode) + and a synchronous read from the same or a different + bank. ... + 16 + 4 + + + ACCMOD + Access mode. These bits specify the + asynchronous access modes as shown in the next timing + diagrams.These bits are taken into account only when + the EXTMOD bit in the FMC_BCRx register is + 1. + 28 + 2 + + + + + BWTR2 + BWTR2 + This register contains the control + information of each memory bank. It is used for SRAMs, + PSRAMs and NOR Flash memories. When the EXTMOD bit is set + in the FMC_BCRx register, then this register is active + for write access. + 0x10C + 0x20 + read-write + 0x0FFFFFFF + + + ADDSET + Address setup phase duration. These bits + are written by software to define the duration of the + address setup phase in KCK_FMC cycles (refer to + Figure81 to Figure93), used in asynchronous accesses: + ... Note: In synchronous accesses, this value is not + used, the address setup phase is always 1 Flash clock + period duration. In muxed mode, the minimum ADDSET + value is 1. + 0 + 4 + + + ADDHLD + Address-hold phase duration. These bits + are written by software to define the duration of the + address hold phase (refer to Figure81 to Figure93), + used in asynchronous multiplexed accesses: ... Note: + In synchronous NOR Flash accesses, this value is not + used, the address hold phase is always 1 Flash clock + period duration. + 4 + 4 + + + DATAST + Data-phase duration. These bits are + written by software to define the duration of the + data phase (refer to Figure81 to Figure93), used in + asynchronous SRAM, PSRAM and NOR Flash memory + accesses: + 8 + 8 + + + BUSTURN + Bus turnaround phase duration These bits + are written by software to add a delay at the end of + a write transaction to match the minimum time between + consecutive transactions (tEHEL from ENx high to ENx + low): (BUSTRUN + 1) KCK_FMC period ≥ + tEHELmin. The programmed bus turnaround delay is + inserted between a an asynchronous write transfer and + any other asynchronous /synchronous read or write + transfer to or from a static bank. If a read + operation is performed, the bank can be the same or a + different one, whereas it must be different in case + of write operation to the bank, except in muxed mode + or mode D. In some cases, whatever the programmed + BUSTRUN values, the bus turnaround delay is fixed as + follows: The bus turnaround delay is not inserted + between two consecutive asynchronous write transfers + to the same static memory bank except for muxed mode + and mode D. There is a bus turnaround delay of 2 FMC + clock cycle between: Two consecutive synchronous + write operations (in Burst or Single mode) to the + same bank A synchronous write transfer ((in Burst or + Single mode) and an asynchronous write or read + transfer to or from static memory bank. There is a + bus turnaround delay of 3 FMC clock cycle between: + Two consecutive synchronous write operations (in + Burst or Single mode) to different static banks. A + synchronous write transfer (in Burst or Single mode) + and a synchronous read from the same or a different + bank. ... + 16 + 4 + + + ACCMOD + Access mode. These bits specify the + asynchronous access modes as shown in the next timing + diagrams.These bits are taken into account only when + the EXTMOD bit in the FMC_BCRx register is + 1. + 28 + 2 + + + + + BWTR3 + BWTR3 + This register contains the control + information of each memory bank. It is used for SRAMs, + PSRAMs and NOR Flash memories. When the EXTMOD bit is set + in the FMC_BCRx register, then this register is active + for write access. + 0x114 + 0x20 + read-write + 0x0FFFFFFF + + + ADDSET + Address setup phase duration. These bits + are written by software to define the duration of the + address setup phase in KCK_FMC cycles (refer to + Figure81 to Figure93), used in asynchronous accesses: + ... Note: In synchronous accesses, this value is not + used, the address setup phase is always 1 Flash clock + period duration. In muxed mode, the minimum ADDSET + value is 1. + 0 + 4 + + + ADDHLD + Address-hold phase duration. These bits + are written by software to define the duration of the + address hold phase (refer to Figure81 to Figure93), + used in asynchronous multiplexed accesses: ... Note: + In synchronous NOR Flash accesses, this value is not + used, the address hold phase is always 1 Flash clock + period duration. + 4 + 4 + + + DATAST + Data-phase duration. These bits are + written by software to define the duration of the + data phase (refer to Figure81 to Figure93), used in + asynchronous SRAM, PSRAM and NOR Flash memory + accesses: + 8 + 8 + + + BUSTURN + Bus turnaround phase duration These bits + are written by software to add a delay at the end of + a write transaction to match the minimum time between + consecutive transactions (tEHEL from ENx high to ENx + low): (BUSTRUN + 1) KCK_FMC period ≥ + tEHELmin. The programmed bus turnaround delay is + inserted between a an asynchronous write transfer and + any other asynchronous /synchronous read or write + transfer to or from a static bank. If a read + operation is performed, the bank can be the same or a + different one, whereas it must be different in case + of write operation to the bank, except in muxed mode + or mode D. In some cases, whatever the programmed + BUSTRUN values, the bus turnaround delay is fixed as + follows: The bus turnaround delay is not inserted + between two consecutive asynchronous write transfers + to the same static memory bank except for muxed mode + and mode D. There is a bus turnaround delay of 2 FMC + clock cycle between: Two consecutive synchronous + write operations (in Burst or Single mode) to the + same bank A synchronous write transfer ((in Burst or + Single mode) and an asynchronous write or read + transfer to or from static memory bank. There is a + bus turnaround delay of 3 FMC clock cycle between: + Two consecutive synchronous write operations (in + Burst or Single mode) to different static banks. A + synchronous write transfer (in Burst or Single mode) + and a synchronous read from the same or a different + bank. ... + 16 + 4 + + + ACCMOD + Access mode. These bits specify the + asynchronous access modes as shown in the next timing + diagrams.These bits are taken into account only when + the EXTMOD bit in the FMC_BCRx register is + 1. + 28 + 2 + + + + + BWTR4 + BWTR4 + This register contains the control + information of each memory bank. It is used for SRAMs, + PSRAMs and NOR Flash memories. When the EXTMOD bit is set + in the FMC_BCRx register, then this register is active + for write access. + 0x11C + 0x20 + read-write + 0x0FFFFFFF + + + ADDSET + Address setup phase duration. These bits + are written by software to define the duration of the + address setup phase in KCK_FMC cycles (refer to + Figure81 to Figure93), used in asynchronous accesses: + ... Note: In synchronous accesses, this value is not + used, the address setup phase is always 1 Flash clock + period duration. In muxed mode, the minimum ADDSET + value is 1. + 0 + 4 + + + ADDHLD + Address-hold phase duration. These bits + are written by software to define the duration of the + address hold phase (refer to Figure81 to Figure93), + used in asynchronous multiplexed accesses: ... Note: + In synchronous NOR Flash accesses, this value is not + used, the address hold phase is always 1 Flash clock + period duration. + 4 + 4 + + + DATAST + Data-phase duration. These bits are + written by software to define the duration of the + data phase (refer to Figure81 to Figure93), used in + asynchronous SRAM, PSRAM and NOR Flash memory + accesses: + 8 + 8 + + + BUSTURN + Bus turnaround phase duration These bits + are written by software to add a delay at the end of + a write transaction to match the minimum time between + consecutive transactions (tEHEL from ENx high to ENx + low): (BUSTRUN + 1) KCK_FMC period ≥ + tEHELmin. The programmed bus turnaround delay is + inserted between a an asynchronous write transfer and + any other asynchronous /synchronous read or write + transfer to or from a static bank. If a read + operation is performed, the bank can be the same or a + different one, whereas it must be different in case + of write operation to the bank, except in muxed mode + or mode D. In some cases, whatever the programmed + BUSTRUN values, the bus turnaround delay is fixed as + follows: The bus turnaround delay is not inserted + between two consecutive asynchronous write transfers + to the same static memory bank except for muxed mode + and mode D. There is a bus turnaround delay of 2 FMC + clock cycle between: Two consecutive synchronous + write operations (in Burst or Single mode) to the + same bank A synchronous write transfer ((in Burst or + Single mode) and an asynchronous write or read + transfer to or from static memory bank. There is a + bus turnaround delay of 3 FMC clock cycle between: + Two consecutive synchronous write operations (in + Burst or Single mode) to different static banks. A + synchronous write transfer (in Burst or Single mode) + and a synchronous read from the same or a different + bank. ... + 16 + 4 + + + ACCMOD + Access mode. These bits specify the + asynchronous access modes as shown in the next timing + diagrams.These bits are taken into account only when + the EXTMOD bit in the FMC_BCRx register is + 1. + 28 + 2 + + + + + SDCR1 + SDCR1 + This register contains the control + parameters for each SDRAM memory bank + 0x140 + 0x20 + read-write + 0x000002D0 + + + NC + Number of column address bits These bits + define the number of bits of a column + address. + 0 + 2 + + + NR + Number of row address bits These bits + define the number of bits of a row + address. + 2 + 2 + + + MWID + Memory data bus width. These bits define + the memory device width. + 4 + 2 + + + NB + Number of internal banks This bit sets + the number of internal banks. + 6 + 1 + + + CAS + CAS Latency This bits sets the SDRAM CAS + latency in number of memory clock + cycles + 7 + 2 + + + WP + Write protection This bit enables write + mode access to the SDRAM bank. + 9 + 1 + + + SDCLK + SDRAM clock configuration These bits + define the SDRAM clock period for both SDRAM banks + and allow disabling the clock before changing the + frequency. In this case the SDRAM must be + re-initialized. Note: The corresponding bits in the + FMC_SDCR2 register is read only. + 10 + 2 + + + RBURST + Burst read This bit enables burst read + mode. The SDRAM controller anticipates the next read + commands during the CAS latency and stores data in + the Read FIFO. Note: The corresponding bit in the + FMC_SDCR2 register is read only. + 12 + 1 + + + RPIPE + Read pipe These bits define the delay, + in KCK_FMC clock cycles, for reading data after CAS + latency. Note: The corresponding bits in the + FMC_SDCR2 register is read only. + 13 + 2 + + + + + SDCR2 + SDCR2 + This register contains the control + parameters for each SDRAM memory bank + 0x144 + 0x20 + read-write + 0x000002D0 + + + NC + Number of column address bits These bits + define the number of bits of a column + address. + 0 + 2 + + + NR + Number of row address bits These bits + define the number of bits of a row + address. + 2 + 2 + + + MWID + Memory data bus width. These bits define + the memory device width. + 4 + 2 + + + NB + Number of internal banks This bit sets + the number of internal banks. + 6 + 1 + + + CAS + CAS Latency This bits sets the SDRAM CAS + latency in number of memory clock + cycles + 7 + 2 + + + WP + Write protection This bit enables write + mode access to the SDRAM bank. + 9 + 1 + + + SDCLK + SDRAM clock configuration These bits + define the SDRAM clock period for both SDRAM banks + and allow disabling the clock before changing the + frequency. In this case the SDRAM must be + re-initialized. Note: The corresponding bits in the + FMC_SDCR2 register is read only. + 10 + 2 + + + RBURST + Burst read This bit enables burst read + mode. The SDRAM controller anticipates the next read + commands during the CAS latency and stores data in + the Read FIFO. Note: The corresponding bit in the + FMC_SDCR2 register is read only. + 12 + 1 + + + RPIPE + Read pipe These bits define the delay, + in KCK_FMC clock cycles, for reading data after CAS + latency. Note: The corresponding bits in the + FMC_SDCR2 register is read only. + 13 + 2 + + + + + SDTR1 + SDTR1 + This register contains the timing parameters + of each SDRAM bank + 0x148 + 0x20 + read-write + 0x0FFFFFFF + + + TMRD + Load Mode Register to Active These bits + define the delay between a Load Mode Register command + and an Active or Refresh command in number of memory + clock cycles. .... + 0 + 4 + + + TXSR + Exit Self-refresh delay These bits + define the delay from releasing the Self-refresh + command to issuing the Activate command in number of + memory clock cycles. .... Note: If two SDRAM devices + are used, the FMC_SDTR1 and FMC_SDTR2 must be + programmed with the same TXSR timing corresponding to + the slowest SDRAM device. + 4 + 4 + + + TRAS + Self refresh time These bits define the + minimum Self-refresh period in number of memory clock + cycles. .... + 8 + 4 + + + TRC + Row cycle delay These bits define the + delay between the Refresh command and the Activate + command, as well as the delay between two consecutive + Refresh commands. It is expressed in number of memory + clock cycles. The TRC timing is only configured in + the FMC_SDTR1 register. If two SDRAM devices are + used, the TRC must be programmed with the timings of + the slowest device. .... Note: TRC must match the TRC + and TRFC (Auto Refresh period) timings defined in the + SDRAM device datasheet. Note: The corresponding bits + in the FMC_SDTR2 register are dont + care. + 12 + 4 + + + TWR + Recovery delay These bits define the + delay between a Write and a Precharge command in + number of memory clock cycles. .... Note: TWR must be + programmed to match the write recovery time (tWR) + defined in the SDRAM datasheet, and to guarantee + that: TWR ≥ TRAS - TRCD and TWR + ≥TRC - TRCD - TRP Example: TRAS= 4 cycles, + TRCD= 2 cycles. So, TWR >= 2 cycles. TWR must + be programmed to 0x1. If two SDRAM devices are used, + the FMC_SDTR1 and FMC_SDTR2 must be programmed with + the same TWR timing corresponding to the slowest + SDRAM device. + 16 + 4 + + + TRP + Row precharge delay These bits define + the delay between a Precharge command and another + command in number of memory clock cycles. The TRP + timing is only configured in the FMC_SDTR1 register. + If two SDRAM devices are used, the TRP must be + programmed with the timing of the slowest device. + .... Note: The corresponding bits in the FMC_SDTR2 + register are dont care. + 20 + 4 + + + TRCD + Row to column delay These bits define + the delay between the Activate command and a + Read/Write command in number of memory clock cycles. + .... + 24 + 4 + + + + + SDTR2 + SDTR2 + This register contains the timing parameters + of each SDRAM bank + 0x14C + 0x20 + read-write + 0x0FFFFFFF + + + TMRD + Load Mode Register to Active These bits + define the delay between a Load Mode Register command + and an Active or Refresh command in number of memory + clock cycles. .... + 0 + 4 + + + TXSR + Exit Self-refresh delay These bits + define the delay from releasing the Self-refresh + command to issuing the Activate command in number of + memory clock cycles. .... Note: If two SDRAM devices + are used, the FMC_SDTR1 and FMC_SDTR2 must be + programmed with the same TXSR timing corresponding to + the slowest SDRAM device. + 4 + 4 + + + TRAS + Self refresh time These bits define the + minimum Self-refresh period in number of memory clock + cycles. .... + 8 + 4 + + + TRC + Row cycle delay These bits define the + delay between the Refresh command and the Activate + command, as well as the delay between two consecutive + Refresh commands. It is expressed in number of memory + clock cycles. The TRC timing is only configured in + the FMC_SDTR1 register. If two SDRAM devices are + used, the TRC must be programmed with the timings of + the slowest device. .... Note: TRC must match the TRC + and TRFC (Auto Refresh period) timings defined in the + SDRAM device datasheet. Note: The corresponding bits + in the FMC_SDTR2 register are dont + care. + 12 + 4 + + + TWR + Recovery delay These bits define the + delay between a Write and a Precharge command in + number of memory clock cycles. .... Note: TWR must be + programmed to match the write recovery time (tWR) + defined in the SDRAM datasheet, and to guarantee + that: TWR ≥ TRAS - TRCD and TWR + ≥TRC - TRCD - TRP Example: TRAS= 4 cycles, + TRCD= 2 cycles. So, TWR >= 2 cycles. TWR must + be programmed to 0x1. If two SDRAM devices are used, + the FMC_SDTR1 and FMC_SDTR2 must be programmed with + the same TWR timing corresponding to the slowest + SDRAM device. + 16 + 4 + + + TRP + Row precharge delay These bits define + the delay between a Precharge command and another + command in number of memory clock cycles. The TRP + timing is only configured in the FMC_SDTR1 register. + If two SDRAM devices are used, the TRP must be + programmed with the timing of the slowest device. + .... Note: The corresponding bits in the FMC_SDTR2 + register are dont care. + 20 + 4 + + + TRCD + Row to column delay These bits define + the delay between the Activate command and a + Read/Write command in number of memory clock cycles. + .... + 24 + 4 + + + + + SDCMR + SDCMR + This register contains the command issued + when the SDRAM device is accessed. This register is used + to initialize the SDRAM device, and to activate the + Self-refresh and the Power-down modes. As soon as the + MODE field is written, the command will be issued only to + one or to both SDRAM banks according to CTB1 and CTB2 + command bits. This register is the same for both SDRAM + banks. + 0x150 + 0x20 + read-write + 0x00000000 + + + MODE + Command mode These bits define the + command issued to the SDRAM device. Note: When a + command is issued, at least one Command Target Bank + bit ( CTB1 or CTB2) must be set otherwise the command + will be ignored. Note: If two SDRAM banks are used, + the Auto-refresh and PALL command must be issued + simultaneously to the two devices with CTB1 and CTB2 + bits set otherwise the command will be ignored. Note: + If only one SDRAM bank is used and a command is + issued with its associated CTB bit set, the other CTB + bit of the unused bank must be kept to + 0. + 0 + 3 + + + CTB2 + Command Target Bank 2 This bit indicates + whether the command will be issued to SDRAM Bank 2 or + not. + 3 + 1 + + + CTB1 + Command Target Bank 1 This bit indicates + whether the command will be issued to SDRAM Bank 1 or + not. + 4 + 1 + + + NRFS + Number of Auto-refresh These bits define + the number of consecutive Auto-refresh commands + issued when MODE = 011. .... + 5 + 4 + + + MRD + Mode Register definition This 14-bit + field defines the SDRAM Mode Register content. The + Mode Register is programmed using the Load Mode + Register command. The MRD[13:0] bits are also used to + program the extended mode register for mobile + SDRAM. + 9 + 14 + + + + + SDRTR + SDRTR + This register sets the refresh rate in + number of SDCLK clock cycles between the refresh cycles + by configuring the Refresh Timer Count value.Examplewhere + 64 ms is the SDRAM refresh period.The refresh rate must + be increased by 20 SDRAM clock cycles (as in the above + example) to obtain a safe margin if an internal refresh + request occurs when a read request has been accepted. It + corresponds to a COUNT value of 0000111000000 (448). This + 13-bit field is loaded into a timer which is decremented + using the SDRAM clock. This timer generates a refresh + pulse when zero is reached. The COUNT value must be set + at least to 41 SDRAM clock cycles.As soon as the + FMC_SDRTR register is programmed, the timer starts + counting. If the value programmed in the register is 0, + no refresh is carried out. This register must not be + reprogrammed after the initialization procedure to avoid + modifying the refresh rate.Each time a refresh pulse is + generated, this 13-bit COUNT field is reloaded into the + counter.If a memory access is in progress, the + Auto-refresh request is delayed. However, if the memory + access and Auto-refresh requests are generated + simultaneously, the Auto-refresh takes precedence. If the + memory access occurs during a refresh operation, the + request is buffered to be processed when the refresh is + complete.This register is common to SDRAM bank 1 and bank + 2. + 0x154 + 0x20 + 0x00000000 + + + CRE + Clear Refresh error flag This bit is + used to clear the Refresh Error Flag (RE) in the + Status Register. + 0 + 1 + write-only + + + COUNT + Refresh Timer Count This 13-bit field + defines the refresh rate of the SDRAM device. It is + expressed in number of memory clock cycles. It must + be set at least to 41 SDRAM clock cycles (0x29). + Refresh rate = (COUNT + 1) x SDRAM frequency clock + COUNT = (SDRAM refresh period / Number of rows) - + 20 + 1 + 13 + read-write + + + REIE + RES Interrupt Enable + 14 + 1 + read-write + + + + + SDSR + SDSR + SDRAM Status register + 0x158 + 0x20 + read-only + 0x00000000 + + + RE + Refresh error flag An interrupt is + generated if REIE = 1 and RE = 1 + 0 + 1 + + + MODES1 + Status Mode for Bank 1 These bits define + the Status Mode of SDRAM Bank 1. + 1 + 2 + + + MODES2 + Status Mode for Bank 2 These bits define + the Status Mode of SDRAM Bank 2. + 3 + 2 + + + + + + + CEC + CEC + CEC + 0x40006C00 + + 0x0 + 0x400 + registers + + + CEC + HDMI-CEC global interrupt + 94 + + + + CR + CR + CEC control register + 0x0 + 0x20 + read-write + 0x00000000 + + + CECEN + CEC Enable The CECEN bit is set and + cleared by software. CECEN=1 starts message reception + and enables the TXSOM control. CECEN=0 disables the + CEC peripheral, clears all bits of CEC_CR register + and aborts any on-going reception or + transmission. + 0 + 1 + + + TXSOM + Tx Start Of Message TXSOM is set by + software to command transmission of the first byte of + a CEC message. If the CEC message consists of only + one byte, TXEOM must be set before of TXSOM. + Start-Bit is effectively started on the CEC line + after SFT is counted. If TXSOM is set while a message + reception is ongoing, transmission will start after + the end of reception. TXSOM is cleared by hardware + after the last byte of the message is sent with a + positive acknowledge (TXEND=1), in case of + transmission underrun (TXUDR=1), negative acknowledge + (TXACKE=1), and transmission error (TXERR=1). It is + also cleared by CECEN=0. It is not cleared and + transmission is automatically retried in case of + arbitration lost (ARBLST=1). TXSOM can be also used + as a status bit informing application whether any + transmission request is pending or under execution. + The application can abort a transmission request at + any time by clearing the CECEN bit. Note: TXSOM must + be set when CECEN=1 TXSOM must be set when + transmission data is available into TXDR HEADERs + first four bits containing own peripheral address are + taken from TXDR[7:4], not from CEC_CFGR.OAR which is + used only for reception + 1 + 1 + + + TXEOM + Tx End Of Message The TXEOM bit is set + by software to command transmission of the last byte + of a CEC message. TXEOM is cleared by hardware at the + same time and under the same conditions as for TXSOM. + Note: TXEOM must be set when CECEN=1 TXEOM must be + set before writing transmission data to TXDR If TXEOM + is set when TXSOM=0, transmitted message will consist + of 1 byte (HEADER) only (PING message) + 2 + 1 + + + + + CFGR + CFGR + This register is used to configure the + HDMI-CEC controller. It is mandatory to write CEC_CFGR + only when CECEN=0. + 0x4 + 0x20 + read-write + 0x00000000 + + + SFT + Signal Free Time SFT bits are set by + software. In the SFT=0x0 configuration the number of + nominal data bit periods waited before transmission + is ruled by hardware according to the transmission + history. In all the other configurations the SFT + number is determined by software. * 0x0 ** 2.5 + Data-Bit periods if CEC is the last bus initiator + with unsuccessful transmission (ARBLST=1, TXERR=1, + TXUDR=1 or TXACKE= 1) ** 4 Data-Bit periods if CEC is + the new bus initiator ** 6 Data-Bit periods if CEC is + the last bus initiator with successful transmission + (TXEOM=1) * 0x1: 0.5 nominal data bit periods * 0x2: + 1.5 nominal data bit periods * 0x3: 2.5 nominal data + bit periods * 0x4: 3.5 nominal data bit periods * + 0x5: 4.5 nominal data bit periods * 0x6: 5.5 nominal + data bit periods * 0x7: 6.5 nominal data bit + periods + 0 + 3 + + + RXTOL + Rx-Tolerance The RXTOL bit is set and + cleared by software. ** Start-Bit, +/- 200 s rise, + +/- 200 s fall. ** Data-Bit: +/- 200 s rise. +/- 350 + s fall. ** Start-Bit: +/- 400 s rise, +/- 400 s fall + ** Data-Bit: +/-300 s rise, +/- 500 s + fall + 3 + 1 + + + BRESTP + Rx-Stop on Bit Rising Error The BRESTP + bit is set and cleared by software. + 4 + 1 + + + BREGEN + Generate Error-Bit on Bit Rising Error + The BREGEN bit is set and cleared by software. Note: + If BRDNOGEN=0, an Error-bit is generated upon BRE + detection with BRESTP=1 in broadcast even if + BREGEN=0 + 5 + 1 + + + LBPEGEN + Generate Error-Bit on Long Bit Period + Error The LBPEGEN bit is set and cleared by software. + Note: If BRDNOGEN=0, an Error-bit is generated upon + LBPE detection in broadcast even if + LBPEGEN=0 + 6 + 1 + + + BRDNOGEN + Avoid Error-Bit Generation in Broadcast + The BRDNOGEN bit is set and cleared by + software. + 7 + 1 + + + SFTOPT + SFT Option Bit The SFTOPT bit is set and + cleared by software. + 8 + 1 + + + OAR + Own addresses configuration The OAR bits + are set by software to select which destination + logical addresses has to be considered in receive + mode. Each bit, when set, enables the CEC logical + address identified by the given bit position. At the + end of HEADER reception, the received destination + address is compared with the enabled addresses. In + case of matching address, the incoming message is + acknowledged and received. In case of non-matching + address, the incoming message is received only in + listen mode (LSTN=1), but without acknowledge sent. + Broadcast messages are always received. Example: OAR + = 0b000 0000 0010 0001 means that CEC acknowledges + addresses 0x0 and 0x5. Consequently, each message + directed to one of these addresses is + received. + 16 + 15 + + + LSTN + Listen mode LSTN bit is set and cleared + by software. + 31 + 1 + + + + + TXDR + TXDR + CEC Tx data register + 0x8 + 0x20 + write-only + 0x00000000 + + + TXD + Tx Data register. TXD is a write-only + register containing the data byte to be transmitted. + Note: TXD must be written when + TXSTART=1 + 0 + 8 + + + + + RXDR + RXDR + CEC Rx Data Register + 0xC + 0x20 + read-only + 0x00000000 + + + RXD + Rx Data register. RXD is read-only and + contains the last data byte which has been received + from the CEC line. + 0 + 8 + + + + + ISR + ISR + CEC Interrupt and Status + Register + 0x10 + 0x20 + read-write + 0x00000000 + + + RXBR + Rx-Byte Received The RXBR bit is set by + hardware to inform application that a new byte has + been received from the CEC line and stored into the + RXD buffer. RXBR is cleared by software write at + 1. + 0 + 1 + + + RXEND + End Of Reception RXEND is set by + hardware to inform application that the last byte of + a CEC message is received from the CEC line and + stored into the RXD buffer. RXEND is set at the same + time of RXBR. RXEND is cleared by software write at + 1. + 1 + 1 + + + RXOVR + Rx-Overrun RXOVR is set by hardware if + RXBR is not yet cleared at the time a new byte is + received on the CEC line and stored into RXD. RXOVR + assertion stops message reception so that no + acknowledge is sent. In case of broadcast, a negative + acknowledge is sent. RXOVR is cleared by software + write at 1. + 2 + 1 + + + BRE + Rx-Bit Rising Error BRE is set by + hardware in case a Data-Bit waveform is detected with + Bit Rising Error. BRE is set either at the time the + misplaced rising edge occurs, or at the end of the + maximum BRE tolerance allowed by RXTOL, in case + rising edge is still longing. BRE stops message + reception if BRESTP=1. BRE generates an Error-Bit on + the CEC line if BREGEN=1. BRE is cleared by software + write at 1. + 3 + 1 + + + SBPE + Rx-Short Bit Period Error SBPE is set by + hardware in case a Data-Bit waveform is detected with + Short Bit Period Error. SBPE is set at the time the + anticipated falling edge occurs. SBPE generates an + Error-Bit on the CEC line. SBPE is cleared by + software write at 1. + 4 + 1 + + + LBPE + Rx-Long Bit Period Error LBPE is set by + hardware in case a Data-Bit waveform is detected with + Long Bit Period Error. LBPE is set at the end of the + maximum bit-extension tolerance allowed by RXTOL, in + case falling edge is still longing. LBPE always stops + reception of the CEC message. LBPE generates an + Error-Bit on the CEC line if LBPEGEN=1. In case of + broadcast, Error-Bit is generated even in case of + LBPEGEN=0. LBPE is cleared by software write at + 1. + 5 + 1 + + + RXACKE + Rx-Missing Acknowledge In receive mode, + RXACKE is set by hardware to inform application that + no acknowledge was seen on the CEC line. RXACKE + applies only for broadcast messages and in listen + mode also for not directly addressed messages + (destination address not enabled in OAR). RXACKE + aborts message reception. RXACKE is cleared by + software write at 1. + 6 + 1 + + + ARBLST + Arbitration Lost ARBLST is set by + hardware to inform application that CEC device is + switching to reception due to arbitration lost event + following the TXSOM command. ARBLST can be due either + to a contending CEC device starting earlier or + starting at the same time but with higher HEADER + priority. After ARBLST assertion TXSOM bit keeps + pending for next transmission attempt. ARBLST is + cleared by software write at 1. + 7 + 1 + + + TXBR + Tx-Byte Request TXBR is set by hardware + to inform application that the next transmission data + has to be written to TXDR. TXBR is set when the 4th + bit of currently transmitted byte is sent. + Application must write the next byte to TXDR within 6 + nominal data-bit periods before transmission underrun + error occurs (TXUDR). TXBR is cleared by software + write at 1. + 8 + 1 + + + TXEND + End of Transmission TXEND is set by + hardware to inform application that the last byte of + the CEC message has been successfully transmitted. + TXEND clears the TXSOM and TXEOM control bits. TXEND + is cleared by software write at 1. + 9 + 1 + + + TXUDR + Tx-Buffer Underrun In transmission mode, + TXUDR is set by hardware if application was not in + time to load TXDR before of next byte transmission. + TXUDR aborts message transmission and clears TXSOM + and TXEOM control bits. TXUDR is cleared by software + write at 1 + 10 + 1 + + + TXERR + Tx-Error In transmission mode, TXERR is + set by hardware if the CEC initiator detects low + impedance on the CEC line while it is released. TXERR + aborts message transmission and clears TXSOM and + TXEOM controls. TXERR is cleared by software write at + 1. + 11 + 1 + + + TXACKE + Tx-Missing Acknowledge Error In + transmission mode, TXACKE is set by hardware to + inform application that no acknowledge was received. + In case of broadcast transmission, TXACKE informs + application that a negative acknowledge was received. + TXACKE aborts message transmission and clears TXSOM + and TXEOM controls. TXACKE is cleared by software + write at 1. + 12 + 1 + + + + + IER + IER + CEC interrupt enable register + 0x14 + 0x20 + read-write + 0x00000000 + + + RXBRIE + Rx-Byte Received Interrupt Enable The + RXBRIE bit is set and cleared by + software. + 0 + 1 + + + RXENDIE + End Of Reception Interrupt Enable The + RXENDIE bit is set and cleared by + software. + 1 + 1 + + + RXOVRIE + Rx-Buffer Overrun Interrupt Enable The + RXOVRIE bit is set and cleared by + software. + 2 + 1 + + + BREIE + Bit Rising Error Interrupt Enable The + BREIE bit is set and cleared by + software. + 3 + 1 + + + SBPEIE + Short Bit Period Error Interrupt Enable + The SBPEIE bit is set and cleared by + software. + 4 + 1 + + + LBPEIE + Long Bit Period Error Interrupt Enable + The LBPEIE bit is set and cleared by + software. + 5 + 1 + + + RXACKIE + Rx-Missing Acknowledge Error Interrupt + Enable The RXACKIE bit is set and cleared by + software. + 6 + 1 + + + ARBLSTIE + Arbitration Lost Interrupt Enable The + ARBLSTIE bit is set and cleared by + software. + 7 + 1 + + + TXBRIE + Tx-Byte Request Interrupt Enable The + TXBRIE bit is set and cleared by + software. + 8 + 1 + + + TXENDIE + Tx-End Of Message Interrupt Enable The + TXENDIE bit is set and cleared by + software. + 9 + 1 + + + TXUDRIE + Tx-Underrun Interrupt Enable The TXUDRIE + bit is set and cleared by software. + 10 + 1 + + + TXERRIE + Tx-Error Interrupt Enable The TXERRIE + bit is set and cleared by software. + 11 + 1 + + + TXACKIE + Tx-Missing Acknowledge Error Interrupt + Enable The TXACKEIE bit is set and cleared by + software. + 12 + 1 + + + + + + + HSEM + HSEM + HSEM + 0x58026400 + + 0x0 + 0x400 + registers + + + HSEM0 + HSEM global interrupt 1 + 125 + + + + HSEM_R0 + HSEM_R0 + HSEM register HSEM_R0 HSEM_R31 + 0x0 + 0x20 + read-write + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_R1 + HSEM_R1 + HSEM register HSEM_R0 HSEM_R31 + 0x4 + 0x20 + read-write + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_R2 + HSEM_R2 + HSEM register HSEM_R0 HSEM_R31 + 0x8 + 0x20 + read-write + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_R3 + HSEM_R3 + HSEM register HSEM_R0 HSEM_R31 + 0xC + 0x20 + read-write + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_R4 + HSEM_R4 + HSEM register HSEM_R0 HSEM_R31 + 0x10 + 0x20 + read-write + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_R5 + HSEM_R5 + HSEM register HSEM_R0 HSEM_R31 + 0x14 + 0x20 + read-write + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_R6 + HSEM_R6 + HSEM register HSEM_R0 HSEM_R31 + 0x18 + 0x20 + read-write + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_R7 + HSEM_R7 + HSEM register HSEM_R0 HSEM_R31 + 0x1C + 0x20 + read-write + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_R8 + HSEM_R8 + HSEM register HSEM_R0 HSEM_R31 + 0x20 + 0x20 + read-write + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_R9 + HSEM_R9 + HSEM register HSEM_R0 HSEM_R31 + 0x24 + 0x20 + read-write + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_R10 + HSEM_R10 + HSEM register HSEM_R0 HSEM_R31 + 0x28 + 0x20 + read-write + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_R11 + HSEM_R11 + HSEM register HSEM_R0 HSEM_R31 + 0x2C + 0x20 + read-write + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_R12 + HSEM_R12 + HSEM register HSEM_R0 HSEM_R31 + 0x30 + 0x20 + read-write + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_R13 + HSEM_R13 + HSEM register HSEM_R0 HSEM_R31 + 0x34 + 0x20 + read-write + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_R14 + HSEM_R14 + HSEM register HSEM_R0 HSEM_R31 + 0x38 + 0x20 + read-write + 0x00000000 + + + PROCID + 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LOCK + Lock indication + 31 + 1 + + + + + HSEM_RLR27 + HSEM_RLR27 + HSEM Read lock register + 0xEC + 0x20 + read-only + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RLR28 + HSEM_RLR28 + HSEM Read lock register + 0xF0 + 0x20 + read-only + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RLR29 + HSEM_RLR29 + HSEM Read lock register + 0xF4 + 0x20 + read-only + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RLR30 + HSEM_RLR30 + HSEM Read lock register + 0xF8 + 0x20 + read-only + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RLR31 + HSEM_RLR31 + HSEM Read lock register + 0xFC + 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12 + 1 + + + ISEM13 + Interrupt semaphore n enable + bit + 13 + 1 + + + ISEM14 + Interrupt semaphore n enable + bit + 14 + 1 + + + ISEM15 + Interrupt semaphore n enable + bit + 15 + 1 + + + ISEM16 + Interrupt semaphore n enable + bit + 16 + 1 + + + ISEM17 + Interrupt semaphore n enable + bit + 17 + 1 + + + ISEM18 + Interrupt semaphore n enable + bit + 18 + 1 + + + ISEM19 + Interrupt semaphore n enable + bit + 19 + 1 + + + ISEM20 + Interrupt semaphore n enable + bit + 20 + 1 + + + ISEM21 + Interrupt semaphore n enable + bit + 21 + 1 + + + ISEM22 + Interrupt semaphore n enable + bit + 22 + 1 + + + ISEM23 + Interrupt semaphore n enable + bit + 23 + 1 + + + ISEM24 + Interrupt semaphore n enable + bit + 24 + 1 + + + ISEM25 + Interrupt semaphore n enable + bit + 25 + 1 + + + ISEM26 + Interrupt semaphore n enable + bit + 26 + 1 + + + ISEM27 + Interrupt semaphore n enable + bit + 27 + 1 + + + ISEM28 + Interrupt semaphore n enable + bit + 28 + 1 + + + ISEM29 + Interrupt semaphore n enable + bit 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ISEM21 + Interrupt(N) semaphore n status bit + before enable (mask) + 21 + 1 + + + ISEM22 + Interrupt(N) semaphore n status bit + before enable (mask) + 22 + 1 + + + ISEM23 + Interrupt(N) semaphore n status bit + before enable (mask) + 23 + 1 + + + ISEM24 + Interrupt(N) semaphore n status bit + before enable (mask) + 24 + 1 + + + ISEM25 + Interrupt(N) semaphore n status bit + before enable (mask) + 25 + 1 + + + ISEM26 + Interrupt(N) semaphore n status bit + before enable (mask) + 26 + 1 + + + ISEM27 + Interrupt(N) semaphore n status bit + before enable (mask) + 27 + 1 + + + ISEM28 + Interrupt(N) semaphore n status bit + before enable (mask) + 28 + 1 + + + ISEM29 + Interrupt(N) semaphore n status bit + before enable (mask) + 29 + 1 + + + ISEM30 + Interrupt(N) semaphore n status bit + before enable (mask) + 30 + 1 + + + ISEM31 + Interrupt(N) semaphore n status bit + before enable (mask) + 31 + 1 + + + + + HSEM_MISR + HSEM_MISR + HSEM Masked interrupt status + register + 0x10C + 0x20 + read-only + 0x00000000 + + + ISEM0 + masked interrupt(N) semaphore n status + bit after enable (mask) + 0 + 1 + + + ISEM1 + masked interrupt(N) semaphore n status + bit after enable (mask) + 1 + 1 + + + ISEM2 + masked interrupt(N) semaphore n status + bit after enable (mask) + 2 + 1 + + + ISEM3 + masked interrupt(N) semaphore n status + bit after enable (mask) + 3 + 1 + + + ISEM4 + masked interrupt(N) semaphore n status + bit after enable (mask) + 4 + 1 + + + ISEM5 + masked interrupt(N) semaphore n status + bit after enable (mask) + 5 + 1 + + + ISEM6 + masked interrupt(N) semaphore n status + bit after enable (mask) + 6 + 1 + + + ISEM7 + masked interrupt(N) semaphore n status + bit after enable (mask) + 7 + 1 + + + ISEM8 + masked interrupt(N) semaphore n status + bit after enable (mask) + 8 + 1 + + + ISEM9 + masked interrupt(N) semaphore n status + bit after enable (mask) + 9 + 1 + + + ISEM10 + masked interrupt(N) semaphore n status + bit after enable (mask) + 10 + 1 + + + ISEM11 + masked interrupt(N) semaphore n status + bit after enable (mask) + 11 + 1 + + + ISEM12 + masked interrupt(N) semaphore n status + bit after enable (mask) + 12 + 1 + + + ISEM13 + masked interrupt(N) semaphore n status + bit after enable (mask) + 13 + 1 + + + ISEM14 + masked interrupt(N) semaphore n status + bit after enable (mask) + 14 + 1 + + + ISEM15 + masked interrupt(N) semaphore n status + bit after enable (mask) + 15 + 1 + + + ISEM16 + masked interrupt(N) semaphore n status + bit after enable (mask) + 16 + 1 + + + ISEM17 + masked interrupt(N) semaphore n status + bit after enable (mask) + 17 + 1 + + + ISEM18 + masked interrupt(N) semaphore n status + bit after enable (mask) + 18 + 1 + + + ISEM19 + masked interrupt(N) semaphore n status + bit after enable (mask) + 19 + 1 + + + ISEM20 + masked interrupt(N) semaphore n status + bit after enable (mask) + 20 + 1 + + + ISEM21 + masked interrupt(N) semaphore n status + bit after enable (mask) + 21 + 1 + + + ISEM22 + masked interrupt(N) semaphore n status + bit after enable (mask) + 22 + 1 + + + ISEM23 + masked interrupt(N) semaphore n status + bit after enable (mask) + 23 + 1 + + + ISEM24 + masked interrupt(N) semaphore n status + bit after enable (mask) + 24 + 1 + + + ISEM25 + masked interrupt(N) semaphore n status + bit after enable (mask) + 25 + 1 + + + ISEM26 + masked interrupt(N) semaphore n status + bit after enable (mask) + 26 + 1 + + + ISEM27 + masked interrupt(N) semaphore n status + bit after enable (mask) + 27 + 1 + + + ISEM28 + masked interrupt(N) semaphore n status + bit after enable (mask) + 28 + 1 + + + ISEM29 + masked interrupt(N) semaphore n status + bit after enable (mask) + 29 + 1 + + + ISEM30 + masked interrupt(N) semaphore n status + bit after enable (mask) + 30 + 1 + + + ISEM31 + masked interrupt(N) semaphore n status + bit after enable (mask) + 31 + 1 + + + + + HSEM_CR + HSEM_CR + HSEM Clear register + 0x140 + 0x20 + read-write + 0x00000000 + + + MASTERID + MasterID of semaphores to be + cleared + 8 + 8 + + + KEY + Semaphore clear Key + 16 + 16 + + + + + HSEM_KEYR + HSEM_KEYR + HSEM Interrupt clear register + 0x144 + 0x20 + read-write + 0x00000000 + + + KEY + Semaphore Clear Key + 16 + 16 + + + + + + + I2C1 + I2C + I2C + 0x40005400 + + 0x0 + 0x400 + registers + + + I2C1_EV + I2C1 event interrupt + 31 + + + I2C1_ER + I2C1 error interrupt + 32 + + + + CR1 + CR1 + Access: No wait states, except if a write + access occurs while a write access to this register is + ongoing. In this case, wait states are inserted in the + second write access until the previous one is completed. + The latency of the second write access can be up to 2 x + PCLK1 + 6 x I2CCLK. + 0x0 + 0x20 + read-write + 0x00000000 + + + PE + Peripheral enable Note: When PE=0, the + I2C SCL and SDA lines are released. Internal state + machines and status bits are put back to their reset + value. When cleared, PE must be kept low for at least + 3 APB clock cycles. + 0 + 1 + + + TXIE + TX Interrupt enable + 1 + 1 + + + RXIE + RX Interrupt enable + 2 + 1 + + + ADDRIE + Address match Interrupt enable (slave + only) + 3 + 1 + + + NACKIE + Not acknowledge received Interrupt + enable + 4 + 1 + + + STOPIE + STOP detection Interrupt + enable + 5 + 1 + + + TCIE + Transfer Complete interrupt enable Note: + Any of these events will generate an interrupt: + Transfer Complete (TC) Transfer Complete Reload + (TCR) + 6 + 1 + + + ERRIE + Error interrupts enable Note: Any of + these errors generate an interrupt: Arbitration Loss + (ARLO) Bus Error detection (BERR) Overrun/Underrun + (OVR) Timeout detection (TIMEOUT) PEC error detection + (PECERR) Alert pin event detection + (ALERT) + 7 + 1 + + + DNF + Digital noise filter These bits are used + to configure the digital noise filter on SDA and SCL + input. The digital filter will filter spikes with a + length of up to DNF[3:0] * tI2CCLK ... Note: If the + analog filter is also enabled, the digital filter is + added to the analog filter. This filter can only be + programmed when the I2C is disabled (PE = + 0). + 8 + 4 + + + ANFOFF + Analog noise filter OFF Note: This bit + can only be programmed when the I2C is disabled (PE = + 0). + 12 + 1 + + + TXDMAEN + DMA transmission requests + enable + 14 + 1 + + + RXDMAEN + DMA reception requests + enable + 15 + 1 + + + SBC + Slave byte control This bit is used to + enable hardware byte control in slave + mode. + 16 + 1 + + + NOSTRETCH + Clock stretching disable This bit is + used to disable clock stretching in slave mode. It + must be kept cleared in master mode. Note: This bit + can only be programmed when the I2C is disabled (PE = + 0). + 17 + 1 + + + WUPEN + Wakeup from Stop mode enable Note: If + the Wakeup from Stop mode feature is not supported, + this bit is reserved and forced by hardware to 0. + Please refer to Section25.3: I2C implementation. + Note: WUPEN can be set only when DNF = + 0000 + 18 + 1 + + + GCEN + General call enable + 19 + 1 + + + SMBHEN + SMBus Host address enable Note: If the + SMBus feature is not supported, this bit is reserved + and forced by hardware to 0. Please refer to + Section25.3: I2C implementation. + 20 + 1 + + + SMBDEN + SMBus Device Default address enable + Note: If the SMBus feature is not supported, this bit + is reserved and forced by hardware to 0. Please refer + to Section25.3: I2C implementation. + 21 + 1 + + + ALERTEN + SMBus alert enable Device mode + (SMBHEN=0): Host mode (SMBHEN=1): Note: When + ALERTEN=0, the SMBA pin can be used as a standard + GPIO. If the SMBus feature is not supported, this bit + is reserved and forced by hardware to 0. Please refer + to Section25.3: I2C implementation. + 22 + 1 + + + PECEN + PEC enable Note: If the SMBus feature is + not supported, this bit is reserved and forced by + hardware to 0. Please refer to Section25.3: I2C + implementation. + 23 + 1 + + + + + CR2 + CR2 + Access: No wait states, except if a write + access occurs while a write access to this register is + ongoing. In this case, wait states are inserted in the + second write access until the previous one is completed. + The latency of the second write access can be up to 2 x + PCLK1 + 6 x I2CCLK. + 0x4 + 0x20 + read-write + 0x00000000 + + + SADD0 + Slave address bit 0 (master mode) In + 7-bit addressing mode (ADD10 = 0): This bit is dont + care In 10-bit addressing mode (ADD10 = 1): This bit + should be written with bit 0 of the slave address to + be sent Note: Changing these bits when the START bit + is set is not allowed. + 0 + 1 + + + SADD1 + Slave address bit 7:1 (master mode) In + 7-bit addressing mode (ADD10 = 0): These bits should + be written with the 7-bit slave address to be sent In + 10-bit addressing mode (ADD10 = 1): These bits should + be written with bits 7:1 of the slave address to be + sent. Note: Changing these bits when the START bit is + set is not allowed. + 1 + 1 + + + SADD2 + Slave address bit 7:1 (master mode) In + 7-bit addressing mode (ADD10 = 0): These bits should + be written with the 7-bit slave address to be sent In + 10-bit addressing mode (ADD10 = 1): These bits should + be written with bits 7:1 of the slave address to be + sent. Note: Changing these bits when the START bit is + set is not allowed. + 2 + 1 + + + SADD3 + Slave address bit 7:1 (master mode) In + 7-bit addressing mode (ADD10 = 0): These bits should + be written with the 7-bit slave address to be sent In + 10-bit addressing mode (ADD10 = 1): These bits should + be written with bits 7:1 of the slave address to be + sent. Note: Changing these bits when the START bit is + set is not allowed. + 3 + 1 + + + SADD4 + Slave address bit 7:1 (master mode) In + 7-bit addressing mode (ADD10 = 0): These bits should + be written with the 7-bit slave address to be sent In + 10-bit addressing mode (ADD10 = 1): These bits should + be written with bits 7:1 of the slave address to be + sent. Note: Changing these bits when the START bit is + set is not allowed. + 4 + 1 + + + SADD5 + Slave address bit 7:1 (master mode) In + 7-bit addressing mode (ADD10 = 0): These bits should + be written with the 7-bit slave address to be sent In + 10-bit addressing mode (ADD10 = 1): These bits should + be written with bits 7:1 of the slave address to be + sent. Note: Changing these bits when the START bit is + set is not allowed. + 5 + 1 + + + SADD6 + Slave address bit 7:1 (master mode) In + 7-bit addressing mode (ADD10 = 0): These bits should + be written with the 7-bit slave address to be sent In + 10-bit addressing mode (ADD10 = 1): These bits should + be written with bits 7:1 of the slave address to be + sent. Note: Changing these bits when the START bit is + set is not allowed. + 6 + 1 + + + SADD7 + Slave address bit 7:1 (master mode) In + 7-bit addressing mode (ADD10 = 0): These bits should + be written with the 7-bit slave address to be sent In + 10-bit addressing mode (ADD10 = 1): These bits should + be written with bits 7:1 of the slave address to be + sent. Note: Changing these bits when the START bit is + set is not allowed. + 7 + 1 + + + SADD8 + Slave address bit 9:8 (master mode) In + 7-bit addressing mode (ADD10 = 0): These bits are + dont care In 10-bit addressing mode (ADD10 = 1): + These bits should be written with bits 9:8 of the + slave address to be sent Note: Changing these bits + when the START bit is set is not + allowed. + 8 + 1 + + + SADD9 + Slave address bit 9:8 (master mode) In + 7-bit addressing mode (ADD10 = 0): These bits are + dont care In 10-bit addressing mode (ADD10 = 1): + These bits should be written with bits 9:8 of the + slave address to be sent Note: Changing these bits + when the START bit is set is not + allowed. + 9 + 1 + + + RD_WRN + Transfer direction (master mode) Note: + Changing this bit when the START bit is set is not + allowed. + 10 + 1 + + + ADD10 + 10-bit addressing mode (master mode) + Note: Changing this bit when the START bit is set is + not allowed. + 11 + 1 + + + HEAD10R + 10-bit address header only read + direction (master receiver mode) Note: Changing this + bit when the START bit is set is not + allowed. + 12 + 1 + + + START + Start generation This bit is set by + software, and cleared by hardware after the Start + followed by the address sequence is sent, by an + arbitration loss, by a timeout error detection, or + when PE = 0. It can also be cleared by software by + writing 1 to the ADDRCF bit in the I2C_ICR register. + If the I2C is already in master mode with AUTOEND = + 0, setting this bit generates a Repeated Start + condition when RELOAD=0, after the end of the NBYTES + transfer. Otherwise setting this bit will generate a + START condition once the bus is free. Note: Writing 0 + to this bit has no effect. The START bit can be set + even if the bus is BUSY or I2C is in slave mode. This + bit has no effect when RELOAD is set. + 13 + 1 + + + STOP + Stop generation (master mode) The bit is + set by software, cleared by hardware when a Stop + condition is detected, or when PE = 0. In Master + Mode: Note: Writing 0 to this bit has no + effect. + 14 + 1 + + + NACK + NACK generation (slave mode) The bit is + set by software, cleared by hardware when the NACK is + sent, or when a STOP condition or an Address matched + is received, or when PE=0. Note: Writing 0 to this + bit has no effect. This bit is used in slave mode + only: in master receiver mode, NACK is automatically + generated after last byte preceding STOP or RESTART + condition, whatever the NACK bit value. When an + overrun occurs in slave receiver NOSTRETCH mode, a + NACK is automatically generated whatever the NACK bit + value. When hardware PEC checking is enabled + (PECBYTE=1), the PEC acknowledge value does not + depend on the NACK value. + 15 + 1 + + + NBYTES + Number of bytes The number of bytes to + be transmitted/received is programmed there. This + field is dont care in slave mode with SBC=0. Note: + Changing these bits when the START bit is set is not + allowed. + 16 + 8 + + + RELOAD + NBYTES reload mode This bit is set and + cleared by software. + 24 + 1 + + + AUTOEND + Automatic end mode (master mode) This + bit is set and cleared by software. Note: This bit + has no effect in slave mode or when the RELOAD bit is + set. + 25 + 1 + + + PECBYTE + Packet error checking byte This bit is + set by software, and cleared by hardware when the PEC + is transferred, or when a STOP condition or an + Address matched is received, also when PE=0. Note: + Writing 0 to this bit has no effect. This bit has no + effect when RELOAD is set. This bit has no effect is + slave mode when SBC=0. If the SMBus feature is not + supported, this bit is reserved and forced by + hardware to 0. Please refer to Section25.3: I2C + implementation. + 26 + 1 + + + + + OAR1 + OAR1 + Access: No wait states, except if a write + access occurs while a write access to this register is + ongoing. In this case, wait states are inserted in the + second write access until the previous one is completed. + The latency of the second write access can be up to 2 x + PCLK1 + 6 x I2CCLK. + 0x8 + 0x20 + read-write + 0x00000000 + + + OA1 + Interface address 7-bit addressing mode: + dont care 10-bit addressing mode: bits 9:8 of address + Note: These bits can be written only when OA1EN=0. + OA1[7:1]: Interface address Bits 7:1 of address Note: + These bits can be written only when OA1EN=0. OA1[0]: + Interface address 7-bit addressing mode: dont care + 10-bit addressing mode: bit 0 of address Note: This + bit can be written only when OA1EN=0. + 0 + 10 + + + OA1MODE + Own Address 1 10-bit mode Note: This bit + can be written only when OA1EN=0. + 10 + 1 + + + OA1EN + Own Address 1 enable + 15 + 1 + + + + + OAR2 + OAR2 + Access: No wait states, except if a write + access occurs while a write access to this register is + ongoing. In this case, wait states are inserted in the + second write access until the previous one is completed. + The latency of the second write access can be up to 2 x + PCLK1 + 6 x I2CCLK. + 0xC + 0x20 + read-write + 0x00000000 + + + OA2 + Interface address bits 7:1 of address + Note: These bits can be written only when + OA2EN=0. + 1 + 7 + + + OA2MSK + Own Address 2 masks Note: These bits can + be written only when OA2EN=0. As soon as OA2MSK is + not equal to 0, the reserved I2C addresses (0b0000xxx + and 0b1111xxx) are not acknowledged even if the + comparison matches. + 8 + 3 + + + OA2EN + Own Address 2 enable + 15 + 1 + + + + + TIMINGR + TIMINGR + Access: No wait states + 0x10 + 0x20 + read-write + 0x00000000 + + + SCLL + SCL low period (master mode) This field + is used to generate the SCL low period in master + mode. tSCLL = (SCLL+1) x tPRESC Note: SCLL is also + used to generate tBUF and tSU:STA + timings. + 0 + 8 + + + SCLH + SCL high period (master mode) This field + is used to generate the SCL high period in master + mode. tSCLH = (SCLH+1) x tPRESC Note: SCLH is also + used to generate tSU:STO and tHD:STA + timing. + 8 + 8 + + + SDADEL + Data hold time This field is used to + generate the delay tSDADEL between SCL falling edge + and SDA edge. In master mode and in slave mode with + NOSTRETCH = 0, the SCL line is stretched low during + tSDADEL. tSDADEL= SDADEL x tPRESC Note: SDADEL is + used to generate tHD:DAT timing. + 16 + 4 + + + SCLDEL + Data setup time This field is used to + generate a delay tSCLDEL between SDA edge and SCL + rising edge. In master mode and in slave mode with + NOSTRETCH = 0, the SCL line is stretched low during + tSCLDEL. tSCLDEL = (SCLDEL+1) x tPRESC Note: tSCLDEL + is used to generate tSU:DAT timing. + 20 + 4 + + + PRESC + Timing prescaler This field is used to + prescale I2CCLK in order to generate the clock period + tPRESC used for data setup and hold counters (refer + to I2C timings on page9) and for SCL high and low + level counters (refer to I2C master initialization on + page24). tPRESC = (PRESC+1) x tI2CCLK + 28 + 4 + + + + + TIMEOUTR + TIMEOUTR + Access: No wait states, except if a write + access occurs while a write access to this register is + ongoing. In this case, wait states are inserted in the + second write access until the previous one is completed. + The latency of the second write access can be up to 2 x + PCLK1 + 6 x I2CCLK. + 0x14 + 0x20 + read-write + 0x00000000 + + + TIMEOUTA + Bus Timeout A This field is used to + configure: The SCL low timeout condition tTIMEOUT + when TIDLE=0 tTIMEOUT= (TIMEOUTA+1) x 2048 x tI2CCLK + The bus idle condition (both SCL and SDA high) when + TIDLE=1 tIDLE= (TIMEOUTA+1) x 4 x tI2CCLK Note: These + bits can be written only when + TIMOUTEN=0. + 0 + 12 + + + TIDLE + Idle clock timeout detection Note: This + bit can be written only when + TIMOUTEN=0. + 12 + 1 + + + TIMOUTEN + Clock timeout enable + 15 + 1 + + + TIMEOUTB + Bus timeout B This field is used to + configure the cumulative clock extension timeout: In + master mode, the master cumulative clock low extend + time (tLOW:MEXT) is detected In slave mode, the slave + cumulative clock low extend time (tLOW:SEXT) is + detected tLOW:EXT= (TIMEOUTB+1) x 2048 x tI2CCLK + Note: These bits can be written only when + TEXTEN=0. + 16 + 12 + + + TEXTEN + Extended clock timeout + enable + 31 + 1 + + + + + ISR + ISR + Access: No wait states + 0x18 + 0x20 + 0x00000001 + + + TXE + Transmit data register empty + (transmitters) This bit is set by hardware when the + I2C_TXDR register is empty. It is cleared when the + next data to be sent is written in the I2C_TXDR + register. This bit can be written to 1 by software in + order to flush the transmit data register I2C_TXDR. + Note: This bit is set by hardware when + PE=0. + 0 + 1 + read-write + + + TXIS + Transmit interrupt status (transmitters) + This bit is set by hardware when the I2C_TXDR + register is empty and the data to be transmitted must + be written in the I2C_TXDR register. It is cleared + when the next data to be sent is written in the + I2C_TXDR register. This bit can be written to 1 by + software when NOSTRETCH=1 only, in order to generate + a TXIS event (interrupt if TXIE=1 or DMA request if + TXDMAEN=1). Note: This bit is cleared by hardware + when PE=0. + 1 + 1 + read-write + + + RXNE + Receive data register not empty + (receivers) This bit is set by hardware when the + received data is copied into the I2C_RXDR register, + and is ready to be read. It is cleared when I2C_RXDR + is read. Note: This bit is cleared by hardware when + PE=0. + 2 + 1 + read-only + + + ADDR + Address matched (slave mode) This bit is + set by hardware as soon as the received slave address + matched with one of the enabled slave addresses. It + is cleared by software by setting ADDRCF bit. Note: + This bit is cleared by hardware when + PE=0. + 3 + 1 + read-only + + + NACKF + Not Acknowledge received flag This flag + is set by hardware when a NACK is received after a + byte transmission. It is cleared by software by + setting the NACKCF bit. Note: This bit is cleared by + hardware when PE=0. + 4 + 1 + read-only + + + STOPF + Stop detection flag This flag is set by + hardware when a Stop condition is detected on the bus + and the peripheral is involved in this transfer: + either as a master, provided that the STOP condition + is generated by the peripheral. or as a slave, + provided that the peripheral has been addressed + previously during this transfer. It is cleared by + software by setting the STOPCF bit. Note: This bit is + cleared by hardware when PE=0. + 5 + 1 + read-only + + + TC + Transfer Complete (master mode) This + flag is set by hardware when RELOAD=0, AUTOEND=0 and + NBYTES data have been transferred. It is cleared by + software when START bit or STOP bit is set. Note: + This bit is cleared by hardware when + PE=0. + 6 + 1 + read-only + + + TCR + Transfer Complete Reload This flag is + set by hardware when RELOAD=1 and NBYTES data have + been transferred. It is cleared by software when + NBYTES is written to a non-zero value. Note: This bit + is cleared by hardware when PE=0. This flag is only + for master mode, or for slave mode when the SBC bit + is set. + 7 + 1 + read-only + + + BERR + Bus error This flag is set by hardware + when a misplaced Start or Stop condition is detected + whereas the peripheral is involved in the transfer. + The flag is not set during the address phase in slave + mode. It is cleared by software by setting BERRCF + bit. Note: This bit is cleared by hardware when + PE=0. + 8 + 1 + read-only + + + ARLO + Arbitration lost This flag is set by + hardware in case of arbitration loss. It is cleared + by software by setting the ARLOCF bit. Note: This bit + is cleared by hardware when PE=0. + 9 + 1 + read-only + + + OVR + Overrun/Underrun (slave mode) This flag + is set by hardware in slave mode with NOSTRETCH=1, + when an overrun/underrun error occurs. It is cleared + by software by setting the OVRCF bit. Note: This bit + is cleared by hardware when PE=0. + 10 + 1 + read-only + + + PECERR + PEC Error in reception This flag is set + by hardware when the received PEC does not match with + the PEC register content. A NACK is automatically + sent after the wrong PEC reception. It is cleared by + software by setting the PECCF bit. Note: This bit is + cleared by hardware when PE=0. If the SMBus feature + is not supported, this bit is reserved and forced by + hardware to 0. Please refer to Section25.3: I2C + implementation. + 11 + 1 + read-only + + + TIMEOUT + Timeout or tLOW detection flag This flag + is set by hardware when a timeout or extended clock + timeout occurred. It is cleared by software by + setting the TIMEOUTCF bit. Note: This bit is cleared + by hardware when PE=0. If the SMBus feature is not + supported, this bit is reserved and forced by + hardware to 0. Please refer to Section25.3: I2C + implementation. + 12 + 1 + read-only + + + ALERT + SMBus alert This flag is set by hardware + when SMBHEN=1 (SMBus host configuration), ALERTEN=1 + and a SMBALERT event (falling edge) is detected on + SMBA pin. It is cleared by software by setting the + ALERTCF bit. Note: This bit is cleared by hardware + when PE=0. If the SMBus feature is not supported, + this bit is reserved and forced by hardware to 0. + Please refer to Section25.3: I2C + implementation. + 13 + 1 + read-only + + + BUSY + Bus busy This flag indicates that a + communication is in progress on the bus. It is set by + hardware when a START condition is detected. It is + cleared by hardware when a Stop condition is + detected, or when PE=0. + 15 + 1 + read-only + + + DIR + Transfer direction (Slave mode) This + flag is updated when an address match event occurs + (ADDR=1). + 16 + 1 + read-only + + + ADDCODE + Address match code (Slave mode) These + bits are updated with the received address when an + address match event occurs (ADDR = 1). In the case of + a 10-bit address, ADDCODE provides the 10-bit header + followed by the 2 MSBs of the address. + 17 + 7 + read-only + + + + + ICR + ICR + Access: No wait states + 0x1C + 0x20 + write-only + 0x00000000 + + + ADDRCF + Address matched flag clear Writing 1 to + this bit clears the ADDR flag in the I2C_ISR + register. Writing 1 to this bit also clears the START + bit in the I2C_CR2 register. + 3 + 1 + + + NACKCF + Not Acknowledge flag clear Writing 1 to + this bit clears the ACKF flag in I2C_ISR + register. + 4 + 1 + + + STOPCF + Stop detection flag clear Writing 1 to + this bit clears the STOPF flag in the I2C_ISR + register. + 5 + 1 + + + BERRCF + Bus error flag clear Writing 1 to this + bit clears the BERRF flag in the I2C_ISR + register. + 8 + 1 + + + ARLOCF + Arbitration Lost flag clear Writing 1 to + this bit clears the ARLO flag in the I2C_ISR + register. + 9 + 1 + + + OVRCF + Overrun/Underrun flag clear Writing 1 to + this bit clears the OVR flag in the I2C_ISR + register. + 10 + 1 + + + PECCF + PEC Error flag clear Writing 1 to this + bit clears the PECERR flag in the I2C_ISR register. + Note: If the SMBus feature is not supported, this bit + is reserved and forced by hardware to 0. Please refer + to Section25.3: I2C implementation. + 11 + 1 + + + TIMOUTCF + Timeout detection flag clear Writing 1 + to this bit clears the TIMEOUT flag in the I2C_ISR + register. Note: If the SMBus feature is not + supported, this bit is reserved and forced by + hardware to 0. Please refer to Section25.3: I2C + implementation. + 12 + 1 + + + ALERTCF + Alert flag clear Writing 1 to this bit + clears the ALERT flag in the I2C_ISR register. Note: + If the SMBus feature is not supported, this bit is + reserved and forced by hardware to 0. Please refer to + Section25.3: I2C implementation. + 13 + 1 + + + + + PECR + PECR + Access: No wait states + 0x20 + 0x20 + read-only + 0x00000000 + + + PEC + Packet error checking register This + field contains the internal PEC when PECEN=1. The PEC + is cleared by hardware when PE=0. + 0 + 8 + + + + + RXDR + RXDR + Access: No wait states + 0x24 + 0x20 + read-only + 0x00000000 + + + RXDATA + 8-bit receive data Data byte received + from the I2C bus. + 0 + 8 + + + + + TXDR + TXDR + Access: No wait states + 0x28 + 0x20 + read-write + 0x00000000 + + + TXDATA + 8-bit transmit data Data byte to be + transmitted to the I2C bus. Note: These bits can be + written only when TXE=1. + 0 + 8 + + + + + + + I2C2 + 0x40005800 + + I2C2_EV + I2C2 event interrupt + 33 + + + I2C2_ER + I2C2 error interrupt + 34 + + + + I2C3 + 0x40005C00 + + I2C3_EV + I2C3 event interrupt + 72 + + + I2C3_ER + I2C3 error interrupt + 73 + + + + I2C4 + 0x58001C00 + + I2C4_EV + I2C4 event interrupt + 95 + + + I2C4_ER + I2C4 error interrupt + 96 + + + + GPIOA + GPIO + GPIO + 0x58020000 + + 0x0 + 0x400 + registers + + + + MODER + MODER + GPIO port mode register + 0x0 + 0x20 + read-write + 0xABFFFFFF + + + MODE0 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O mode. + 0 + 2 + + + MODE1 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O mode. + 2 + 2 + + + MODE2 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O mode. + 4 + 2 + + + MODE3 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O mode. + 6 + 2 + + + MODE4 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O mode. + 8 + 2 + + + MODE5 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O mode. + 10 + 2 + + + MODE6 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O mode. + 12 + 2 + + + MODE7 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O mode. + 14 + 2 + + + MODE8 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O mode. + 16 + 2 + + + MODE9 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O mode. + 18 + 2 + + + MODE10 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O mode. + 20 + 2 + + + MODE11 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O mode. + 22 + 2 + + + MODE12 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O mode. + 24 + 2 + + + MODE13 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O mode. + 26 + 2 + + + MODE14 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O mode. + 28 + 2 + + + MODE15 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O mode. + 30 + 2 + + + + + OTYPER + OTYPER + GPIO port output type register + 0x4 + 0x20 + read-write + 0x00000000 + + + OT0 + Port x configuration bits (y = 0..15) + These bits are written by software to configure the + I/O output type. + 0 + 1 + + + OT1 + Port x configuration bits (y = 0..15) + These bits are written by software to configure the + I/O output type. + 1 + 1 + + + OT2 + Port x configuration bits (y = 0..15) + These bits are written by software to configure the + I/O output type. + 2 + 1 + + + OT3 + Port x configuration bits (y = 0..15) + These bits are written by software to configure the + I/O output type. + 3 + 1 + + + OT4 + Port x configuration bits (y = 0..15) + These bits are written by software to configure the + I/O output type. + 4 + 1 + + + OT5 + Port x configuration bits (y = 0..15) + These bits are written by software to configure the + I/O output type. + 5 + 1 + + + OT6 + Port x configuration bits (y = 0..15) + These bits are written by software to configure the + I/O output type. + 6 + 1 + + + OT7 + Port x configuration bits (y = 0..15) + These bits are written by software to configure the + I/O output type. + 7 + 1 + + + OT8 + Port x configuration bits (y = 0..15) + These bits are written by software to configure the + I/O output type. + 8 + 1 + + + OT9 + Port x configuration bits (y = 0..15) + These bits are written by software to configure the + I/O output type. + 9 + 1 + + + OT10 + Port x configuration bits (y = 0..15) + These bits are written by software to configure the + I/O output type. + 10 + 1 + + + OT11 + Port x configuration bits (y = 0..15) + These bits are written by software to configure the + I/O output type. + 11 + 1 + + + OT12 + Port x configuration bits (y = 0..15) + These bits are written by software to configure the + I/O output type. + 12 + 1 + + + OT13 + Port x configuration bits (y = 0..15) + These bits are written by software to configure the + I/O output type. + 13 + 1 + + + OT14 + Port x configuration bits (y = 0..15) + These bits are written by software to configure the + I/O output type. + 14 + 1 + + + OT15 + Port x configuration bits (y = 0..15) + These bits are written by software to configure the + I/O output type. + 15 + 1 + + + + + OSPEEDR + OSPEEDR + GPIO port output speed + register + 0x8 + 0x20 + read-write + 0x0C000000 + + + OSPEED0 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O output speed. Note: Refer to the + device datasheet for the frequency specifications and + the power supply and load conditions for each + speed. + 0 + 2 + + + OSPEED1 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O output speed. Note: Refer to the + device datasheet for the frequency specifications and + the power supply and load conditions for each + speed. + 2 + 2 + + + OSPEED2 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O output speed. Note: Refer to the + device datasheet for the frequency specifications and + the power supply and load conditions for each + speed. + 4 + 2 + + + OSPEED3 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O output speed. Note: Refer to the + device datasheet for the frequency specifications and + the power supply and load conditions for each + speed. + 6 + 2 + + + OSPEED4 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O output speed. Note: Refer to the + device datasheet for the frequency specifications and + the power supply and load conditions for each + speed. + 8 + 2 + + + OSPEED5 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O output speed. Note: Refer to the + device datasheet for the frequency specifications and + the power supply and load conditions for each + speed. + 10 + 2 + + + OSPEED6 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O output speed. Note: Refer to the + device datasheet for the frequency specifications and + the power supply and load conditions for each + speed. + 12 + 2 + + + OSPEED7 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O output speed. Note: Refer to the + device datasheet for the frequency specifications and + the power supply and load conditions for each + speed. + 14 + 2 + + + OSPEED8 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O output speed. Note: Refer to the + device datasheet for the frequency specifications and + the power supply and load conditions for each + speed. + 16 + 2 + + + OSPEED9 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O output speed. Note: Refer to the + device datasheet for the frequency specifications and + the power supply and load conditions for each + speed. + 18 + 2 + + + OSPEED10 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O output speed. Note: Refer to the + device datasheet for the frequency specifications and + the power supply and load conditions for each + speed. + 20 + 2 + + + OSPEED11 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O output speed. Note: Refer to the + device datasheet for the frequency specifications and + the power supply and load conditions for each + speed. + 22 + 2 + + + OSPEED12 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O output speed. Note: Refer to the + device datasheet for the frequency specifications and + the power supply and load conditions for each + speed. + 24 + 2 + + + OSPEED13 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O output speed. Note: Refer to the + device datasheet for the frequency specifications and + the power supply and load conditions for each + speed. + 26 + 2 + + + OSPEED14 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O output speed. Note: Refer to the + device datasheet for the frequency specifications and + the power supply and load conditions for each + speed. + 28 + 2 + + + OSPEED15 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O output speed. Note: Refer to the + device datasheet for the frequency specifications and + the power supply and load conditions for each + speed. + 30 + 2 + + + + + PUPDR + PUPDR + GPIO port pull-up/pull-down + register + 0xC + 0x20 + read-write + 0x12100000 + + + PUPD0 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O pull-up or pull-down + 0 + 2 + + + PUPD1 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O pull-up or pull-down + 2 + 2 + + + PUPD2 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O pull-up or pull-down + 4 + 2 + + + PUPD3 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O pull-up or pull-down + 6 + 2 + + + PUPD4 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O pull-up or pull-down + 8 + 2 + + + PUPD5 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O pull-up or pull-down + 10 + 2 + + + PUPD6 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O pull-up or pull-down + 12 + 2 + + + PUPD7 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O pull-up or pull-down + 14 + 2 + + + PUPD8 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O pull-up or pull-down + 16 + 2 + + + PUPD9 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O pull-up or pull-down + 18 + 2 + + + PUPD10 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O pull-up or pull-down + 20 + 2 + + + PUPD11 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O pull-up or pull-down + 22 + 2 + + + PUPD12 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O pull-up or pull-down + 24 + 2 + + + PUPD13 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O pull-up or pull-down + 26 + 2 + + + PUPD14 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O pull-up or pull-down + 28 + 2 + + + PUPD15 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O pull-up or pull-down + 30 + 2 + + + + + IDR + IDR + GPIO port input data register + 0x10 + 0x20 + read-only + 0x00000000 + + + ID0 + Port input data bit (y = 0..15) These + bits are read-only. They contain the input value of + the corresponding I/O port. + 0 + 1 + + + ID1 + Port input data bit (y = 0..15) These + bits are read-only. They contain the input value of + the corresponding I/O port. + 1 + 1 + + + ID2 + Port input data bit (y = 0..15) These + bits are read-only. They contain the input value of + the corresponding I/O port. + 2 + 1 + + + ID3 + Port input data bit (y = 0..15) These + bits are read-only. They contain the input value of + the corresponding I/O port. + 3 + 1 + + + ID4 + Port input data bit (y = 0..15) These + bits are read-only. They contain the input value of + the corresponding I/O port. + 4 + 1 + + + ID5 + Port input data bit (y = 0..15) These + bits are read-only. They contain the input value of + the corresponding I/O port. + 5 + 1 + + + ID6 + Port input data bit (y = 0..15) These + bits are read-only. They contain the input value of + the corresponding I/O port. + 6 + 1 + + + ID7 + Port input data bit (y = 0..15) These + bits are read-only. They contain the input value of + the corresponding I/O port. + 7 + 1 + + + ID8 + Port input data bit (y = 0..15) These + bits are read-only. They contain the input value of + the corresponding I/O port. + 8 + 1 + + + ID9 + Port input data bit (y = 0..15) These + bits are read-only. They contain the input value of + the corresponding I/O port. + 9 + 1 + + + ID10 + Port input data bit (y = 0..15) These + bits are read-only. They contain the input value of + the corresponding I/O port. + 10 + 1 + + + ID11 + Port input data bit (y = 0..15) These + bits are read-only. They contain the input value of + the corresponding I/O port. + 11 + 1 + + + ID12 + Port input data bit (y = 0..15) These + bits are read-only. They contain the input value of + the corresponding I/O port. + 12 + 1 + + + ID13 + Port input data bit (y = 0..15) These + bits are read-only. They contain the input value of + the corresponding I/O port. + 13 + 1 + + + ID14 + Port input data bit (y = 0..15) These + bits are read-only. They contain the input value of + the corresponding I/O port. + 14 + 1 + + + ID15 + Port input data bit (y = 0..15) These + bits are read-only. They contain the input value of + the corresponding I/O port. + 15 + 1 + + + + + ODR + ODR + GPIO port output data register + 0x14 + 0x20 + read-write + 0x00000000 + + + OD0 + Port output data bit These bits can be + read and written by software. Note: For atomic bit + set/reset, the OD bits can be individually set and/or + reset by writing to the GPIOx_BSRR or GPIOx_BRR + registers (x = A..F). + 0 + 1 + + + OD1 + Port output data bit These bits can be + read and written by software. Note: For atomic bit + set/reset, the OD bits can be individually set and/or + reset by writing to the GPIOx_BSRR or GPIOx_BRR + registers (x = A..F). + 1 + 1 + + + OD2 + Port output data bit These bits can be + read and written by software. Note: For atomic bit + set/reset, the OD bits can be individually set and/or + reset by writing to the GPIOx_BSRR or GPIOx_BRR + registers (x = A..F). + 2 + 1 + + + OD3 + Port output data bit These bits can be + read and written by software. Note: For atomic bit + set/reset, the OD bits can be individually set and/or + reset by writing to the GPIOx_BSRR or GPIOx_BRR + registers (x = A..F). + 3 + 1 + + + OD4 + Port output data bit These bits can be + read and written by software. Note: For atomic bit + set/reset, the OD bits can be individually set and/or + reset by writing to the GPIOx_BSRR or GPIOx_BRR + registers (x = A..F). + 4 + 1 + + + OD5 + Port output data bit These bits can be + read and written by software. Note: For atomic bit + set/reset, the OD bits can be individually set and/or + reset by writing to the GPIOx_BSRR or GPIOx_BRR + registers (x = A..F). + 5 + 1 + + + OD6 + Port output data bit These bits can be + read and written by software. Note: For atomic bit + set/reset, the OD bits can be individually set and/or + reset by writing to the GPIOx_BSRR or GPIOx_BRR + registers (x = A..F). + 6 + 1 + + + OD7 + Port output data bit These bits can be + read and written by software. Note: For atomic bit + set/reset, the OD bits can be individually set and/or + reset by writing to the GPIOx_BSRR or GPIOx_BRR + registers (x = A..F). + 7 + 1 + + + OD8 + Port output data bit These bits can be + read and written by software. Note: For atomic bit + set/reset, the OD bits can be individually set and/or + reset by writing to the GPIOx_BSRR or GPIOx_BRR + registers (x = A..F). + 8 + 1 + + + OD9 + Port output data bit These bits can be + read and written by software. Note: For atomic bit + set/reset, the OD bits can be individually set and/or + reset by writing to the GPIOx_BSRR or GPIOx_BRR + registers (x = A..F). + 9 + 1 + + + OD10 + Port output data bit These bits can be + read and written by software. Note: For atomic bit + set/reset, the OD bits can be individually set and/or + reset by writing to the GPIOx_BSRR or GPIOx_BRR + registers (x = A..F). + 10 + 1 + + + OD11 + Port output data bit These bits can be + read and written by software. Note: For atomic bit + set/reset, the OD bits can be individually set and/or + reset by writing to the GPIOx_BSRR or GPIOx_BRR + registers (x = A..F). + 11 + 1 + + + OD12 + Port output data bit These bits can be + read and written by software. Note: For atomic bit + set/reset, the OD bits can be individually set and/or + reset by writing to the GPIOx_BSRR or GPIOx_BRR + registers (x = A..F). + 12 + 1 + + + OD13 + Port output data bit These bits can be + read and written by software. Note: For atomic bit + set/reset, the OD bits can be individually set and/or + reset by writing to the GPIOx_BSRR or GPIOx_BRR + registers (x = A..F). + 13 + 1 + + + OD14 + Port output data bit These bits can be + read and written by software. Note: For atomic bit + set/reset, the OD bits can be individually set and/or + reset by writing to the GPIOx_BSRR or GPIOx_BRR + registers (x = A..F). + 14 + 1 + + + OD15 + Port output data bit These bits can be + read and written by software. Note: For atomic bit + set/reset, the OD bits can be individually set and/or + reset by writing to the GPIOx_BSRR or GPIOx_BRR + registers (x = A..F). + 15 + 1 + + + + + BSRR + BSRR + GPIO port bit set/reset + register + 0x18 + 0x20 + write-only + 0x00000000 + + + BS0 + Port x set bit y (y= 0..15) These bits + are write-only. A read to these bits returns the + value 0x0000. + 0 + 1 + + + BS1 + Port x set bit y (y= 0..15) These bits + are write-only. A read to these bits returns the + value 0x0000. + 1 + 1 + + + BS2 + Port x set bit y (y= 0..15) These bits + are write-only. A read to these bits returns the + value 0x0000. + 2 + 1 + + + BS3 + Port x set bit y (y= 0..15) These bits + are write-only. A read to these bits returns the + value 0x0000. + 3 + 1 + + + BS4 + Port x set bit y (y= 0..15) These bits + are write-only. A read to these bits returns the + value 0x0000. + 4 + 1 + + + BS5 + Port x set bit y (y= 0..15) These bits + are write-only. A read to these bits returns the + value 0x0000. + 5 + 1 + + + BS6 + Port x set bit y (y= 0..15) These bits + are write-only. A read to these bits returns the + value 0x0000. + 6 + 1 + + + BS7 + Port x set bit y (y= 0..15) These bits + are write-only. A read to these bits returns the + value 0x0000. + 7 + 1 + + + BS8 + Port x set bit y (y= 0..15) These bits + are write-only. A read to these bits returns the + value 0x0000. + 8 + 1 + + + BS9 + Port x set bit y (y= 0..15) These bits + are write-only. A read to these bits returns the + value 0x0000. + 9 + 1 + + + BS10 + Port x set bit y (y= 0..15) These bits + are write-only. A read to these bits returns the + value 0x0000. + 10 + 1 + + + BS11 + Port x set bit y (y= 0..15) These bits + are write-only. A read to these bits returns the + value 0x0000. + 11 + 1 + + + BS12 + Port x set bit y (y= 0..15) These bits + are write-only. A read to these bits returns the + value 0x0000. + 12 + 1 + + + BS13 + Port x set bit y (y= 0..15) These bits + are write-only. A read to these bits returns the + value 0x0000. + 13 + 1 + + + BS14 + Port x set bit y (y= 0..15) These bits + are write-only. A read to these bits returns the + value 0x0000. + 14 + 1 + + + BS15 + Port x set bit y (y= 0..15) These bits + are write-only. A read to these bits returns the + value 0x0000. + 15 + 1 + + + BR0 + Port x reset bit y (y = 0..15) These + bits are write-only. A read to these bits returns the + value 0x0000. Note: If both BSx and BRx are set, BSx + has priority. + 16 + 1 + + + BR1 + Port x reset bit y (y = 0..15) These + bits are write-only. A read to these bits returns the + value 0x0000. Note: If both BSx and BRx are set, BSx + has priority. + 17 + 1 + + + BR2 + Port x reset bit y (y = 0..15) These + bits are write-only. A read to these bits returns the + value 0x0000. Note: If both BSx and BRx are set, BSx + has priority. + 18 + 1 + + + BR3 + Port x reset bit y (y = 0..15) These + bits are write-only. A read to these bits returns the + value 0x0000. Note: If both BSx and BRx are set, BSx + has priority. + 19 + 1 + + + BR4 + Port x reset bit y (y = 0..15) These + bits are write-only. A read to these bits returns the + value 0x0000. Note: If both BSx and BRx are set, BSx + has priority. + 20 + 1 + + + BR5 + Port x reset bit y (y = 0..15) These + bits are write-only. A read to these bits returns the + value 0x0000. Note: If both BSx and BRx are set, BSx + has priority. + 21 + 1 + + + BR6 + Port x reset bit y (y = 0..15) These + bits are write-only. A read to these bits returns the + value 0x0000. Note: If both BSx and BRx are set, BSx + has priority. + 22 + 1 + + + BR7 + Port x reset bit y (y = 0..15) These + bits are write-only. A read to these bits returns the + value 0x0000. Note: If both BSx and BRx are set, BSx + has priority. + 23 + 1 + + + BR8 + Port x reset bit y (y = 0..15) These + bits are write-only. A read to these bits returns the + value 0x0000. Note: If both BSx and BRx are set, BSx + has priority. + 24 + 1 + + + BR9 + Port x reset bit y (y = 0..15) These + bits are write-only. A read to these bits returns the + value 0x0000. Note: If both BSx and BRx are set, BSx + has priority. + 25 + 1 + + + BR10 + Port x reset bit y (y = 0..15) These + bits are write-only. A read to these bits returns the + value 0x0000. Note: If both BSx and BRx are set, BSx + has priority. + 26 + 1 + + + BR11 + Port x reset bit y (y = 0..15) These + bits are write-only. A read to these bits returns the + value 0x0000. Note: If both BSx and BRx are set, BSx + has priority. + 27 + 1 + + + BR12 + Port x reset bit y (y = 0..15) These + bits are write-only. A read to these bits returns the + value 0x0000. Note: If both BSx and BRx are set, BSx + has priority. + 28 + 1 + + + BR13 + Port x reset bit y (y = 0..15) These + bits are write-only. A read to these bits returns the + value 0x0000. Note: If both BSx and BRx are set, BSx + has priority. + 29 + 1 + + + BR14 + Port x reset bit y (y = 0..15) These + bits are write-only. A read to these bits returns the + value 0x0000. Note: If both BSx and BRx are set, BSx + has priority. + 30 + 1 + + + BR15 + Port x reset bit y (y = 0..15) These + bits are write-only. A read to these bits returns the + value 0x0000. Note: If both BSx and BRx are set, BSx + has priority. + 31 + 1 + + + + + LCKR + LCKR + This register is used to lock the + configuration of the port bits when a correct write + sequence is applied to bit 16 (LCKK). The value of bits + [15:0] is used to lock the configuration of the GPIO. + During the write sequence, the value of LCKR[15:0] must + not change. When the LOCK sequence has been applied on a + port bit, the value of this port bit can no longer be + modified until the next MCU reset or peripheral reset.A + specific write sequence is used to write to the + GPIOx_LCKR register. Only word access (32-bit long) is + allowed during this locking sequence.Each lock bit + freezes a specific configuration register (control and + alternate function registers). + 0x1C + 0x20 + read-write + 0x00000000 + + + LCK0 + Port x lock bit y (y= 0..15) These bits + are read/write but can only be written when the LCKK + bit is 0. + 0 + 1 + + + LCK1 + Port x lock bit y (y= 0..15) These bits + are read/write but can only be written when the LCKK + bit is 0. + 1 + 1 + + + LCK2 + Port x lock bit y (y= 0..15) These bits + are read/write but can only be written when the LCKK + bit is 0. + 2 + 1 + + + LCK3 + Port x lock bit y (y= 0..15) These bits + are read/write but can only be written when the LCKK + bit is 0. + 3 + 1 + + + LCK4 + Port x lock bit y (y= 0..15) These bits + are read/write but can only be written when the LCKK + bit is 0. + 4 + 1 + + + LCK5 + Port x lock bit y (y= 0..15) These bits + are read/write but can only be written when the LCKK + bit is 0. + 5 + 1 + + + LCK6 + Port x lock bit y (y= 0..15) These bits + are read/write but can only be written when the LCKK + bit is 0. + 6 + 1 + + + LCK7 + Port x lock bit y (y= 0..15) These bits + are read/write but can only be written when the LCKK + bit is 0. + 7 + 1 + + + LCK8 + Port x lock bit y (y= 0..15) These bits + are read/write but can only be written when the LCKK + bit is 0. + 8 + 1 + + + LCK9 + Port x lock bit y (y= 0..15) These bits + are read/write but can only be written when the LCKK + bit is 0. + 9 + 1 + + + LCK10 + Port x lock bit y (y= 0..15) These bits + are read/write but can only be written when the LCKK + bit is 0. + 10 + 1 + + + LCK11 + Port x lock bit y (y= 0..15) These bits + are read/write but can only be written when the LCKK + bit is 0. + 11 + 1 + + + LCK12 + Port x lock bit y (y= 0..15) These bits + are read/write but can only be written when the LCKK + bit is 0. + 12 + 1 + + + LCK13 + Port x lock bit y (y= 0..15) These bits + are read/write but can only be written when the LCKK + bit is 0. + 13 + 1 + + + LCK14 + Port x lock bit y (y= 0..15) These bits + are read/write but can only be written when the LCKK + bit is 0. + 14 + 1 + + + LCK15 + Port x lock bit y (y= 0..15) These bits + are read/write but can only be written when the LCKK + bit is 0. + 15 + 1 + + + LCKK + Lock key This bit can be read any time. + It can only be modified using the lock key write + sequence. LOCK key write sequence: WR LCKR[16] = 1 + + LCKR[15:0] WR LCKR[16] = 0 + LCKR[15:0] WR LCKR[16] = + 1 + LCKR[15:0] RD LCKR RD LCKR[16] = 1 (this read + operation is optional but it confirms that the lock + is active) Note: During the LOCK key write sequence, + the value of LCK[15:0] must not change. Any error in + the lock sequence aborts the lock. After the first + lock sequence on any bit of the port, any read access + on the LCKK bit will return 1 until the next MCU + reset or peripheral reset. + 16 + 1 + + + + + AFRL + AFRL + GPIO alternate function low + register + 0x20 + 0x20 + read-write + 0x00000000 + + + AFSEL0 + [3:0]: Alternate function selection for + port x pin y (y = 0..7) These bits are written by + software to configure alternate function I/Os AFSELy + selection: + 0 + 4 + + + AFSEL1 + [3:0]: Alternate function selection for + port x pin y (y = 0..7) These bits are written by + software to configure alternate function I/Os AFSELy + selection: + 4 + 4 + + + AFSEL2 + [3:0]: Alternate function selection for + port x pin y (y = 0..7) These bits are written by + software to configure alternate function I/Os AFSELy + selection: + 8 + 4 + + + AFSEL3 + [3:0]: Alternate function selection for + port x pin y (y = 0..7) These bits are written by + software to configure alternate function I/Os AFSELy + selection: + 12 + 4 + + + AFSEL4 + [3:0]: Alternate function selection for + port x pin y (y = 0..7) These bits are written by + software to configure alternate function I/Os AFSELy + selection: + 16 + 4 + + + AFSEL5 + [3:0]: Alternate function selection for + port x pin y (y = 0..7) These bits are written by + software to configure alternate function I/Os AFSELy + selection: + 20 + 4 + + + AFSEL6 + [3:0]: Alternate function selection for + port x pin y (y = 0..7) These bits are written by + software to configure alternate function I/Os AFSELy + selection: + 24 + 4 + + + AFSEL7 + [3:0]: Alternate function selection for + port x pin y (y = 0..7) These bits are written by + software to configure alternate function I/Os AFSELy + selection: + 28 + 4 + + + + + AFRH + AFRH + GPIO alternate function high + register + 0x24 + 0x20 + read-write + 0x00000000 + + + AFSEL8 + [3:0]: Alternate function selection for + port x pin y (y = 8..15) These bits are written by + software to configure alternate function + I/Os + 0 + 4 + + + AFSEL9 + [3:0]: Alternate function selection for + port x pin y (y = 8..15) These bits are written by + software to configure alternate function + I/Os + 4 + 4 + + + AFSEL10 + [3:0]: Alternate function selection for + port x pin y (y = 8..15) These bits are written by + software to configure alternate function + I/Os + 8 + 4 + + + AFSEL11 + [3:0]: Alternate function selection for + port x pin y (y = 8..15) These bits are written by + software to configure alternate function + I/Os + 12 + 4 + + + AFSEL12 + [3:0]: Alternate function selection for + port x pin y (y = 8..15) These bits are written by + software to configure alternate function + I/Os + 16 + 4 + + + AFSEL13 + [3:0]: Alternate function selection for + port x pin y (y = 8..15) These bits are written by + software to configure alternate function + I/Os + 20 + 4 + + + AFSEL14 + [3:0]: Alternate function selection for + port x pin y (y = 8..15) These bits are written by + software to configure alternate function + I/Os + 24 + 4 + + + AFSEL15 + [3:0]: Alternate function selection for + port x pin y (y = 8..15) These bits are written by + software to configure alternate function + I/Os + 28 + 4 + + + + + + + GPIOB + 0x58020400 + + + GPIOC + 0x58020800 + + + GPIOD + 0x58020C00 + + + GPIOE + 0x58021000 + + + GPIOF + 0x58021400 + + + GPIOG + 0x58021800 + + + GPIOH + 0x58021C00 + + + GPIOI + 0x58022000 + + + GPIOJ + 0x58022400 + + + GPIOK + 0x58022800 + + + JPEG + JPEG + JPEG + 0x52003000 + + 0x0 + 0x400 + registers + + + JPEG + JPEG global interrupt + 121 + + + + CONFR0 + CONFR0 + JPEG codec control register + 0x0 + 0x20 + write-only + 0x00000000 + + + START + Start This bit start or stop the + encoding or decoding process. Read this register + always return 0. + 0 + 1 + + + + + CONFR1 + CONFR1 + JPEG codec configuration register + 1 + 0x4 + 0x20 + read-write + 0x00000000 + + + NF + Number of color components This field + defines the number of color components minus + 1. + 0 + 2 + + + DE + Decoding Enable This bit selects the + coding or decoding process + 3 + 1 + + + COLORSPACE + Color Space This filed defines the + number of quantization tables minus 1 to insert in + the output stream. + 4 + 2 + + + NS + Number of components for Scan This field + defines the number of components minus 1 for scan + header marker segment. + 6 + 2 + + + HDR + Header Processing This bit enable the + header processing (generation/parsing). + 8 + 1 + + + YSIZE + Y Size This field defines the number of + lines in source image. + 16 + 16 + + + + + CONFR2 + CONFR2 + JPEG codec configuration register + 2 + 0x8 + 0x20 + read-write + 0x00000000 + + + NMCU + Number of MCU For encoding: this field + defines the number of MCU units minus 1 to encode. + For decoding: this field indicates the number of + complete MCU units minus 1 to be decoded (this field + is updated after the JPEG header parsing). If the + decoded image size has not a X or Y size multiple of + 8 or 16 (depending on the sub-sampling process), the + resulting incomplete or empty MCU must be added to + this value to get the total number of MCU + generated. + 0 + 26 + + + + + CONFR3 + CONFR3 + JPEG codec configuration register + 3 + 0xC + 0x20 + read-write + 0x00000000 + + + XSIZE + X size This field defines the number of + pixels per line. + 16 + 16 + + + + + CONFRN1 + CONFRN1 + JPEG codec configuration register + 4-7 + 0x10 + 0x20 + read-write + 0x00000000 + + + HD + Huffman DC Selects the Huffman table for + encoding the DC coefficients. + 0 + 1 + + + HA + Huffman AC Selects the Huffman table for + encoding the AC coefficients. + 1 + 1 + + + QT + Quantization Table Selects quantization + table associated with a color + component. + 2 + 2 + + + NB + Number of Block Number of data units + minus 1 that belong to a particular color in the + MCU. + 4 + 4 + + + VSF + Vertical Sampling Factor Vertical + sampling factor for component i. + 8 + 4 + + + HSF + Horizontal Sampling Factor Horizontal + sampling factor for component i. + 12 + 4 + + + + + CONFRN2 + CONFRN2 + JPEG codec configuration register + 4-7 + 0x14 + 0x20 + read-write + 0x00000000 + + + HD + Huffman DC Selects the Huffman table for + encoding the DC coefficients. + 0 + 1 + + + HA + Huffman AC Selects the Huffman table for + encoding the AC coefficients. + 1 + 1 + + + QT + Quantization Table Selects quantization + table associated with a color + component. + 2 + 2 + + + NB + Number of Block Number of data units + minus 1 that belong to a particular color in the + MCU. + 4 + 4 + + + VSF + Vertical Sampling Factor Vertical + sampling factor for component i. + 8 + 4 + + + HSF + Horizontal Sampling Factor Horizontal + sampling factor for component i. + 12 + 4 + + + + + CONFRN3 + CONFRN3 + JPEG codec configuration register + 4-7 + 0x18 + 0x20 + read-write + 0x00000000 + + + HD + Huffman DC Selects the Huffman table for + encoding the DC coefficients. + 0 + 1 + + + HA + Huffman AC Selects the Huffman table for + encoding the AC coefficients. + 1 + 1 + + + QT + Quantization Table Selects quantization + table associated with a color + component. + 2 + 2 + + + NB + Number of Block Number of data units + minus 1 that belong to a particular color in the + MCU. + 4 + 4 + + + VSF + Vertical Sampling Factor Vertical + sampling factor for component i. + 8 + 4 + + + HSF + Horizontal Sampling Factor Horizontal + sampling factor for component i. + 12 + 4 + + + + + CONFRN4 + CONFRN4 + JPEG codec configuration register + 4-7 + 0x1C + 0x20 + read-write + 0x00000000 + + + HD + Huffman DC Selects the Huffman table for + encoding the DC coefficients. + 0 + 1 + + + HA + Huffman AC Selects the Huffman table for + encoding the AC coefficients. + 1 + 1 + + + QT + Quantization Table Selects quantization + table associated with a color + component. + 2 + 2 + + + NB + Number of Block Number of data units + minus 1 that belong to a particular color in the + MCU. + 4 + 4 + + + VSF + Vertical Sampling Factor Vertical + sampling factor for component i. + 8 + 4 + + + HSF + Horizontal Sampling Factor Horizontal + sampling factor for component i. + 12 + 4 + + + + + CR + CR + JPEG control register + 0x30 + 0x20 + read-write + 0x00000000 + + + JCEN + JPEG Core Enable Enable the JPEG codec + Core. + 0 + 1 + + + IFTIE + Input FIFO Threshold Interrupt Enable + This bit enables the interrupt generation when input + FIFO reach the threshold. + 1 + 1 + + + IFNFIE + Input FIFO Not Full Interrupt Enable + This bit enables the interrupt generation when input + FIFO is not empty. + 2 + 1 + + + OFTIE + Output FIFO Threshold Interrupt Enable + This bit enables the interrupt generation when output + FIFO reach the threshold. + 3 + 1 + + + OFNEIE + Output FIFO Not Empty Interrupt Enable + This bit enables the interrupt generation when output + FIFO is not empty. + 4 + 1 + + + EOCIE + End of Conversion Interrupt Enable This + bit enables the interrupt generation on the end of + conversion. + 5 + 1 + + + HPDIE + Header Parsing Done Interrupt Enable + This bit enables the interrupt generation on the + Header Parsing Operation. + 6 + 1 + + + IDMAEN + Input DMA Enable Enable the DMA request + generation for the input FIFO. + 11 + 1 + + + ODMAEN + Output DMA Enable Enable the DMA request + generation for the output FIFO. + 12 + 1 + + + IFF + Input FIFO Flush This bit flush the + input FIFO. This bit is always read as + 0. + 13 + 1 + + + OFF + Output FIFO Flush This bit flush the + output FIFO. This bit is always read as + 0. + 14 + 1 + + + + + SR + SR + JPEG status register + 0x34 + 0x20 + read-only + 0x00000006 + + + IFTF + Input FIFO Threshold Flag This bit is + set when the input FIFO is not full and is bellow its + threshold. + 1 + 1 + + + IFNFF + Input FIFO Not Full Flag This bit is set + when the input FIFO is not full (a data can be + written). + 2 + 1 + + + OFTF + Output FIFO Threshold Flag This bit is + set when the output FIFO is not empty and has reach + its threshold. + 3 + 1 + + + OFNEF + Output FIFO Not Empty Flag This bit is + set when the output FIFO is not empty (a data is + available). + 4 + 1 + + + EOCF + End of Conversion Flag This bit is set + when the JPEG codec core has finished the encoding or + the decoding process and than last data has been sent + to the output FIFO. + 5 + 1 + + + HPDF + Header Parsing Done Flag This bit is set + in decode mode when the JPEG codec has finished the + parsing of the headers and the internal registers + have been updated. + 6 + 1 + + + COF + Codec Operation Flag This bit is set + when when a JPEG codec operation is on going + (encoding or decoding). + 7 + 1 + + + + + CFR + CFR + JPEG clear flag register + 0x38 + 0x20 + read-write + 0x00000000 + + + CEOCF + Clear End of Conversion Flag Writing 1 + clears the End of Conversion Flag of the JPEG Status + Register. + 5 + 1 + + + CHPDF + Clear Header Parsing Done Flag Writing 1 + clears the Header Parsing Done Flag of the JPEG + Status Register. + 6 + 1 + + + + + DIR + DIR + JPEG data input register + 0x40 + 0x20 + write-only + 0x00000000 + + + DATAIN + Data Input FIFO Input FIFO data + register. + 0 + 32 + + + + + DOR + DOR + JPEG data output register + 0x44 + 0x20 + read-only + 0x00000000 + + + DATAOUT + Data Output FIFO Output FIFO data + register. + 0 + 32 + + + + + + + MDMA + MDMA + MDMA + 0x52000000 + + 0x0 + 0x1000 + registers + + + MDMA + MDMA + 122 + + + + MDMA_GISR0 + MDMA_GISR0 + MDMA Global Interrupt/Status + Register + 0x0 + 0x20 + read-only + 0x00000000 + + + GIF0 + Channel x global interrupt flag (x=...) + This bit is set and reset by hardware. It is a + logical OR of all the Channel x interrupt flags + (CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in + the interrupt mask register (CTCIEx, BTIEx, BRTIEx, + TEIEx) + 0 + 1 + + + GIF1 + Channel x global interrupt flag (x=...) + This bit is set and reset by hardware. It is a + logical OR of all the Channel x interrupt flags + (CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in + the interrupt mask register (CTCIEx, BTIEx, BRTIEx, + TEIEx) + 1 + 1 + + + GIF2 + Channel x global interrupt flag (x=...) + This bit is set and reset by hardware. It is a + logical OR of all the Channel x interrupt flags + (CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in + the interrupt mask register (CTCIEx, BTIEx, BRTIEx, + TEIEx) + 2 + 1 + + + GIF3 + Channel x global interrupt flag (x=...) + This bit is set and reset by hardware. It is a + logical OR of all the Channel x interrupt flags + (CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in + the interrupt mask register (CTCIEx, BTIEx, BRTIEx, + TEIEx) + 3 + 1 + + + GIF4 + Channel x global interrupt flag (x=...) + This bit is set and reset by hardware. It is a + logical OR of all the Channel x interrupt flags + (CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in + the interrupt mask register (CTCIEx, BTIEx, BRTIEx, + TEIEx) + 4 + 1 + + + GIF5 + Channel x global interrupt flag (x=...) + This bit is set and reset by hardware. It is a + logical OR of all the Channel x interrupt flags + (CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in + the interrupt mask register (CTCIEx, BTIEx, BRTIEx, + TEIEx) + 5 + 1 + + + GIF6 + Channel x global interrupt flag (x=...) + This bit is set and reset by hardware. It is a + logical OR of all the Channel x interrupt flags + (CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in + the interrupt mask register (CTCIEx, BTIEx, BRTIEx, + TEIEx) + 6 + 1 + + + GIF7 + Channel x global interrupt flag (x=...) + This bit is set and reset by hardware. It is a + logical OR of all the Channel x interrupt flags + (CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in + the interrupt mask register (CTCIEx, BTIEx, BRTIEx, + TEIEx) + 7 + 1 + + + GIF8 + Channel x global interrupt flag (x=...) + This bit is set and reset by hardware. It is a + logical OR of all the Channel x interrupt flags + (CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in + the interrupt mask register (CTCIEx, BTIEx, BRTIEx, + TEIEx) + 8 + 1 + + + GIF9 + Channel x global interrupt flag (x=...) + This bit is set and reset by hardware. It is a + logical OR of all the Channel x interrupt flags + (CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in + the interrupt mask register (CTCIEx, BTIEx, BRTIEx, + TEIEx) + 9 + 1 + + + GIF10 + Channel x global interrupt flag (x=...) + This bit is set and reset by hardware. It is a + logical OR of all the Channel x interrupt flags + (CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in + the interrupt mask register (CTCIEx, BTIEx, BRTIEx, + TEIEx) + 10 + 1 + + + GIF11 + Channel x global interrupt flag (x=...) + This bit is set and reset by hardware. It is a + logical OR of all the Channel x interrupt flags + (CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in + the interrupt mask register (CTCIEx, BTIEx, BRTIEx, + TEIEx) + 11 + 1 + + + GIF12 + Channel x global interrupt flag (x=...) + This bit is set and reset by hardware. It is a + logical OR of all the Channel x interrupt flags + (CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in + the interrupt mask register (CTCIEx, BTIEx, BRTIEx, + TEIEx) + 12 + 1 + + + GIF13 + Channel x global interrupt flag (x=...) + This bit is set and reset by hardware. It is a + logical OR of all the Channel x interrupt flags + (CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in + the interrupt mask register (CTCIEx, BTIEx, BRTIEx, + TEIEx) + 13 + 1 + + + GIF14 + Channel x global interrupt flag (x=...) + This bit is set and reset by hardware. It is a + logical OR of all the Channel x interrupt flags + (CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in + the interrupt mask register (CTCIEx, BTIEx, BRTIEx, + TEIEx) + 14 + 1 + + + GIF15 + Channel x global interrupt flag (x=...) + This bit is set and reset by hardware. It is a + logical OR of all the Channel x interrupt flags + (CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in + the interrupt mask register (CTCIEx, BTIEx, BRTIEx, + TEIEx) + 15 + 1 + + + + + MDMA_C0ISR + MDMA_C0ISR + MDMA channel x interrupt/status + register + 0x40 + 0x20 + read-only + 0x00000000 + + + TEIF0 + Channel x transfer error interrupt flag + This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCRy register. + 0 + 1 + + + CTCIF0 + Channel x Channel Transfer Complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. CTC is set when the + last block was transferred and the channel has been + automatically disabled. CTC is also set when the + channel is suspended, as a result of writing EN bit + to 0. + 1 + 1 + + + BRTIF0 + Channel x block repeat transfer complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. + 2 + 1 + + + BTIF0 + Channel x block transfer complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. + 3 + 1 + + + TCIF0 + channel x buffer transfer + complete + 4 + 1 + + + CRQA0 + channel x request active + flag + 16 + 1 + + + + + MDMA_C0IFCR + MDMA_C0IFCR + MDMA channel x interrupt flag clear + register + 0x44 + 0x20 + write-only + 0x00000000 + + + CTEIF0 + Channel x clear transfer error interrupt + flag Writing a 1 into this bit clears TEIFx in the + MDMA_ISRy register + 0 + 1 + + + CCTCIF0 + Clear Channel transfer complete + interrupt flag for channel x Writing a 1 into this + bit clears CTCIFx in the MDMA_ISRy + register + 1 + 1 + + + CBRTIF0 + Channel x clear block repeat transfer + complete interrupt flag Writing a 1 into this bit + clears BRTIFx in the MDMA_ISRy register + 2 + 1 + + + CBTIF0 + Channel x Clear block transfer complete + interrupt flag Writing a 1 into this bit clears BTIFx + in the MDMA_ISRy register + 3 + 1 + + + CLTCIF0 + CLear buffer Transfer Complete Interrupt + Flag for channel x Writing a 1 into this bit clears + TCIFx in the MDMA_ISRy register + 4 + 1 + + + + + MDMA_C0ESR + MDMA_C0ESR + MDMA Channel x error status + register + 0x48 + 0x20 + read-only + 0x00000000 + + + TEA + Transfer Error Address These bits are + set and cleared by HW, in case of an MDMA data + transfer error. It is used in conjunction with TED. + This field indicates the 7 LSBits of the address + which generated a transfer/access error. It may be + used by SW to retrieve the failing address, by adding + this value (truncated to the buffer transfer length + size) to the current SAR/DAR value. Note: The SAR/DAR + current value doesnt reflect this last address due to + the FIFO management system. The SAR/DAR are only + updated at the end of a (buffer) transfer (of TLEN+1 + bytes). Note: It is not set in case of a link data + error. + 0 + 7 + + + TED + Transfer Error Direction These bit is + set and cleared by HW, in case of an MDMA data + transfer error. + 7 + 1 + + + TELD + Transfer Error Link Data These bit is + set by HW, in case of a transfer error while reading + the block link data structure. It is cleared by + software writing 1 to the CTEIFx bit in the DMA_IFCRy + register. + 8 + 1 + + + TEMD + Transfer Error Mask Data These bit is + set by HW, in case of a transfer error while writing + the Mask Data. It is cleared by software writing 1 to + the CTEIFx bit in the DMA_IFCRy + register. + 9 + 1 + + + ASE + Address/Size Error These bit is set by + HW, when the programmed address is not aligned with + the data size. TED will indicate whether the problem + is on the source or destination. It is cleared by + software writing 1 to the CTEIFx bit in the DMA_IFCRy + register. + 10 + 1 + + + BSE + Block Size Error These bit is set by HW, + when the block size is not an integer multiple of the + data size either for source or destination. TED will + indicate whether the problem is on the source or + destination. It is cleared by software writing 1 to + the CTEIFx bit in the DMA_IFCRy + register. + 11 + 1 + + + + + MDMA_C0CR + MDMA_C0CR + This register is used to control the + concerned channel. + 0x4C + 0x20 + 0x00000000 + + + EN + channel enable + 0 + 1 + read-write + + + TEIE + Transfer error interrupt enable This bit + is set and cleared by software. + 1 + 1 + read-write + + + CTCIE + Channel Transfer Complete interrupt + enable This bit is set and cleared by + software. + 2 + 1 + read-write + + + BRTIE + Block Repeat transfer interrupt enable + This bit is set and cleared by + software. + 3 + 1 + read-write + + + BTIE + Block Transfer interrupt enable This bit + is set and cleared by software. + 4 + 1 + read-write + + + TCIE + buffer Transfer Complete interrupt + enable This bit is set and cleared by + software. + 5 + 1 + read-write + + + PL + Priority level These bits are set and + cleared by software. These bits are protected and can + be written only if EN is 0. + 6 + 2 + read-write + + + BEX + byte Endianness exchange + 12 + 1 + read-write + + + HEX + Half word Endianes + exchange + 13 + 1 + read-write + + + WEX + Word Endianness exchange + 14 + 1 + read-write + + + SWRQ + SW ReQuest Writing a 1 into this bit + sets the CRQAx in MDMA_ISRy register, activating the + request on Channel x Note: Either the whole CxCR + register or the 8-bit/16-bit register @ Address + offset: 0x4E + 0x40 chn may be used for SWRQ + activation. In case of a SW request, acknowledge is + not generated (neither HW signal, nor CxMAR write + access). + 16 + 1 + write-only + + + + + MDMA_C0TCR + MDMA_C0TCR + This register is used to configure the + concerned channel. + 0x50 + 0x20 + read-write + 0x00000000 + + + SINC + Source increment mode These bits are set + and cleared by software. These bits are protected and + can be written only if EN is 0 Note: When source is + AHB (SBUS=1), SINC = 00 is forbidden. In Linked List + Mode, at the end of a block (single or last block in + repeated block transfer mode), this register will be + loaded from memory (from address given by current + LAR[31:0] + 0x00). + 0 + 2 + + + DINC + Destination increment mode These bits + are set and cleared by software. These bits are + protected and can be written only if EN is 0 Note: + When destination is AHB (DBUS=1), DINC = 00 is + forbidden. + 2 + 2 + + + SSIZE + Source data size These bits are set and + cleared by software. These bits are protected and can + be written only if EN is 0 Note: If a value of 11 is + programmed for the TCM access/AHB port, a transfer + error will occur (TEIF bit set) If SINCOS < + SSIZE and SINC ≠ 00, the result will be + unpredictable. Note: SSIZE = 11 (double-word) is + forbidden when source is TCM/AHB bus + (SBUS=1). + 4 + 2 + + + DSIZE + Destination data size These bits are set + and cleared by software. These bits are protected and + can be written only if EN is 0. Note: If a value of + 11 is programmed for the TCM access/AHB port, a + transfer error will occur (TEIF bit set) If DINCOS + < DSIZE and DINC ≠ 00, the result + will be unpredictable. Note: DSIZE = 11 (double-word) + is forbidden when destination is TCM/AHB bus + (DBUS=1). + 6 + 2 + + + SINCOS + source increment offset + size + 8 + 2 + + + DINCOS + Destination increment + offset + 10 + 2 + + + SBURST + source burst transfer + configuration + 12 + 3 + + + DBURST + Destination burst transfer + configuration + 15 + 3 + + + TLEN + buffer transfer lengh + 18 + 7 + + + PKE + PacK Enable These bit is set and cleared + by software. If the Source Size is smaller than the + destination, it will be padded according to the PAM + value. If the Source data size is larger than the + destination one, it will be truncated. The alignment + will be done according to the PAM[0] value. This bit + is protected and can be written only if EN is + 0 + 25 + 1 + + + PAM + Padding/Alignement Mode These bits are + set and cleared by software. Case 1: Source data size + smaller than destination data size - 3 options are + valid. Case 2: Source data size larger than + destination data size. The remainder part is + discarded. When PKE = 1 or DSIZE=SSIZE, these bits + are ignored. These bits are protected and can be + written only if EN is 0 + 26 + 2 + + + TRGM + Trigger Mode These bits are set and + cleared by software. Note: If TRGM is 11 for the + current block, all the values loaded at the end of + the current block through the linked list mechanism + must keep the same value (TRGM=11) and the same SWRM + value, otherwise the result is undefined. These bits + are protected and can be written only if EN is + 0. + 28 + 2 + + + SWRM + SW Request Mode This bit is set and + cleared by software. If a HW or SW request is + currently active, the bit change will be delayed + until the current transfer is completed. If the CxMAR + contains a valid address, the CxMDR value will also + be written @ CxMAR address. This bit is protected and + can be written only if EN is 0. + 30 + 1 + + + BWM + Bufferable Write Mode This bit is set + and cleared by software. This bit is protected and + can be written only if EN is 0. Note: All MDMA + destination accesses are non-cacheable. + 31 + 1 + + + + + MDMA_C0BNDTR + MDMA_C0BNDTR + MDMA Channel x block number of data + register + 0x54 + 0x20 + read-write + 0x00000000 + + + BNDT + block number of data to + transfer + 0 + 17 + + + BRSUM + Block Repeat Source address Update Mode + These bits are protected and can be written only if + EN is 0. + 18 + 1 + + + BRDUM + Block Repeat Destination address Update + Mode These bits are protected and can be written only + if EN is 0. + 19 + 1 + + + BRC + Block Repeat Count This field contains + the number of repetitions of the current block (0 to + 4095). When the channel is enabled, this register is + read-only, indicating the remaining number of blocks, + excluding the current one. This register decrements + after each complete block transfer. Once the last + block transfer has completed, this register can + either stay at zero or be reloaded automatically from + memory (in Linked List mode - i.e. Link Address + valid). These bits are protected and can be written + only if EN is 0. + 20 + 12 + + + + + MDMA_C0SAR + MDMA_C0SAR + MDMA channel x source address + register + 0x58 + 0x20 + read-write + 0x00000000 + + + SAR + source adr base + 0 + 32 + + + + + MDMA_C0DAR + MDMA_C0DAR + MDMA channel x destination address + register + 0x5C + 0x20 + read-write + 0x00000000 + + + DAR + Destination adr base + 0 + 32 + + + + + MDMA_C0BRUR + MDMA_C0BRUR + MDMA channel x Block Repeat address Update + register + 0x60 + 0x20 + read-write + 0x00000000 + + + SUV + source adresse update + value + 0 + 16 + + + DUV + destination address update + 16 + 16 + + + + + MDMA_C0LAR + MDMA_C0LAR + MDMA channel x Link Address + register + 0x64 + 0x20 + read-write + 0x00000000 + + + LAR + Link address register + 0 + 32 + + + + + MDMA_C0TBR + MDMA_C0TBR + MDMA channel x Trigger and Bus selection + Register + 0x68 + 0x20 + read-write + 0x00000000 + + + TSEL + Trigger selection + 0 + 6 + + + SBUS + Source BUS select This bit is protected + and can be written only if EN is 0. + 16 + 1 + + + DBUS + Destination BUS slect This bit is + protected and can be written only if EN is + 0. + 17 + 1 + + + + + MDMA_C0MAR + MDMA_C0MAR + MDMA channel x Mask address + register + 0x70 + 0x20 + read-write + 0x00000000 + + + MAR + Mask address + 0 + 32 + + + + + MDMA_C0MDR + MDMA_C0MDR + MDMA channel x Mask Data + register + 0x74 + 0x20 + read-write + 0x00000000 + + + MDR + Mask data + 0 + 32 + + + + + MDMA_C1ISR + MDMA_C1ISR + MDMA channel x interrupt/status + register + 0x80 + 0x20 + read-only + 0x00000000 + + + TEIF1 + Channel x transfer error interrupt flag + This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCRy register. + 0 + 1 + + + CTCIF1 + Channel x Channel Transfer Complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. CTC is set when the + last block was transferred and the channel has been + automatically disabled. CTC is also set when the + channel is suspended, as a result of writing EN bit + to 0. + 1 + 1 + + + BRTIF1 + Channel x block repeat transfer complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. + 2 + 1 + + + BTIF1 + Channel x block transfer complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. + 3 + 1 + + + TCIF1 + channel x buffer transfer + complete + 4 + 1 + + + CRQA1 + channel x request active + flag + 16 + 1 + + + + + MDMA_C1IFCR + MDMA_C1IFCR + MDMA channel x interrupt flag clear + register + 0x84 + 0x20 + write-only + 0x00000000 + + + CTEIF1 + Channel x clear transfer error interrupt + flag Writing a 1 into this bit clears TEIFx in the + MDMA_ISRy register + 0 + 1 + + + CCTCIF1 + Clear Channel transfer complete + interrupt flag for channel x Writing a 1 into this + bit clears CTCIFx in the MDMA_ISRy + register + 1 + 1 + + + CBRTIF1 + Channel x clear block repeat transfer + complete interrupt flag Writing a 1 into this bit + clears BRTIFx in the MDMA_ISRy register + 2 + 1 + + + CBTIF1 + Channel x Clear block transfer complete + interrupt flag Writing a 1 into this bit clears BTIFx + in the MDMA_ISRy register + 3 + 1 + + + CLTCIF1 + CLear buffer Transfer Complete Interrupt + Flag for channel x Writing a 1 into this bit clears + TCIFx in the MDMA_ISRy register + 4 + 1 + + + + + MDMA_C1ESR + MDMA_C1ESR + MDMA Channel x error status + register + 0x88 + 0x20 + read-only + 0x00000000 + + + TEA + Transfer Error Address These bits are + set and cleared by HW, in case of an MDMA data + transfer error. It is used in conjunction with TED. + This field indicates the 7 LSBits of the address + which generated a transfer/access error. It may be + used by SW to retrieve the failing address, by adding + this value (truncated to the buffer transfer length + size) to the current SAR/DAR value. Note: The SAR/DAR + current value doesnt reflect this last address due to + the FIFO management system. The SAR/DAR are only + updated at the end of a (buffer) transfer (of TLEN+1 + bytes). Note: It is not set in case of a link data + error. + 0 + 7 + + + TED + Transfer Error Direction These bit is + set and cleared by HW, in case of an MDMA data + transfer error. + 7 + 1 + + + TELD + Transfer Error Link Data These bit is + set by HW, in case of a transfer error while reading + the block link data structure. It is cleared by + software writing 1 to the CTEIFx bit in the DMA_IFCRy + register. + 8 + 1 + + + TEMD + Transfer Error Mask Data These bit is + set by HW, in case of a transfer error while writing + the Mask Data. It is cleared by software writing 1 to + the CTEIFx bit in the DMA_IFCRy + register. + 9 + 1 + + + ASE + Address/Size Error These bit is set by + HW, when the programmed address is not aligned with + the data size. TED will indicate whether the problem + is on the source or destination. It is cleared by + software writing 1 to the CTEIFx bit in the DMA_IFCRy + register. + 10 + 1 + + + BSE + Block Size Error These bit is set by HW, + when the block size is not an integer multiple of the + data size either for source or destination. TED will + indicate whether the problem is on the source or + destination. It is cleared by software writing 1 to + the CTEIFx bit in the DMA_IFCRy + register. + 11 + 1 + + + + + MDMA_C1CR + MDMA_C1CR + This register is used to control the + concerned channel. + 0x8C + 0x20 + 0x00000000 + + + EN + channel enable + 0 + 1 + read-write + + + TEIE + Transfer error interrupt enable This bit + is set and cleared by software. + 1 + 1 + read-write + + + CTCIE + Channel Transfer Complete interrupt + enable This bit is set and cleared by + software. + 2 + 1 + read-write + + + BRTIE + Block Repeat transfer interrupt enable + This bit is set and cleared by + software. + 3 + 1 + read-write + + + BTIE + Block Transfer interrupt enable This bit + is set and cleared by software. + 4 + 1 + read-write + + + TCIE + buffer Transfer Complete interrupt + enable This bit is set and cleared by + software. + 5 + 1 + read-write + + + PL + Priority level These bits are set and + cleared by software. These bits are protected and can + be written only if EN is 0. + 6 + 2 + read-write + + + BEX + byte Endianness exchange + 12 + 1 + read-write + + + HEX + Half word Endianes + exchange + 13 + 1 + read-write + + + WEX + Word Endianness exchange + 14 + 1 + read-write + + + SWRQ + SW ReQuest Writing a 1 into this bit + sets the CRQAx in MDMA_ISRy register, activating the + request on Channel x Note: Either the whole CxCR + register or the 8-bit/16-bit register @ Address + offset: 0x4E + 0x40 chn may be used for SWRQ + activation. In case of a SW request, acknowledge is + not generated (neither HW signal, nor CxMAR write + access). + 16 + 1 + write-only + + + + + MDMA_C1TCR + MDMA_C1TCR + This register is used to configure the + concerned channel. + 0x90 + 0x20 + read-write + 0x00000000 + + + SINC + Source increment mode These bits are set + and cleared by software. These bits are protected and + can be written only if EN is 0 Note: When source is + AHB (SBUS=1), SINC = 00 is forbidden. In Linked List + Mode, at the end of a block (single or last block in + repeated block transfer mode), this register will be + loaded from memory (from address given by current + LAR[31:0] + 0x00). + 0 + 2 + + + DINC + Destination increment mode These bits + are set and cleared by software. These bits are + protected and can be written only if EN is 0 Note: + When destination is AHB (DBUS=1), DINC = 00 is + forbidden. + 2 + 2 + + + SSIZE + Source data size These bits are set and + cleared by software. These bits are protected and can + be written only if EN is 0 Note: If a value of 11 is + programmed for the TCM access/AHB port, a transfer + error will occur (TEIF bit set) If SINCOS < + SSIZE and SINC ≠ 00, the result will be + unpredictable. Note: SSIZE = 11 (double-word) is + forbidden when source is TCM/AHB bus + (SBUS=1). + 4 + 2 + + + DSIZE + Destination data size These bits are set + and cleared by software. These bits are protected and + can be written only if EN is 0. Note: If a value of + 11 is programmed for the TCM access/AHB port, a + transfer error will occur (TEIF bit set) If DINCOS + < DSIZE and DINC ≠ 00, the result + will be unpredictable. Note: DSIZE = 11 (double-word) + is forbidden when destination is TCM/AHB bus + (DBUS=1). + 6 + 2 + + + SINCOS + source increment offset + size + 8 + 2 + + + DINCOS + Destination increment + offset + 10 + 2 + + + SBURST + source burst transfer + configuration + 12 + 3 + + + DBURST + Destination burst transfer + configuration + 15 + 3 + + + TLEN + buffer transfer lengh + 18 + 7 + + + PKE + PacK Enable These bit is set and cleared + by software. If the Source Size is smaller than the + destination, it will be padded according to the PAM + value. If the Source data size is larger than the + destination one, it will be truncated. The alignment + will be done according to the PAM[0] value. This bit + is protected and can be written only if EN is + 0 + 25 + 1 + + + PAM + Padding/Alignement Mode These bits are + set and cleared by software. Case 1: Source data size + smaller than destination data size - 3 options are + valid. Case 2: Source data size larger than + destination data size. The remainder part is + discarded. When PKE = 1 or DSIZE=SSIZE, these bits + are ignored. These bits are protected and can be + written only if EN is 0 + 26 + 2 + + + TRGM + Trigger Mode These bits are set and + cleared by software. Note: If TRGM is 11 for the + current block, all the values loaded at the end of + the current block through the linked list mechanism + must keep the same value (TRGM=11) and the same SWRM + value, otherwise the result is undefined. These bits + are protected and can be written only if EN is + 0. + 28 + 2 + + + SWRM + SW Request Mode This bit is set and + cleared by software. If a HW or SW request is + currently active, the bit change will be delayed + until the current transfer is completed. If the CxMAR + contains a valid address, the CxMDR value will also + be written @ CxMAR address. This bit is protected and + can be written only if EN is 0. + 30 + 1 + + + BWM + Bufferable Write Mode This bit is set + and cleared by software. This bit is protected and + can be written only if EN is 0. Note: All MDMA + destination accesses are non-cacheable. + 31 + 1 + + + + + MDMA_C1BNDTR + MDMA_C1BNDTR + MDMA Channel x block number of data + register + 0x94 + 0x20 + read-write + 0x00000000 + + + BNDT + block number of data to + transfer + 0 + 17 + + + BRSUM + Block Repeat Source address Update Mode + These bits are protected and can be written only if + EN is 0. + 18 + 1 + + + BRDUM + Block Repeat Destination address Update + Mode These bits are protected and can be written only + if EN is 0. + 19 + 1 + + + BRC + Block Repeat Count This field contains + the number of repetitions of the current block (0 to + 4095). When the channel is enabled, this register is + read-only, indicating the remaining number of blocks, + excluding the current one. This register decrements + after each complete block transfer. Once the last + block transfer has completed, this register can + either stay at zero or be reloaded automatically from + memory (in Linked List mode - i.e. Link Address + valid). These bits are protected and can be written + only if EN is 0. + 20 + 12 + + + + + MDMA_C1SAR + MDMA_C1SAR + MDMA channel x source address + register + 0x98 + 0x20 + read-write + 0x00000000 + + + SAR + source adr base + 0 + 32 + + + + + MDMA_C1DAR + MDMA_C1DAR + MDMA channel x destination address + register + 0x9C + 0x20 + read-write + 0x00000000 + + + DAR + Destination adr base + 0 + 32 + + + + + MDMA_C1BRUR + MDMA_C1BRUR + MDMA channel x Block Repeat address Update + register + 0xA0 + 0x20 + read-write + 0x00000000 + + + SUV + source adresse update + value + 0 + 16 + + + DUV + destination address update + 16 + 16 + + + + + MDMA_C1LAR + MDMA_C1LAR + MDMA channel x Link Address + register + 0xA4 + 0x20 + read-write + 0x00000000 + + + LAR + Link address register + 0 + 32 + + + + + MDMA_C1TBR + MDMA_C1TBR + MDMA channel x Trigger and Bus selection + Register + 0xA8 + 0x20 + read-write + 0x00000000 + + + TSEL + Trigger selection + 0 + 6 + + + SBUS + Source BUS select This bit is protected + and can be written only if EN is 0. + 16 + 1 + + + DBUS + Destination BUS slect This bit is + protected and can be written only if EN is + 0. + 17 + 1 + + + + + MDMA_C1MAR + MDMA_C1MAR + MDMA channel x Mask address + register + 0xB0 + 0x20 + read-write + 0x00000000 + + + MAR + Mask address + 0 + 32 + + + + + MDMA_C1MDR + MDMA_C1MDR + MDMA channel x Mask Data + register + 0xB4 + 0x20 + read-write + 0x00000000 + + + MDR + Mask data + 0 + 32 + + + + + MDMA_C2ISR + MDMA_C2ISR + MDMA channel x interrupt/status + register + 0xC0 + 0x20 + read-only + 0x00000000 + + + TEIF2 + Channel x transfer error interrupt flag + This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCRy register. + 0 + 1 + + + CTCIF2 + Channel x Channel Transfer Complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. CTC is set when the + last block was transferred and the channel has been + automatically disabled. CTC is also set when the + channel is suspended, as a result of writing EN bit + to 0. + 1 + 1 + + + BRTIF2 + Channel x block repeat transfer complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. + 2 + 1 + + + BTIF2 + Channel x block transfer complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. + 3 + 1 + + + TCIF2 + channel x buffer transfer + complete + 4 + 1 + + + CRQA2 + channel x request active + flag + 16 + 1 + + + + + MDMA_C2IFCR + MDMA_C2IFCR + MDMA channel x interrupt flag clear + register + 0xC4 + 0x20 + write-only + 0x00000000 + + + CTEIF2 + Channel x clear transfer error interrupt + flag Writing a 1 into this bit clears TEIFx in the + MDMA_ISRy register + 0 + 1 + + + CCTCIF2 + Clear Channel transfer complete + interrupt flag for channel x Writing a 1 into this + bit clears CTCIFx in the MDMA_ISRy + register + 1 + 1 + + + CBRTIF2 + Channel x clear block repeat transfer + complete interrupt flag Writing a 1 into this bit + clears BRTIFx in the MDMA_ISRy register + 2 + 1 + + + CBTIF2 + Channel x Clear block transfer complete + interrupt flag Writing a 1 into this bit clears BTIFx + in the MDMA_ISRy register + 3 + 1 + + + CLTCIF2 + CLear buffer Transfer Complete Interrupt + Flag for channel x Writing a 1 into this bit clears + TCIFx in the MDMA_ISRy register + 4 + 1 + + + + + MDMA_C2ESR + MDMA_C2ESR + MDMA Channel x error status + register + 0xC8 + 0x20 + read-only + 0x00000000 + + + TEA + Transfer Error Address These bits are + set and cleared by HW, in case of an MDMA data + transfer error. It is used in conjunction with TED. + This field indicates the 7 LSBits of the address + which generated a transfer/access error. It may be + used by SW to retrieve the failing address, by adding + this value (truncated to the buffer transfer length + size) to the current SAR/DAR value. Note: The SAR/DAR + current value doesnt reflect this last address due to + the FIFO management system. The SAR/DAR are only + updated at the end of a (buffer) transfer (of TLEN+1 + bytes). Note: It is not set in case of a link data + error. + 0 + 7 + + + TED + Transfer Error Direction These bit is + set and cleared by HW, in case of an MDMA data + transfer error. + 7 + 1 + + + TELD + Transfer Error Link Data These bit is + set by HW, in case of a transfer error while reading + the block link data structure. It is cleared by + software writing 1 to the CTEIFx bit in the DMA_IFCRy + register. + 8 + 1 + + + TEMD + Transfer Error Mask Data These bit is + set by HW, in case of a transfer error while writing + the Mask Data. It is cleared by software writing 1 to + the CTEIFx bit in the DMA_IFCRy + register. + 9 + 1 + + + ASE + Address/Size Error These bit is set by + HW, when the programmed address is not aligned with + the data size. TED will indicate whether the problem + is on the source or destination. It is cleared by + software writing 1 to the CTEIFx bit in the DMA_IFCRy + register. + 10 + 1 + + + BSE + Block Size Error These bit is set by HW, + when the block size is not an integer multiple of the + data size either for source or destination. TED will + indicate whether the problem is on the source or + destination. It is cleared by software writing 1 to + the CTEIFx bit in the DMA_IFCRy + register. + 11 + 1 + + + + + MDMA_C2CR + MDMA_C2CR + This register is used to control the + concerned channel. + 0xCC + 0x20 + 0x00000000 + + + EN + channel enable + 0 + 1 + read-write + + + TEIE + Transfer error interrupt enable This bit + is set and cleared by software. + 1 + 1 + read-write + + + CTCIE + Channel Transfer Complete interrupt + enable This bit is set and cleared by + software. + 2 + 1 + read-write + + + BRTIE + Block Repeat transfer interrupt enable + This bit is set and cleared by + software. + 3 + 1 + read-write + + + BTIE + Block Transfer interrupt enable This bit + is set and cleared by software. + 4 + 1 + read-write + + + TCIE + buffer Transfer Complete interrupt + enable This bit is set and cleared by + software. + 5 + 1 + read-write + + + PL + Priority level These bits are set and + cleared by software. These bits are protected and can + be written only if EN is 0. + 6 + 2 + read-write + + + BEX + byte Endianness exchange + 12 + 1 + read-write + + + HEX + Half word Endianes + exchange + 13 + 1 + read-write + + + WEX + Word Endianness exchange + 14 + 1 + read-write + + + SWRQ + SW ReQuest Writing a 1 into this bit + sets the CRQAx in MDMA_ISRy register, activating the + request on Channel x Note: Either the whole CxCR + register or the 8-bit/16-bit register @ Address + offset: 0x4E + 0x40 chn may be used for SWRQ + activation. In case of a SW request, acknowledge is + not generated (neither HW signal, nor CxMAR write + access). + 16 + 1 + write-only + + + + + MDMA_C2TCR + MDMA_C2TCR + This register is used to configure the + concerned channel. + 0xD0 + 0x20 + read-write + 0x00000000 + + + SINC + Source increment mode These bits are set + and cleared by software. These bits are protected and + can be written only if EN is 0 Note: When source is + AHB (SBUS=1), SINC = 00 is forbidden. In Linked List + Mode, at the end of a block (single or last block in + repeated block transfer mode), this register will be + loaded from memory (from address given by current + LAR[31:0] + 0x00). + 0 + 2 + + + DINC + Destination increment mode These bits + are set and cleared by software. These bits are + protected and can be written only if EN is 0 Note: + When destination is AHB (DBUS=1), DINC = 00 is + forbidden. + 2 + 2 + + + SSIZE + Source data size These bits are set and + cleared by software. These bits are protected and can + be written only if EN is 0 Note: If a value of 11 is + programmed for the TCM access/AHB port, a transfer + error will occur (TEIF bit set) If SINCOS < + SSIZE and SINC ≠ 00, the result will be + unpredictable. Note: SSIZE = 11 (double-word) is + forbidden when source is TCM/AHB bus + (SBUS=1). + 4 + 2 + + + DSIZE + Destination data size These bits are set + and cleared by software. These bits are protected and + can be written only if EN is 0. Note: If a value of + 11 is programmed for the TCM access/AHB port, a + transfer error will occur (TEIF bit set) If DINCOS + < DSIZE and DINC ≠ 00, the result + will be unpredictable. Note: DSIZE = 11 (double-word) + is forbidden when destination is TCM/AHB bus + (DBUS=1). + 6 + 2 + + + SINCOS + source increment offset + size + 8 + 2 + + + DINCOS + Destination increment + offset + 10 + 2 + + + SBURST + source burst transfer + configuration + 12 + 3 + + + DBURST + Destination burst transfer + configuration + 15 + 3 + + + TLEN + buffer transfer lengh + 18 + 7 + + + PKE + PacK Enable These bit is set and cleared + by software. If the Source Size is smaller than the + destination, it will be padded according to the PAM + value. If the Source data size is larger than the + destination one, it will be truncated. The alignment + will be done according to the PAM[0] value. This bit + is protected and can be written only if EN is + 0 + 25 + 1 + + + PAM + Padding/Alignement Mode These bits are + set and cleared by software. Case 1: Source data size + smaller than destination data size - 3 options are + valid. Case 2: Source data size larger than + destination data size. The remainder part is + discarded. When PKE = 1 or DSIZE=SSIZE, these bits + are ignored. These bits are protected and can be + written only if EN is 0 + 26 + 2 + + + TRGM + Trigger Mode These bits are set and + cleared by software. Note: If TRGM is 11 for the + current block, all the values loaded at the end of + the current block through the linked list mechanism + must keep the same value (TRGM=11) and the same SWRM + value, otherwise the result is undefined. These bits + are protected and can be written only if EN is + 0. + 28 + 2 + + + SWRM + SW Request Mode This bit is set and + cleared by software. If a HW or SW request is + currently active, the bit change will be delayed + until the current transfer is completed. If the CxMAR + contains a valid address, the CxMDR value will also + be written @ CxMAR address. This bit is protected and + can be written only if EN is 0. + 30 + 1 + + + BWM + Bufferable Write Mode This bit is set + and cleared by software. This bit is protected and + can be written only if EN is 0. Note: All MDMA + destination accesses are non-cacheable. + 31 + 1 + + + + + MDMA_C2BNDTR + MDMA_C2BNDTR + MDMA Channel x block number of data + register + 0xD4 + 0x20 + read-write + 0x00000000 + + + BNDT + block number of data to + transfer + 0 + 17 + + + BRSUM + Block Repeat Source address Update Mode + These bits are protected and can be written only if + EN is 0. + 18 + 1 + + + BRDUM + Block Repeat Destination address Update + Mode These bits are protected and can be written only + if EN is 0. + 19 + 1 + + + BRC + Block Repeat Count This field contains + the number of repetitions of the current block (0 to + 4095). When the channel is enabled, this register is + read-only, indicating the remaining number of blocks, + excluding the current one. This register decrements + after each complete block transfer. Once the last + block transfer has completed, this register can + either stay at zero or be reloaded automatically from + memory (in Linked List mode - i.e. Link Address + valid). These bits are protected and can be written + only if EN is 0. + 20 + 12 + + + + + MDMA_C2SAR + MDMA_C2SAR + MDMA channel x source address + register + 0xD8 + 0x20 + read-write + 0x00000000 + + + SAR + source adr base + 0 + 32 + + + + + MDMA_C2DAR + MDMA_C2DAR + MDMA channel x destination address + register + 0xDC + 0x20 + read-write + 0x00000000 + + + DAR + Destination adr base + 0 + 32 + + + + + MDMA_C2BRUR + MDMA_C2BRUR + MDMA channel x Block Repeat address Update + register + 0xE0 + 0x20 + read-write + 0x00000000 + + + SUV + source adresse update + value + 0 + 16 + + + DUV + destination address update + 16 + 16 + + + + + MDMA_C2LAR + MDMA_C2LAR + MDMA channel x Link Address + register + 0xE4 + 0x20 + read-write + 0x00000000 + + + LAR + Link address register + 0 + 32 + + + + + MDMA_C2TBR + MDMA_C2TBR + MDMA channel x Trigger and Bus selection + Register + 0xE8 + 0x20 + read-write + 0x00000000 + + + TSEL + Trigger selection + 0 + 6 + + + SBUS + Source BUS select This bit is protected + and can be written only if EN is 0. + 16 + 1 + + + DBUS + Destination BUS slect This bit is + protected and can be written only if EN is + 0. + 17 + 1 + + + + + MDMA_C2MAR + MDMA_C2MAR + MDMA channel x Mask address + register + 0xF0 + 0x20 + read-write + 0x00000000 + + + MAR + Mask address + 0 + 32 + + + + + MDMA_C2MDR + MDMA_C2MDR + MDMA channel x Mask Data + register + 0xF4 + 0x20 + read-write + 0x00000000 + + + MDR + Mask data + 0 + 32 + + + + + MDMA_C3ISR + MDMA_C3ISR + MDMA channel x interrupt/status + register + 0x100 + 0x20 + read-only + 0x00000000 + + + TEIF3 + Channel x transfer error interrupt flag + This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCRy register. + 0 + 1 + + + CTCIF3 + Channel x Channel Transfer Complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. CTC is set when the + last block was transferred and the channel has been + automatically disabled. CTC is also set when the + channel is suspended, as a result of writing EN bit + to 0. + 1 + 1 + + + BRTIF3 + Channel x block repeat transfer complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. + 2 + 1 + + + BTIF3 + Channel x block transfer complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. + 3 + 1 + + + TCIF3 + channel x buffer transfer + complete + 4 + 1 + + + CRQA3 + channel x request active + flag + 16 + 1 + + + + + MDMA_C3IFCR + MDMA_C3IFCR + MDMA channel x interrupt flag clear + register + 0x104 + 0x20 + write-only + 0x00000000 + + + CTEIF3 + Channel x clear transfer error interrupt + flag Writing a 1 into this bit clears TEIFx in the + MDMA_ISRy register + 0 + 1 + + + CCTCIF3 + Clear Channel transfer complete + interrupt flag for channel x Writing a 1 into this + bit clears CTCIFx in the MDMA_ISRy + register + 1 + 1 + + + CBRTIF3 + Channel x clear block repeat transfer + complete interrupt flag Writing a 1 into this bit + clears BRTIFx in the MDMA_ISRy register + 2 + 1 + + + CBTIF3 + Channel x Clear block transfer complete + interrupt flag Writing a 1 into this bit clears BTIFx + in the MDMA_ISRy register + 3 + 1 + + + CLTCIF3 + CLear buffer Transfer Complete Interrupt + Flag for channel x Writing a 1 into this bit clears + TCIFx in the MDMA_ISRy register + 4 + 1 + + + + + MDMA_C3ESR + MDMA_C3ESR + MDMA Channel x error status + register + 0x108 + 0x20 + read-only + 0x00000000 + + + TEA + Transfer Error Address These bits are + set and cleared by HW, in case of an MDMA data + transfer error. It is used in conjunction with TED. + This field indicates the 7 LSBits of the address + which generated a transfer/access error. It may be + used by SW to retrieve the failing address, by adding + this value (truncated to the buffer transfer length + size) to the current SAR/DAR value. Note: The SAR/DAR + current value doesnt reflect this last address due to + the FIFO management system. The SAR/DAR are only + updated at the end of a (buffer) transfer (of TLEN+1 + bytes). Note: It is not set in case of a link data + error. + 0 + 7 + + + TED + Transfer Error Direction These bit is + set and cleared by HW, in case of an MDMA data + transfer error. + 7 + 1 + + + TELD + Transfer Error Link Data These bit is + set by HW, in case of a transfer error while reading + the block link data structure. It is cleared by + software writing 1 to the CTEIFx bit in the DMA_IFCRy + register. + 8 + 1 + + + TEMD + Transfer Error Mask Data These bit is + set by HW, in case of a transfer error while writing + the Mask Data. It is cleared by software writing 1 to + the CTEIFx bit in the DMA_IFCRy + register. + 9 + 1 + + + ASE + Address/Size Error These bit is set by + HW, when the programmed address is not aligned with + the data size. TED will indicate whether the problem + is on the source or destination. It is cleared by + software writing 1 to the CTEIFx bit in the DMA_IFCRy + register. + 10 + 1 + + + BSE + Block Size Error These bit is set by HW, + when the block size is not an integer multiple of the + data size either for source or destination. TED will + indicate whether the problem is on the source or + destination. It is cleared by software writing 1 to + the CTEIFx bit in the DMA_IFCRy + register. + 11 + 1 + + + + + MDMA_C3CR + MDMA_C3CR + This register is used to control the + concerned channel. + 0x10C + 0x20 + 0x00000000 + + + EN + channel enable + 0 + 1 + read-write + + + TEIE + Transfer error interrupt enable This bit + is set and cleared by software. + 1 + 1 + read-write + + + CTCIE + Channel Transfer Complete interrupt + enable This bit is set and cleared by + software. + 2 + 1 + read-write + + + BRTIE + Block Repeat transfer interrupt enable + This bit is set and cleared by + software. + 3 + 1 + read-write + + + BTIE + Block Transfer interrupt enable This bit + is set and cleared by software. + 4 + 1 + read-write + + + TCIE + buffer Transfer Complete interrupt + enable This bit is set and cleared by + software. + 5 + 1 + read-write + + + PL + Priority level These bits are set and + cleared by software. These bits are protected and can + be written only if EN is 0. + 6 + 2 + read-write + + + BEX + byte Endianness exchange + 12 + 1 + read-write + + + HEX + Half word Endianes + exchange + 13 + 1 + read-write + + + WEX + Word Endianness exchange + 14 + 1 + read-write + + + SWRQ + SW ReQuest Writing a 1 into this bit + sets the CRQAx in MDMA_ISRy register, activating the + request on Channel x Note: Either the whole CxCR + register or the 8-bit/16-bit register @ Address + offset: 0x4E + 0x40 chn may be used for SWRQ + activation. In case of a SW request, acknowledge is + not generated (neither HW signal, nor CxMAR write + access). + 16 + 1 + write-only + + + + + MDMA_C3TCR + MDMA_C3TCR + This register is used to configure the + concerned channel. + 0x110 + 0x20 + read-write + 0x00000000 + + + SINC + Source increment mode These bits are set + and cleared by software. These bits are protected and + can be written only if EN is 0 Note: When source is + AHB (SBUS=1), SINC = 00 is forbidden. In Linked List + Mode, at the end of a block (single or last block in + repeated block transfer mode), this register will be + loaded from memory (from address given by current + LAR[31:0] + 0x00). + 0 + 2 + + + DINC + Destination increment mode These bits + are set and cleared by software. These bits are + protected and can be written only if EN is 0 Note: + When destination is AHB (DBUS=1), DINC = 00 is + forbidden. + 2 + 2 + + + SSIZE + Source data size These bits are set and + cleared by software. These bits are protected and can + be written only if EN is 0 Note: If a value of 11 is + programmed for the TCM access/AHB port, a transfer + error will occur (TEIF bit set) If SINCOS < + SSIZE and SINC ≠ 00, the result will be + unpredictable. Note: SSIZE = 11 (double-word) is + forbidden when source is TCM/AHB bus + (SBUS=1). + 4 + 2 + + + DSIZE + Destination data size These bits are set + and cleared by software. These bits are protected and + can be written only if EN is 0. Note: If a value of + 11 is programmed for the TCM access/AHB port, a + transfer error will occur (TEIF bit set) If DINCOS + < DSIZE and DINC ≠ 00, the result + will be unpredictable. Note: DSIZE = 11 (double-word) + is forbidden when destination is TCM/AHB bus + (DBUS=1). + 6 + 2 + + + SINCOS + source increment offset + size + 8 + 2 + + + DINCOS + Destination increment + offset + 10 + 2 + + + SBURST + source burst transfer + configuration + 12 + 3 + + + DBURST + Destination burst transfer + configuration + 15 + 3 + + + TLEN + buffer transfer lengh + 18 + 7 + + + PKE + PacK Enable These bit is set and cleared + by software. If the Source Size is smaller than the + destination, it will be padded according to the PAM + value. If the Source data size is larger than the + destination one, it will be truncated. The alignment + will be done according to the PAM[0] value. This bit + is protected and can be written only if EN is + 0 + 25 + 1 + + + PAM + Padding/Alignement Mode These bits are + set and cleared by software. Case 1: Source data size + smaller than destination data size - 3 options are + valid. Case 2: Source data size larger than + destination data size. The remainder part is + discarded. When PKE = 1 or DSIZE=SSIZE, these bits + are ignored. These bits are protected and can be + written only if EN is 0 + 26 + 2 + + + TRGM + Trigger Mode These bits are set and + cleared by software. Note: If TRGM is 11 for the + current block, all the values loaded at the end of + the current block through the linked list mechanism + must keep the same value (TRGM=11) and the same SWRM + value, otherwise the result is undefined. These bits + are protected and can be written only if EN is + 0. + 28 + 2 + + + SWRM + SW Request Mode This bit is set and + cleared by software. If a HW or SW request is + currently active, the bit change will be delayed + until the current transfer is completed. If the CxMAR + contains a valid address, the CxMDR value will also + be written @ CxMAR address. This bit is protected and + can be written only if EN is 0. + 30 + 1 + + + BWM + Bufferable Write Mode This bit is set + and cleared by software. This bit is protected and + can be written only if EN is 0. Note: All MDMA + destination accesses are non-cacheable. + 31 + 1 + + + + + MDMA_C3BNDTR + MDMA_C3BNDTR + MDMA Channel x block number of data + register + 0x114 + 0x20 + read-write + 0x00000000 + + + BNDT + block number of data to + transfer + 0 + 17 + + + BRSUM + Block Repeat Source address Update Mode + These bits are protected and can be written only if + EN is 0. + 18 + 1 + + + BRDUM + Block Repeat Destination address Update + Mode These bits are protected and can be written only + if EN is 0. + 19 + 1 + + + BRC + Block Repeat Count This field contains + the number of repetitions of the current block (0 to + 4095). When the channel is enabled, this register is + read-only, indicating the remaining number of blocks, + excluding the current one. This register decrements + after each complete block transfer. Once the last + block transfer has completed, this register can + either stay at zero or be reloaded automatically from + memory (in Linked List mode - i.e. Link Address + valid). These bits are protected and can be written + only if EN is 0. + 20 + 12 + + + + + MDMA_C3SAR + MDMA_C3SAR + MDMA channel x source address + register + 0x118 + 0x20 + read-write + 0x00000000 + + + SAR + source adr base + 0 + 32 + + + + + MDMA_C3DAR + MDMA_C3DAR + MDMA channel x destination address + register + 0x11C + 0x20 + read-write + 0x00000000 + + + DAR + Destination adr base + 0 + 32 + + + + + MDMA_C3BRUR + MDMA_C3BRUR + MDMA channel x Block Repeat address Update + register + 0x120 + 0x20 + read-write + 0x00000000 + + + SUV + source adresse update + value + 0 + 16 + + + DUV + destination address update + 16 + 16 + + + + + MDMA_C3LAR + MDMA_C3LAR + MDMA channel x Link Address + register + 0x124 + 0x20 + read-write + 0x00000000 + + + LAR + Link address register + 0 + 32 + + + + + MDMA_C3TBR + MDMA_C3TBR + MDMA channel x Trigger and Bus selection + Register + 0x128 + 0x20 + read-write + 0x00000000 + + + TSEL + Trigger selection + 0 + 6 + + + SBUS + Source BUS select This bit is protected + and can be written only if EN is 0. + 16 + 1 + + + DBUS + Destination BUS slect This bit is + protected and can be written only if EN is + 0. + 17 + 1 + + + + + MDMA_C3MAR + MDMA_C3MAR + MDMA channel x Mask address + register + 0x130 + 0x20 + read-write + 0x00000000 + + + MAR + Mask address + 0 + 32 + + + + + MDMA_C3MDR + MDMA_C3MDR + MDMA channel x Mask Data + register + 0x134 + 0x20 + read-write + 0x00000000 + + + MDR + Mask data + 0 + 32 + + + + + MDMA_C4ISR + MDMA_C4ISR + MDMA channel x interrupt/status + register + 0x140 + 0x20 + read-only + 0x00000000 + + + TEIF4 + Channel x transfer error interrupt flag + This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCRy register. + 0 + 1 + + + CTCIF4 + Channel x Channel Transfer Complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. CTC is set when the + last block was transferred and the channel has been + automatically disabled. CTC is also set when the + channel is suspended, as a result of writing EN bit + to 0. + 1 + 1 + + + BRTIF4 + Channel x block repeat transfer complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. + 2 + 1 + + + BTIF4 + Channel x block transfer complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. + 3 + 1 + + + TCIF4 + channel x buffer transfer + complete + 4 + 1 + + + CRQA4 + channel x request active + flag + 16 + 1 + + + + + MDMA_C4IFCR + MDMA_C4IFCR + MDMA channel x interrupt flag clear + register + 0x144 + 0x20 + write-only + 0x00000000 + + + CTEIF4 + Channel x clear transfer error interrupt + flag Writing a 1 into this bit clears TEIFx in the + MDMA_ISRy register + 0 + 1 + + + CCTCIF4 + Clear Channel transfer complete + interrupt flag for channel x Writing a 1 into this + bit clears CTCIFx in the MDMA_ISRy + register + 1 + 1 + + + CBRTIF4 + Channel x clear block repeat transfer + complete interrupt flag Writing a 1 into this bit + clears BRTIFx in the MDMA_ISRy register + 2 + 1 + + + CBTIF4 + Channel x Clear block transfer complete + interrupt flag Writing a 1 into this bit clears BTIFx + in the MDMA_ISRy register + 3 + 1 + + + CLTCIF4 + CLear buffer Transfer Complete Interrupt + Flag for channel x Writing a 1 into this bit clears + TCIFx in the MDMA_ISRy register + 4 + 1 + + + + + MDMA_C4ESR + MDMA_C4ESR + MDMA Channel x error status + register + 0x148 + 0x20 + read-only + 0x00000000 + + + TEA + Transfer Error Address These bits are + set and cleared by HW, in case of an MDMA data + transfer error. It is used in conjunction with TED. + This field indicates the 7 LSBits of the address + which generated a transfer/access error. It may be + used by SW to retrieve the failing address, by adding + this value (truncated to the buffer transfer length + size) to the current SAR/DAR value. Note: The SAR/DAR + current value doesnt reflect this last address due to + the FIFO management system. The SAR/DAR are only + updated at the end of a (buffer) transfer (of TLEN+1 + bytes). Note: It is not set in case of a link data + error. + 0 + 7 + + + TED + Transfer Error Direction These bit is + set and cleared by HW, in case of an MDMA data + transfer error. + 7 + 1 + + + TELD + Transfer Error Link Data These bit is + set by HW, in case of a transfer error while reading + the block link data structure. It is cleared by + software writing 1 to the CTEIFx bit in the DMA_IFCRy + register. + 8 + 1 + + + TEMD + Transfer Error Mask Data These bit is + set by HW, in case of a transfer error while writing + the Mask Data. It is cleared by software writing 1 to + the CTEIFx bit in the DMA_IFCRy + register. + 9 + 1 + + + ASE + Address/Size Error These bit is set by + HW, when the programmed address is not aligned with + the data size. TED will indicate whether the problem + is on the source or destination. It is cleared by + software writing 1 to the CTEIFx bit in the DMA_IFCRy + register. + 10 + 1 + + + BSE + Block Size Error These bit is set by HW, + when the block size is not an integer multiple of the + data size either for source or destination. TED will + indicate whether the problem is on the source or + destination. It is cleared by software writing 1 to + the CTEIFx bit in the DMA_IFCRy + register. + 11 + 1 + + + + + MDMA_C4CR + MDMA_C4CR + This register is used to control the + concerned channel. + 0x14C + 0x20 + 0x00000000 + + + EN + channel enable + 0 + 1 + read-write + + + TEIE + Transfer error interrupt enable This bit + is set and cleared by software. + 1 + 1 + read-write + + + CTCIE + Channel Transfer Complete interrupt + enable This bit is set and cleared by + software. + 2 + 1 + read-write + + + BRTIE + Block Repeat transfer interrupt enable + This bit is set and cleared by + software. + 3 + 1 + read-write + + + BTIE + Block Transfer interrupt enable This bit + is set and cleared by software. + 4 + 1 + read-write + + + TCIE + buffer Transfer Complete interrupt + enable This bit is set and cleared by + software. + 5 + 1 + read-write + + + PL + Priority level These bits are set and + cleared by software. These bits are protected and can + be written only if EN is 0. + 6 + 2 + read-write + + + BEX + byte Endianness exchange + 12 + 1 + read-write + + + HEX + Half word Endianes + exchange + 13 + 1 + read-write + + + WEX + Word Endianness exchange + 14 + 1 + read-write + + + SWRQ + SW ReQuest Writing a 1 into this bit + sets the CRQAx in MDMA_ISRy register, activating the + request on Channel x Note: Either the whole CxCR + register or the 8-bit/16-bit register @ Address + offset: 0x4E + 0x40 chn may be used for SWRQ + activation. In case of a SW request, acknowledge is + not generated (neither HW signal, nor CxMAR write + access). + 16 + 1 + write-only + + + + + MDMA_C4TCR + MDMA_C4TCR + This register is used to configure the + concerned channel. + 0x150 + 0x20 + read-write + 0x00000000 + + + SINC + Source increment mode These bits are set + and cleared by software. These bits are protected and + can be written only if EN is 0 Note: When source is + AHB (SBUS=1), SINC = 00 is forbidden. In Linked List + Mode, at the end of a block (single or last block in + repeated block transfer mode), this register will be + loaded from memory (from address given by current + LAR[31:0] + 0x00). + 0 + 2 + + + DINC + Destination increment mode These bits + are set and cleared by software. These bits are + protected and can be written only if EN is 0 Note: + When destination is AHB (DBUS=1), DINC = 00 is + forbidden. + 2 + 2 + + + SSIZE + Source data size These bits are set and + cleared by software. These bits are protected and can + be written only if EN is 0 Note: If a value of 11 is + programmed for the TCM access/AHB port, a transfer + error will occur (TEIF bit set) If SINCOS < + SSIZE and SINC ≠ 00, the result will be + unpredictable. Note: SSIZE = 11 (double-word) is + forbidden when source is TCM/AHB bus + (SBUS=1). + 4 + 2 + + + DSIZE + Destination data size These bits are set + and cleared by software. These bits are protected and + can be written only if EN is 0. Note: If a value of + 11 is programmed for the TCM access/AHB port, a + transfer error will occur (TEIF bit set) If DINCOS + < DSIZE and DINC ≠ 00, the result + will be unpredictable. Note: DSIZE = 11 (double-word) + is forbidden when destination is TCM/AHB bus + (DBUS=1). + 6 + 2 + + + SINCOS + source increment offset + size + 8 + 2 + + + DINCOS + Destination increment + offset + 10 + 2 + + + SBURST + source burst transfer + configuration + 12 + 3 + + + DBURST + Destination burst transfer + configuration + 15 + 3 + + + TLEN + buffer transfer lengh + 18 + 7 + + + PKE + PacK Enable These bit is set and cleared + by software. If the Source Size is smaller than the + destination, it will be padded according to the PAM + value. If the Source data size is larger than the + destination one, it will be truncated. The alignment + will be done according to the PAM[0] value. This bit + is protected and can be written only if EN is + 0 + 25 + 1 + + + PAM + Padding/Alignement Mode These bits are + set and cleared by software. Case 1: Source data size + smaller than destination data size - 3 options are + valid. Case 2: Source data size larger than + destination data size. The remainder part is + discarded. When PKE = 1 or DSIZE=SSIZE, these bits + are ignored. These bits are protected and can be + written only if EN is 0 + 26 + 2 + + + TRGM + Trigger Mode These bits are set and + cleared by software. Note: If TRGM is 11 for the + current block, all the values loaded at the end of + the current block through the linked list mechanism + must keep the same value (TRGM=11) and the same SWRM + value, otherwise the result is undefined. These bits + are protected and can be written only if EN is + 0. + 28 + 2 + + + SWRM + SW Request Mode This bit is set and + cleared by software. If a HW or SW request is + currently active, the bit change will be delayed + until the current transfer is completed. If the CxMAR + contains a valid address, the CxMDR value will also + be written @ CxMAR address. This bit is protected and + can be written only if EN is 0. + 30 + 1 + + + BWM + Bufferable Write Mode This bit is set + and cleared by software. This bit is protected and + can be written only if EN is 0. Note: All MDMA + destination accesses are non-cacheable. + 31 + 1 + + + + + MDMA_C4BNDTR + MDMA_C4BNDTR + MDMA Channel x block number of data + register + 0x154 + 0x20 + read-write + 0x00000000 + + + BNDT + block number of data to + transfer + 0 + 17 + + + BRSUM + Block Repeat Source address Update Mode + These bits are protected and can be written only if + EN is 0. + 18 + 1 + + + BRDUM + Block Repeat Destination address Update + Mode These bits are protected and can be written only + if EN is 0. + 19 + 1 + + + BRC + Block Repeat Count This field contains + the number of repetitions of the current block (0 to + 4095). When the channel is enabled, this register is + read-only, indicating the remaining number of blocks, + excluding the current one. This register decrements + after each complete block transfer. Once the last + block transfer has completed, this register can + either stay at zero or be reloaded automatically from + memory (in Linked List mode - i.e. Link Address + valid). These bits are protected and can be written + only if EN is 0. + 20 + 12 + + + + + MDMA_C4SAR + MDMA_C4SAR + MDMA channel x source address + register + 0x158 + 0x20 + read-write + 0x00000000 + + + SAR + source adr base + 0 + 32 + + + + + MDMA_C4DAR + MDMA_C4DAR + MDMA channel x destination address + register + 0x15C + 0x20 + read-write + 0x00000000 + + + DAR + Destination adr base + 0 + 32 + + + + + MDMA_C4BRUR + MDMA_C4BRUR + MDMA channel x Block Repeat address Update + register + 0x160 + 0x20 + read-write + 0x00000000 + + + SUV + source adresse update + value + 0 + 16 + + + DUV + destination address update + 16 + 16 + + + + + MDMA_C4LAR + MDMA_C4LAR + MDMA channel x Link Address + register + 0x164 + 0x20 + read-write + 0x00000000 + + + LAR + Link address register + 0 + 32 + + + + + MDMA_C4TBR + MDMA_C4TBR + MDMA channel x Trigger and Bus selection + Register + 0x168 + 0x20 + read-write + 0x00000000 + + + TSEL + Trigger selection + 0 + 6 + + + SBUS + Source BUS select This bit is protected + and can be written only if EN is 0. + 16 + 1 + + + DBUS + Destination BUS slect This bit is + protected and can be written only if EN is + 0. + 17 + 1 + + + + + MDMA_C4MAR + MDMA_C4MAR + MDMA channel x Mask address + register + 0x170 + 0x20 + read-write + 0x00000000 + + + MAR + Mask address + 0 + 32 + + + + + MDMA_C4MDR + MDMA_C4MDR + MDMA channel x Mask Data + register + 0x174 + 0x20 + read-write + 0x00000000 + + + MDR + Mask data + 0 + 32 + + + + + MDMA_C5ISR + MDMA_C5ISR + MDMA channel x interrupt/status + register + 0x180 + 0x20 + read-only + 0x00000000 + + + TEIF5 + Channel x transfer error interrupt flag + This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCRy register. + 0 + 1 + + + CTCIF5 + Channel x Channel Transfer Complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. CTC is set when the + last block was transferred and the channel has been + automatically disabled. CTC is also set when the + channel is suspended, as a result of writing EN bit + to 0. + 1 + 1 + + + BRTIF5 + Channel x block repeat transfer complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. + 2 + 1 + + + BTIF5 + Channel x block transfer complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. + 3 + 1 + + + TCIF5 + channel x buffer transfer + complete + 4 + 1 + + + CRQA5 + channel x request active + flag + 16 + 1 + + + + + MDMA_C5IFCR + MDMA_C5IFCR + MDMA channel x interrupt flag clear + register + 0x184 + 0x20 + write-only + 0x00000000 + + + CTEIF5 + Channel x clear transfer error interrupt + flag Writing a 1 into this bit clears TEIFx in the + MDMA_ISRy register + 0 + 1 + + + CCTCIF5 + Clear Channel transfer complete + interrupt flag for channel x Writing a 1 into this + bit clears CTCIFx in the MDMA_ISRy + register + 1 + 1 + + + CBRTIF5 + Channel x clear block repeat transfer + complete interrupt flag Writing a 1 into this bit + clears BRTIFx in the MDMA_ISRy register + 2 + 1 + + + CBTIF5 + Channel x Clear block transfer complete + interrupt flag Writing a 1 into this bit clears BTIFx + in the MDMA_ISRy register + 3 + 1 + + + CLTCIF5 + CLear buffer Transfer Complete Interrupt + Flag for channel x Writing a 1 into this bit clears + TCIFx in the MDMA_ISRy register + 4 + 1 + + + + + MDMA_C5ESR + MDMA_C5ESR + MDMA Channel x error status + register + 0x188 + 0x20 + read-only + 0x00000000 + + + TEA + Transfer Error Address These bits are + set and cleared by HW, in case of an MDMA data + transfer error. It is used in conjunction with TED. + This field indicates the 7 LSBits of the address + which generated a transfer/access error. It may be + used by SW to retrieve the failing address, by adding + this value (truncated to the buffer transfer length + size) to the current SAR/DAR value. Note: The SAR/DAR + current value doesnt reflect this last address due to + the FIFO management system. The SAR/DAR are only + updated at the end of a (buffer) transfer (of TLEN+1 + bytes). Note: It is not set in case of a link data + error. + 0 + 7 + + + TED + Transfer Error Direction These bit is + set and cleared by HW, in case of an MDMA data + transfer error. + 7 + 1 + + + TELD + Transfer Error Link Data These bit is + set by HW, in case of a transfer error while reading + the block link data structure. It is cleared by + software writing 1 to the CTEIFx bit in the DMA_IFCRy + register. + 8 + 1 + + + TEMD + Transfer Error Mask Data These bit is + set by HW, in case of a transfer error while writing + the Mask Data. It is cleared by software writing 1 to + the CTEIFx bit in the DMA_IFCRy + register. + 9 + 1 + + + ASE + Address/Size Error These bit is set by + HW, when the programmed address is not aligned with + the data size. TED will indicate whether the problem + is on the source or destination. It is cleared by + software writing 1 to the CTEIFx bit in the DMA_IFCRy + register. + 10 + 1 + + + BSE + Block Size Error These bit is set by HW, + when the block size is not an integer multiple of the + data size either for source or destination. TED will + indicate whether the problem is on the source or + destination. It is cleared by software writing 1 to + the CTEIFx bit in the DMA_IFCRy + register. + 11 + 1 + + + + + MDMA_C5CR + MDMA_C5CR + This register is used to control the + concerned channel. + 0x18C + 0x20 + 0x00000000 + + + EN + channel enable + 0 + 1 + read-write + + + TEIE + Transfer error interrupt enable This bit + is set and cleared by software. + 1 + 1 + read-write + + + CTCIE + Channel Transfer Complete interrupt + enable This bit is set and cleared by + software. + 2 + 1 + read-write + + + BRTIE + Block Repeat transfer interrupt enable + This bit is set and cleared by + software. + 3 + 1 + read-write + + + BTIE + Block Transfer interrupt enable This bit + is set and cleared by software. + 4 + 1 + read-write + + + TCIE + buffer Transfer Complete interrupt + enable This bit is set and cleared by + software. + 5 + 1 + read-write + + + PL + Priority level These bits are set and + cleared by software. These bits are protected and can + be written only if EN is 0. + 6 + 2 + read-write + + + BEX + byte Endianness exchange + 12 + 1 + read-write + + + HEX + Half word Endianes + exchange + 13 + 1 + read-write + + + WEX + Word Endianness exchange + 14 + 1 + read-write + + + SWRQ + SW ReQuest Writing a 1 into this bit + sets the CRQAx in MDMA_ISRy register, activating the + request on Channel x Note: Either the whole CxCR + register or the 8-bit/16-bit register @ Address + offset: 0x4E + 0x40 chn may be used for SWRQ + activation. In case of a SW request, acknowledge is + not generated (neither HW signal, nor CxMAR write + access). + 16 + 1 + write-only + + + + + MDMA_C5TCR + MDMA_C5TCR + This register is used to configure the + concerned channel. + 0x190 + 0x20 + read-write + 0x00000000 + + + SINC + Source increment mode These bits are set + and cleared by software. These bits are protected and + can be written only if EN is 0 Note: When source is + AHB (SBUS=1), SINC = 00 is forbidden. In Linked List + Mode, at the end of a block (single or last block in + repeated block transfer mode), this register will be + loaded from memory (from address given by current + LAR[31:0] + 0x00). + 0 + 2 + + + DINC + Destination increment mode These bits + are set and cleared by software. These bits are + protected and can be written only if EN is 0 Note: + When destination is AHB (DBUS=1), DINC = 00 is + forbidden. + 2 + 2 + + + SSIZE + Source data size These bits are set and + cleared by software. These bits are protected and can + be written only if EN is 0 Note: If a value of 11 is + programmed for the TCM access/AHB port, a transfer + error will occur (TEIF bit set) If SINCOS < + SSIZE and SINC ≠ 00, the result will be + unpredictable. Note: SSIZE = 11 (double-word) is + forbidden when source is TCM/AHB bus + (SBUS=1). + 4 + 2 + + + DSIZE + Destination data size These bits are set + and cleared by software. These bits are protected and + can be written only if EN is 0. Note: If a value of + 11 is programmed for the TCM access/AHB port, a + transfer error will occur (TEIF bit set) If DINCOS + < DSIZE and DINC ≠ 00, the result + will be unpredictable. Note: DSIZE = 11 (double-word) + is forbidden when destination is TCM/AHB bus + (DBUS=1). + 6 + 2 + + + SINCOS + source increment offset + size + 8 + 2 + + + DINCOS + Destination increment + offset + 10 + 2 + + + SBURST + source burst transfer + configuration + 12 + 3 + + + DBURST + Destination burst transfer + configuration + 15 + 3 + + + TLEN + buffer transfer lengh + 18 + 7 + + + PKE + PacK Enable These bit is set and cleared + by software. If the Source Size is smaller than the + destination, it will be padded according to the PAM + value. If the Source data size is larger than the + destination one, it will be truncated. The alignment + will be done according to the PAM[0] value. This bit + is protected and can be written only if EN is + 0 + 25 + 1 + + + PAM + Padding/Alignement Mode These bits are + set and cleared by software. Case 1: Source data size + smaller than destination data size - 3 options are + valid. Case 2: Source data size larger than + destination data size. The remainder part is + discarded. When PKE = 1 or DSIZE=SSIZE, these bits + are ignored. These bits are protected and can be + written only if EN is 0 + 26 + 2 + + + TRGM + Trigger Mode These bits are set and + cleared by software. Note: If TRGM is 11 for the + current block, all the values loaded at the end of + the current block through the linked list mechanism + must keep the same value (TRGM=11) and the same SWRM + value, otherwise the result is undefined. These bits + are protected and can be written only if EN is + 0. + 28 + 2 + + + SWRM + SW Request Mode This bit is set and + cleared by software. If a HW or SW request is + currently active, the bit change will be delayed + until the current transfer is completed. If the CxMAR + contains a valid address, the CxMDR value will also + be written @ CxMAR address. This bit is protected and + can be written only if EN is 0. + 30 + 1 + + + BWM + Bufferable Write Mode This bit is set + and cleared by software. This bit is protected and + can be written only if EN is 0. Note: All MDMA + destination accesses are non-cacheable. + 31 + 1 + + + + + MDMA_C5BNDTR + MDMA_C5BNDTR + MDMA Channel x block number of data + register + 0x194 + 0x20 + read-write + 0x00000000 + + + BNDT + block number of data to + transfer + 0 + 17 + + + BRSUM + Block Repeat Source address Update Mode + These bits are protected and can be written only if + EN is 0. + 18 + 1 + + + BRDUM + Block Repeat Destination address Update + Mode These bits are protected and can be written only + if EN is 0. + 19 + 1 + + + BRC + Block Repeat Count This field contains + the number of repetitions of the current block (0 to + 4095). When the channel is enabled, this register is + read-only, indicating the remaining number of blocks, + excluding the current one. This register decrements + after each complete block transfer. Once the last + block transfer has completed, this register can + either stay at zero or be reloaded automatically from + memory (in Linked List mode - i.e. Link Address + valid). These bits are protected and can be written + only if EN is 0. + 20 + 12 + + + + + MDMA_C5SAR + MDMA_C5SAR + MDMA channel x source address + register + 0x198 + 0x20 + read-write + 0x00000000 + + + SAR + source adr base + 0 + 32 + + + + + MDMA_C5DAR + MDMA_C5DAR + MDMA channel x destination address + register + 0x19C + 0x20 + read-write + 0x00000000 + + + DAR + Destination adr base + 0 + 32 + + + + + MDMA_C5BRUR + MDMA_C5BRUR + MDMA channel x Block Repeat address Update + register + 0x1A0 + 0x20 + read-write + 0x00000000 + + + SUV + source adresse update + value + 0 + 16 + + + DUV + destination address update + 16 + 16 + + + + + MDMA_C5LAR + MDMA_C5LAR + MDMA channel x Link Address + register + 0x1A4 + 0x20 + read-write + 0x00000000 + + + LAR + Link address register + 0 + 32 + + + + + MDMA_C5TBR + MDMA_C5TBR + MDMA channel x Trigger and Bus selection + Register + 0x1A8 + 0x20 + read-write + 0x00000000 + + + TSEL + Trigger selection + 0 + 6 + + + SBUS + Source BUS select This bit is protected + and can be written only if EN is 0. + 16 + 1 + + + DBUS + Destination BUS slect This bit is + protected and can be written only if EN is + 0. + 17 + 1 + + + + + MDMA_C5MAR + MDMA_C5MAR + MDMA channel x Mask address + register + 0x1B0 + 0x20 + read-write + 0x00000000 + + + MAR + Mask address + 0 + 32 + + + + + MDMA_C5MDR + MDMA_C5MDR + MDMA channel x Mask Data + register + 0x1B4 + 0x20 + read-write + 0x00000000 + + + MDR + Mask data + 0 + 32 + + + + + MDMA_C6ISR + MDMA_C6ISR + MDMA channel x interrupt/status + register + 0x1C0 + 0x20 + read-only + 0x00000000 + + + TEIF6 + Channel x transfer error interrupt flag + This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCRy register. + 0 + 1 + + + CTCIF6 + Channel x Channel Transfer Complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. CTC is set when the + last block was transferred and the channel has been + automatically disabled. CTC is also set when the + channel is suspended, as a result of writing EN bit + to 0. + 1 + 1 + + + BRTIF6 + Channel x block repeat transfer complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. + 2 + 1 + + + BTIF6 + Channel x block transfer complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. + 3 + 1 + + + TCIF6 + channel x buffer transfer + complete + 4 + 1 + + + CRQA6 + channel x request active + flag + 16 + 1 + + + + + MDMA_C6IFCR + MDMA_C6IFCR + MDMA channel x interrupt flag clear + register + 0x1C4 + 0x20 + write-only + 0x00000000 + + + CTEIF6 + Channel x clear transfer error interrupt + flag Writing a 1 into this bit clears TEIFx in the + MDMA_ISRy register + 0 + 1 + + + CCTCIF6 + Clear Channel transfer complete + interrupt flag for channel x Writing a 1 into this + bit clears CTCIFx in the MDMA_ISRy + register + 1 + 1 + + + CBRTIF6 + Channel x clear block repeat transfer + complete interrupt flag Writing a 1 into this bit + clears BRTIFx in the MDMA_ISRy register + 2 + 1 + + + CBTIF6 + Channel x Clear block transfer complete + interrupt flag Writing a 1 into this bit clears BTIFx + in the MDMA_ISRy register + 3 + 1 + + + CLTCIF6 + CLear buffer Transfer Complete Interrupt + Flag for channel x Writing a 1 into this bit clears + TCIFx in the MDMA_ISRy register + 4 + 1 + + + + + MDMA_C6ESR + MDMA_C6ESR + MDMA Channel x error status + register + 0x1C8 + 0x20 + read-only + 0x00000000 + + + TEA + Transfer Error Address These bits are + set and cleared by HW, in case of an MDMA data + transfer error. It is used in conjunction with TED. + This field indicates the 7 LSBits of the address + which generated a transfer/access error. It may be + used by SW to retrieve the failing address, by adding + this value (truncated to the buffer transfer length + size) to the current SAR/DAR value. Note: The SAR/DAR + current value doesnt reflect this last address due to + the FIFO management system. The SAR/DAR are only + updated at the end of a (buffer) transfer (of TLEN+1 + bytes). Note: It is not set in case of a link data + error. + 0 + 7 + + + TED + Transfer Error Direction These bit is + set and cleared by HW, in case of an MDMA data + transfer error. + 7 + 1 + + + TELD + Transfer Error Link Data These bit is + set by HW, in case of a transfer error while reading + the block link data structure. It is cleared by + software writing 1 to the CTEIFx bit in the DMA_IFCRy + register. + 8 + 1 + + + TEMD + Transfer Error Mask Data These bit is + set by HW, in case of a transfer error while writing + the Mask Data. It is cleared by software writing 1 to + the CTEIFx bit in the DMA_IFCRy + register. + 9 + 1 + + + ASE + Address/Size Error These bit is set by + HW, when the programmed address is not aligned with + the data size. TED will indicate whether the problem + is on the source or destination. It is cleared by + software writing 1 to the CTEIFx bit in the DMA_IFCRy + register. + 10 + 1 + + + BSE + Block Size Error These bit is set by HW, + when the block size is not an integer multiple of the + data size either for source or destination. TED will + indicate whether the problem is on the source or + destination. It is cleared by software writing 1 to + the CTEIFx bit in the DMA_IFCRy + register. + 11 + 1 + + + + + MDMA_C6CR + MDMA_C6CR + This register is used to control the + concerned channel. + 0x1CC + 0x20 + 0x00000000 + + + EN + channel enable + 0 + 1 + read-write + + + TEIE + Transfer error interrupt enable This bit + is set and cleared by software. + 1 + 1 + read-write + + + CTCIE + Channel Transfer Complete interrupt + enable This bit is set and cleared by + software. + 2 + 1 + read-write + + + BRTIE + Block Repeat transfer interrupt enable + This bit is set and cleared by + software. + 3 + 1 + read-write + + + BTIE + Block Transfer interrupt enable This bit + is set and cleared by software. + 4 + 1 + read-write + + + TCIE + buffer Transfer Complete interrupt + enable This bit is set and cleared by + software. + 5 + 1 + read-write + + + PL + Priority level These bits are set and + cleared by software. These bits are protected and can + be written only if EN is 0. + 6 + 2 + read-write + + + BEX + byte Endianness exchange + 12 + 1 + read-write + + + HEX + Half word Endianes + exchange + 13 + 1 + read-write + + + WEX + Word Endianness exchange + 14 + 1 + read-write + + + SWRQ + SW ReQuest Writing a 1 into this bit + sets the CRQAx in MDMA_ISRy register, activating the + request on Channel x Note: Either the whole CxCR + register or the 8-bit/16-bit register @ Address + offset: 0x4E + 0x40 chn may be used for SWRQ + activation. In case of a SW request, acknowledge is + not generated (neither HW signal, nor CxMAR write + access). + 16 + 1 + write-only + + + + + MDMA_C6TCR + MDMA_C6TCR + This register is used to configure the + concerned channel. + 0x1D0 + 0x20 + read-write + 0x00000000 + + + SINC + Source increment mode These bits are set + and cleared by software. These bits are protected and + can be written only if EN is 0 Note: When source is + AHB (SBUS=1), SINC = 00 is forbidden. In Linked List + Mode, at the end of a block (single or last block in + repeated block transfer mode), this register will be + loaded from memory (from address given by current + LAR[31:0] + 0x00). + 0 + 2 + + + DINC + Destination increment mode These bits + are set and cleared by software. These bits are + protected and can be written only if EN is 0 Note: + When destination is AHB (DBUS=1), DINC = 00 is + forbidden. + 2 + 2 + + + SSIZE + Source data size These bits are set and + cleared by software. These bits are protected and can + be written only if EN is 0 Note: If a value of 11 is + programmed for the TCM access/AHB port, a transfer + error will occur (TEIF bit set) If SINCOS < + SSIZE and SINC ≠ 00, the result will be + unpredictable. Note: SSIZE = 11 (double-word) is + forbidden when source is TCM/AHB bus + (SBUS=1). + 4 + 2 + + + DSIZE + Destination data size These bits are set + and cleared by software. These bits are protected and + can be written only if EN is 0. Note: If a value of + 11 is programmed for the TCM access/AHB port, a + transfer error will occur (TEIF bit set) If DINCOS + < DSIZE and DINC ≠ 00, the result + will be unpredictable. Note: DSIZE = 11 (double-word) + is forbidden when destination is TCM/AHB bus + (DBUS=1). + 6 + 2 + + + SINCOS + source increment offset + size + 8 + 2 + + + DINCOS + Destination increment + offset + 10 + 2 + + + SBURST + source burst transfer + configuration + 12 + 3 + + + DBURST + Destination burst transfer + configuration + 15 + 3 + + + TLEN + buffer transfer lengh + 18 + 7 + + + PKE + PacK Enable These bit is set and cleared + by software. If the Source Size is smaller than the + destination, it will be padded according to the PAM + value. If the Source data size is larger than the + destination one, it will be truncated. The alignment + will be done according to the PAM[0] value. This bit + is protected and can be written only if EN is + 0 + 25 + 1 + + + PAM + Padding/Alignement Mode These bits are + set and cleared by software. Case 1: Source data size + smaller than destination data size - 3 options are + valid. Case 2: Source data size larger than + destination data size. The remainder part is + discarded. When PKE = 1 or DSIZE=SSIZE, these bits + are ignored. These bits are protected and can be + written only if EN is 0 + 26 + 2 + + + TRGM + Trigger Mode These bits are set and + cleared by software. Note: If TRGM is 11 for the + current block, all the values loaded at the end of + the current block through the linked list mechanism + must keep the same value (TRGM=11) and the same SWRM + value, otherwise the result is undefined. These bits + are protected and can be written only if EN is + 0. + 28 + 2 + + + SWRM + SW Request Mode This bit is set and + cleared by software. If a HW or SW request is + currently active, the bit change will be delayed + until the current transfer is completed. If the CxMAR + contains a valid address, the CxMDR value will also + be written @ CxMAR address. This bit is protected and + can be written only if EN is 0. + 30 + 1 + + + BWM + Bufferable Write Mode This bit is set + and cleared by software. This bit is protected and + can be written only if EN is 0. Note: All MDMA + destination accesses are non-cacheable. + 31 + 1 + + + + + MDMA_C6BNDTR + MDMA_C6BNDTR + MDMA Channel x block number of data + register + 0x1D4 + 0x20 + read-write + 0x00000000 + + + BNDT + block number of data to + transfer + 0 + 17 + + + BRSUM + Block Repeat Source address Update Mode + These bits are protected and can be written only if + EN is 0. + 18 + 1 + + + BRDUM + Block Repeat Destination address Update + Mode These bits are protected and can be written only + if EN is 0. + 19 + 1 + + + BRC + Block Repeat Count This field contains + the number of repetitions of the current block (0 to + 4095). When the channel is enabled, this register is + read-only, indicating the remaining number of blocks, + excluding the current one. This register decrements + after each complete block transfer. Once the last + block transfer has completed, this register can + either stay at zero or be reloaded automatically from + memory (in Linked List mode - i.e. Link Address + valid). These bits are protected and can be written + only if EN is 0 + 20 + 12 + + + + + MDMA_C6SAR + MDMA_C6SAR + MDMA channel x source address + register + 0x1D8 + 0x20 + read-write + 0x00000000 + + + SAR + source adr base + 0 + 32 + + + + + MDMA_C6DAR + MDMA_C6DAR + MDMA channel x destination address + register + 0x1DC + 0x20 + read-write + 0x00000000 + + + DAR + Destination adr base + 0 + 32 + + + + + MDMA_C6BRUR + MDMA_C6BRUR + MDMA channel x Block Repeat address Update + register + 0x1E0 + 0x20 + read-write + 0x00000000 + + + SUV + source adresse update + value + 0 + 16 + + + DUV + destination address update + 16 + 16 + + + + + MDMA_C6LAR + MDMA_C6LAR + MDMA channel x Link Address + register + 0x1E4 + 0x20 + read-write + 0x00000000 + + + LAR + Link address register + 0 + 32 + + + + + MDMA_C6TBR + MDMA_C6TBR + MDMA channel x Trigger and Bus selection + Register + 0x1E8 + 0x20 + read-write + 0x00000000 + + + TSEL + Trigger selection + 0 + 6 + + + SBUS + Source BUS select This bit is protected + and can be written only if EN is 0. + 16 + 1 + + + DBUS + Destination BUS slect This bit is + protected and can be written only if EN is + 0. + 17 + 1 + + + + + MDMA_C6MAR + MDMA_C6MAR + MDMA channel x Mask address + register + 0x1F0 + 0x20 + read-write + 0x00000000 + + + MAR + Mask address + 0 + 32 + + + + + MDMA_C6MDR + MDMA_C6MDR + MDMA channel x Mask Data + register + 0x1F4 + 0x20 + read-write + 0x00000000 + + + MDR + Mask data + 0 + 32 + + + + + MDMA_C7ISR + MDMA_C7ISR + MDMA channel x interrupt/status + register + 0x200 + 0x20 + read-only + 0x00000000 + + + TEIF7 + Channel x transfer error interrupt flag + This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCRy register. + 0 + 1 + + + CTCIF7 + Channel x Channel Transfer Complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. CTC is set when the + last block was transferred and the channel has been + automatically disabled. CTC is also set when the + channel is suspended, as a result of writing EN bit + to 0. + 1 + 1 + + + BRTIF7 + Channel x block repeat transfer complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. + 2 + 1 + + + BTIF7 + Channel x block transfer complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. + 3 + 1 + + + TCIF7 + channel x buffer transfer + complete + 4 + 1 + + + CRQA7 + channel x request active + flag + 16 + 1 + + + + + MDMA_C7IFCR + MDMA_C7IFCR + MDMA channel x interrupt flag clear + register + 0x204 + 0x20 + write-only + 0x00000000 + + + CTEIF7 + Channel x clear transfer error interrupt + flag Writing a 1 into this bit clears TEIFx in the + MDMA_ISRy register + 0 + 1 + + + CCTCIF7 + Clear Channel transfer complete + interrupt flag for channel x Writing a 1 into this + bit clears CTCIFx in the MDMA_ISRy + register + 1 + 1 + + + CBRTIF7 + Channel x clear block repeat transfer + complete interrupt flag Writing a 1 into this bit + clears BRTIFx in the MDMA_ISRy register + 2 + 1 + + + CBTIF7 + Channel x Clear block transfer complete + interrupt flag Writing a 1 into this bit clears BTIFx + in the MDMA_ISRy register + 3 + 1 + + + CLTCIF7 + CLear buffer Transfer Complete Interrupt + Flag for channel x Writing a 1 into this bit clears + TCIFx in the MDMA_ISRy register + 4 + 1 + + + + + MDMA_C7ESR + MDMA_C7ESR + MDMA Channel x error status + register + 0x208 + 0x20 + read-only + 0x00000000 + + + TEA + Transfer Error Address These bits are + set and cleared by HW, in case of an MDMA data + transfer error. It is used in conjunction with TED. + This field indicates the 7 LSBits of the address + which generated a transfer/access error. It may be + used by SW to retrieve the failing address, by adding + this value (truncated to the buffer transfer length + size) to the current SAR/DAR value. Note: The SAR/DAR + current value doesnt reflect this last address due to + the FIFO management system. The SAR/DAR are only + updated at the end of a (buffer) transfer (of TLEN+1 + bytes). Note: It is not set in case of a link data + error. + 0 + 7 + + + TED + Transfer Error Direction These bit is + set and cleared by HW, in case of an MDMA data + transfer error. + 7 + 1 + + + TELD + Transfer Error Link Data These bit is + set by HW, in case of a transfer error while reading + the block link data structure. It is cleared by + software writing 1 to the CTEIFx bit in the DMA_IFCRy + register. + 8 + 1 + + + TEMD + Transfer Error Mask Data These bit is + set by HW, in case of a transfer error while writing + the Mask Data. It is cleared by software writing 1 to + the CTEIFx bit in the DMA_IFCRy + register. + 9 + 1 + + + ASE + Address/Size Error These bit is set by + HW, when the programmed address is not aligned with + the data size. TED will indicate whether the problem + is on the source or destination. It is cleared by + software writing 1 to the CTEIFx bit in the DMA_IFCRy + register. + 10 + 1 + + + BSE + Block Size Error These bit is set by HW, + when the block size is not an integer multiple of the + data size either for source or destination. TED will + indicate whether the problem is on the source or + destination. It is cleared by software writing 1 to + the CTEIFx bit in the DMA_IFCRy + register. + 11 + 1 + + + + + MDMA_C7CR + MDMA_C7CR + This register is used to control the + concerned channel. + 0x20C + 0x20 + 0x00000000 + + + EN + channel enable + 0 + 1 + read-write + + + TEIE + Transfer error interrupt enable This bit + is set and cleared by software. + 1 + 1 + read-write + + + CTCIE + Channel Transfer Complete interrupt + enable This bit is set and cleared by + software. + 2 + 1 + read-write + + + BRTIE + Block Repeat transfer interrupt enable + This bit is set and cleared by + software. + 3 + 1 + read-write + + + BTIE + Block Transfer interrupt enable This bit + is set and cleared by software. + 4 + 1 + read-write + + + TCIE + buffer Transfer Complete interrupt + enable This bit is set and cleared by + software. + 5 + 1 + read-write + + + PL + Priority level These bits are set and + cleared by software. These bits are protected and can + be written only if EN is 0. + 6 + 2 + read-write + + + BEX + byte Endianness exchange + 12 + 1 + read-write + + + HEX + Half word Endianes + exchange + 13 + 1 + read-write + + + WEX + Word Endianness exchange + 14 + 1 + read-write + + + SWRQ + SW ReQuest Writing a 1 into this bit + sets the CRQAx in MDMA_ISRy register, activating the + request on Channel x Note: Either the whole CxCR + register or the 8-bit/16-bit register @ Address + offset: 0x4E + 0x40 chn may be used for SWRQ + activation. In case of a SW request, acknowledge is + not generated (neither HW signal, nor CxMAR write + access). + 16 + 1 + write-only + + + + + MDMA_C7TCR + MDMA_C7TCR + This register is used to configure the + concerned channel. + 0x210 + 0x20 + read-write + 0x00000000 + + + SINC + Source increment mode These bits are set + and cleared by software. These bits are protected and + can be written only if EN is 0 Note: When source is + AHB (SBUS=1), SINC = 00 is forbidden. In Linked List + Mode, at the end of a block (single or last block in + repeated block transfer mode), this register will be + loaded from memory (from address given by current + LAR[31:0] + 0x00). + 0 + 2 + + + DINC + Destination increment mode These bits + are set and cleared by software. These bits are + protected and can be written only if EN is 0 Note: + When destination is AHB (DBUS=1), DINC = 00 is + forbidden. + 2 + 2 + + + SSIZE + Source data size These bits are set and + cleared by software. These bits are protected and can + be written only if EN is 0 Note: If a value of 11 is + programmed for the TCM access/AHB port, a transfer + error will occur (TEIF bit set) If SINCOS < + SSIZE and SINC ≠ 00, the result will be + unpredictable. Note: SSIZE = 11 (double-word) is + forbidden when source is TCM/AHB bus + (SBUS=1). + 4 + 2 + + + DSIZE + Destination data size These bits are set + and cleared by software. These bits are protected and + can be written only if EN is 0. Note: If a value of + 11 is programmed for the TCM access/AHB port, a + transfer error will occur (TEIF bit set) If DINCOS + < DSIZE and DINC ≠ 00, the result + will be unpredictable. Note: DSIZE = 11 (double-word) + is forbidden when destination is TCM/AHB bus + (DBUS=1). + 6 + 2 + + + SINCOS + source increment offset + size + 8 + 2 + + + DINCOS + Destination increment + offset + 10 + 2 + + + SBURST + source burst transfer + configuration + 12 + 3 + + + DBURST + Destination burst transfer + configuration + 15 + 3 + + + TLEN + buffer transfer lengh + 18 + 7 + + + PKE + PacK Enable These bit is set and cleared + by software. If the Source Size is smaller than the + destination, it will be padded according to the PAM + value. If the Source data size is larger than the + destination one, it will be truncated. The alignment + will be done according to the PAM[0] value. This bit + is protected and can be written only if EN is + 0 + 25 + 1 + + + PAM + Padding/Alignement Mode These bits are + set and cleared by software. Case 1: Source data size + smaller than destination data size - 3 options are + valid. Case 2: Source data size larger than + destination data size. The remainder part is + discarded. When PKE = 1 or DSIZE=SSIZE, these bits + are ignored. These bits are protected and can be + written only if EN is 0 + 26 + 2 + + + TRGM + Trigger Mode These bits are set and + cleared by software. Note: If TRGM is 11 for the + current block, all the values loaded at the end of + the current block through the linked list mechanism + must keep the same value (TRGM=11) and the same SWRM + value, otherwise the result is undefined. These bits + are protected and can be written only if EN is + 0. + 28 + 2 + + + SWRM + SW Request Mode This bit is set and + cleared by software. If a HW or SW request is + currently active, the bit change will be delayed + until the current transfer is completed. If the CxMAR + contains a valid address, the CxMDR value will also + be written @ CxMAR address. This bit is protected and + can be written only if EN is 0. + 30 + 1 + + + BWM + Bufferable Write Mode This bit is set + and cleared by software. This bit is protected and + can be written only if EN is 0. Note: All MDMA + destination accesses are non-cacheable. + 31 + 1 + + + + + MDMA_C7BNDTR + MDMA_C7BNDTR + MDMA Channel x block number of data + register + 0x214 + 0x20 + read-write + 0x00000000 + + + BNDT + block number of data to + transfer + 0 + 17 + + + BRSUM + Block Repeat Source address Update Mode + These bits are protected and can be written only if + EN is 0. + 18 + 1 + + + BRDUM + Block Repeat Destination address Update + Mode These bits are protected and can be written only + if EN is 0. + 19 + 1 + + + BRC + Block Repeat Count This field contains + the number of repetitions of the current block (0 to + 4095). When the channel is enabled, this register is + read-only, indicating the remaining number of blocks, + excluding the current one. This register decrements + after each complete block transfer. Once the last + block transfer has completed, this register can + either stay at zero or be reloaded automatically from + memory (in Linked List mode - i.e. Link Address + valid). These bits are protected and can be written + only if EN is 0. + 20 + 12 + + + + + MDMA_C7SAR + MDMA_C7SAR + MDMA channel x source address + register + 0x218 + 0x20 + read-write + 0x00000000 + + + SAR + source adr base + 0 + 32 + + + + + MDMA_C7DAR + MDMA_C7DAR + MDMA channel x destination address + register + 0x21C + 0x20 + read-write + 0x00000000 + + + DAR + Destination adr base + 0 + 32 + + + + + MDMA_C7BRUR + MDMA_C7BRUR + MDMA channel x Block Repeat address Update + register + 0x220 + 0x20 + read-write + 0x00000000 + + + SUV + source adresse update + value + 0 + 16 + + + DUV + destination address update + 16 + 16 + + + + + MDMA_C7LAR + MDMA_C7LAR + MDMA channel x Link Address + register + 0x224 + 0x20 + read-write + 0x00000000 + + + LAR + Link address register + 0 + 32 + + + + + MDMA_C7TBR + MDMA_C7TBR + MDMA channel x Trigger and Bus selection + Register + 0x228 + 0x20 + read-write + 0x00000000 + + + TSEL + Trigger selection + 0 + 6 + + + SBUS + Source BUS select This bit is protected + and can be written only if EN is 0. + 16 + 1 + + + DBUS + Destination BUS slect This bit is + protected and can be written only if EN is + 0. + 17 + 1 + + + + + MDMA_C7MAR + MDMA_C7MAR + MDMA channel x Mask address + register + 0x230 + 0x20 + read-write + 0x00000000 + + + MAR + Mask address + 0 + 32 + + + + + MDMA_C7MDR + MDMA_C7MDR + MDMA channel x Mask Data + register + 0x234 + 0x20 + read-write + 0x00000000 + + + MDR + Mask data + 0 + 32 + + + + + MDMA_C8ISR + MDMA_C8ISR + MDMA channel x interrupt/status + register + 0x240 + 0x20 + read-only + 0x00000000 + + + TEIF8 + Channel x transfer error interrupt flag + This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCRy register. + 0 + 1 + + + CTCIF8 + Channel x Channel Transfer Complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. CTC is set when the + last block was transferred and the channel has been + automatically disabled. CTC is also set when the + channel is suspended, as a result of writing EN bit + to 0. + 1 + 1 + + + BRTIF8 + Channel x block repeat transfer complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. + 2 + 1 + + + BTIF8 + Channel x block transfer complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. + 3 + 1 + + + TCIF8 + channel x buffer transfer + complete + 4 + 1 + + + CRQA8 + channel x request active + flag + 16 + 1 + + + + + MDMA_C8IFCR + MDMA_C8IFCR + MDMA channel x interrupt flag clear + register + 0x244 + 0x20 + write-only + 0x00000000 + + + CTEIF8 + Channel x clear transfer error interrupt + flag Writing a 1 into this bit clears TEIFx in the + MDMA_ISRy register + 0 + 1 + + + CCTCIF8 + Clear Channel transfer complete + interrupt flag for channel x Writing a 1 into this + bit clears CTCIFx in the MDMA_ISRy + register + 1 + 1 + + + CBRTIF8 + Channel x clear block repeat transfer + complete interrupt flag Writing a 1 into this bit + clears BRTIFx in the MDMA_ISRy register + 2 + 1 + + + CBTIF8 + Channel x Clear block transfer complete + interrupt flag Writing a 1 into this bit clears BTIFx + in the MDMA_ISRy register + 3 + 1 + + + CLTCIF8 + CLear buffer Transfer Complete Interrupt + Flag for channel x Writing a 1 into this bit clears + TCIFx in the MDMA_ISRy register + 4 + 1 + + + + + MDMA_C8ESR + MDMA_C8ESR + MDMA Channel x error status + register + 0x248 + 0x20 + read-only + 0x00000000 + + + TEA + Transfer Error Address These bits are + set and cleared by HW, in case of an MDMA data + transfer error. It is used in conjunction with TED. + This field indicates the 7 LSBits of the address + which generated a transfer/access error. It may be + used by SW to retrieve the failing address, by adding + this value (truncated to the buffer transfer length + size) to the current SAR/DAR value. Note: The SAR/DAR + current value doesnt reflect this last address due to + the FIFO management system. The SAR/DAR are only + updated at the end of a (buffer) transfer (of TLEN+1 + bytes). Note: It is not set in case of a link data + error. + 0 + 7 + + + TED + Transfer Error Direction These bit is + set and cleared by HW, in case of an MDMA data + transfer error. + 7 + 1 + + + TELD + Transfer Error Link Data These bit is + set by HW, in case of a transfer error while reading + the block link data structure. It is cleared by + software writing 1 to the CTEIFx bit in the DMA_IFCRy + register. + 8 + 1 + + + TEMD + Transfer Error Mask Data These bit is + set by HW, in case of a transfer error while writing + the Mask Data. It is cleared by software writing 1 to + the CTEIFx bit in the DMA_IFCRy + register. + 9 + 1 + + + ASE + Address/Size Error These bit is set by + HW, when the programmed address is not aligned with + the data size. TED will indicate whether the problem + is on the source or destination. It is cleared by + software writing 1 to the CTEIFx bit in the DMA_IFCRy + register. + 10 + 1 + + + BSE + Block Size Error These bit is set by HW, + when the block size is not an integer multiple of the + data size either for source or destination. TED will + indicate whether the problem is on the source or + destination. It is cleared by software writing 1 to + the CTEIFx bit in the DMA_IFCRy + register. + 11 + 1 + + + + + MDMA_C8CR + MDMA_C8CR + This register is used to control the + concerned channel. + 0x24C + 0x20 + 0x00000000 + + + EN + channel enable + 0 + 1 + read-write + + + TEIE + Transfer error interrupt enable This bit + is set and cleared by software. + 1 + 1 + read-write + + + CTCIE + Channel Transfer Complete interrupt + enable This bit is set and cleared by + software. + 2 + 1 + read-write + + + BRTIE + Block Repeat transfer interrupt enable + This bit is set and cleared by + software. + 3 + 1 + read-write + + + BTIE + Block Transfer interrupt enable This bit + is set and cleared by software. + 4 + 1 + read-write + + + TCIE + buffer Transfer Complete interrupt + enable This bit is set and cleared by + software. + 5 + 1 + read-write + + + PL + Priority level These bits are set and + cleared by software. These bits are protected and can + be written only if EN is 0. + 6 + 2 + read-write + + + BEX + byte Endianness exchange + 12 + 1 + read-write + + + HEX + Half word Endianes + exchange + 13 + 1 + read-write + + + WEX + Word Endianness exchange + 14 + 1 + read-write + + + SWRQ + SW ReQuest Writing a 1 into this bit + sets the CRQAx in MDMA_ISRy register, activating the + request on Channel x Note: Either the whole CxCR + register or the 8-bit/16-bit register @ Address + offset: 0x4E + 0x40 chn may be used for SWRQ + activation. In case of a SW request, acknowledge is + not generated (neither HW signal, nor CxMAR write + access). + 16 + 1 + write-only + + + + + MDMA_C8TCR + MDMA_C8TCR + This register is used to configure the + concerned channel. + 0x250 + 0x20 + read-write + 0x00000000 + + + SINC + Source increment mode These bits are set + and cleared by software. These bits are protected and + can be written only if EN is 0 Note: When source is + AHB (SBUS=1), SINC = 00 is forbidden. In Linked List + Mode, at the end of a block (single or last block in + repeated block transfer mode), this register will be + loaded from memory (from address given by current + LAR[31:0] + 0x00). + 0 + 2 + + + DINC + Destination increment mode These bits + are set and cleared by software. These bits are + protected and can be written only if EN is 0 Note: + When destination is AHB (DBUS=1), DINC = 00 is + forbidden. + 2 + 2 + + + SSIZE + Source data size These bits are set and + cleared by software. These bits are protected and can + be written only if EN is 0 Note: If a value of 11 is + programmed for the TCM access/AHB port, a transfer + error will occur (TEIF bit set) If SINCOS < + SSIZE and SINC ≠ 00, the result will be + unpredictable. Note: SSIZE = 11 (double-word) is + forbidden when source is TCM/AHB bus + (SBUS=1). + 4 + 2 + + + DSIZE + Destination data size These bits are set + and cleared by software. These bits are protected and + can be written only if EN is 0. Note: If a value of + 11 is programmed for the TCM access/AHB port, a + transfer error will occur (TEIF bit set) If DINCOS + < DSIZE and DINC ≠ 00, the result + will be unpredictable. Note: DSIZE = 11 (double-word) + is forbidden when destination is TCM/AHB bus + (DBUS=1). + 6 + 2 + + + SINCOS + source increment offset + size + 8 + 2 + + + DINCOS + Destination increment + offset + 10 + 2 + + + SBURST + source burst transfer + configuration + 12 + 3 + + + DBURST + Destination burst transfer + configuration + 15 + 3 + + + TLEN + buffer transfer lengh + 18 + 7 + + + PKE + PacK Enable These bit is set and cleared + by software. If the Source Size is smaller than the + destination, it will be padded according to the PAM + value. If the Source data size is larger than the + destination one, it will be truncated. The alignment + will be done according to the PAM[0] value. This bit + is protected and can be written only if EN is + 0 + 25 + 1 + + + PAM + Padding/Alignement Mode These bits are + set and cleared by software. Case 1: Source data size + smaller than destination data size - 3 options are + valid. Case 2: Source data size larger than + destination data size. The remainder part is + discarded. When PKE = 1 or DSIZE=SSIZE, these bits + are ignored. These bits are protected and can be + written only if EN is 0 + 26 + 2 + + + TRGM + Trigger Mode These bits are set and + cleared by software. Note: If TRGM is 11 for the + current block, all the values loaded at the end of + the current block through the linked list mechanism + must keep the same value (TRGM=11) and the same SWRM + value, otherwise the result is undefined. These bits + are protected and can be written only if EN is + 0. + 28 + 2 + + + SWRM + SW Request Mode This bit is set and + cleared by software. If a HW or SW request is + currently active, the bit change will be delayed + until the current transfer is completed. If the CxMAR + contains a valid address, the CxMDR value will also + be written @ CxMAR address. This bit is protected and + can be written only if EN is 0. + 30 + 1 + + + BWM + Bufferable Write Mode This bit is set + and cleared by software. This bit is protected and + can be written only if EN is 0. Note: All MDMA + destination accesses are non-cacheable. + 31 + 1 + + + + + MDMA_C8BNDTR + MDMA_C8BNDTR + MDMA Channel x block number of data + register + 0x254 + 0x20 + read-write + 0x00000000 + + + BNDT + block number of data to + transfer + 0 + 17 + + + BRSUM + Block Repeat Source address Update Mode + These bits are protected and can be written only if + EN is 0. + 18 + 1 + + + BRDUM + Block Repeat Destination address Update + Mode These bits are protected and can be written only + if EN is 0. + 19 + 1 + + + BRC + Block Repeat Count This field contains + the number of repetitions of the current block (0 to + 4095). When the channel is enabled, this register is + read-only, indicating the remaining number of blocks, + excluding the current one. This register decrements + after each complete block transfer. Once the last + block transfer has completed, this register can + either stay at zero or be reloaded automatically from + memory (in Linked List mode - i.e. Link Address + valid). These bits are protected and can be written + only if EN is 0. + 20 + 12 + + + + + MDMA_C8SAR + MDMA_C8SAR + MDMA channel x source address + register + 0x258 + 0x20 + read-write + 0x00000000 + + + SAR + source adr base + 0 + 32 + + + + + MDMA_C8DAR + MDMA_C8DAR + MDMA channel x destination address + register + 0x25C + 0x20 + read-write + 0x00000000 + + + DAR + Destination adr base + 0 + 32 + + + + + MDMA_C8BRUR + MDMA_C8BRUR + MDMA channel x Block Repeat address Update + register + 0x260 + 0x20 + read-write + 0x00000000 + + + SUV + source adresse update + value + 0 + 16 + + + DUV + destination address update + 16 + 16 + + + + + MDMA_C8LAR + MDMA_C8LAR + MDMA channel x Link Address + register + 0x264 + 0x20 + read-write + 0x00000000 + + + LAR + Link address register + 0 + 32 + + + + + MDMA_C8TBR + MDMA_C8TBR + MDMA channel x Trigger and Bus selection + Register + 0x268 + 0x20 + read-write + 0x00000000 + + + TSEL + Trigger selection + 0 + 6 + + + SBUS + Source BUS select This bit is protected + and can be written only if EN is 0. + 16 + 1 + + + DBUS + Destination BUS slect This bit is + protected and can be written only if EN is + 0. + 17 + 1 + + + + + MDMA_C8MAR + MDMA_C8MAR + MDMA channel x Mask address + register + 0x270 + 0x20 + read-write + 0x00000000 + + + MAR + Mask address + 0 + 32 + + + + + MDMA_C8MDR + MDMA_C8MDR + MDMA channel x Mask Data + register + 0x274 + 0x20 + read-write + 0x00000000 + + + MDR + Mask data + 0 + 32 + + + + + MDMA_C9ISR + MDMA_C9ISR + MDMA channel x interrupt/status + register + 0x280 + 0x20 + read-only + 0x00000000 + + + TEIF9 + Channel x transfer error interrupt flag + This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCRy register. + 0 + 1 + + + CTCIF9 + Channel x Channel Transfer Complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. CTC is set when the + last block was transferred and the channel has been + automatically disabled. CTC is also set when the + channel is suspended, as a result of writing EN bit + to 0. + 1 + 1 + + + BRTIF9 + Channel x block repeat transfer complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. + 2 + 1 + + + BTIF9 + Channel x block transfer complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. + 3 + 1 + + + TCIF9 + channel x buffer transfer + complete + 4 + 1 + + + CRQA9 + channel x request active + flag + 16 + 1 + + + + + MDMA_C9IFCR + MDMA_C9IFCR + MDMA channel x interrupt flag clear + register + 0x284 + 0x20 + write-only + 0x00000000 + + + CTEIF9 + Channel x clear transfer error interrupt + flag Writing a 1 into this bit clears TEIFx in the + MDMA_ISRy register + 0 + 1 + + + CCTCIF9 + Clear Channel transfer complete + interrupt flag for channel x Writing a 1 into this + bit clears CTCIFx in the MDMA_ISRy + register + 1 + 1 + + + CBRTIF9 + Channel x clear block repeat transfer + complete interrupt flag Writing a 1 into this bit + clears BRTIFx in the MDMA_ISRy register + 2 + 1 + + + CBTIF9 + Channel x Clear block transfer complete + interrupt flag Writing a 1 into this bit clears BTIFx + in the MDMA_ISRy register + 3 + 1 + + + CLTCIF9 + CLear buffer Transfer Complete Interrupt + Flag for channel x Writing a 1 into this bit clears + TCIFx in the MDMA_ISRy register + 4 + 1 + + + + + MDMA_C9ESR + MDMA_C9ESR + MDMA Channel x error status + register + 0x288 + 0x20 + read-only + 0x00000000 + + + TEA + Transfer Error Address These bits are + set and cleared by HW, in case of an MDMA data + transfer error. It is used in conjunction with TED. + This field indicates the 7 LSBits of the address + which generated a transfer/access error. It may be + used by SW to retrieve the failing address, by adding + this value (truncated to the buffer transfer length + size) to the current SAR/DAR value. Note: The SAR/DAR + current value doesnt reflect this last address due to + the FIFO management system. The SAR/DAR are only + updated at the end of a (buffer) transfer (of TLEN+1 + bytes). Note: It is not set in case of a link data + error. + 0 + 7 + + + TED + Transfer Error Direction These bit is + set and cleared by HW, in case of an MDMA data + transfer error. + 7 + 1 + + + TELD + Transfer Error Link Data These bit is + set by HW, in case of a transfer error while reading + the block link data structure. It is cleared by + software writing 1 to the CTEIFx bit in the DMA_IFCRy + register. + 8 + 1 + + + TEMD + Transfer Error Mask Data These bit is + set by HW, in case of a transfer error while writing + the Mask Data. It is cleared by software writing 1 to + the CTEIFx bit in the DMA_IFCRy + register. + 9 + 1 + + + ASE + Address/Size Error These bit is set by + HW, when the programmed address is not aligned with + the data size. TED will indicate whether the problem + is on the source or destination. It is cleared by + software writing 1 to the CTEIFx bit in the DMA_IFCRy + register. + 10 + 1 + + + BSE + Block Size Error These bit is set by HW, + when the block size is not an integer multiple of the + data size either for source or destination. TED will + indicate whether the problem is on the source or + destination. It is cleared by software writing 1 to + the CTEIFx bit in the DMA_IFCRy + register. + 11 + 1 + + + + + MDMA_C9CR + MDMA_C9CR + This register is used to control the + concerned channel. + 0x28C + 0x20 + 0x00000000 + + + EN + channel enable + 0 + 1 + read-write + + + TEIE + Transfer error interrupt enable This bit + is set and cleared by software. + 1 + 1 + read-write + + + CTCIE + Channel Transfer Complete interrupt + enable This bit is set and cleared by + software. + 2 + 1 + read-write + + + BRTIE + Block Repeat transfer interrupt enable + This bit is set and cleared by + software. + 3 + 1 + read-write + + + BTIE + Block Transfer interrupt enable This bit + is set and cleared by software. + 4 + 1 + read-write + + + TCIE + buffer Transfer Complete interrupt + enable This bit is set and cleared by + software. + 5 + 1 + read-write + + + PL + Priority level These bits are set and + cleared by software. These bits are protected and can + be written only if EN is 0. + 6 + 2 + read-write + + + BEX + byte Endianness exchange + 12 + 1 + read-write + + + HEX + Half word Endianes + exchange + 13 + 1 + read-write + + + WEX + Word Endianness exchange + 14 + 1 + read-write + + + SWRQ + SW ReQuest Writing a 1 into this bit + sets the CRQAx in MDMA_ISRy register, activating the + request on Channel x Note: Either the whole CxCR + register or the 8-bit/16-bit register @ Address + offset: 0x4E + 0x40 chn may be used for SWRQ + activation. In case of a SW request, acknowledge is + not generated (neither HW signal, nor CxMAR write + access). + 16 + 1 + write-only + + + + + MDMA_C9TCR + MDMA_C9TCR + This register is used to configure the + concerned channel. + 0x290 + 0x20 + read-write + 0x00000000 + + + SINC + Source increment mode These bits are set + and cleared by software. These bits are protected and + can be written only if EN is 0 Note: When source is + AHB (SBUS=1), SINC = 00 is forbidden. In Linked List + Mode, at the end of a block (single or last block in + repeated block transfer mode), this register will be + loaded from memory (from address given by current + LAR[31:0] + 0x00). + 0 + 2 + + + DINC + Destination increment mode These bits + are set and cleared by software. These bits are + protected and can be written only if EN is 0 Note: + When destination is AHB (DBUS=1), DINC = 00 is + forbidden. + 2 + 2 + + + SSIZE + Source data size These bits are set and + cleared by software. These bits are protected and can + be written only if EN is 0 Note: If a value of 11 is + programmed for the TCM access/AHB port, a transfer + error will occur (TEIF bit set) If SINCOS < + SSIZE and SINC ≠ 00, the result will be + unpredictable. Note: SSIZE = 11 (double-word) is + forbidden when source is TCM/AHB bus + (SBUS=1). + 4 + 2 + + + DSIZE + Destination data size These bits are set + and cleared by software. These bits are protected and + can be written only if EN is 0. Note: If a value of + 11 is programmed for the TCM access/AHB port, a + transfer error will occur (TEIF bit set) If DINCOS + < DSIZE and DINC ≠ 00, the result + will be unpredictable. Note: DSIZE = 11 (double-word) + is forbidden when destination is TCM/AHB bus + (DBUS=1). + 6 + 2 + + + SINCOS + source increment offset + size + 8 + 2 + + + DINCOS + Destination increment + offset + 10 + 2 + + + SBURST + source burst transfer + configuration + 12 + 3 + + + DBURST + Destination burst transfer + configuration + 15 + 3 + + + TLEN + buffer transfer lengh + 18 + 7 + + + PKE + PacK Enable These bit is set and cleared + by software. If the Source Size is smaller than the + destination, it will be padded according to the PAM + value. If the Source data size is larger than the + destination one, it will be truncated. The alignment + will be done according to the PAM[0] value. This bit + is protected and can be written only if EN is + 0 + 25 + 1 + + + PAM + Padding/Alignement Mode These bits are + set and cleared by software. Case 1: Source data size + smaller than destination data size - 3 options are + valid. Case 2: Source data size larger than + destination data size. The remainder part is + discarded. When PKE = 1 or DSIZE=SSIZE, these bits + are ignored. These bits are protected and can be + written only if EN is 0 + 26 + 2 + + + TRGM + Trigger Mode These bits are set and + cleared by software. Note: If TRGM is 11 for the + current block, all the values loaded at the end of + the current block through the linked list mechanism + must keep the same value (TRGM=11) and the same SWRM + value, otherwise the result is undefined. These bits + are protected and can be written only if EN is + 0. + 28 + 2 + + + SWRM + SW Request Mode This bit is set and + cleared by software. If a HW or SW request is + currently active, the bit change will be delayed + until the current transfer is completed. If the CxMAR + contains a valid address, the CxMDR value will also + be written @ CxMAR address. This bit is protected and + can be written only if EN is 0. + 30 + 1 + + + BWM + Bufferable Write Mode This bit is set + and cleared by software. This bit is protected and + can be written only if EN is 0. Note: All MDMA + destination accesses are non-cacheable. + 31 + 1 + + + + + MDMA_C9BNDTR + MDMA_C9BNDTR + MDMA Channel x block number of data + register + 0x294 + 0x20 + read-write + 0x00000000 + + + BNDT + block number of data to + transfer + 0 + 17 + + + BRSUM + Block Repeat Source address Update Mode + These bits are protected and can be written only if + EN is 0. + 18 + 1 + + + BRDUM + Block Repeat Destination address Update + Mode These bits are protected and can be written only + if EN is 0. + 19 + 1 + + + BRC + Block Repeat Count This field contains + the number of repetitions of the current block (0 to + 4095). When the channel is enabled, this register is + read-only, indicating the remaining number of blocks, + excluding the current one. This register decrements + after each complete block transfer. Once the last + block transfer has completed, this register can + either stay at zero or be reloaded automatically from + memory (in Linked List mode - i.e. Link Address + valid). These bits are protected and can be written + only if EN is 0. + 20 + 12 + + + + + MDMA_C9SAR + MDMA_C9SAR + MDMA channel x source address + register + 0x298 + 0x20 + read-write + 0x00000000 + + + SAR + source adr base + 0 + 32 + + + + + MDMA_C9DAR + MDMA_C9DAR + MDMA channel x destination address + register + 0x29C + 0x20 + read-write + 0x00000000 + + + DAR + Destination adr base + 0 + 32 + + + + + MDMA_C9BRUR + MDMA_C9BRUR + MDMA channel x Block Repeat address Update + register + 0x2A0 + 0x20 + read-write + 0x00000000 + + + SUV + source adresse update + value + 0 + 16 + + + DUV + destination address update + 16 + 16 + + + + + MDMA_C9LAR + MDMA_C9LAR + MDMA channel x Link Address + register + 0x2A4 + 0x20 + read-write + 0x00000000 + + + LAR + Link address register + 0 + 32 + + + + + MDMA_C9TBR + MDMA_C9TBR + MDMA channel x Trigger and Bus selection + Register + 0x2A8 + 0x20 + read-write + 0x00000000 + + + TSEL + Trigger selection + 0 + 6 + + + SBUS + Source BUS select This bit is protected + and can be written only if EN is 0. + 16 + 1 + + + DBUS + Destination BUS slect This bit is + protected and can be written only if EN is + 0. + 17 + 1 + + + + + MDMA_C9MAR + MDMA_C9MAR + MDMA channel x Mask address + register + 0x2B0 + 0x20 + read-write + 0x00000000 + + + MAR + Mask address + 0 + 32 + + + + + MDMA_C9MDR + MDMA_C9MDR + MDMA channel x Mask Data + register + 0x2B4 + 0x20 + read-write + 0x00000000 + + + MDR + Mask data + 0 + 32 + + + + + MDMA_C10ISR + MDMA_C10ISR + MDMA channel x interrupt/status + register + 0x2C0 + 0x20 + read-only + 0x00000000 + + + TEIF10 + Channel x transfer error interrupt flag + This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCRy register. + 0 + 1 + + + CTCIF10 + Channel x Channel Transfer Complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. CTC is set when the + last block was transferred and the channel has been + automatically disabled. CTC is also set when the + channel is suspended, as a result of writing EN bit + to 0. + 1 + 1 + + + BRTIF10 + Channel x block repeat transfer complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. + 2 + 1 + + + BTIF10 + Channel x block transfer complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. + 3 + 1 + + + TCIF10 + channel x buffer transfer + complete + 4 + 1 + + + CRQA10 + channel x request active + flag + 16 + 1 + + + + + MDMA_C10IFCR + MDMA_C10IFCR + MDMA channel x interrupt flag clear + register + 0x2C4 + 0x20 + write-only + 0x00000000 + + + CTEIF10 + Channel x clear transfer error interrupt + flag Writing a 1 into this bit clears TEIFx in the + MDMA_ISRy register + 0 + 1 + + + CCTCIF10 + Clear Channel transfer complete + interrupt flag for channel x Writing a 1 into this + bit clears CTCIFx in the MDMA_ISRy + register + 1 + 1 + + + CBRTIF10 + Channel x clear block repeat transfer + complete interrupt flag Writing a 1 into this bit + clears BRTIFx in the MDMA_ISRy register + 2 + 1 + + + CBTIF10 + Channel x Clear block transfer complete + interrupt flag Writing a 1 into this bit clears BTIFx + in the MDMA_ISRy register + 3 + 1 + + + CLTCIF10 + CLear buffer Transfer Complete Interrupt + Flag for channel x Writing a 1 into this bit clears + TCIFx in the MDMA_ISRy register + 4 + 1 + + + + + MDMA_C10ESR + MDMA_C10ESR + MDMA Channel x error status + register + 0x2C8 + 0x20 + read-only + 0x00000000 + + + TEA + Transfer Error Address These bits are + set and cleared by HW, in case of an MDMA data + transfer error. It is used in conjunction with TED. + This field indicates the 7 LSBits of the address + which generated a transfer/access error. It may be + used by SW to retrieve the failing address, by adding + this value (truncated to the buffer transfer length + size) to the current SAR/DAR value. Note: The SAR/DAR + current value doesnt reflect this last address due to + the FIFO management system. The SAR/DAR are only + updated at the end of a (buffer) transfer (of TLEN+1 + bytes). Note: It is not set in case of a link data + error. + 0 + 7 + + + TED + Transfer Error Direction These bit is + set and cleared by HW, in case of an MDMA data + transfer error. + 7 + 1 + + + TELD + Transfer Error Link Data These bit is + set by HW, in case of a transfer error while reading + the block link data structure. It is cleared by + software writing 1 to the CTEIFx bit in the DMA_IFCRy + register. + 8 + 1 + + + TEMD + Transfer Error Mask Data These bit is + set by HW, in case of a transfer error while writing + the Mask Data. It is cleared by software writing 1 to + the CTEIFx bit in the DMA_IFCRy + register. + 9 + 1 + + + ASE + Address/Size Error These bit is set by + HW, when the programmed address is not aligned with + the data size. TED will indicate whether the problem + is on the source or destination. It is cleared by + software writing 1 to the CTEIFx bit in the DMA_IFCRy + register. + 10 + 1 + + + BSE + Block Size Error These bit is set by HW, + when the block size is not an integer multiple of the + data size either for source or destination. TED will + indicate whether the problem is on the source or + destination. It is cleared by software writing 1 to + the CTEIFx bit in the DMA_IFCRy + register. + 11 + 1 + + + + + MDMA_C10CR + MDMA_C10CR + This register is used to control the + concerned channel. + 0x2CC + 0x20 + 0x00000000 + + + EN + channel enable + 0 + 1 + read-write + + + TEIE + Transfer error interrupt enable This bit + is set and cleared by software. + 1 + 1 + read-write + + + CTCIE + Channel Transfer Complete interrupt + enable This bit is set and cleared by + software. + 2 + 1 + read-write + + + BRTIE + Block Repeat transfer interrupt enable + This bit is set and cleared by + software. + 3 + 1 + read-write + + + BTIE + Block Transfer interrupt enable This bit + is set and cleared by software. + 4 + 1 + read-write + + + TCIE + buffer Transfer Complete interrupt + enable This bit is set and cleared by + software. + 5 + 1 + read-write + + + PL + Priority level These bits are set and + cleared by software. These bits are protected and can + be written only if EN is 0. + 6 + 2 + read-write + + + BEX + byte Endianness exchange + 12 + 1 + read-write + + + HEX + Half word Endianes + exchange + 13 + 1 + read-write + + + WEX + Word Endianness exchange + 14 + 1 + read-write + + + SWRQ + SW ReQuest Writing a 1 into this bit + sets the CRQAx in MDMA_ISRy register, activating the + request on Channel x Note: Either the whole CxCR + register or the 8-bit/16-bit register @ Address + offset: 0x4E + 0x40 chn may be used for SWRQ + activation. In case of a SW request, acknowledge is + not generated (neither HW signal, nor CxMAR write + access). + 16 + 1 + write-only + + + + + MDMA_C10TCR + MDMA_C10TCR + This register is used to configure the + concerned channel. + 0x2D0 + 0x20 + read-write + 0x00000000 + + + SINC + Source increment mode These bits are set + and cleared by software. These bits are protected and + can be written only if EN is 0 Note: When source is + AHB (SBUS=1), SINC = 00 is forbidden. In Linked List + Mode, at the end of a block (single or last block in + repeated block transfer mode), this register will be + loaded from memory (from address given by current + LAR[31:0] + 0x00). + 0 + 2 + + + DINC + Destination increment mode These bits + are set and cleared by software. These bits are + protected and can be written only if EN is 0 Note: + When destination is AHB (DBUS=1), DINC = 00 is + forbidden. + 2 + 2 + + + SSIZE + Source data size These bits are set and + cleared by software. These bits are protected and can + be written only if EN is 0 Note: If a value of 11 is + programmed for the TCM access/AHB port, a transfer + error will occur (TEIF bit set) If SINCOS < + SSIZE and SINC ≠ 00, the result will be + unpredictable. Note: SSIZE = 11 (double-word) is + forbidden when source is TCM/AHB bus + (SBUS=1). + 4 + 2 + + + DSIZE + Destination data size These bits are set + and cleared by software. These bits are protected and + can be written only if EN is 0. Note: If a value of + 11 is programmed for the TCM access/AHB port, a + transfer error will occur (TEIF bit set) If DINCOS + < DSIZE and DINC ≠ 00, the result + will be unpredictable. Note: DSIZE = 11 (double-word) + is forbidden when destination is TCM/AHB bus + (DBUS=1). + 6 + 2 + + + SINCOS + source increment offset + size + 8 + 2 + + + DINCOS + Destination increment + offset + 10 + 2 + + + SBURST + source burst transfer + configuration + 12 + 3 + + + DBURST + Destination burst transfer + configuration + 15 + 3 + + + TLEN + buffer transfer lengh + 18 + 7 + + + PKE + PacK Enable These bit is set and cleared + by software. If the Source Size is smaller than the + destination, it will be padded according to the PAM + value. If the Source data size is larger than the + destination one, it will be truncated. The alignment + will be done according to the PAM[0] value. This bit + is protected and can be written only if EN is + 0 + 25 + 1 + + + PAM + Padding/Alignement Mode These bits are + set and cleared by software. Case 1: Source data size + smaller than destination data size - 3 options are + valid. Case 2: Source data size larger than + destination data size. The remainder part is + discarded. When PKE = 1 or DSIZE=SSIZE, these bits + are ignored. These bits are protected and can be + written only if EN is 0 + 26 + 2 + + + TRGM + Trigger Mode These bits are set and + cleared by software. Note: If TRGM is 11 for the + current block, all the values loaded at the end of + the current block through the linked list mechanism + must keep the same value (TRGM=11) and the same SWRM + value, otherwise the result is undefined. These bits + are protected and can be written only if EN is + 0. + 28 + 2 + + + SWRM + SW Request Mode This bit is set and + cleared by software. If a HW or SW request is + currently active, the bit change will be delayed + until the current transfer is completed. If the CxMAR + contains a valid address, the CxMDR value will also + be written @ CxMAR address. This bit is protected and + can be written only if EN is 0. + 30 + 1 + + + BWM + Bufferable Write Mode This bit is set + and cleared by software. This bit is protected and + can be written only if EN is 0. Note: All MDMA + destination accesses are non-cacheable. + 31 + 1 + + + + + MDMA_C10BNDTR + MDMA_C10BNDTR + MDMA Channel x block number of data + register + 0x2D4 + 0x20 + read-write + 0x00000000 + + + BNDT + block number of data to + transfer + 0 + 17 + + + BRSUM + Block Repeat Source address Update Mode + These bits are protected and can be written only if + EN is 0. + 18 + 1 + + + BRDUM + Block Repeat Destination address Update + Mode These bits are protected and can be written only + if EN is 0. + 19 + 1 + + + BRC + Block Repeat Count This field contains + the number of repetitions of the current block (0 to + 4095). When the channel is enabled, this register is + read-only, indicating the remaining number of blocks, + excluding the current one. This register decrements + after each complete block transfer. Once the last + block transfer has completed, this register can + either stay at zero or be reloaded automatically from + memory (in Linked List mode - i.e. Link Address + valid). These bits are protected and can be written + only if EN is 0. + 20 + 12 + + + + + MDMA_C10SAR + MDMA_C10SAR + MDMA channel x source address + register + 0x2D8 + 0x20 + read-write + 0x00000000 + + + SAR + source adr base + 0 + 32 + + + + + MDMA_C10DAR + MDMA_C10DAR + MDMA channel x destination address + register + 0x2DC + 0x20 + read-write + 0x00000000 + + + DAR + Destination adr base + 0 + 32 + + + + + MDMA_C10BRUR + MDMA_C10BRUR + MDMA channel x Block Repeat address Update + register + 0x2E0 + 0x20 + read-write + 0x00000000 + + + SUV + source adresse update + value + 0 + 16 + + + DUV + destination address update + 16 + 16 + + + + + MDMA_C10LAR + MDMA_C10LAR + MDMA channel x Link Address + register + 0x2E4 + 0x20 + read-write + 0x00000000 + + + LAR + Link address register + 0 + 32 + + + + + MDMA_C10TBR + MDMA_C10TBR + MDMA channel x Trigger and Bus selection + Register + 0x2E8 + 0x20 + read-write + 0x00000000 + + + TSEL + Trigger selection + 0 + 6 + + + SBUS + Source BUS select This bit is protected + and can be written only if EN is 0. + 16 + 1 + + + DBUS + Destination BUS slect This bit is + protected and can be written only if EN is + 0. + 17 + 1 + + + + + MDMA_C10MAR + MDMA_C10MAR + MDMA channel x Mask address + register + 0x2F0 + 0x20 + read-write + 0x00000000 + + + MAR + Mask address + 0 + 32 + + + + + MDMA_C10MDR + MDMA_C10MDR + MDMA channel x Mask Data + register + 0x2F4 + 0x20 + read-write + 0x00000000 + + + MDR + Mask data + 0 + 32 + + + + + MDMA_C11ISR + MDMA_C11ISR + MDMA channel x interrupt/status + register + 0x300 + 0x20 + read-only + 0x00000000 + + + TEIF11 + Channel x transfer error interrupt flag + This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCRy register. + 0 + 1 + + + CTCIF11 + Channel x Channel Transfer Complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. CTC is set when the + last block was transferred and the channel has been + automatically disabled. CTC is also set when the + channel is suspended, as a result of writing EN bit + to 0. + 1 + 1 + + + BRTIF11 + Channel x block repeat transfer complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. + 2 + 1 + + + BTIF11 + Channel x block transfer complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. + 3 + 1 + + + TCIF11 + channel x buffer transfer + complete + 4 + 1 + + + CRQA11 + channel x request active + flag + 16 + 1 + + + + + MDMA_C11IFCR + MDMA_C11IFCR + MDMA channel x interrupt flag clear + register + 0x304 + 0x20 + write-only + 0x00000000 + + + CTEIF11 + Channel x clear transfer error interrupt + flag Writing a 1 into this bit clears TEIFx in the + MDMA_ISRy register + 0 + 1 + + + CCTCIF11 + Clear Channel transfer complete + interrupt flag for channel x Writing a 1 into this + bit clears CTCIFx in the MDMA_ISRy + register + 1 + 1 + + + CBRTIF11 + Channel x clear block repeat transfer + complete interrupt flag Writing a 1 into this bit + clears BRTIFx in the MDMA_ISRy register + 2 + 1 + + + CBTIF11 + Channel x Clear block transfer complete + interrupt flag Writing a 1 into this bit clears BTIFx + in the MDMA_ISRy register + 3 + 1 + + + CLTCIF11 + CLear buffer Transfer Complete Interrupt + Flag for channel x Writing a 1 into this bit clears + TCIFx in the MDMA_ISRy register + 4 + 1 + + + + + MDMA_C11ESR + MDMA_C11ESR + MDMA Channel x error status + register + 0x308 + 0x20 + read-only + 0x00000000 + + + TEA + Transfer Error Address These bits are + set and cleared by HW, in case of an MDMA data + transfer error. It is used in conjunction with TED. + This field indicates the 7 LSBits of the address + which generated a transfer/access error. It may be + used by SW to retrieve the failing address, by adding + this value (truncated to the buffer transfer length + size) to the current SAR/DAR value. Note: The SAR/DAR + current value doesnt reflect this last address due to + the FIFO management system. The SAR/DAR are only + updated at the end of a (buffer) transfer (of TLEN+1 + bytes). Note: It is not set in case of a link data + error. + 0 + 7 + + + TED + Transfer Error Direction These bit is + set and cleared by HW, in case of an MDMA data + transfer error. + 7 + 1 + + + TELD + Transfer Error Link Data These bit is + set by HW, in case of a transfer error while reading + the block link data structure. It is cleared by + software writing 1 to the CTEIFx bit in the DMA_IFCRy + register. + 8 + 1 + + + TEMD + Transfer Error Mask Data These bit is + set by HW, in case of a transfer error while writing + the Mask Data. It is cleared by software writing 1 to + the CTEIFx bit in the DMA_IFCRy + register. + 9 + 1 + + + ASE + Address/Size Error These bit is set by + HW, when the programmed address is not aligned with + the data size. TED will indicate whether the problem + is on the source or destination. It is cleared by + software writing 1 to the CTEIFx bit in the DMA_IFCRy + register. + 10 + 1 + + + BSE + Block Size Error These bit is set by HW, + when the block size is not an integer multiple of the + data size either for source or destination. TED will + indicate whether the problem is on the source or + destination. It is cleared by software writing 1 to + the CTEIFx bit in the DMA_IFCRy + register. + 11 + 1 + + + + + MDMA_C11CR + MDMA_C11CR + This register is used to control the + concerned channel. + 0x30C + 0x20 + 0x00000000 + + + EN + channel enable + 0 + 1 + read-write + + + TEIE + Transfer error interrupt enable This bit + is set and cleared by software. + 1 + 1 + read-write + + + CTCIE + Channel Transfer Complete interrupt + enable This bit is set and cleared by + software. + 2 + 1 + read-write + + + BRTIE + Block Repeat transfer interrupt enable + This bit is set and cleared by + software. + 3 + 1 + read-write + + + BTIE + Block Transfer interrupt enable This bit + is set and cleared by software. + 4 + 1 + read-write + + + TCIE + buffer Transfer Complete interrupt + enable This bit is set and cleared by + software. + 5 + 1 + read-write + + + PL + Priority level These bits are set and + cleared by software. These bits are protected and can + be written only if EN is 0. + 6 + 2 + read-write + + + BEX + byte Endianness exchange + 12 + 1 + read-write + + + HEX + Half word Endianes + exchange + 13 + 1 + read-write + + + WEX + Word Endianness exchange + 14 + 1 + read-write + + + SWRQ + SW ReQuest Writing a 1 into this bit + sets the CRQAx in MDMA_ISRy register, activating the + request on Channel x Note: Either the whole CxCR + register or the 8-bit/16-bit register @ Address + offset: 0x4E + 0x40 chn may be used for SWRQ + activation. In case of a SW request, acknowledge is + not generated (neither HW signal, nor CxMAR write + access). + 16 + 1 + write-only + + + + + MDMA_C11TCR + MDMA_C11TCR + This register is used to configure the + concerned channel. + 0x310 + 0x20 + read-write + 0x00000000 + + + SINC + Source increment mode These bits are set + and cleared by software. These bits are protected and + can be written only if EN is 0 Note: When source is + AHB (SBUS=1), SINC = 00 is forbidden. In Linked List + Mode, at the end of a block (single or last block in + repeated block transfer mode), this register will be + loaded from memory (from address given by current + LAR[31:0] + 0x00). + 0 + 2 + + + DINC + Destination increment mode These bits + are set and cleared by software. These bits are + protected and can be written only if EN is 0 Note: + When destination is AHB (DBUS=1), DINC = 00 is + forbidden. + 2 + 2 + + + SSIZE + Source data size These bits are set and + cleared by software. These bits are protected and can + be written only if EN is 0 Note: If a value of 11 is + programmed for the TCM access/AHB port, a transfer + error will occur (TEIF bit set) If SINCOS < + SSIZE and SINC ≠ 00, the result will be + unpredictable. Note: SSIZE = 11 (double-word) is + forbidden when source is TCM/AHB bus + (SBUS=1). + 4 + 2 + + + DSIZE + Destination data size These bits are set + and cleared by software. These bits are protected and + can be written only if EN is 0. Note: If a value of + 11 is programmed for the TCM access/AHB port, a + transfer error will occur (TEIF bit set) If DINCOS + < DSIZE and DINC ≠ 00, the result + will be unpredictable. Note: DSIZE = 11 (double-word) + is forbidden when destination is TCM/AHB bus + (DBUS=1). + 6 + 2 + + + SINCOS + source increment offset + size + 8 + 2 + + + DINCOS + Destination increment + offset + 10 + 2 + + + SBURST + source burst transfer + configuration + 12 + 3 + + + DBURST + Destination burst transfer + configuration + 15 + 3 + + + TLEN + buffer transfer lengh + 18 + 7 + + + PKE + PacK Enable These bit is set and cleared + by software. If the Source Size is smaller than the + destination, it will be padded according to the PAM + value. If the Source data size is larger than the + destination one, it will be truncated. The alignment + will be done according to the PAM[0] value. This bit + is protected and can be written only if EN is + 0 + 25 + 1 + + + PAM + Padding/Alignement Mode These bits are + set and cleared by software. Case 1: Source data size + smaller than destination data size - 3 options are + valid. Case 2: Source data size larger than + destination data size. The remainder part is + discarded. When PKE = 1 or DSIZE=SSIZE, these bits + are ignored. These bits are protected and can be + written only if EN is 0 + 26 + 2 + + + TRGM + Trigger Mode These bits are set and + cleared by software. Note: If TRGM is 11 for the + current block, all the values loaded at the end of + the current block through the linked list mechanism + must keep the same value (TRGM=11) and the same SWRM + value, otherwise the result is undefined. These bits + are protected and can be written only if EN is + 0. + 28 + 2 + + + SWRM + SW Request Mode This bit is set and + cleared by software. If a HW or SW request is + currently active, the bit change will be delayed + until the current transfer is completed. If the CxMAR + contains a valid address, the CxMDR value will also + be written @ CxMAR address. This bit is protected and + can be written only if EN is 0. + 30 + 1 + + + BWM + Bufferable Write Mode This bit is set + and cleared by software. This bit is protected and + can be written only if EN is 0. Note: All MDMA + destination accesses are non-cacheable. + 31 + 1 + + + + + MDMA_C11BNDTR + MDMA_C11BNDTR + MDMA Channel x block number of data + register + 0x314 + 0x20 + read-write + 0x00000000 + + + BNDT + block number of data to + transfer + 0 + 17 + + + BRSUM + Block Repeat Source address Update Mode + These bits are protected and can be written only if + EN is 0. + 18 + 1 + + + BRDUM + Block Repeat Destination address Update + Mode These bits are protected and can be written only + if EN is 0. + 19 + 1 + + + BRC + Block Repeat Count This field contains + the number of repetitions of the current block (0 to + 4095). When the channel is enabled, this register is + read-only, indicating the remaining number of blocks, + excluding the current one. This register decrements + after each complete block transfer. Once the last + block transfer has completed, this register can + either stay at zero or be reloaded automatically from + memory (in Linked List mode - i.e. Link Address + valid). These bits are protected and can be written + only if EN is 0. + 20 + 12 + + + + + MDMA_C11SAR + MDMA_C11SAR + MDMA channel x source address + register + 0x318 + 0x20 + read-write + 0x00000000 + + + SAR + source adr base + 0 + 32 + + + + + MDMA_C11DAR + MDMA_C11DAR + MDMA channel x destination address + register + 0x31C + 0x20 + read-write + 0x00000000 + + + DAR + Destination adr base + 0 + 32 + + + + + MDMA_C11BRUR + MDMA_C11BRUR + MDMA channel x Block Repeat address Update + register + 0x320 + 0x20 + read-write + 0x00000000 + + + SUV + source adresse update + value + 0 + 16 + + + DUV + destination address update + 16 + 16 + + + + + MDMA_C11LAR + MDMA_C11LAR + MDMA channel x Link Address + register + 0x324 + 0x20 + read-write + 0x00000000 + + + LAR + Link address register + 0 + 32 + + + + + MDMA_C11TBR + MDMA_C11TBR + MDMA channel x Trigger and Bus selection + Register + 0x328 + 0x20 + read-write + 0x00000000 + + + TSEL + Trigger selection + 0 + 6 + + + SBUS + Source BUS select This bit is protected + and can be written only if EN is 0. + 16 + 1 + + + DBUS + Destination BUS slect This bit is + protected and can be written only if EN is + 0. + 17 + 1 + + + + + MDMA_C11MAR + MDMA_C11MAR + MDMA channel x Mask address + register + 0x330 + 0x20 + read-write + 0x00000000 + + + MAR + Mask address + 0 + 32 + + + + + MDMA_C11MDR + MDMA_C11MDR + MDMA channel x Mask Data + register + 0x334 + 0x20 + read-write + 0x00000000 + + + MDR + Mask data + 0 + 32 + + + + + MDMA_C12ISR + MDMA_C12ISR + MDMA channel x interrupt/status + register + 0x340 + 0x20 + read-only + 0x00000000 + + + TEIF12 + Channel x transfer error interrupt flag + This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCRy register. + 0 + 1 + + + CTCIF12 + Channel x Channel Transfer Complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. CTC is set when the + last block was transferred and the channel has been + automatically disabled. CTC is also set when the + channel is suspended, as a result of writing EN bit + to 0. + 1 + 1 + + + BRTIF12 + Channel x block repeat transfer complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. + 2 + 1 + + + BTIF12 + Channel x block transfer complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. + 3 + 1 + + + TCIF12 + channel x buffer transfer + complete + 4 + 1 + + + CRQA12 + channel x request active + flag + 16 + 1 + + + + + MDMA_C12IFCR + MDMA_C12IFCR + MDMA channel x interrupt flag clear + register + 0x344 + 0x20 + write-only + 0x00000000 + + + CTEIF12 + Channel x clear transfer error interrupt + flag Writing a 1 into this bit clears TEIFx in the + MDMA_ISRy register + 0 + 1 + + + CCTCIF12 + Clear Channel transfer complete + interrupt flag for channel x Writing a 1 into this + bit clears CTCIFx in the MDMA_ISRy + register + 1 + 1 + + + CBRTIF12 + Channel x clear block repeat transfer + complete interrupt flag Writing a 1 into this bit + clears BRTIFx in the MDMA_ISRy register + 2 + 1 + + + CBTIF12 + Channel x Clear block transfer complete + interrupt flag Writing a 1 into this bit clears BTIFx + in the MDMA_ISRy register + 3 + 1 + + + CLTCIF12 + CLear buffer Transfer Complete Interrupt + Flag for channel x Writing a 1 into this bit clears + TCIFx in the MDMA_ISRy register + 4 + 1 + + + + + MDMA_C12ESR + MDMA_C12ESR + MDMA Channel x error status + register + 0x348 + 0x20 + read-only + 0x00000000 + + + TEA + Transfer Error Address These bits are + set and cleared by HW, in case of an MDMA data + transfer error. It is used in conjunction with TED. + This field indicates the 7 LSBits of the address + which generated a transfer/access error. It may be + used by SW to retrieve the failing address, by adding + this value (truncated to the buffer transfer length + size) to the current SAR/DAR value. Note: The SAR/DAR + current value doesnt reflect this last address due to + the FIFO management system. The SAR/DAR are only + updated at the end of a (buffer) transfer (of TLEN+1 + bytes). Note: It is not set in case of a link data + error. + 0 + 7 + + + TED + Transfer Error Direction These bit is + set and cleared by HW, in case of an MDMA data + transfer error. + 7 + 1 + + + TELD + Transfer Error Link Data These bit is + set by HW, in case of a transfer error while reading + the block link data structure. It is cleared by + software writing 1 to the CTEIFx bit in the DMA_IFCRy + register. + 8 + 1 + + + TEMD + Transfer Error Mask Data These bit is + set by HW, in case of a transfer error while writing + the Mask Data. It is cleared by software writing 1 to + the CTEIFx bit in the DMA_IFCRy + register. + 9 + 1 + + + ASE + Address/Size Error These bit is set by + HW, when the programmed address is not aligned with + the data size. TED will indicate whether the problem + is on the source or destination. It is cleared by + software writing 1 to the CTEIFx bit in the DMA_IFCRy + register. + 10 + 1 + + + BSE + Block Size Error These bit is set by HW, + when the block size is not an integer multiple of the + data size either for source or destination. TED will + indicate whether the problem is on the source or + destination. It is cleared by software writing 1 to + the CTEIFx bit in the DMA_IFCRy + register. + 11 + 1 + + + + + MDMA_C12CR + MDMA_C12CR + This register is used to control the + concerned channel. + 0x34C + 0x20 + 0x00000000 + + + EN + channel enable + 0 + 1 + read-write + + + TEIE + Transfer error interrupt enable This bit + is set and cleared by software. + 1 + 1 + read-write + + + CTCIE + Channel Transfer Complete interrupt + enable This bit is set and cleared by + software. + 2 + 1 + read-write + + + BRTIE + Block Repeat transfer interrupt enable + This bit is set and cleared by + software. + 3 + 1 + read-write + + + BTIE + Block Transfer interrupt enable This bit + is set and cleared by software. + 4 + 1 + read-write + + + TCIE + buffer Transfer Complete interrupt + enable This bit is set and cleared by + software. + 5 + 1 + read-write + + + PL + Priority level These bits are set and + cleared by software. These bits are protected and can + be written only if EN is 0. + 6 + 2 + read-write + + + BEX + byte Endianness exchange + 12 + 1 + read-write + + + HEX + Half word Endianes + exchange + 13 + 1 + read-write + + + WEX + Word Endianness exchange + 14 + 1 + read-write + + + SWRQ + SW ReQuest Writing a 1 into this bit + sets the CRQAx in MDMA_ISRy register, activating the + request on Channel x Note: Either the whole CxCR + register or the 8-bit/16-bit register @ Address + offset: 0x4E + 0x40 chn may be used for SWRQ + activation. In case of a SW request, acknowledge is + not generated (neither HW signal, nor CxMAR write + access). + 16 + 1 + write-only + + + + + MDMA_C12TCR + MDMA_C12TCR + This register is used to configure the + concerned channel. + 0x350 + 0x20 + read-write + 0x00000000 + + + SINC + Source increment mode These bits are set + and cleared by software. These bits are protected and + can be written only if EN is 0 Note: When source is + AHB (SBUS=1), SINC = 00 is forbidden. In Linked List + Mode, at the end of a block (single or last block in + repeated block transfer mode), this register will be + loaded from memory (from address given by current + LAR[31:0] + 0x00). + 0 + 2 + + + DINC + Destination increment mode These bits + are set and cleared by software. These bits are + protected and can be written only if EN is 0 Note: + When destination is AHB (DBUS=1), DINC = 00 is + forbidden. + 2 + 2 + + + SSIZE + Source data size These bits are set and + cleared by software. These bits are protected and can + be written only if EN is 0 Note: If a value of 11 is + programmed for the TCM access/AHB port, a transfer + error will occur (TEIF bit set) If SINCOS < + SSIZE and SINC ≠ 00, the result will be + unpredictable. Note: SSIZE = 11 (double-word) is + forbidden when source is TCM/AHB bus + (SBUS=1). + 4 + 2 + + + DSIZE + Destination data size These bits are set + and cleared by software. These bits are protected and + can be written only if EN is 0. Note: If a value of + 11 is programmed for the TCM access/AHB port, a + transfer error will occur (TEIF bit set) If DINCOS + < DSIZE and DINC ≠ 00, the result + will be unpredictable. Note: DSIZE = 11 (double-word) + is forbidden when destination is TCM/AHB bus + (DBUS=1). + 6 + 2 + + + SINCOS + source increment offset + size + 8 + 2 + + + DINCOS + Destination increment + offset + 10 + 2 + + + SBURST + source burst transfer + configuration + 12 + 3 + + + DBURST + Destination burst transfer + configuration + 15 + 3 + + + TLEN + buffer transfer lengh + 18 + 7 + + + PKE + PacK Enable These bit is set and cleared + by software. If the Source Size is smaller than the + destination, it will be padded according to the PAM + value. If the Source data size is larger than the + destination one, it will be truncated. The alignment + will be done according to the PAM[0] value. This bit + is protected and can be written only if EN is + 0 + 25 + 1 + + + PAM + Padding/Alignement Mode These bits are + set and cleared by software. Case 1: Source data size + smaller than destination data size - 3 options are + valid. Case 2: Source data size larger than + destination data size. The remainder part is + discarded. When PKE = 1 or DSIZE=SSIZE, these bits + are ignored. These bits are protected and can be + written only if EN is 0 + 26 + 2 + + + TRGM + Trigger Mode These bits are set and + cleared by software. Note: If TRGM is 11 for the + current block, all the values loaded at the end of + the current block through the linked list mechanism + must keep the same value (TRGM=11) and the same SWRM + value, otherwise the result is undefined. These bits + are protected and can be written only if EN is + 0. + 28 + 2 + + + SWRM + SW Request Mode This bit is set and + cleared by software. If a HW or SW request is + currently active, the bit change will be delayed + until the current transfer is completed. If the CxMAR + contains a valid address, the CxMDR value will also + be written @ CxMAR address. This bit is protected and + can be written only if EN is 0. + 30 + 1 + + + BWM + Bufferable Write Mode This bit is set + and cleared by software. This bit is protected and + can be written only if EN is 0. Note: All MDMA + destination accesses are non-cacheable. + 31 + 1 + + + + + MDMA_C12BNDTR + MDMA_C12BNDTR + MDMA Channel x block number of data + register + 0x354 + 0x20 + read-write + 0x00000000 + + + BNDT + block number of data to + transfer + 0 + 17 + + + BRSUM + Block Repeat Source address Update Mode + These bits are protected and can be written only if + EN is 0. + 18 + 1 + + + BRDUM + Block Repeat Destination address Update + Mode These bits are protected and can be written only + if EN is 0. + 19 + 1 + + + BRC + Block Repeat Count This field contains + the number of repetitions of the current block (0 to + 4095). When the channel is enabled, this register is + read-only, indicating the remaining number of blocks, + excluding the current one. This register decrements + after each complete block transfer. Once the last + block transfer has completed, this register can + either stay at zero or be reloaded automatically from + memory (in Linked List mode - i.e. Link Address + valid). These bits are protected and can be written + only if EN is 0. + 20 + 12 + + + + + MDMA_C12SAR + MDMA_C12SAR + MDMA channel x source address + register + 0x358 + 0x20 + read-write + 0x00000000 + + + SAR + source adr base + 0 + 32 + + + + + MDMA_C12DAR + MDMA_C12DAR + MDMA channel x destination address + register + 0x35C + 0x20 + read-write + 0x00000000 + + + DAR + Destination adr base + 0 + 32 + + + + + MDMA_C12BRUR + MDMA_C12BRUR + MDMA channel x Block Repeat address Update + register + 0x360 + 0x20 + read-write + 0x00000000 + + + SUV + source adresse update + value + 0 + 16 + + + DUV + destination address update + 16 + 16 + + + + + MDMA_C12LAR + MDMA_C12LAR + MDMA channel x Link Address + register + 0x364 + 0x20 + read-write + 0x00000000 + + + LAR + Link address register + 0 + 32 + + + + + MDMA_C12TBR + MDMA_C12TBR + MDMA channel x Trigger and Bus selection + Register + 0x368 + 0x20 + read-write + 0x00000000 + + + TSEL + Trigger selection + 0 + 6 + + + SBUS + Source BUS select This bit is protected + and can be written only if EN is 0. + 16 + 1 + + + DBUS + Destination BUS slect This bit is + protected and can be written only if EN is + 0. + 17 + 1 + + + + + MDMA_C12MAR + MDMA_C12MAR + MDMA channel x Mask address + register + 0x370 + 0x20 + read-write + 0x00000000 + + + MAR + Mask address + 0 + 32 + + + + + MDMA_C12MDR + MDMA_C12MDR + MDMA channel x Mask Data + register + 0x374 + 0x20 + read-write + 0x00000000 + + + MDR + Mask data + 0 + 32 + + + + + MDMA_C13ISR + MDMA_C13ISR + MDMA channel x interrupt/status + register + 0x380 + 0x20 + read-only + 0x00000000 + + + TEIF13 + Channel x transfer error interrupt flag + This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCRy register. + 0 + 1 + + + CTCIF13 + Channel x Channel Transfer Complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. CTC is set when the + last block was transferred and the channel has been + automatically disabled. CTC is also set when the + channel is suspended, as a result of writing EN bit + to 0. + 1 + 1 + + + BRTIF13 + Channel x block repeat transfer complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. + 2 + 1 + + + BTIF13 + Channel x block transfer complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. + 3 + 1 + + + TCIF13 + channel x buffer transfer + complete + 4 + 1 + + + CRQA13 + channel x request active + flag + 16 + 1 + + + + + MDMA_C13IFCR + MDMA_C13IFCR + MDMA channel x interrupt flag clear + register + 0x384 + 0x20 + write-only + 0x00000000 + + + CTEIF13 + Channel x clear transfer error interrupt + flag Writing a 1 into this bit clears TEIFx in the + MDMA_ISRy register + 0 + 1 + + + CCTCIF13 + Clear Channel transfer complete + interrupt flag for channel x Writing a 1 into this + bit clears CTCIFx in the MDMA_ISRy + register + 1 + 1 + + + CBRTIF13 + Channel x clear block repeat transfer + complete interrupt flag Writing a 1 into this bit + clears BRTIFx in the MDMA_ISRy register + 2 + 1 + + + CBTIF13 + Channel x Clear block transfer complete + interrupt flag Writing a 1 into this bit clears BTIFx + in the MDMA_ISRy register + 3 + 1 + + + CLTCIF13 + CLear buffer Transfer Complete Interrupt + Flag for channel x Writing a 1 into this bit clears + TCIFx in the MDMA_ISRy register + 4 + 1 + + + + + MDMA_C13ESR + MDMA_C13ESR + MDMA Channel x error status + register + 0x388 + 0x20 + read-only + 0x00000000 + + + TEA + Transfer Error Address These bits are + set and cleared by HW, in case of an MDMA data + transfer error. It is used in conjunction with TED. + This field indicates the 7 LSBits of the address + which generated a transfer/access error. It may be + used by SW to retrieve the failing address, by adding + this value (truncated to the buffer transfer length + size) to the current SAR/DAR value. Note: The SAR/DAR + current value doesnt reflect this last address due to + the FIFO management system. The SAR/DAR are only + updated at the end of a (buffer) transfer (of TLEN+1 + bytes). Note: It is not set in case of a link data + error. + 0 + 7 + + + TED + Transfer Error Direction These bit is + set and cleared by HW, in case of an MDMA data + transfer error. + 7 + 1 + + + TELD + Transfer Error Link Data These bit is + set by HW, in case of a transfer error while reading + the block link data structure. It is cleared by + software writing 1 to the CTEIFx bit in the DMA_IFCRy + register. + 8 + 1 + + + TEMD + Transfer Error Mask Data These bit is + set by HW, in case of a transfer error while writing + the Mask Data. It is cleared by software writing 1 to + the CTEIFx bit in the DMA_IFCRy + register. + 9 + 1 + + + ASE + Address/Size Error These bit is set by + HW, when the programmed address is not aligned with + the data size. TED will indicate whether the problem + is on the source or destination. It is cleared by + software writing 1 to the CTEIFx bit in the DMA_IFCRy + register. + 10 + 1 + + + BSE + Block Size Error These bit is set by HW, + when the block size is not an integer multiple of the + data size either for source or destination. TED will + indicate whether the problem is on the source or + destination. It is cleared by software writing 1 to + the CTEIFx bit in the DMA_IFCRy + register. + 11 + 1 + + + + + MDMA_C13CR + MDMA_C13CR + This register is used to control the + concerned channel. + 0x38C + 0x20 + 0x00000000 + + + EN + channel enable + 0 + 1 + read-write + + + TEIE + Transfer error interrupt enable This bit + is set and cleared by software. + 1 + 1 + read-write + + + CTCIE + Channel Transfer Complete interrupt + enable This bit is set and cleared by + software. + 2 + 1 + read-write + + + BRTIE + Block Repeat transfer interrupt enable + This bit is set and cleared by + software. + 3 + 1 + read-write + + + BTIE + Block Transfer interrupt enable This bit + is set and cleared by software. + 4 + 1 + read-write + + + TCIE + buffer Transfer Complete interrupt + enable This bit is set and cleared by + software. + 5 + 1 + read-write + + + PL + Priority level These bits are set and + cleared by software. These bits are protected and can + be written only if EN is 0. + 6 + 2 + read-write + + + BEX + byte Endianness exchange + 12 + 1 + read-write + + + HEX + Half word Endianes + exchange + 13 + 1 + read-write + + + WEX + Word Endianness exchange + 14 + 1 + read-write + + + SWRQ + SW ReQuest Writing a 1 into this bit + sets the CRQAx in MDMA_ISRy register, activating the + request on Channel x Note: Either the whole CxCR + register or the 8-bit/16-bit register @ Address + offset: 0x4E + 0x40 chn may be used for SWRQ + activation. In case of a SW request, acknowledge is + not generated (neither HW signal, nor CxMAR write + access). + 16 + 1 + write-only + + + + + MDMA_C13TCR + MDMA_C13TCR + This register is used to configure the + concerned channel. + 0x390 + 0x20 + read-write + 0x00000000 + + + SINC + Source increment mode These bits are set + and cleared by software. These bits are protected and + can be written only if EN is 0 Note: When source is + AHB (SBUS=1), SINC = 00 is forbidden. In Linked List + Mode, at the end of a block (single or last block in + repeated block transfer mode), this register will be + loaded from memory (from address given by current + LAR[31:0] + 0x00). + 0 + 2 + + + DINC + Destination increment mode These bits + are set and cleared by software. These bits are + protected and can be written only if EN is 0 Note: + When destination is AHB (DBUS=1), DINC = 00 is + forbidden. + 2 + 2 + + + SSIZE + Source data size These bits are set and + cleared by software. These bits are protected and can + be written only if EN is 0 Note: If a value of 11 is + programmed for the TCM access/AHB port, a transfer + error will occur (TEIF bit set) If SINCOS < + SSIZE and SINC ≠ 00, the result will be + unpredictable. Note: SSIZE = 11 (double-word) is + forbidden when source is TCM/AHB bus + (SBUS=1). + 4 + 2 + + + DSIZE + Destination data size These bits are set + and cleared by software. These bits are protected and + can be written only if EN is 0. Note: If a value of + 11 is programmed for the TCM access/AHB port, a + transfer error will occur (TEIF bit set) If DINCOS + < DSIZE and DINC ≠ 00, the result + will be unpredictable. Note: DSIZE = 11 (double-word) + is forbidden when destination is TCM/AHB bus + (DBUS=1). + 6 + 2 + + + SINCOS + source increment offset + size + 8 + 2 + + + DINCOS + Destination increment + offset + 10 + 2 + + + SBURST + source burst transfer + configuration + 12 + 3 + + + DBURST + Destination burst transfer + configuration + 15 + 3 + + + TLEN + buffer transfer lengh + 18 + 7 + + + PKE + PacK Enable These bit is set and cleared + by software. If the Source Size is smaller than the + destination, it will be padded according to the PAM + value. If the Source data size is larger than the + destination one, it will be truncated. The alignment + will be done according to the PAM[0] value. This bit + is protected and can be written only if EN is + 0 + 25 + 1 + + + PAM + Padding/Alignement Mode These bits are + set and cleared by software. Case 1: Source data size + smaller than destination data size - 3 options are + valid. Case 2: Source data size larger than + destination data size. The remainder part is + discarded. When PKE = 1 or DSIZE=SSIZE, these bits + are ignored. These bits are protected and can be + written only if EN is 0 + 26 + 2 + + + TRGM + Trigger Mode These bits are set and + cleared by software. Note: If TRGM is 11 for the + current block, all the values loaded at the end of + the current block through the linked list mechanism + must keep the same value (TRGM=11) and the same SWRM + value, otherwise the result is undefined. These bits + are protected and can be written only if EN is + 0. + 28 + 2 + + + SWRM + SW Request Mode This bit is set and + cleared by software. If a HW or SW request is + currently active, the bit change will be delayed + until the current transfer is completed. If the CxMAR + contains a valid address, the CxMDR value will also + be written @ CxMAR address. This bit is protected and + can be written only if EN is 0. + 30 + 1 + + + BWM + Bufferable Write Mode This bit is set + and cleared by software. This bit is protected and + can be written only if EN is 0. Note: All MDMA + destination accesses are non-cacheable. + 31 + 1 + + + + + MDMA_C13BNDTR + MDMA_C13BNDTR + MDMA Channel x block number of data + register + 0x394 + 0x20 + read-write + 0x00000000 + + + BNDT + block number of data to + transfer + 0 + 17 + + + BRSUM + Block Repeat Source address Update Mode + These bits are protected and can be written only if + EN is 0. + 18 + 1 + + + BRDUM + Block Repeat Destination address Update + Mode These bits are protected and can be written only + if EN is 0. + 19 + 1 + + + BRC + Block Repeat Count This field contains + the number of repetitions of the current block (0 to + 4095). When the channel is enabled, this register is + read-only, indicating the remaining number of blocks, + excluding the current one. This register decrements + after each complete block transfer. Once the last + block transfer has completed, this register can + either stay at zero or be reloaded automatically from + memory (in Linked List mode - i.e. Link Address + valid). These bits are protected and can be written + only if EN is 0. + 20 + 12 + + + + + MDMA_C13SAR + MDMA_C13SAR + MDMA channel x source address + register + 0x398 + 0x20 + read-write + 0x00000000 + + + SAR + source adr base + 0 + 32 + + + + + MDMA_C13DAR + MDMA_C13DAR + MDMA channel x destination address + register + 0x39C + 0x20 + read-write + 0x00000000 + + + DAR + Destination adr base + 0 + 32 + + + + + MDMA_C13BRUR + MDMA_C13BRUR + MDMA channel x Block Repeat address Update + register + 0x3A0 + 0x20 + read-write + 0x00000000 + + + SUV + source adresse update + value + 0 + 16 + + + DUV + destination address update + 16 + 16 + + + + + MDMA_C13LAR + MDMA_C13LAR + MDMA channel x Link Address + register + 0x3A4 + 0x20 + read-write + 0x00000000 + + + LAR + Link address register + 0 + 32 + + + + + MDMA_C13TBR + MDMA_C13TBR + MDMA channel x Trigger and Bus selection + Register + 0x3A8 + 0x20 + read-write + 0x00000000 + + + TSEL + Trigger selection + 0 + 6 + + + SBUS + Source BUS select This bit is protected + and can be written only if EN is 0. + 16 + 1 + + + DBUS + Destination BUS slect This bit is + protected and can be written only if EN is + 0. + 17 + 1 + + + + + MDMA_C13MAR + MDMA_C13MAR + MDMA channel x Mask address + register + 0x3B0 + 0x20 + read-write + 0x00000000 + + + MAR + Mask address + 0 + 32 + + + + + MDMA_C13MDR + MDMA_C13MDR + MDMA channel x Mask Data + register + 0x3B4 + 0x20 + read-write + 0x00000000 + + + MDR + Mask data + 0 + 32 + + + + + MDMA_C14ISR + MDMA_C14ISR + MDMA channel x interrupt/status + register + 0x3C0 + 0x20 + read-only + 0x00000000 + + + TEIF14 + Channel x transfer error interrupt flag + This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCRy register. + 0 + 1 + + + CTCIF14 + Channel x Channel Transfer Complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. CTC is set when the + last block was transferred and the channel has been + automatically disabled. CTC is also set when the + channel is suspended, as a result of writing EN bit + to 0. + 1 + 1 + + + BRTIF14 + Channel x block repeat transfer complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. + 2 + 1 + + + BTIF14 + Channel x block transfer complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. + 3 + 1 + + + TCIF14 + channel x buffer transfer + complete + 4 + 1 + + + CRQA14 + channel x request active + flag + 16 + 1 + + + + + MDMA_C14IFCR + MDMA_C14IFCR + MDMA channel x interrupt flag clear + register + 0x3C4 + 0x20 + write-only + 0x00000000 + + + CTEIF14 + Channel x clear transfer error interrupt + flag Writing a 1 into this bit clears TEIFx in the + MDMA_ISRy register + 0 + 1 + + + CCTCIF14 + Clear Channel transfer complete + interrupt flag for channel x Writing a 1 into this + bit clears CTCIFx in the MDMA_ISRy + register + 1 + 1 + + + CBRTIF14 + Channel x clear block repeat transfer + complete interrupt flag Writing a 1 into this bit + clears BRTIFx in the MDMA_ISRy register + 2 + 1 + + + CBTIF14 + Channel x Clear block transfer complete + interrupt flag Writing a 1 into this bit clears BTIFx + in the MDMA_ISRy register + 3 + 1 + + + CLTCIF14 + CLear buffer Transfer Complete Interrupt + Flag for channel x Writing a 1 into this bit clears + TCIFx in the MDMA_ISRy register + 4 + 1 + + + + + MDMA_C14ESR + MDMA_C14ESR + MDMA Channel x error status + register + 0x3C8 + 0x20 + read-only + 0x00000000 + + + TEA + Transfer Error Address These bits are + set and cleared by HW, in case of an MDMA data + transfer error. It is used in conjunction with TED. + This field indicates the 7 LSBits of the address + which generated a transfer/access error. It may be + used by SW to retrieve the failing address, by adding + this value (truncated to the buffer transfer length + size) to the current SAR/DAR value. Note: The SAR/DAR + current value doesnt reflect this last address due to + the FIFO management system. The SAR/DAR are only + updated at the end of a (buffer) transfer (of TLEN+1 + bytes). Note: It is not set in case of a link data + error. + 0 + 7 + + + TED + Transfer Error Direction These bit is + set and cleared by HW, in case of an MDMA data + transfer error. + 7 + 1 + + + TELD + Transfer Error Link Data These bit is + set by HW, in case of a transfer error while reading + the block link data structure. It is cleared by + software writing 1 to the CTEIFx bit in the DMA_IFCRy + register. + 8 + 1 + + + TEMD + Transfer Error Mask Data These bit is + set by HW, in case of a transfer error while writing + the Mask Data. It is cleared by software writing 1 to + the CTEIFx bit in the DMA_IFCRy + register. + 9 + 1 + + + ASE + Address/Size Error These bit is set by + HW, when the programmed address is not aligned with + the data size. TED will indicate whether the problem + is on the source or destination. It is cleared by + software writing 1 to the CTEIFx bit in the DMA_IFCRy + register. + 10 + 1 + + + BSE + Block Size Error These bit is set by HW, + when the block size is not an integer multiple of the + data size either for source or destination. TED will + indicate whether the problem is on the source or + destination. It is cleared by software writing 1 to + the CTEIFx bit in the DMA_IFCRy + register. + 11 + 1 + + + + + MDMA_C14CR + MDMA_C14CR + This register is used to control the + concerned channel. + 0x3CC + 0x20 + 0x00000000 + + + EN + channel enable + 0 + 1 + read-write + + + TEIE + Transfer error interrupt enable This bit + is set and cleared by software. + 1 + 1 + read-write + + + CTCIE + Channel Transfer Complete interrupt + enable This bit is set and cleared by + software. + 2 + 1 + read-write + + + BRTIE + Block Repeat transfer interrupt enable + This bit is set and cleared by + software. + 3 + 1 + read-write + + + BTIE + Block Transfer interrupt enable This bit + is set and cleared by software. + 4 + 1 + read-write + + + TCIE + buffer Transfer Complete interrupt + enable This bit is set and cleared by + software. + 5 + 1 + read-write + + + PL + Priority level These bits are set and + cleared by software. These bits are protected and can + be written only if EN is 0. + 6 + 2 + read-write + + + BEX + byte Endianness exchange + 12 + 1 + read-write + + + HEX + Half word Endianes + exchange + 13 + 1 + read-write + + + WEX + Word Endianness exchange + 14 + 1 + read-write + + + SWRQ + SW ReQuest Writing a 1 into this bit + sets the CRQAx in MDMA_ISRy register, activating the + request on Channel x Note: Either the whole CxCR + register or the 8-bit/16-bit register @ Address + offset: 0x4E + 0x40 chn may be used for SWRQ + activation. In case of a SW request, acknowledge is + not generated (neither HW signal, nor CxMAR write + access). + 16 + 1 + write-only + + + + + MDMA_C14TCR + MDMA_C14TCR + This register is used to configure the + concerned channel. + 0x3D0 + 0x20 + read-write + 0x00000000 + + + SINC + Source increment mode These bits are set + and cleared by software. These bits are protected and + can be written only if EN is 0 Note: When source is + AHB (SBUS=1), SINC = 00 is forbidden. In Linked List + Mode, at the end of a block (single or last block in + repeated block transfer mode), this register will be + loaded from memory (from address given by current + LAR[31:0] + 0x00). + 0 + 2 + + + DINC + Destination increment mode These bits + are set and cleared by software. These bits are + protected and can be written only if EN is 0 Note: + When destination is AHB (DBUS=1), DINC = 00 is + forbidden. + 2 + 2 + + + SSIZE + Source data size These bits are set and + cleared by software. These bits are protected and can + be written only if EN is 0 Note: If a value of 11 is + programmed for the TCM access/AHB port, a transfer + error will occur (TEIF bit set) If SINCOS < + SSIZE and SINC ≠ 00, the result will be + unpredictable. Note: SSIZE = 11 (double-word) is + forbidden when source is TCM/AHB bus + (SBUS=1). + 4 + 2 + + + DSIZE + Destination data size These bits are set + and cleared by software. These bits are protected and + can be written only if EN is 0. Note: If a value of + 11 is programmed for the TCM access/AHB port, a + transfer error will occur (TEIF bit set) If DINCOS + < DSIZE and DINC ≠ 00, the result + will be unpredictable. Note: DSIZE = 11 (double-word) + is forbidden when destination is TCM/AHB bus + (DBUS=1). + 6 + 2 + + + SINCOS + source increment offset + size + 8 + 2 + + + DINCOS + Destination increment + offset + 10 + 2 + + + SBURST + source burst transfer + configuration + 12 + 3 + + + DBURST + Destination burst transfer + configuration + 15 + 3 + + + TLEN + buffer transfer lengh + 18 + 7 + + + PKE + PacK Enable These bit is set and cleared + by software. If the Source Size is smaller than the + destination, it will be padded according to the PAM + value. If the Source data size is larger than the + destination one, it will be truncated. The alignment + will be done according to the PAM[0] value. This bit + is protected and can be written only if EN is + 0 + 25 + 1 + + + PAM + Padding/Alignement Mode These bits are + set and cleared by software. Case 1: Source data size + smaller than destination data size - 3 options are + valid. Case 2: Source data size larger than + destination data size. The remainder part is + discarded. When PKE = 1 or DSIZE=SSIZE, these bits + are ignored. These bits are protected and can be + written only if EN is 0 + 26 + 2 + + + TRGM + Trigger Mode These bits are set and + cleared by software. Note: If TRGM is 11 for the + current block, all the values loaded at the end of + the current block through the linked list mechanism + must keep the same value (TRGM=11) and the same SWRM + value, otherwise the result is undefined. These bits + are protected and can be written only if EN is + 0. + 28 + 2 + + + SWRM + SW Request Mode This bit is set and + cleared by software. If a HW or SW request is + currently active, the bit change will be delayed + until the current transfer is completed. If the CxMAR + contains a valid address, the CxMDR value will also + be written @ CxMAR address. This bit is protected and + can be written only if EN is 0. + 30 + 1 + + + BWM + Bufferable Write Mode This bit is set + and cleared by software. This bit is protected and + can be written only if EN is 0. Note: All MDMA + destination accesses are non-cacheable. + 31 + 1 + + + + + MDMA_C14BNDTR + MDMA_C14BNDTR + MDMA Channel x block number of data + register + 0x3D4 + 0x20 + read-write + 0x00000000 + + + BNDT + block number of data to + transfer + 0 + 17 + + + BRSUM + Block Repeat Source address Update Mode + These bits are protected and can be written only if + EN is 0. + 18 + 1 + + + BRDUM + Block Repeat Destination address Update + Mode These bits are protected and can be written only + if EN is 0. + 19 + 1 + + + BRC + Block Repeat Count This field contains + the number of repetitions of the current block (0 to + 4095). When the channel is enabled, this register is + read-only, indicating the remaining number of blocks, + excluding the current one. This register decrements + after each complete block transfer. Once the last + block transfer has completed, this register can + either stay at zero or be reloaded automatically from + memory (in Linked List mode - i.e. Link Address + valid). These bits are protected and can be written + only if EN is 0. + 20 + 12 + + + + + MDMA_C14SAR + MDMA_C14SAR + MDMA channel x source address + register + 0x3D8 + 0x20 + read-write + 0x00000000 + + + SAR + source adr base + 0 + 32 + + + + + MDMA_C14DAR + MDMA_C14DAR + MDMA channel x destination address + register + 0x3DC + 0x20 + read-write + 0x00000000 + + + DAR + Destination adr base + 0 + 32 + + + + + MDMA_C14BRUR + MDMA_C14BRUR + MDMA channel x Block Repeat address Update + register + 0x3E0 + 0x20 + read-write + 0x00000000 + + + SUV + source adresse update + value + 0 + 16 + + + DUV + destination address update + 16 + 16 + + + + + MDMA_C14LAR + MDMA_C14LAR + MDMA channel x Link Address + register + 0x3E4 + 0x20 + read-write + 0x00000000 + + + LAR + Link address register + 0 + 32 + + + + + MDMA_C14TBR + MDMA_C14TBR + MDMA channel x Trigger and Bus selection + Register + 0x3E8 + 0x20 + read-write + 0x00000000 + + + TSEL + Trigger selection + 0 + 6 + + + SBUS + Source BUS select This bit is protected + and can be written only if EN is 0. + 16 + 1 + + + DBUS + Destination BUS slect This bit is + protected and can be written only if EN is + 0. + 17 + 1 + + + + + MDMA_C14MAR + MDMA_C14MAR + MDMA channel x Mask address + register + 0x3F0 + 0x20 + read-write + 0x00000000 + + + MAR + Mask address + 0 + 32 + + + + + MDMA_C14MDR + MDMA_C14MDR + MDMA channel x Mask Data + register + 0x3F4 + 0x20 + read-write + 0x00000000 + + + MDR + Mask data + 0 + 32 + + + + + MDMA_C15ISR + MDMA_C15ISR + MDMA channel x interrupt/status + register + 0x400 + 0x20 + read-only + 0x00000000 + + + TEIF15 + Channel x transfer error interrupt flag + This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCRy register. + 0 + 1 + + + CTCIF15 + Channel x Channel Transfer Complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. CTC is set when the + last block was transferred and the channel has been + automatically disabled. CTC is also set when the + channel is suspended, as a result of writing EN bit + to 0. + 1 + 1 + + + BRTIF15 + Channel x block repeat transfer complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. + 2 + 1 + + + BTIF15 + Channel x block transfer complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. + 3 + 1 + + + TCIF15 + channel x buffer transfer + complete + 4 + 1 + + + CRQA15 + channel x request active + flag + 16 + 1 + + + + + MDMA_C15IFCR + MDMA_C15IFCR + MDMA channel x interrupt flag clear + register + 0x404 + 0x20 + write-only + 0x00000000 + + + CTEIF15 + Channel x clear transfer error interrupt + flag Writing a 1 into this bit clears TEIFx in the + MDMA_ISRy register + 0 + 1 + + + CCTCIF15 + Clear Channel transfer complete + interrupt flag for channel x Writing a 1 into this + bit clears CTCIFx in the MDMA_ISRy + register + 1 + 1 + + + CBRTIF15 + Channel x clear block repeat transfer + complete interrupt flag Writing a 1 into this bit + clears BRTIFx in the MDMA_ISRy register + 2 + 1 + + + CBTIF15 + Channel x Clear block transfer complete + interrupt flag Writing a 1 into this bit clears BTIFx + in the MDMA_ISRy register + 3 + 1 + + + CLTCIF15 + CLear buffer Transfer Complete Interrupt + Flag for channel x Writing a 1 into this bit clears + TCIFx in the MDMA_ISRy register + 4 + 1 + + + + + MDMA_C15ESR + MDMA_C15ESR + MDMA Channel x error status + register + 0x408 + 0x20 + read-only + 0x00000000 + + + TEA + Transfer Error Address These bits are + set and cleared by HW, in case of an MDMA data + transfer error. It is used in conjunction with TED. + This field indicates the 7 LSBits of the address + which generated a transfer/access error. It may be + used by SW to retrieve the failing address, by adding + this value (truncated to the buffer transfer length + size) to the current SAR/DAR value. Note: The SAR/DAR + current value doesnt reflect this last address due to + the FIFO management system. The SAR/DAR are only + updated at the end of a (buffer) transfer (of TLEN+1 + bytes). Note: It is not set in case of a link data + error. + 0 + 7 + + + TED + Transfer Error Direction These bit is + set and cleared by HW, in case of an MDMA data + transfer error. + 7 + 1 + + + TELD + Transfer Error Link Data These bit is + set by HW, in case of a transfer error while reading + the block link data structure. It is cleared by + software writing 1 to the CTEIFx bit in the DMA_IFCRy + register. + 8 + 1 + + + TEMD + Transfer Error Mask Data These bit is + set by HW, in case of a transfer error while writing + the Mask Data. It is cleared by software writing 1 to + the CTEIFx bit in the DMA_IFCRy + register. + 9 + 1 + + + ASE + Address/Size Error These bit is set by + HW, when the programmed address is not aligned with + the data size. TED will indicate whether the problem + is on the source or destination. It is cleared by + software writing 1 to the CTEIFx bit in the DMA_IFCRy + register. + 10 + 1 + + + BSE + Block Size Error These bit is set by HW, + when the block size is not an integer multiple of the + data size either for source or destination. TED will + indicate whether the problem is on the source or + destination. It is cleared by software writing 1 to + the CTEIFx bit in the DMA_IFCRy + register. + 11 + 1 + + + + + MDMA_C15CR + MDMA_C15CR + This register is used to control the + concerned channel. + 0x40C + 0x20 + 0x00000000 + + + EN + channel enable + 0 + 1 + read-write + + + TEIE + Transfer error interrupt enable This bit + is set and cleared by software. + 1 + 1 + read-write + + + CTCIE + Channel Transfer Complete interrupt + enable This bit is set and cleared by + software. + 2 + 1 + read-write + + + BRTIE + Block Repeat transfer interrupt enable + This bit is set and cleared by + software. + 3 + 1 + read-write + + + BTIE + Block Transfer interrupt enable This bit + is set and cleared by software. + 4 + 1 + read-write + + + TCIE + buffer Transfer Complete interrupt + enable This bit is set and cleared by + software. + 5 + 1 + read-write + + + PL + Priority level These bits are set and + cleared by software. These bits are protected and can + be written only if EN is 0. + 6 + 2 + read-write + + + BEX + byte Endianness exchange + 12 + 1 + read-write + + + HEX + Half word Endianes + exchange + 13 + 1 + read-write + + + WEX + Word Endianness exchange + 14 + 1 + read-write + + + SWRQ + SW ReQuest Writing a 1 into this bit + sets the CRQAx in MDMA_ISRy register, activating the + request on Channel x Note: Either the whole CxCR + register or the 8-bit/16-bit register @ Address + offset: 0x4E + 0x40 chn may be used for SWRQ + activation. In case of a SW request, acknowledge is + not generated (neither HW signal, nor CxMAR write + access). + 16 + 1 + write-only + + + + + MDMA_C15TCR + MDMA_C15TCR + This register is used to configure the + concerned channel. + 0x410 + 0x20 + read-write + 0x00000000 + + + SINC + Source increment mode These bits are set + and cleared by software. These bits are protected and + can be written only if EN is 0 Note: When source is + AHB (SBUS=1), SINC = 00 is forbidden. In Linked List + Mode, at the end of a block (single or last block in + repeated block transfer mode), this register will be + loaded from memory (from address given by current + LAR[31:0] + 0x00). + 0 + 2 + + + DINC + Destination increment mode These bits + are set and cleared by software. These bits are + protected and can be written only if EN is 0 Note: + When destination is AHB (DBUS=1), DINC = 00 is + forbidden. + 2 + 2 + + + SSIZE + Source data size These bits are set and + cleared by software. These bits are protected and can + be written only if EN is 0 Note: If a value of 11 is + programmed for the TCM access/AHB port, a transfer + error will occur (TEIF bit set) If SINCOS < + SSIZE and SINC ≠ 00, the result will be + unpredictable. Note: SSIZE = 11 (double-word) is + forbidden when source is TCM/AHB bus + (SBUS=1). + 4 + 2 + + + DSIZE + Destination data size These bits are set + and cleared by software. These bits are protected and + can be written only if EN is 0. Note: If a value of + 11 is programmed for the TCM access/AHB port, a + transfer error will occur (TEIF bit set) If DINCOS + < DSIZE and DINC ≠ 00, the result + will be unpredictable. Note: DSIZE = 11 (double-word) + is forbidden when destination is TCM/AHB bus + (DBUS=1). + 6 + 2 + + + SINCOS + source increment offset + size + 8 + 2 + + + DINCOS + Destination increment + offset + 10 + 2 + + + SBURST + source burst transfer + configuration + 12 + 3 + + + DBURST + Destination burst transfer + configuration + 15 + 3 + + + TLEN + buffer transfer lengh + 18 + 7 + + + PKE + PacK Enable These bit is set and cleared + by software. If the Source Size is smaller than the + destination, it will be padded according to the PAM + value. If the Source data size is larger than the + destination one, it will be truncated. The alignment + will be done according to the PAM[0] value. This bit + is protected and can be written only if EN is + 0 + 25 + 1 + + + PAM + Padding/Alignement Mode These bits are + set and cleared by software. Case 1: Source data size + smaller than destination data size - 3 options are + valid. Case 2: Source data size larger than + destination data size. The remainder part is + discarded. When PKE = 1 or DSIZE=SSIZE, these bits + are ignored. These bits are protected and can be + written only if EN is 0 + 26 + 2 + + + TRGM + Trigger Mode These bits are set and + cleared by software. Note: If TRGM is 11 for the + current block, all the values loaded at the end of + the current block through the linked list mechanism + must keep the same value (TRGM=11) and the same SWRM + value, otherwise the result is undefined. These bits + are protected and can be written only if EN is + 0. + 28 + 2 + + + SWRM + SW Request Mode This bit is set and + cleared by software. If a HW or SW request is + currently active, the bit change will be delayed + until the current transfer is completed. If the CxMAR + contains a valid address, the CxMDR value will also + be written @ CxMAR address. This bit is protected and + can be written only if EN is 0. + 30 + 1 + + + BWM + Bufferable Write Mode This bit is set + and cleared by software. This bit is protected and + can be written only if EN is 0. Note: All MDMA + destination accesses are non-cacheable. + 31 + 1 + + + + + MDMA_C15BNDTR + MDMA_C15BNDTR + MDMA Channel x block number of data + register + 0x414 + 0x20 + read-write + 0x00000000 + + + BNDT + block number of data to + transfer + 0 + 17 + + + BRSUM + Block Repeat Source address Update Mode + These bits are protected and can be written only if + EN is 0. + 18 + 1 + + + BRDUM + Block Repeat Destination address Update + Mode These bits are protected and can be written only + if EN is 0. + 19 + 1 + + + BRC + Block Repeat Count This field contains + the number of repetitions of the current block (0 to + 4095). When the channel is enabled, this register is + read-only, indicating the remaining number of blocks, + excluding the current one. This register decrements + after each complete block transfer. Once the last + block transfer has completed, this register can + either stay at zero or be reloaded automatically from + memory (in Linked List mode - i.e. Link Address + valid). These bits are protected and can be written + only if EN is 0. + 20 + 12 + + + + + MDMA_C15SAR + MDMA_C15SAR + MDMA channel x source address + register + 0x418 + 0x20 + read-write + 0x00000000 + + + SAR + source adr base + 0 + 32 + + + + + MDMA_C15DAR + MDMA_C15DAR + MDMA channel x destination address + register + 0x41C + 0x20 + read-write + 0x00000000 + + + DAR + Destination adr base + 0 + 32 + + + + + MDMA_C15BRUR + MDMA_C15BRUR + MDMA channel x Block Repeat address Update + register + 0x420 + 0x20 + read-write + 0x00000000 + + + SUV + source adresse update + value + 0 + 16 + + + DUV + destination address update + 16 + 16 + + + + + MDMA_C15LAR + MDMA_C15LAR + MDMA channel x Link Address + register + 0x424 + 0x20 + read-write + 0x00000000 + + + LAR + Link address register + 0 + 32 + + + + + MDMA_C15TBR + MDMA_C15TBR + MDMA channel x Trigger and Bus selection + Register + 0x428 + 0x20 + read-write + 0x00000000 + + + TSEL + Trigger selection + 0 + 6 + + + SBUS + Source BUS select This bit is protected + and can be written only if EN is 0. + 16 + 1 + + + DBUS + Destination BUS slect This bit is + protected and can be written only if EN is + 0. + 17 + 1 + + + + + MDMA_C15MAR + MDMA_C15MAR + MDMA channel x Mask address + register + 0x430 + 0x20 + read-write + 0x00000000 + + + MAR + Mask address + 0 + 32 + + + + + MDMA_C15MDR + MDMA_C15MDR + MDMA channel x Mask Data + register + 0x434 + 0x20 + read-write + 0x00000000 + + + MDR + Mask data + 0 + 32 + + + + + + + QUADSPI + QUADSPI + QUADSPI + 0x52005000 + + 0x0 + 0x400 + registers + + + QUADSPI + QuadSPI global interrupt + 92 + + + + CR + CR + QUADSPI control register + 0x0 + 0x20 + read-write + 0x00000000 + + + EN + Enable Enable the QUADSPI. + 0 + 1 + + + ABORT + Abort request This bit aborts the + on-going command sequence. It is automatically reset + once the abort is complete. This bit stops the + current transfer. In polling mode or memory-mapped + mode, this bit also reset the APM bit or the DM + bit. + 1 + 1 + + + DMAEN + DMA enable In indirect mode, DMA can be + used to input or output data via the QUADSPI_DR + register. DMA transfers are initiated when the FIFO + threshold flag, FTF, is set. + 2 + 1 + + + TCEN + Timeout counter enable This bit is valid + only when memory-mapped mode (FMODE = 11) is + selected. Activating this bit causes the chip select + (nCS) to be released (and thus reduces consumption) + if there has not been an access after a certain + amount of time, where this time is defined by + TIMEOUT[15:0] (QUADSPI_LPTR). Enable the timeout + counter. By default, the QUADSPI never stops its + prefetch operation, keeping the previous read + operation active with nCS maintained low, even if no + access to the Flash memory occurs for a long time. + Since Flash memories tend to consume more when nCS is + held low, the application might want to activate the + timeout counter (TCEN = 1, QUADSPI_CR[3]) so that nCS + is released after a period of TIMEOUT[15:0] + (QUADSPI_LPTR) cycles have elapsed without an access + since when the FIFO becomes full with prefetch data. + This bit can be modified only when BUSY = + 0. + 3 + 1 + + + SSHIFT + Sample shift By default, the QUADSPI + samples data 1/2 of a CLK cycle after the data is + driven by the Flash memory. This bit allows the data + is to be sampled later in order to account for + external signal delays. Firmware must assure that + SSHIFT = 0 when in DDR mode (when DDRM = 1). This + field can be modified only when BUSY = + 0. + 4 + 1 + + + DFM + Dual-flash mode This bit activates + dual-flash mode, where two external Flash memories + are used simultaneously to double throughput and + capacity. This bit can be modified only when BUSY = + 0. + 6 + 1 + + + FSEL + Flash memory selection This bit selects + the Flash memory to be addressed in single flash mode + (when DFM = 0). This bit can be modified only when + BUSY = 0. This bit is ignored when DFM = + 1. + 7 + 1 + + + FTHRES + FIFO threshold level Defines, in + indirect mode, the threshold number of bytes in the + FIFO that will cause the FIFO threshold flag (FTF, + QUADSPI_SR[2]) to be set. In indirect write mode + (FMODE = 00): ... In indirect read mode (FMODE = 01): + ... If DMAEN = 1, then the DMA controller for the + corresponding channel must be disabled before + changing the FTHRES value. + 8 + 5 + + + TEIE + Transfer error interrupt enable This bit + enables the transfer error interrupt. + 16 + 1 + + + TCIE + Transfer complete interrupt enable This + bit enables the transfer complete + interrupt. + 17 + 1 + + + FTIE + FIFO threshold interrupt enable This bit + enables the FIFO threshold interrupt. + 18 + 1 + + + SMIE + Status match interrupt enable This bit + enables the status match interrupt. + 19 + 1 + + + TOIE + TimeOut interrupt enable This bit + enables the TimeOut interrupt. + 20 + 1 + + + APMS + Automatic poll mode stop This bit + determines if automatic polling is stopped after a + match. This bit can be modified only when BUSY = + 0. + 22 + 1 + + + PMM + Polling match mode This bit indicates + which method should be used for determining a match + during automatic polling mode. This bit can be + modified only when BUSY = 0. + 23 + 1 + + + PRESCALER + clock prescaler + 24 + 8 + + + + + DCR + DCR + QUADSPI device configuration + register + 0x4 + 0x20 + read-write + 0x00000000 + + + CKMODE + indicates the level that clk takes + between command + 0 + 1 + + + CSHT + Chip select high time CSHT+1 defines the + minimum number of CLK cycles which the chip select + (nCS) must remain high between commands issued to the + Flash memory. ... This field can be modified only + when BUSY = 0. + 8 + 3 + + + FSIZE + Flash memory size This field defines the + size of external memory using the following formula: + Number of bytes in Flash memory = 2[FSIZE+1] FSIZE+1 + is effectively the number of address bits required to + address the Flash memory. The Flash memory capacity + can be up to 4GB (addressed using 32 bits) in + indirect mode, but the addressable space in + memory-mapped mode is limited to 256MB. If DFM = 1, + FSIZE indicates the total capacity of the two Flash + memories together. This field can be modified only + when BUSY = 0. + 16 + 5 + + + + + SR + SR + QUADSPI status register + 0x8 + 0x20 + read-only + 0x00000000 + + + TEF + Transfer error flag This bit is set in + indirect mode when an invalid address is being + accessed in indirect mode. It is cleared by writing 1 + to CTEF. + 0 + 1 + + + TCF + Transfer complete flag This bit is set + in indirect mode when the programmed number of data + has been transferred or in any mode when the transfer + has been aborted.It is cleared by writing 1 to + CTCF. + 1 + 1 + + + FTF + FIFO threshold flag In indirect mode, + this bit is set when the FIFO threshold has been + reached, or if there is any data left in the FIFO + after reads from the Flash memory are complete. It is + cleared automatically as soon as threshold condition + is no longer true. In automatic polling mode this bit + is set every time the status register is read, and + the bit is cleared when the data register is + read. + 2 + 1 + + + SMF + Status match flag This bit is set in + automatic polling mode when the unmasked received + data matches the corresponding bits in the match + register (QUADSPI_PSMAR). It is cleared by writing 1 + to CSMF. + 3 + 1 + + + TOF + Timeout flag This bit is set when + timeout occurs. It is cleared by writing 1 to + CTOF. + 4 + 1 + + + BUSY + Busy This bit is set when an operation + is on going. This bit clears automatically when the + operation with the Flash memory is finished and the + FIFO is empty. + 5 + 1 + + + FLEVEL + FIFO level This field gives the number + of valid bytes which are being held in the FIFO. + FLEVEL = 0 when the FIFO is empty, and 16 when it is + full. In memory-mapped mode and in automatic status + polling mode, FLEVEL is zero. + 8 + 6 + + + + + FCR + FCR + QUADSPI flag clear register + 0xC + 0x20 + read-write + 0x00000000 + + + CTEF + Clear transfer error flag Writing 1 + clears the TEF flag in the QUADSPI_SR + register + 0 + 1 + + + CTCF + Clear transfer complete flag Writing 1 + clears the TCF flag in the QUADSPI_SR + register + 1 + 1 + + + CSMF + Clear status match flag Writing 1 clears + the SMF flag in the QUADSPI_SR register + 3 + 1 + + + CTOF + Clear timeout flag Writing 1 clears the + TOF flag in the QUADSPI_SR register + 4 + 1 + + + + + DLR + DLR + QUADSPI data length register + 0x10 + 0x20 + read-write + 0x00000000 + + + DL + Data length Number of data to be + retrieved (value+1) in indirect and status-polling + modes. A value no greater than 3 (indicating 4 bytes) + should be used for status-polling mode. All 1s in + indirect mode means undefined length, where QUADSPI + will continue until the end of memory, as defined by + FSIZE. 0x0000_0000: 1 byte is to be transferred + 0x0000_0001: 2 bytes are to be transferred + 0x0000_0002: 3 bytes are to be transferred + 0x0000_0003: 4 bytes are to be transferred ... + 0xFFFF_FFFD: 4,294,967,294 (4G-2) bytes are to be + transferred 0xFFFF_FFFE: 4,294,967,295 (4G-1) bytes + are to be transferred 0xFFFF_FFFF: undefined length + -- all bytes until the end of Flash memory (as + defined by FSIZE) are to be transferred. Continue + reading indefinitely if FSIZE = 0x1F. DL[0] is stuck + at 1 in dual-flash mode (DFM = 1) even when 0 is + written to this bit, thus assuring that each access + transfers an even number of bytes. This field has no + effect when in memory-mapped mode (FMODE = 10). This + field can be written only when BUSY = + 0. + 0 + 32 + + + + + CCR + CCR + QUADSPI communication configuration + register + 0x14 + 0x20 + read-write + 0x00000000 + + + INSTRUCTION + Instruction Instruction to be send to + the external SPI device. This field can be written + only when BUSY = 0. + 0 + 8 + + + IMODE + Instruction mode This field defines the + instruction phase mode of operation: This field can + be written only when BUSY = 0. + 8 + 2 + + + ADMODE + Address mode This field defines the + address phase mode of operation: This field can be + written only when BUSY = 0. + 10 + 2 + + + ADSIZE + Address size This bit defines address + size: This field can be written only when BUSY = + 0. + 12 + 2 + + + ABMODE + Alternate bytes mode This field defines + the alternate-bytes phase mode of operation: This + field can be written only when BUSY = + 0. + 14 + 2 + + + ABSIZE + Alternate bytes size This bit defines + alternate bytes size: This field can be written only + when BUSY = 0. + 16 + 2 + + + DCYC + Number of dummy cycles This field + defines the duration of the dummy phase. In both SDR + and DDR modes, it specifies a number of CLK cycles + (0-31). This field can be written only when BUSY = + 0. + 18 + 5 + + + DMODE + Data mode This field defines the data + phases mode of operation: This field also determines + the dummy phase mode of operation. This field can be + written only when BUSY = 0. + 24 + 2 + + + FMODE + Functional mode This field defines the + QUADSPI functional mode of operation. If DMAEN = 1 + already, then the DMA controller for the + corresponding channel must be disabled before + changing the FMODE value. This field can be written + only when BUSY = 0. + 26 + 2 + + + SIOO + Send instruction only once mode See + Section15.3.11: Sending the instruction only once on + page13. This bit has no effect when IMODE = 00. This + field can be written only when BUSY = + 0. + 28 + 1 + + + DHHC + DDR hold Delay the data output by 1/4 of + the QUADSPI output clock cycle in DDR mode: This + feature is only active in DDR mode. This field can be + written only when BUSY = 0. + 30 + 1 + + + DDRM + Double data rate mode This bit sets the + DDR mode for the address, alternate byte and data + phase: This field can be written only when BUSY = + 0. + 31 + 1 + + + + + AR + AR + QUADSPI address register + 0x18 + 0x20 + read-write + 0x00000000 + + + ADDRESS + [31 0]: Address Address to be send to + the external Flash memory Writes to this field are + ignored when BUSY = 0 or when FMODE = 11 + (memory-mapped mode). In dual flash mode, ADDRESS[0] + is automatically stuck to 0 as the address should + always be even + 0 + 32 + + + + + ABR + ABR + QUADSPI alternate bytes + registers + 0x1C + 0x20 + read-write + 0x00000000 + + + ALTERNATE + Alternate Bytes Optional data to be send + to the external SPI device right after the address. + This field can be written only when BUSY = + 0. + 0 + 32 + + + + + DR + DR + QUADSPI data register + 0x20 + 0x20 + read-write + 0x00000000 + + + DATA + Data Data to be sent/received to/from + the external SPI device. In indirect write mode, data + written to this register is stored on the FIFO before + it is sent to the Flash memory during the data phase. + If the FIFO is too full, a write operation is stalled + until the FIFO has enough space to accept the amount + of data being written. In indirect read mode, reading + this register gives (via the FIFO) the data which was + received from the Flash memory. If the FIFO does not + have as many bytes as requested by the read operation + and if BUSY=1, the read operation is stalled until + enough data is present or until the transfer is + complete, whichever happens first. In automatic + polling mode, this register contains the last data + read from the Flash memory (without masking). Word, + halfword, and byte accesses to this register are + supported. In indirect write mode, a byte write adds + 1 byte to the FIFO, a halfword write 2, and a word + write 4. Similarly, in indirect read mode, a byte + read removes 1 byte from the FIFO, a halfword read 2, + and a word read 4. Accesses in indirect mode must be + aligned to the bottom of this register: a byte read + must read DATA[7:0] and a halfword read must read + DATA[15:0]. + 0 + 32 + + + + + PSMKR + PSMKR + QUADSPI polling status mask + register + 0x24 + 0x20 + read-write + 0x00000000 + + + MASK + Status mask Mask to be applied to the + status bytes received in polling mode. For bit n: + This field can be written only when BUSY = + 0. + 0 + 32 + + + + + PSMAR + PSMAR + QUADSPI polling status match + register + 0x28 + 0x20 + read-write + 0x00000000 + + + MATCH + Status match Value to be compared with + the masked status register to get a match. This field + can be written only when BUSY = 0. + 0 + 32 + + + + + PIR + PIR + QUADSPI polling interval + register + 0x2C + 0x20 + read-write + 0x00000000 + + + INTERVAL + Polling interval Number of CLK cycles + between to read during automatic polling phases. This + field can be written only when BUSY = + 0. + 0 + 16 + + + + + LPTR + LPTR + QUADSPI low-power timeout + register + 0x30 + 0x20 + read-write + 0x00000000 + + + TIMEOUT + Timeout period After each access in + memory-mapped mode, the QUADSPI prefetches the + subsequent bytes and holds these bytes in the FIFO. + This field indicates how many CLK cycles the QUADSPI + waits after the FIFO becomes full until it raises + nCS, putting the Flash memory in a lower-consumption + state. This field can be written only when BUSY = + 0. + 0 + 16 + + + + + + + RNG + RNG + RNG + 0x48021800 + + 0x0 + 0x400 + registers + + + + CR + CR + RNG control register + 0x0 + 0x20 + read-write + 0x00000000 + + + RNGEN + Random number generator + enable + 2 + 1 + + + IE + Interrupt enable + 3 + 1 + + + CED + Clock error detection Note: The clock + error detection can be used only when ck_rc48 or + ck_pll1_q (ck_pll1_q = 48MHz) source is selected + otherwise, CED bit must be equal to 1. The clock + error detection cannot be enabled nor disabled on the + fly when RNG peripheral is enabled, to enable or + disable CED the RNG must be disabled. + 5 + 1 + + + + + SR + SR + RNG status register + 0x4 + 0x20 + 0x00000000 + + + DRDY + Data ready Note: If IE=1 in RNG_CR, an + interrupt is generated when DRDY=1. It can rise when + the peripheral is disabled. When the output buffer + becomes empty (after reading RNG_DR), this bit + returns to 0 until a new random value is + generated. + 0 + 1 + read-only + + + CECS + Clock error current status Note: This + bit is meaningless if CED (Clock error detection) bit + in RNG_CR is equal to 1. + 1 + 1 + read-only + + + SECS + Seed error current status ** More than + 64 consecutive bits at the same value (0 or 1) ** + More than 32 consecutive alternances of 0 and 1 + (0101010101...01) + 2 + 1 + read-only + + + CEIS + Clock error interrupt status This bit is + set at the same time as CECS. It is cleared by + writing it to 0. An interrupt is pending if IE = 1 in + the RNG_CR register. Note: This bit is meaningless if + CED (Clock error detection) bit in RNG_CR is equal to + 1. + 5 + 1 + read-write + + + SEIS + Seed error interrupt status This bit is + set at the same time as SECS. It is cleared by + writing it to 0. ** More than 64 consecutive bits at + the same value (0 or 1) ** More than 32 consecutive + alternances of 0 and 1 (0101010101...01) An interrupt + is pending if IE = 1 in the RNG_CR + register. + 6 + 1 + read-write + + + + + DR + DR + The RNG_DR register is a read-only register + that delivers a 32-bit random value when read. The + content of this register is valid when DRDY= 1, even if + RNGEN=0. + 0x8 + 0x20 + read-only + 0x00000000 + + + RNDATA + Random data 32-bit random data which are + valid when DRDY=1. + 0 + 32 + + + + + + + RTC + RTC + RTC + 0x58004000 + + 0x0 + 0x400 + registers + + + RTC_TAMP_STAMP_CSS_LSE + RTC tamper, timestamp + 2 + + + RTC_WKUP + RTC Wakeup interrupt + 3 + + + + RTC_TR + RTC_TR + The RTC_TR is the calendar time shadow + register. This register must be written in initialization + mode only. Refer to Calendar initialization and + configuration on page9 and Reading the calendar on + page10.This register is write protected. The write access + procedure is described in RTC register write protection + on page9. + 0x0 + 0x20 + read-write + 0x00000000 + + + SU + Second units in BCD format + 0 + 4 + + + ST + Second tens in BCD format + 4 + 3 + + + MNU + Minute units in BCD format + 8 + 4 + + + MNT + Minute tens in BCD format + 12 + 3 + + + HU + Hour units in BCD format + 16 + 4 + + + HT + Hour tens in BCD format + 20 + 2 + + + PM + AM/PM notation + 22 + 1 + + + + + RTC_DR + RTC_DR + The RTC_DR is the calendar date shadow + register. This register must be written in initialization + mode only. Refer to Calendar initialization and + configuration on page9 and Reading the calendar on + page10.This register is write protected. The write access + procedure is described in RTC register write protection + on page9. + 0x4 + 0x20 + read-write + 0x00002101 + + + DU + Date units in BCD format + 0 + 4 + + + DT + Date tens in BCD format + 4 + 2 + + + MU + Month units in BCD format + 8 + 4 + + + MT + Month tens in BCD format + 12 + 1 + + + WDU + Week day units + 13 + 3 + + + YU + Year units in BCD format + 16 + 4 + + + YT + Year tens in BCD format + 20 + 4 + + + + + RTC_CR + RTC_CR + RTC control register + 0x8 + 0x20 + 0x00000000 + + + WUCKSEL + Wakeup clock selection + 0 + 3 + read-write + + + TSEDGE + Time-stamp event active edge TSE must be + reset when TSEDGE is changed to avoid unwanted TSF + setting. + 3 + 1 + read-write + + + REFCKON + RTC_REFIN reference clock detection + enable (50 or 60Hz) Note: PREDIV_S must be + 0x00FF. + 4 + 1 + read-write + + + BYPSHAD + Bypass the shadow registers Note: If the + frequency of the APB clock is less than seven times + the frequency of RTCCLK, BYPSHAD must be set to + 1. + 5 + 1 + read-write + + + FMT + Hour format + 6 + 1 + read-write + + + ALRAE + Alarm A enable + 8 + 1 + read-write + + + ALRBE + Alarm B enable + 9 + 1 + read-write + + + WUTE + Wakeup timer enable + 10 + 1 + read-write + + + TSE + timestamp enable + 11 + 1 + read-write + + + ALRAIE + Alarm A interrupt enable + 12 + 1 + read-write + + + ALRBIE + Alarm B interrupt enable + 13 + 1 + read-write + + + WUTIE + Wakeup timer interrupt + enable + 14 + 1 + read-write + + + TSIE + Time-stamp interrupt + enable + 15 + 1 + read-write + + + ADD1H + Add 1 hour (summer time change) When + this bit is set outside initialization mode, 1 hour + is added to the calendar time. This bit is always + read as 0. + 16 + 1 + write-only + + + SUB1H + Subtract 1 hour (winter time change) + When this bit is set outside initialization mode, 1 + hour is subtracted to the calendar time if the + current hour is not 0. This bit is always read as 0. + Setting this bit has no effect when current hour is + 0. + 17 + 1 + write-only + + + BKP + Backup This bit can be written by the + user to memorize whether the daylight saving time + change has been performed or not. + 18 + 1 + read-write + + + COSEL + Calibration output selection When COE=1, + this bit selects which signal is output on RTC_CALIB. + These frequencies are valid for RTCCLK at 32.768 kHz + and prescalers at their default values (PREDIV_A=127 + and PREDIV_S=255). Refer to Section24.3.15: + Calibration clock output + 19 + 1 + read-write + + + POL + Output polarity This bit is used to + configure the polarity of RTC_ALARM + output + 20 + 1 + read-write + + + OSEL + Output selection These bits are used to + select the flag to be routed to RTC_ALARM + output + 21 + 2 + read-write + + + COE + Calibration output enable This bit + enables the RTC_CALIB output + 23 + 1 + read-write + + + ITSE + timestamp on internal event + enable + 24 + 1 + read-write + + + + + RTC_ISR + RTC_ISR + This register is write protected (except for + RTC_ISR[13:8] bits). The write access procedure is + described in RTC register write protection on + page9. + 0xC + 0x20 + 0x00000007 + + + ALRAWF + Alarm A write flag This bit is set by + hardware when Alarm A values can be changed, after + the ALRAE bit has been set to 0 in RTC_CR. It is + cleared by hardware in initialization + mode. + 0 + 1 + read-only + + + ALRBWF + Alarm B write flag This bit is set by + hardware when Alarm B values can be changed, after + the ALRBE bit has been set to 0 in RTC_CR. It is + cleared by hardware in initialization + mode. + 1 + 1 + read-only + + + WUTWF + Wakeup timer write flag This bit is set + by hardware up to 2 RTCCLK cycles after the WUTE bit + has been set to 0 in RTC_CR, and is cleared up to 2 + RTCCLK cycles after the WUTE bit has been set to 1. + The wakeup timer values can be changed when WUTE bit + is cleared and WUTWF is set. + 2 + 1 + read-only + + + SHPF + Shift operation pending This flag is set + by hardware as soon as a shift operation is initiated + by a write to the RTC_SHIFTR register. It is cleared + by hardware when the corresponding shift operation + has been executed. Writing to the SHPF bit has no + effect. + 3 + 1 + read-only + + + INITS + Initialization status flag This bit is + set by hardware when the calendar year field is + different from 0 (Backup domain reset + state). + 4 + 1 + read-only + + + RSF + Registers synchronization flag This bit + is set by hardware each time the calendar registers + are copied into the shadow registers (RTC_SSRx, + RTC_TRx and RTC_DRx). This bit is cleared by hardware + in initialization mode, while a shift operation is + pending (SHPF=1), or when in bypass shadow register + mode (BYPSHAD=1). This bit can also be cleared by + software. It is cleared either by software or by + hardware in initialization mode. + 5 + 1 + read-write + + + INITF + Initialization flag When this bit is set + to 1, the RTC is in initialization state, and the + time, date and prescaler registers can be + updated. + 6 + 1 + read-only + + + INIT + Initialization mode + 7 + 1 + read-write + + + ALRAF + Alarm A flag This flag is set by + hardware when the time/date registers (RTC_TR and + RTC_DR) match the Alarm A register (RTC_ALRMAR). This + flag is cleared by software by writing + 0. + 8 + 1 + read-write + + + ALRBF + Alarm B flag This flag is set by + hardware when the time/date registers (RTC_TR and + RTC_DR) match the Alarm B register (RTC_ALRMBR). This + flag is cleared by software by writing + 0. + 9 + 1 + read-write + + + WUTF + Wakeup timer flag This flag is set by + hardware when the wakeup auto-reload counter reaches + 0. This flag is cleared by software by writing 0. + This flag must be cleared by software at least 1.5 + RTCCLK periods before WUTF is set to 1 + again. + 10 + 1 + read-write + + + TSF + Time-stamp flag This flag is set by + hardware when a time-stamp event occurs. This flag is + cleared by software by writing 0. + 11 + 1 + read-write + + + TSOVF + Time-stamp overflow flag This flag is + set by hardware when a time-stamp event occurs while + TSF is already set. This flag is cleared by software + by writing 0. It is recommended to check and then + clear TSOVF only after clearing the TSF bit. + Otherwise, an overflow might not be noticed if a + time-stamp event occurs immediately before the TSF + bit is cleared. + 12 + 1 + read-write + + + TAMP1F + RTC_TAMP1 detection flag This flag is + set by hardware when a tamper detection event is + detected on the RTC_TAMP1 input. It is cleared by + software writing 0 + 13 + 1 + read-write + + + TAMP2F + RTC_TAMP2 detection flag This flag is + set by hardware when a tamper detection event is + detected on the RTC_TAMP2 input. It is cleared by + software writing 0 + 14 + 1 + read-write + + + TAMP3F + RTC_TAMP3 detection flag This flag is + set by hardware when a tamper detection event is + detected on the RTC_TAMP3 input. It is cleared by + software writing 0 + 15 + 1 + read-write + + + RECALPF + Recalibration pending Flag The RECALPF + status flag is automatically set to 1 when software + writes to the RTC_CALR register, indicating that the + RTC_CALR register is blocked. When the new + calibration settings are taken into account, this bit + returns to 0. Refer to Re-calibration + on-the-fly. + 16 + 1 + read-only + + + ITSF + Internal tTime-stamp flag + 17 + 1 + read-write + + + + + RTC_PRER + RTC_PRER + This register must be written in + initialization mode only. The initialization must be + performed in two separate write accesses. Refer to + Calendar initialization and configuration on page9.This + register is write protected. The write access procedure + is described in RTC register write protection on + page9. + 0x10 + 0x20 + read-write + 0x007F00FF + + + PREDIV_S + Synchronous prescaler factor This is the + synchronous division factor: ck_spre frequency = + ck_apre frequency/(PREDIV_S+1) + 0 + 15 + + + PREDIV_A + Asynchronous prescaler factor This is + the asynchronous division factor: ck_apre frequency = + RTCCLK frequency/(PREDIV_A+1) + 16 + 7 + + + + + RTC_WUTR + RTC_WUTR + This register can be written only when WUTWF + is set to 1 in RTC_ISR.This register is write protected. + The write access procedure is described in RTC register + write protection on page9. + 0x14 + 0x20 + read-write + 0x0000FFFF + + + WUT + Wakeup auto-reload value bits When the + wakeup timer is enabled (WUTE set to 1), the WUTF + flag is set every (WUT[15:0] + 1) ck_wut cycles. The + ck_wut period is selected through WUCKSEL[2:0] bits + of the RTC_CR register When WUCKSEL[2] = 1, the + wakeup timer becomes 17-bits and WUCKSEL[1] + effectively becomes WUT[16] the most-significant bit + to be reloaded into the timer. The first assertion of + WUTF occurs (WUT+1) ck_wut cycles after WUTE is set. + Setting WUT[15:0] to 0x0000 with WUCKSEL[2:0] =011 + (RTCCLK/2) is forbidden. + 0 + 16 + + + + + RTC_ALRMAR + RTC_ALRMAR + This register can be written only when + ALRAWF is set to 1 in RTC_ISR, or in initialization + mode.This register is write protected. The write access + procedure is described in RTC register write protection + on page9. + 0x1C + 0x20 + read-write + 0x00000000 + + + SU + Second units in BCD + format. + 0 + 4 + + + ST + Second tens in BCD format. + 4 + 3 + + + MSK1 + Alarm A seconds mask + 7 + 1 + + + MNU + Minute units in BCD + format. + 8 + 4 + + + MNT + Minute tens in BCD format. + 12 + 3 + + + MSK2 + Alarm A minutes mask + 15 + 1 + + + HU + Hour units in BCD format. + 16 + 4 + + + HT + Hour tens in BCD format. + 20 + 2 + + + PM + AM/PM notation + 22 + 1 + + + MSK3 + Alarm A hours mask + 23 + 1 + + + DU + Date units or day in BCD + format. + 24 + 4 + + + DT + Date tens in BCD format. + 28 + 2 + + + WDSEL + Week day selection + 30 + 1 + + + MSK4 + Alarm A date mask + 31 + 1 + + + + + RTC_ALRMBR + RTC_ALRMBR + This register can be written only when + ALRBWF is set to 1 in RTC_ISR, or in initialization + mode.This register is write protected. The write access + procedure is described in RTC register write protection + on page9. + 0x20 + 0x20 + read-write + 0x00000000 + + + SU + Second units in BCD format + 0 + 4 + + + ST + Second tens in BCD format + 4 + 3 + + + MSK1 + Alarm B seconds mask + 7 + 1 + + + MNU + Minute units in BCD format + 8 + 4 + + + MNT + Minute tens in BCD format + 12 + 3 + + + MSK2 + Alarm B minutes mask + 15 + 1 + + + HU + Hour units in BCD format + 16 + 4 + + + HT + Hour tens in BCD format + 20 + 2 + + + PM + AM/PM notation + 22 + 1 + + + MSK3 + Alarm B hours mask + 23 + 1 + + + DU + Date units or day in BCD + format + 24 + 4 + + + DT + Date tens in BCD format + 28 + 2 + + + WDSEL + Week day selection + 30 + 1 + + + MSK4 + Alarm B date mask + 31 + 1 + + + + + RTC_WPR + RTC_WPR + RTC write protection register + 0x24 + 0x20 + write-only + 0x00000000 + + + KEY + Write protection key This byte is + written by software. Reading this byte always returns + 0x00. Refer to RTC register write protection for a + description of how to unlock RTC register write + protection. + 0 + 8 + + + + + RTC_SSR + RTC_SSR + RTC sub second register + 0x28 + 0x20 + read-only + 0x00000000 + + + SS + Sub second value SS[15:0] is the value + in the synchronous prescaler counter. The fraction of + a second is given by the formula below: Second + fraction = (PREDIV_S - SS) / (PREDIV_S + 1) Note: SS + can be larger than PREDIV_S only after a shift + operation. In that case, the correct time/date is one + second less than as indicated by + RTC_TR/RTC_DR. + 0 + 16 + + + + + RTC_SHIFTR + RTC_SHIFTR + This register is write protected. The write + access procedure is described in RTC register write + protection on page9. + 0x2C + 0x20 + write-only + 0x00000000 + + + SUBFS + Subtract a fraction of a second These + bits are write only and is always read as zero. + Writing to this bit has no effect when a shift + operation is pending (when SHPF=1, in RTC_ISR). The + value which is written to SUBFS is added to the + synchronous prescaler counter. Since this counter + counts down, this operation effectively subtracts + from (delays) the clock by: Delay (seconds) = SUBFS / + (PREDIV_S + 1) A fraction of a second can effectively + be added to the clock (advancing the clock) when the + ADD1S function is used in conjunction with SUBFS, + effectively advancing the clock by: Advance (seconds) + = (1 - (SUBFS / (PREDIV_S + 1))). Note: Writing to + SUBFS causes RSF to be cleared. Software can then + wait until RSF=1 to be sure that the shadow registers + have been updated with the shifted + time. + 0 + 15 + + + ADD1S + Add one second This bit is write only + and is always read as zero. Writing to this bit has + no effect when a shift operation is pending (when + SHPF=1, in RTC_ISR). This function is intended to be + used with SUBFS (see description below) in order to + effectively add a fraction of a second to the clock + in an atomic operation. + 31 + 1 + + + + + RTC_TSTR + RTC_TSTR + The content of this register is valid only + when TSF is set to 1 in RTC_ISR. It is cleared when TSF + bit is reset. + 0x30 + 0x20 + read-only + 0x00000000 + + + SU + Second units in BCD + format. + 0 + 4 + + + ST + Second tens in BCD format. + 4 + 3 + + + MNU + Minute units in BCD + format. + 8 + 4 + + + MNT + Minute tens in BCD format. + 12 + 3 + + + HU + Hour units in BCD format. + 16 + 4 + + + HT + Hour tens in BCD format. + 20 + 2 + + + PM + AM/PM notation + 22 + 1 + + + + + RTC_TSDR + RTC_TSDR + The content of this register is valid only + when TSF is set to 1 in RTC_ISR. It is cleared when TSF + bit is reset. + 0x34 + 0x20 + read-only + 0x00000000 + + + DU + Date units in BCD format + 0 + 4 + + + DT + Date tens in BCD format + 4 + 2 + + + MU + Month units in BCD format + 8 + 4 + + + MT + Month tens in BCD format + 12 + 1 + + + WDU + Week day units + 13 + 3 + + + + + RTC_TSSSR + RTC_TSSSR + The content of this register is valid only + when RTC_ISR/TSF is set. It is cleared when the + RTC_ISR/TSF bit is reset. + 0x38 + 0x20 + read-only + 0x00000000 + + + SS + Sub second value SS[15:0] is the value + of the synchronous prescaler counter when the + timestamp event occurred. + 0 + 16 + + + + + RTC_CALR + RTC_CALR + This register is write protected. The write + access procedure is described in RTC register write + protection on page9. + 0x3C + 0x20 + read-write + 0x00000000 + + + CALM + Calibration minus The frequency of the + calendar is reduced by masking CALM out of 220 RTCCLK + pulses (32 seconds if the input frequency is 32768 + Hz). This decreases the frequency of the calendar + with a resolution of 0.9537 ppm. To increase the + frequency of the calendar, this feature should be + used in conjunction with CALP. See Section24.3.12: + RTC smooth digital calibration on + page13. + 0 + 9 + + + CALW16 + Use a 16-second calibration cycle period + When CALW16 is set to 1, the 16-second calibration + cycle period is selected.This bit must not be set to + 1 if CALW8=1. Note: CALM[0] is stuck at 0 when + CALW16= 1. Refer to Section24.3.12: RTC smooth + digital calibration. + 13 + 1 + + + CALW8 + Use an 8-second calibration cycle period + When CALW8 is set to 1, the 8-second calibration + cycle period is selected. Note: CALM[1:0] are stuck + at 00; when CALW8= 1. Refer to Section24.3.12: RTC + smooth digital calibration. + 14 + 1 + + + CALP + Increase frequency of RTC by 488.5 ppm + This feature is intended to be used in conjunction + with CALM, which lowers the frequency of the calendar + with a fine resolution. if the input frequency is + 32768 Hz, the number of RTCCLK pulses added during a + 32-second window is calculated as follows: (512 * + CALP) - CALM. Refer to Section24.3.12: RTC smooth + digital calibration. + 15 + 1 + + + + + RTC_TAMPCR + RTC_TAMPCR + RTC tamper and alternate function + configuration register + 0x40 + 0x20 + read-write + 0x00000000 + + + TAMP1E + RTC_TAMP1 input detection + enable + 0 + 1 + + + TAMP1TRG + Active level for RTC_TAMP1 input If + TAMPFLT != 00 if TAMPFLT = 00: + 1 + 1 + + + TAMPIE + Tamper interrupt enable + 2 + 1 + + + TAMP2E + RTC_TAMP2 input detection + enable + 3 + 1 + + + TAMP2TRG + Active level for RTC_TAMP2 input if + TAMPFLT != 00: if TAMPFLT = 00: + 4 + 1 + + + TAMP3E + RTC_TAMP3 detection enable + 5 + 1 + + + TAMP3TRG + Active level for RTC_TAMP3 input if + TAMPFLT != 00: if TAMPFLT = 00: + 6 + 1 + + + TAMPTS + Activate timestamp on tamper detection + event TAMPTS is valid even if TSE=0 in the RTC_CR + register. + 7 + 1 + + + TAMPFREQ + Tamper sampling frequency Determines the + frequency at which each of the RTC_TAMPx inputs are + sampled. + 8 + 3 + + + TAMPFLT + RTC_TAMPx filter count These bits + determines the number of consecutive samples at the + specified level (TAMP*TRG) needed to activate a + Tamper event. TAMPFLT is valid for each of the + RTC_TAMPx inputs. + 11 + 2 + + + TAMPPRCH + RTC_TAMPx precharge duration These bit + determines the duration of time during which the + pull-up/is activated before each sample. TAMPPRCH is + valid for each of the RTC_TAMPx inputs. + 13 + 2 + + + TAMPPUDIS + RTC_TAMPx pull-up disable This bit + determines if each of the RTC_TAMPx pins are + pre-charged before each sample. + 15 + 1 + + + TAMP1IE + Tamper 1 interrupt enable + 16 + 1 + + + TAMP1NOERASE + Tamper 1 no erase + 17 + 1 + + + TAMP1MF + Tamper 1 mask flag + 18 + 1 + + + TAMP2IE + Tamper 2 interrupt enable + 19 + 1 + + + TAMP2NOERASE + Tamper 2 no erase + 20 + 1 + + + TAMP2MF + Tamper 2 mask flag + 21 + 1 + + + TAMP3IE + Tamper 3 interrupt enable + 22 + 1 + + + TAMP3NOERASE + Tamper 3 no erase + 23 + 1 + + + TAMP3MF + Tamper 3 mask flag + 24 + 1 + + + + + RTC_ALRMASSR + RTC_ALRMASSR + This register can be written only when ALRAE + is reset in RTC_CR register, or in initialization + mode.This register is write protected. The write access + procedure is described in RTC register write protection + on page9 + 0x44 + 0x20 + read-write + 0x00000000 + + + SS + Sub seconds value This value is compared + with the contents of the synchronous prescaler + counter to determine if Alarm A is to be activated. + Only bits 0 up MASKSS-1 are compared. + 0 + 15 + + + MASKSS + Mask the most-significant bits starting + at this bit ... The overflow bits of the synchronous + counter (bits 15) is never compared. This bit can be + different from 0 only after a shift + operation. + 24 + 4 + + + + + RTC_ALRMBSSR + RTC_ALRMBSSR + This register can be written only when ALRBE + is reset in RTC_CR register, or in initialization + mode.This register is write protected.The write access + procedure is described in Section: RTC register write + protection. + 0x48 + 0x20 + read-write + 0x00000000 + + + SS + Sub seconds value This value is compared + with the contents of the synchronous prescaler + counter to determine if Alarm B is to be activated. + Only bits 0 up to MASKSS-1 are + compared. + 0 + 15 + + + MASKSS + Mask the most-significant bits starting + at this bit ... The overflow bits of the synchronous + counter (bits 15) is never compared. This bit can be + different from 0 only after a shift + operation. + 24 + 4 + + + + + RTC_BKP0R + RTC_BKP0R + RTC backup registers + 0x50 + 0x20 + read-write + 0x00000000 + + + BKP + The application can write or read data + to and from these registers. They are powered-on by + VBAT when VDD is switched off, so that they are not + reset by System reset, and their contents remain + valid when the device operates in low-power mode. + This register is reset on a tamper detection event, + as long as TAMPxF=1. or when the Flash readout + protection is disabled. + 0 + 32 + + + + + RTC_BKP1R + RTC_BKP1R + RTC backup registers + 0x54 + 0x20 + read-write + 0x00000000 + + + BKP + The application can write or read data + to and from these registers. They are powered-on by + VBAT when VDD is switched off, so that they are not + reset by System reset, and their contents remain + valid when the device operates in low-power mode. + This register is reset on a tamper detection event, + as long as TAMPxF=1. or when the Flash readout + protection is disabled. + 0 + 32 + + + + + RTC_BKP2R + RTC_BKP2R + RTC backup registers + 0x58 + 0x20 + read-write + 0x00000000 + + + BKP + The application can write or read data + to and from these registers. They are powered-on by + VBAT when VDD is switched off, so that they are not + reset by System reset, and their contents remain + valid when the device operates in low-power mode. + This register is reset on a tamper detection event, + as long as TAMPxF=1. or when the Flash readout + protection is disabled. + 0 + 32 + + + + + RTC_BKP3R + RTC_BKP3R + RTC backup registers + 0x5C + 0x20 + read-write + 0x00000000 + + + BKP + The application can write or read data + to and from these registers. They are powered-on by + VBAT when VDD is switched off, so that they are not + reset by System reset, and their contents remain + valid when the device operates in low-power mode. + This register is reset on a tamper detection event, + as long as TAMPxF=1. or when the Flash readout + protection is disabled. + 0 + 32 + + + + + RTC_BKP4R + RTC_BKP4R + RTC backup registers + 0x60 + 0x20 + read-write + 0x00000000 + + + BKP + The application can write or read data + to and from these registers. They are powered-on by + VBAT when VDD is switched off, so that they are not + reset by System reset, and their contents remain + valid when the device operates in low-power mode. + This register is reset on a tamper detection event, + as long as TAMPxF=1. or when the Flash readout + protection is disabled. + 0 + 32 + + + + + RTC_BKP5R + RTC_BKP5R + RTC backup registers + 0x64 + 0x20 + read-write + 0x00000000 + + + BKP + The application can write or read data + to and from these registers. They are powered-on by + VBAT when VDD is switched off, so that they are not + reset by System reset, and their contents remain + valid when the device operates in low-power mode. + This register is reset on a tamper detection event, + as long as TAMPxF=1. or when the Flash readout + protection is disabled. + 0 + 32 + + + + + RTC_BKP6R + RTC_BKP6R + RTC backup registers + 0x68 + 0x20 + read-write + 0x00000000 + + + BKP + The application can write or read data + to and from these registers. They are powered-on by + VBAT when VDD is switched off, so that they are not + reset by System reset, and their contents remain + valid when the device operates in low-power mode. + This register is reset on a tamper detection event, + as long as TAMPxF=1. or when the Flash readout + protection is disabled. + 0 + 32 + + + + + RTC_BKP7R + RTC_BKP7R + RTC backup registers + 0x6C + 0x20 + read-write + 0x00000000 + + + BKP + The application can write or read data + to and from these registers. They are powered-on by + VBAT when VDD is switched off, so that they are not + reset by System reset, and their contents remain + valid when the device operates in low-power mode. + This register is reset on a tamper detection event, + as long as TAMPxF=1. or when the Flash readout + protection is disabled. + 0 + 32 + + + + + RTC_BKP8R + RTC_BKP8R + RTC backup registers + 0x70 + 0x20 + read-write + 0x00000000 + + + BKP + The application can write or read data + to and from these registers. They are powered-on by + VBAT when VDD is switched off, so that they are not + reset by System reset, and their contents remain + valid when the device operates in low-power mode. + This register is reset on a tamper detection event, + as long as TAMPxF=1. or when the Flash readout + protection is disabled. + 0 + 32 + + + + + RTC_BKP9R + RTC_BKP9R + RTC backup registers + 0x74 + 0x20 + read-write + 0x00000000 + + + BKP + The application can write or read data + to and from these registers. They are powered-on by + VBAT when VDD is switched off, so that they are not + reset by System reset, and their contents remain + valid when the device operates in low-power mode. + This register is reset on a tamper detection event, + as long as TAMPxF=1. or when the Flash readout + protection is disabled. + 0 + 32 + + + + + RTC_BKP10R + RTC_BKP10R + RTC backup registers + 0x78 + 0x20 + read-write + 0x00000000 + + + BKP + The application can write or read data + to and from these registers. They are powered-on by + VBAT when VDD is switched off, so that they are not + reset by System reset, and their contents remain + valid when the device operates in low-power mode. + This register is reset on a tamper detection event, + as long as TAMPxF=1. or when the Flash readout + protection is disabled. + 0 + 32 + + + + + RTC_BKP11R + RTC_BKP11R + RTC backup registers + 0x7C + 0x20 + read-write + 0x00000000 + + + BKP + The application can write or read data + to and from these registers. They are powered-on by + VBAT when VDD is switched off, so that they are not + reset by System reset, and their contents remain + valid when the device operates in low-power mode. + This register is reset on a tamper detection event, + as long as TAMPxF=1. or when the Flash readout + protection is disabled. + 0 + 32 + + + + + RTC_BKP12R + RTC_BKP12R + RTC backup registers + 0x80 + 0x20 + read-write + 0x00000000 + + + BKP + The application can write or read data + to and from these registers. They are powered-on by + VBAT when VDD is switched off, so that they are not + reset by System reset, and their contents remain + valid when the device operates in low-power mode. + This register is reset on a tamper detection event, + as long as TAMPxF=1. or when the Flash readout + protection is disabled. + 0 + 32 + + + + + RTC_BKP13R + RTC_BKP13R + RTC backup registers + 0x84 + 0x20 + read-write + 0x00000000 + + + BKP + The application can write or read data + to and from these registers. They are powered-on by + VBAT when VDD is switched off, so that they are not + reset by System reset, and their contents remain + valid when the device operates in low-power mode. + This register is reset on a tamper detection event, + as long as TAMPxF=1. or when the Flash readout + protection is disabled. + 0 + 32 + + + + + RTC_BKP14R + RTC_BKP14R + RTC backup registers + 0x88 + 0x20 + read-write + 0x00000000 + + + BKP + The application can write or read data + to and from these registers. They are powered-on by + VBAT when VDD is switched off, so that they are not + reset by System reset, and their contents remain + valid when the device operates in low-power mode. + This register is reset on a tamper detection event, + as long as TAMPxF=1. or when the Flash readout + protection is disabled. + 0 + 32 + + + + + RTC_BKP15R + RTC_BKP15R + RTC backup registers + 0x8C + 0x20 + read-write + 0x00000000 + + + BKP + The application can write or read data + to and from these registers. They are powered-on by + VBAT when VDD is switched off, so that they are not + reset by System reset, and their contents remain + valid when the device operates in low-power mode. + This register is reset on a tamper detection event, + as long as TAMPxF=1. or when the Flash readout + protection is disabled. + 0 + 32 + + + + + RTC_OR + RTC_OR + RTC option register + 0x4C + 0x20 + read-write + 0x00000000 + + + RTC_ALARM_TYPE + RTC_ALARM output type on + PC13 + 0 + 1 + + + RTC_OUT_RMP + RTC_OUT remap + 1 + 1 + + + + + RTC_BKP16R + RTC_BKP16R + RTC backup registers + 0x90 + 0x20 + read-write + 0x00000000 + + + BKP + The application can write or read data + to and from these registers. They are powered-on by + VBAT when VDD is switched off, so that they are not + reset by System reset, and their contents remain + valid when the device operates in low-power mode. + This register is reset on a tamper detection event, + as long as TAMPxF=1. or when the Flash readout + protection is disabled. + 0 + 32 + + + + + RTC_BKP17R + RTC_BKP17R + RTC backup registers + 0x94 + 0x20 + read-write + 0x00000000 + + + BKP + The application can write or read data + to and from these registers. They are powered-on by + VBAT when VDD is switched off, so that they are not + reset by System reset, and their contents remain + valid when the device operates in low-power mode. + This register is reset on a tamper detection event, + as long as TAMPxF=1. or when the Flash readout + protection is disabled. + 0 + 32 + + + + + RTC_BKP18R + RTC_BKP18R + RTC backup registers + 0x98 + 0x20 + read-write + 0x00000000 + + + BKP + The application can write or read data + to and from these registers. They are powered-on by + VBAT when VDD is switched off, so that they are not + reset by System reset, and their contents remain + valid when the device operates in low-power mode. + This register is reset on a tamper detection event, + as long as TAMPxF=1. or when the Flash readout + protection is disabled. + 0 + 32 + + + + + RTC_BKP19R + RTC_BKP19R + RTC backup registers + 0x9C + 0x20 + read-write + 0x00000000 + + + BKP + The application can write or read data + to and from these registers. They are powered-on by + VBAT when VDD is switched off, so that they are not + reset by System reset, and their contents remain + valid when the device operates in low-power mode. + This register is reset on a tamper detection event, + as long as TAMPxF=1. or when the Flash readout + protection is disabled. + 0 + 32 + + + + + RTC_BKP20R + RTC_BKP20R + RTC backup registers + 0xA0 + 0x20 + read-write + 0x00000000 + + + BKP + The application can write or read data + to and from these registers. They are powered-on by + VBAT when VDD is switched off, so that they are not + reset by System reset, and their contents remain + valid when the device operates in low-power mode. + This register is reset on a tamper detection event, + as long as TAMPxF=1. or when the Flash readout + protection is disabled. + 0 + 32 + + + + + RTC_BKP21R + RTC_BKP21R + RTC backup registers + 0xA4 + 0x20 + read-write + 0x00000000 + + + BKP + The application can write or read data + to and from these registers. They are powered-on by + VBAT when VDD is switched off, so that they are not + reset by System reset, and their contents remain + valid when the device operates in low-power mode. + This register is reset on a tamper detection event, + as long as TAMPxF=1. or when the Flash readout + protection is disabled. + 0 + 32 + + + + + RTC_BKP22R + RTC_BKP22R + RTC backup registers + 0xA8 + 0x20 + read-write + 0x00000000 + + + BKP + The application can write or read data + to and from these registers. They are powered-on by + VBAT when VDD is switched off, so that they are not + reset by System reset, and their contents remain + valid when the device operates in low-power mode. + This register is reset on a tamper detection event, + as long as TAMPxF=1. or when the Flash readout + protection is disabled. + 0 + 32 + + + + + RTC_BKP23R + RTC_BKP23R + RTC backup registers + 0xAC + 0x20 + read-write + 0x00000000 + + + BKP + The application can write or read data + to and from these registers. They are powered-on by + VBAT when VDD is switched off, so that they are not + reset by System reset, and their contents remain + valid when the device operates in low-power mode. + This register is reset on a tamper detection event, + as long as TAMPxF=1. or when the Flash readout + protection is disabled. + 0 + 32 + + + + + RTC_BKP24R + RTC_BKP24R + RTC backup registers + 0xB0 + 0x20 + read-write + 0x00000000 + + + BKP + The application can write or read data + to and from these registers. They are powered-on by + VBAT when VDD is switched off, so that they are not + reset by System reset, and their contents remain + valid when the device operates in low-power mode. + This register is reset on a tamper detection event, + as long as TAMPxF=1. or when the Flash readout + protection is disabled. + 0 + 32 + + + + + RTC_BKP25R + RTC_BKP25R + RTC backup registers + 0xB4 + 0x20 + read-write + 0x00000000 + + + BKP + The application can write or read data + to and from these registers. They are powered-on by + VBAT when VDD is switched off, so that they are not + reset by System reset, and their contents remain + valid when the device operates in low-power mode. + This register is reset on a tamper detection event, + as long as TAMPxF=1. or when the Flash readout + protection is disabled. + 0 + 32 + + + + + RTC_BKP26R + RTC_BKP26R + RTC backup registers + 0xB8 + 0x20 + read-write + 0x00000000 + + + BKP + The application can write or read data + to and from these registers. They are powered-on by + VBAT when VDD is switched off, so that they are not + reset by System reset, and their contents remain + valid when the device operates in low-power mode. + This register is reset on a tamper detection event, + as long as TAMPxF=1. or when the Flash readout + protection is disabled. + 0 + 32 + + + + + RTC_BKP27R + RTC_BKP27R + RTC backup registers + 0xBC + 0x20 + read-write + 0x00000000 + + + BKP + The application can write or read data + to and from these registers. They are powered-on by + VBAT when VDD is switched off, so that they are not + reset by System reset, and their contents remain + valid when the device operates in low-power mode. + This register is reset on a tamper detection event, + as long as TAMPxF=1. or when the Flash readout + protection is disabled. + 0 + 32 + + + + + RTC_BKP28R + RTC_BKP28R + RTC backup registers + 0xC0 + 0x20 + read-write + 0x00000000 + + + BKP + The application can write or read data + to and from these registers. They are powered-on by + VBAT when VDD is switched off, so that they are not + reset by System reset, and their contents remain + valid when the device operates in low-power mode. + This register is reset on a tamper detection event, + as long as TAMPxF=1. or when the Flash readout + protection is disabled. + 0 + 32 + + + + + RTC_BKP29R + RTC_BKP29R + RTC backup registers + 0xC4 + 0x20 + read-write + 0x00000000 + + + BKP + The application can write or read data + to and from these registers. They are powered-on by + VBAT when VDD is switched off, so that they are not + reset by System reset, and their contents remain + valid when the device operates in low-power mode. + This register is reset on a tamper detection event, + as long as TAMPxF=1. or when the Flash readout + protection is disabled. + 0 + 32 + + + + + RTC_BKP30R + RTC_BKP30R + RTC backup registers + 0xC8 + 0x20 + read-write + 0x00000000 + + + BKP + The application can write or read data + to and from these registers. They are powered-on by + VBAT when VDD is switched off, so that they are not + reset by System reset, and their contents remain + valid when the device operates in low-power mode. + This register is reset on a tamper detection event, + as long as TAMPxF=1. or when the Flash readout + protection is disabled. + 0 + 32 + + + + + RTC_BKP31R + RTC_BKP31R + RTC backup registers + 0xCC + 0x20 + read-write + 0x00000000 + + + BKP + The application can write or read data + to and from these registers. They are powered-on by + VBAT when VDD is switched off, so that they are not + reset by System reset, and their contents remain + valid when the device operates in low-power mode. + This register is reset on a tamper detection event, + as long as TAMPxF=1. or when the Flash readout + protection is disabled. + 0 + 32 + + + + + + + SAI4 + SAI + SAI + 0x58005400 + + 0x0 + 0x400 + registers + + + SAI4 + SAI4 global interrupt + 146 + + + + SAI_GCR + SAI_GCR + Global configuration register + 0x0 + 0x20 + read-write + 0x00000000 + + + SYNCOUT + Synchronization outputs These bits are + set and cleared by software. + 4 + 2 + + + SYNCIN + Synchronization inputs + 0 + 2 + + + + + SAI_ACR1 + SAI_ACR1 + Configuration register 1 + 0x4 + 0x20 + read-write + 0x00000040 + + + MODE + SAIx audio block mode + immediately + 0 + 2 + + + PRTCFG + Protocol configuration. These bits are + set and cleared by software. These bits have to be + configured when the audio block is + disabled. + 2 + 2 + + + DS + Data size. These bits are set and + cleared by software. These bits are ignored when the + SPDIF protocols are selected (bit PRTCFG[1:0]), + because the frame and the data size are fixed in such + case. When the companding mode is selected through + COMP[1:0] bits, DS[1:0] are ignored since the data + size is fixed to 8 bits by the algorithm. These bits + must be configured when the audio block is + disabled. + 5 + 3 + + + LSBFIRST + Least significant bit first. This bit is + set and cleared by software. It must be configured + when the audio block is disabled. This bit has no + meaning in AC97 audio protocol since AC97 data are + always transferred with the MSB first. This bit has + no meaning in SPDIF audio protocol since in SPDIF + data are always transferred with LSB + first. + 8 + 1 + + + CKSTR + Clock strobing edge. This bit is set and + cleared by software. It must be configured when the + audio block is disabled. This bit has no meaning in + SPDIF audio protocol. + 9 + 1 + + + SYNCEN + Synchronization enable. These bits are + set and cleared by software. They must be configured + when the audio sub-block is disabled. Note: The audio + sub-block should be configured as asynchronous when + SPDIF mode is enabled. + 10 + 2 + + + MONO + Mono mode. This bit is set and cleared + by software. It is meaningful only when the number of + slots is equal to 2. When the mono mode is selected, + slot 0 data are duplicated on slot 1 when the audio + block operates as a transmitter. In reception mode, + the slot1 is discarded and only the data received + from slot 0 are stored. Refer to Section: Mono/stereo + mode for more details. + 12 + 1 + + + OUTDRIV + Output drive. This bit is set and + cleared by software. Note: This bit has to be set + before enabling the audio block and after the audio + block configuration. + 13 + 1 + + + SAIXEN + Audio block enable where x is A or B. + This bit is set by software. To switch off the audio + block, the application software must program this bit + to 0 and poll the bit till it reads back 0, meaning + that the block is completely disabled. Before setting + this bit to 1, check that it is set to 0, otherwise + the enable command will not be taken into account. + This bit allows to control the state of SAIx audio + block. If it is disabled when an audio frame transfer + is ongoing, the ongoing transfer completes and the + cell is fully disabled at the end of this audio frame + transfer. Note: When SAIx block is configured in + master mode, the clock must be present on the input + of SAIx before setting SAIXEN bit. + 16 + 1 + + + DMAEN + DMA enable. This bit is set and cleared + by software. Note: Since the audio block defaults to + operate as a transmitter after reset, the MODE[1:0] + bits must be configured before setting DMAEN to avoid + a DMA request in receiver mode. + 17 + 1 + + + NOMCK + No divider + 19 + 1 + + + MCKDIV + Master clock divider. These bits are set + and cleared by software. These bits are meaningless + when the audio block operates in slave mode. They + have to be configured when the audio block is + disabled. Others: the master clock frequency is + calculated accordingly to the following + formula: + 20 + 4 + + + OSR + Oversampling ratio for master + clock + 26 + 1 + + + + + SAI_ACR2 + SAI_ACR2 + Configuration register 2 + 0x8 + 0x20 + 0x00000000 + + + FTH + FIFO threshold. This bit is set and + cleared by software. + 0 + 3 + read-write + + + FFLUSH + FIFO flush. This bit is set by software. + It is always read as 0. This bit should be configured + when the SAI is disabled. + 3 + 1 + write-only + + + TRIS + Tristate management on data line. This + bit is set and cleared by software. It is meaningful + only if the audio block is configured as a + transmitter. This bit is not used when the audio + block is configured in SPDIF mode. It should be + configured when SAI is disabled. Refer to Section: + Output data line management on an inactive slot for + more details. + 4 + 1 + read-write + + + MUTE + Mute. This bit is set and cleared by + software. It is meaningful only when the audio block + operates as a transmitter. The MUTE value is linked + to value of MUTEVAL if the number of slots is lower + or equal to 2, or equal to 0 if it is greater than 2. + Refer to Section: Mute mode for more details. Note: + This bit is meaningless and should not be used for + SPDIF audio blocks. + 5 + 1 + read-write + + + MUTEVAL + Mute value. This bit is set and cleared + by software.It must be written before enabling the + audio block: SAIXEN. This bit is meaningful only when + the audio block operates as a transmitter, the number + of slots is lower or equal to 2 and the MUTE bit is + set. If more slots are declared, the bit value sent + during the transmission in mute mode is equal to 0, + whatever the value of MUTEVAL. if the number of slot + is lower or equal to 2 and MUTEVAL = 1, the MUTE + value transmitted for each slot is the one sent + during the previous frame. Refer to Section: Mute + mode for more details. Note: This bit is meaningless + and should not be used for SPDIF audio + blocks. + 6 + 1 + read-write + + + MUTECNT + Mute counter. These bits are set and + cleared by software. They are used only in reception + mode. The value set in these bits is compared to the + number of consecutive mute frames detected in + reception. When the number of mute frames is equal to + this value, the flag MUTEDET will be set and an + interrupt will be generated if bit MUTEDETIE is set. + Refer to Section: Mute mode for more + details. + 7 + 6 + read-write + + + CPL + Complement bit. This bit is set and + cleared by software. It defines the type of + complement to be used for companding mode Note: This + bit has effect only when the companding mode is -Law + algorithm or A-Law algorithm. + 13 + 1 + read-write + + + COMP + Companding mode. These bits are set and + cleared by software. The -Law and the A-Law log are a + part of the CCITT G.711 recommendation, the type of + complement that will be used depends on CPL bit. The + data expansion or data compression are determined by + the state of bit MODE[0]. The data compression is + applied if the audio block is configured as a + transmitter. The data expansion is automatically + applied when the audio block is configured as a + receiver. Refer to Section: Companding mode for more + details. Note: Companding mode is applicable only + when TDM is selected. + 14 + 2 + read-write + + + + + SAI_AFRCR + SAI_AFRCR + This register has no meaning in AC97 and + SPDIF audio protocol + 0xC + 0x20 + 0x00000007 + + + FRL + Frame length. These bits are set and + cleared by software. They define the audio frame + length expressed in number of SCK clock cycles: the + number of bits in the frame is equal to FRL[7:0] + 1. + The minimum number of bits to transfer in an audio + frame must be equal to 8, otherwise the audio block + will behaves in an unexpected way. This is the case + when the data size is 8 bits and only one slot 0 is + defined in NBSLOT[4:0] of SAI_xSLOTR register + (NBSLOT[3:0] = 0000). In master mode, if the master + clock (available on MCLK_x pin) is used, the frame + length should be aligned with a number equal to a + power of 2, ranging from 8 to 256. When the master + clock is not used (NODIV = 1), it is recommended to + program the frame length to an value ranging from 8 + to 256. These bits are meaningless and are not used + in AC97 or SPDIF audio block + configuration. + 0 + 8 + read-write + + + FSALL + Frame synchronization active level + length. These bits are set and cleared by software. + They specify the length in number of bit clock (SCK) + + 1 (FSALL[6:0] + 1) of the active level of the FS + signal in the audio frame These bits are meaningless + and are not used in AC97 or SPDIF audio block + configuration. They must be configured when the audio + block is disabled. + 8 + 7 + read-write + + + FSDEF + Frame synchronization definition. This + bit is set and cleared by software. When the bit is + set, the number of slots defined in the SAI_xSLOTR + register has to be even. It means that half of this + number of slots will be dedicated to the left channel + and the other slots for the right channel (e.g: this + bit has to be set for I2S or MSB/LSB-justified + protocols...). This bit is meaningless and is not + used in AC97 or SPDIF audio block configuration. It + must be configured when the audio block is + disabled. + 16 + 1 + read-only + + + FSPOL + Frame synchronization polarity. This bit + is set and cleared by software. It is used to + configure the level of the start of frame on the FS + signal. It is meaningless and is not used in AC97 or + SPDIF audio block configuration. This bit must be + configured when the audio block is + disabled. + 17 + 1 + read-write + + + FSOFF + Frame synchronization offset. This bit + is set and cleared by software. It is meaningless and + is not used in AC97 or SPDIF audio block + configuration. This bit must be configured when the + audio block is disabled. + 18 + 1 + read-write + + + + + SAI_ASLOTR + SAI_ASLOTR + This register has no meaning in AC97 and + SPDIF audio protocol + 0x10 + 0x20 + read-write + 0x00000000 + + + FBOFF + First bit offset These bits are set and + cleared by software. The value set in this bitfield + defines the position of the first data transfer bit + in the slot. It represents an offset value. In + transmission mode, the bits outside the data field + are forced to 0. In reception mode, the extra + received bits are discarded. These bits must be set + when the audio block is disabled. They are ignored in + AC97 or SPDIF mode. + 0 + 5 + + + SLOTSZ + Slot size This bits is set and cleared + by software. The slot size must be higher or equal to + the data size. If this condition is not respected, + the behavior of the SAI will be undetermined. Refer + to Section: Output data line management on an + inactive slot for information on how to drive SD + line. These bits must be set when the audio block is + disabled. They are ignored in AC97 or SPDIF + mode. + 6 + 2 + + + NBSLOT + Number of slots in an audio frame. These + bits are set and cleared by software. The value set + in this bitfield represents the number of slots + 1 + in the audio frame (including the number of inactive + slots). The maximum number of slots is 16. The number + of slots should be even if FSDEF bit in the SAI_xFRCR + register is set. The number of slots must be + configured when the audio block is disabled. They are + ignored in AC97 or SPDIF mode. + 8 + 4 + + + SLOTEN + Slot enable. These bits are set and + cleared by software. Each SLOTEN bit corresponds to a + slot position from 0 to 15 (maximum 16 slots). The + slot must be enabled when the audio block is + disabled. They are ignored in AC97 or SPDIF + mode. + 16 + 16 + + + + + SAI_AIM + SAI_AIM + Interrupt mask register 2 + 0x14 + 0x20 + read-write + 0x00000000 + + + OVRUDRIE + Overrun/underrun interrupt enable. This + bit is set and cleared by software. When this bit is + set, an interrupt is generated if the OVRUDR bit in + the SAI_xSR register is set. + 0 + 1 + + + MUTEDETIE + Mute detection interrupt enable. This + bit is set and cleared by software. When this bit is + set, an interrupt is generated if the MUTEDET bit in + the SAI_xSR register is set. This bit has a meaning + only if the audio block is configured in receiver + mode. + 1 + 1 + + + WCKCFGIE + Wrong clock configuration interrupt + enable. This bit is set and cleared by software. This + bit is taken into account only if the audio block is + configured as a master (MODE[1] = 0) and NODIV = 0. + It generates an interrupt if the WCKCFG flag in the + SAI_xSR register is set. Note: This bit is used only + in TDM mode and is meaningless in other + modes. + 2 + 1 + + + FREQIE + FIFO request interrupt enable. This bit + is set and cleared by software. When this bit is set, + an interrupt is generated if the FREQ bit in the + SAI_xSR register is set. Since the audio block + defaults to operate as a transmitter after reset, the + MODE bit must be configured before setting FREQIE to + avoid a parasitic interruption in receiver + mode, + 3 + 1 + + + CNRDYIE + Codec not ready interrupt enable (AC97). + This bit is set and cleared by software. When the + interrupt is enabled, the audio block detects in the + slot 0 (tag0) of the AC97 frame if the Codec + connected to this line is ready or not. If it is not + ready, the CNRDY flag in the SAI_xSR register is set + and an interruption i generated. This bit has a + meaning only if the AC97 mode is selected through + PRTCFG[1:0] bits and the audio block is operates as a + receiver. + 4 + 1 + + + AFSDETIE + Anticipated frame synchronization + detection interrupt enable. This bit is set and + cleared by software. When this bit is set, an + interrupt will be generated if the AFSDET bit in the + SAI_xSR register is set. This bit is meaningless in + AC97, SPDIF mode or when the audio block operates as + a master. + 5 + 1 + + + LFSDETIE + Late frame synchronization detection + interrupt enable. This bit is set and cleared by + software. When this bit is set, an interrupt will be + generated if the LFSDET bit is set in the SAI_xSR + register. This bit is meaningless in AC97, SPDIF mode + or when the audio block operates as a + master. + 6 + 1 + + + + + SAI_ASR + SAI_ASR + Status register + 0x18 + 0x20 + read-only + 0x00000008 + + + OVRUDR + Overrun / underrun. This bit is read + only. The overrun and underrun conditions can occur + only when the audio block is configured as a receiver + and a transmitter, respectively. It can generate an + interrupt if OVRUDRIE bit is set in SAI_xIM register. + This flag is cleared when the software sets COVRUDR + bit in SAI_xCLRFR register. + 0 + 1 + + + MUTEDET + Mute detection. This bit is read only. + This flag is set if consecutive 0 values are received + in each slot of a given audio frame and for a + consecutive number of audio frames (set in the + MUTECNT bit in the SAI_xCR2 register). It can + generate an interrupt if MUTEDETIE bit is set in + SAI_xIM register. This flag is cleared when the + software sets bit CMUTEDET in the SAI_xCLRFR + register. + 1 + 1 + + + WCKCFG + Wrong clock configuration flag. This bit + is read only. This bit is used only when the audio + block operates in master mode (MODE[1] = 0) and NODIV + = 0. It can generate an interrupt if WCKCFGIE bit is + set in SAI_xIM register. This flag is cleared when + the software sets CWCKCFG bit in SAI_xCLRFR + register. + 2 + 1 + + + FREQ + FIFO request. This bit is read only. The + request depends on the audio block configuration: If + the block is configured in transmission mode, the + FIFO request is related to a write request operation + in the SAI_xDR. If the block configured in reception, + the FIFO request related to a read request operation + from the SAI_xDR. This flag can generate an interrupt + if FREQIE bit is set in SAI_xIM + register. + 3 + 1 + + + CNRDY + Codec not ready. This bit is read only. + This bit is used only when the AC97 audio protocol is + selected in the SAI_xCR1 register and configured in + receiver mode. It can generate an interrupt if + CNRDYIE bit is set in SAI_xIM register. This flag is + cleared when the software sets CCNRDY bit in + SAI_xCLRFR register. + 4 + 1 + + + AFSDET + Anticipated frame synchronization + detection. This bit is read only. This flag can be + set only if the audio block is configured in slave + mode. It is not used in AC97or SPDIF mode. It can + generate an interrupt if AFSDETIE bit is set in + SAI_xIM register. This flag is cleared when the + software sets CAFSDET bit in SAI_xCLRFR + register. + 5 + 1 + + + LFSDET + Late frame synchronization detection. + This bit is read only. This flag can be set only if + the audio block is configured in slave mode. It is + not used in AC97 or SPDIF mode. It can generate an + interrupt if LFSDETIE bit is set in the SAI_xIM + register. This flag is cleared when the software sets + bit CLFSDET in SAI_xCLRFR register + 6 + 1 + + + FLVL + FIFO level threshold. This bit is read + only. The FIFO level threshold flag is managed only + by hardware and its setting depends on SAI block + configuration (transmitter or receiver mode). If the + SAI block is configured as transmitter: If SAI block + is configured as receiver: + 16 + 3 + + + + + SAI_ACLRFR + SAI_ACLRFR + Clear flag register + 0x1C + 0x20 + write-only + 0x00000000 + + + COVRUDR + Clear overrun / underrun. This bit is + write only. Programming this bit to 1 clears the + OVRUDR flag in the SAI_xSR register. Reading this bit + always returns the value 0. + 0 + 1 + + + CMUTEDET + Mute detection flag. This bit is write + only. Programming this bit to 1 clears the MUTEDET + flag in the SAI_xSR register. Reading this bit always + returns the value 0. + 1 + 1 + + + CWCKCFG + Clear wrong clock configuration flag. + This bit is write only. Programming this bit to 1 + clears the WCKCFG flag in the SAI_xSR register. This + bit is used only when the audio block is set as + master (MODE[1] = 0) and NODIV = 0 in the SAI_xCR1 + register. Reading this bit always returns the value + 0. + 2 + 1 + + + CCNRDY + Clear Codec not ready flag. This bit is + write only. Programming this bit to 1 clears the + CNRDY flag in the SAI_xSR register. This bit is used + only when the AC97 audio protocol is selected in the + SAI_xCR1 register. Reading this bit always returns + the value 0. + 4 + 1 + + + CAFSDET + Clear anticipated frame synchronization + detection flag. This bit is write only. Programming + this bit to 1 clears the AFSDET flag in the SAI_xSR + register. It is not used in AC97or SPDIF mode. + Reading this bit always returns the value + 0. + 5 + 1 + + + CLFSDET + Clear late frame synchronization + detection flag. This bit is write only. Programming + this bit to 1 clears the LFSDET flag in the SAI_xSR + register. This bit is not used in AC97or SPDIF mode + Reading this bit always returns the value + 0. + 6 + 1 + + + + + SAI_ADR + SAI_ADR + Data register + 0x20 + 0x20 + read-write + 0x00000000 + + + DATA + Data A write to this register loads the + FIFO provided the FIFO is not full. A read from this + register empties the FIFO if the FIFO is not + empty. + 0 + 32 + + + + + SAI_BCR1 + SAI_BCR1 + Configuration register 1 + 0x24 + 0x20 + read-write + 0x00000040 + + + MODE + SAIx audio block mode + immediately + 0 + 2 + + + PRTCFG + Protocol configuration. These bits are + set and cleared by software. These bits have to be + configured when the audio block is + disabled. + 2 + 2 + + + DS + Data size. These bits are set and + cleared by software. These bits are ignored when the + SPDIF protocols are selected (bit PRTCFG[1:0]), + because the frame and the data size are fixed in such + case. When the companding mode is selected through + COMP[1:0] bits, DS[1:0] are ignored since the data + size is fixed to 8 bits by the algorithm. These bits + must be configured when the audio block is + disabled. + 5 + 3 + + + LSBFIRST + Least significant bit first. This bit is + set and cleared by software. It must be configured + when the audio block is disabled. This bit has no + meaning in AC97 audio protocol since AC97 data are + always transferred with the MSB first. This bit has + no meaning in SPDIF audio protocol since in SPDIF + data are always transferred with LSB + first. + 8 + 1 + + + CKSTR + Clock strobing edge. This bit is set and + cleared by software. It must be configured when the + audio block is disabled. This bit has no meaning in + SPDIF audio protocol. + 9 + 1 + + + SYNCEN + Synchronization enable. These bits are + set and cleared by software. They must be configured + when the audio sub-block is disabled. Note: The audio + sub-block should be configured as asynchronous when + SPDIF mode is enabled. + 10 + 2 + + + MONO + Mono mode. This bit is set and cleared + by software. It is meaningful only when the number of + slots is equal to 2. When the mono mode is selected, + slot 0 data are duplicated on slot 1 when the audio + block operates as a transmitter. In reception mode, + the slot1 is discarded and only the data received + from slot 0 are stored. Refer to Section: Mono/stereo + mode for more details. + 12 + 1 + + + OUTDRIV + Output drive. This bit is set and + cleared by software. Note: This bit has to be set + before enabling the audio block and after the audio + block configuration. + 13 + 1 + + + SAIXEN + Audio block enable where x is A or B. + This bit is set by software. To switch off the audio + block, the application software must program this bit + to 0 and poll the bit till it reads back 0, meaning + that the block is completely disabled. Before setting + this bit to 1, check that it is set to 0, otherwise + the enable command will not be taken into account. + This bit allows to control the state of SAIx audio + block. If it is disabled when an audio frame transfer + is ongoing, the ongoing transfer completes and the + cell is fully disabled at the end of this audio frame + transfer. Note: When SAIx block is configured in + master mode, the clock must be present on the input + of SAIx before setting SAIXEN bit. + 16 + 1 + + + DMAEN + DMA enable. This bit is set and cleared + by software. Note: Since the audio block defaults to + operate as a transmitter after reset, the MODE[1:0] + bits must be configured before setting DMAEN to avoid + a DMA request in receiver mode. + 17 + 1 + + + NOMCK + No divider + 19 + 1 + + + MCKDIV + Master clock divider. These bits are set + and cleared by software. These bits are meaningless + when the audio block operates in slave mode. They + have to be configured when the audio block is + disabled. Others: the master clock frequency is + calculated accordingly to the following + formula: + 20 + 4 + + + OSR + Oversampling ratio for master + clock + 26 + 1 + + + + + SAI_BCR2 + SAI_BCR2 + Configuration register 2 + 0x28 + 0x20 + 0x00000000 + + + FTH + FIFO threshold. This bit is set and + cleared by software. + 0 + 3 + read-write + + + FFLUSH + FIFO flush. This bit is set by software. + It is always read as 0. This bit should be configured + when the SAI is disabled. + 3 + 1 + write-only + + + TRIS + Tristate management on data line. This + bit is set and cleared by software. It is meaningful + only if the audio block is configured as a + transmitter. This bit is not used when the audio + block is configured in SPDIF mode. It should be + configured when SAI is disabled. Refer to Section: + Output data line management on an inactive slot for + more details. + 4 + 1 + read-write + + + MUTE + Mute. This bit is set and cleared by + software. It is meaningful only when the audio block + operates as a transmitter. The MUTE value is linked + to value of MUTEVAL if the number of slots is lower + or equal to 2, or equal to 0 if it is greater than 2. + Refer to Section: Mute mode for more details. Note: + This bit is meaningless and should not be used for + SPDIF audio blocks. + 5 + 1 + read-write + + + MUTEVAL + Mute value. This bit is set and cleared + by software.It must be written before enabling the + audio block: SAIXEN. This bit is meaningful only when + the audio block operates as a transmitter, the number + of slots is lower or equal to 2 and the MUTE bit is + set. If more slots are declared, the bit value sent + during the transmission in mute mode is equal to 0, + whatever the value of MUTEVAL. if the number of slot + is lower or equal to 2 and MUTEVAL = 1, the MUTE + value transmitted for each slot is the one sent + during the previous frame. Refer to Section: Mute + mode for more details. Note: This bit is meaningless + and should not be used for SPDIF audio + blocks. + 6 + 1 + read-write + + + MUTECNT + Mute counter. These bits are set and + cleared by software. They are used only in reception + mode. The value set in these bits is compared to the + number of consecutive mute frames detected in + reception. When the number of mute frames is equal to + this value, the flag MUTEDET will be set and an + interrupt will be generated if bit MUTEDETIE is set. + Refer to Section: Mute mode for more + details. + 7 + 6 + read-write + + + CPL + Complement bit. This bit is set and + cleared by software. It defines the type of + complement to be used for companding mode Note: This + bit has effect only when the companding mode is -Law + algorithm or A-Law algorithm. + 13 + 1 + read-write + + + COMP + Companding mode. These bits are set and + cleared by software. The -Law and the A-Law log are a + part of the CCITT G.711 recommendation, the type of + complement that will be used depends on CPL bit. The + data expansion or data compression are determined by + the state of bit MODE[0]. The data compression is + applied if the audio block is configured as a + transmitter. The data expansion is automatically + applied when the audio block is configured as a + receiver. Refer to Section: Companding mode for more + details. Note: Companding mode is applicable only + when TDM is selected. + 14 + 2 + read-write + + + + + SAI_BFRCR + SAI_BFRCR + This register has no meaning in AC97 and + SPDIF audio protocol + 0x2C + 0x20 + 0x00000007 + + + FRL + Frame length. These bits are set and + cleared by software. They define the audio frame + length expressed in number of SCK clock cycles: the + number of bits in the frame is equal to FRL[7:0] + 1. + The minimum number of bits to transfer in an audio + frame must be equal to 8, otherwise the audio block + will behaves in an unexpected way. This is the case + when the data size is 8 bits and only one slot 0 is + defined in NBSLOT[4:0] of SAI_xSLOTR register + (NBSLOT[3:0] = 0000). In master mode, if the master + clock (available on MCLK_x pin) is used, the frame + length should be aligned with a number equal to a + power of 2, ranging from 8 to 256. When the master + clock is not used (NODIV = 1), it is recommended to + program the frame length to an value ranging from 8 + to 256. These bits are meaningless and are not used + in AC97 or SPDIF audio block + configuration. + 0 + 8 + read-write + + + FSALL + Frame synchronization active level + length. These bits are set and cleared by software. + They specify the length in number of bit clock (SCK) + + 1 (FSALL[6:0] + 1) of the active level of the FS + signal in the audio frame These bits are meaningless + and are not used in AC97 or SPDIF audio block + configuration. They must be configured when the audio + block is disabled. + 8 + 7 + read-write + + + FSDEF + Frame synchronization definition. This + bit is set and cleared by software. When the bit is + set, the number of slots defined in the SAI_xSLOTR + register has to be even. It means that half of this + number of slots will be dedicated to the left channel + and the other slots for the right channel (e.g: this + bit has to be set for I2S or MSB/LSB-justified + protocols...). This bit is meaningless and is not + used in AC97 or SPDIF audio block configuration. It + must be configured when the audio block is + disabled. + 16 + 1 + read-only + + + FSPOL + Frame synchronization polarity. This bit + is set and cleared by software. It is used to + configure the level of the start of frame on the FS + signal. It is meaningless and is not used in AC97 or + SPDIF audio block configuration. This bit must be + configured when the audio block is + disabled. + 17 + 1 + read-write + + + FSOFF + Frame synchronization offset. This bit + is set and cleared by software. It is meaningless and + is not used in AC97 or SPDIF audio block + configuration. This bit must be configured when the + audio block is disabled. + 18 + 1 + read-write + + + + + SAI_BSLOTR + SAI_BSLOTR + This register has no meaning in AC97 and + SPDIF audio protocol + 0x30 + 0x20 + read-write + 0x00000000 + + + FBOFF + First bit offset These bits are set and + cleared by software. The value set in this bitfield + defines the position of the first data transfer bit + in the slot. It represents an offset value. In + transmission mode, the bits outside the data field + are forced to 0. In reception mode, the extra + received bits are discarded. These bits must be set + when the audio block is disabled. They are ignored in + AC97 or SPDIF mode. + 0 + 5 + + + SLOTSZ + Slot size This bits is set and cleared + by software. The slot size must be higher or equal to + the data size. If this condition is not respected, + the behavior of the SAI will be undetermined. Refer + to Section: Output data line management on an + inactive slot for information on how to drive SD + line. These bits must be set when the audio block is + disabled. They are ignored in AC97 or SPDIF + mode. + 6 + 2 + + + NBSLOT + Number of slots in an audio frame. These + bits are set and cleared by software. The value set + in this bitfield represents the number of slots + 1 + in the audio frame (including the number of inactive + slots). The maximum number of slots is 16. The number + of slots should be even if FSDEF bit in the SAI_xFRCR + register is set. The number of slots must be + configured when the audio block is disabled. They are + ignored in AC97 or SPDIF mode. + 8 + 4 + + + SLOTEN + Slot enable. These bits are set and + cleared by software. Each SLOTEN bit corresponds to a + slot position from 0 to 15 (maximum 16 slots). The + slot must be enabled when the audio block is + disabled. They are ignored in AC97 or SPDIF + mode. + 16 + 16 + + + + + SAI_BIM + SAI_BIM + Interrupt mask register 2 + 0x34 + 0x20 + read-write + 0x00000000 + + + OVRUDRIE + Overrun/underrun interrupt enable. This + bit is set and cleared by software. When this bit is + set, an interrupt is generated if the OVRUDR bit in + the SAI_xSR register is set. + 0 + 1 + + + MUTEDETIE + Mute detection interrupt enable. This + bit is set and cleared by software. When this bit is + set, an interrupt is generated if the MUTEDET bit in + the SAI_xSR register is set. This bit has a meaning + only if the audio block is configured in receiver + mode. + 1 + 1 + + + WCKCFGIE + Wrong clock configuration interrupt + enable. This bit is set and cleared by software. This + bit is taken into account only if the audio block is + configured as a master (MODE[1] = 0) and NODIV = 0. + It generates an interrupt if the WCKCFG flag in the + SAI_xSR register is set. Note: This bit is used only + in TDM mode and is meaningless in other + modes. + 2 + 1 + + + FREQIE + FIFO request interrupt enable. This bit + is set and cleared by software. When this bit is set, + an interrupt is generated if the FREQ bit in the + SAI_xSR register is set. Since the audio block + defaults to operate as a transmitter after reset, the + MODE bit must be configured before setting FREQIE to + avoid a parasitic interruption in receiver + mode, + 3 + 1 + + + CNRDYIE + Codec not ready interrupt enable (AC97). + This bit is set and cleared by software. When the + interrupt is enabled, the audio block detects in the + slot 0 (tag0) of the AC97 frame if the Codec + connected to this line is ready or not. If it is not + ready, the CNRDY flag in the SAI_xSR register is set + and an interruption i generated. This bit has a + meaning only if the AC97 mode is selected through + PRTCFG[1:0] bits and the audio block is operates as a + receiver. + 4 + 1 + + + AFSDETIE + Anticipated frame synchronization + detection interrupt enable. This bit is set and + cleared by software. When this bit is set, an + interrupt will be generated if the AFSDET bit in the + SAI_xSR register is set. This bit is meaningless in + AC97, SPDIF mode or when the audio block operates as + a master. + 5 + 1 + + + LFSDETIE + Late frame synchronization detection + interrupt enable. This bit is set and cleared by + software. When this bit is set, an interrupt will be + generated if the LFSDET bit is set in the SAI_xSR + register. This bit is meaningless in AC97, SPDIF mode + or when the audio block operates as a + master. + 6 + 1 + + + + + SAI_BSR + SAI_BSR + Status register + 0x38 + 0x20 + read-only + 0x00000008 + + + OVRUDR + Overrun / underrun. This bit is read + only. The overrun and underrun conditions can occur + only when the audio block is configured as a receiver + and a transmitter, respectively. It can generate an + interrupt if OVRUDRIE bit is set in SAI_xIM register. + This flag is cleared when the software sets COVRUDR + bit in SAI_xCLRFR register. + 0 + 1 + + + MUTEDET + Mute detection. This bit is read only. + This flag is set if consecutive 0 values are received + in each slot of a given audio frame and for a + consecutive number of audio frames (set in the + MUTECNT bit in the SAI_xCR2 register). It can + generate an interrupt if MUTEDETIE bit is set in + SAI_xIM register. This flag is cleared when the + software sets bit CMUTEDET in the SAI_xCLRFR + register. + 1 + 1 + + + WCKCFG + Wrong clock configuration flag. This bit + is read only. This bit is used only when the audio + block operates in master mode (MODE[1] = 0) and NODIV + = 0. It can generate an interrupt if WCKCFGIE bit is + set in SAI_xIM register. This flag is cleared when + the software sets CWCKCFG bit in SAI_xCLRFR + register. + 2 + 1 + + + FREQ + FIFO request. This bit is read only. The + request depends on the audio block configuration: If + the block is configured in transmission mode, the + FIFO request is related to a write request operation + in the SAI_xDR. If the block configured in reception, + the FIFO request related to a read request operation + from the SAI_xDR. This flag can generate an interrupt + if FREQIE bit is set in SAI_xIM + register. + 3 + 1 + + + CNRDY + Codec not ready. This bit is read only. + This bit is used only when the AC97 audio protocol is + selected in the SAI_xCR1 register and configured in + receiver mode. It can generate an interrupt if + CNRDYIE bit is set in SAI_xIM register. This flag is + cleared when the software sets CCNRDY bit in + SAI_xCLRFR register. + 4 + 1 + + + AFSDET + Anticipated frame synchronization + detection. This bit is read only. This flag can be + set only if the audio block is configured in slave + mode. It is not used in AC97or SPDIF mode. It can + generate an interrupt if AFSDETIE bit is set in + SAI_xIM register. This flag is cleared when the + software sets CAFSDET bit in SAI_xCLRFR + register. + 5 + 1 + + + LFSDET + Late frame synchronization detection. + This bit is read only. This flag can be set only if + the audio block is configured in slave mode. It is + not used in AC97 or SPDIF mode. It can generate an + interrupt if LFSDETIE bit is set in the SAI_xIM + register. This flag is cleared when the software sets + bit CLFSDET in SAI_xCLRFR register + 6 + 1 + + + FLVL + FIFO level threshold. This bit is read + only. The FIFO level threshold flag is managed only + by hardware and its setting depends on SAI block + configuration (transmitter or receiver mode). If the + SAI block is configured as transmitter: If SAI block + is configured as receiver: + 16 + 3 + + + + + SAI_BCLRFR + SAI_BCLRFR + Clear flag register + 0x3C + 0x20 + write-only + 0x00000000 + + + COVRUDR + Clear overrun / underrun. This bit is + write only. Programming this bit to 1 clears the + OVRUDR flag in the SAI_xSR register. Reading this bit + always returns the value 0. + 0 + 1 + + + CMUTEDET + Mute detection flag. This bit is write + only. Programming this bit to 1 clears the MUTEDET + flag in the SAI_xSR register. Reading this bit always + returns the value 0. + 1 + 1 + + + CWCKCFG + Clear wrong clock configuration flag. + This bit is write only. Programming this bit to 1 + clears the WCKCFG flag in the SAI_xSR register. This + bit is used only when the audio block is set as + master (MODE[1] = 0) and NODIV = 0 in the SAI_xCR1 + register. Reading this bit always returns the value + 0. + 2 + 1 + + + CCNRDY + Clear Codec not ready flag. This bit is + write only. Programming this bit to 1 clears the + CNRDY flag in the SAI_xSR register. This bit is used + only when the AC97 audio protocol is selected in the + SAI_xCR1 register. Reading this bit always returns + the value 0. + 4 + 1 + + + CAFSDET + Clear anticipated frame synchronization + detection flag. This bit is write only. Programming + this bit to 1 clears the AFSDET flag in the SAI_xSR + register. It is not used in AC97or SPDIF mode. + Reading this bit always returns the value + 0. + 5 + 1 + + + CLFSDET + Clear late frame synchronization + detection flag. This bit is write only. Programming + this bit to 1 clears the LFSDET flag in the SAI_xSR + register. This bit is not used in AC97or SPDIF mode + Reading this bit always returns the value + 0. + 6 + 1 + + + + + SAI_BDR + SAI_BDR + Data register + 0x40 + 0x20 + read-write + 0x00000000 + + + DATA + Data A write to this register loads the + FIFO provided the FIFO is not full. A read from this + register empties the FIFO if the FIFO is not + empty. + 0 + 32 + + + + + SAI_PDMCR + SAI_PDMCR + PDM control register + 0x44 + 0x20 + read-write + 0x00000000 + + + PDMEN + PDM enable + 0 + 1 + + + MICNBR + Number of microphones + 4 + 2 + + + CKEN1 + Clock enable of bitstream clock number + 1 + 8 + 1 + + + CKEN2 + Clock enable of bitstream clock number + 2 + 9 + 1 + + + CKEN3 + Clock enable of bitstream clock number + 3 + 10 + 1 + + + CKEN4 + Clock enable of bitstream clock number + 4 + 11 + 1 + + + + + SAI_PDMDLY + SAI_PDMDLY + PDM delay register + 0x48 + 0x20 + read-write + 0x00000000 + + + DLYM1L + Delay line adjust for first microphone + of pair 1 + 0 + 3 + + + DLYM1R + Delay line adjust for second microphone + of pair 1 + 4 + 3 + + + DLYM2L + Delay line for first microphone of pair + 2 + 8 + 3 + + + DLYM2R + Delay line for second microphone of pair + 2 + 12 + 3 + + + DLYM3L + Delay line for first microphone of pair + 3 + 16 + 3 + + + DLYM3R + Delay line for second microphone of pair + 3 + 20 + 3 + + + DLYM4L + Delay line for first microphone of pair + 4 + 24 + 3 + + + DLYM4R + Delay line for second microphone of pair + 4 + 28 + 3 + + + + + + + SAI1 + 0x40015800 + + SAI1 + SAI1 global interrupt + 87 + + + + SAI2 + 0x40015C00 + + SAI2 + SAI2 global interrupt + 91 + + + + SAI3 + 0x40016000 + + SAI3 + SAI3 global interrupt + 114 + + + + SDMMC1 + SDMMC1 + SDMMC + 0x52007000 + + 0x0 + 0x3FD + registers + + + SDMMC1 + SDMMC global interrupt + 49 + + + SDMMC + SDMMC global interrupt + 124 + + + + POWER + POWER + SDMMC power control register + 0x0 + 0x20 + read-write + 0x00000000 + + + PWRCTRL + SDMMC state control bits. These bits can + only be written when the SDMMC is not in the power-on + state (PWRCTRL?11). These bits are used to define the + functional state of the SDMMC signals: Any further + write will be ignored, PWRCTRL value will keep + 11. + 0 + 2 + + + VSWITCH + Voltage switch sequence start. This bit + is used to start the timing critical section of the + voltage switch sequence: + 2 + 1 + + + VSWITCHEN + Voltage switch procedure enable. This + bit can only be written by firmware when CPSM is + disabled (CPSMEN = 0). This bit is used to stop the + SDMMC_CK after the voltage switch command + response: + 3 + 1 + + + DIRPOL + Data and command direction signals + polarity selection. This bit can only be written when + the SDMMC is in the power-off state (PWRCTRL = + 00). + 4 + 1 + + + + + CLKCR + CLKCR + The SDMMC_CLKCR register controls the + SDMMC_CK output clock, the SDMMC_RX_CLK receive clock, + and the bus width. + 0x4 + 0x20 + read-write + 0x00000000 + + + CLKDIV + Clock divide factor This bit can only be + written when the CPSM and DPSM are not active + (CPSMACT = 0 and DPSMACT = 0). This field defines the + divide factor between the input clock (SDMMCCLK) and + the output clock (SDMMC_CK): SDMMC_CK frequency = + SDMMCCLK / [2 * CLKDIV]. 0xx: etc.. xxx: + etc.. + 0 + 10 + + + PWRSAV + Power saving configuration bit This bit + can only be written when the CPSM and DPSM are not + active (CPSMACT = 0 and DPSMACT = 0) For power + saving, the SDMMC_CK clock output can be disabled + when the bus is idle by setting PWRSAV: + 12 + 1 + + + WIDBUS + Wide bus mode enable bit This bit can + only be written when the CPSM and DPSM are not active + (CPSMACT = 0 and DPSMACT = 0) + 14 + 2 + + + NEGEDGE + SDMMC_CK dephasing selection bit for + data and Command. This bit can only be written when + the CPSM and DPSM are not active (CPSMACT = 0 and + DPSMACT = 0). When clock division = 1 (CLKDIV = 0), + this bit has no effect. Data and Command change on + SDMMC_CK falling edge. When clock division >1 + (CLKDIV > 0) & DDR = 0: - SDMMC_CK + edge occurs on SDMMCCLK rising edge. When clock + division >1 (CLKDIV > 0) & DDR = 1: - Data + changed on the SDMMCCLK falling edge succeeding a + SDMMC_CK edge. - SDMMC_CK edge occurs on SDMMCCLK + rising edge. - Data changed on the SDMMC_CK falling + edge succeeding a SDMMC_CK edge. - SDMMC_CK edge + occurs on SDMMCCLK rising edge. + 16 + 1 + + + HWFC_EN + Hardware flow control enable This bit + can only be written when the CPSM and DPSM are not + active (CPSMACT = 0 and DPSMACT = 0) When Hardware + flow control is enabled, the meaning of the TXFIFOE + and RXFIFOF flags change, please see SDMMC status + register definition in Section56.8.11. + 17 + 1 + + + DDR + Data rate signaling selection This bit + can only be written when the CPSM and DPSM are not + active (CPSMACT = 0 and DPSMACT = 0) DDR rate shall + only be selected with 4-bit or 8-bit wide bus mode. + (WIDBUS > 00). DDR = 1 has no effect when + WIDBUS = 00 (1-bit wide bus). DDR rate shall only be + selected with clock division >1. (CLKDIV + > 0) + 18 + 1 + + + BUSSPEED + Bus speed mode selection between DS, HS, + SDR12, SDR25 and SDR50, DDR50, SDR104. This bit can + only be written when the CPSM and DPSM are not active + (CPSMACT = 0 and DPSMACT = 0) + 19 + 1 + + + SELCLKRX + Receive clock selection. These bits can + only be written when the CPSM and DPSM are not active + (CPSMACT = 0 and DPSMACT = 0) + 20 + 2 + + + + + ARGR + ARGR + The SDMMC_ARGR register contains a 32-bit + command argument, which is sent to a card as part of a + command message. + 0x8 + 0x20 + read-write + 0x00000000 + + + CMDARG + Command argument. These bits can only be + written by firmware when CPSM is disabled (CPSMEN = + 0). Command argument sent to a card as part of a + command message. If a command contains an argument, + it must be loaded into this register before writing a + command to the command register. + 0 + 32 + + + + + CMDR + CMDR + The SDMMC_CMDR register contains the command + index and command type bits. The command index is sent to + a card as part of a command message. The command type + bits control the command path state machine + (CPSM). + 0xC + 0x20 + read-write + 0x00000000 + + + CMDINDEX + Command index. This bit can only be + written by firmware when CPSM is disabled (CPSMEN = + 0). The command index is sent to the card as part of + a command message. + 0 + 6 + + + CMDTRANS + The CPSM treats the command as a data + transfer command, stops the interrupt period, and + signals DataEnable to the DPSM This bit can only be + written by firmware when CPSM is disabled (CPSMEN = + 0). If this bit is set, the CPSM issues an end of + interrupt period and issues DataEnable signal to the + DPSM when the command is sent. + 6 + 1 + + + CMDSTOP + The CPSM treats the command as a Stop + Transmission command and signals Abort to the DPSM. + This bit can only be written by firmware when CPSM is + disabled (CPSMEN = 0). If this bit is set, the CPSM + issues the Abort signal to the DPSM when the command + is sent. + 7 + 1 + + + WAITRESP + Wait for response bits. This bit can + only be written by firmware when CPSM is disabled + (CPSMEN = 0). They are used to configure whether the + CPSM is to wait for a response, and if yes, which + kind of response. + 8 + 2 + + + WAITINT + CPSM waits for interrupt request. If + this bit is set, the CPSM disables command timeout + and waits for an card interrupt request (Response). + If this bit is cleared in the CPSM Wait state, will + cause the abort of the interrupt mode. + 10 + 1 + + + WAITPEND + CPSM Waits for end of data transfer + (CmdPend internal signal) from DPSM. This bit when + set, the CPSM waits for the end of data transfer + trigger before it starts sending a command. WAITPEND + is only taken into account when DTMODE = MMC stream + data transfer, WIDBUS = 1-bit wide bus mode, DPSMACT + = 1 and DTDIR = from host to card. + 11 + 1 + + + CPSMEN + Command path state machine (CPSM) Enable + bit This bit is written 1 by firmware, and cleared by + hardware when the CPSM enters the Idle state. If this + bit is set, the CPSM is enabled. When DTEN = 1, no + command will be transfered nor boot procedure will be + started. CPSMEN is cleared to 0. + 12 + 1 + + + DTHOLD + Hold new data block transmission and + reception in the DPSM. If this bit is set, the DPSM + will not move from the Wait_S state to the Send state + or from the Wait_R state to the Receive + state. + 13 + 1 + + + BOOTMODE + Select the boot mode procedure to be + used. This bit can only be written by firmware when + CPSM is disabled (CPSMEN = 0) + 14 + 1 + + + BOOTEN + Enable boot mode + procedure. + 15 + 1 + + + CMDSUSPEND + The CPSM treats the command as a Suspend + or Resume command and signals interrupt period + start/end. This bit can only be written by firmware + when CPSM is disabled (CPSMEN = 0). CMDSUSPEND = 1 + and CMDTRANS = 0 Suspend command, start interrupt + period when response bit BS=0. CMDSUSPEND = 1 and + CMDTRANS = 1 Resume command with data, end interrupt + period when response bit DF=1. + 16 + 1 + + + + + RESP1R + RESP1R + The SDMMC_RESP1/2/3/4R registers contain the + status of a card, which is part of the received + response. + 0x14 + 0x20 + read-only + 0x00000000 + + + CARDSTATUS1 + see Table 432 + 0 + 32 + + + + + RESP2R + RESP2R + The SDMMC_RESP1/2/3/4R registers contain the + status of a card, which is part of the received + response. + 0x18 + 0x20 + read-only + 0x00000000 + + + CARDSTATUS2 + see Table404. + 0 + 32 + + + + + RESP3R + RESP3R + The SDMMC_RESP1/2/3/4R registers contain the + status of a card, which is part of the received + response. + 0x1C + 0x20 + read-only + 0x00000000 + + + CARDSTATUS3 + see Table404. + 0 + 32 + + + + + RESP4R + RESP4R + The SDMMC_RESP1/2/3/4R registers contain the + status of a card, which is part of the received + response. + 0x20 + 0x20 + read-only + 0x00000000 + + + CARDSTATUS4 + see Table404. + 0 + 32 + + + + + DTIMER + DTIMER + The SDMMC_DTIMER register contains the data + timeout period, in card bus clock periods. A counter + loads the value from the SDMMC_DTIMER register, and + starts decrementing when the data path state machine + (DPSM) enters the Wait_R or Busy state. If the timer + reaches 0 while the DPSM is in either of these states, + the timeout status flag is set. + 0x24 + 0x20 + read-write + 0x00000000 + + + DATATIME + Data and R1b busy timeout period This + bit can only be written when the CPSM and DPSM are + not active (CPSMACT = 0 and DPSMACT = 0). Data and + R1b busy timeout period expressed in card bus clock + periods. + 0 + 32 + + + + + DLENR + DLENR + The SDMMC_DLENR register contains the number + of data bytes to be transferred. The value is loaded into + the data counter when data transfer starts. + 0x28 + 0x20 + read-write + 0x00000000 + + + DATALENGTH + Data length value This register can only + be written by firmware when DPSM is inactive (DPSMACT + = 0). Number of data bytes to be transferred. When + DDR = 1 DATALENGTH is truncated to a multiple of 2. + (The last odd byte is not transfered) When DATALENGTH + = 0 no data will be transfered, when requested by a + CPSMEN and CMDTRANS = 1 also no command will be + transfered. DTEN and CPSMEN are cleared to + 0. + 0 + 25 + + + + + DCTRL + DCTRL + The SDMMC_DCTRL register control the data + path state machine (DPSM). + 0x2C + 0x20 + read-write + 0x00000000 + + + DTEN + Data transfer enable bit This bit can + only be written by firmware when DPSM is inactive + (DPSMACT = 0). This bit is cleared by Hardware when + data transfer completes. This bit shall only be used + to transfer data when no associated data transfer + command is used, i.e. shall not be used with SD or + eMMC cards. + 0 + 1 + + + DTDIR + Data transfer direction selection This + bit can only be written by firmware when DPSM is + inactive (DPSMACT = 0). + 1 + 1 + + + DTMODE + Data transfer mode selection. This bit + can only be written by firmware when DPSM is inactive + (DPSMACT = 0). + 2 + 2 + + + DBLOCKSIZE + Data block size This bit can only be + written by firmware when DPSM is inactive (DPSMACT = + 0). Define the data block length when the block data + transfer mode is selected: When DATALENGTH is not a + multiple of DBLOCKSIZE, the transfered data is + truncated at a multiple of DBLOCKSIZE. (Any remain + data will not be transfered.) When DDR = 1, + DBLOCKSIZE = 0000 shall not be used. (No data will be + transfered) + 4 + 4 + + + RWSTART + Read wait start. If this bit is set, + read wait operation starts. + 8 + 1 + + + RWSTOP + Read wait stop This bit is written by + firmware and auto cleared by hardware when the DPSM + moves from the READ_WAIT state to the WAIT_R or IDLE + state. + 9 + 1 + + + RWMOD + Read wait mode. This bit can only be + written by firmware when DPSM is inactive (DPSMACT = + 0). + 10 + 1 + + + SDIOEN + SD I/O interrupt enable functions This + bit can only be written by firmware when DPSM is + inactive (DPSMACT = 0). If this bit is set, the DPSM + enables the SD I/O card specific interrupt + operation. + 11 + 1 + + + BOOTACKEN + Enable the reception of the boot + acknowledgment. This bit can only be written by + firmware when DPSM is inactive (DPSMACT = + 0). + 12 + 1 + + + FIFORST + FIFO reset, will flush any remaining + data. This bit can only be written by firmware when + IDMAEN= 0 and DPSM is active (DPSMACT = 1). This bit + will only take effect when a transfer error or + transfer hold occurs. + 13 + 1 + + + + + DCNTR + DCNTR + The SDMMC_DCNTR register loads the value + from the data length register (see SDMMC_DLENR) when the + DPSM moves from the Idle state to the Wait_R or Wait_S + state. As data is transferred, the counter decrements the + value until it reaches 0. The DPSM then moves to the Idle + state and when there has been no error, the data status + end flag (DATAEND) is set. + 0x30 + 0x20 + read-only + 0x00000000 + + + DATACOUNT + Data count value When read, the number + of remaining data bytes to be transferred is + returned. Write has no effect. + 0 + 25 + + + + + STAR + STAR + The SDMMC_STAR register is a read-only + register. It contains two types of flag:Static flags + (bits [29,21,11:0]): these bits remain asserted until + they are cleared by writing to the SDMMC interrupt Clear + register (see SDMMC_ICR)Dynamic flags (bits [20:12]): + these bits change state depending on the state of the + underlying logic (for example, FIFO full and empty flags + are asserted and de-asserted as data while written to the + FIFO) + 0x34 + 0x20 + read-only + 0x00000000 + + + CCRCFAIL + Command response received (CRC check + failed). Interrupt flag is cleared by writing + corresponding interrupt clear bit in + SDMMC_ICR. + 0 + 1 + + + DCRCFAIL + Data block sent/received (CRC check + failed). Interrupt flag is cleared by writing + corresponding interrupt clear bit in + SDMMC_ICR. + 1 + 1 + + + CTIMEOUT + Command response timeout. Interrupt flag + is cleared by writing corresponding interrupt clear + bit in SDMMC_ICR. The Command Timeout period has a + fixed value of 64 SDMMC_CK clock + periods. + 2 + 1 + + + DTIMEOUT + Data timeout. Interrupt flag is cleared + by writing corresponding interrupt clear bit in + SDMMC_ICR. + 3 + 1 + + + TXUNDERR + Transmit FIFO underrun error or IDMA + read transfer error. Interrupt flag is cleared by + writing corresponding interrupt clear bit in + SDMMC_ICR. + 4 + 1 + + + RXOVERR + Received FIFO overrun error or IDMA + write transfer error. Interrupt flag is cleared by + writing corresponding interrupt clear bit in + SDMMC_ICR. + 5 + 1 + + + CMDREND + Command response received (CRC check + passed, or no CRC). Interrupt flag is cleared by + writing corresponding interrupt clear bit in + SDMMC_ICR. + 6 + 1 + + + CMDSENT + Command sent (no response required). + Interrupt flag is cleared by writing corresponding + interrupt clear bit in SDMMC_ICR. + 7 + 1 + + + DATAEND + Data transfer ended correctly. (data + counter, DATACOUNT is zero and no errors occur). + Interrupt flag is cleared by writing corresponding + interrupt clear bit in SDMMC_ICR. + 8 + 1 + + + DHOLD + Data transfer Hold. Interrupt flag is + cleared by writing corresponding interrupt clear bit + in SDMMC_ICR. + 9 + 1 + + + DBCKEND + Data block sent/received. (CRC check + passed) and DPSM moves to the READWAIT state. + Interrupt flag is cleared by writing corresponding + interrupt clear bit in SDMMC_ICR. + 10 + 1 + + + DABORT + Data transfer aborted by CMD12. + Interrupt flag is cleared by writing corresponding + interrupt clear bit in SDMMC_ICR. + 11 + 1 + + + DPSMACT + Data path state machine active, i.e. not + in Idle state. This is a hardware status flag only, + does not generate an interrupt. + 12 + 1 + + + CPSMACT + Command path state machine active, i.e. + not in Idle state. This is a hardware status flag + only, does not generate an interrupt. + 13 + 1 + + + TXFIFOHE + Transmit FIFO half empty At least half + the number of words can be written into the FIFO. + This bit is cleared when the FIFO becomes half+1 + full. + 14 + 1 + + + RXFIFOHF + Receive FIFO half full There are at + least half the number of words in the FIFO. This bit + is cleared when the FIFO becomes half+1 + empty. + 15 + 1 + + + TXFIFOF + Transmit FIFO full This is a hardware + status flag only, does not generate an interrupt. + This bit is cleared when one FIFO location becomes + empty. + 16 + 1 + + + RXFIFOF + Receive FIFO full This bit is cleared + when one FIFO location becomes empty. + 17 + 1 + + + TXFIFOE + Transmit FIFO empty This bit is cleared + when one FIFO location becomes full. + 18 + 1 + + + RXFIFOE + Receive FIFO empty This is a hardware + status flag only, does not generate an interrupt. + This bit is cleared when one FIFO location becomes + full. + 19 + 1 + + + BUSYD0 + Inverted value of SDMMC_D0 line (Busy), + sampled at the end of a CMD response and a second + time 2 SDMMC_CK cycles after the CMD response. This + bit is reset to not busy when the SDMMCD0 line + changes from busy to not busy. This bit does not + signal busy due to data transfer. This is a hardware + status flag only, it does not generate an + interrupt. + 20 + 1 + + + BUSYD0END + end of SDMMC_D0 Busy following a CMD + response detected. This indicates only end of busy + following a CMD response. This bit does not signal + busy due to data transfer. Interrupt flag is cleared + by writing corresponding interrupt clear bit in + SDMMC_ICR. + 21 + 1 + + + SDIOIT + SDIO interrupt received. Interrupt flag + is cleared by writing corresponding interrupt clear + bit in SDMMC_ICR. + 22 + 1 + + + ACKFAIL + Boot acknowledgment received (boot + acknowledgment check fail). Interrupt flag is cleared + by writing corresponding interrupt clear bit in + SDMMC_ICR. + 23 + 1 + + + ACKTIMEOUT + Boot acknowledgment timeout. Interrupt + flag is cleared by writing corresponding interrupt + clear bit in SDMMC_ICR. + 24 + 1 + + + VSWEND + Voltage switch critical timing section + completion. Interrupt flag is cleared by writing + corresponding interrupt clear bit in + SDMMC_ICR. + 25 + 1 + + + CKSTOP + SDMMC_CK stopped in Voltage switch + procedure. Interrupt flag is cleared by writing + corresponding interrupt clear bit in + SDMMC_ICR. + 26 + 1 + + + IDMATE + IDMA transfer error. Interrupt flag is + cleared by writing corresponding interrupt clear bit + in SDMMC_ICR. + 27 + 1 + + + IDMABTC + IDMA buffer transfer complete. interrupt + flag is cleared by writing corresponding interrupt + clear bit in SDMMC_ICR. + 28 + 1 + + + + + ICR + ICR + The SDMMC_ICR register is a write-only + register. Writing a bit with 1 clears the corresponding + bit in the SDMMC_STAR status register. + 0x38 + 0x20 + read-write + 0x00000000 + + + CCRCFAILC + CCRCFAIL flag clear bit Set by software + to clear the CCRCFAIL flag. + 0 + 1 + + + DCRCFAILC + DCRCFAIL flag clear bit Set by software + to clear the DCRCFAIL flag. + 1 + 1 + + + CTIMEOUTC + CTIMEOUT flag clear bit Set by software + to clear the CTIMEOUT flag. + 2 + 1 + + + DTIMEOUTC + DTIMEOUT flag clear bit Set by software + to clear the DTIMEOUT flag. + 3 + 1 + + + TXUNDERRC + TXUNDERR flag clear bit Set by software + to clear TXUNDERR flag. + 4 + 1 + + + RXOVERRC + RXOVERR flag clear bit Set by software + to clear the RXOVERR flag. + 5 + 1 + + + CMDRENDC + CMDREND flag clear bit Set by software + to clear the CMDREND flag. + 6 + 1 + + + CMDSENTC + CMDSENT flag clear bit Set by software + to clear the CMDSENT flag. + 7 + 1 + + + DATAENDC + DATAEND flag clear bit Set by software + to clear the DATAEND flag. + 8 + 1 + + + DHOLDC + DHOLD flag clear bit Set by software to + clear the DHOLD flag. + 9 + 1 + + + DBCKENDC + DBCKEND flag clear bit Set by software + to clear the DBCKEND flag. + 10 + 1 + + + DABORTC + DABORT flag clear bit Set by software to + clear the DABORT flag. + 11 + 1 + + + BUSYD0ENDC + BUSYD0END flag clear bit Set by software + to clear the BUSYD0END flag. + 21 + 1 + + + SDIOITC + SDIOIT flag clear bit Set by software to + clear the SDIOIT flag. + 22 + 1 + + + ACKFAILC + ACKFAIL flag clear bit Set by software + to clear the ACKFAIL flag. + 23 + 1 + + + ACKTIMEOUTC + ACKTIMEOUT flag clear bit Set by + software to clear the ACKTIMEOUT flag. + 24 + 1 + + + VSWENDC + VSWEND flag clear bit Set by software to + clear the VSWEND flag. + 25 + 1 + + + CKSTOPC + CKSTOP flag clear bit Set by software to + clear the CKSTOP flag. + 26 + 1 + + + IDMATEC + IDMA transfer error clear bit Set by + software to clear the IDMATE flag. + 27 + 1 + + + IDMABTCC + IDMA buffer transfer complete clear bit + Set by software to clear the IDMABTC + flag. + 28 + 1 + + + + + MASKR + MASKR + The interrupt mask register determines which + status flags generate an interrupt request by setting the + corresponding bit to 1. + 0x3C + 0x20 + read-write + 0x00000000 + + + CCRCFAILIE + Command CRC fail interrupt enable Set + and cleared by software to enable/disable interrupt + caused by command CRC failure. + 0 + 1 + + + DCRCFAILIE + Data CRC fail interrupt enable Set and + cleared by software to enable/disable interrupt + caused by data CRC failure. + 1 + 1 + + + CTIMEOUTIE + Command timeout interrupt enable Set and + cleared by software to enable/disable interrupt + caused by command timeout. + 2 + 1 + + + DTIMEOUTIE + Data timeout interrupt enable Set and + cleared by software to enable/disable interrupt + caused by data timeout. + 3 + 1 + + + TXUNDERRIE + Tx FIFO underrun error interrupt enable + Set and cleared by software to enable/disable + interrupt caused by Tx FIFO underrun + error. + 4 + 1 + + + RXOVERRIE + Rx FIFO overrun error interrupt enable + Set and cleared by software to enable/disable + interrupt caused by Rx FIFO overrun + error. + 5 + 1 + + + CMDRENDIE + Command response received interrupt + enable Set and cleared by software to enable/disable + interrupt caused by receiving command + response. + 6 + 1 + + + CMDSENTIE + Command sent interrupt enable Set and + cleared by software to enable/disable interrupt + caused by sending command. + 7 + 1 + + + DATAENDIE + Data end interrupt enable Set and + cleared by software to enable/disable interrupt + caused by data end. + 8 + 1 + + + DHOLDIE + Data hold interrupt enable Set and + cleared by software to enable/disable the interrupt + generated when sending new data is hold in the DPSM + Wait_S state. + 9 + 1 + + + DBCKENDIE + Data block end interrupt enable Set and + cleared by software to enable/disable interrupt + caused by data block end. + 10 + 1 + + + DABORTIE + Data transfer aborted interrupt enable + Set and cleared by software to enable/disable + interrupt caused by a data transfer being + aborted. + 11 + 1 + + + TXFIFOHEIE + Tx FIFO half empty interrupt enable Set + and cleared by software to enable/disable interrupt + caused by Tx FIFO half empty. + 14 + 1 + + + RXFIFOHFIE + Rx FIFO half full interrupt enable Set + and cleared by software to enable/disable interrupt + caused by Rx FIFO half full. + 15 + 1 + + + RXFIFOFIE + Rx FIFO full interrupt enable Set and + cleared by software to enable/disable interrupt + caused by Rx FIFO full. + 17 + 1 + + + TXFIFOEIE + Tx FIFO empty interrupt enable Set and + cleared by software to enable/disable interrupt + caused by Tx FIFO empty. + 18 + 1 + + + BUSYD0ENDIE + BUSYD0END interrupt enable Set and + cleared by software to enable/disable the interrupt + generated when SDMMC_D0 signal changes from busy to + NOT busy following a CMD response. + 21 + 1 + + + SDIOITIE + SDIO mode interrupt received interrupt + enable Set and cleared by software to enable/disable + the interrupt generated when receiving the SDIO mode + interrupt. + 22 + 1 + + + ACKFAILIE + Acknowledgment Fail interrupt enable Set + and cleared by software to enable/disable interrupt + caused by acknowledgment Fail. + 23 + 1 + + + ACKTIMEOUTIE + Acknowledgment timeout interrupt enable + Set and cleared by software to enable/disable + interrupt caused by acknowledgment + timeout. + 24 + 1 + + + VSWENDIE + Voltage switch critical timing section + completion interrupt enable Set and cleared by + software to enable/disable the interrupt generated + when voltage switch critical timing section + completion. + 25 + 1 + + + CKSTOPIE + Voltage Switch clock stopped interrupt + enable Set and cleared by software to enable/disable + interrupt caused by Voltage Switch clock + stopped. + 26 + 1 + + + IDMABTCIE + IDMA buffer transfer complete interrupt + enable Set and cleared by software to enable/disable + the interrupt generated when the IDMA has transferred + all data belonging to a memory buffer. + 28 + 1 + + + + + ACKTIMER + ACKTIMER + The SDMMC_ACKTIMER register contains the + acknowledgment timeout period, in SDMMC_CK bus clock + periods. A counter loads the value from the + SDMMC_ACKTIMER register, and starts decrementing when the + data path state machine (DPSM) enters the Wait_Ack state. + If the timer reaches 0 while the DPSM is in this states, + the acknowledgment timeout status flag is + set. + 0x40 + 0x20 + read-write + 0x00000000 + + + ACKTIME + Boot acknowledgment timeout period This + bit can only be written by firmware when CPSM is + disabled (CPSMEN = 0). Boot acknowledgment timeout + period expressed in card bus clock + periods. + 0 + 25 + + + + + IDMACTRLR + IDMACTRLR + The receive and transmit FIFOs can be read + or written as 32-bit wide registers. The FIFOs contain 32 + entries on 32 sequential addresses. This allows the CPU + to use its load and store multiple operands to read + from/write to the FIFO. + 0x50 + 0x20 + read-write + 0x00000000 + + + IDMAEN + IDMA enable This bit can only be written + by firmware when DPSM is inactive (DPSMACT = + 0). + 0 + 1 + + + IDMABMODE + Buffer mode selection. This bit can only + be written by firmware when DPSM is inactive (DPSMACT + = 0). + 1 + 1 + + + IDMABACT + Double buffer mode active buffer + indication This bit can only be written by firmware + when DPSM is inactive (DPSMACT = 0). When IDMA is + enabled this bit is toggled by + hardware. + 2 + 1 + + + + + IDMABSIZER + IDMABSIZER + The SDMMC_IDMABSIZER register contains the + buffers size when in double buffer + configuration. + 0x54 + 0x20 + read-write + 0x00000000 + + + IDMABNDT + Number of transfers per buffer. This + 8-bit value shall be multiplied by 8 to get the size + of the buffer in 32-bit words and by 32 to get the + size of the buffer in bytes. Example: IDMABNDT = + 0x01: buffer size = 8 words = 32 bytes. These bits + can only be written by firmware when DPSM is inactive + (DPSMACT = 0). + 5 + 8 + + + + + IDMABASE0R + IDMABASE0R + The SDMMC_IDMABASE0R register contains the + memory buffer base address in single buffer configuration + and the buffer 0 base address in double buffer + configuration. + 0x58 + 0x20 + read-write + 0x00000000 + + + IDMABASE0 + Buffer 0 memory base address bits + [31:2], shall be word aligned (bit [1:0] are always 0 + and read only). This register can be written by + firmware when DPSM is inactive (DPSMACT = 0), and can + dynamically be written by firmware when DPSM active + (DPSMACT = 1) and memory buffer 0 is inactive + (IDMABACT = 1). + 0 + 32 + + + + + IDMABASE1R + IDMABASE1R + The SDMMC_IDMABASE1R register contains the + double buffer configuration second buffer memory base + address. + 0x5C + 0x20 + read-write + 0x00000000 + + + IDMABASE1 + Buffer 1 memory base address, shall be + word aligned (bit [1:0] are always 0 and read only). + This register can be written by firmware when DPSM is + inactive (DPSMACT = 0), and can dynamically be + written by firmware when DPSM active (DPSMACT = 1) + and memory buffer 1 is inactive (IDMABACT = + 0). + 0 + 32 + + + + + FIFOR + FIFOR + The receive and transmit FIFOs can be only + read or written as word (32-bit) wide registers. The + FIFOs contain 16 entries on sequential addresses. This + allows the CPU to use its load and store multiple + operands to read from/write to the FIFO.When accessing + SDMMC_FIFOR with half word or byte access an AHB bus + fault is generated. + 0x80 + 0x20 + read-write + 0x00000000 + + + FIFODATA + Receive and transmit FIFO data This + register can only be read or written by firmware when + the DPSM is active (DPSMACT=1). The FIFO data + occupies 16 entries of 32-bit words. + 0 + 32 + + + + + VER + VER + SDMMC IP version register + 0x3F4 + 0x20 + read-only + 0x00000010 + + + MINREV + IP minor revision number. + 0 + 4 + + + MAJREV + IP major revision number. + 4 + 4 + + + + + ID + ID + SDMMC IP identification + register + 0x3F8 + 0x20 + read-only + 0x00140022 + + + IP_ID + SDMMC IP identification. + 0 + 32 + + + + + RESPCMDR + RESPCMDR + SDMMC command response + register + 0x10 + 0x20 + read-only + 0xA3C5DD01 + + + RESPCMD + Response command index + 0 + 6 + + + + + + + SDMMC2 + 0x48022400 + + + VREFBUF + VREFBUF + VREFBUF + 0x58003C00 + + 0x0 + 0x400 + registers + + + + CSR + CSR + VREFBUF control and status + register + 0x0 + 0x20 + 0x00000002 + + + ENVR + Voltage reference buffer mode enable + This bit is used to enable the voltage reference + buffer mode. + 0 + 1 + read-write + + + HIZ + High impedance mode This bit controls + the analog switch to connect or not the VREF+ pin. + Refer to Table196: VREF buffer modes for the mode + descriptions depending on ENVR bit + configuration. + 1 + 1 + read-write + + + VRR + Voltage reference buffer + ready + 3 + 1 + read-only + + + VRS + Voltage reference scale These bits + select the value generated by the voltage reference + buffer. Other: Reserved + 4 + 3 + read-write + + + + + CCR + CCR + VREFBUF calibration control + register + 0x4 + 0x20 + read-write + 0x00000000 + + + TRIM + Trimming code These bits are + automatically initialized after reset with the + trimming value stored in the Flash memory during the + production test. Writing into these bits allows to + tune the internal reference buffer + voltage. + 0 + 6 + + + + + + + IWDG + IWDG + IWDG + 0x58004800 + + 0x0 + 0x400 + registers + + + + KR + KR + Key register + 0x0 + 0x20 + write-only + 0x00000000 + + + KEY + Key value (write only, read 0x0000) + These bits must be written by software at regular + intervals with the key value 0xAAAA, otherwise the + watchdog generates a reset when the counter reaches + 0. Writing the key value 0x5555 to enable access to + the IWDG_PR, IWDG_RLR and IWDG_WINR registers (see + Section23.3.6: Register access protection) Writing + the key value CCCCh starts the watchdog (except if + the hardware watchdog option is + selected) + 0 + 16 + + + + + PR + PR + Prescaler register + 0x4 + 0x20 + read-write + 0x00000000 + + + PR + Prescaler divider These bits are write + access protected see Section23.3.6: Register access + protection. They are written by software to select + the prescaler divider feeding the counter clock. PVU + bit of IWDG_SR must be reset in order to be able to + change the prescaler divider. Note: Reading this + register returns the prescaler value from the VDD + voltage domain. This value may not be up to + date/valid if a write operation to this register is + ongoing. For this reason the value read from this + register is valid only when the PVU bit in the + IWDG_SR register is reset. + 0 + 3 + + + + + RLR + RLR + Reload register + 0x8 + 0x20 + read-write + 0x00000FFF + + + RL + Watchdog counter reload value These bits + are write access protected see Section23.3.6. They + are written by software to define the value to be + loaded in the watchdog counter each time the value + 0xAAAA is written in the IWDG_KR register. The + watchdog counter counts down from this value. The + timeout period is a function of this value and the + clock prescaler. Refer to the datasheet for the + timeout information. The RVU bit in the IWDG_SR + register must be reset in order to be able to change + the reload value. Note: Reading this register returns + the reload value from the VDD voltage domain. This + value may not be up to date/valid if a write + operation to this register is ongoing on this + register. For this reason the value read from this + register is valid only when the RVU bit in the + IWDG_SR register is reset. + 0 + 12 + + + + + SR + SR + Status register + 0xC + 0x20 + read-only + 0x00000000 + + + PVU + Watchdog prescaler value update This bit + is set by hardware to indicate that an update of the + prescaler value is ongoing. It is reset by hardware + when the prescaler update operation is completed in + the VDD voltage domain (takes up to 5 RC 40 kHz + cycles). Prescaler value can be updated only when PVU + bit is reset. + 0 + 1 + + + RVU + Watchdog counter reload value update + This bit is set by hardware to indicate that an + update of the reload value is ongoing. It is reset by + hardware when the reload value update operation is + completed in the VDD voltage domain (takes up to 5 RC + 40 kHz cycles). Reload value can be updated only when + RVU bit is reset. + 1 + 1 + + + WVU + Watchdog counter window value update + This bit is set by hardware to indicate that an + update of the window value is ongoing. It is reset by + hardware when the reload value update operation is + completed in the VDD voltage domain (takes up to 5 RC + 40 kHz cycles). Window value can be updated only when + WVU bit is reset. This bit is generated only if + generic window = 1 + 2 + 1 + + + + + WINR + WINR + Window register + 0x10 + 0x20 + read-write + 0x00000FFF + + + WIN + Watchdog counter window value These bits + are write access protected see Section23.3.6. These + bits contain the high limit of the window value to be + compared to the downcounter. To prevent a reset, the + downcounter must be reloaded when its value is lower + than the window register value and greater than 0x0 + The WVU bit in the IWDG_SR register must be reset in + order to be able to change the reload value. Note: + Reading this register returns the reload value from + the VDD voltage domain. This value may not be valid + if a write operation to this register is ongoing. For + this reason the value read from this register is + valid only when the WVU bit in the IWDG_SR register + is reset. + 0 + 12 + + + + + + + WWDG + WWDG + WWDG + 0x50003000 + + 0x0 + 0x400 + registers + + + WWDG1 + Window Watchdog interrupt + 0 + + + WWDG1_RST + Window Watchdog interrupt + 143 + + + + CR + CR + Control register + 0x0 + 0x20 + read-write + 0x0000007F + + + T + 7-bit counter (MSB to LSB) These bits + contain the value of the watchdog counter. It is + decremented every (4096 x 2WDGTB[1:0]) PCLK cycles. A + reset is produced when it is decremented from 0x40 to + 0x3F (T6 becomes cleared). + 0 + 7 + + + WDGA + Activation bit This bit is set by + software and only cleared by hardware after a reset. + When WDGA=1, the watchdog can generate a + reset. + 7 + 1 + + + + + CFR + CFR + Configuration register + 0x4 + 0x20 + read-write + 0x0000007F + + + W + 7-bit window value These bits contain + the window value to be compared to the + downcounter. + 0 + 7 + + + WDGTB + Timer base The time base of the + prescaler can be modified as follows: + 11 + 2 + + + EWI + Early wakeup interrupt When set, an + interrupt occurs whenever the counter reaches the + value 0x40. This interrupt is only cleared by + hardware after a reset. + 9 + 1 + + + + + SR + SR + Status register + 0x8 + 0x20 + read-write + 0x00000000 + + + EWIF + Early wakeup interrupt flag This bit is + set by hardware when the counter has reached the + value 0x40. It must be cleared by software by writing + 0. A write of 1 has no effect. This bit is also set + if the interrupt is not enabled. + 0 + 1 + + + + + + + PWR + PWR + PWR + 0x58024800 + + 0x0 + 0x400 + registers + + + + CR1 + CR1 + PWR control register 1 + 0x0 + 0x20 + read-write + 0xF000C000 + + + LPDS + Low-power Deepsleep with SVOS3 (SVOS4 + and SVOS5 always use low-power, regardless of the + setting of this bit) + 0 + 1 + + + PVDE + Programmable voltage detector + enable + 4 + 1 + + + PLS + Programmable voltage detector level + selection These bits select the voltage threshold + detected by the PVD. Note: Refer to Section + Electrical characteristics of the product datasheet + for more details. + 5 + 3 + + + DBP + Disable backup domain write protection + In reset state, the RCC_BDCR register, the RTC + registers (including the backup registers), BREN and + MOEN bits in PWR_CR2 register, are protected against + parasitic write access. This bit must be set to + enable write access to these registers. + 8 + 1 + + + FLPS + Flash low-power mode in DStop mode This + bit allows to obtain the best trade-off between + low-power consumption and restart time when exiting + from DStop mode. When it is set, the Flash memory + enters low-power mode when D1 domain is in DStop + mode. + 9 + 1 + + + SVOS + System Stop mode voltage scaling + selection These bits control the VCORE voltage level + in system Stop mode, to obtain the best trade-off + between power consumption and + performance. + 14 + 2 + + + AVDEN + Peripheral voltage monitor on VDDA + enable + 16 + 1 + + + ALS + Analog voltage detector level selection + These bits select the voltage threshold detected by + the AVD. + 17 + 2 + + + + + CSR1 + CSR1 + PWR control status register 1 + 0x4 + 0x20 + read-only + 0x00004000 + + + PVDO + Programmable voltage detect output This + bit is set and cleared by hardware. It is valid only + if the PVD has been enabled by the PVDE bit. Note: + since the PVD is disabled in Standby mode, this bit + is equal to 0 after Standby or reset until the PVDE + bit is set. + 4 + 1 + + + ACTVOSRDY + Voltage levels ready bit for currently + used VOS and SDLEVEL This bit is set to 1 by hardware + when the voltage regulator and the SD converter are + both disabled and Bypass mode is selected in PWR + control register 3 (PWR_CR3). + 13 + 1 + + + ACTVOS + VOS currently applied for VCORE voltage + scaling selection. These bits reflect the last VOS + value applied to the PMU. + 14 + 2 + + + AVDO + Analog voltage detector output on VDDA + This bit is set and cleared by hardware. It is valid + only if AVD on VDDA is enabled by the AVDEN bit. + Note: Since the AVD is disabled in Standby mode, this + bit is equal to 0 after Standby or reset until the + AVDEN bit is set. + 16 + 1 + + + + + CR2 + CR2 + This register is not reset by wakeup from + Standby mode, RESET signal and VDD POR. It is only reset + by VSW POR and VSWRST reset. This register shall not be + accessed when VSWRST bit in RCC_BDCR register resets the + VSW domain.After reset, PWR_CR2 register is + write-protected. Prior to modifying its content, the DBP + bit in PWR_CR1 register must be set to disable the write + protection. + 0x8 + 0x20 + 0x00000000 + + + BREN + Backup regulator enable When set, the + Backup regulator (used to maintain the backup RAM + content in Standby and VBAT modes) is enabled. If + BREN is reset, the backup regulator is switched off. + The backup RAM can still be used in Run and Stop + modes. However, its content will be lost in Standby + and VBAT modes. If BREN is set, the application must + wait till the Backup Regulator Ready flag (BRRDY) is + set to indicate that the data written into the SRAM + will be maintained in Standby and VBAT + modes. + 0 + 1 + read-write + + + MONEN + VBAT and temperature monitoring enable + When set, the VBAT supply and temperature monitoring + is enabled. + 4 + 1 + read-write + + + BRRDY + Backup regulator ready This bit is set + by hardware to indicate that the Backup regulator is + ready. + 16 + 1 + read-only + + + VBATL + VBAT level monitoring versus low + threshold + 20 + 1 + read-only + + + VBATH + VBAT level monitoring versus high + threshold + 21 + 1 + read-only + + + TEMPL + Temperature level monitoring versus low + threshold + 22 + 1 + read-only + + + TEMPH + Temperature level monitoring versus high + threshold + 23 + 1 + read-only + + + + + CR3 + CR3 + Reset only by POR only, not reset by wakeup + from Standby mode and RESET pad. The lower byte of this + register is written once after POR and shall be written + before changing VOS level or ck_sys clock frequency. No + limitation applies to the upper bytes.Programming data + corresponding to an invalid combination of SDLEVEL, + SDEXTHP, SDEN, LDOEN and BYPASS bits (see Table9) will be + ignored: data will not be written, the written-once + mechanism will lock the register and any further write + access will be ignored. The default supply configuration + will be kept and the ACTVOSRDY bit in PWR control status + register 1 (PWR_CSR1) will go on indicating invalid + voltage levels. The system shall be power cycled before + writing a new value. + 0xC + 0x20 + 0x00000006 + + + BYPASS + Power management unit + bypass + 0 + 1 + read-write + + + LDOEN + Low drop-out regulator + enable + 1 + 1 + read-write + + + SCUEN + SD converter Enable + 2 + 1 + read-write + + + VBE + VBAT charging enable + 8 + 1 + read-write + + + VBRS + VBAT charging resistor + selection + 9 + 1 + read-write + + + USB33DEN + VDD33USB voltage level detector + enable. + 24 + 1 + read-write + + + USBREGEN + USB regulator enable. + 25 + 1 + read-write + + + USB33RDY + USB supply ready. + 26 + 1 + read-only + + + + + CPUCR + CPUCR + This register allows controlling CPU1 + power. + 0x10 + 0x20 + 0x00000000 + + + PDDS_D1 + D1 domain Power Down Deepsleep + selection. This bit allows CPU1 to define the + Deepsleep mode for D1 domain. + 0 + 1 + read-write + + + PDDS_D2 + D2 domain Power Down Deepsleep. This bit + allows CPU1 to define the Deepsleep mode for D2 + domain. + 1 + 1 + read-write + + + PDDS_D3 + System D3 domain Power Down Deepsleep. + This bit allows CPU1 to define the Deepsleep mode for + System D3 domain. + 2 + 1 + read-write + + + STOPF + STOP flag This bit is set by hardware + and cleared only by any reset or by setting the CPU1 + CSSF bit. + 5 + 1 + read-only + + + SBF + System Standby flag This bit is set by + hardware and cleared only by a POR (Power-on Reset) + or by setting the CPU1 CSSF bit + 6 + 1 + read-only + + + SBF_D1 + D1 domain DStandby flag This bit is set + by hardware and cleared by any system reset or by + setting the CPU1 CSSF bit. Once set, this bit can be + cleared only when the D1 domain is no longer in + DStandby mode. + 7 + 1 + read-only + + + SBF_D2 + D2 domain DStandby flag This bit is set + by hardware and cleared by any system reset or by + setting the CPU1 CSSF bit. Once set, this bit can be + cleared only when the D2 domain is no longer in + DStandby mode. + 8 + 1 + read-only + + + CSSF + Clear D1 domain CPU1 Standby, Stop and + HOLD flags (always read as 0) This bit is cleared to + 0 by hardware. + 9 + 1 + read-write + + + RUN_D3 + Keep system D3 domain in Run mode + regardless of the CPU sub-systems modes + 11 + 1 + read-write + + + + + D3CR + D3CR + This register allows controlling D3 domain + power.Following reset VOSRDY will be read 1 by + software + 0x18 + 0x20 + 0x00004000 + + + VOSRDY + VOS Ready bit for VCORE voltage scaling + output selection. This bit is set to 1 by hardware + when Bypass mode is selected in PWR control register + 3 (PWR_CR3). + 13 + 1 + read-only + + + VOS + Voltage scaling selection according to + performance These bits control the VCORE voltage + level and allow to obtains the best trade-off between + power consumption and performance: When increasing + the performance, the voltage scaling shall be changed + before increasing the system frequency. When + decreasing performance, the system frequency shall + first be decreased before changing the voltage + scaling. + 14 + 2 + read-write + + + + + WKUPCR + WKUPCR + reset only by system reset, not reset by + wakeup from Standby mode5 wait states are required when + writing this register (when clearing a WKUPF bit in + PWR_WKUPFR, the AHB write access will complete after the + WKUPF has been cleared). + 0x20 + 0x20 + read-write + 0x00000000 + + + WKUPC + Clear Wakeup pin flag for WKUP. These + bits are always read as 0. + 0 + 6 + + + + + WKUPFR + WKUPFR + reset only by system reset, not reset by + wakeup from Standby mode + 0x24 + 0x20 + read-write + 0x00000000 + + + WKUPF1 + Wakeup pin WKUPF flag. This bit is set + by hardware and cleared only by a Reset pin or by + setting the WKUPCn+1 bit in the PWR wakeup clear + register (PWR_WKUPCR). + 0 + 1 + + + WKUPF2 + Wakeup pin WKUPF flag. This bit is set + by hardware and cleared only by a Reset pin or by + setting the WKUPCn+1 bit in the PWR wakeup clear + register (PWR_WKUPCR). + 1 + 1 + + + WKUPF3 + Wakeup pin WKUPF flag. This bit is set + by hardware and cleared only by a Reset pin or by + setting the WKUPCn+1 bit in the PWR wakeup clear + register (PWR_WKUPCR). + 2 + 1 + + + WKUPF4 + Wakeup pin WKUPF flag. This bit is set + by hardware and cleared only by a Reset pin or by + setting the WKUPCn+1 bit in the PWR wakeup clear + register (PWR_WKUPCR). + 3 + 1 + + + WKUPF5 + Wakeup pin WKUPF flag. This bit is set + by hardware and cleared only by a Reset pin or by + setting the WKUPCn+1 bit in the PWR wakeup clear + register (PWR_WKUPCR). + 4 + 1 + + + WKUPF6 + Wakeup pin WKUPF flag. This bit is set + by hardware and cleared only by a Reset pin or by + setting the WKUPCn+1 bit in the PWR wakeup clear + register (PWR_WKUPCR). + 5 + 1 + + + + + WKUPEPR + WKUPEPR + Reset only by system reset, not reset by + wakeup from Standby mode + 0x28 + 0x20 + read-write + 0x00000000 + + + WKUPEN1 + Enable Wakeup Pin WKUPn+1 Each bit is + set and cleared by software. Note: An additional + wakeup event is detected if WKUPn+1 pin is enabled + (by setting the WKUPENn+1 bit) when WKUPn+1 pin level + is already high when WKUPPn+1 selects rising edge, or + low when WKUPPn+1 selects falling edge. + 0 + 1 + + + WKUPEN2 + Enable Wakeup Pin WKUPn+1 Each bit is + set and cleared by software. Note: An additional + wakeup event is detected if WKUPn+1 pin is enabled + (by setting the WKUPENn+1 bit) when WKUPn+1 pin level + is already high when WKUPPn+1 selects rising edge, or + low when WKUPPn+1 selects falling edge. + 1 + 1 + + + WKUPEN3 + Enable Wakeup Pin WKUPn+1 Each bit is + set and cleared by software. Note: An additional + wakeup event is detected if WKUPn+1 pin is enabled + (by setting the WKUPENn+1 bit) when WKUPn+1 pin level + is already high when WKUPPn+1 selects rising edge, or + low when WKUPPn+1 selects falling edge. + 2 + 1 + + + WKUPEN4 + Enable Wakeup Pin WKUPn+1 Each bit is + set and cleared by software. Note: An additional + wakeup event is detected if WKUPn+1 pin is enabled + (by setting the WKUPENn+1 bit) when WKUPn+1 pin level + is already high when WKUPPn+1 selects rising edge, or + low when WKUPPn+1 selects falling edge. + 3 + 1 + + + WKUPEN5 + Enable Wakeup Pin WKUPn+1 Each bit is + set and cleared by software. Note: An additional + wakeup event is detected if WKUPn+1 pin is enabled + (by setting the WKUPENn+1 bit) when WKUPn+1 pin level + is already high when WKUPPn+1 selects rising edge, or + low when WKUPPn+1 selects falling edge. + 4 + 1 + + + WKUPEN6 + Enable Wakeup Pin WKUPn+1 Each bit is + set and cleared by software. Note: An additional + wakeup event is detected if WKUPn+1 pin is enabled + (by setting the WKUPENn+1 bit) when WKUPn+1 pin level + is already high when WKUPPn+1 selects rising edge, or + low when WKUPPn+1 selects falling edge. + 5 + 1 + + + WKUPP1 + Wakeup pin polarity bit for WKUPn-7 + These bits define the polarity used for event + detection on WKUPn-7 external wakeup + pin. + 8 + 1 + + + WKUPP2 + Wakeup pin polarity bit for WKUPn-7 + These bits define the polarity used for event + detection on WKUPn-7 external wakeup + pin. + 9 + 1 + + + WKUPP3 + Wakeup pin polarity bit for WKUPn-7 + These bits define the polarity used for event + detection on WKUPn-7 external wakeup + pin. + 10 + 1 + + + WKUPP4 + Wakeup pin polarity bit for WKUPn-7 + These bits define the polarity used for event + detection on WKUPn-7 external wakeup + pin. + 11 + 1 + + + WKUPP5 + Wakeup pin polarity bit for WKUPn-7 + These bits define the polarity used for event + detection on WKUPn-7 external wakeup + pin. + 12 + 1 + + + WKUPP6 + Wakeup pin polarity bit for WKUPn-7 + These bits define the polarity used for event + detection on WKUPn-7 external wakeup + pin. + 13 + 1 + + + WKUPPUPD1 + Wakeup pin pull + configuration + 16 + 2 + + + WKUPPUPD2 + Wakeup pin pull + configuration + 18 + 2 + + + WKUPPUPD3 + Wakeup pin pull + configuration + 20 + 2 + + + WKUPPUPD4 + Wakeup pin pull + configuration + 22 + 2 + + + WKUPPUPD5 + Wakeup pin pull + configuration + 24 + 2 + + + WKUPPUPD6 + Wakeup pin pull configuration for + WKUP(truncate(n/2)-7) These bits define the I/O pad + pull configuration used when WKUPEN(truncate(n/2)-7) + = 1. The associated GPIO port pull configuration + shall be set to the same value or to 00. The Wakeup + pin pull configuration is kept in Standby + mode. + 26 + 2 + + + + + + + SPI1 + Serial peripheral interface + SPI + 0x40013000 + + 0x0 + 0x400 + registers + + + SPI1 + SPI1 global interrupt + 35 + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + 0x00000000 + + + IOLOCK + Locking the AF configuration of + associated IOs + 16 + 1 + read-only + + + TCRCI + CRC calculation initialization pattern + control for transmitter + 15 + 1 + read-write + + + RCRCI + CRC calculation initialization pattern + control for receiver + 14 + 1 + read-write + + + CRC33_17 + 32-bit CRC polynomial + configuration + 13 + 1 + read-write + + + SSI + Internal SS signal input + level + 12 + 1 + read-write + + + HDDIR + Rx/Tx direction at Half-duplex + mode + 11 + 1 + read-write + + + CSUSP + Master SUSPend request + 10 + 1 + write-only + + + CSTART + Master transfer start + 9 + 1 + read-only + + + MASRX + Master automatic SUSP in Receive + mode + 8 + 1 + read-write + + + SPE + Serial Peripheral Enable + 0 + 1 + read-write + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + 0x00000000 + + + TSER + Number of data transfer extension to be + reload into TSIZE just when a previous + 16 + 16 + read-only + + + TSIZE + Number of data at current + transfer + 0 + 16 + read-write + + + + + CFG1 + CFG1 + configuration register 1 + 0x8 + 0x20 + read-write + 0x00070007 + + + MBR + Master baud rate + 28 + 3 + + + CRCEN + Hardware CRC computation + enable + 22 + 1 + + + CRCSIZE + Length of CRC frame to be transacted and + compared + 16 + 5 + + + TXDMAEN + Tx DMA stream enable + 15 + 1 + + + RXDMAEN + Rx DMA stream enable + 14 + 1 + + + UDRDET + Detection of underrun condition at slave + transmitter + 11 + 2 + + + UDRCFG + Behavior of slave transmitter at + underrun condition + 9 + 2 + + + FTHVL + threshold level + 5 + 4 + + + DSIZE + Number of bits in at single SPI data + frame + 0 + 5 + + + + + CFG2 + CFG2 + configuration register 2 + 0xC + 0x20 + read-write + 0x00000000 + + + AFCNTR + Alternate function GPIOs + control + 31 + 1 + + + SSOM + SS output management in master + mode + 30 + 1 + + + SSOE + SS output enable + 29 + 1 + + + SSIOP + SS input/output polarity + 28 + 1 + + + SSM + Software management of SS signal + input + 26 + 1 + + + CPOL + Clock polarity + 25 + 1 + + + CPHA + Clock phase + 24 + 1 + + + LSBFRST + Data frame format + 23 + 1 + + + MASTER + SPI Master + 22 + 1 + + + SP + Serial Protocol + 19 + 3 + + + COMM + SPI Communication Mode + 17 + 2 + + + IOSWP + Swap functionality of MISO and MOSI + pins + 15 + 1 + + + MIDI + Master Inter-Data Idleness + 4 + 4 + + + MSSI + Master SS Idleness + 0 + 4 + + + + + IER + IER + Interrupt Enable Register + 0x10 + 0x20 + 0x00000000 + + + TSERFIE + Additional number of transactions reload + interrupt enable + 10 + 1 + read-write + + + MODFIE + Mode Fault interrupt + enable + 9 + 1 + read-write + + + TIFREIE + TIFRE interrupt enable + 8 + 1 + read-write + + + CRCEIE + CRC Interrupt enable + 7 + 1 + read-write + + + OVRIE + OVR interrupt enable + 6 + 1 + read-write + + + UDRIE + UDR interrupt enable + 5 + 1 + read-write + + + TXTFIE + TXTFIE interrupt enable + 4 + 1 + read-write + + + EOTIE + EOT, SUSP and TXC interrupt + enable + 3 + 1 + read-write + + + DPXPIE + DXP interrupt enabled + 2 + 1 + read-only + + + TXPIE + TXP interrupt enable + 1 + 1 + read-only + + + RXPIE + RXP Interrupt Enable + 0 + 1 + read-write + + + + + SR + SR + Status Register + 0x14 + 0x20 + read-only + 0x00001002 + + + CTSIZE + Number of data frames remaining in + current TSIZE session + 16 + 16 + + + RXWNE + RxFIFO Word Not Empty + 15 + 1 + + + RXPLVL + RxFIFO Packing LeVeL + 13 + 2 + + + TXC + TxFIFO transmission + complete + 12 + 1 + + + SUSP + SUSPend + 11 + 1 + + + TSERF + Additional number of SPI data to be + transacted was reload + 10 + 1 + + + MODF + Mode Fault + 9 + 1 + + + TIFRE + TI frame format error + 8 + 1 + + + CRCE + CRC Error + 7 + 1 + + + OVR + Overrun + 6 + 1 + + + UDR + Underrun at slave transmission + mode + 5 + 1 + + + TXTF + Transmission Transfer + Filled + 4 + 1 + + + EOT + End Of Transfer + 3 + 1 + + + DXP + Duplex Packet + 2 + 1 + + + TXP + Tx-Packet space available + 1 + 1 + + + RXP + Rx-Packet available + 0 + 1 + + + + + IFCR + IFCR + Interrupt/Status Flags Clear + Register + 0x18 + 0x20 + write-only + 0x00000000 + + + SUSPC + SUSPend flag clear + 11 + 1 + + + TSERFC + TSERFC flag clear + 10 + 1 + + + MODFC + Mode Fault flag clear + 9 + 1 + + + TIFREC + TI frame format error flag + clear + 8 + 1 + + + CRCEC + CRC Error flag clear + 7 + 1 + + + OVRC + Overrun flag clear + 6 + 1 + + + UDRC + Underrun flag clear + 5 + 1 + + + TXTFC + Transmission Transfer Filled flag + clear + 4 + 1 + + + EOTC + End Of Transfer flag clear + 3 + 1 + + + + + TXDR + TXDR + Transmit Data Register + 0x20 + 0x20 + write-only + 0x00000000 + + + TXDR + Transmit data register + 0 + 32 + + + + + RXDR + RXDR + Receive Data Register + 0x30 + 0x20 + read-only + 0x00000000 + + + RXDR + Receive data register + 0 + 32 + + + + + CRCPOLY + CRCPOLY + Polynomial Register + 0x40 + 0x20 + read-write + 0x00000107 + + + CRCPOLY + CRC polynomial register + 0 + 32 + + + + + TXCRC + TXCRC + Transmitter CRC Register + 0x44 + 0x20 + read-write + 0x00000000 + + + TXCRC + CRC register for + transmitter + 0 + 32 + + + + + RXCRC + RXCRC + Receiver CRC Register + 0x48 + 0x20 + read-write + 0x00000000 + + + RXCRC + CRC register for receiver + 0 + 32 + + + + + UDRDR + UDRDR + Underrun Data Register + 0x4C + 0x20 + read-write + 0x00000000 + + + UDRDR + Data at slave underrun + condition + 0 + 32 + + + + + CGFR + CGFR + configuration register + 0x50 + 0x20 + read-write + 0x00000000 + + + MCKOE + Master clock output enable + 25 + 1 + + + ODD + Odd factor for the + prescaler + 24 + 1 + + + I2SDIV + I2S linear prescaler + 16 + 8 + + + DATFMT + Data format + 14 + 1 + + + WSINV + Fixed channel length in + SLAVE + 13 + 1 + + + FIXCH + Word select inversion + 12 + 1 + + + CKPOL + Serial audio clock + polarity + 11 + 1 + + + CHLEN + Channel length (number of bits per audio + channel) + 10 + 1 + + + DATLEN + Data length to be + transferred + 8 + 2 + + + PCMSYNC + PCM frame synchronization + 7 + 1 + + + I2SSTD + I2S standard selection + 4 + 2 + + + I2SCFG + I2S configuration mode + 1 + 3 + + + I2SMOD + I2S mode selection + 0 + 1 + + + + + + + SPI2 + 0x40003800 + + SPI2 + SPI2 global interrupt + 36 + + + + SPI3 + 0x40003C00 + + SPI3 + SPI3 global interrupt + 51 + + + + SPI4 + 0x40013400 + + SPI4 + SPI4 global interrupt + 84 + + + + SPI5 + 0x40015000 + + SPI5 + SPI5 global interrupt + 85 + + + + SPI6 + 0x58001400 + + SPI6 + SPI6 global interrupt + 86 + + + + LTDC + LCD-TFT Controller + LTDC + 0x50001000 + + 0x0 + 0x1000 + registers + + + LTDC + LCD-TFT global interrupt + 88 + + + LTDC_ER + LCD-TFT error interrupt + 89 + + + + SSCR + SSCR + Synchronization Size Configuration + Register + 0x8 + 0x20 + read-write + 0x00000000 + + + HSW + Horizontal Synchronization Width (in + units of pixel clock period) + 16 + 10 + + + VSH + Vertical Synchronization Height (in + units of horizontal scan line) + 0 + 11 + + + + + BPCR + BPCR + Back Porch Configuration + Register + 0xC + 0x20 + read-write + 0x00000000 + + + AHBP + Accumulated Horizontal back porch (in + units of pixel clock period) + 16 + 12 + + + AVBP + Accumulated Vertical back porch (in + units of horizontal scan line) + 0 + 11 + + + + + AWCR + AWCR + Active Width Configuration + Register + 0x10 + 0x20 + read-write + 0x00000000 + + + AAV + AAV + 16 + 12 + + + AAH + Accumulated Active Height (in units of + horizontal scan line) + 0 + 11 + + + + + TWCR + TWCR + Total Width Configuration + Register + 0x14 + 0x20 + read-write + 0x00000000 + + + TOTALW + Total Width (in units of pixel clock + period) + 16 + 12 + + + TOTALH + Total Height (in units of horizontal + scan line) + 0 + 11 + + + + + GCR + GCR + Global Control Register + 0x18 + 0x20 + 0x00002220 + + + HSPOL + Horizontal Synchronization + Polarity + 31 + 1 + read-write + + + VSPOL + Vertical Synchronization + Polarity + 30 + 1 + read-write + + + DEPOL + Data Enable Polarity + 29 + 1 + read-write + + + PCPOL + Pixel Clock Polarity + 28 + 1 + read-write + + + DEN + Dither Enable + 16 + 1 + read-write + + + DRW + Dither Red Width + 12 + 3 + read-only + + + DGW + Dither Green Width + 8 + 3 + read-only + + + DBW + Dither Blue Width + 4 + 3 + read-only + + + LTDCEN + LCD-TFT controller enable + bit + 0 + 1 + read-write + + + + + SRCR + SRCR + Shadow Reload Configuration + Register + 0x24 + 0x20 + read-write + 0x00000000 + + + VBR + Vertical Blanking Reload + 1 + 1 + + + IMR + Immediate Reload + 0 + 1 + + + + + BCCR + BCCR + Background Color Configuration + Register + 0x2C + 0x20 + read-write + 0x00000000 + + + BCBLUE + Background Color Blue + value + 0 + 8 + + + BCGREEN + Background Color Green + value + 8 + 8 + + + BCRED + Background Color Red value + 16 + 8 + + + + + IER + IER + Interrupt Enable Register + 0x34 + 0x20 + read-write + 0x00000000 + + + RRIE + Register Reload interrupt + enable + 3 + 1 + + + TERRIE + Transfer Error Interrupt + Enable + 2 + 1 + + + FUIE + FIFO Underrun Interrupt + Enable + 1 + 1 + + + LIE + Line Interrupt Enable + 0 + 1 + + + + + ISR + ISR + Interrupt Status Register + 0x38 + 0x20 + read-only + 0x00000000 + + + RRIF + Register Reload Interrupt + Flag + 3 + 1 + + + TERRIF + Transfer Error interrupt + flag + 2 + 1 + + + FUIF + FIFO Underrun Interrupt + flag + 1 + 1 + + + LIF + Line Interrupt flag + 0 + 1 + + + + + ICR + ICR + Interrupt Clear Register + 0x3C + 0x20 + write-only + 0x00000000 + + + CRRIF + Clears Register Reload Interrupt + Flag + 3 + 1 + + + CTERRIF + Clears the Transfer Error Interrupt + Flag + 2 + 1 + + + CFUIF + Clears the FIFO Underrun Interrupt + flag + 1 + 1 + + + CLIF + Clears the Line Interrupt + Flag + 0 + 1 + + + + + LIPCR + LIPCR + Line Interrupt Position Configuration + Register + 0x40 + 0x20 + read-write + 0x00000000 + + + LIPOS + Line Interrupt Position + 0 + 11 + + + + + CPSR + CPSR + Current Position Status + Register + 0x44 + 0x20 + read-only + 0x00000000 + + + CXPOS + Current X Position + 16 + 16 + + + CYPOS + Current Y Position + 0 + 16 + + + + + CDSR + CDSR + Current Display Status + Register + 0x48 + 0x20 + read-only + 0x0000000F + + + HSYNCS + Horizontal Synchronization display + Status + 3 + 1 + + + VSYNCS + Vertical Synchronization display + Status + 2 + 1 + + + HDES + Horizontal Data Enable display + Status + 1 + 1 + + + VDES + Vertical Data Enable display + Status + 0 + 1 + + + + + L1CR + L1CR + Layerx Control Register + 0x84 + 0x20 + read-write + 0x00000000 + + + CLUTEN + Color Look-Up Table Enable + 4 + 1 + + + COLKEN + Color Keying Enable + 1 + 1 + + + LEN + Layer Enable + 0 + 1 + + + + + L1WHPCR + L1WHPCR + Layerx Window Horizontal Position + Configuration Register + 0x88 + 0x20 + read-write + 0x00000000 + + + WHSPPOS + Window Horizontal Stop + Position + 16 + 12 + + + WHSTPOS + Window Horizontal Start + Position + 0 + 12 + + + + + L1WVPCR + L1WVPCR + Layerx Window Vertical Position + Configuration Register + 0x8C + 0x20 + read-write + 0x00000000 + + + WVSPPOS + Window Vertical Stop + Position + 16 + 11 + + + WVSTPOS + Window Vertical Start + Position + 0 + 11 + + + + + L1CKCR + L1CKCR + Layerx Color Keying Configuration + Register + 0x90 + 0x20 + read-write + 0x00000000 + + + CKRED + Color Key Red value + 16 + 8 + + + CKGREEN + Color Key Green value + 8 + 8 + + + CKBLUE + Color Key Blue value + 0 + 8 + + + + + L1PFCR + L1PFCR + Layerx Pixel Format Configuration + Register + 0x94 + 0x20 + read-write + 0x00000000 + + + PF + Pixel Format + 0 + 3 + + + + + L1CACR + L1CACR + Layerx Constant Alpha Configuration + Register + 0x98 + 0x20 + read-write + 0x00000000 + + + CONSTA + Constant Alpha + 0 + 8 + + + + + L1DCCR + L1DCCR + Layerx Default Color Configuration + Register + 0x9C + 0x20 + read-write + 0x00000000 + + + DCALPHA + Default Color Alpha + 24 + 8 + + + DCRED + Default Color Red + 16 + 8 + + + DCGREEN + Default Color Green + 8 + 8 + + + DCBLUE + Default Color Blue + 0 + 8 + + + + + L1BFCR + L1BFCR + Layerx Blending Factors Configuration + Register + 0xA0 + 0x20 + read-write + 0x00000607 + + + BF1 + Blending Factor 1 + 8 + 3 + + + BF2 + Blending Factor 2 + 0 + 3 + + + + + L1CFBAR + L1CFBAR + Layerx Color Frame Buffer Address + Register + 0xAC + 0x20 + read-write + 0x00000000 + + + CFBADD + Color Frame Buffer Start + Address + 0 + 32 + + + + + L1CFBLR + L1CFBLR + Layerx Color Frame Buffer Length + Register + 0xB0 + 0x20 + read-write + 0x00000000 + + + CFBP + Color Frame Buffer Pitch in + bytes + 16 + 13 + + + CFBLL + Color Frame Buffer Line + Length + 0 + 13 + + + + + L1CFBLNR + L1CFBLNR + Layerx ColorFrame Buffer Line Number + Register + 0xB4 + 0x20 + read-write + 0x00000000 + + + CFBLNBR + Frame Buffer Line Number + 0 + 11 + + + + + L1CLUTWR + L1CLUTWR + Layerx CLUT Write Register + 0xC4 + 0x20 + write-only + 0x00000000 + + + CLUTADD + CLUT Address + 24 + 8 + + + RED + Red value + 16 + 8 + + + GREEN + Green value + 8 + 8 + + + BLUE + Blue value + 0 + 8 + + + + + L2CR + L2CR + Layerx Control Register + 0x104 + 0x20 + read-write + 0x00000000 + + + CLUTEN + Color Look-Up Table Enable + 4 + 1 + + + COLKEN + Color Keying Enable + 1 + 1 + + + LEN + Layer Enable + 0 + 1 + + + + + L2WHPCR + L2WHPCR + Layerx Window Horizontal Position + Configuration Register + 0x108 + 0x20 + read-write + 0x00000000 + + + WHSPPOS + Window Horizontal Stop + Position + 16 + 12 + + + WHSTPOS + Window Horizontal Start + Position + 0 + 12 + + + + + L2WVPCR + L2WVPCR + Layerx Window Vertical Position + Configuration Register + 0x10C + 0x20 + read-write + 0x00000000 + + + WVSPPOS + Window Vertical Stop + Position + 16 + 11 + + + WVSTPOS + Window Vertical Start + Position + 0 + 11 + + + + + L2CKCR + L2CKCR + Layerx Color Keying Configuration + Register + 0x110 + 0x20 + read-write + 0x00000000 + + + CKRED + Color Key Red value + 16 + 8 + + + CKGREEN + Color Key Green value + 8 + 8 + + + CKBLUE + Color Key Blue value + 0 + 8 + + + + + L2PFCR + L2PFCR + Layerx Pixel Format Configuration + Register + 0x114 + 0x20 + read-write + 0x00000000 + + + PF + Pixel Format + 0 + 3 + + + + + L2CACR + L2CACR + Layerx Constant Alpha Configuration + Register + 0x118 + 0x20 + read-write + 0x00000000 + + + CONSTA + Constant Alpha + 0 + 8 + + + + + L2DCCR + L2DCCR + Layerx Default Color Configuration + Register + 0x11C + 0x20 + read-write + 0x00000000 + + + DCALPHA + Default Color Alpha + 24 + 8 + + + DCRED + Default Color Red + 16 + 8 + + + DCGREEN + Default Color Green + 8 + 8 + + + DCBLUE + Default Color Blue + 0 + 8 + + + + + L2BFCR + L2BFCR + Layerx Blending Factors Configuration + Register + 0x120 + 0x20 + read-write + 0x00000607 + + + BF1 + Blending Factor 1 + 8 + 3 + + + BF2 + Blending Factor 2 + 0 + 3 + + + + + L2CFBAR + L2CFBAR + Layerx Color Frame Buffer Address + Register + 0x12C + 0x20 + read-write + 0x00000000 + + + CFBADD + Color Frame Buffer Start + Address + 0 + 32 + + + + + L2CFBLR + L2CFBLR + Layerx Color Frame Buffer Length + Register + 0x130 + 0x20 + read-write + 0x00000000 + + + CFBP + Color Frame Buffer Pitch in + bytes + 16 + 13 + + + CFBLL + Color Frame Buffer Line + Length + 0 + 13 + + + + + L2CFBLNR + L2CFBLNR + Layerx ColorFrame Buffer Line Number + Register + 0x134 + 0x20 + read-write + 0x00000000 + + + CFBLNBR + Frame Buffer Line Number + 0 + 11 + + + + + L2CLUTWR + L2CLUTWR + Layerx CLUT Write Register + 0x144 + 0x20 + write-only + 0x00000000 + + + CLUTADD + CLUT Address + 24 + 8 + + + RED + Red value + 16 + 8 + + + GREEN + Green value + 8 + 8 + + + BLUE + Blue value + 0 + 8 + + + + + + + SPDIFRX + Receiver Interface + SPDIFRX + 0x40004000 + + 0x0 + 0x400 + registers + + + SPDIF + SPDIFRX global interrupt + 97 + + + + CR + CR + Control register + 0x0 + 0x20 + read-write + 0x00000000 + + + SPDIFRXEN + Peripheral Block Enable + 0 + 2 + + + RXDMAEN + Receiver DMA ENable for data + flow + 2 + 1 + + + RXSTEO + STerEO Mode + 3 + 1 + + + DRFMT + RX Data format + 4 + 2 + + + PMSK + Mask Parity error bit + 6 + 1 + + + VMSK + Mask of Validity bit + 7 + 1 + + + CUMSK + Mask of channel status and user + bits + 8 + 1 + + + PTMSK + Mask of Preamble Type bits + 9 + 1 + + + CBDMAEN + Control Buffer DMA ENable for control + flow + 10 + 1 + + + CHSEL + Channel Selection + 11 + 1 + + + NBTR + Maximum allowed re-tries during + synchronization phase + 12 + 2 + + + WFA + Wait For Activity + 14 + 1 + + + INSEL + input selection + 16 + 3 + + + CKSEN + Symbol Clock Enable + 20 + 1 + + + CKSBKPEN + Backup Symbol Clock Enable + 21 + 1 + + + + + IMR + IMR + Interrupt mask register + 0x4 + 0x20 + read-write + 0x00000000 + + + RXNEIE + RXNE interrupt enable + 0 + 1 + + + CSRNEIE + Control Buffer Ready Interrupt + Enable + 1 + 1 + + + PERRIE + Parity error interrupt + enable + 2 + 1 + + + OVRIE + Overrun error Interrupt + Enable + 3 + 1 + + + SBLKIE + Synchronization Block Detected Interrupt + Enable + 4 + 1 + + + SYNCDIE + Synchronization Done + 5 + 1 + + + IFEIE + Serial Interface Error Interrupt + Enable + 6 + 1 + + + + + SR + SR + Status register + 0x8 + 0x20 + read-only + 0x00000000 + + + RXNE + Read data register not + empty + 0 + 1 + + + CSRNE + Control Buffer register is not + empty + 1 + 1 + + + PERR + Parity error + 2 + 1 + + + OVR + Overrun error + 3 + 1 + + + SBD + Synchronization Block + Detected + 4 + 1 + + + SYNCD + Synchronization Done + 5 + 1 + + + FERR + Framing error + 6 + 1 + + + SERR + Synchronization error + 7 + 1 + + + TERR + Time-out error + 8 + 1 + + + WIDTH5 + Duration of 5 symbols counted with + SPDIF_CLK + 16 + 15 + + + + + IFCR + IFCR + Interrupt Flag Clear register + 0xC + 0x20 + write-only + 0x00000000 + + + PERRCF + Clears the Parity error + flag + 2 + 1 + + + OVRCF + Clears the Overrun error + flag + 3 + 1 + + + SBDCF + Clears the Synchronization Block + Detected flag + 4 + 1 + + + SYNCDCF + Clears the Synchronization Done + flag + 5 + 1 + + + + + DR_00 + DR_00 + Data input register + 0x10 + 0x20 + read-only + 0x00000000 + + + DR + Parity Error bit + 0 + 24 + + + PE + Parity Error bit + 24 + 1 + + + V + Validity bit + 25 + 1 + + + U + User bit + 26 + 1 + + + C + Channel Status bit + 27 + 1 + + + PT + Preamble Type + 28 + 2 + + + + + CSR + CSR + Channel Status register + 0x14 + 0x20 + read-only + 0x00000000 + + + USR + User data information + 0 + 16 + + + CS + Channel A status + information + 16 + 8 + + + SOB + Start Of Block + 24 + 1 + + + + + DIR + DIR + Debug Information register + 0x18 + 0x20 + read-only + 0x00000000 + + + THI + Threshold HIGH + 0 + 13 + + + TLO + Threshold LOW + 16 + 13 + + + + + VERR + VERR + SPDIFRX version register + 0x3F4 + 0x20 + read-only + 0x00000012 + + + MINREV + Minor revision + 0 + 4 + + + MAJREV + Major revision + 4 + 4 + + + + + IDR + IDR + SPDIFRX identification + register + 0x3F8 + 0x20 + read-only + 0x00130041 + + + ID + SPDIFRX identifier + 0 + 32 + + + + + SIDR + SIDR + SPDIFRX size identification + register + 0x3FC + 0x20 + read-only + 0xA3C5DD01 + + + SID + Size identification + 0 + 32 + + + + + DR_01 + DR_01 + Data input register + DR_00 + 0x10 + 0x20 + read-only + 0x00000000 + + + PE + Parity Error bit + 0 + 1 + + + V + Validity bit + 1 + 1 + + + U + User bit + 2 + 1 + + + C + Channel Status bit + 3 + 1 + + + PT + Preamble Type + 4 + 2 + + + DR + Data value + 8 + 24 + + + + + DR_10 + DR_10 + Data input register + DR_00 + 0x10 + 0x20 + read-only + 0x00000000 + + + DRNL1 + Data value + 0 + 16 + + + DRNL2 + Data value + 16 + 16 + + + + + + + ADC3 + Analog to Digital Converter + ADC + 0x58026000 + + 0x0 + 0xD1 + registers + + + ADC3 + ADC3 global interrupt + 127 + + + + ISR + ISR + ADC interrupt and status + register + 0x0 + 0x20 + read-write + 0x00000000 + + + JQOVF + ADC group injected contexts queue + overflow flag + 10 + 1 + + + AWD3 + ADC analog watchdog 3 flag + 9 + 1 + + + AWD2 + ADC analog watchdog 2 flag + 8 + 1 + + + AWD1 + ADC analog watchdog 1 flag + 7 + 1 + + + JEOS + ADC group injected end of sequence + conversions flag + 6 + 1 + + + JEOC + ADC group injected end of unitary + conversion flag + 5 + 1 + + + OVR + ADC group regular overrun + flag + 4 + 1 + + + EOS + ADC group regular end of sequence + conversions flag + 3 + 1 + + + EOC + ADC group regular end of unitary + conversion flag + 2 + 1 + + + EOSMP + ADC group regular end of sampling + flag + 1 + 1 + + + ADRDY + ADC ready flag + 0 + 1 + + + + + IER + IER + ADC interrupt enable register + 0x4 + 0x20 + read-write + 0x00000000 + + + JQOVFIE + ADC group injected contexts queue + overflow interrupt + 10 + 1 + + + AWD3IE + ADC analog watchdog 3 + interrupt + 9 + 1 + + + AWD2IE + ADC analog watchdog 2 + interrupt + 8 + 1 + + + AWD1IE + ADC analog watchdog 1 + interrupt + 7 + 1 + + + JEOSIE + ADC group injected end of sequence + conversions interrupt + 6 + 1 + + + JEOCIE + ADC group injected end of unitary + conversion interrupt + 5 + 1 + + + OVRIE + ADC group regular overrun + interrupt + 4 + 1 + + + EOSIE + ADC group regular end of sequence + conversions interrupt + 3 + 1 + + + EOCIE + ADC group regular end of unitary + conversion interrupt + 2 + 1 + + + EOSMPIE + ADC group regular end of sampling + interrupt + 1 + 1 + + + ADRDYIE + ADC ready interrupt + 0 + 1 + + + + + CR + CR + ADC control register + 0x8 + 0x20 + read-write + 0x00000000 + + + ADCAL + ADC calibration + 31 + 1 + + + ADCALDIF + ADC differential mode for + calibration + 30 + 1 + + + DEEPPWD + ADC deep power down enable + 29 + 1 + + + ADVREGEN + ADC voltage regulator + enable + 28 + 1 + + + LINCALRDYW6 + Linearity calibration ready Word + 6 + 27 + 1 + + + LINCALRDYW5 + Linearity calibration ready Word + 5 + 26 + 1 + + + LINCALRDYW4 + Linearity calibration ready Word + 4 + 25 + 1 + + + LINCALRDYW3 + Linearity calibration ready Word + 3 + 24 + 1 + + + LINCALRDYW2 + Linearity calibration ready Word + 2 + 23 + 1 + + + LINCALRDYW1 + Linearity calibration ready Word + 1 + 22 + 1 + + + ADCALLIN + Linearity calibration + 16 + 1 + + + BOOST + Boost mode control + 8 + 1 + + + JADSTP + ADC group injected conversion + stop + 5 + 1 + + + ADSTP + ADC group regular conversion + stop + 4 + 1 + + + JADSTART + ADC group injected conversion + start + 3 + 1 + + + ADSTART + ADC group regular conversion + start + 2 + 1 + + + ADDIS + ADC disable + 1 + 1 + + + ADEN + ADC enable + 0 + 1 + + + + + CFGR + CFGR + ADC configuration register 1 + 0xC + 0x20 + read-write + 0x00000000 + + + JQDIS + ADC group injected contexts queue + disable + 31 + 1 + + + AWDCH1CH + ADC analog watchdog 1 monitored channel + selection + 26 + 5 + + + JAUTO + ADC group injected automatic trigger + mode + 25 + 1 + + + JAWD1EN + ADC analog watchdog 1 enable on scope + ADC group injected + 24 + 1 + + + AWD1EN + ADC analog watchdog 1 enable on scope + ADC group regular + 23 + 1 + + + AWD1SGL + ADC analog watchdog 1 monitoring a + single channel or all channels + 22 + 1 + + + JQM + ADC group injected contexts queue + mode + 21 + 1 + + + JDISCEN + ADC group injected sequencer + discontinuous mode + 20 + 1 + + + DISCNUM + ADC group regular sequencer + discontinuous number of ranks + 17 + 3 + + + DISCEN + ADC group regular sequencer + discontinuous mode + 16 + 1 + + + AUTDLY + ADC low power auto wait + 14 + 1 + + + CONT + ADC group regular continuous conversion + mode + 13 + 1 + + + OVRMOD + ADC group regular overrun + configuration + 12 + 1 + + + EXTEN + ADC group regular external trigger + polarity + 10 + 2 + + + EXTSEL + ADC group regular external trigger + source + 5 + 5 + + + RES + ADC data resolution + 2 + 3 + + + DMNGT + ADC DMA transfer enable + 0 + 2 + + + + + CFGR2 + CFGR2 + ADC configuration register 2 + 0x10 + 0x20 + read-write + 0x00000000 + + + ROVSE + ADC oversampler enable on scope ADC + group regular + 0 + 1 + + + JOVSE + ADC oversampler enable on scope ADC + group injected + 1 + 1 + + + OVSS + ADC oversampling shift + 5 + 4 + + + TROVS + ADC oversampling discontinuous mode + (triggered mode) for ADC group regular + 9 + 1 + + + ROVSM + Regular Oversampling mode + 10 + 1 + + + RSHIFT1 + Right-shift data after Offset 1 + correction + 11 + 1 + + + RSHIFT2 + Right-shift data after Offset 2 + correction + 12 + 1 + + + RSHIFT3 + Right-shift data after Offset 3 + correction + 13 + 1 + + + RSHIFT4 + Right-shift data after Offset 4 + correction + 14 + 1 + + + OSR + Oversampling ratio + 16 + 10 + + + LSHIFT + Left shift factor + 28 + 4 + + + + + SMPR1 + SMPR1 + ADC sampling time register 1 + 0x14 + 0x20 + read-write + 0x00000000 + + + SMP9 + ADC channel 9 sampling time + selection + 27 + 3 + + + SMP8 + ADC channel 8 sampling time + selection + 24 + 3 + + + SMP7 + ADC channel 7 sampling time + selection + 21 + 3 + + + SMP6 + ADC channel 6 sampling time + selection + 18 + 3 + + + SMP5 + ADC channel 5 sampling time + selection + 15 + 3 + + + SMP4 + ADC channel 4 sampling time + selection + 12 + 3 + + + SMP3 + ADC channel 3 sampling time + selection + 9 + 3 + + + SMP2 + ADC channel 2 sampling time + selection + 6 + 3 + + + SMP1 + ADC channel 1 sampling time + selection + 3 + 3 + + + + + SMPR2 + SMPR2 + ADC sampling time register 2 + 0x18 + 0x20 + read-write + 0x00000000 + + + SMP19 + ADC channel 18 sampling time + selection + 27 + 3 + + + SMP18 + ADC channel 18 sampling time + selection + 24 + 3 + + + SMP17 + ADC channel 17 sampling time + selection + 21 + 3 + + + SMP16 + ADC channel 16 sampling time + selection + 18 + 3 + + + SMP15 + ADC channel 15 sampling time + selection + 15 + 3 + + + SMP14 + ADC channel 14 sampling time + selection + 12 + 3 + + + SMP13 + ADC channel 13 sampling time + selection + 9 + 3 + + + SMP12 + ADC channel 12 sampling time + selection + 6 + 3 + + + SMP11 + ADC channel 11 sampling time + selection + 3 + 3 + + + SMP10 + ADC channel 10 sampling time + selection + 0 + 3 + + + + + LTR1 + LTR1 + ADC analog watchdog 1 threshold + register + 0x20 + 0x20 + read-write + 0x0FFF0000 + + + LTR1 + ADC analog watchdog 1 threshold + low + 0 + 26 + + + + + LHTR1 + LHTR1 + ADC analog watchdog 2 threshold + register + 0x24 + 0x20 + read-write + 0x0FFF0000 + + + LHTR1 + ADC analog watchdog 2 threshold + low + 0 + 26 + + + + + SQR1 + SQR1 + ADC group regular sequencer ranks register + 1 + 0x30 + 0x20 + read-write + 0x00000000 + + + SQ4 + ADC group regular sequencer rank + 4 + 24 + 5 + + + SQ3 + ADC group regular sequencer rank + 3 + 18 + 5 + + + SQ2 + ADC group regular sequencer rank + 2 + 12 + 5 + + + SQ1 + ADC group regular sequencer rank + 1 + 6 + 5 + + + L3 + L3 + 0 + 4 + + + + + SQR2 + SQR2 + ADC group regular sequencer ranks register + 2 + 0x34 + 0x20 + read-write + 0x00000000 + + + SQ9 + ADC group regular sequencer rank + 9 + 24 + 5 + + + SQ8 + ADC group regular sequencer rank + 8 + 18 + 5 + + + SQ7 + ADC group regular sequencer rank + 7 + 12 + 5 + + + SQ6 + ADC group regular sequencer rank + 6 + 6 + 5 + + + SQ5 + ADC group regular sequencer rank + 5 + 0 + 5 + + + + + SQR3 + SQR3 + ADC group regular sequencer ranks register + 3 + 0x38 + 0x20 + read-write + 0x00000000 + + + SQ14 + ADC group regular sequencer rank + 14 + 24 + 5 + + + SQ13 + ADC group regular sequencer rank + 13 + 18 + 5 + + + SQ12 + ADC group regular sequencer rank + 12 + 12 + 5 + + + SQ11 + ADC group regular sequencer rank + 11 + 6 + 5 + + + SQ10 + ADC group regular sequencer rank + 10 + 0 + 5 + + + + + SQR4 + SQR4 + ADC group regular sequencer ranks register + 4 + 0x3C + 0x20 + read-write + 0x00000000 + + + SQ16 + ADC group regular sequencer rank + 16 + 6 + 5 + + + SQ15 + ADC group regular sequencer rank + 15 + 0 + 5 + + + + + DR + DR + ADC group regular conversion data + register + 0x40 + 0x20 + read-only + 0x00000000 + + + RDATA + ADC group regular conversion + data + 0 + 16 + + + + + JSQR + JSQR + ADC group injected sequencer + register + 0x4C + 0x20 + read-write + 0x00000000 + + + JSQ4 + ADC group injected sequencer rank + 4 + 27 + 5 + + + JSQ3 + ADC group injected sequencer rank + 3 + 21 + 5 + + + JSQ2 + ADC group injected sequencer rank + 2 + 15 + 5 + + + JSQ1 + ADC group injected sequencer rank + 1 + 9 + 5 + + + JEXTEN + ADC group injected external trigger + polarity + 7 + 2 + + + JEXTSEL + ADC group injected external trigger + source + 2 + 5 + + + JL + ADC group injected sequencer scan + length + 0 + 2 + + + + + OFR1 + OFR1 + ADC offset number 1 register + 0x60 + 0x20 + read-write + 0x00000000 + + + SSATE + ADC offset number 1 enable + 31 + 1 + + + OFFSET1_CH + ADC offset number 1 channel + selection + 26 + 5 + + + OFFSET1 + ADC offset number 1 offset + level + 0 + 26 + + + + + OFR2 + OFR2 + ADC offset number 2 register + 0x64 + 0x20 + read-write + 0x00000000 + + + SSATE + ADC offset number 1 enable + 31 + 1 + + + OFFSET1_CH + ADC offset number 1 channel + selection + 26 + 5 + + + OFFSET1 + ADC offset number 1 offset + level + 0 + 26 + + + + + OFR3 + OFR3 + ADC offset number 3 register + 0x68 + 0x20 + read-write + 0x00000000 + + + SSATE + ADC offset number 1 enable + 31 + 1 + + + OFFSET1_CH + ADC offset number 1 channel + selection + 26 + 5 + + + OFFSET1 + ADC offset number 1 offset + level + 0 + 26 + + + + + OFR4 + OFR4 + ADC offset number 4 register + 0x6C + 0x20 + read-write + 0x00000000 + + + SSATE + ADC offset number 1 enable + 31 + 1 + + + OFFSET1_CH + ADC offset number 1 channel + selection + 26 + 5 + + + OFFSET1 + ADC offset number 1 offset + level + 0 + 26 + + + + + JDR1 + JDR1 + ADC group injected sequencer rank 1 + register + 0x80 + 0x20 + read-only + 0x00000000 + + + JDATA1 + ADC group injected sequencer rank 1 + conversion data + 0 + 32 + + + + + JDR2 + JDR2 + ADC group injected sequencer rank 2 + register + 0x84 + 0x20 + read-only + 0x00000000 + + + JDATA2 + ADC group injected sequencer rank 2 + conversion data + 0 + 32 + + + + + JDR3 + JDR3 + ADC group injected sequencer rank 3 + register + 0x88 + 0x20 + read-only + 0x00000000 + + + JDATA3 + ADC group injected sequencer rank 3 + conversion data + 0 + 32 + + + + + JDR4 + JDR4 + ADC group injected sequencer rank 4 + register + 0x8C + 0x20 + read-only + 0x00000000 + + + JDATA4 + ADC group injected sequencer rank 4 + conversion data + 0 + 32 + + + + + AWD2CR + AWD2CR + ADC analog watchdog 2 configuration + register + 0xA0 + 0x20 + read-write + 0x00000000 + + + AWD2CH + ADC analog watchdog 2 monitored channel + selection + 0 + 20 + + + + + AWD3CR + AWD3CR + ADC analog watchdog 3 configuration + register + 0xA4 + 0x20 + read-write + 0x00000000 + + + AWD3CH + ADC analog watchdog 3 monitored channel + selection + 1 + 20 + + + + + DIFSEL + DIFSEL + ADC channel differential or single-ended + mode selection register + 0xC0 + 0x20 + read-write + 0x00000000 + + + DIFSEL + ADC channel differential or single-ended + mode for channel + 0 + 20 + + + + + CALFACT + CALFACT + ADC calibration factors + register + 0xC4 + 0x20 + read-write + 0x00000000 + + + CALFACT_D + ADC calibration factor in differential + mode + 16 + 11 + + + CALFACT_S + ADC calibration factor in single-ended + mode + 0 + 11 + + + + + PCSEL + PCSEL + ADC pre channel selection + register + 0x1C + 0x20 + read-write + 0x00000000 + + + PCSEL + Channel x (VINP[i]) pre + selection + 0 + 20 + + + + + LTR2 + LTR2 + ADC watchdog lower threshold register + 2 + 0xB0 + 0x20 + read-write + 0x00000000 + + + LTR2 + Analog watchdog 2 lower + threshold + 0 + 26 + + + + + HTR2 + HTR2 + ADC watchdog higher threshold register + 2 + 0xB4 + 0x20 + read-write + 0x00000000 + + + HTR2 + Analog watchdog 2 higher + threshold + 0 + 26 + + + + + LTR3 + LTR3 + ADC watchdog lower threshold register + 3 + 0xB8 + 0x20 + read-write + 0x00000000 + + + LTR3 + Analog watchdog 3 lower + threshold + 0 + 26 + + + + + HTR3 + HTR3 + ADC watchdog higher threshold register + 3 + 0xBC + 0x20 + read-write + 0x00000000 + + + HTR3 + Analog watchdog 3 higher + threshold + 0 + 26 + + + + + CALFACT2 + CALFACT2 + ADC Calibration Factor register + 2 + 0xC8 + 0x20 + read-write + 0x00000000 + + + LINCALFACT + Linearity Calibration + Factor + 0 + 30 + + + + + + + ADC1 + 0x40022000 + + + ADC2 + 0x40022100 + + + ADC3_Common + Analog-to-Digital Converter + ADC + 0x58026300 + + 0x0 + 0x100 + registers + + + + CSR + CSR + ADC Common status register + 0x0 + 0x20 + read-only + 0x00000000 + + + ADRDY_MST + Master ADC ready + 0 + 1 + + + EOSMP_MST + End of Sampling phase flag of the master + ADC + 1 + 1 + + + EOC_MST + End of regular conversion of the master + ADC + 2 + 1 + + + EOS_MST + End of regular sequence flag of the + master ADC + 3 + 1 + + + OVR_MST + Overrun flag of the master + ADC + 4 + 1 + + + JEOC_MST + End of injected conversion flag of the + master ADC + 5 + 1 + + + JEOS_MST + End of injected sequence flag of the + master ADC + 6 + 1 + + + AWD1_MST + Analog watchdog 1 flag of the master + ADC + 7 + 1 + + + AWD2_MST + Analog watchdog 2 flag of the master + ADC + 8 + 1 + + + AWD3_MST + Analog watchdog 3 flag of the master + ADC + 9 + 1 + + + JQOVF_MST + Injected Context Queue Overflow flag of + the master ADC + 10 + 1 + + + ADRDY_SLV + Slave ADC ready + 16 + 1 + + + EOSMP_SLV + End of Sampling phase flag of the slave + ADC + 17 + 1 + + + EOC_SLV + End of regular conversion of the slave + ADC + 18 + 1 + + + EOS_SLV + End of regular sequence flag of the + slave ADC + 19 + 1 + + + OVR_SLV + Overrun flag of the slave + ADC + 20 + 1 + + + JEOC_SLV + End of injected conversion flag of the + slave ADC + 21 + 1 + + + JEOS_SLV + End of injected sequence flag of the + slave ADC + 22 + 1 + + + AWD1_SLV + Analog watchdog 1 flag of the slave + ADC + 23 + 1 + + + AWD2_SLV + Analog watchdog 2 flag of the slave + ADC + 24 + 1 + + + AWD3_SLV + Analog watchdog 3 flag of the slave + ADC + 25 + 1 + + + JQOVF_SLV + Injected Context Queue Overflow flag of + the slave ADC + 26 + 1 + + + + + CCR + CCR + ADC common control register + 0x8 + 0x20 + read-write + 0x00000000 + + + DUAL + Dual ADC mode selection + 0 + 5 + + + DELAY + Delay between 2 sampling + phases + 8 + 4 + + + DAMDF + Dual ADC Mode Data Format + 14 + 2 + + + CKMODE + ADC clock mode + 16 + 2 + + + PRESC + ADC prescaler + 18 + 4 + + + VREFEN + VREFINT enable + 22 + 1 + + + VSENSEEN + Temperature sensor enable + 23 + 1 + + + VBATEN + VBAT enable + 24 + 1 + + + + + CDR + CDR + ADC common regular data register for dual + and triple modes + 0xC + 0x20 + read-only + 0x00000000 + + + RDATA_SLV + Regular data of the slave + ADC + 16 + 16 + + + RDATA_MST + Regular data of the master + ADC + 0 + 16 + + + + + CDR2 + CDR2 + ADC x common regular data register for + 32-bit dual mode + 0x10 + 0x20 + read-only + 0x00000000 + + + RDATA_ALT + Regular data of the master/slave + alternated ADCs + 0 + 32 + + + + + + + ADC12_Common + 0x40022300 + + ADC1_2 + ADC1 and ADC2 + 18 + + + + DMAMUX1 + DMAMUX + DMAMUX + 0x40020800 + + 0x0 + 0x400 + registers + + + DMAMUX1_OV + DMAMUX1 overrun interrupt + 102 + + + + C0CR + C0CR + DMAMux - DMA request line multiplexer + channel x control register + 0x0 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line + selected + 0 + 8 + + + SOIE + Interrupt enable at synchronization + event overrun + 8 + 1 + + + EGE + Event generation + enable/disable + 9 + 1 + + + SE + Synchronous operating mode + enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector + Defines the synchronization event on the selected + synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward + Defines the number of DMA requests forwarded before + output event is generated. In synchronous mode, it + also defines the number of DMA requests to forward + after a synchronization event, then stop forwarding. + The actual number of DMA requests forwarded is + NBREQ+1. Note: This field can only be written when + both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input + selected + 24 + 5 + + + + + C1CR + C1CR + DMAMux - DMA request line multiplexer + channel x control register + 0x4 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line + selected + 0 + 8 + + + SOIE + Interrupt enable at synchronization + event overrun + 8 + 1 + + + EGE + Event generation + enable/disable + 9 + 1 + + + SE + Synchronous operating mode + enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector + Defines the synchronization event on the selected + synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward + Defines the number of DMA requests forwarded before + output event is generated. In synchronous mode, it + also defines the number of DMA requests to forward + after a synchronization event, then stop forwarding. + The actual number of DMA requests forwarded is + NBREQ+1. Note: This field can only be written when + both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input + selected + 24 + 5 + + + + + C2CR + C2CR + DMAMux - DMA request line multiplexer + channel x control register + 0x8 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line + selected + 0 + 8 + + + SOIE + Interrupt enable at synchronization + event overrun + 8 + 1 + + + EGE + Event generation + enable/disable + 9 + 1 + + + SE + Synchronous operating mode + enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector + Defines the synchronization event on the selected + synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward + Defines the number of DMA requests forwarded before + output event is generated. In synchronous mode, it + also defines the number of DMA requests to forward + after a synchronization event, then stop forwarding. + The actual number of DMA requests forwarded is + NBREQ+1. Note: This field can only be written when + both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input + selected + 24 + 5 + + + + + C3CR + C3CR + DMAMux - DMA request line multiplexer + channel x control register + 0xC + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line + selected + 0 + 8 + + + SOIE + Interrupt enable at synchronization + event overrun + 8 + 1 + + + EGE + Event generation + enable/disable + 9 + 1 + + + SE + Synchronous operating mode + enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector + Defines the synchronization event on the selected + synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward + Defines the number of DMA requests forwarded before + output event is generated. In synchronous mode, it + also defines the number of DMA requests to forward + after a synchronization event, then stop forwarding. + The actual number of DMA requests forwarded is + NBREQ+1. Note: This field can only be written when + both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input + selected + 24 + 5 + + + + + C4CR + C4CR + DMAMux - DMA request line multiplexer + channel x control register + 0x10 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line + selected + 0 + 8 + + + SOIE + Interrupt enable at synchronization + event overrun + 8 + 1 + + + EGE + Event generation + enable/disable + 9 + 1 + + + SE + Synchronous operating mode + enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector + Defines the synchronization event on the selected + synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward + Defines the number of DMA requests forwarded before + output event is generated. In synchronous mode, it + also defines the number of DMA requests to forward + after a synchronization event, then stop forwarding. + The actual number of DMA requests forwarded is + NBREQ+1. Note: This field can only be written when + both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input + selected + 24 + 5 + + + + + C5CR + C5CR + DMAMux - DMA request line multiplexer + channel x control register + 0x14 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line + selected + 0 + 8 + + + SOIE + Interrupt enable at synchronization + event overrun + 8 + 1 + + + EGE + Event generation + enable/disable + 9 + 1 + + + SE + Synchronous operating mode + enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector + Defines the synchronization event on the selected + synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward + Defines the number of DMA requests forwarded before + output event is generated. In synchronous mode, it + also defines the number of DMA requests to forward + after a synchronization event, then stop forwarding. + The actual number of DMA requests forwarded is + NBREQ+1. Note: This field can only be written when + both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input + selected + 24 + 5 + + + + + C6CR + C6CR + DMAMux - DMA request line multiplexer + channel x control register + 0x18 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line + selected + 0 + 8 + + + SOIE + Interrupt enable at synchronization + event overrun + 8 + 1 + + + EGE + Event generation + enable/disable + 9 + 1 + + + SE + Synchronous operating mode + enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector + Defines the synchronization event on the selected + synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward + Defines the number of DMA requests forwarded before + output event is generated. In synchronous mode, it + also defines the number of DMA requests to forward + after a synchronization event, then stop forwarding. + The actual number of DMA requests forwarded is + NBREQ+1. Note: This field can only be written when + both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input + selected + 24 + 5 + + + + + C7CR + C7CR + DMAMux - DMA request line multiplexer + channel x control register + 0x1C + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line + selected + 0 + 8 + + + SOIE + Interrupt enable at synchronization + event overrun + 8 + 1 + + + EGE + Event generation + enable/disable + 9 + 1 + + + SE + Synchronous operating mode + enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector + Defines the synchronization event on the selected + synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward + Defines the number of DMA requests forwarded before + output event is generated. In synchronous mode, it + also defines the number of DMA requests to forward + after a synchronization event, then stop forwarding. + The actual number of DMA requests forwarded is + NBREQ+1. Note: This field can only be written when + both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input + selected + 24 + 5 + + + + + C8CR + C8CR + DMAMux - DMA request line multiplexer + channel x control register + 0x20 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line + selected + 0 + 8 + + + SOIE + Interrupt enable at synchronization + event overrun + 8 + 1 + + + EGE + Event generation + enable/disable + 9 + 1 + + + SE + Synchronous operating mode + enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector + Defines the synchronization event on the selected + synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward + Defines the number of DMA requests forwarded before + output event is generated. In synchronous mode, it + also defines the number of DMA requests to forward + after a synchronization event, then stop forwarding. + The actual number of DMA requests forwarded is + NBREQ+1. Note: This field can only be written when + both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input + selected + 24 + 5 + + + + + C9CR + C9CR + DMAMux - DMA request line multiplexer + channel x control register + 0x24 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line + selected + 0 + 8 + + + SOIE + Interrupt enable at synchronization + event overrun + 8 + 1 + + + EGE + Event generation + enable/disable + 9 + 1 + + + SE + Synchronous operating mode + enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector + Defines the synchronization event on the selected + synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward + Defines the number of DMA requests forwarded before + output event is generated. In synchronous mode, it + also defines the number of DMA requests to forward + after a synchronization event, then stop forwarding. + The actual number of DMA requests forwarded is + NBREQ+1. Note: This field can only be written when + both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input + selected + 24 + 5 + + + + + C10CR + C10CR + DMAMux - DMA request line multiplexer + channel x control register + 0x28 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line + selected + 0 + 8 + + + SOIE + Interrupt enable at synchronization + event overrun + 8 + 1 + + + EGE + Event generation + enable/disable + 9 + 1 + + + SE + Synchronous operating mode + enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector + Defines the synchronization event on the selected + synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward + Defines the number of DMA requests forwarded before + output event is generated. In synchronous mode, it + also defines the number of DMA requests to forward + after a synchronization event, then stop forwarding. + The actual number of DMA requests forwarded is + NBREQ+1. Note: This field can only be written when + both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input + selected + 24 + 5 + + + + + C11CR + C11CR + DMAMux - DMA request line multiplexer + channel x control register + 0x2C + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line + selected + 0 + 8 + + + SOIE + Interrupt enable at synchronization + event overrun + 8 + 1 + + + EGE + Event generation + enable/disable + 9 + 1 + + + SE + Synchronous operating mode + enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector + Defines the synchronization event on the selected + synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward + Defines the number of DMA requests forwarded before + output event is generated. In synchronous mode, it + also defines the number of DMA requests to forward + after a synchronization event, then stop forwarding. + The actual number of DMA requests forwarded is + NBREQ+1. Note: This field can only be written when + both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input + selected + 24 + 5 + + + + + C12CR + C12CR + DMAMux - DMA request line multiplexer + channel x control register + 0x30 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line + selected + 0 + 8 + + + SOIE + Interrupt enable at synchronization + event overrun + 8 + 1 + + + EGE + Event generation + enable/disable + 9 + 1 + + + SE + Synchronous operating mode + enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector + Defines the synchronization event on the selected + synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward + Defines the number of DMA requests forwarded before + output event is generated. In synchronous mode, it + also defines the number of DMA requests to forward + after a synchronization event, then stop forwarding. + The actual number of DMA requests forwarded is + NBREQ+1. Note: This field can only be written when + both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input + selected + 24 + 5 + + + + + C13CR + C13CR + DMAMux - DMA request line multiplexer + channel x control register + 0x34 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line + selected + 0 + 8 + + + SOIE + Interrupt enable at synchronization + event overrun + 8 + 1 + + + EGE + Event generation + enable/disable + 9 + 1 + + + SE + Synchronous operating mode + enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector + Defines the synchronization event on the selected + synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward + Defines the number of DMA requests forwarded before + output event is generated. In synchronous mode, it + also defines the number of DMA requests to forward + after a synchronization event, then stop forwarding. + The actual number of DMA requests forwarded is + NBREQ+1. Note: This field can only be written when + both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input + selected + 24 + 5 + + + + + C14CR + C14CR + DMAMux - DMA request line multiplexer + channel x control register + 0x38 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line + selected + 0 + 8 + + + SOIE + Interrupt enable at synchronization + event overrun + 8 + 1 + + + EGE + Event generation + enable/disable + 9 + 1 + + + SE + Synchronous operating mode + enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector + Defines the synchronization event on the selected + synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward + Defines the number of DMA requests forwarded before + output event is generated. In synchronous mode, it + also defines the number of DMA requests to forward + after a synchronization event, then stop forwarding. + The actual number of DMA requests forwarded is + NBREQ+1. Note: This field can only be written when + both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input + selected + 24 + 5 + + + + + C15CR + C15CR + DMAMux - DMA request line multiplexer + channel x control register + 0x3C + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line + selected + 0 + 8 + + + SOIE + Interrupt enable at synchronization + event overrun + 8 + 1 + + + EGE + Event generation + enable/disable + 9 + 1 + + + SE + Synchronous operating mode + enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector + Defines the synchronization event on the selected + synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward + Defines the number of DMA requests forwarded before + output event is generated. In synchronous mode, it + also defines the number of DMA requests to forward + after a synchronization event, then stop forwarding. + The actual number of DMA requests forwarded is + NBREQ+1. Note: This field can only be written when + both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input + selected + 24 + 5 + + + + + RG0CR + RG0CR + DMAMux - DMA request generator channel x + control register + 0x100 + 0x20 + read-write + 0x00000000 + + + SIG_ID + DMA request trigger input + selected + 0 + 5 + + + OIE + Interrupt enable at trigger event + overrun + 8 + 1 + + + GE + DMA request generator channel + enable/disable + 16 + 1 + + + GPOL + DMA request generator trigger event type + selection Defines the trigger event on the selected + DMA request trigger input + 17 + 2 + + + GNBREQ + Number of DMA requests to generate + Defines the number of DMA requests generated after a + trigger event, then stop generating. The actual + number of generated DMA requests is GNBREQ+1. Note: + This field can only be written when GE bit is + reset. + 19 + 5 + + + + + RG1CR + RG1CR + DMAMux - DMA request generator channel x + control register + 0x104 + 0x20 + read-write + 0x00000000 + + + SIG_ID + DMA request trigger input + selected + 0 + 5 + + + OIE + Interrupt enable at trigger event + overrun + 8 + 1 + + + GE + DMA request generator channel + enable/disable + 16 + 1 + + + GPOL + DMA request generator trigger event type + selection Defines the trigger event on the selected + DMA request trigger input + 17 + 2 + + + GNBREQ + Number of DMA requests to generate + Defines the number of DMA requests generated after a + trigger event, then stop generating. The actual + number of generated DMA requests is GNBREQ+1. Note: + This field can only be written when GE bit is + reset. + 19 + 5 + + + + + RG2CR + RG2CR + DMAMux - DMA request generator channel x + control register + 0x108 + 0x20 + read-write + 0x00000000 + + + SIG_ID + DMA request trigger input + selected + 0 + 5 + + + OIE + Interrupt enable at trigger event + overrun + 8 + 1 + + + GE + DMA request generator channel + enable/disable + 16 + 1 + + + GPOL + DMA request generator trigger event type + selection Defines the trigger event on the selected + DMA request trigger input + 17 + 2 + + + GNBREQ + Number of DMA requests to generate + Defines the number of DMA requests generated after a + trigger event, then stop generating. The actual + number of generated DMA requests is GNBREQ+1. Note: + This field can only be written when GE bit is + reset. + 19 + 5 + + + + + RG3CR + RG3CR + DMAMux - DMA request generator channel x + control register + 0x10C + 0x20 + read-write + 0x00000000 + + + SIG_ID + DMA request trigger input + selected + 0 + 5 + + + OIE + Interrupt enable at trigger event + overrun + 8 + 1 + + + GE + DMA request generator channel + enable/disable + 16 + 1 + + + GPOL + DMA request generator trigger event type + selection Defines the trigger event on the selected + DMA request trigger input + 17 + 2 + + + GNBREQ + Number of DMA requests to generate + Defines the number of DMA requests generated after a + trigger event, then stop generating. The actual + number of generated DMA requests is GNBREQ+1. Note: + This field can only be written when GE bit is + reset. + 19 + 5 + + + + + RG4CR + RG4CR + DMAMux - DMA request generator channel x + control register + 0x110 + 0x20 + read-write + 0x00000000 + + + SIG_ID + DMA request trigger input + selected + 0 + 5 + + + OIE + Interrupt enable at trigger event + overrun + 8 + 1 + + + GE + DMA request generator channel + enable/disable + 16 + 1 + + + GPOL + DMA request generator trigger event type + selection Defines the trigger event on the selected + DMA request trigger input + 17 + 2 + + + GNBREQ + Number of DMA requests to generate + Defines the number of DMA requests generated after a + trigger event, then stop generating. The actual + number of generated DMA requests is GNBREQ+1. Note: + This field can only be written when GE bit is + reset. + 19 + 5 + + + + + RG5CR + RG5CR + DMAMux - DMA request generator channel x + control register + 0x114 + 0x20 + read-write + 0x00000000 + + + SIG_ID + DMA request trigger input + selected + 0 + 5 + + + OIE + Interrupt enable at trigger event + overrun + 8 + 1 + + + GE + DMA request generator channel + enable/disable + 16 + 1 + + + GPOL + DMA request generator trigger event type + selection Defines the trigger event on the selected + DMA request trigger input + 17 + 2 + + + GNBREQ + Number of DMA requests to generate + Defines the number of DMA requests generated after a + trigger event, then stop generating. The actual + number of generated DMA requests is GNBREQ+1. Note: + This field can only be written when GE bit is + reset. + 19 + 5 + + + + + RG6CR + RG6CR + DMAMux - DMA request generator channel x + control register + 0x118 + 0x20 + read-write + 0x00000000 + + + SIG_ID + DMA request trigger input + selected + 0 + 5 + + + OIE + Interrupt enable at trigger event + overrun + 8 + 1 + + + GE + DMA request generator channel + enable/disable + 16 + 1 + + + GPOL + DMA request generator trigger event type + selection Defines the trigger event on the selected + DMA request trigger input + 17 + 2 + + + GNBREQ + Number of DMA requests to generate + Defines the number of DMA requests generated after a + trigger event, then stop generating. The actual + number of generated DMA requests is GNBREQ+1. Note: + This field can only be written when GE bit is + reset. + 19 + 5 + + + + + RG7CR + RG7CR + DMAMux - DMA request generator channel x + control register + 0x11C + 0x20 + read-write + 0x00000000 + + + SIG_ID + DMA request trigger input + selected + 0 + 5 + + + OIE + Interrupt enable at trigger event + overrun + 8 + 1 + + + GE + DMA request generator channel + enable/disable + 16 + 1 + + + GPOL + DMA request generator trigger event type + selection Defines the trigger event on the selected + DMA request trigger input + 17 + 2 + + + GNBREQ + Number of DMA requests to generate + Defines the number of DMA requests generated after a + trigger event, then stop generating. The actual + number of generated DMA requests is GNBREQ+1. Note: + This field can only be written when GE bit is + reset. + 19 + 5 + + + + + RGSR + RGSR + DMAMux - DMA request generator status + register + 0x140 + 0x20 + read-only + 0x00000000 + + + OF + Trigger event overrun flag The flag is + set when a trigger event occurs on DMA request + generator channel x, while the DMA request generator + counter value is lower than GNBREQ. The flag is + cleared by writing 1 to the corresponding COFx bit in + DMAMUX_RGCFR register. + 0 + 8 + + + + + RGCFR + RGCFR + DMAMux - DMA request generator clear flag + register + 0x144 + 0x20 + write-only + 0x00000000 + + + COF + Clear trigger event overrun flag Upon + setting, this bit clears the corresponding overrun + flag OFx in the DMAMUX_RGCSR register. + 0 + 8 + + + + + CSR + CSR + DMAMUX request line multiplexer interrupt + channel status register + 0x80 + 0x20 + read-only + 0x00000000 + + + SOF + Synchronization overrun event + flag + 0 + 16 + + + + + CFR + CFR + DMAMUX request line multiplexer interrupt + clear flag register + 0x84 + 0x20 + write-only + 0x00000000 + + + CSOF + Clear synchronization overrun event + flag + 0 + 16 + + + + + + + CRC + Cryptographic processor + CRC + 0x58024C00 + + 0x0 + 0x400 + registers + + + + DR + DR + Data register + 0x0 + 0x20 + read-write + 0xFFFFFFFF + + + DR + Data Register + 0 + 32 + + + + + IDR + IDR + Independent Data register + 0x4 + 0x20 + read-write + 0x00000000 + + + IDR + Independent Data register + 0 + 32 + + + + + CR + CR + Control register + 0x8 + 0x20 + 0x00000000 + + + RESET + RESET bit + 0 + 1 + write-only + + + POLYSIZE + Polynomial size + 3 + 2 + read-write + + + REV_IN + Reverse input data + 5 + 2 + read-write + + + REV_OUT + Reverse output data + 7 + 1 + read-write + + + + + INIT + INIT + Initial CRC value + 0xC + 0x20 + read-write + 0x00000000 + + + CRC_INIT + Programmable initial CRC + value + 0 + 32 + + + + + POL + POL + CRC polynomial + 0x10 + 0x20 + read-write + 0x00000000 + + + POL + Programmable polynomial + 0 + 32 + + + + + + + RCC + Reset and clock control + RCC + 0x58024400 + + 0x0 + 0x400 + registers + + + RCC + RCC global interrupt + 5 + + + + CR + CR + clock control register + 0x0 + 0x20 + read-write + 0x00000083 + + + HSION + Internal high-speed clock + enable + 0 + 1 + + + HSIKERON + High Speed Internal clock enable in Stop + mode + 1 + 1 + + + HSIRDY + HSI clock ready flag + 2 + 1 + + + HSIDIV + HSI clock divider + 3 + 2 + + + HSIDIVF + HSI divider flag + 5 + 1 + + + CSION + CSI clock enable + 7 + 1 + + + CSIRDY + CSI clock ready flag + 8 + 1 + + + CSIKERON + CSI clock enable in Stop + mode + 9 + 1 + + + RC48ON + RC48 clock enable + 12 + 1 + + + RC48RDY + RC48 clock ready flag + 13 + 1 + + + D1CKRDY + D1 domain clocks ready + flag + 14 + 1 + + + D2CKRDY + D2 domain clocks ready + flag + 15 + 1 + + + HSEON + HSE clock enable + 16 + 1 + + + HSERDY + HSE clock ready flag + 17 + 1 + + + HSEBYP + HSE clock bypass + 18 + 1 + + + HSECSSON + HSE Clock Security System + enable + 19 + 1 + + + PLL1ON + PLL1 enable + 24 + 1 + + + PLL1RDY + PLL1 clock ready flag + 25 + 1 + + + PLL2ON + PLL2 enable + 26 + 1 + + + PLL2RDY + PLL2 clock ready flag + 27 + 1 + + + PLL3ON + PLL3 enable + 28 + 1 + + + PLL3RDY + PLL3 clock ready flag + 29 + 1 + + + + + ICSCR + ICSCR + RCC Internal Clock Source Calibration + Register + 0x4 + 0x20 + 0x40000000 + + + HSICAL + HSI clock calibration + 0 + 12 + read-only + + + HSITRIM + HSI clock trimming + 12 + 6 + read-write + + + CSICAL + CSI clock calibration + 18 + 8 + read-only + + + CSITRIM + CSI clock trimming + 26 + 5 + read-write + + + + + CRRCR + CRRCR + RCC Clock Recovery RC Register + 0x8 + 0x20 + read-only + 0x00000000 + + + RC48CAL + Internal RC 48 MHz clock + calibration + 0 + 10 + + + + + CFGR + CFGR + RCC Clock Configuration + Register + 0x10 + 0x20 + read-write + 0x00000000 + + + SW + System clock switch + 0 + 3 + + + SWS + System clock switch status + 3 + 3 + + + STOPWUCK + System clock selection after a wake up + from system Stop + 6 + 1 + + + STOPKERWUCK + Kernel clock selection after a wake up + from system Stop + 7 + 1 + + + RTCPRE + HSE division factor for RTC + clock + 8 + 6 + + + HRTIMSEL + High Resolution Timer clock prescaler + selection + 14 + 1 + + + TIMPRE + Timers clocks prescaler + selection + 15 + 1 + + + MCO1PRE + MCO1 prescaler + 18 + 4 + + + MCO1SEL + Micro-controller clock output + 1 + 22 + 3 + + + MCO2PRE + MCO2 prescaler + 25 + 4 + + + MCO2SEL + Micro-controller clock output + 2 + 29 + 3 + + + + + D1CFGR + D1CFGR + RCC Domain 1 Clock Configuration + Register + 0x18 + 0x20 + read-write + 0x00000000 + + + HPRE + D1 domain AHB prescaler + 0 + 4 + + + D1PPRE + D1 domain APB3 prescaler + 4 + 3 + + + D1CPRE + D1 domain Core prescaler + 8 + 4 + + + + + D2CFGR + D2CFGR + RCC Domain 2 Clock Configuration + Register + 0x1C + 0x20 + read-write + 0x00000000 + + + D2PPRE1 + D2 domain APB1 prescaler + 4 + 3 + + + D2PPRE2 + D2 domain APB2 prescaler + 8 + 3 + + + + + D3CFGR + D3CFGR + RCC Domain 3 Clock Configuration + Register + 0x20 + 0x20 + read-write + 0x00000000 + + + D3PPRE + D3 domain APB4 prescaler + 4 + 3 + + + + + PLLCKSELR + PLLCKSELR + RCC PLLs Clock Source Selection + Register + 0x28 + 0x20 + read-write + 0x02020200 + + + PLLSRC + DIVMx and PLLs clock source + selection + 0 + 2 + + + DIVM1 + Prescaler for PLL1 + 4 + 6 + + + DIVM2 + Prescaler for PLL2 + 12 + 6 + + + DIVM3 + Prescaler for PLL3 + 20 + 6 + + + + + PLLCFGR + PLLCFGR + RCC PLLs Configuration + Register + 0x2C + 0x20 + read-write + 0x01FF0000 + + + PLL1FRACEN + PLL1 fractional latch + enable + 0 + 1 + + + PLL1VCOSEL + PLL1 VCO selection + 1 + 1 + + + PLL1RGE + PLL1 input frequency range + 2 + 2 + + + PLL2FRACEN + PLL2 fractional latch + enable + 4 + 1 + + + PLL2VCOSEL + PLL2 VCO selection + 5 + 1 + + + PLL2RGE + PLL2 input frequency range + 6 + 2 + + + PLL3FRACEN + PLL3 fractional latch + enable + 8 + 1 + + + PLL3VCOSEL + PLL3 VCO selection + 9 + 1 + + + PLL3RGE + PLL3 input frequency range + 10 + 2 + + + DIVP1EN + PLL1 DIVP divider output + enable + 16 + 1 + + + DIVQ1EN + PLL1 DIVQ divider output + enable + 17 + 1 + + + DIVR1EN + PLL1 DIVR divider output + enable + 18 + 1 + + + DIVP2EN + PLL2 DIVP divider output + enable + 19 + 1 + + + DIVQ2EN + PLL2 DIVQ divider output + enable + 20 + 1 + + + DIVR2EN + PLL2 DIVR divider output + enable + 21 + 1 + + + DIVP3EN + PLL3 DIVP divider output + enable + 22 + 1 + + + DIVQ3EN + PLL3 DIVQ divider output + enable + 23 + 1 + + + DIVR3EN + PLL3 DIVR divider output + enable + 24 + 1 + + + + + PLL1DIVR + PLL1DIVR + RCC PLL1 Dividers Configuration + Register + 0x30 + 0x20 + read-write + 0x01010280 + + + DIVN1 + Multiplication factor for PLL1 + VCO + 0 + 9 + + + DIVP1 + PLL1 DIVP division factor + 9 + 7 + + + DIVQ1 + PLL1 DIVQ division factor + 16 + 7 + + + DIVR1 + PLL1 DIVR division factor + 24 + 7 + + + + + PLL1FRACR + PLL1FRACR + RCC PLL1 Fractional Divider + Register + 0x34 + 0x20 + read-write + 0x00000000 + + + FRACN1 + Fractional part of the multiplication + factor for PLL1 VCO + 3 + 13 + + + + + PLL2DIVR + PLL2DIVR + RCC PLL2 Dividers Configuration + Register + 0x38 + 0x20 + read-write + 0x01010280 + + + DIVN1 + Multiplication factor for PLL1 + VCO + 0 + 9 + + + DIVP1 + PLL1 DIVP division factor + 9 + 7 + + + DIVQ1 + PLL1 DIVQ division factor + 16 + 7 + + + DIVR1 + PLL1 DIVR division factor + 24 + 7 + + + + + PLL2FRACR + PLL2FRACR + RCC PLL2 Fractional Divider + Register + 0x3C + 0x20 + read-write + 0x00000000 + + + FRACN2 + Fractional part of the multiplication + factor for PLL VCO + 3 + 13 + + + + + PLL3DIVR + PLL3DIVR + RCC PLL3 Dividers Configuration + Register + 0x40 + 0x20 + read-write + 0x01010280 + + + DIVN3 + Multiplication factor for PLL1 + VCO + 0 + 9 + + + DIVP3 + PLL DIVP division factor + 9 + 7 + + + DIVQ3 + PLL DIVQ division factor + 16 + 7 + + + DIVR3 + PLL DIVR division factor + 24 + 7 + + + + + PLL3FRACR + PLL3FRACR + RCC PLL3 Fractional Divider + Register + 0x44 + 0x20 + read-write + 0x00000000 + + + FRACN3 + Fractional part of the multiplication + factor for PLL3 VCO + 3 + 13 + + + + + D1CCIPR + D1CCIPR + RCC Domain 1 Kernel Clock Configuration + Register + 0x4C + 0x20 + read-write + 0x00000000 + + + FMCSRC + FMC kernel clock source + selection + 0 + 2 + + + QSPISRC + QUADSPI kernel clock source + selection + 4 + 2 + + + SDMMCSRC + SDMMC kernel clock source + selection + 16 + 1 + + + CKPERSRC + per_ck clock source + selection + 28 + 2 + + + + + D2CCIP1R + D2CCIP1R + RCC Domain 2 Kernel Clock Configuration + Register + 0x50 + 0x20 + read-write + 0x00000000 + + + SAI1SRC + SAI1 and DFSDM1 kernel Aclk clock source + selection + 0 + 3 + + + SAI23SRC + SAI2 and SAI3 kernel clock source + selection + 6 + 3 + + + SPI123SRC + SPI/I2S1,2 and 3 kernel clock source + selection + 12 + 3 + + + SPI45SRC + SPI4 and 5 kernel clock source + selection + 16 + 3 + + + SPDIFSRC + SPDIFRX kernel clock source + selection + 20 + 2 + + + DFSDM1SRC + DFSDM1 kernel Clk clock source + selection + 24 + 1 + + + FDCANSRC + FDCAN kernel clock source + selection + 28 + 2 + + + SWPSRC + SWPMI kernel clock source + selection + 31 + 1 + + + + + D2CCIP2R + D2CCIP2R + RCC Domain 2 Kernel Clock Configuration + Register + 0x54 + 0x20 + read-write + 0x00000000 + + + USART234578SRC + USART2/3, UART4,5, 7/8 (APB1) kernel + clock source selection + 0 + 3 + + + USART16SRC + USART1 and 6 kernel clock source + selection + 3 + 3 + + + RNGSRC + RNG kernel clock source + selection + 8 + 2 + + + I2C123SRC + I2C1,2,3 kernel clock source + selection + 12 + 2 + + + USBSRC + USBOTG 1 and 2 kernel clock source + selection + 20 + 2 + + + CECSRC + HDMI-CEC kernel clock source + selection + 22 + 2 + + + LPTIM1SRC + LPTIM1 kernel clock source + selection + 28 + 3 + + + + + D3CCIPR + D3CCIPR + RCC Domain 3 Kernel Clock Configuration + Register + 0x58 + 0x20 + read-write + 0x00000000 + + + LPUART1SRC + LPUART1 kernel clock source + selection + 0 + 3 + + + I2C4SRC + I2C4 kernel clock source + selection + 8 + 2 + + + LPTIM2SRC + LPTIM2 kernel clock source + selection + 10 + 3 + + + LPTIM345SRC + LPTIM3,4,5 kernel clock source + selection + 13 + 3 + + + ADCSRC + SAR ADC kernel clock source + selection + 16 + 2 + + + SAI4ASRC + Sub-Block A of SAI4 kernel clock source + selection + 21 + 3 + + + SAI4BSRC + Sub-Block B of SAI4 kernel clock source + selection + 24 + 3 + + + SPI6SRC + SPI6 kernel clock source + selection + 28 + 3 + + + + + CIER + CIER + RCC Clock Source Interrupt Enable + Register + 0x60 + 0x20 + read-write + 0x00000000 + + + LSIRDYIE + LSI ready Interrupt Enable + 0 + 1 + + + LSERDYIE + LSE ready Interrupt Enable + 1 + 1 + + + HSIRDYIE + HSI ready Interrupt Enable + 2 + 1 + + + HSERDYIE + HSE ready Interrupt Enable + 3 + 1 + + + CSIRDYIE + CSI ready Interrupt Enable + 4 + 1 + + + RC48RDYIE + RC48 ready Interrupt + Enable + 5 + 1 + + + PLL1RDYIE + PLL1 ready Interrupt + Enable + 6 + 1 + + + PLL2RDYIE + PLL2 ready Interrupt + Enable + 7 + 1 + + + PLL3RDYIE + PLL3 ready Interrupt + Enable + 8 + 1 + + + LSECSSIE + LSE clock security system Interrupt + Enable + 9 + 1 + + + + + CIFR + CIFR + RCC Clock Source Interrupt Flag + Register + 0x64 + 0x20 + read-write + 0x00000000 + + + LSIRDYF + LSI ready Interrupt Flag + 0 + 1 + + + LSERDYF + LSE ready Interrupt Flag + 1 + 1 + + + HSIRDYF + HSI ready Interrupt Flag + 2 + 1 + + + HSERDYF + HSE ready Interrupt Flag + 3 + 1 + + + CSIRDY + CSI ready Interrupt Flag + 4 + 1 + + + RC48RDYF + RC48 ready Interrupt Flag + 5 + 1 + + + PLL1RDYF + PLL1 ready Interrupt Flag + 6 + 1 + + + PLL2RDYF + PLL2 ready Interrupt Flag + 7 + 1 + + + PLL3RDYF + PLL3 ready Interrupt Flag + 8 + 1 + + + LSECSSF + LSE clock security system Interrupt + Flag + 9 + 1 + + + HSECSSF + HSE clock security system Interrupt + Flag + 10 + 1 + + + + + CICR + CICR + RCC Clock Source Interrupt Clear + Register + 0x68 + 0x20 + read-write + 0x00000000 + + + LSIRDYC + LSI ready Interrupt Clear + 0 + 1 + + + LSERDYC + LSE ready Interrupt Clear + 1 + 1 + + + HSIRDYC + HSI ready Interrupt Clear + 2 + 1 + + + HSERDYC + HSE ready Interrupt Clear + 3 + 1 + + + HSE_ready_Interrupt_Clear + CSI ready Interrupt Clear + 4 + 1 + + + RC48RDYC + RC48 ready Interrupt Clear + 5 + 1 + + + PLL1RDYC + PLL1 ready Interrupt Clear + 6 + 1 + + + PLL2RDYC + PLL2 ready Interrupt Clear + 7 + 1 + + + PLL3RDYC + PLL3 ready Interrupt Clear + 8 + 1 + + + LSECSSC + LSE clock security system Interrupt + Clear + 9 + 1 + + + HSECSSC + HSE clock security system Interrupt + Clear + 10 + 1 + + + + + BDCR + BDCR + RCC Backup Domain Control + Register + 0x70 + 0x20 + read-write + 0x00000000 + + + LSEON + LSE oscillator enabled + 0 + 1 + + + LSERDY + LSE oscillator ready + 1 + 1 + + + LSEBYP + LSE oscillator bypass + 2 + 1 + + + LSEDRV + LSE oscillator driving + capability + 3 + 2 + + + LSECSSON + LSE clock security system + enable + 5 + 1 + + + LSECSSD + LSE clock security system failure + detection + 6 + 1 + + + RTCSRC + RTC clock source selection + 8 + 2 + + + RTCEN + RTC clock enable + 15 + 1 + + + VSWRST + VSwitch domain software + reset + 16 + 1 + + + + + CSR + CSR + RCC Clock Control and Status + Register + 0x74 + 0x20 + read-write + 0x00000000 + + + LSION + LSI oscillator enable + 0 + 1 + + + LSIRDY + LSI oscillator ready + 1 + 1 + + + + + AHB3RSTR + AHB3RSTR + RCC AHB3 Reset Register + 0x7C + 0x20 + read-write + 0x00000000 + + + MDMARST + MDMA block reset + 0 + 1 + + + DMA2DRST + DMA2D block reset + 4 + 1 + + + JPGDECRST + JPGDEC block reset + 5 + 1 + + + FMCRST + FMC block reset + 12 + 1 + + + QSPIRST + QUADSPI and QUADSPI delay block + reset + 14 + 1 + + + SDMMC1RST + SDMMC1 and SDMMC1 delay block + reset + 16 + 1 + + + CPURST + CPU reset + 31 + 1 + + + + + AHB1RSTR + AHB1RSTR + RCC AHB1 Peripheral Reset + Register + 0x80 + 0x20 + read-write + 0x00000000 + + + DMA1RST + DMA1 block reset + 0 + 1 + + + DMA2RST + DMA2 block reset + 1 + 1 + + + ADC12RST + ADC1&2 block reset + 5 + 1 + + + ETH1MACRST + ETH1MAC block reset + 15 + 1 + + + USB1OTGRST + USB1OTG block reset + 25 + 1 + + + USB2OTGRST + USB2OTG block reset + 27 + 1 + + + + + AHB2RSTR + AHB2RSTR + RCC AHB2 Peripheral Reset + Register + 0x84 + 0x20 + read-write + 0x00000000 + + + CAMITFRST + CAMITF block reset + 0 + 1 + + + CRYPTRST + Cryptography block reset + 4 + 1 + + + HASHRST + Hash block reset + 5 + 1 + + + RNGRST + Random Number Generator block + reset + 6 + 1 + + + SDMMC2RST + SDMMC2 and SDMMC2 Delay block + reset + 9 + 1 + + + + + AHB4RSTR + AHB4RSTR + RCC AHB4 Peripheral Reset + Register + 0x88 + 0x20 + read-write + 0x00000000 + + + GPIOARST + GPIO block reset + 0 + 1 + + + GPIOBRST + GPIO block reset + 1 + 1 + + + GPIOCRST + GPIO block reset + 2 + 1 + + + GPIODRST + GPIO block reset + 3 + 1 + + + GPIOERST + GPIO block reset + 4 + 1 + + + GPIOFRST + GPIO block reset + 5 + 1 + + + GPIOGRST + GPIO block reset + 6 + 1 + + + GPIOHRST + GPIO block reset + 7 + 1 + + + GPIOIRST + GPIO block reset + 8 + 1 + + + GPIOJRST + GPIO block reset + 9 + 1 + + + GPIOKRST + GPIO block reset + 10 + 1 + + + CRCRST + CRC block reset + 19 + 1 + + + BDMARST + BDMA block reset + 21 + 1 + + + ADC3RST + ADC3 block reset + 24 + 1 + + + HSEMRST + HSEM block reset + 25 + 1 + + + + + APB3RSTR + APB3RSTR + RCC APB3 Peripheral Reset + Register + 0x8C + 0x20 + read-write + 0x00000000 + + + LTDCRST + LTDC block reset + 3 + 1 + + + + + APB1LRSTR + APB1LRSTR + RCC APB1 Peripheral Reset + Register + 0x90 + 0x20 + read-write + 0x00000000 + + + TIM2RST + TIM block reset + 0 + 1 + + + TIM3RST + TIM block reset + 1 + 1 + + + TIM4RST + TIM block reset + 2 + 1 + + + TIM5RST + TIM block reset + 3 + 1 + + + TIM6RST + TIM block reset + 4 + 1 + + + TIM7RST + TIM block reset + 5 + 1 + + + TIM12RST + TIM block reset + 6 + 1 + + + TIM13RST + TIM block reset + 7 + 1 + + + TIM14RST + TIM block reset + 8 + 1 + + + LPTIM1RST + TIM block reset + 9 + 1 + + + SPI2RST + SPI2 block reset + 14 + 1 + + + SPI3RST + SPI3 block reset + 15 + 1 + + + SPDIFRXRST + SPDIFRX block reset + 16 + 1 + + + USART2RST + USART2 block reset + 17 + 1 + + + USART3RST + USART3 block reset + 18 + 1 + + + UART4RST + UART4 block reset + 19 + 1 + + + UART5RST + UART5 block reset + 20 + 1 + + + I2C1RST + I2C1 block reset + 21 + 1 + + + I2C2RST + I2C2 block reset + 22 + 1 + + + I2C3RST + I2C3 block reset + 23 + 1 + + + CECRST + HDMI-CEC block reset + 27 + 1 + + + DAC12RST + DAC1 and 2 Blocks Reset + 29 + 1 + + + USART7RST + USART7 block reset + 30 + 1 + + + USART8RST + USART8 block reset + 31 + 1 + + + + + APB1HRSTR + APB1HRSTR + RCC APB1 Peripheral Reset + Register + 0x94 + 0x20 + read-write + 0x00000000 + + + CRSRST + Clock Recovery System + reset + 1 + 1 + + + SWPRST + SWPMI block reset + 2 + 1 + + + OPAMPRST + OPAMP block reset + 4 + 1 + + + MDIOSRST + MDIOS block reset + 5 + 1 + + + FDCANRST + FDCAN block reset + 8 + 1 + + + + + APB2RSTR + APB2RSTR + RCC APB2 Peripheral Reset + Register + 0x98 + 0x20 + read-write + 0x00000000 + + + TIM1RST + TIM1 block reset + 0 + 1 + + + TIM8RST + TIM8 block reset + 1 + 1 + + + USART1RST + USART1 block reset + 4 + 1 + + + USART6RST + USART6 block reset + 5 + 1 + + + SPI1RST + SPI1 block reset + 12 + 1 + + + SPI4RST + SPI4 block reset + 13 + 1 + + + TIM15RST + TIM15 block reset + 16 + 1 + + + TIM16RST + TIM16 block reset + 17 + 1 + + + TIM17RST + TIM17 block reset + 18 + 1 + + + SPI5RST + SPI5 block reset + 20 + 1 + + + SAI1RST + SAI1 block reset + 22 + 1 + + + SAI2RST + SAI2 block reset + 23 + 1 + + + SAI3RST + SAI3 block reset + 24 + 1 + + + DFSDM1RST + DFSDM1 block reset + 28 + 1 + + + HRTIMRST + HRTIM block reset + 29 + 1 + + + + + APB4RSTR + APB4RSTR + RCC APB4 Peripheral Reset + Register + 0x9C + 0x20 + read-write + 0x00000000 + + + SYSCFGRST + SYSCFG block reset + 1 + 1 + + + LPUART1RST + LPUART1 block reset + 3 + 1 + + + SPI6RST + SPI6 block reset + 5 + 1 + + + I2C4RST + I2C4 block reset + 7 + 1 + + + LPTIM2RST + LPTIM2 block reset + 9 + 1 + + + LPTIM3RST + LPTIM3 block reset + 10 + 1 + + + LPTIM4RST + LPTIM4 block reset + 11 + 1 + + + LPTIM5RST + LPTIM5 block reset + 12 + 1 + + + COMP12RST + COMP12 Blocks Reset + 14 + 1 + + + VREFRST + VREF block reset + 15 + 1 + + + SAI4RST + SAI4 block reset + 21 + 1 + + + + + GCR + GCR + RCC Global Control Register + 0xA0 + 0x20 + read-write + 0x00000000 + + + WW1RSC + WWDG1 reset scope control + 0 + 1 + + + + + D3AMR + D3AMR + RCC D3 Autonomous mode + Register + 0xA8 + 0x20 + read-write + 0x00000000 + + + BDMAAMEN + BDMA and DMAMUX Autonomous mode + enable + 0 + 1 + + + LPUART1AMEN + LPUART1 Autonomous mode + enable + 3 + 1 + + + SPI6AMEN + SPI6 Autonomous mode + enable + 5 + 1 + + + I2C4AMEN + I2C4 Autonomous mode + enable + 7 + 1 + + + LPTIM2AMEN + LPTIM2 Autonomous mode + enable + 9 + 1 + + + LPTIM3AMEN + LPTIM3 Autonomous mode + enable + 10 + 1 + + + LPTIM4AMEN + LPTIM4 Autonomous mode + enable + 11 + 1 + + + LPTIM5AMEN + LPTIM5 Autonomous mode + enable + 12 + 1 + + + COMP12AMEN + COMP12 Autonomous mode + enable + 14 + 1 + + + VREFAMEN + VREF Autonomous mode + enable + 15 + 1 + + + RTCAMEN + RTC Autonomous mode enable + 16 + 1 + + + CRCAMEN + CRC Autonomous mode enable + 19 + 1 + + + SAI4AMEN + SAI4 Autonomous mode + enable + 21 + 1 + + + ADC3AMEN + ADC3 Autonomous mode + enable + 24 + 1 + + + BKPRAMAMEN + Backup RAM Autonomous mode + enable + 28 + 1 + + + SRAM4AMEN + SRAM4 Autonomous mode + enable + 29 + 1 + + + + + RSR + RSR + RCC Reset Status Register + 0xD0 + 0x20 + read-write + 0x00000000 + + + RMVF + Remove reset flag + 16 + 1 + + + CPURSTF + CPU reset flag + 17 + 1 + + + D1RSTF + D1 domain power switch reset + flag + 19 + 1 + + + D2RSTF + D2 domain power switch reset + flag + 20 + 1 + + + BORRSTF + BOR reset flag + 21 + 1 + + + PINRSTF + Pin reset flag (NRST) + 22 + 1 + + + PORRSTF + POR/PDR reset flag + 23 + 1 + + + SFTRSTF + System reset from CPU reset + flag + 24 + 1 + + + IWDG1RSTF + Independent Watchdog reset + flag + 26 + 1 + + + WWDG1RSTF + Window Watchdog reset flag + 28 + 1 + + + LPWRRSTF + Reset due to illegal D1 DStandby or CPU + CStop flag + 30 + 1 + + + + + C1_RSR + C1_RSR + RCC Reset Status Register + 0x130 + 0x20 + read-write + 0x00000000 + + + RMVF + Remove reset flag + 16 + 1 + + + CPURSTF + CPU reset flag + 17 + 1 + + + D1RSTF + D1 domain power switch reset + flag + 19 + 1 + + + D2RSTF + D2 domain power switch reset + flag + 20 + 1 + + + BORRSTF + BOR reset flag + 21 + 1 + + + PINRSTF + Pin reset flag (NRST) + 22 + 1 + + + PORRSTF + POR/PDR reset flag + 23 + 1 + + + SFTRSTF + System reset from CPU reset + flag + 24 + 1 + + + IWDG1RSTF + Independent Watchdog reset + flag + 26 + 1 + + + WWDG1RSTF + Window Watchdog reset flag + 28 + 1 + + + LPWRRSTF + Reset due to illegal D1 DStandby or CPU + CStop flag + 30 + 1 + + + + + C1_AHB3ENR + C1_AHB3ENR + RCC AHB3 Clock Register + 0x134 + 0x20 + read-write + 0x00000000 + + + MDMAEN + MDMA Peripheral Clock + Enable + 0 + 1 + + + DMA2DEN + DMA2D Peripheral Clock + Enable + 4 + 1 + + + JPGDECEN + JPGDEC Peripheral Clock + Enable + 5 + 1 + + + FMCEN + FMC Peripheral Clocks + Enable + 12 + 1 + + + QSPIEN + QUADSPI and QUADSPI Delay Clock + Enable + 14 + 1 + + + SDMMC1EN + SDMMC1 and SDMMC1 Delay Clock + Enable + 16 + 1 + + + + + AHB3ENR + AHB3ENR + RCC AHB3 Clock Register + 0xD4 + 0x20 + read-write + 0x00000000 + + + MDMAEN + MDMA Peripheral Clock + Enable + 0 + 1 + + + DMA2DEN + DMA2D Peripheral Clock + Enable + 4 + 1 + + + JPGDECEN + JPGDEC Peripheral Clock + Enable + 5 + 1 + + + FMCEN + FMC Peripheral Clocks + Enable + 12 + 1 + + + QSPIEN + QUADSPI and QUADSPI Delay Clock + Enable + 14 + 1 + + + SDMMC1EN + SDMMC1 and SDMMC1 Delay Clock + Enable + 16 + 1 + + + + + AHB1ENR + AHB1ENR + RCC AHB1 Clock Register + 0xD8 + 0x20 + read-write + 0x00000000 + + + DMA1EN + DMA1 Clock Enable + 0 + 1 + + + DMA2EN + DMA2 Clock Enable + 1 + 1 + + + ADC12EN + ADC1/2 Peripheral Clocks + Enable + 5 + 1 + + + ETH1MACEN + Ethernet MAC bus interface Clock + Enable + 15 + 1 + + + ETH1TXEN + Ethernet Transmission Clock + Enable + 16 + 1 + + + ETH1RXEN + Ethernet Reception Clock + Enable + 17 + 1 + + + USB2OTGHSULPIEN + Enable USB_PHY2 clocks + 18 + 1 + + + USB1OTGEN + USB1OTG Peripheral Clocks + Enable + 25 + 1 + + + USB1ULPIEN + USB_PHY1 Clocks Enable + 26 + 1 + + + USB2OTGEN + USB2OTG Peripheral Clocks + Enable + 27 + 1 + + + USB2ULPIEN + USB_PHY2 Clocks Enable + 28 + 1 + + + + + C1_AHB1ENR + C1_AHB1ENR + RCC AHB1 Clock Register + 0x138 + 0x20 + read-write + 0x00000000 + + + DMA1EN + DMA1 Clock Enable + 0 + 1 + + + DMA2EN + DMA2 Clock Enable + 1 + 1 + + + ADC12EN + ADC1/2 Peripheral Clocks + Enable + 5 + 1 + + + ETH1MACEN + Ethernet MAC bus interface Clock + Enable + 15 + 1 + + + ETH1TXEN + Ethernet Transmission Clock + Enable + 16 + 1 + + + ETH1RXEN + Ethernet Reception Clock + Enable + 17 + 1 + + + USB1OTGEN + USB1OTG Peripheral Clocks + Enable + 25 + 1 + + + USB1ULPIEN + USB_PHY1 Clocks Enable + 26 + 1 + + + USB2OTGEN + USB2OTG Peripheral Clocks + Enable + 27 + 1 + + + USB2ULPIEN + USB_PHY2 Clocks Enable + 28 + 1 + + + + + C1_AHB2ENR + C1_AHB2ENR + RCC AHB2 Clock Register + 0x13C + 0x20 + read-write + 0x00000000 + + + CAMITFEN + CAMITF peripheral clock + enable + 0 + 1 + + + CRYPTEN + CRYPT peripheral clock + enable + 4 + 1 + + + HASHEN + HASH peripheral clock + enable + 5 + 1 + + + RNGEN + RNG peripheral clocks + enable + 6 + 1 + + + SDMMC2EN + SDMMC2 and SDMMC2 delay clock + enable + 9 + 1 + + + SRAM1EN + SRAM1 block enable + 29 + 1 + + + SRAM2EN + SRAM2 block enable + 30 + 1 + + + SRAM3EN + SRAM3 block enable + 31 + 1 + + + + + AHB2ENR + AHB2ENR + RCC AHB2 Clock Register + 0xDC + 0x20 + read-write + 0x00000000 + + + CAMITFEN + CAMITF peripheral clock + enable + 0 + 1 + + + CRYPTEN + CRYPT peripheral clock + enable + 4 + 1 + + + HASHEN + HASH peripheral clock + enable + 5 + 1 + + + RNGEN + RNG peripheral clocks + enable + 6 + 1 + + + SDMMC2EN + SDMMC2 and SDMMC2 delay clock + enable + 9 + 1 + + + SRAM1EN + SRAM1 block enable + 29 + 1 + + + SRAM2EN + SRAM2 block enable + 30 + 1 + + + SRAM3EN + SRAM3 block enable + 31 + 1 + + + + + AHB4ENR + AHB4ENR + RCC AHB4 Clock Register + 0xE0 + 0x20 + read-write + 0x00000000 + + + GPIOAEN + 0GPIO peripheral clock + enable + 0 + 1 + + + GPIOBEN + 0GPIO peripheral clock + enable + 1 + 1 + + + GPIOCEN + 0GPIO peripheral clock + enable + 2 + 1 + + + GPIODEN + 0GPIO peripheral clock + enable + 3 + 1 + + + GPIOEEN + 0GPIO peripheral clock + enable + 4 + 1 + + + GPIOFEN + 0GPIO peripheral clock + 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1 + + + GPIOGEN + 0GPIO peripheral clock + enable + 6 + 1 + + + GPIOHEN + 0GPIO peripheral clock + enable + 7 + 1 + + + GPIOIEN + 0GPIO peripheral clock + enable + 8 + 1 + + + GPIOJEN + 0GPIO peripheral clock + enable + 9 + 1 + + + GPIOKEN + 0GPIO peripheral clock + enable + 10 + 1 + + + CRCEN + CRC peripheral clock + enable + 19 + 1 + + + BDMAEN + BDMA and DMAMUX2 Clock + Enable + 21 + 1 + + + ADC3EN + ADC3 Peripheral Clocks + Enable + 24 + 1 + + + HSEMEN + HSEM peripheral clock + enable + 25 + 1 + + + BKPRAMEN + Backup RAM Clock Enable + 28 + 1 + + + + + C1_APB3ENR + C1_APB3ENR + RCC APB3 Clock Register + 0x144 + 0x20 + read-write + 0x00000000 + + + LTDCEN + LTDC peripheral clock + enable + 3 + 1 + + + WWDG1EN + WWDG1 Clock Enable + 6 + 1 + + + + + APB3ENR + APB3ENR + RCC APB3 Clock Register + 0xE4 + 0x20 + read-write + 0x00000000 + + + LTDCEN + LTDC peripheral clock + enable + 3 + 1 + + + WWDG1EN + WWDG1 Clock Enable + 6 + 1 + + + + + APB1LENR + APB1LENR + RCC APB1 Clock Register + 0xE8 + 0x20 + read-write + 0x00000000 + + + TIM2EN + TIM peripheral clock + enable + 0 + 1 + + + TIM3EN + TIM peripheral clock + enable + 1 + 1 + + + TIM4EN + TIM peripheral clock + enable + 2 + 1 + + + TIM5EN + TIM peripheral clock + enable + 3 + 1 + + + TIM6EN + TIM peripheral clock + enable + 4 + 1 + + + TIM7EN + TIM peripheral clock + enable + 5 + 1 + + + TIM12EN + TIM peripheral clock + enable + 6 + 1 + + + TIM13EN + TIM peripheral clock + enable + 7 + 1 + + + TIM14EN + TIM peripheral clock + enable + 8 + 1 + + + LPTIM1EN + LPTIM1 Peripheral Clocks + Enable + 9 + 1 + + + SPI2EN + SPI2 Peripheral Clocks + Enable + 14 + 1 + + + SPI3EN + SPI3 Peripheral Clocks + Enable + 15 + 1 + + + SPDIFRXEN + SPDIFRX Peripheral Clocks + Enable + 16 + 1 + + + USART2EN + USART2 Peripheral Clocks + Enable + 17 + 1 + + + USART3EN + USART3 Peripheral Clocks + Enable + 18 + 1 + + + UART4EN + UART4 Peripheral Clocks + Enable + 19 + 1 + + + UART5EN + UART5 Peripheral Clocks + Enable + 20 + 1 + + + I2C1EN + I2C1 Peripheral Clocks + Enable + 21 + 1 + + + I2C2EN + I2C2 Peripheral Clocks + Enable + 22 + 1 + + + I2C3EN + I2C3 Peripheral Clocks + Enable + 23 + 1 + + + CECEN + HDMI-CEC peripheral clock + enable + 27 + 1 + + + DAC12EN + DAC1&2 peripheral clock + enable + 29 + 1 + + + USART7EN + USART7 Peripheral Clocks + Enable + 30 + 1 + + + USART8EN + USART8 Peripheral Clocks + Enable + 31 + 1 + + + + + C1_APB1LENR + C1_APB1LENR + RCC APB1 Clock Register + 0x148 + 0x20 + read-write + 0x00000000 + + + TIM2EN + TIM peripheral clock + enable + 0 + 1 + + + TIM3EN + TIM peripheral clock + enable + 1 + 1 + + + TIM4EN + TIM peripheral clock + enable + 2 + 1 + + + TIM5EN + TIM peripheral clock + enable + 3 + 1 + + + TIM6EN + TIM peripheral clock + enable + 4 + 1 + + + TIM7EN + TIM peripheral clock + enable + 5 + 1 + + + TIM12EN + TIM peripheral clock + enable + 6 + 1 + + + TIM13EN + TIM peripheral clock + enable + 7 + 1 + + + TIM14EN + TIM peripheral clock + enable + 8 + 1 + + + LPTIM1EN + LPTIM1 Peripheral Clocks + Enable + 9 + 1 + + + SPI2EN + SPI2 Peripheral Clocks + Enable + 14 + 1 + + + SPI3EN + SPI3 Peripheral Clocks + Enable + 15 + 1 + + + SPDIFRXEN + SPDIFRX Peripheral Clocks + Enable + 16 + 1 + + + USART2EN + USART2 Peripheral Clocks + Enable + 17 + 1 + + + USART3EN + USART3 Peripheral Clocks + Enable + 18 + 1 + + + UART4EN + UART4 Peripheral Clocks + Enable + 19 + 1 + + + UART5EN + UART5 Peripheral Clocks + Enable + 20 + 1 + + + I2C1EN + I2C1 Peripheral Clocks + Enable + 21 + 1 + + + I2C2EN + I2C2 Peripheral Clocks + Enable + 22 + 1 + + + I2C3EN + I2C3 Peripheral Clocks + Enable + 23 + 1 + + + HDMICECEN + HDMI-CEC peripheral clock + enable + 27 + 1 + + + DAC12EN + DAC1&2 peripheral clock + enable + 29 + 1 + + + USART7EN + USART7 Peripheral Clocks + Enable + 30 + 1 + + + USART8EN + USART8 Peripheral Clocks + Enable + 31 + 1 + + + + + APB1HENR + APB1HENR + RCC APB1 Clock Register + 0xEC + 0x20 + read-write + 0x00000000 + + + CRSEN + Clock Recovery System peripheral clock + enable + 1 + 1 + + + SWPEN + SWPMI Peripheral Clocks + Enable + 2 + 1 + + + OPAMPEN + OPAMP peripheral clock + enable + 4 + 1 + + + MDIOSEN + MDIOS peripheral clock + enable + 5 + 1 + + + FDCANEN + FDCAN Peripheral Clocks + Enable + 8 + 1 + + + + + C1_APB1HENR + C1_APB1HENR + RCC APB1 Clock Register + 0x14C + 0x20 + read-write + 0x00000000 + + + CRSEN + Clock Recovery System peripheral clock + enable + 1 + 1 + + + SWPEN + SWPMI Peripheral Clocks + Enable + 2 + 1 + + + OPAMPEN + OPAMP peripheral clock + enable + 4 + 1 + + + MDIOSEN + MDIOS peripheral clock + enable + 5 + 1 + + + FDCANEN + FDCAN Peripheral Clocks + Enable + 8 + 1 + + + + + C1_APB2ENR + C1_APB2ENR + RCC APB2 Clock Register + 0x150 + 0x20 + read-write + 0x00000000 + + + TIM1EN + TIM1 peripheral clock + enable + 0 + 1 + + + TIM8EN + TIM8 peripheral clock + enable + 1 + 1 + + + USART1EN + USART1 Peripheral Clocks + Enable + 4 + 1 + + + USART6EN + USART6 Peripheral Clocks + Enable + 5 + 1 + + + SPI1EN + SPI1 Peripheral Clocks + Enable + 12 + 1 + + + SPI4EN + SPI4 Peripheral Clocks + Enable + 13 + 1 + + + TIM16EN + TIM16 peripheral clock + enable + 17 + 1 + + + TIM15EN + TIM15 peripheral clock + enable + 16 + 1 + + + TIM17EN + TIM17 peripheral clock + enable + 18 + 1 + + + SPI5EN + SPI5 Peripheral Clocks + Enable + 20 + 1 + + + SAI1EN + SAI1 Peripheral Clocks + Enable + 22 + 1 + + + SAI2EN + SAI2 Peripheral Clocks + Enable + 23 + 1 + + + SAI3EN + SAI3 Peripheral Clocks + Enable + 24 + 1 + + + DFSDM1EN + DFSDM1 Peripheral Clocks + Enable + 28 + 1 + + + HRTIMEN + HRTIM peripheral clock + enable + 29 + 1 + + + + + APB2ENR + APB2ENR + RCC APB2 Clock Register + 0xF0 + 0x20 + read-write + 0x00000000 + + + TIM1EN + TIM1 peripheral clock + enable + 0 + 1 + + + TIM8EN + TIM8 peripheral clock + enable + 1 + 1 + + + USART1EN + USART1 Peripheral Clocks + Enable + 4 + 1 + + + USART6EN + USART6 Peripheral Clocks + Enable + 5 + 1 + + + SPI1EN + SPI1 Peripheral Clocks + Enable + 12 + 1 + + + SPI4EN + SPI4 Peripheral Clocks + Enable + 13 + 1 + + + TIM16EN + TIM16 peripheral clock + enable + 17 + 1 + + + TIM15EN + TIM15 peripheral clock + enable + 16 + 1 + + + TIM17EN + TIM17 peripheral clock + enable + 18 + 1 + + + SPI5EN + SPI5 Peripheral Clocks + Enable + 20 + 1 + + + SAI1EN + SAI1 Peripheral Clocks + Enable + 22 + 1 + + + SAI2EN + SAI2 Peripheral Clocks + Enable + 23 + 1 + + + SAI3EN + SAI3 Peripheral Clocks + Enable + 24 + 1 + + + DFSDM1EN + DFSDM1 Peripheral Clocks + Enable + 28 + 1 + + + HRTIMEN + HRTIM peripheral clock + enable + 29 + 1 + + + + + APB4ENR + APB4ENR + RCC APB4 Clock Register + 0xF4 + 0x20 + read-write + 0x00000000 + + + SYSCFGEN + SYSCFG peripheral clock + enable + 1 + 1 + + + LPUART1EN + LPUART1 Peripheral Clocks + Enable + 3 + 1 + + + SPI6EN + SPI6 Peripheral Clocks + Enable + 5 + 1 + + + I2C4EN + I2C4 Peripheral Clocks + Enable + 7 + 1 + + + LPTIM2EN + LPTIM2 Peripheral Clocks + Enable + 9 + 1 + + + LPTIM3EN + LPTIM3 Peripheral Clocks + Enable + 10 + 1 + + + LPTIM4EN + LPTIM4 Peripheral Clocks + Enable + 11 + 1 + + + LPTIM5EN + LPTIM5 Peripheral Clocks + Enable + 12 + 1 + + + COMP12EN + COMP1/2 peripheral clock + enable + 14 + 1 + + + VREFEN + VREF peripheral clock + enable + 15 + 1 + + + RTCAPBEN + RTC APB Clock Enable + 16 + 1 + + + SAI4EN + SAI4 Peripheral Clocks + Enable + 21 + 1 + + + + + C1_APB4ENR + C1_APB4ENR + RCC APB4 Clock Register + 0x154 + 0x20 + read-write + 0x00000000 + + + SYSCFGEN + SYSCFG peripheral clock + enable + 1 + 1 + + + LPUART1EN + LPUART1 Peripheral Clocks + Enable + 3 + 1 + + + SPI6EN + SPI6 Peripheral Clocks + Enable + 5 + 1 + + + I2C4EN + I2C4 Peripheral Clocks + Enable + 7 + 1 + + + LPTIM2EN + LPTIM2 Peripheral Clocks + Enable + 9 + 1 + + + LPTIM3EN + LPTIM3 Peripheral Clocks + Enable + 10 + 1 + + + LPTIM4EN + LPTIM4 Peripheral Clocks + Enable + 11 + 1 + + + LPTIM5EN + LPTIM5 Peripheral Clocks + Enable + 12 + 1 + + + COMP12EN + COMP1/2 peripheral clock + enable + 14 + 1 + + + VREFEN + VREF peripheral clock + enable + 15 + 1 + + + RTCAPBEN + RTC APB Clock Enable + 16 + 1 + + + SAI4EN + SAI4 Peripheral Clocks + Enable + 21 + 1 + + + + + C1_AHB3LPENR + C1_AHB3LPENR + RCC AHB3 Sleep Clock Register + 0x15C + 0x20 + read-write + 0x00000000 + + + MDMALPEN + MDMA Clock Enable During CSleep + Mode + 0 + 1 + + + DMA2DLPEN + DMA2D Clock Enable During CSleep + Mode + 4 + 1 + + + JPGDECLPEN + JPGDEC Clock Enable During CSleep + Mode + 5 + 1 + + + FLITFLPEN + FLITF Clock Enable During CSleep + Mode + 8 + 1 + + + FMCLPEN + FMC Peripheral Clocks Enable During + CSleep Mode + 12 + 1 + + + QSPILPEN + QUADSPI and QUADSPI Delay Clock Enable + During CSleep Mode + 14 + 1 + + + SDMMC1LPEN + SDMMC1 and SDMMC1 Delay Clock Enable + During CSleep Mode + 16 + 1 + + + D1DTCM1LPEN + D1DTCM1 Block Clock Enable During CSleep + mode + 28 + 1 + + + DTCM2LPEN + D1 DTCM2 Block Clock Enable During + CSleep mode + 29 + 1 + + + ITCMLPEN + D1ITCM Block Clock Enable During CSleep + mode + 30 + 1 + + + AXISRAMLPEN + AXISRAM Block Clock Enable During CSleep + mode + 31 + 1 + + + + + AHB3LPENR + AHB3LPENR + RCC AHB3 Sleep Clock Register + 0xFC + 0x20 + read-write + 0x00000000 + + + MDMALPEN + MDMA Clock Enable During CSleep + Mode + 0 + 1 + + + DMA2DLPEN + DMA2D Clock Enable During CSleep + Mode + 4 + 1 + + + JPGDECLPEN + JPGDEC Clock Enable During CSleep + Mode + 5 + 1 + + + FLASHLPEN + FLITF Clock Enable During CSleep + Mode + 8 + 1 + + + FMCLPEN + FMC Peripheral Clocks Enable During + CSleep Mode + 12 + 1 + + + QSPILPEN + QUADSPI and QUADSPI Delay Clock Enable + During CSleep Mode + 14 + 1 + + + SDMMC1LPEN + SDMMC1 and SDMMC1 Delay Clock Enable + During CSleep Mode + 16 + 1 + + + D1DTCM1LPEN + D1DTCM1 Block Clock Enable During CSleep + mode + 28 + 1 + + + DTCM2LPEN + D1 DTCM2 Block Clock Enable During + CSleep mode + 29 + 1 + + + ITCMLPEN + D1ITCM Block Clock Enable During CSleep + mode + 30 + 1 + + + AXISRAMLPEN + AXISRAM Block Clock Enable During CSleep + mode + 31 + 1 + + + + + AHB1LPENR + AHB1LPENR + RCC AHB1 Sleep Clock Register + 0x100 + 0x20 + read-write + 0x00000000 + + + DMA1LPEN + DMA1 Clock Enable During CSleep + Mode + 0 + 1 + + + DMA2LPEN + DMA2 Clock Enable During CSleep + Mode + 1 + 1 + + + ADC12LPEN + ADC1/2 Peripheral Clocks Enable During + CSleep Mode + 5 + 1 + + + ETH1MACLPEN + Ethernet MAC bus interface Clock Enable + During CSleep Mode + 15 + 1 + + + ETH1TXLPEN + Ethernet Transmission Clock Enable + During CSleep Mode + 16 + 1 + + + ETH1RXLPEN + Ethernet Reception Clock Enable During + CSleep Mode + 17 + 1 + + + USB1OTGHSLPEN + USB1OTG peripheral clock enable during + CSleep mode + 25 + 1 + + + USB1OTGHSULPILPEN + USB_PHY1 clock enable during CSleep + mode + 26 + 1 + + + USB2OTGHSLPEN + USB2OTG peripheral clock enable during + CSleep mode + 27 + 1 + + + USB2OTGHSULPILPEN + USB_PHY2 clocks enable during CSleep + mode + 28 + 1 + + + + + C1_AHB1LPENR + C1_AHB1LPENR + RCC AHB1 Sleep Clock Register + 0x160 + 0x20 + read-write + 0x00000000 + + + DMA1LPEN + DMA1 Clock Enable During CSleep + Mode + 0 + 1 + + + DMA2LPEN + DMA2 Clock Enable During CSleep + Mode + 1 + 1 + + + ADC12LPEN + ADC1/2 Peripheral Clocks Enable During + CSleep Mode + 5 + 1 + + + ETH1MACLPEN + Ethernet MAC bus interface Clock Enable + During CSleep Mode + 15 + 1 + + + ETH1TXLPEN + Ethernet Transmission Clock Enable + During CSleep Mode + 16 + 1 + + + ETH1RXLPEN + Ethernet Reception Clock Enable During + CSleep Mode + 17 + 1 + + + USB1OTGLPEN + USB1OTG peripheral clock enable during + CSleep mode + 25 + 1 + + + USB1ULPILPEN + USB_PHY1 clock enable during CSleep + mode + 26 + 1 + + + USB2OTGLPEN + USB2OTG peripheral clock enable during + CSleep mode + 27 + 1 + + + USB2ULPILPEN + USB_PHY2 clocks enable during CSleep + mode + 28 + 1 + + + + + C1_AHB2LPENR + C1_AHB2LPENR + RCC AHB2 Sleep Clock Register + 0x164 + 0x20 + read-write + 0x00000000 + + + CAMITFLPEN + CAMITF peripheral clock enable during + CSleep mode + 0 + 1 + + + CRYPTLPEN + CRYPT peripheral clock enable during + CSleep mode + 4 + 1 + + + HASHLPEN + HASH peripheral clock enable during + CSleep mode + 5 + 1 + + + SDMMC2LPEN + SDMMC2 and SDMMC2 Delay Clock Enable + During CSleep Mode + 9 + 1 + + + RNGLPEN + RNG peripheral clock enable during + CSleep mode + 6 + 1 + + + SRAM1LPEN + SRAM1 Clock Enable During CSleep + Mode + 29 + 1 + + + SRAM2LPEN + SRAM2 Clock Enable During CSleep + Mode + 30 + 1 + + + SRAM3LPEN + SRAM3 Clock Enable During CSleep + Mode + 31 + 1 + + + + + AHB2LPENR + AHB2LPENR + RCC AHB2 Sleep Clock Register + 0x104 + 0x20 + read-write + 0x00000000 + + + CAMITFLPEN + CAMITF peripheral clock enable during + CSleep mode + 0 + 1 + + + CRYPTLPEN + CRYPT peripheral clock enable during + CSleep mode + 4 + 1 + + + HASHLPEN + HASH peripheral clock enable during + CSleep mode + 5 + 1 + + + SDMMC2LPEN + SDMMC2 and SDMMC2 Delay Clock Enable + During CSleep Mode + 9 + 1 + + + RNGLPEN + RNG peripheral clock enable during + CSleep mode + 6 + 1 + + + SRAM1LPEN + SRAM1 Clock Enable During CSleep + Mode + 29 + 1 + + + SRAM2LPEN + SRAM2 Clock Enable During CSleep + Mode + 30 + 1 + + + SRAM3LPEN + SRAM3 Clock Enable During CSleep + Mode + 31 + 1 + + + + + AHB4LPENR + AHB4LPENR + RCC AHB4 Sleep Clock Register + 0x108 + 0x20 + read-write + 0x00000000 + + + GPIOALPEN + GPIO peripheral clock enable during + CSleep mode + 0 + 1 + + + GPIOBLPEN + GPIO peripheral clock enable during + CSleep mode + 1 + 1 + + + GPIOCLPEN + GPIO peripheral clock enable during + CSleep mode + 2 + 1 + + + GPIODLPEN + GPIO peripheral clock enable during + CSleep mode + 3 + 1 + + + GPIOELPEN + GPIO peripheral clock enable during + CSleep mode + 4 + 1 + + + GPIOFLPEN + GPIO peripheral clock enable during + CSleep mode + 5 + 1 + + + GPIOGLPEN + GPIO peripheral clock enable during + CSleep mode + 6 + 1 + + + GPIOHLPEN + GPIO peripheral clock enable during + CSleep mode + 7 + 1 + + + GPIOILPEN + GPIO peripheral clock enable during + CSleep mode + 8 + 1 + + + GPIOJLPEN + GPIO peripheral clock enable during + CSleep mode + 9 + 1 + + + GPIOKLPEN + GPIO peripheral clock enable during + CSleep mode + 10 + 1 + + + CRCLPEN + CRC peripheral clock enable during + CSleep mode + 19 + 1 + + + BDMALPEN + BDMA Clock Enable During CSleep + Mode + 21 + 1 + + + ADC3LPEN + ADC3 Peripheral Clocks Enable During + CSleep Mode + 24 + 1 + + + BKPRAMLPEN + Backup RAM Clock Enable During CSleep + Mode + 28 + 1 + + + SRAM4LPEN + SRAM4 Clock Enable During CSleep + Mode + 29 + 1 + + + + + C1_AHB4LPENR + C1_AHB4LPENR + RCC AHB4 Sleep Clock Register + 0x168 + 0x20 + read-write + 0x00000000 + + + GPIOALPEN + GPIO peripheral clock enable during + CSleep mode + 0 + 1 + + + GPIOBLPEN + GPIO peripheral clock enable during + CSleep mode + 1 + 1 + + + GPIOCLPEN + GPIO peripheral clock enable during + CSleep mode + 2 + 1 + + + GPIODLPEN + GPIO peripheral clock enable during + CSleep mode + 3 + 1 + + + GPIOELPEN + GPIO peripheral clock enable during + CSleep mode + 4 + 1 + + + GPIOFLPEN + GPIO peripheral clock enable during + CSleep mode + 5 + 1 + + + GPIOGLPEN + GPIO peripheral clock enable during + CSleep mode + 6 + 1 + + + GPIOHLPEN + GPIO peripheral clock enable during + CSleep mode + 7 + 1 + + + GPIOILPEN + GPIO peripheral clock enable during + CSleep mode + 8 + 1 + + + GPIOJLPEN + GPIO peripheral clock enable during + CSleep mode + 9 + 1 + + + GPIOKLPEN + GPIO peripheral clock enable during + CSleep mode + 10 + 1 + + + CRCLPEN + CRC peripheral clock enable during + CSleep mode + 19 + 1 + + + BDMALPEN + BDMA Clock Enable During CSleep + Mode + 21 + 1 + + + ADC3LPEN + ADC3 Peripheral Clocks Enable During + CSleep Mode + 24 + 1 + + + BKPRAMLPEN + Backup RAM Clock Enable During CSleep + Mode + 28 + 1 + + + SRAM4LPEN + SRAM4 Clock Enable During CSleep + Mode + 29 + 1 + + + + + C1_APB3LPENR + C1_APB3LPENR + RCC APB3 Sleep Clock Register + 0x16C + 0x20 + read-write + 0x00000000 + + + LTDCLPEN + LTDC peripheral clock enable during + CSleep mode + 3 + 1 + + + WWDG1LPEN + WWDG1 Clock Enable During CSleep + Mode + 6 + 1 + + + + + APB3LPENR + APB3LPENR + RCC APB3 Sleep Clock Register + 0x10C + 0x20 + read-write + 0x00000000 + + + LTDCLPEN + LTDC peripheral clock enable during + CSleep mode + 3 + 1 + + + WWDG1LPEN + WWDG1 Clock Enable During CSleep + Mode + 6 + 1 + + + + + APB1LLPENR + APB1LLPENR + RCC APB1 Low Sleep Clock + Register + 0x110 + 0x20 + read-write + 0x00000000 + + + TIM2LPEN + TIM2 peripheral clock enable during + CSleep mode + 0 + 1 + + + TIM3LPEN + TIM3 peripheral clock enable during + CSleep mode + 1 + 1 + + + TIM4LPEN + TIM4 peripheral clock enable during + CSleep mode + 2 + 1 + + + TIM5LPEN + TIM5 peripheral clock enable during + CSleep mode + 3 + 1 + + + TIM6LPEN + TIM6 peripheral clock enable during + CSleep mode + 4 + 1 + + + TIM7LPEN + TIM7 peripheral clock enable during + CSleep mode + 5 + 1 + + + TIM12LPEN + TIM12 peripheral clock enable during + CSleep mode + 6 + 1 + + + TIM13LPEN + TIM13 peripheral clock enable during + CSleep mode + 7 + 1 + + + TIM14LPEN + TIM14 peripheral clock enable during + CSleep mode + 8 + 1 + + + LPTIM1LPEN + LPTIM1 Peripheral Clocks Enable During + CSleep Mode + 9 + 1 + + + SPI2LPEN + SPI2 Peripheral Clocks Enable During + CSleep Mode + 14 + 1 + + + SPI3LPEN + SPI3 Peripheral Clocks Enable During + CSleep Mode + 15 + 1 + + + SPDIFRXLPEN + SPDIFRX Peripheral Clocks Enable During + CSleep Mode + 16 + 1 + + + USART2LPEN + USART2 Peripheral Clocks Enable During + CSleep Mode + 17 + 1 + + + USART3LPEN + USART3 Peripheral Clocks Enable During + CSleep Mode + 18 + 1 + + + UART4LPEN + UART4 Peripheral Clocks Enable During + CSleep Mode + 19 + 1 + + + UART5LPEN + UART5 Peripheral Clocks Enable During + CSleep Mode + 20 + 1 + + + I2C1LPEN + I2C1 Peripheral Clocks Enable During + CSleep Mode + 21 + 1 + + + I2C2LPEN + I2C2 Peripheral Clocks Enable During + CSleep Mode + 22 + 1 + + + I2C3LPEN + I2C3 Peripheral Clocks Enable During + CSleep Mode + 23 + 1 + + + HDMICECLPEN + HDMI-CEC Peripheral Clocks Enable During + CSleep Mode + 27 + 1 + + + DAC12LPEN + DAC1/2 peripheral clock enable during + CSleep mode + 29 + 1 + + + USART7LPEN + USART7 Peripheral Clocks Enable During + CSleep Mode + 30 + 1 + + + USART8LPEN + USART8 Peripheral Clocks Enable During + CSleep Mode + 31 + 1 + + + + + C1_APB1LLPENR + C1_APB1LLPENR + RCC APB1 Low Sleep Clock + Register + 0x170 + 0x20 + read-write + 0x00000000 + + + TIM2LPEN + TIM2 peripheral clock enable during + CSleep mode + 0 + 1 + + + TIM3LPEN + TIM3 peripheral clock enable during + CSleep mode + 1 + 1 + + + TIM4LPEN + TIM4 peripheral clock enable during + CSleep mode + 2 + 1 + + + TIM5LPEN + TIM5 peripheral clock enable during + CSleep mode + 3 + 1 + + + TIM6LPEN + TIM6 peripheral clock enable during + CSleep mode + 4 + 1 + + + TIM7LPEN + TIM7 peripheral clock enable during + CSleep mode + 5 + 1 + + + TIM12LPEN + TIM12 peripheral clock enable during + CSleep mode + 6 + 1 + + + TIM13LPEN + TIM13 peripheral clock enable during + CSleep mode + 7 + 1 + + + TIM14LPEN + TIM14 peripheral clock enable during + CSleep mode + 8 + 1 + + + LPTIM1LPEN + LPTIM1 Peripheral Clocks Enable During + CSleep Mode + 9 + 1 + + + SPI2LPEN + SPI2 Peripheral Clocks Enable During + CSleep Mode + 14 + 1 + + + SPI3LPEN + SPI3 Peripheral Clocks Enable During + CSleep Mode + 15 + 1 + + + SPDIFRXLPEN + SPDIFRX Peripheral Clocks Enable During + CSleep Mode + 16 + 1 + + + USART2LPEN + USART2 Peripheral Clocks Enable During + CSleep Mode + 17 + 1 + + + USART3LPEN + USART3 Peripheral Clocks Enable During + CSleep Mode + 18 + 1 + + + UART4LPEN + UART4 Peripheral Clocks Enable During + CSleep Mode + 19 + 1 + + + UART5LPEN + UART5 Peripheral Clocks Enable During + CSleep Mode + 20 + 1 + + + I2C1LPEN + I2C1 Peripheral Clocks Enable During + CSleep Mode + 21 + 1 + + + I2C2LPEN + I2C2 Peripheral Clocks Enable During + CSleep Mode + 22 + 1 + + + I2C3LPEN + I2C3 Peripheral Clocks Enable During + CSleep Mode + 23 + 1 + + + HDMICECLPEN + HDMI-CEC Peripheral Clocks Enable During + CSleep Mode + 27 + 1 + + + DAC12LPEN + DAC1/2 peripheral clock enable during + CSleep mode + 29 + 1 + + + USART7LPEN + USART7 Peripheral Clocks Enable During + CSleep Mode + 30 + 1 + + + USART8LPEN + USART8 Peripheral Clocks Enable During + CSleep Mode + 31 + 1 + + + + + C1_APB1HLPENR + C1_APB1HLPENR + RCC APB1 High Sleep Clock + Register + 0x174 + 0x20 + read-write + 0x00000000 + + + CRSLPEN + Clock Recovery System peripheral clock + enable during CSleep mode + 1 + 1 + + + SWPLPEN + SWPMI Peripheral Clocks Enable During + CSleep Mode + 2 + 1 + + + OPAMPLPEN + OPAMP peripheral clock enable during + CSleep mode + 4 + 1 + + + MDIOSLPEN + MDIOS peripheral clock enable during + CSleep mode + 5 + 1 + + + FDCANLPEN + FDCAN Peripheral Clocks Enable During + CSleep Mode + 8 + 1 + + + + + APB1HLPENR + APB1HLPENR + RCC APB1 High Sleep Clock + Register + 0x114 + 0x20 + read-write + 0x00000000 + + + CRSLPEN + Clock Recovery System peripheral clock + enable during CSleep mode + 1 + 1 + + + SWPLPEN + SWPMI Peripheral Clocks Enable During + CSleep Mode + 2 + 1 + + + OPAMPLPEN + OPAMP peripheral clock enable during + CSleep mode + 4 + 1 + + + MDIOSLPEN + MDIOS peripheral clock enable during + CSleep mode + 5 + 1 + + + FDCANLPEN + FDCAN Peripheral Clocks Enable During + CSleep Mode + 8 + 1 + + + + + APB2LPENR + APB2LPENR + RCC APB2 Sleep Clock Register + 0x118 + 0x20 + read-write + 0x00000000 + + + TIM1LPEN + TIM1 peripheral clock enable during + CSleep mode + 0 + 1 + + + TIM8LPEN + TIM8 peripheral clock enable during + CSleep mode + 1 + 1 + + + USART1LPEN + USART1 Peripheral Clocks Enable During + CSleep Mode + 4 + 1 + + + USART6LPEN + USART6 Peripheral Clocks Enable During + CSleep Mode + 5 + 1 + + + SPI1LPEN + SPI1 Peripheral Clocks Enable During + CSleep Mode + 12 + 1 + + + SPI4LPEN + SPI4 Peripheral Clocks Enable During + CSleep Mode + 13 + 1 + + + TIM15LPEN + TIM15 peripheral clock enable during + CSleep mode + 16 + 1 + + + TIM16LPEN + TIM16 peripheral clock enable during + CSleep mode + 17 + 1 + + + TIM17LPEN + TIM17 peripheral clock enable during + CSleep mode + 18 + 1 + + + SPI5LPEN + SPI5 Peripheral Clocks Enable During + CSleep Mode + 20 + 1 + + + SAI1LPEN + SAI1 Peripheral Clocks Enable During + CSleep Mode + 22 + 1 + + + SAI2LPEN + SAI2 Peripheral Clocks Enable During + CSleep Mode + 23 + 1 + + + SAI3LPEN + SAI3 Peripheral Clocks Enable During + CSleep Mode + 24 + 1 + + + DFSDM1LPEN + DFSDM1 Peripheral Clocks Enable During + CSleep Mode + 28 + 1 + + + HRTIMLPEN + HRTIM peripheral clock enable during + CSleep mode + 29 + 1 + + + + + C1_APB2LPENR + C1_APB2LPENR + RCC APB2 Sleep Clock Register + 0x178 + 0x20 + read-write + 0x00000000 + + + TIM1LPEN + TIM1 peripheral clock enable during + CSleep mode + 0 + 1 + + + TIM8LPEN + TIM8 peripheral clock enable during + CSleep mode + 1 + 1 + + + USART1LPEN + USART1 Peripheral Clocks Enable During + CSleep Mode + 4 + 1 + + + USART6LPEN + USART6 Peripheral Clocks Enable During + CSleep Mode + 5 + 1 + + + SPI1LPEN + SPI1 Peripheral Clocks Enable During + CSleep Mode + 12 + 1 + + + SPI4LPEN + SPI4 Peripheral Clocks Enable During + CSleep Mode + 13 + 1 + + + TIM15LPEN + TIM15 peripheral clock enable during + CSleep mode + 16 + 1 + + + TIM16LPEN + TIM16 peripheral clock enable during + CSleep mode + 17 + 1 + + + TIM17LPEN + TIM17 peripheral clock enable during + CSleep mode + 18 + 1 + + + SPI5LPEN + SPI5 Peripheral Clocks Enable During + CSleep Mode + 20 + 1 + + + SAI1LPEN + SAI1 Peripheral Clocks Enable During + CSleep Mode + 22 + 1 + + + SAI2LPEN + SAI2 Peripheral Clocks Enable During + CSleep Mode + 23 + 1 + + + SAI3LPEN + SAI3 Peripheral Clocks Enable During + CSleep Mode + 24 + 1 + + + DFSDM1LPEN + DFSDM1 Peripheral Clocks Enable During + CSleep Mode + 28 + 1 + + + HRTIMLPEN + HRTIM peripheral clock enable during + CSleep mode + 29 + 1 + + + + + C1_APB4LPENR + C1_APB4LPENR + RCC APB4 Sleep Clock Register + 0x17C + 0x20 + read-write + 0x00000000 + + + SYSCFGLPEN + SYSCFG peripheral clock enable during + CSleep mode + 1 + 1 + + + LPUART1LPEN + LPUART1 Peripheral Clocks Enable During + CSleep Mode + 3 + 1 + + + SPI6LPEN + SPI6 Peripheral Clocks Enable During + CSleep Mode + 5 + 1 + + + I2C4LPEN + I2C4 Peripheral Clocks Enable During + CSleep Mode + 7 + 1 + + + LPTIM2LPEN + LPTIM2 Peripheral Clocks Enable During + CSleep Mode + 9 + 1 + + + LPTIM3LPEN + LPTIM3 Peripheral Clocks Enable During + CSleep Mode + 10 + 1 + + + LPTIM4LPEN + LPTIM4 Peripheral Clocks Enable During + CSleep Mode + 11 + 1 + + + LPTIM5LPEN + LPTIM5 Peripheral Clocks Enable During + CSleep Mode + 12 + 1 + + + COMP12LPEN + COMP1/2 peripheral clock enable during + CSleep mode + 14 + 1 + + + VREFLPEN + VREF peripheral clock enable during + CSleep mode + 15 + 1 + + + RTCAPBLPEN + RTC APB Clock Enable During CSleep + Mode + 16 + 1 + + + SAI4LPEN + SAI4 Peripheral Clocks Enable During + CSleep Mode + 21 + 1 + + + + + APB4LPENR + APB4LPENR + RCC APB4 Sleep Clock Register + 0x11C + 0x20 + read-write + 0x00000000 + + + SYSCFGLPEN + SYSCFG peripheral clock enable during + CSleep mode + 1 + 1 + + + LPUART1LPEN + LPUART1 Peripheral Clocks Enable During + CSleep Mode + 3 + 1 + + + SPI6LPEN + SPI6 Peripheral Clocks Enable During + CSleep Mode + 5 + 1 + + + I2C4LPEN + I2C4 Peripheral Clocks Enable During + CSleep Mode + 7 + 1 + + + LPTIM2LPEN + LPTIM2 Peripheral Clocks Enable During + CSleep Mode + 9 + 1 + + + LPTIM3LPEN + LPTIM3 Peripheral Clocks Enable During + CSleep Mode + 10 + 1 + + + LPTIM4LPEN + LPTIM4 Peripheral Clocks Enable During + CSleep Mode + 11 + 1 + + + LPTIM5LPEN + LPTIM5 Peripheral Clocks Enable During + CSleep Mode + 12 + 1 + + + COMP12LPEN + COMP1/2 peripheral clock enable during + CSleep mode + 14 + 1 + + + VREFLPEN + VREF peripheral clock enable during + CSleep mode + 15 + 1 + + + RTCAPBLPEN + RTC APB Clock Enable During CSleep + Mode + 16 + 1 + + + SAI4LPEN + SAI4 Peripheral Clocks Enable During + CSleep Mode + 21 + 1 + + + + + + + LPTIM1 + Low power timer + LPTIM + 0x40002400 + + 0x0 + 0x400 + registers + + + LPTIM1 + LPTIM1 global interrupt + 93 + + + + ISR + ISR + Interrupt and Status Register + 0x0 + 0x20 + read-only + 0x00000000 + + + DOWN + Counter direction change up to + down + 6 + 1 + + + UP + Counter direction change down to + up + 5 + 1 + + + ARROK + Autoreload register update + OK + 4 + 1 + + + CMPOK + Compare register update OK + 3 + 1 + + + EXTTRIG + External trigger edge + event + 2 + 1 + + + ARRM + Autoreload match + 1 + 1 + + + CMPM + Compare match + 0 + 1 + + + + + ICR + ICR + Interrupt Clear Register + 0x4 + 0x20 + write-only + 0x00000000 + + + DOWNCF + Direction change to down Clear + Flag + 6 + 1 + + + UPCF + Direction change to UP Clear + Flag + 5 + 1 + + + ARROKCF + Autoreload register update OK Clear + Flag + 4 + 1 + + + CMPOKCF + Compare register update OK Clear + Flag + 3 + 1 + + + EXTTRIGCF + External trigger valid edge Clear + Flag + 2 + 1 + + + ARRMCF + Autoreload match Clear + Flag + 1 + 1 + + + CMPMCF + compare match Clear Flag + 0 + 1 + + + + + IER + IER + Interrupt Enable Register + 0x8 + 0x20 + read-write + 0x00000000 + + + DOWNIE + Direction change to down Interrupt + Enable + 6 + 1 + + + UPIE + Direction change to UP Interrupt + Enable + 5 + 1 + + + ARROKIE + Autoreload register update OK Interrupt + Enable + 4 + 1 + + + CMPOKIE + Compare register update OK Interrupt + Enable + 3 + 1 + + + EXTTRIGIE + External trigger valid edge Interrupt + Enable + 2 + 1 + + + ARRMIE + Autoreload match Interrupt + Enable + 1 + 1 + + + CMPMIE + Compare match Interrupt + Enable + 0 + 1 + + + + + CFGR + CFGR + Configuration Register + 0xC + 0x20 + read-write + 0x00000000 + + + ENC + Encoder mode enable + 24 + 1 + + + COUNTMODE + counter mode enabled + 23 + 1 + + + PRELOAD + Registers update mode + 22 + 1 + + + WAVPOL + Waveform shape polarity + 21 + 1 + + + WAVE + Waveform shape + 20 + 1 + + + TIMOUT + Timeout enable + 19 + 1 + + + TRIGEN + Trigger enable and + polarity + 17 + 2 + + + TRIGSEL + Trigger selector + 13 + 3 + + + PRESC + Clock prescaler + 9 + 3 + + + TRGFLT + Configurable digital filter for + trigger + 6 + 2 + + + CKFLT + Configurable digital filter for external + clock + 3 + 2 + + + CKPOL + Clock Polarity + 1 + 2 + + + CKSEL + Clock selector + 0 + 1 + + + + + CR + CR + Control Register + 0x10 + 0x20 + read-write + 0x00000000 + + + ENABLE + LPTIM Enable + 0 + 1 + + + SNGSTRT + LPTIM start in single mode + 1 + 1 + + + CNTSTRT + Timer start in continuous + mode + 2 + 1 + + + COUNTRST + Counter reset + 3 + 1 + + + RSTARE + Reset after read enable + 4 + 1 + + + + + CMP + CMP + Compare Register + 0x14 + 0x20 + read-write + 0x00000000 + + + CMP + Compare value + 0 + 16 + + + + + ARR + ARR + Autoreload Register + 0x18 + 0x20 + read-write + 0x00000001 + + + ARR + Auto reload value + 0 + 16 + + + + + CNT + CNT + Counter Register + 0x1C + 0x20 + read-only + 0x00000000 + + + CNT + Counter value + 0 + 16 + + + + + CFGR2 + CFGR2 + LPTIM configuration register 2 + 0x24 + 0x20 + read-write + 0x00000000 + + + IN1SEL + LPTIM Input 1 selection + 0 + 2 + + + IN2SEL + LPTIM Input 2 selection + 4 + 2 + + + + + + + LPTIM2 + 0x58002400 + + LPTIM2 + LPTIM2 timer interrupt + 138 + + + + LPTIM3 + Low power timer + LPTIM + 0x58002800 + + 0x0 + 0x400 + registers + + + LPTIM3 + LPTIM2 timer interrupt + 139 + + + + ISR + ISR + Interrupt and Status Register + 0x0 + 0x20 + read-only + 0x00000000 + + + DOWN + Counter direction change up to + down + 6 + 1 + + + UP + Counter direction change down to + up + 5 + 1 + + + ARROK + Autoreload register update + OK + 4 + 1 + + + CMPOK + Compare register update OK + 3 + 1 + + + EXTTRIG + External trigger edge + event + 2 + 1 + + + ARRM + Autoreload match + 1 + 1 + + + CMPM + Compare match + 0 + 1 + + + + + ICR + ICR + Interrupt Clear Register + 0x4 + 0x20 + write-only + 0x00000000 + + + DOWNCF + Direction change to down Clear + Flag + 6 + 1 + + + UPCF + Direction change to UP Clear + Flag + 5 + 1 + + + ARROKCF + Autoreload register update OK Clear + Flag + 4 + 1 + + + CMPOKCF + Compare register update OK Clear + Flag + 3 + 1 + + + EXTTRIGCF + External trigger valid edge Clear + Flag + 2 + 1 + + + ARRMCF + Autoreload match Clear + Flag + 1 + 1 + + + CMPMCF + compare match Clear Flag + 0 + 1 + + + + + IER + IER + Interrupt Enable Register + 0x8 + 0x20 + read-write + 0x00000000 + + + DOWNIE + Direction change to down Interrupt + Enable + 6 + 1 + + + UPIE + Direction change to UP Interrupt + Enable + 5 + 1 + + + ARROKIE + Autoreload register update OK Interrupt + Enable + 4 + 1 + + + CMPOKIE + Compare register update OK Interrupt + Enable + 3 + 1 + + + EXTTRIGIE + External trigger valid edge Interrupt + Enable + 2 + 1 + + + ARRMIE + Autoreload match Interrupt + Enable + 1 + 1 + + + CMPMIE + Compare match Interrupt + Enable + 0 + 1 + + + + + CFGR + CFGR + Configuration Register + 0xC + 0x20 + read-write + 0x00000000 + + + ENC + Encoder mode enable + 24 + 1 + + + COUNTMODE + counter mode enabled + 23 + 1 + + + PRELOAD + Registers update mode + 22 + 1 + + + WAVPOL + Waveform shape polarity + 21 + 1 + + + WAVE + Waveform shape + 20 + 1 + + + TIMOUT + Timeout enable + 19 + 1 + + + TRIGEN + Trigger enable and + polarity + 17 + 2 + + + TRIGSEL + Trigger selector + 13 + 3 + + + PRESC + Clock prescaler + 9 + 3 + + + TRGFLT + Configurable digital filter for + trigger + 6 + 2 + + + CKFLT + Configurable digital filter for external + clock + 3 + 2 + + + CKPOL + Clock Polarity + 1 + 2 + + + CKSEL + Clock selector + 0 + 1 + + + + + CR + CR + Control Register + 0x10 + 0x20 + read-write + 0x00000000 + + + ENABLE + LPTIM Enable + 0 + 1 + + + SNGSTRT + LPTIM start in single mode + 1 + 1 + + + CNTSTRT + Timer start in continuous + mode + 2 + 1 + + + COUNTRST + Counter reset + 3 + 1 + + + RSTARE + Reset after read enable + 4 + 1 + + + + + CMP + CMP + Compare Register + 0x14 + 0x20 + read-write + 0x00000000 + + + CMP + Compare value + 0 + 16 + + + + + ARR + ARR + Autoreload Register + 0x18 + 0x20 + read-write + 0x00000001 + + + ARR + Auto reload value + 0 + 16 + + + + + CNT + CNT + Counter Register + 0x1C + 0x20 + read-only + 0x00000000 + + + CNT + Counter value + 0 + 16 + + + + + CFGR2 + CFGR2 + LPTIM configuration register 2 + 0x24 + 0x20 + read-write + 0x00000000 + + + IN1SEL + LPTIM Input 1 selection + 0 + 2 + + + + + + + LPTIM4 + 0x58002C00 + + ETH_WKUP + Ethernet wakeup through EXTI + 62 + + + LPTIM4 + LPTIM2 timer interrupt + 140 + + + + LPTIM5 + 0x58003000 + + LPTIM5 + LPTIM2 timer interrupt + 141 + + + + LPUART1 + LPUART1 + LPUART + 0x58000C00 + + 0x0 + 0x400 + registers + + + LPUART + LPUART global interrupt + 142 + + + + CR1 + CR1 + Control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + RXFFIE + RXFIFO Full interrupt + enable + 31 + 1 + + + TXFEIE + TXFIFO empty interrupt + enable + 30 + 1 + + + FIFOEN + FIFO mode enable + 29 + 1 + + + M1 + Word length + 28 + 1 + + + DEAT + Driver Enable assertion + time + 21 + 5 + + + DEDT + Driver Enable deassertion + time + 16 + 5 + + + CMIE + Character match interrupt + enable + 14 + 1 + + + MME + Mute mode enable + 13 + 1 + + + M0 + Word length + 12 + 1 + + + WAKE + Receiver wakeup method + 11 + 1 + + + PCE + Parity control enable + 10 + 1 + + + PS + Parity selection + 9 + 1 + + + PEIE + PE interrupt enable + 8 + 1 + + + TXEIE + interrupt enable + 7 + 1 + + + TCIE + Transmission complete interrupt + enable + 6 + 1 + + + RXNEIE + RXNE interrupt enable + 5 + 1 + + + IDLEIE + IDLE interrupt enable + 4 + 1 + + + TE + Transmitter enable + 3 + 1 + + + RE + Receiver enable + 2 + 1 + + + UESM + USART enable in Stop mode + 1 + 1 + + + UE + USART enable + 0 + 1 + + + + + CR2 + CR2 + Control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + ADD + Address of the USART node + 24 + 8 + + + MSBFIRST + Most significant bit first + 19 + 1 + + + DATAINV + Binary data inversion + 18 + 1 + + + TXINV + TX pin active level + inversion + 17 + 1 + + + RXINV + RX pin active level + inversion + 16 + 1 + + + SWAP + Swap TX/RX pins + 15 + 1 + + + STOP + STOP bits + 12 + 2 + + + ADDM7 + 7-bit Address Detection/4-bit Address + Detection + 4 + 1 + + + + + CR3 + CR3 + Control register 3 + 0x8 + 0x20 + read-write + 0x0000 + + + TXFTCFG + TXFIFO threshold + configuration + 29 + 3 + + + RXFTIE + RXFIFO threshold interrupt + enable + 28 + 1 + + + RXFTCFG + Receive FIFO threshold + configuration + 25 + 3 + + + TXFTIE + TXFIFO threshold interrupt + enable + 23 + 1 + + + WUFIE + Wakeup from Stop mode interrupt + enable + 22 + 1 + + + WUS + Wakeup from Stop mode interrupt flag + selection + 20 + 2 + + + DEP + Driver enable polarity + selection + 15 + 1 + + + DEM + Driver enable mode + 14 + 1 + + + DDRE + DMA Disable on Reception + Error + 13 + 1 + + + OVRDIS + Overrun Disable + 12 + 1 + + + CTSIE + CTS interrupt enable + 10 + 1 + + + CTSE + CTS enable + 9 + 1 + + + RTSE + RTS enable + 8 + 1 + + + DMAT + DMA enable transmitter + 7 + 1 + + + DMAR + DMA enable receiver + 6 + 1 + + + HDSEL + Half-duplex selection + 3 + 1 + + + EIE + Error interrupt enable + 0 + 1 + + + + + BRR + BRR + Baud rate register + 0xC + 0x20 + read-write + 0x0000 + + + BRR + BRR + 0 + 20 + + + + + GTPR + GTPR + Guard time and prescaler + register + 0x10 + 0x20 + read-write + 0x0000 + + + GT + Guard time value + 8 + 8 + + + PSC + Prescaler value + 0 + 8 + + + + + RTOR + RTOR + Receiver timeout register + 0x14 + 0x20 + read-write + 0x0000 + + + BLEN + Block Length + 24 + 8 + + + RTO + Receiver timeout value + 0 + 24 + + + + + RQR + RQR + Request register + 0x18 + 0x20 + write-only + 0x0000 + + + TXFRQ + Transmit data flush + request + 4 + 1 + + + RXFRQ + Receive data flush request + 3 + 1 + + + MMRQ + Mute mode request + 2 + 1 + + + SBKRQ + Send break request + 1 + 1 + + + ABRRQ + Auto baud rate request + 0 + 1 + + + + + ISR + ISR + Interrupt & status + register + 0x1C + 0x20 + read-only + 0x00C0 + + + TXFT + TXFIFO threshold flag + 27 + 1 + + + RXFT + RXFIFO threshold flag + 26 + 1 + + + RXFF + RXFIFO Full + 24 + 1 + + + TXFE + TXFIFO Empty + 23 + 1 + + + REACK + REACK + 22 + 1 + + + TEACK + TEACK + 21 + 1 + + + WUF + WUF + 20 + 1 + + + RWU + RWU + 19 + 1 + + + SBKF + SBKF + 18 + 1 + + + CMF + CMF + 17 + 1 + + + BUSY + BUSY + 16 + 1 + + + CTS + CTS + 10 + 1 + + + CTSIF + CTSIF + 9 + 1 + + + TXE + TXE + 7 + 1 + + + TC + TC + 6 + 1 + + + RXNE + RXNE + 5 + 1 + + + IDLE + IDLE + 4 + 1 + + + ORE + ORE + 3 + 1 + + + NE + NE + 2 + 1 + + + FE + FE + 1 + 1 + + + PE + PE + 0 + 1 + + + + + ICR + ICR + Interrupt flag clear register + 0x20 + 0x20 + write-only + 0x0000 + + + WUCF + Wakeup from Stop mode clear + flag + 20 + 1 + + + CMCF + Character match clear flag + 17 + 1 + + + CTSCF + CTS clear flag + 9 + 1 + + + TCCF + Transmission complete clear + flag + 6 + 1 + + + IDLECF + Idle line detected clear + flag + 4 + 1 + + + ORECF + Overrun error clear flag + 3 + 1 + + + NCF + Noise detected clear flag + 2 + 1 + + + FECF + Framing error clear flag + 1 + 1 + + + PECF + Parity error clear flag + 0 + 1 + + + + + RDR + RDR + Receive data register + 0x24 + 0x20 + read-only + 0x0000 + + + RDR + Receive data value + 0 + 9 + + + + + TDR + TDR + Transmit data register + 0x28 + 0x20 + read-write + 0x0000 + + + TDR + Transmit data value + 0 + 9 + + + + + PRESC + PRESC + Prescaler register + 0x2C + 0x20 + read-write + 0x0000 + + + PRESCALER + Clock prescaler + 0 + 4 + + + + + + + SYSCFG + System configuration controller + SYSCFG + 0x58000400 + + 0x0 + 0x400 + registers + + + + PMCR + PMCR + peripheral mode configuration + register + 0x4 + 0x20 + read-write + 0x00000000 + + + I2C1FMP + I2C1 Fm+ + 0 + 1 + + + I2C2FMP + I2C2 Fm+ + 1 + 1 + + + I2C3FMP + I2C3 Fm+ + 2 + 1 + + + I2C4FMP + I2C4 Fm+ + 3 + 1 + + + PB6FMP + PB(6) Fm+ + 4 + 1 + + + PB7FMP + PB(7) Fast Mode Plus + 5 + 1 + + + PB8FMP + PB(8) Fast Mode Plus + 6 + 1 + + + PB9FMP + PB(9) Fm+ + 7 + 1 + + + BOOSTE + Booster Enable + 8 + 1 + + + BOOSTVDDSEL + Analog switch supply voltage selection + 9 + 1 + + + EPIS + Ethernet PHY Interface + Selection + 21 + 3 + + + PA0SO + PA0 Switch Open + 24 + 1 + + + PA1SO + PA1 Switch Open + 25 + 1 + + + PC2SO + PC2 Switch Open + 26 + 1 + + + PC3SO + PC3 Switch Open + 27 + 1 + + + + + EXTICR1 + EXTICR1 + external interrupt configuration register + 1 + 0x8 + 0x20 + read-write + 0x0000 + + + EXTI3 + EXTI x configuration (x = 0 to + 3) + 12 + 4 + + + EXTI2 + EXTI x configuration (x = 0 to + 3) + 8 + 4 + + + EXTI1 + EXTI x configuration (x = 0 to + 3) + 4 + 4 + + + EXTI0 + EXTI x configuration (x = 0 to + 3) + 0 + 4 + + + + + EXTICR2 + EXTICR2 + external interrupt configuration register + 2 + 0xC + 0x20 + read-write + 0x0000 + + + EXTI7 + EXTI x configuration (x = 4 to + 7) + 12 + 4 + + + EXTI6 + EXTI x configuration (x = 4 to + 7) + 8 + 4 + + + EXTI5 + EXTI x configuration (x = 4 to + 7) + 4 + 4 + + + EXTI4 + EXTI x configuration (x = 4 to + 7) + 0 + 4 + + + + + EXTICR3 + EXTICR3 + external interrupt configuration register + 3 + 0x10 + 0x20 + read-write + 0x0000 + + + EXTI11 + EXTI x configuration (x = 8 to + 11) + 12 + 4 + + + EXTI10 + EXTI10 + 8 + 4 + + + EXTI9 + EXTI x configuration (x = 8 to + 11) + 4 + 4 + + + EXTI8 + EXTI x configuration (x = 8 to + 11) + 0 + 4 + + + + + EXTICR4 + EXTICR4 + external interrupt configuration register + 4 + 0x14 + 0x20 + read-write + 0x0000 + + + EXTI15 + EXTI x configuration (x = 12 to + 15) + 12 + 4 + + + EXTI14 + EXTI x configuration (x = 12 to + 15) + 8 + 4 + + + EXTI13 + EXTI x configuration (x = 12 to + 15) + 4 + 4 + + + EXTI12 + EXTI x configuration (x = 12 to + 15) + 0 + 4 + + + + + CCCSR + CCCSR + compensation cell control/status + register + 0x20 + 0x20 + read-write + 0x00000000 + + + EN + enable + 0 + 1 + + + CS + Code selection + 1 + 1 + + + READY + Compensation cell ready + flag + 8 + 1 + + + HSLV + High-speed at low-voltage + 16 + 1 + + + + + CCVR + CCVR + SYSCFG compensation cell value + register + 0x24 + 0x20 + read-only + 0x00000000 + + + NCV + NMOS compensation value + 0 + 4 + + + PCV + PMOS compensation value + 4 + 4 + + + + + CCCR + CCCR + SYSCFG compensation cell code + register + 0x28 + 0x20 + read-write + 0x00000000 + + + NCC + NMOS compensation code + 0 + 4 + + + PCC + PMOS compensation code + 4 + 4 + + + + + PWRCR + PWRCR + SYSCFG power control register + 0x2C + 0x20 + read-write + 0x00000000 + + + ODEN + Overdrive enable + 0 + 4 + + + + + + PKGR + PKGR + SYSCFG package register + 0x124 + 0x20 + read-only + 0x00000000 + + + PKG + Package + 0 + 4 + + + + + UR0 + UR0 + SYSCFG user register 0 + 0x300 + 0x20 + read-only + 0x00000000 + + + BKS + Bank Swap + 0 + 1 + + + RDP + Readout protection + 16 + 8 + + + + + UR2 + UR2 + SYSCFG user register 2 + 0x308 + 0x20 + read-write + 0x00000000 + + + BORH + BOR_LVL Brownout Reset Threshold + Level + 0 + 2 + + + BOOT_ADD0 + Boot Address 0 + 16 + 16 + + + + + UR3 + UR3 + SYSCFG user register 3 + 0x30C + 0x20 + read-write + 0x00000000 + + + BOOT_ADD1 + Boot Address 1 + 16 + 16 + + + + + UR4 + UR4 + SYSCFG user register 4 + 0x310 + 0x20 + read-only + 0x00000000 + + + MEPAD_1 + Mass Erase Protected Area Disabled for + bank 1 + 16 + 1 + + + + + UR5 + UR5 + SYSCFG user register 5 + 0x314 + 0x20 + read-only + 0x00000000 + + + MESAD_1 + Mass erase secured area disabled for + bank 1 + 0 + 1 + + + WRPN_1 + Write protection for flash bank + 1 + 16 + 8 + + + + + UR6 + UR6 + SYSCFG user register 6 + 0x318 + 0x20 + read-only + 0x00000000 + + + PA_BEG_1 + Protected area start address for bank + 1 + 0 + 12 + + + PA_END_1 + Protected area end address for bank + 1 + 16 + 12 + + + + + UR7 + UR7 + SYSCFG user register 7 + 0x31C + 0x20 + read-only + 0x00000000 + + + SA_BEG_1 + Secured area start address for bank + 1 + 0 + 12 + + + SA_END_1 + Secured area end address for bank + 1 + 16 + 12 + + + + + UR8 + UR8 + SYSCFG user register 8 + 0x320 + 0x20 + read-only + 0x00000000 + + + MEPAD_2 + Mass erase protected area disabled for + bank 2 + 0 + 1 + + + MESAD_2 + Mass erase secured area disabled for + bank 2 + 16 + 1 + + + + + UR9 + UR9 + SYSCFG user register 9 + 0x324 + 0x20 + read-only + 0x00000000 + + + WRPN_2 + Write protection for flash bank + 2 + 0 + 8 + + + PA_BEG_2 + Protected area start address for bank + 2 + 16 + 12 + + + + + UR10 + UR10 + SYSCFG user register 10 + 0x328 + 0x20 + read-only + 0x00000000 + + + PA_END_2 + Protected area end address for bank + 2 + 0 + 12 + + + SA_BEG_2 + Secured area start address for bank + 2 + 16 + 12 + + + + + UR11 + UR11 + SYSCFG user register 11 + 0x32C + 0x20 + read-only + 0x00000000 + + + SA_END_2 + Secured area end address for bank + 2 + 0 + 12 + + + IWDG1M + Independent Watchdog 1 + mode + 16 + 1 + + + + + UR12 + UR12 + SYSCFG user register 12 + 0x330 + 0x20 + read-only + 0x00000000 + + + SECURE + Secure mode + 16 + 1 + + + + + UR13 + UR13 + SYSCFG user register 13 + 0x334 + 0x20 + read-only + 0x00000000 + + + SDRS + Secured DTCM RAM Size + 0 + 2 + + + D1SBRST + D1 Standby reset + 16 + 1 + + + + + UR14 + UR14 + SYSCFG user register 14 + 0x338 + 0x20 + read-write + 0x00000000 + + + D1STPRST + D1 Stop Reset + 0 + 1 + + + + + UR15 + UR15 + SYSCFG user register 15 + 0x33C + 0x20 + read-only + 0x00000000 + + + FZIWDGSTB + Freeze independent watchdog in Standby + mode + 16 + 1 + + + + + UR16 + UR16 + SYSCFG user register 16 + 0x340 + 0x20 + read-only + 0x00000000 + + + FZIWDGSTP + Freeze independent watchdog in Stop + mode + 0 + 1 + + + PKP + Private key programmed + 16 + 1 + + + + + UR17 + UR17 + SYSCFG user register 17 + 0x344 + 0x20 + read-only + 0x00000000 + + + IO_HSLV + I/O high speed / low + voltage + 0 + 1 + + + + + + + EXTI + External interrupt/event + controller + EXTI + 0x58000000 + + 0x0 + 0x400 + registers + + + PVD_PVM + PVD through EXTI line + 1 + + + EXTI0 + EXTI Line 0 interrupt + 6 + + + EXTI1 + EXTI Line 1 interrupt + 7 + + + EXTI2 + EXTI Line 2 interrupt + 8 + + + EXTI3 + EXTI Line 3interrupt + 9 + + + EXTI4 + EXTI Line 4interrupt + 10 + + + EXTI9_5 + EXTI Line[9:5] interrupts + 23 + + + EXTI15_10 + EXTI Line[15:10] interrupts + 40 + + + RTC_ALARM + RTC alarms (A and B) + 41 + + + + RTSR1 + RTSR1 + EXTI rising trigger selection + register + 0x0 + 0x20 + read-write + 0x00000000 + + + TR0 + Rising trigger event configuration bit + of Configurable Event input + 0 + 1 + + + TR1 + Rising trigger event configuration bit + of Configurable Event input + 1 + 1 + + + TR2 + Rising trigger event configuration bit + of Configurable Event input + 2 + 1 + + + TR3 + Rising trigger event configuration bit + of Configurable Event input + 3 + 1 + + + TR4 + Rising trigger event configuration bit + of Configurable Event input + 4 + 1 + + + TR5 + Rising trigger event configuration bit + of Configurable Event input + 5 + 1 + + + TR6 + Rising trigger event configuration bit + of Configurable Event input + 6 + 1 + + + TR7 + Rising trigger event configuration bit + of Configurable Event input + 7 + 1 + + + TR8 + Rising trigger event configuration bit + of Configurable Event input + 8 + 1 + + + TR9 + Rising trigger event configuration bit + of Configurable Event input + 9 + 1 + + + TR10 + Rising trigger event configuration bit + of Configurable Event input + 10 + 1 + + + TR11 + Rising trigger event configuration bit + of Configurable Event input + 11 + 1 + + + TR12 + Rising trigger event configuration bit + of Configurable Event input + 12 + 1 + + + TR13 + Rising trigger event configuration bit + of Configurable Event input + 13 + 1 + + + TR14 + Rising trigger event configuration bit + of Configurable Event input + 14 + 1 + + + TR15 + Rising trigger event configuration bit + of Configurable Event input + 15 + 1 + + + TR16 + Rising trigger event configuration bit + of Configurable Event input + 16 + 1 + + + TR17 + Rising trigger event configuration bit + of Configurable Event input + 17 + 1 + + + TR18 + Rising trigger event configuration bit + of Configurable Event input + 18 + 1 + + + TR19 + Rising trigger event configuration bit + of Configurable Event input + 19 + 1 + + + TR20 + Rising trigger event configuration bit + of Configurable Event input + 20 + 1 + + + TR21 + Rising trigger event configuration bit + of Configurable Event input + 21 + 1 + + + + + FTSR1 + FTSR1 + EXTI falling trigger selection + register + 0x4 + 0x20 + read-write + 0x00000000 + + + TR0 + Rising trigger event configuration bit + of Configurable Event input + 0 + 1 + + + TR1 + Rising trigger event configuration bit + of Configurable Event input + 1 + 1 + + + TR2 + Rising trigger event configuration bit + of Configurable Event input + 2 + 1 + + + TR3 + Rising trigger event configuration bit + of Configurable Event input + 3 + 1 + + + TR4 + Rising trigger event configuration bit + of Configurable Event input + 4 + 1 + + + TR5 + Rising trigger event configuration bit + of Configurable Event input + 5 + 1 + + + TR6 + Rising trigger event configuration bit + of Configurable Event input + 6 + 1 + + + TR7 + Rising trigger event configuration bit + of Configurable Event input + 7 + 1 + + + TR8 + Rising trigger event configuration bit + of Configurable Event input + 8 + 1 + + + TR9 + Rising trigger event configuration bit + of Configurable Event input + 9 + 1 + + + TR10 + Rising trigger event configuration bit + of Configurable Event input + 10 + 1 + + + TR11 + Rising trigger event configuration bit + of Configurable Event input + 11 + 1 + + + TR12 + Rising trigger event configuration bit + of Configurable Event input + 12 + 1 + + + TR13 + Rising trigger event configuration bit + of Configurable Event input + 13 + 1 + + + TR14 + Rising trigger event configuration bit + of Configurable Event input + 14 + 1 + + + TR15 + Rising trigger event configuration bit + of Configurable Event input + 15 + 1 + + + TR16 + Rising trigger event configuration bit + of Configurable Event input + 16 + 1 + + + TR17 + Rising trigger event configuration bit + of Configurable Event input + 17 + 1 + + + TR18 + Rising trigger event configuration bit + of Configurable Event input + 18 + 1 + + + TR19 + Rising trigger event configuration bit + of Configurable Event input + 19 + 1 + + + TR20 + Rising trigger event configuration bit + of Configurable Event input + 20 + 1 + + + TR21 + Rising trigger event configuration bit + of Configurable Event input + 21 + 1 + + + + + SWIER1 + SWIER1 + EXTI software interrupt event + register + 0x8 + 0x20 + read-write + 0x00000000 + + + SWIER0 + Rising trigger event configuration bit + of Configurable Event input + 0 + 1 + + + SWIER1 + Rising trigger event configuration bit + of Configurable Event input + 1 + 1 + + + SWIER2 + Rising trigger event configuration bit + of Configurable Event input + 2 + 1 + + + SWIER3 + Rising trigger event configuration bit + of Configurable Event input + 3 + 1 + + + SWIER4 + Rising trigger event configuration bit + of Configurable Event input + 4 + 1 + + + SWIER5 + Rising trigger event configuration bit + of Configurable Event input + 5 + 1 + + + SWIER6 + Rising trigger event configuration bit + of Configurable Event input + 6 + 1 + + + SWIER7 + Rising trigger event configuration bit + of Configurable Event input + 7 + 1 + + + SWIER8 + Rising trigger event configuration bit + of Configurable Event input + 8 + 1 + + + SWIER9 + Rising trigger event configuration bit + of Configurable Event input + 9 + 1 + + + SWIER10 + Rising trigger event configuration bit + of Configurable Event input + 10 + 1 + + + SWIER11 + Rising trigger event configuration bit + of Configurable Event input + 11 + 1 + + + SWIER12 + Rising trigger event configuration bit + of Configurable Event input + 12 + 1 + + + SWIER13 + Rising trigger event configuration bit + of Configurable Event input + 13 + 1 + + + SWIER14 + Rising trigger event configuration bit + of Configurable Event input + 14 + 1 + + + SWIER15 + Rising trigger event configuration bit + of Configurable Event input + 15 + 1 + + + SWIER16 + Rising trigger event configuration bit + of Configurable Event input + 16 + 1 + + + SWIER17 + Rising trigger event configuration bit + of Configurable Event input + 17 + 1 + + + SWIER18 + Rising trigger event configuration bit + of Configurable Event input + 18 + 1 + + + SWIER19 + Rising trigger event configuration bit + of Configurable Event input + 19 + 1 + + + SWIER20 + Rising trigger event configuration bit + of Configurable Event input + 20 + 1 + + + SWIER21 + Rising trigger event configuration bit + of Configurable Event input + 21 + 1 + + + + + D3PMR1 + D3PMR1 + EXTI D3 pending mask register + 0xC + 0x20 + read-write + 0x00000000 + + + MR0 + Rising trigger event configuration bit + of Configurable Event input + 0 + 1 + + + MR1 + Rising trigger event configuration bit + of Configurable Event input + 1 + 1 + + + MR2 + Rising trigger event configuration bit + of Configurable Event input + 2 + 1 + + + MR3 + Rising trigger event configuration bit + of Configurable Event input + 3 + 1 + + + MR4 + Rising trigger event configuration bit + of Configurable Event input + 4 + 1 + + + MR5 + Rising trigger event configuration bit + of Configurable Event input + 5 + 1 + + + MR6 + Rising trigger event configuration bit + of Configurable Event input + 6 + 1 + + + MR7 + Rising trigger event configuration bit + of Configurable Event input + 7 + 1 + + + MR8 + Rising trigger event configuration bit + of Configurable Event input + 8 + 1 + + + MR9 + Rising trigger event configuration bit + of Configurable Event input + 9 + 1 + + + MR10 + Rising trigger event configuration bit + of Configurable Event input + 10 + 1 + + + MR11 + Rising trigger event configuration bit + of Configurable Event input + 11 + 1 + + + MR12 + Rising trigger event configuration bit + of Configurable Event input + 12 + 1 + + + MR13 + Rising trigger event configuration bit + of Configurable Event input + 13 + 1 + + + MR14 + Rising trigger event configuration bit + of Configurable Event input + 14 + 1 + + + MR15 + Rising trigger event configuration bit + of Configurable Event input + 15 + 1 + + + MR19 + Rising trigger event configuration bit + of Configurable Event input + 19 + 1 + + + MR20 + Rising trigger event configuration bit + of Configurable Event input + 20 + 1 + + + MR21 + Rising trigger event configuration bit + of Configurable Event input + 21 + 1 + + + MR25 + Rising trigger event configuration bit + of Configurable Event input + 25 + 1 + + + + + D3PCR1L + D3PCR1L + EXTI D3 pending clear selection register + low + 0x10 + 0x20 + read-write + 0x00000000 + + + PCS0 + D3 Pending request clear input signal + selection on Event input x = truncate + (n/2) + 0 + 2 + + + PCS1 + D3 Pending request clear input signal + selection on Event input x = truncate + (n/2) + 2 + 2 + + + PCS2 + D3 Pending request clear input signal + selection on Event input x = truncate + (n/2) + 4 + 2 + + + PCS3 + D3 Pending request clear input signal + selection on Event input x = truncate + (n/2) + 6 + 2 + + + PCS4 + D3 Pending request clear input signal + selection on Event input x = truncate + (n/2) + 8 + 2 + + + PCS5 + D3 Pending request clear input signal + selection on Event input x = truncate + (n/2) + 10 + 2 + + + PCS6 + D3 Pending request clear input signal + selection on Event input x = truncate + (n/2) + 12 + 2 + + + PCS7 + D3 Pending request clear input signal + selection on Event input x = truncate + (n/2) + 14 + 2 + + + PCS8 + D3 Pending request clear input signal + selection on Event input x = truncate + (n/2) + 16 + 2 + + + PCS9 + D3 Pending request clear input signal + selection on Event input x = truncate + (n/2) + 18 + 2 + + + PCS10 + D3 Pending request clear input signal + selection on Event input x = truncate + (n/2) + 20 + 2 + + + PCS11 + D3 Pending request clear input signal + selection on Event input x = truncate + (n/2) + 22 + 2 + + + PCS12 + D3 Pending request clear input signal + selection on Event input x = truncate + (n/2) + 24 + 2 + + + PCS13 + D3 Pending request clear input signal + selection on Event input x = truncate + (n/2) + 26 + 2 + + + PCS14 + D3 Pending request clear input signal + selection on Event input x = truncate + (n/2) + 28 + 2 + + + PCS15 + D3 Pending request clear input signal + selection on Event input x = truncate + (n/2) + 30 + 2 + + + + + D3PCR1H + D3PCR1H + EXTI D3 pending clear selection register + high + 0x14 + 0x20 + read-write + 0x00000000 + + + PCS19 + D3 Pending request clear input signal + selection on Event input x = truncate + ((n+32)/2) + 6 + 2 + + + PCS20 + D3 Pending request clear input signal + selection on Event input x = truncate + ((n+32)/2) + 8 + 2 + + + PCS21 + D3 Pending request clear input signal + selection on Event input x = truncate + ((n+32)/2) + 10 + 2 + + + PCS25 + D3 Pending request clear input signal + selection on Event input x = truncate + ((n+32)/2) + 18 + 2 + + + + + RTSR2 + RTSR2 + EXTI rising trigger selection + register + 0x20 + 0x20 + read-write + 0x00000000 + + + TR49 + Rising trigger event configuration bit + of Configurable Event input x+32 + 17 + 1 + + + TR51 + Rising trigger event configuration bit + of Configurable Event input x+32 + 19 + 1 + + + + + FTSR2 + FTSR2 + EXTI falling trigger selection + register + 0x24 + 0x20 + read-write + 0x00000000 + + + TR49 + Falling trigger event configuration bit + of Configurable Event input x+32 + 17 + 1 + + + TR51 + Falling trigger event configuration bit + of Configurable Event input x+32 + 19 + 1 + + + + + SWIER2 + SWIER2 + EXTI software interrupt event + register + 0x28 + 0x20 + read-write + 0x00000000 + + + SWIER49 + Software interrupt on line + x+32 + 17 + 1 + + + SWIER51 + Software interrupt on line + x+32 + 19 + 1 + + + + + D3PMR2 + D3PMR2 + EXTI D3 pending mask register + 0x2C + 0x20 + read-write + 0x00000000 + + + MR34 + D3 Pending Mask on Event input + x+32 + 2 + 1 + + + MR35 + D3 Pending Mask on Event input + x+32 + 3 + 1 + + + MR41 + D3 Pending Mask on Event input + x+32 + 9 + 1 + + + MR48 + D3 Pending Mask on Event input + x+32 + 16 + 1 + + + MR49 + D3 Pending Mask on Event input + x+32 + 17 + 1 + + + MR50 + D3 Pending Mask on Event input + x+32 + 18 + 1 + + + MR51 + D3 Pending Mask on Event input + x+32 + 19 + 1 + + + MR52 + D3 Pending Mask on Event input + x+32 + 20 + 1 + + + MR53 + D3 Pending Mask on Event input + x+32 + 21 + 1 + + + + + D3PCR2L + D3PCR2L + EXTI D3 pending clear selection register + low + 0x30 + 0x20 + read-write + 0x00000000 + + + PCS35 + D3 Pending request clear input signal + selection on Event input x = truncate + ((n+64)/2) + 6 + 2 + + + PCS34 + D3 Pending request clear input signal + selection on Event input x = truncate + ((n+64)/2) + 4 + 2 + + + PCS41 + D3 Pending request clear input signal + selection on Event input x = truncate + ((n+64)/2) + 18 + 2 + + + + + D3PCR2H + D3PCR2H + EXTI D3 pending clear selection register + high + 0x34 + 0x20 + read-write + 0x00000000 + + + PCS48 + Pending request clear input signal + selection on Event input x= truncate + ((n+96)/2) + 0 + 2 + + + PCS49 + Pending request clear input signal + selection on Event input x= truncate + ((n+96)/2) + 2 + 2 + + + PCS50 + Pending request clear input signal + selection on Event input x= truncate + ((n+96)/2) + 4 + 2 + + + PCS51 + Pending request clear input signal + selection on Event input x= truncate + ((n+96)/2) + 6 + 2 + + + PCS52 + Pending request clear input signal + selection on Event input x= truncate + ((n+96)/2) + 8 + 2 + + + PCS53 + Pending request clear input signal + selection on Event input x= truncate + ((n+96)/2) + 10 + 2 + + + + + RTSR3 + RTSR3 + EXTI rising trigger selection + register + 0x40 + 0x20 + read-write + 0x00000000 + + + TR82 + Rising trigger event configuration bit + of Configurable Event input x+64 + 18 + 1 + + + TR84 + Rising trigger event configuration bit + of Configurable Event input x+64 + 20 + 1 + + + TR85 + Rising trigger event configuration bit + of Configurable Event input x+64 + 21 + 1 + + + TR86 + Rising trigger event configuration bit + of Configurable Event input x+64 + 22 + 1 + + + + + FTSR3 + FTSR3 + EXTI falling trigger selection + register + 0x44 + 0x20 + read-write + 0x00000000 + + + TR82 + Falling trigger event configuration bit + of Configurable Event input x+64 + 18 + 1 + + + TR84 + Falling trigger event configuration bit + of Configurable Event input x+64 + 20 + 1 + + + TR85 + Falling trigger event configuration bit + of Configurable Event input x+64 + 21 + 1 + + + TR86 + Falling trigger event configuration bit + of Configurable Event input x+64 + 22 + 1 + + + + + SWIER3 + SWIER3 + EXTI software interrupt event + register + 0x48 + 0x20 + read-write + 0x00000000 + + + SWIER82 + Software interrupt on line + x+64 + 18 + 1 + + + SWIER84 + Software interrupt on line + x+64 + 20 + 1 + + + SWIER85 + Software interrupt on line + x+64 + 21 + 1 + + + SWIER86 + Software interrupt on line + x+64 + 22 + 1 + + + + + D3PMR3 + D3PMR3 + EXTI D3 pending mask register + 0x4C + 0x20 + read-write + 0x00000000 + + + MR88 + D3 Pending Mask on Event input + x+64 + 24 + 1 + + + + + D3PCR3H + D3PCR3H + EXTI D3 pending clear selection register + high + 0x54 + 0x20 + read-write + 0x00000000 + + + PCS88 + D3 Pending request clear input signal + selection on Event input x= truncate + N+160/2 + 18 + 2 + + + + + CPUIMR1 + CPUIMR1 + EXTI interrupt mask register + 0x80 + 0x20 + read-write + 0xFFC00000 + + + MR0 + Rising trigger event configuration bit + of Configurable Event input + 0 + 1 + + + MR1 + Rising trigger event configuration bit + of Configurable Event input + 1 + 1 + + + MR2 + Rising trigger event configuration bit + of Configurable Event input + 2 + 1 + + + MR3 + Rising trigger event configuration bit + of Configurable Event input + 3 + 1 + + + MR4 + Rising trigger event configuration bit + of Configurable Event input + 4 + 1 + + + MR5 + Rising trigger event configuration bit + of Configurable Event input + 5 + 1 + + + MR6 + Rising trigger event configuration bit + of Configurable Event input + 6 + 1 + + + MR7 + Rising trigger event configuration bit + of Configurable Event input + 7 + 1 + + + MR8 + Rising trigger event configuration bit + of Configurable Event input + 8 + 1 + + + MR9 + Rising trigger event configuration bit + of Configurable Event input + 9 + 1 + + + MR10 + Rising trigger event configuration bit + of Configurable Event input + 10 + 1 + + + MR11 + Rising trigger event configuration bit + of Configurable Event input + 11 + 1 + + + MR12 + Rising trigger event configuration bit + of Configurable Event input + 12 + 1 + + + MR13 + Rising trigger event configuration bit + of Configurable Event input + 13 + 1 + + + MR14 + Rising trigger event configuration bit + of Configurable Event input + 14 + 1 + + + MR15 + Rising trigger event configuration bit + of Configurable Event input + 15 + 1 + + + MR16 + Rising trigger event configuration bit + of Configurable Event input + 16 + 1 + + + MR17 + Rising trigger event configuration bit + of Configurable Event input + 17 + 1 + + + MR18 + Rising trigger event configuration bit + of Configurable Event input + 18 + 1 + + + MR19 + Rising trigger event configuration bit + of Configurable Event input + 19 + 1 + + + MR20 + Rising trigger event configuration bit + of Configurable Event input + 20 + 1 + + + MR21 + Rising trigger event configuration bit + of Configurable Event input + 21 + 1 + + + MR22 + Rising trigger event configuration bit + of Configurable Event input + 22 + 1 + + + MR23 + Rising trigger event configuration bit + of Configurable Event input + 23 + 1 + + + MR24 + Rising trigger event configuration bit + of Configurable Event input + 24 + 1 + + + MR25 + Rising trigger event configuration bit + of Configurable Event input + 25 + 1 + + + MR26 + Rising trigger event configuration bit + of Configurable Event input + 26 + 1 + + + MR27 + Rising trigger event configuration bit + of Configurable Event input + 27 + 1 + + + MR28 + Rising trigger event configuration bit + of Configurable Event input + 28 + 1 + + + MR29 + Rising trigger event configuration bit + of Configurable Event input + 29 + 1 + + + MR30 + Rising trigger event configuration bit + of Configurable Event input + 30 + 1 + + + MR31 + Rising trigger event configuration bit + of Configurable Event input + 31 + 1 + + + + + CPUEMR1 + CPUEMR1 + EXTI event mask register + 0x84 + 0x20 + read-write + 0x00000000 + + + MR0 + CPU Event mask on Event input + x + 0 + 1 + + + MR1 + CPU Event mask on Event input + x + 1 + 1 + + + MR2 + CPU Event mask on Event input + x + 2 + 1 + + + MR3 + CPU Event mask on Event input + x + 3 + 1 + + + MR4 + CPU Event mask on Event input + x + 4 + 1 + + + MR5 + CPU Event mask on Event input + x + 5 + 1 + + + MR6 + CPU Event mask on Event input + x + 6 + 1 + + + MR7 + CPU Event mask on Event input + x + 7 + 1 + + + MR8 + CPU Event mask on Event input + x + 8 + 1 + + + MR9 + CPU Event mask on Event input + x + 9 + 1 + + + MR10 + CPU Event mask on Event input + x + 10 + 1 + + + MR11 + CPU Event mask on Event input + x + 11 + 1 + + + MR12 + CPU Event mask on Event input + x + 12 + 1 + + + MR13 + CPU Event mask on Event input + x + 13 + 1 + + + MR14 + CPU Event mask on Event input + x + 14 + 1 + + + MR15 + CPU Event mask on Event input + x + 15 + 1 + + + MR16 + CPU Event mask on Event input + x + 16 + 1 + + + MR17 + CPU Event mask on Event input + x + 17 + 1 + + + MR18 + CPU Event mask on Event input + x + 18 + 1 + + + MR19 + CPU Event mask on Event input + x + 19 + 1 + + + MR20 + CPU Event mask on Event input + x + 20 + 1 + + + MR21 + CPU Event mask on Event input + x + 21 + 1 + + + MR22 + CPU Event mask on Event input + x + 22 + 1 + + + MR23 + CPU Event mask on Event input + x + 23 + 1 + + + MR24 + CPU Event mask on Event input + x + 24 + 1 + + + MR25 + CPU Event mask on Event input + x + 25 + 1 + + + MR26 + CPU Event mask on Event input + x + 26 + 1 + + + MR27 + CPU Event mask on Event input + x + 27 + 1 + + + MR28 + CPU Event mask on Event input + x + 28 + 1 + + + MR29 + CPU Event mask on Event input + x + 29 + 1 + + + MR30 + CPU Event mask on Event input + x + 30 + 1 + + + MR31 + CPU Event mask on Event input + x + 31 + 1 + + + + + CPUPR1 + CPUPR1 + EXTI pending register + 0x88 + 0x20 + read-write + 0x00000000 + + + PR0 + CPU Event mask on Event input + x + 0 + 1 + + + PR1 + CPU Event mask on Event input + x + 1 + 1 + + + PR2 + CPU Event mask on Event input + x + 2 + 1 + + + PR3 + CPU Event mask on Event input + x + 3 + 1 + + + PR4 + CPU Event mask on Event input + x + 4 + 1 + + + PR5 + CPU Event mask on Event input + x + 5 + 1 + + + PR6 + CPU Event mask on Event input + x + 6 + 1 + + + PR7 + CPU Event mask on Event input + x + 7 + 1 + + + PR8 + CPU Event mask on Event input + x + 8 + 1 + + + PR9 + CPU Event mask on Event input + x + 9 + 1 + + + PR10 + CPU Event mask on Event input + x + 10 + 1 + + + PR11 + CPU Event mask on Event input + x + 11 + 1 + + + PR12 + CPU Event mask on Event input + x + 12 + 1 + + + PR13 + CPU Event mask on Event input + x + 13 + 1 + + + PR14 + CPU Event mask on Event input + x + 14 + 1 + + + PR15 + CPU Event mask on Event input + x + 15 + 1 + + + PR16 + CPU Event mask on Event input + x + 16 + 1 + + + PR17 + CPU Event mask on Event input + x + 17 + 1 + + + PR18 + CPU Event mask on Event input + x + 18 + 1 + + + PR19 + CPU Event mask on Event input + x + 19 + 1 + + + PR20 + CPU Event mask on Event input + x + 20 + 1 + + + PR21 + CPU Event mask on Event input + x + 21 + 1 + + + + + CPUIMR2 + CPUIMR2 + EXTI interrupt mask register + 0x90 + 0x20 + read-write + 0x00000000 + + + MR0 + CPU Interrupt Mask on Direct Event input + x+32 + 0 + 1 + + + MR1 + CPU Interrupt Mask on Direct Event input + x+32 + 1 + 1 + + + MR2 + CPU Interrupt Mask on Direct Event input + x+32 + 2 + 1 + + + MR3 + CPU Interrupt Mask on Direct Event input + x+32 + 3 + 1 + + + MR4 + CPU Interrupt Mask on Direct Event input + x+32 + 4 + 1 + + + MR5 + CPU Interrupt Mask on Direct Event input + x+32 + 5 + 1 + + + MR6 + CPU Interrupt Mask on Direct Event input + x+32 + 6 + 1 + + + MR7 + CPU Interrupt Mask on Direct Event input + x+32 + 7 + 1 + + + MR8 + CPU Interrupt Mask on Direct Event input + x+32 + 8 + 1 + + + MR9 + CPU Interrupt Mask on Direct Event input + x+32 + 9 + 1 + + + MR10 + CPU Interrupt Mask on Direct Event input + x+32 + 10 + 1 + + + MR11 + CPU Interrupt Mask on Direct Event input + x+32 + 11 + 1 + + + MR12 + CPU Interrupt Mask on Direct Event input + x+32 + 12 + 1 + + + MR14 + CPU Interrupt Mask on Direct Event input + x+32 + 14 + 1 + + + MR15 + CPU Interrupt Mask on Direct Event input + x+32 + 15 + 1 + + + MR16 + CPU Interrupt Mask on Direct Event input + x+32 + 16 + 1 + + + MR17 + CPU Interrupt Mask on Direct Event input + x+32 + 17 + 1 + + + MR18 + CPU Interrupt Mask on Direct Event input + x+32 + 18 + 1 + + + MR19 + CPU Interrupt Mask on Direct Event input + x+32 + 19 + 1 + + + MR20 + CPU Interrupt Mask on Direct Event input + x+32 + 20 + 1 + + + MR21 + CPU Interrupt Mask on Direct Event input + x+32 + 21 + 1 + + + MR22 + CPU Interrupt Mask on Direct Event input + x+32 + 22 + 1 + + + MR23 + CPU Interrupt Mask on Direct Event input + x+32 + 23 + 1 + + + MR24 + CPU Interrupt Mask on Direct Event input + x+32 + 24 + 1 + + + MR25 + CPU Interrupt Mask on Direct Event input + x+32 + 25 + 1 + + + MR26 + CPU Interrupt Mask on Direct Event input + x+32 + 26 + 1 + + + MR27 + CPU Interrupt Mask on Direct Event input + x+32 + 27 + 1 + + + MR28 + CPU Interrupt Mask on Direct Event input + x+32 + 28 + 1 + + + MR29 + CPU Interrupt Mask on Direct Event input + x+32 + 29 + 1 + + + MR30 + CPU Interrupt Mask on Direct Event input + x+32 + 30 + 1 + + + MR31 + CPU Interrupt Mask on Direct Event input + x+32 + 31 + 1 + + + + + CPUEMR2 + CPUEMR2 + EXTI event mask register + 0x94 + 0x20 + read-write + 0x00000000 + + + MR32 + CPU Interrupt Mask on Direct Event input + x+32 + 0 + 1 + + + MR33 + CPU Interrupt Mask on Direct Event input + x+32 + 1 + 1 + + + MR34 + CPU Interrupt Mask on Direct Event input + x+32 + 2 + 1 + + + MR35 + CPU Interrupt Mask on Direct Event input + x+32 + 3 + 1 + + + MR36 + CPU Interrupt Mask on Direct Event input + x+32 + 4 + 1 + + + MR37 + CPU Interrupt Mask on Direct Event input + x+32 + 5 + 1 + + + MR38 + CPU Interrupt Mask on Direct Event input + x+32 + 6 + 1 + + + MR39 + CPU Interrupt Mask on Direct Event input + x+32 + 7 + 1 + + + MR40 + CPU Interrupt Mask on Direct Event input + x+32 + 8 + 1 + + + MR41 + CPU Interrupt Mask on Direct Event input + x+32 + 9 + 1 + + + MR42 + CPU Interrupt Mask on Direct Event input + x+32 + 10 + 1 + + + MR43 + CPU Interrupt Mask on Direct Event input + x+32 + 11 + 1 + + + MR44 + CPU Interrupt Mask on Direct Event input + x+32 + 12 + 1 + + + MR46 + CPU Interrupt Mask on Direct Event input + x+32 + 14 + 1 + + + MR47 + CPU Interrupt Mask on Direct Event input + x+32 + 15 + 1 + + + MR48 + CPU Interrupt Mask on Direct Event input + x+32 + 16 + 1 + + + MR49 + CPU Interrupt Mask on Direct Event input + x+32 + 17 + 1 + + + MR50 + CPU Interrupt Mask on Direct Event input + x+32 + 18 + 1 + + + MR51 + CPU Interrupt Mask on Direct Event input + x+32 + 19 + 1 + + + MR52 + CPU Interrupt Mask on Direct Event input + x+32 + 20 + 1 + + + MR53 + CPU Interrupt Mask on Direct Event input + x+32 + 21 + 1 + + + MR54 + CPU Interrupt Mask on Direct Event input + x+32 + 22 + 1 + + + MR55 + CPU Interrupt Mask on Direct Event input + x+32 + 23 + 1 + + + MR56 + CPU Interrupt Mask on Direct Event input + x+32 + 24 + 1 + + + MR57 + CPU Interrupt Mask on Direct Event input + x+32 + 25 + 1 + + + MR58 + CPU Interrupt Mask on Direct Event input + x+32 + 26 + 1 + + + MR59 + CPU Interrupt Mask on Direct Event input + x+32 + 27 + 1 + + + MR60 + CPU Interrupt Mask on Direct Event input + x+32 + 28 + 1 + + + MR61 + CPU Interrupt Mask on Direct Event input + x+32 + 29 + 1 + + + MR62 + CPU Interrupt Mask on Direct Event input + x+32 + 30 + 1 + + + MR63 + CPU Interrupt Mask on Direct Event input + x+32 + 31 + 1 + + + + + CPUPR2 + CPUPR2 + EXTI pending register + 0x98 + 0x20 + read-only + 0x00000000 + + + PR49 + Configurable event inputs x+32 Pending + bit + 17 + 1 + + + PR51 + Configurable event inputs x+32 Pending + bit + 19 + 1 + + + + + CPUIMR3 + CPUIMR3 + EXTI interrupt mask register + 0xA0 + 0x20 + read-only + 0x00000000 + + + MR64 + CPU Interrupt Mask on Direct Event input + x+64 + 0 + 1 + + + MR65 + CPU Interrupt Mask on Direct Event input + x+64 + 1 + 1 + + + MR66 + CPU Interrupt Mask on Direct Event input + x+64 + 2 + 1 + + + MR67 + CPU Interrupt Mask on Direct Event input + x+64 + 3 + 1 + + + MR68 + CPU Interrupt Mask on Direct Event input + x+64 + 4 + 1 + + + MR69 + CPU Interrupt Mask on Direct Event input + x+64 + 5 + 1 + + + MR70 + CPU Interrupt Mask on Direct Event input + x+64 + 6 + 1 + + + MR71 + CPU Interrupt Mask on Direct Event input + x+64 + 7 + 1 + + + MR72 + CPU Interrupt Mask on Direct Event input + x+64 + 8 + 1 + + + MR73 + CPU Interrupt Mask on Direct Event input + x+64 + 9 + 1 + + + MR74 + CPU Interrupt Mask on Direct Event input + x+64 + 10 + 1 + + + MR75 + CPU Interrupt Mask on Direct Event input + x+64 + 11 + 1 + + + MR76 + CPU Interrupt Mask on Direct Event input + x+64 + 12 + 1 + + + MR77 + CPU Interrupt Mask on Direct Event input + x+64 + 13 + 1 + + + MR78 + CPU Interrupt Mask on Direct Event input + x+64 + 14 + 1 + + + MR79 + CPU Interrupt Mask on Direct Event input + x+64 + 15 + 1 + + + MR80 + CPU Interrupt Mask on Direct Event input + x+64 + 16 + 1 + + + MR82 + CPU Interrupt Mask on Direct Event input + x+64 + 18 + 1 + + + MR84 + CPU Interrupt Mask on Direct Event input + x+64 + 20 + 1 + + + MR85 + CPU Interrupt Mask on Direct Event input + x+64 + 21 + 1 + + + MR86 + CPU Interrupt Mask on Direct Event input + x+64 + 22 + 1 + + + MR87 + CPU Interrupt Mask on Direct Event input + x+64 + 23 + 1 + + + MR88 + CPU Interrupt Mask on Direct Event input + x+64 + 24 + 1 + + + + + CPUEMR3 + CPUEMR3 + EXTI event mask register + 0xA4 + 0x20 + read-only + 0x00000000 + + + MR64 + CPU Event mask on Event input + x+64 + 0 + 1 + + + MR65 + CPU Event mask on Event input + x+64 + 1 + 1 + + + MR66 + CPU Event mask on Event input + x+64 + 2 + 1 + + + MR67 + CPU Event mask on Event input + x+64 + 3 + 1 + + + MR68 + CPU Event mask on Event input + x+64 + 4 + 1 + + + MR69 + CPU Event mask on Event input + x+64 + 5 + 1 + + + MR70 + CPU Event mask on Event input + x+64 + 6 + 1 + + + MR71 + CPU Event mask on Event input + x+64 + 7 + 1 + + + MR72 + CPU Event mask on Event input + x+64 + 8 + 1 + + + MR73 + CPU Event mask on Event input + x+64 + 9 + 1 + + + MR74 + CPU Event mask on Event input + x+64 + 10 + 1 + + + MR75 + CPU Event mask on Event input + x+64 + 11 + 1 + + + MR76 + CPU Event mask on Event input + x+64 + 12 + 1 + + + MR77 + CPU Event mask on Event input + x+64 + 13 + 1 + + + MR78 + CPU Event mask on Event input + x+64 + 14 + 1 + + + MR79 + CPU Event mask on Event input + x+64 + 15 + 1 + + + MR80 + CPU Event mask on Event input + x+64 + 16 + 1 + + + MR82 + CPU Event mask on Event input + x+64 + 18 + 1 + + + MR84 + CPU Event mask on Event input + x+64 + 20 + 1 + + + MR85 + CPU Event mask on Event input + x+64 + 21 + 1 + + + MR86 + CPU Event mask on Event input + x+64 + 22 + 1 + + + MR87 + CPU Event mask on Event input + x+64 + 23 + 1 + + + MR88 + CPU Event mask on Event input + x+64 + 24 + 1 + + + + + CPUPR3 + CPUPR3 + EXTI pending register + 0xA8 + 0x20 + read-only + 0x00000000 + + + PR82 + Configurable event inputs x+64 Pending + bit + 18 + 1 + + + PR84 + Configurable event inputs x+64 Pending + bit + 20 + 1 + + + PR85 + Configurable event inputs x+64 Pending + bit + 21 + 1 + + + PR86 + Configurable event inputs x+64 Pending + bit + 22 + 1 + + + + + + + DELAY_Block_SDMMC1 + DELAY_Block_SDMMC1 + DLYB + 0x52008000 + + 0x0 + 0x1000 + registers + + + WKUP + WKUP1 to WKUP6 pins + 149 + + + + CR + CR + DLYB control register + 0x0 + 0x20 + read-write + 0x00000000 + + + DEN + Delay block enable bit + 0 + 1 + + + SEN + Sampler length enable bit + 1 + 1 + + + + + CFGR + CFGR + DLYB configuration register + 0x4 + 0x20 + read-write + 0x00000000 + + + SEL + Select the phase for the Output + clock + 0 + 4 + + + UNIT + Delay Defines the delay of a Unit delay + cell + 8 + 7 + + + LNG + Delay line length value + 16 + 12 + + + LNGF + Length valid flag + 31 + 1 + + + + + + + DELAY_Block_QUADSPI + 0x52006000 + + + DELAY_Block_SDMMC2 + 0x48022800 + + + Flash + Flash + Flash + 0x52002000 + + 0x0 + 0x1000 + registers + + + FLASH + Flash memory + 4 + + + + ACR + ACR + Access control register + 0x0 + 0x20 + read-write + 0x00000600 + + + LATENCY + Read latency + 0 + 3 + + + WRHIGHFREQ + Flash signal delay + 4 + 2 + + + + + ACR_ + ACR_ + Access control register + 0x100 + 0x20 + read-write + 0x00000000 + + + LATENCY + Read latency + 0 + 3 + + + WRHIGHFREQ + Flash signal delay + 4 + 2 + + + + + KEYR1 + KEYR1 + FLASH key register for bank 1 + 0x4 + 0x20 + read-write + 0x00000000 + + + KEYR1 + Bank 1 access configuration unlock + key + 0 + 32 + + + + + OPTKEYR + OPTKEYR + FLASH option key register + 0x8 + 0x20 + read-write + 0x00000000 + + + OPTKEYR + Unlock key option bytes + 0 + 32 + + + + + OPTKEYR_ + OPTKEYR_ + FLASH option key register + 0x108 + 0x20 + read-write + 0x00000000 + + + OPTKEYR + Unlock key option bytes + 0 + 32 + + + + + CR1 + CR1 + FLASH control register for bank + 1 + 0xC + 0x20 + read-write + 0x00000000 + + + LOCK1 + Bank 1 configuration lock + bit + 0 + 1 + + + PG1 + Bank 1 program enable bit + 1 + 1 + + + SER1 + Bank 1 sector erase + request + 2 + 1 + + + BER1 + Bank 1 erase request + 3 + 1 + + + PSIZE1 + Bank 1 program size + 4 + 2 + + + FW1 + Bank 1 write forcing control + bit + 6 + 1 + + + START1 + Bank 1 bank or sector erase start + control bit + 7 + 1 + + + SNB1 + Bank 1 sector erase selection + number + 8 + 3 + + + CRC_EN + Bank 1 CRC control bit + 15 + 1 + + + EOPIE1 + Bank 1 end-of-program interrupt control + bit + 16 + 1 + + + WRPERRIE1 + Bank 1 write protection error interrupt + enable bit + 17 + 1 + + + PGSERRIE1 + Bank 1 programming sequence error + interrupt enable bit + 18 + 1 + + + STRBERRIE1 + Bank 1 strobe error interrupt enable + bit + 19 + 1 + + + INCERRIE1 + Bank 1 inconsistency error interrupt + enable bit + 21 + 1 + + + OPERRIE1 + Bank 1 write/erase error interrupt + enable bit + 22 + 1 + + + RDPERRIE1 + Bank 1 read protection error interrupt + enable bit + 23 + 1 + + + RDSERRIE1 + Bank 1 secure error interrupt enable + bit + 24 + 1 + + + SNECCERRIE1 + Bank 1 ECC single correction error + interrupt enable bit + 25 + 1 + + + DBECCERRIE1 + Bank 1 ECC double detection error + interrupt enable bit + 26 + 1 + + + CRCENDIE1 + Bank 1 end of CRC calculation interrupt + enable bit + 27 + 1 + + + + + SR1 + SR1 + FLASH status register for bank + 1 + 0x10 + 0x20 + read-write + 0x00000000 + + + BSY1 + Bank 1 ongoing program + flag + 0 + 1 + + + WBNE1 + Bank 1 write buffer not empty + flag + 1 + 1 + + + QW1 + Bank 1 wait queue flag + 2 + 1 + + + CRC_BUSY1 + Bank 1 CRC busy flag + 3 + 1 + + + EOP1 + Bank 1 end-of-program flag + 16 + 1 + + + WRPERR1 + Bank 1 write protection error + flag + 17 + 1 + + + PGSERR1 + Bank 1 programming sequence error + flag + 18 + 1 + + + STRBERR1 + Bank 1 strobe error flag + 19 + 1 + + + INCERR1 + Bank 1 inconsistency error + flag + 21 + 1 + + + OPERR1 + Bank 1 write/erase error + flag + 22 + 1 + + + RDPERR1 + Bank 1 read protection error + flag + 23 + 1 + + + RDSERR1 + Bank 1 secure error flag + 24 + 1 + + + SNECCERR11 + Bank 1 single correction error + flag + 25 + 1 + + + DBECCERR1 + Bank 1 ECC double detection error + flag + 26 + 1 + + + CRCEND1 + Bank 1 CRC-complete flag + 27 + 1 + + + + + CCR1 + CCR1 + FLASH clear control register for bank + 1 + 0x14 + 0x20 + read-write + 0x00000000 + + + CLR_EOP1 + Bank 1 EOP1 flag clear bit + 16 + 1 + + + CLR_WRPERR1 + Bank 1 WRPERR1 flag clear + bit + 17 + 1 + + + CLR_PGSERR1 + Bank 1 PGSERR1 flag clear + bi + 18 + 1 + + + CLR_STRBERR1 + Bank 1 STRBERR1 flag clear + bit + 19 + 1 + + + CLR_INCERR1 + Bank 1 INCERR1 flag clear + bit + 21 + 1 + + + CLR_OPERR1 + Bank 1 OPERR1 flag clear + bit + 22 + 1 + + + CLR_RDPERR1 + Bank 1 RDPERR1 flag clear + bit + 23 + 1 + + + CLR_RDSERR1 + Bank 1 RDSERR1 flag clear + bit + 24 + 1 + + + CLR_SNECCERR1 + Bank 1 SNECCERR1 flag clear + bit + 25 + 1 + + + CLR_DBECCERR1 + Bank 1 DBECCERR1 flag clear + bit + 26 + 1 + + + CLR_CRCEND1 + Bank 1 CRCEND1 flag clear + bit + 27 + 1 + + + + + OPTCR + OPTCR + FLASH option control register + 0x18 + 0x20 + read-write + 0x00000000 + + + OPTLOCK + FLASH_OPTCR lock option configuration + bit + 0 + 1 + + + OPTSTART + Option byte start change option + configuration bit + 1 + 1 + + + MER + Flash mass erase enable + bit + 4 + 1 + + + OPTCHANGEERRIE + Option byte change error interrupt + enable bit + 30 + 1 + + + SWAP_BANK + Bank swapping configuration + bit + 31 + 1 + + + + + OPTCR_ + OPTCR_ + FLASH option control register + 0x118 + 0x20 + read-write + 0x00000000 + + + OPTLOCK + FLASH_OPTCR lock option configuration + bit + 0 + 1 + + + OPTSTART + Option byte start change option + configuration bit + 1 + 1 + + + MER + Flash mass erase enable + bit + 4 + 1 + + + OPTCHANGEERRIE + Option byte change error interrupt + enable bit + 30 + 1 + + + SWAP_BANK + Bank swapping configuration + bit + 31 + 1 + + + + + OPTSR_CUR_ + OPTSR_CUR_ + FLASH option status register + 0x11C + 0x20 + read-write + 0x00000000 + + + OPT_BUSY + Option byte change ongoing + flag + 0 + 1 + + + BOR_LEV + Brownout level option status + bit + 2 + 2 + + + IWDG1_HW + IWDG1 control option status + bit + 4 + 1 + + + nRST_STOP_D1 + D1 DStop entry reset option status + bit + 6 + 1 + + + nRST_STBY_D1 + D1 DStandby entry reset option status + bit + 7 + 1 + + + RDP + Readout protection level option status + byte + 8 + 8 + + + FZ_IWDG_STOP + IWDG Stop mode freeze option status + bit + 17 + 1 + + + FZ_IWDG_SDBY + IWDG Standby mode freeze option status + bit + 18 + 1 + + + ST_RAM_SIZE + DTCM RAM size option + status + 19 + 2 + + + SECURITY + Security enable option status + bit + 21 + 1 + + + RSS1 + User option bit 1 + 26 + 1 + + + PERSO_OK + Device personalization status + bit + 28 + 1 + + + IO_HSLV + I/O high-speed at low-voltage status bit + (PRODUCT_BELOW_25V) + 29 + 1 + + + OPTCHANGEERR + Option byte change error + flag + 30 + 1 + + + SWAP_BANK_OPT + Bank swapping option status + bit + 31 + 1 + + + + + OPTSR_CUR + OPTSR_CUR + FLASH option status register + 0x1C + 0x20 + read-write + 0x00000000 + + + OPT_BUSY + Option byte change ongoing + flag + 0 + 1 + + + BOR_LEV + Brownout level option status + bit + 2 + 2 + + + IWDG1_HW + IWDG1 control option status + bit + 4 + 1 + + + nRST_STOP_D1 + D1 DStop entry reset option status + bit + 6 + 1 + + + nRST_STBY_D1 + D1 DStandby entry reset option status + bit + 7 + 1 + + + RDP + Readout protection level option status + byte + 8 + 8 + + + FZ_IWDG_STOP + IWDG Stop mode freeze option status + bit + 17 + 1 + + + FZ_IWDG_SDBY + IWDG Standby mode freeze option status + bit + 18 + 1 + + + ST_RAM_SIZE + DTCM RAM size option + status + 19 + 2 + + + SECURITY + Security enable option status + bit + 21 + 1 + + + RSS1 + User option bit 1 + 26 + 1 + + + PERSO_OK + Device personalization status + bit + 28 + 1 + + + IO_HSLV + I/O high-speed at low-voltage status bit + (PRODUCT_BELOW_25V) + 29 + 1 + + + OPTCHANGEERR + Option byte change error + flag + 30 + 1 + + + SWAP_BANK_OPT + Bank swapping option status + bit + 31 + 1 + + + + + OPTSR_PRG + OPTSR_PRG + FLASH option status register + 0x20 + 0x20 + read-write + 0x00000000 + + + BOR_LEV + BOR reset level option configuration + bits + 2 + 2 + + + IWDG1_HW + IWDG1 option configuration + bit + 4 + 1 + + + nRST_STOP_D1 + Option byte erase after D1 DStop option + configuration bit + 6 + 1 + + + nRST_STBY_D1 + Option byte erase after D1 DStandby + option configuration bit + 7 + 1 + + + RDP + Readout protection level option + configuration byte + 8 + 8 + + + FZ_IWDG_STOP + IWDG Stop mode freeze option + configuration bit + 17 + 1 + + + FZ_IWDG_SDBY + IWDG Standby mode freeze option + configuration bit + 18 + 1 + + + ST_RAM_SIZE + DTCM size select option configuration + bits + 19 + 2 + + + SECURITY + Security option configuration + bit + 21 + 1 + + + RSS1 + User option configuration bit + 1 + 26 + 1 + + + RSS2 + User option configuration bit + 2 + 27 + 1 + + + IO_HSLV + I/O high-speed at low-voltage + (PRODUCT_BELOW_25V) + 29 + 1 + + + SWAP_BANK_OPT + Bank swapping option configuration + bit + 31 + 1 + + + + + OPTSR_PRG_ + OPTSR_PRG_ + FLASH option status register + 0x120 + 0x20 + read-write + 0x00000000 + + + BOR_LEV + BOR reset level option configuration + bits + 2 + 2 + + + IWDG1_HW + IWDG1 option configuration + bit + 4 + 1 + + + nRST_STOP_D1 + Option byte erase after D1 DStop option + configuration bit + 6 + 1 + + + nRST_STBY_D1 + Option byte erase after D1 DStandby + option configuration bit + 7 + 1 + + + RDP + Readout protection level option + configuration byte + 8 + 8 + + + FZ_IWDG_STOP + IWDG Stop mode freeze option + configuration bit + 17 + 1 + + + FZ_IWDG_SDBY + IWDG Standby mode freeze option + configuration bit + 18 + 1 + + + ST_RAM_SIZE + DTCM size select option configuration + bits + 19 + 2 + + + SECURITY + Security option configuration + bit + 21 + 1 + + + RSS1 + User option configuration bit + 1 + 26 + 1 + + + RSS2 + User option configuration bit + 2 + 27 + 1 + + + IO_HSLV + I/O high-speed at low-voltage + (PRODUCT_BELOW_25V) + 29 + 1 + + + SWAP_BANK_OPT + Bank swapping option configuration + bit + 31 + 1 + + + + + OPTCCR_ + OPTCCR_ + FLASH option clear control + register + 0x124 + 0x20 + write-only + 0x00000000 + + + CLR_OPTCHANGEERR + OPTCHANGEERR reset bit + 30 + 1 + + + + + OPTCCR + OPTCCR + FLASH option clear control + register + 0x24 + 0x20 + write-only + 0x00000000 + + + CLR_OPTCHANGEERR + OPTCHANGEERR reset bit + 30 + 1 + + + + + PRAR_CUR1 + PRAR_CUR1 + FLASH protection address for bank + 1 + 0x28 + 0x20 + read-only + 0x00000000 + + + PROT_AREA_START1 + Bank 1 lowest PCROP protected + address + 0 + 12 + + + PROT_AREA_END1 + Bank 1 highest PCROP protected + address + 16 + 12 + + + DMEP1 + Bank 1 PCROP protected erase enable + option status bit + 31 + 1 + + + + + PRAR_PRG1 + PRAR_PRG1 + FLASH protection address for bank + 1 + 0x2C + 0x20 + read-write + 0x00000000 + + + PROT_AREA_START1 + Bank 1 lowest PCROP protected address + configuration + 0 + 12 + + + PROT_AREA_END1 + Bank 1 highest PCROP protected address + configuration + 16 + 12 + + + DMEP1 + Bank 1 PCROP protected erase enable + option configuration bit + 31 + 1 + + + + + SCAR_CUR1 + SCAR_CUR1 + FLASH secure address for bank + 1 + 0x30 + 0x20 + read-write + 0x00000000 + + + SEC_AREA_START1 + Bank 1 lowest secure protected + address + 0 + 12 + + + SEC_AREA_END1 + Bank 1 highest secure protected + address + 16 + 12 + + + DMES1 + Bank 1 secure protected erase enable + option status bit + 31 + 1 + + + + + SCAR_PRG1 + SCAR_PRG1 + FLASH secure address for bank + 1 + 0x34 + 0x20 + read-write + 0x00000000 + + + SEC_AREA_START1 + Bank 1 lowest secure protected address + configuration + 0 + 12 + + + SEC_AREA_END1 + Bank 1 highest secure protected address + configuration + 16 + 12 + + + DMES1 + Bank 1 secure protected erase enable + option configuration bit + 31 + 1 + + + + + WPSN_CUR1R + WPSN_CUR1R + FLASH write sector protection for bank + 1 + 0x38 + 0x20 + read-only + 0x00000000 + + + WRPSn1 + Bank 1 sector write protection option + status byte + 0 + 8 + + + + + WPSN_PRG1R + WPSN_PRG1R + FLASH write sector protection for bank + 1 + 0x3C + 0x20 + read-write + 0x00000000 + + + WRPSn1 + Bank 1 sector write protection + configuration byte + 0 + 8 + + + + + BOOT_CURR + BOOT_CURR + FLASH register with boot + address + 0x40 + 0x20 + read-only + 0x00000000 + + + BOOT_ADD0 + Boot address 0 + 0 + 16 + + + BOOT_ADD1 + Boot address 1 + 16 + 16 + + + + + BOOT_PRGR + BOOT_PRGR + FLASH register with boot + address + 0x44 + 0x20 + read-only + 0x00000000 + + + BOOT_ADD0 + Boot address 0 + 0 + 16 + + + BOOT_ADD1 + Boot address 1 + 16 + 16 + + + + + CRCCR1 + CRCCR1 + FLASH CRC control register for bank + 1 + 0x50 + 0x20 + read-write + 0x00000000 + + + CRC_SECT + Bank 1 CRC sector number + 0 + 3 + + + ALL_BANK + Bank 1 CRC select bit + 7 + 1 + + + CRC_BY_SECT + Bank 1 CRC sector mode select + bit + 8 + 1 + + + ADD_SECT + Bank 1 CRC sector select + bit + 9 + 1 + + + CLEAN_SECT + Bank 1 CRC sector list clear + bit + 10 + 1 + + + START_CRC + Bank 1 CRC start bit + 16 + 1 + + + CLEAN_CRC + Bank 1 CRC clear bit + 17 + 1 + + + CRC_BURST + Bank 1 CRC burst size + 20 + 2 + + + + + CRCSADD1R + CRCSADD1R + FLASH CRC start address register for bank + 1 + 0x54 + 0x20 + read-write + 0x00000000 + + + CRC_START_ADDR + CRC start address on bank + 1 + 0 + 32 + + + + + CRCEADD1R + CRCEADD1R + FLASH CRC end address register for bank + 1 + 0x58 + 0x20 + read-write + 0x00000000 + + + CRC_END_ADDR + CRC end address on bank 1 + 0 + 32 + + + + + CRCDATAR + CRCDATAR + FLASH CRC data register + 0x5C + 0x20 + read-write + 0x00000000 + + + CRC_DATA + CRC result + 0 + 32 + + + + + ECC_FA1R + ECC_FA1R + FLASH ECC fail address for bank + 1 + 0x60 + 0x20 + read-only + 0x00000000 + + + FAIL_ECC_ADDR1 + Bank 1 ECC error address + 0 + 15 + + + + + KEYR2 + KEYR2 + FLASH key register for bank 2 + 0x104 + 0x20 + read-only + 0x00000000 + + + KEYR2 + Bank 2 access configuration unlock + key + 0 + 32 + + + + + CR2 + CR2 + FLASH control register for bank + 2 + 0x10C + 0x20 + read-write + 0x00000000 + + + LOCK2 + Bank 2 configuration lock + bit + 0 + 1 + + + PG2 + Bank 2 program enable bit + 1 + 1 + + + SER2 + Bank 2 sector erase + request + 2 + 1 + + + BER2 + Bank 2 erase request + 3 + 1 + + + PSIZE2 + Bank 2 program size + 4 + 2 + + + FW2 + Bank 2 write forcing control + bit + 6 + 1 + + + START2 + Bank 2 bank or sector erase start + control bit + 7 + 1 + + + SNB2 + Bank 2 sector erase selection + number + 8 + 3 + + + CRC_EN + Bank 2 CRC control bit + 15 + 1 + + + EOPIE2 + Bank 2 end-of-program interrupt control + bit + 16 + 1 + + + WRPERRIE2 + Bank 2 write protection error interrupt + enable bit + 17 + 1 + + + PGSERRIE2 + Bank 2 programming sequence error + interrupt enable bit + 18 + 1 + + + STRBERRIE2 + Bank 2 strobe error interrupt enable + bit + 19 + 1 + + + INCERRIE2 + Bank 2 inconsistency error interrupt + enable bit + 21 + 1 + + + OPERRIE2 + Bank 2 write/erase error interrupt + enable bit + 22 + 1 + + + RDPERRIE2 + Bank 2 read protection error interrupt + enable bit + 23 + 1 + + + RDSERRIE2 + Bank 2 secure error interrupt enable + bit + 24 + 1 + + + SNECCERRIE2 + Bank 2 ECC single correction error + interrupt enable bit + 25 + 1 + + + DBECCERRIE2 + Bank 2 ECC double detection error + interrupt enable bit + 26 + 1 + + + CRCENDIE2 + Bank 2 end of CRC calculation interrupt + enable bit + 27 + 1 + + + + + SR2 + SR2 + FLASH status register for bank + 2 + 0x110 + 0x20 + read-write + 0x00000000 + + + BSY2 + Bank 2 ongoing program + flag + 0 + 1 + + + WBNE2 + Bank 2 write buffer not empty + flag + 1 + 1 + + + QW2 + Bank 2 wait queue flag + 2 + 1 + + + CRC_BUSY2 + Bank 2 CRC busy flag + 3 + 1 + + + EOP2 + Bank 2 end-of-program flag + 16 + 1 + + + WRPERR2 + Bank 2 write protection error + flag + 17 + 1 + + + PGSERR2 + Bank 2 programming sequence error + flag + 18 + 1 + + + STRBERR2 + Bank 2 strobe error flag + 19 + 1 + + + INCERR2 + Bank 2 inconsistency error + flag + 21 + 1 + + + OPERR2 + Bank 2 write/erase error + flag + 22 + 1 + + + RDPERR2 + Bank 2 read protection error + flag + 23 + 1 + + + RDSERR2 + Bank 2 secure error flag + 24 + 1 + + + SNECCERR2 + Bank 2 single correction error + flag + 25 + 1 + + + DBECCERR2 + Bank 2 ECC double detection error + flag + 26 + 1 + + + CRCEND2 + Bank 2 CRC-complete flag + 27 + 1 + + + + + CCR2 + CCR2 + FLASH clear control register for bank + 2 + 0x114 + 0x20 + read-write + 0x00000000 + + + CLR_EOP2 + Bank 1 EOP1 flag clear bit + 16 + 1 + + + CLR_WRPERR2 + Bank 2 WRPERR1 flag clear + bit + 17 + 1 + + + CLR_PGSERR2 + Bank 2 PGSERR1 flag clear + bi + 18 + 1 + + + CLR_STRBERR2 + Bank 2 STRBERR1 flag clear + bit + 19 + 1 + + + CLR_INCERR2 + Bank 2 INCERR1 flag clear + bit + 21 + 1 + + + CLR_OPERR2 + Bank 2 OPERR1 flag clear + bit + 22 + 1 + + + CLR_RDPERR2 + Bank 2 RDPERR1 flag clear + bit + 23 + 1 + + + CLR_RDSERR1 + Bank 1 RDSERR1 flag clear + bit + 24 + 1 + + + CLR_SNECCERR2 + Bank 2 SNECCERR1 flag clear + bit + 25 + 1 + + + CLR_DBECCERR1 + Bank 1 DBECCERR1 flag clear + bit + 26 + 1 + + + CLR_CRCEND2 + Bank 2 CRCEND1 flag clear + bit + 27 + 1 + + + + + PRAR_CUR2 + PRAR_CUR2 + FLASH protection address for bank + 1 + 0x128 + 0x20 + read-only + 0x00000000 + + + PROT_AREA_START2 + Bank 2 lowest PCROP protected + address + 0 + 12 + + + PROT_AREA_END2 + Bank 2 highest PCROP protected + address + 16 + 12 + + + DMEP2 + Bank 2 PCROP protected erase enable + option status bit + 31 + 1 + + + + + PRAR_PRG2 + PRAR_PRG2 + FLASH protection address for bank + 2 + PRAR_PRG1 + 0x2C + 0x20 + read-write + 0x00000000 + + + PROT_AREA_START2 + Bank 2 lowest PCROP protected address + configuration + 0 + 12 + + + PROT_AREA_END2 + Bank 2 highest PCROP protected address + configuration + 16 + 12 + + + DMEP2 + Bank 2 PCROP protected erase enable + option configuration bit + 31 + 1 + + + + + SCAR_CUR2 + SCAR_CUR2 + FLASH secure address for bank + 2 + 0x130 + 0x20 + read-write + 0x00000000 + + + SEC_AREA_START2 + Bank 2 lowest secure protected + address + 0 + 12 + + + SEC_AREA_END2 + Bank 2 highest secure protected + address + 16 + 12 + + + DMES2 + Bank 2 secure protected erase enable + option status bit + 31 + 1 + + + + + SCAR_PRG2 + SCAR_PRG2 + FLASH secure address for bank + 2 + 0x134 + 0x20 + read-write + 0x00000000 + + + SEC_AREA_START2 + Bank 2 lowest secure protected address + configuration + 0 + 12 + + + SEC_AREA_END2 + Bank 2 highest secure protected address + configuration + 16 + 12 + + + DMES2 + Bank 2 secure protected erase enable + option configuration bit + 31 + 1 + + + + + WPSN_CUR2R + WPSN_CUR2R + FLASH write sector protection for bank + 2 + 0x138 + 0x20 + read-only + 0x00000000 + + + WRPSn2 + Bank 2 sector write protection option + status byte + 0 + 8 + + + + + WPSN_PRG2R + WPSN_PRG2R + FLASH write sector protection for bank + 2 + 0x13C + 0x20 + read-write + 0x00000000 + + + WRPSn2 + Bank 2 sector write protection + configuration byte + 0 + 8 + + + + + CRCCR2 + CRCCR2 + FLASH CRC control register for bank + 1 + 0x150 + 0x20 + read-write + 0x00000000 + + + CRC_SECT + Bank 2 CRC sector number + 0 + 3 + + + ALL_BANK + Bank 2 CRC select bit + 7 + 1 + + + CRC_BY_SECT + Bank 2 CRC sector mode select + bit + 8 + 1 + + + ADD_SECT + Bank 2 CRC sector select + bit + 9 + 1 + + + CLEAN_SECT + Bank 2 CRC sector list clear + bit + 10 + 1 + + + START_CRC + Bank 2 CRC start bit + 16 + 1 + + + CLEAN_CRC + Bank 2 CRC clear bit + 17 + 1 + + + CRC_BURST + Bank 2 CRC burst size + 20 + 2 + + + + + CRCSADD2R + CRCSADD2R + FLASH CRC start address register for bank + 2 + 0x154 + 0x20 + read-write + 0x00000000 + + + CRC_START_ADDR + CRC start address on bank + 2 + 0 + 32 + + + + + CRCEADD2R + CRCEADD2R + FLASH CRC end address register for bank + 2 + 0x158 + 0x20 + read-write + 0x00000000 + + + CRC_END_ADDR + CRC end address on bank 2 + 0 + 32 + + + + + ECC_FA2R + ECC_FA2R + FLASH ECC fail address for bank + 2 + 0x160 + 0x20 + read-only + 0x00000000 + + + FAIL_ECC_ADDR2 + Bank 2 ECC error address + 0 + 15 + + + + + + + AXI + AXI interconnect registers + AXI + 0x51000000 + + 0x0 + 0x100000 + registers + + + + AXI_PERIPH_ID_4 + AXI_PERIPH_ID_4 + AXI interconnect - peripheral ID4 + register + 0x1FD0 + 0x20 + read-only + 0x00000004 + + + JEP106CON + JEP106 continuation code + 0 + 4 + + + KCOUNT4 + Register file size + 4 + 4 + + + + + AXI_PERIPH_ID_0 + AXI_PERIPH_ID_0 + AXI interconnect - peripheral ID0 + register + 0x1FE0 + 0x20 + read-only + 0x00000004 + + + PARTNUM + Peripheral part number bits 0 to + 7 + 0 + 8 + + + + + AXI_PERIPH_ID_1 + AXI_PERIPH_ID_1 + AXI interconnect - peripheral ID1 + register + 0x1FE4 + 0x20 + read-only + 0x00000004 + + + PARTNUM + Peripheral part number bits 8 to + 11 + 0 + 4 + + + JEP106I + JEP106 identity bits 0 to + 3 + 4 + 4 + + + + + AXI_PERIPH_ID_2 + AXI_PERIPH_ID_2 + AXI interconnect - peripheral ID2 + register + 0x1FE8 + 0x20 + read-only + 0x00000004 + + + JEP106ID + JEP106 Identity bits 4 to + 6 + 0 + 3 + + + JEDEC + JEP106 code flag + 3 + 1 + + + REVISION + Peripheral revision number + 4 + 4 + + + + + AXI_PERIPH_ID_3 + AXI_PERIPH_ID_3 + AXI interconnect - peripheral ID3 + register + 0x1FEC + 0x20 + read-only + 0x00000004 + + + CUST_MOD_NUM + Customer modification + 0 + 4 + + + REV_AND + Customer version + 4 + 4 + + + + + AXI_COMP_ID_0 + AXI_COMP_ID_0 + AXI interconnect - component ID0 + register + 0x1FF0 + 0x20 + read-only + 0x00000004 + + + PREAMBLE + Preamble bits 0 to 7 + 0 + 8 + + + + + AXI_COMP_ID_1 + AXI_COMP_ID_1 + AXI interconnect - component ID1 + register + 0x1FF4 + 0x20 + read-only + 0x00000004 + + + PREAMBLE + Preamble bits 8 to 11 + 0 + 4 + + + CLASS + Component class + 4 + 4 + + + + + AXI_COMP_ID_2 + AXI_COMP_ID_2 + AXI interconnect - component ID2 + register + 0x1FF8 + 0x20 + read-only + 0x00000004 + + + PREAMBLE + Preamble bits 12 to 19 + 0 + 8 + + + + + AXI_COMP_ID_3 + AXI_COMP_ID_3 + AXI interconnect - component ID3 + register + 0x1FFC + 0x20 + read-only + 0x00000004 + + + PREAMBLE + Preamble bits 20 to 27 + 0 + 8 + + + + + AXI_TARG1_FN_MOD_ISS_BM + AXI_TARG1_FN_MOD_ISS_BM + AXI interconnect - TARG x bus matrix issuing + functionality register + 0x2008 + 0x20 + read-write + 0x00000004 + + + READ_ISS_OVERRIDE + READ_ISS_OVERRIDE + 0 + 1 + + + WRITE_ISS_OVERRIDE + Switch matrix write issuing override for + target + 1 + 1 + + + + + AXI_TARG2_FN_MOD_ISS_BM + AXI_TARG2_FN_MOD_ISS_BM + AXI interconnect - TARG x bus matrix issuing + functionality register + 0x3008 + 0x20 + read-write + 0x00000004 + + + READ_ISS_OVERRIDE + READ_ISS_OVERRIDE + 0 + 1 + + + WRITE_ISS_OVERRIDE + Switch matrix write issuing override for + target + 1 + 1 + + + + + AXI_TARG3_FN_MOD_ISS_BM + AXI_TARG3_FN_MOD_ISS_BM + AXI interconnect - TARG x bus matrix issuing + functionality register + 0x4008 + 0x20 + read-write + 0x00000004 + + + READ_ISS_OVERRIDE + READ_ISS_OVERRIDE + 0 + 1 + + + WRITE_ISS_OVERRIDE + Switch matrix write issuing override for + target + 1 + 1 + + + + + AXI_TARG4_FN_MOD_ISS_BM + AXI_TARG4_FN_MOD_ISS_BM + AXI interconnect - TARG x bus matrix issuing + functionality register + 0x5008 + 0x20 + read-write + 0x00000004 + + + READ_ISS_OVERRIDE + READ_ISS_OVERRIDE + 0 + 1 + + + WRITE_ISS_OVERRIDE + Switch matrix write issuing override for + target + 1 + 1 + + + + + AXI_TARG5_FN_MOD_ISS_BM + AXI_TARG5_FN_MOD_ISS_BM + AXI interconnect - TARG x bus matrix issuing + functionality register + 0x6008 + 0x20 + read-write + 0x00000004 + + + READ_ISS_OVERRIDE + READ_ISS_OVERRIDE + 0 + 1 + + + WRITE_ISS_OVERRIDE + Switch matrix write issuing override for + target + 1 + 1 + + + + + AXI_TARG6_FN_MOD_ISS_BM + AXI_TARG6_FN_MOD_ISS_BM + AXI interconnect - TARG x bus matrix issuing + functionality register + 0x7008 + 0x20 + read-write + 0x00000004 + + + READ_ISS_OVERRIDE + READ_ISS_OVERRIDE + 0 + 1 + + + WRITE_ISS_OVERRIDE + Switch matrix write issuing override for + target + 1 + 1 + + + + + AXI_TARG7_FN_MOD_ISS_BM + AXI_TARG7_FN_MOD_ISS_BM + AXI interconnect - TARG x bus matrix issuing + functionality register + 0x800C + 0x20 + read-write + 0x00000004 + + + READ_ISS_OVERRIDE + READ_ISS_OVERRIDE + 0 + 1 + + + WRITE_ISS_OVERRIDE + Switch matrix write issuing override for + target + 1 + 1 + + + + + AXI_TARG1_FN_MOD2 + AXI_TARG1_FN_MOD2 + AXI interconnect - TARG x bus matrix + functionality 2 register + 0x2024 + 0x20 + read-write + 0x00000004 + + + BYPASS_MERGE + Disable packing of beats to match the + output data width + 0 + 1 + + + + + AXI_TARG2_FN_MOD2 + AXI_TARG2_FN_MOD2 + AXI interconnect - TARG x bus matrix + functionality 2 register + 0x3024 + 0x20 + read-write + 0x00000004 + + + BYPASS_MERGE + Disable packing of beats to match the + output data width + 0 + 1 + + + + + AXI_TARG7_FN_MOD2 + AXI_TARG7_FN_MOD2 + AXI interconnect - TARG x bus matrix + functionality 2 register + 0x8024 + 0x20 + read-write + 0x00000004 + + + BYPASS_MERGE + Disable packing of beats to match the + output data width + 0 + 1 + + + + + AXI_TARG1_FN_MOD_LB + AXI_TARG1_FN_MOD_LB + AXI interconnect - TARG x long burst + functionality modification + 0x202C + 0x20 + read-write + 0x00000004 + + + FN_MOD_LB + Controls burst breaking of long + bursts + 0 + 1 + + + + + AXI_TARG2_FN_MOD_LB + AXI_TARG2_FN_MOD_LB + AXI interconnect - TARG x long burst + functionality modification + 0x302C + 0x20 + read-write + 0x00000004 + + + FN_MOD_LB + Controls burst breaking of long + bursts + 0 + 1 + + + + + AXI_TARG1_FN_MOD + AXI_TARG1_FN_MOD + AXI interconnect - TARG x long burst + functionality modification + 0x2108 + 0x20 + read-write + 0x00000004 + + + READ_ISS_OVERRIDE + Override AMIB read issuing + capability + 0 + 1 + + + WRITE_ISS_OVERRIDE + Override AMIB write issuing + capability + 1 + 1 + + + + + AXI_TARG2_FN_MOD + AXI_TARG2_FN_MOD + AXI interconnect - TARG x long burst + functionality modification + 0x3108 + 0x20 + read-write + 0x00000004 + + + READ_ISS_OVERRIDE + Override AMIB read issuing + capability + 0 + 1 + + + WRITE_ISS_OVERRIDE + Override AMIB write issuing + capability + 1 + 1 + + + + + AXI_TARG7_FN_MOD + AXI_TARG7_FN_MOD + AXI interconnect - TARG x long burst + functionality modification + 0x8108 + 0x20 + read-write + 0x00000004 + + + READ_ISS_OVERRIDE + Override AMIB read issuing + capability + 0 + 1 + + + WRITE_ISS_OVERRIDE + Override AMIB write issuing + capability + 1 + 1 + + + + + AXI_INI1_FN_MOD2 + AXI_INI1_FN_MOD2 + AXI interconnect - INI x functionality + modification 2 register + 0x42024 + 0x20 + read-write + 0x00000004 + + + BYPASS_MERGE + Disables alteration of transactions by + the up-sizer unless required by the + protocol + 0 + 1 + + + + + AXI_INI3_FN_MOD2 + AXI_INI3_FN_MOD2 + AXI interconnect - INI x functionality + modification 2 register + 0x44024 + 0x20 + read-write + 0x00000004 + + + BYPASS_MERGE + Disables alteration of transactions by + the up-sizer unless required by the + protocol + 0 + 1 + + + + + AXI_INI1_FN_MOD_AHB + AXI_INI1_FN_MOD_AHB + AXI interconnect - INI x AHB functionality + modification register + 0x42028 + 0x20 + read-write + 0x00000004 + + + RD_INC_OVERRIDE + Converts all AHB-Lite write transactions + to a series of single beat AXI + 0 + 1 + + + WR_INC_OVERRIDE + Converts all AHB-Lite read transactions + to a series of single beat AXI + 1 + 1 + + + + + AXI_INI3_FN_MOD_AHB + AXI_INI3_FN_MOD_AHB + AXI interconnect - INI x AHB functionality + modification register + 0x44028 + 0x20 + read-write + 0x00000004 + + + RD_INC_OVERRIDE + Converts all AHB-Lite write transactions + to a series of single beat AXI + 0 + 1 + + + WR_INC_OVERRIDE + Converts all AHB-Lite read transactions + to a series of single beat AXI + 1 + 1 + + + + + AXI_INI1_READ_QOS + AXI_INI1_READ_QOS + AXI interconnect - INI x read QoS + register + 0x42100 + 0x20 + read-write + 0x00000004 + + + AR_QOS + Read channel QoS setting + 0 + 4 + + + + + AXI_INI2_READ_QOS + AXI_INI2_READ_QOS + AXI interconnect - INI x read QoS + register + 0x43100 + 0x20 + read-write + 0x00000004 + + + AR_QOS + Read channel QoS setting + 0 + 4 + + + + + AXI_INI3_READ_QOS + AXI_INI3_READ_QOS + AXI interconnect - INI x read QoS + register + 0x44100 + 0x20 + read-write + 0x00000004 + + + AR_QOS + Read channel QoS setting + 0 + 4 + + + + + AXI_INI4_READ_QOS + AXI_INI4_READ_QOS + AXI interconnect - INI x read QoS + register + 0x45100 + 0x20 + read-write + 0x00000004 + + + AR_QOS + Read channel QoS setting + 0 + 4 + + + + + AXI_INI5_READ_QOS + AXI_INI5_READ_QOS + AXI interconnect - INI x read QoS + register + 0x46100 + 0x20 + read-write + 0x00000004 + + + AR_QOS + Read channel QoS setting + 0 + 4 + + + + + AXI_INI6_READ_QOS + AXI_INI6_READ_QOS + AXI interconnect - INI x read QoS + register + 0x47100 + 0x20 + read-write + 0x00000004 + + + AR_QOS + Read channel QoS setting + 0 + 4 + + + + + AXI_INI1_WRITE_QOS + AXI_INI1_WRITE_QOS + AXI interconnect - INI x write QoS + register + 0x42104 + 0x20 + read-write + 0x00000004 + + + AW_QOS + Write channel QoS setting + 0 + 4 + + + + + AXI_INI2_WRITE_QOS + AXI_INI2_WRITE_QOS + AXI interconnect - INI x write QoS + register + 0x43104 + 0x20 + read-write + 0x00000004 + + + AW_QOS + Write channel QoS setting + 0 + 4 + + + + + AXI_INI3_WRITE_QOS + AXI_INI3_WRITE_QOS + AXI interconnect - INI x write QoS + register + 0x44104 + 0x20 + read-write + 0x00000004 + + + AW_QOS + Write channel QoS setting + 0 + 4 + + + + + AXI_INI4_WRITE_QOS + AXI_INI4_WRITE_QOS + AXI interconnect - INI x write QoS + register + 0x45104 + 0x20 + read-write + 0x00000004 + + + AW_QOS + Write channel QoS setting + 0 + 4 + + + + + AXI_INI5_WRITE_QOS + AXI_INI5_WRITE_QOS + AXI interconnect - INI x write QoS + register + 0x46104 + 0x20 + read-write + 0x00000004 + + + AW_QOS + Write channel QoS setting + 0 + 4 + + + + + AXI_INI6_WRITE_QOS + AXI_INI6_WRITE_QOS + AXI interconnect - INI x write QoS + register + 0x47104 + 0x20 + read-write + 0x00000004 + + + AW_QOS + Write channel QoS setting + 0 + 4 + + + + + AXI_INI1_FN_MOD + AXI_INI1_FN_MOD + AXI interconnect - INI x issuing + functionality modification register + 0x42108 + 0x20 + read-write + 0x00000004 + + + READ_ISS_OVERRIDE + Override ASIB read issuing + capability + 0 + 1 + + + WRITE_ISS_OVERRIDE + Override ASIB write issuing + capability + 1 + 1 + + + + + AXI_INI2_FN_MOD + AXI_INI2_FN_MOD + AXI interconnect - INI x issuing + functionality modification register + 0x43108 + 0x20 + read-write + 0x00000004 + + + READ_ISS_OVERRIDE + Override ASIB read issuing + capability + 0 + 1 + + + WRITE_ISS_OVERRIDE + Override ASIB write issuing + capability + 1 + 1 + + + + + AXI_INI3_FN_MOD + AXI_INI3_FN_MOD + AXI interconnect - INI x issuing + functionality modification register + 0x44108 + 0x20 + read-write + 0x00000004 + + + READ_ISS_OVERRIDE + Override ASIB read issuing + capability + 0 + 1 + + + WRITE_ISS_OVERRIDE + Override ASIB write issuing + capability + 1 + 1 + + + + + AXI_INI4_FN_MOD + AXI_INI4_FN_MOD + AXI interconnect - INI x issuing + functionality modification register + 0x45108 + 0x20 + read-write + 0x00000004 + + + READ_ISS_OVERRIDE + Override ASIB read issuing + capability + 0 + 1 + + + WRITE_ISS_OVERRIDE + Override ASIB write issuing + capability + 1 + 1 + + + + + AXI_INI5_FN_MOD + AXI_INI5_FN_MOD + AXI interconnect - INI x issuing + functionality modification register + 0x46108 + 0x20 + read-write + 0x00000004 + + + READ_ISS_OVERRIDE + Override ASIB read issuing + capability + 0 + 1 + + + WRITE_ISS_OVERRIDE + Override ASIB write issuing + capability + 1 + 1 + + + + + AXI_INI6_FN_MOD + AXI_INI6_FN_MOD + AXI interconnect - INI x issuing + functionality modification register + 0x47108 + 0x20 + read-write + 0x00000004 + + + READ_ISS_OVERRIDE + Override ASIB read issuing + capability + 0 + 1 + + + WRITE_ISS_OVERRIDE + Override ASIB write issuing + capability + 1 + 1 + + + + + + + + + DCMI + Digital camera interface + DCMI + 0x48020000 + + 0x0 + 0x400 + registers + + + DCMI + DCMI global interrupt + 78 + + + + CR + CR + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + OELS + Odd/Even Line Select (Line Select + Start) + 20 + 1 + + + LSM + Line Select mode + 19 + 1 + + + OEBS + Odd/Even Byte Select (Byte Select + Start) + 18 + 1 + + + BSM + Byte Select mode + 16 + 2 + + + ENABLE + DCMI enable + 14 + 1 + + + EDM + Extended data mode + 10 + 2 + + + FCRC + Frame capture rate control + 8 + 2 + + + VSPOL + Vertical synchronization + polarity + 7 + 1 + + + HSPOL + Horizontal synchronization + polarity + 6 + 1 + + + PCKPOL + Pixel clock polarity + 5 + 1 + + + ESS + Embedded synchronization + select + 4 + 1 + + + JPEG + JPEG format + 3 + 1 + + + CROP + Crop feature + 2 + 1 + + + CM + Capture mode + 1 + 1 + + + CAPTURE + Capture enable + 0 + 1 + + + + + SR + SR + status register + 0x4 + 0x20 + read-only + 0x0000 + + + FNE + FIFO not empty + 2 + 1 + + + VSYNC + VSYNC + 1 + 1 + + + HSYNC + HSYNC + 0 + 1 + + + + + RIS + RIS + raw interrupt status register + 0x8 + 0x20 + read-only + 0x0000 + + + LINE_RIS + Line raw interrupt status + 4 + 1 + + + VSYNC_RIS + VSYNC raw interrupt status + 3 + 1 + + + ERR_RIS + Synchronization error raw interrupt + status + 2 + 1 + + + OVR_RIS + Overrun raw interrupt + status + 1 + 1 + + + FRAME_RIS + Capture complete raw interrupt + status + 0 + 1 + + + + + IER + IER + interrupt enable register + 0xC + 0x20 + read-write + 0x0000 + + + LINE_IE + Line interrupt enable + 4 + 1 + + + VSYNC_IE + VSYNC interrupt enable + 3 + 1 + + + ERR_IE + Synchronization error interrupt + enable + 2 + 1 + + + OVR_IE + Overrun interrupt enable + 1 + 1 + + + FRAME_IE + Capture complete interrupt + enable + 0 + 1 + + + + + MIS + MIS + masked interrupt status + register + 0x10 + 0x20 + read-only + 0x0000 + + + LINE_MIS + Line masked interrupt + status + 4 + 1 + + + VSYNC_MIS + VSYNC masked interrupt + status + 3 + 1 + + + ERR_MIS + Synchronization error masked interrupt + status + 2 + 1 + + + OVR_MIS + Overrun masked interrupt + status + 1 + 1 + + + FRAME_MIS + Capture complete masked interrupt + status + 0 + 1 + + + + + ICR + ICR + interrupt clear register + 0x14 + 0x20 + write-only + 0x0000 + + + LINE_ISC + line interrupt status + clear + 4 + 1 + + + VSYNC_ISC + Vertical synch interrupt status + clear + 3 + 1 + + + ERR_ISC + Synchronization error interrupt status + clear + 2 + 1 + + + OVR_ISC + Overrun interrupt status + clear + 1 + 1 + + + FRAME_ISC + Capture complete interrupt status + clear + 0 + 1 + + + + + ESCR + ESCR + embedded synchronization code + register + 0x18 + 0x20 + read-write + 0x0000 + + + FEC + Frame end delimiter code + 24 + 8 + + + LEC + Line end delimiter code + 16 + 8 + + + LSC + Line start delimiter code + 8 + 8 + + + FSC + Frame start delimiter code + 0 + 8 + + + + + ESUR + ESUR + embedded synchronization unmask + register + 0x1C + 0x20 + read-write + 0x0000 + + + FEU + Frame end delimiter unmask + 24 + 8 + + + LEU + Line end delimiter unmask + 16 + 8 + + + LSU + Line start delimiter + unmask + 8 + 8 + + + FSU + Frame start delimiter + unmask + 0 + 8 + + + + + CWSTRT + CWSTRT + crop window start + 0x20 + 0x20 + read-write + 0x0000 + + + VST + Vertical start line count + 16 + 13 + + + HOFFCNT + Horizontal offset count + 0 + 14 + + + + + CWSIZE + CWSIZE + crop window size + 0x24 + 0x20 + read-write + 0x0000 + + + VLINE + Vertical line count + 16 + 14 + + + CAPCNT + Capture count + 0 + 14 + + + + + DR + DR + data register + 0x28 + 0x20 + read-only + 0x0000 + + + Byte3 + Data byte 3 + 24 + 8 + + + Byte2 + Data byte 2 + 16 + 8 + + + Byte1 + Data byte 1 + 8 + 8 + + + Byte0 + Data byte 0 + 0 + 8 + + + + + + + OTG1_HS_GLOBAL + USB 1 on the go high speed + USB_OTG_HS + 0x40040000 + + 0x0 + 0x400 + registers + + + + OTG_HS_GOTGCTL + OTG_HS_GOTGCTL + OTG_HS control and status + register + 0x0 + 32 + 0x00000800 + + + SRQSCS + Session request success + 0 + 1 + read-only + + + SRQ + Session request + 1 + 1 + read-write + + + HNGSCS + Host negotiation success + 8 + 1 + read-only + + + HNPRQ + HNP request + 9 + 1 + read-write + + + HSHNPEN + Host set HNP enable + 10 + 1 + read-write + + + DHNPEN + Device HNP enabled + 11 + 1 + read-write + + + CIDSTS + Connector ID status + 16 + 1 + read-only + + + DBCT + Long/short debounce time + 17 + 1 + read-only + + + ASVLD + A-session valid + 18 + 1 + read-only + + + BSVLD + B-session valid + 19 + 1 + read-only + + + EHEN + Embedded host enable + 12 + 1 + read-write + + + + + OTG_HS_GOTGINT + OTG_HS_GOTGINT + OTG_HS interrupt register + 0x4 + 32 + read-write + 0x0 + + + SEDET + Session end detected + 2 + 1 + + + SRSSCHG + Session request success status + change + 8 + 1 + + + HNSSCHG + Host negotiation success status + change + 9 + 1 + + + HNGDET + Host negotiation detected + 17 + 1 + + + ADTOCHG + A-device timeout change + 18 + 1 + + + DBCDNE + Debounce done + 19 + 1 + + + IDCHNG + ID input pin changed + 20 + 1 + + + + + OTG_HS_GAHBCFG + OTG_HS_GAHBCFG + OTG_HS AHB configuration + register + 0x8 + 32 + read-write + 0x0 + + + GINT + Global interrupt mask + 0 + 1 + + + HBSTLEN + Burst length/type + 1 + 4 + + + DMAEN + DMA enable + 5 + 1 + + + TXFELVL + TxFIFO empty level + 7 + 1 + + + PTXFELVL + Periodic TxFIFO empty + level + 8 + 1 + + + + + OTG_HS_GUSBCFG + OTG_HS_GUSBCFG + OTG_HS USB configuration + register + 0xC + 32 + 0x00000A00 + + + TOCAL + FS timeout calibration + 0 + 3 + read-write + + + PHYSEL + USB 2.0 high-speed ULPI PHY or USB 1.1 + full-speed serial transceiver select + 6 + 1 + write-only + + + SRPCAP + SRP-capable + 8 + 1 + read-write + + + HNPCAP + HNP-capable + 9 + 1 + read-write + + + TRDT + USB turnaround time + 10 + 4 + read-write + + + PHYLPCS + PHY Low-power clock select + 15 + 1 + read-write + + + ULPIFSLS + ULPI FS/LS select + 17 + 1 + read-write + + + ULPIAR + ULPI Auto-resume + 18 + 1 + read-write + + + ULPICSM + ULPI Clock SuspendM + 19 + 1 + read-write + + + ULPIEVBUSD + ULPI External VBUS Drive + 20 + 1 + read-write + + + ULPIEVBUSI + ULPI external VBUS + indicator + 21 + 1 + read-write + + + TSDPS + TermSel DLine pulsing + selection + 22 + 1 + read-write + + + PCCI + Indicator complement + 23 + 1 + read-write + + + PTCI + Indicator pass through + 24 + 1 + read-write + + + ULPIIPD + ULPI interface protect + disable + 25 + 1 + read-write + + + FHMOD + Forced host mode + 29 + 1 + read-write + + + FDMOD + Forced peripheral mode + 30 + 1 + read-write + + + + + OTG_HS_GRSTCTL + OTG_HS_GRSTCTL + OTG_HS reset register + 0x10 + 32 + 0x20000000 + + + CSRST + Core soft reset + 0 + 1 + read-write + + + HSRST + HCLK soft reset + 1 + 1 + read-write + + + FCRST + Host frame counter reset + 2 + 1 + read-write + + + RXFFLSH + RxFIFO flush + 4 + 1 + read-write + + + TXFFLSH + TxFIFO flush + 5 + 1 + read-write + + + TXFNUM + TxFIFO number + 6 + 5 + read-write + + + AHBIDL + AHB master idle + 31 + 1 + read-only + + + DMAREQ + DMA request signal enabled for USB OTG + HS + 30 + 1 + read-only + + + + + OTG_HS_GINTSTS + OTG_HS_GINTSTS + OTG_HS core interrupt register + 0x14 + 32 + 0x04000020 + + + CMOD + Current mode of operation + 0 + 1 + read-only + + + MMIS + Mode mismatch interrupt + 1 + 1 + read-write + + + OTGINT + OTG interrupt + 2 + 1 + read-only + + + SOF + Start of frame + 3 + 1 + read-write + + + RXFLVL + RxFIFO nonempty + 4 + 1 + read-only + + + NPTXFE + Nonperiodic TxFIFO empty + 5 + 1 + read-only + + + GINAKEFF + Global IN nonperiodic NAK + effective + 6 + 1 + read-only + + + BOUTNAKEFF + Global OUT NAK effective + 7 + 1 + read-only + + + ESUSP + Early suspend + 10 + 1 + read-write + + + USBSUSP + USB suspend + 11 + 1 + read-write + + + USBRST + USB reset + 12 + 1 + read-write + + + ENUMDNE + Enumeration done + 13 + 1 + read-write + + + ISOODRP + Isochronous OUT packet dropped + interrupt + 14 + 1 + read-write + + + EOPF + End of periodic frame + interrupt + 15 + 1 + read-write + + + IEPINT + IN endpoint interrupt + 18 + 1 + read-only + + + OEPINT + OUT endpoint interrupt + 19 + 1 + read-only + + + IISOIXFR + Incomplete isochronous IN + transfer + 20 + 1 + read-write + + + PXFR_INCOMPISOOUT + Incomplete periodic + transfer + 21 + 1 + read-write + + + DATAFSUSP + Data fetch suspended + 22 + 1 + read-write + + + HPRTINT + Host port interrupt + 24 + 1 + read-only + + + HCINT + Host channels interrupt + 25 + 1 + read-only + + + PTXFE + Periodic TxFIFO empty + 26 + 1 + read-only + + + CIDSCHG + Connector ID status change + 28 + 1 + read-write + + + DISCINT + Disconnect detected + interrupt + 29 + 1 + read-write + + + SRQINT + Session request/new session detected + interrupt + 30 + 1 + read-write + + + WKUINT + Resume/remote wakeup detected + interrupt + 31 + 1 + read-write + + + + + OTG_HS_GINTMSK + OTG_HS_GINTMSK + OTG_HS interrupt mask register + 0x18 + 32 + 0x0 + + + MMISM + Mode mismatch interrupt + mask + 1 + 1 + read-write + + + OTGINT + OTG interrupt mask + 2 + 1 + read-write + + + SOFM + Start of frame mask + 3 + 1 + read-write + + + RXFLVLM + Receive FIFO nonempty mask + 4 + 1 + read-write + + + NPTXFEM + Nonperiodic TxFIFO empty + mask + 5 + 1 + read-write + + + GINAKEFFM + Global nonperiodic IN NAK effective + mask + 6 + 1 + read-write + + + GONAKEFFM + Global OUT NAK effective + mask + 7 + 1 + read-write + + + ESUSPM + Early suspend mask + 10 + 1 + read-write + + + USBSUSPM + USB suspend mask + 11 + 1 + read-write + + + USBRST + USB reset mask + 12 + 1 + read-write + + + ENUMDNEM + Enumeration done mask + 13 + 1 + read-write + + + ISOODRPM + Isochronous OUT packet dropped interrupt + mask + 14 + 1 + read-write + + + EOPFM + End of periodic frame interrupt + mask + 15 + 1 + read-write + + + IEPINT + IN endpoints interrupt + mask + 18 + 1 + read-write + + + OEPINT + OUT endpoints interrupt + mask + 19 + 1 + read-write + + + IISOIXFRM + Incomplete isochronous IN transfer + mask + 20 + 1 + read-write + + + PXFRM_IISOOXFRM + Incomplete periodic transfer + mask + 21 + 1 + read-write + + + FSUSPM + Data fetch suspended mask + 22 + 1 + read-write + + + PRTIM + Host port interrupt mask + 24 + 1 + read-only + + + HCIM + Host channels interrupt + mask + 25 + 1 + read-write + + + PTXFEM + Periodic TxFIFO empty mask + 26 + 1 + read-write + + + CIDSCHGM + Connector ID status change + mask + 28 + 1 + read-write + + + DISCINT + Disconnect detected interrupt + mask + 29 + 1 + read-write + + + SRQIM + Session request/new session detected + interrupt mask + 30 + 1 + read-write + + + WUIM + Resume/remote wakeup detected interrupt + mask + 31 + 1 + read-write + + + RSTDE + Reset detected interrupt + mask + 23 + 1 + read-write + + + LPMINTM + LPM interrupt mask + 27 + 1 + read-write + + + + + OTG_HS_GRXSTSR_Host + OTG_HS_GRXSTSR_Host + OTG_HS Receive status debug read register + (host mode) + 0x1C + 32 + read-only + 0x0 + + + CHNUM + Channel number + 0 + 4 + + + BCNT + Byte count + 4 + 11 + + + DPID + Data PID + 15 + 2 + + + PKTSTS + Packet status + 17 + 4 + + + + + OTG_HS_GRXSTSP_Host + OTG_HS_GRXSTSP_Host + OTG_HS status read and pop register (host + mode) + 0x20 + 32 + read-only + 0x0 + + + CHNUM + Channel number + 0 + 4 + + + BCNT + Byte count + 4 + 11 + + + DPID + Data PID + 15 + 2 + + + PKTSTS + Packet status + 17 + 4 + + + + + OTG_HS_GRXFSIZ + OTG_HS_GRXFSIZ + OTG_HS Receive FIFO size + register + 0x24 + 32 + read-write + 0x00000200 + + + RXFD + RxFIFO depth + 0 + 16 + + + + + OTG_HS_HNPTXFSIZ_Host + OTG_HS_HNPTXFSIZ_Host + OTG_HS nonperiodic transmit FIFO size + register (host mode) + 0x28 + 32 + read-write + 0x00000200 + + + NPTXFSA + Nonperiodic transmit RAM start + address + 0 + 16 + + + NPTXFD + Nonperiodic TxFIFO depth + 16 + 16 + + + + + OTG_HS_DIEPTXF0_Device + OTG_HS_DIEPTXF0_Device + Endpoint 0 transmit FIFO size (peripheral + mode) + OTG_HS_HNPTXFSIZ_Host + 0x28 + 32 + read-write + 0x00000200 + + + TX0FSA + Endpoint 0 transmit RAM start + address + 0 + 16 + + + TX0FD + Endpoint 0 TxFIFO depth + 16 + 16 + + + + + OTG_HS_HNPTXSTS + OTG_HS_HNPTXSTS + OTG_HS nonperiodic transmit FIFO/queue + status register + 0x2C + 32 + read-only + 0x00080200 + + + NPTXFSAV + Nonperiodic TxFIFO space + available + 0 + 16 + + + NPTQXSAV + Nonperiodic transmit request queue space + available + 16 + 8 + + + NPTXQTOP + Top of the nonperiodic transmit request + queue + 24 + 7 + + + + + OTG_HS_GCCFG + OTG_HS_GCCFG + OTG_HS general core configuration + register + 0x38 + 32 + read-write + 0x0 + + + PWRDWN + Power down + 16 + 1 + + + BCDEN + Battery charging detector (BCD) + enable + 17 + 1 + + + DCDEN + Data contact detection (DCD) mode + enable + 18 + 1 + + + PDEN + Primary detection (PD) mode + enable + 19 + 1 + + + SDEN + Secondary detection (SD) mode + enable + 20 + 1 + + + VBDEN + USB VBUS detection enable + 21 + 1 + + + DCDET + Data contact detection (DCD) + status + 0 + 1 + + + PDET + Primary detection (PD) + status + 1 + 1 + + + SDET + Secondary detection (SD) + status + 2 + 1 + + + PS2DET + DM pull-up detection + status + 3 + 1 + + + + + OTG_HS_CID + OTG_HS_CID + OTG_HS core ID register + 0x3C + 32 + read-write + 0x00001200 + + + PRODUCT_ID + Product ID field + 0 + 32 + + + + + OTG_HS_HPTXFSIZ + OTG_HS_HPTXFSIZ + OTG_HS Host periodic transmit FIFO size + register + 0x100 + 32 + read-write + 0x02000600 + + + PTXSA + Host periodic TxFIFO start + address + 0 + 16 + + + PTXFSIZ + Host periodic TxFIFO depth + 16 + 16 + + + + + OTG_HS_DIEPTXF1 + OTG_HS_DIEPTXF1 + OTG_HS device IN endpoint transmit FIFO size + register + 0x104 + 32 + read-write + 0x02000400 + + + INEPTXSA + IN endpoint FIFOx transmit RAM start + address + 0 + 16 + + + INEPTXFD + IN endpoint TxFIFO depth + 16 + 16 + + + + + OTG_HS_DIEPTXF2 + OTG_HS_DIEPTXF2 + OTG_HS device IN endpoint transmit FIFO size + register + 0x108 + 32 + read-write + 0x02000400 + + + INEPTXSA + IN endpoint FIFOx transmit RAM start + address + 0 + 16 + + + INEPTXFD + IN endpoint TxFIFO depth + 16 + 16 + + + + + OTG_HS_DIEPTXF3 + OTG_HS_DIEPTXF3 + OTG_HS device IN endpoint transmit FIFO size + register + 0x10C + 32 + read-write + 0x02000400 + + + INEPTXSA + IN endpoint FIFOx transmit RAM start + address + 0 + 16 + + + INEPTXFD + IN endpoint TxFIFO depth + 16 + 16 + + + + + OTG_HS_DIEPTXF4 + OTG_HS_DIEPTXF4 + OTG_HS device IN endpoint transmit FIFO size + register + 0x110 + 32 + read-write + 0x02000400 + + + INEPTXSA + IN endpoint FIFOx transmit RAM start + address + 0 + 16 + + + INEPTXFD + IN endpoint TxFIFO depth + 16 + 16 + + + + + OTG_HS_DIEPTXF5 + OTG_HS_DIEPTXF5 + OTG_HS device IN endpoint transmit FIFO size + register + 0x114 + 32 + read-write + 0x02000400 + + + INEPTXSA + IN endpoint FIFOx transmit RAM start + address + 0 + 16 + + + INEPTXFD + IN endpoint TxFIFO depth + 16 + 16 + + + + + OTG_HS_DIEPTXF6 + OTG_HS_DIEPTXF6 + OTG_HS device IN endpoint transmit FIFO size + register + 0x118 + 32 + read-write + 0x02000400 + + + INEPTXSA + IN endpoint FIFOx transmit RAM start + address + 0 + 16 + + + INEPTXFD + IN endpoint TxFIFO depth + 16 + 16 + + + + + OTG_HS_DIEPTXF7 + OTG_HS_DIEPTXF7 + OTG_HS device IN endpoint transmit FIFO size + register + 0x11C + 32 + read-write + 0x02000400 + + + INEPTXSA + IN endpoint FIFOx transmit RAM start + address + 0 + 16 + + + INEPTXFD + IN endpoint TxFIFO depth + 16 + 16 + + + + + OTG_HS_DIEPTXF8 + OTG_HS_DIEPTXF8 + OTG_HS device IN endpoint transmit FIFO size + register + 0x120 + 32 + read-write + 0x02000400 + + + INEPTXSA + IN endpoint FIFOx transmit RAM start + address + 0 + 16 + + + INEPTXFD + IN endpoint TxFIFO depth + 16 + 16 + + + + + OTG_HS_GRXSTSR_Device + OTG_HS_GRXSTSR_Device + OTG_HS Receive status debug read register + (peripheral mode mode) + OTG_HS_GRXSTSR_Host + 0x1C + 32 + read-only + 0x0 + + + EPNUM + Endpoint number + 0 + 4 + + + BCNT + Byte count + 4 + 11 + + + DPID + Data PID + 15 + 2 + + + PKTSTS + Packet status + 17 + 4 + + + FRMNUM + Frame number + 21 + 4 + + + + + OTG_HS_GRXSTSP_Device + OTG_HS_GRXSTSP_Device + OTG_HS status read and pop register + (peripheral mode) + OTG_HS_GRXSTSP_Host + 0x20 + 32 + read-only + 0x0 + + + EPNUM + Endpoint number + 0 + 4 + + + BCNT + Byte count + 4 + 11 + + + DPID + Data PID + 15 + 2 + + + PKTSTS + Packet status + 17 + 4 + + + FRMNUM + Frame number + 21 + 4 + + + + + OTG_HS_GLPMCFG + OTG_HS_GLPMCFG + OTG core LPM configuration + register + 0x54 + 32 + 0x0 + + + LPMEN + LPM support enable + 0 + 1 + read-write + + + LPMACK + LPM token acknowledge + enable + 1 + 1 + read-write + + + BESL + Best effort service + latency + 2 + 4 + read-only + + + REMWAKE + bRemoteWake value + 6 + 1 + read-only + + + L1SSEN + L1 Shallow Sleep enable + 7 + 1 + read-write + + + BESLTHRS + BESL threshold + 8 + 4 + read-write + + + L1DSEN + L1 deep sleep enable + 12 + 1 + read-write + + + LPMRST + LPM response + 13 + 2 + read-only + + + SLPSTS + Port sleep status + 15 + 1 + read-only + + + L1RSMOK + Sleep State Resume OK + 16 + 1 + read-only + + + LPMCHIDX + LPM Channel Index + 17 + 4 + read-write + + + LPMRCNT + LPM retry count + 21 + 3 + read-write + + + SNDLPM + Send LPM transaction + 24 + 1 + read-write + + + LPMRCNTSTS + LPM retry count status + 25 + 3 + read-only + + + ENBESL + Enable best effort service + latency + 28 + 1 + read-write + + + + + + + OTG2_HS_GLOBAL + 0x40080000 + + OTG_HS_EP1_OUT + OTG_HS out global interrupt + 74 + + + OTG_HS_EP1_IN + OTG_HS in global interrupt + 75 + + + OTG_HS_WKUP + OTG_HS wakeup interrupt + 76 + + + OTG_HS + OTG_HS global interrupt + 77 + + + OTG_FS_EP1_OUT + OTG_FS out global interrupt + 98 + + + OTG_FS_EP1_IN + OTG_FS in global interrupt + 99 + + + OTG_FS_WKUP + OTG_FS wakeup + 100 + + + + OTG1_HS_HOST + USB 1 on the go high speed + USB_OTG_HS + 0x40040400 + + 0x0 + 0x400 + registers + + + OTG_FS + OTG_FS global interrupt + 101 + + + + OTG_HS_HCFG + OTG_HS_HCFG + OTG_HS host configuration + register + 0x0 + 32 + 0x0 + + + FSLSPCS + FS/LS PHY clock select + 0 + 2 + read-write + + + FSLSS + FS- and LS-only support + 2 + 1 + read-only + + + + + OTG_HS_HFIR + OTG_HS_HFIR + OTG_HS Host frame interval + register + 0x4 + 32 + read-write + 0x0000EA60 + + + FRIVL + Frame interval + 0 + 16 + + + + + OTG_HS_HFNUM + OTG_HS_HFNUM + OTG_HS host frame number/frame time + remaining register + 0x8 + 32 + read-only + 0x00003FFF + + + FRNUM + Frame number + 0 + 16 + + + FTREM + Frame time remaining + 16 + 16 + + + + + OTG_HS_HPTXSTS + OTG_HS_HPTXSTS + OTG_HS_Host periodic transmit FIFO/queue + status register + 0x10 + 32 + 0x00080100 + + + PTXFSAVL + Periodic transmit data FIFO space + available + 0 + 16 + read-write + + + PTXQSAV + Periodic transmit request queue space + available + 16 + 8 + read-only + + + PTXQTOP + Top of the periodic transmit request + queue + 24 + 8 + read-only + + + + + OTG_HS_HAINT + OTG_HS_HAINT + OTG_HS Host all channels interrupt + register + 0x14 + 32 + read-only + 0x0 + + + HAINT + Channel interrupts + 0 + 16 + + + + + OTG_HS_HAINTMSK + OTG_HS_HAINTMSK + OTG_HS host all channels interrupt mask + register + 0x18 + 32 + read-write + 0x0 + + + HAINTM + Channel interrupt mask + 0 + 16 + + + + + OTG_HS_HPRT + OTG_HS_HPRT + OTG_HS host port control and status + register + 0x40 + 32 + 0x0 + + + PCSTS + Port connect status + 0 + 1 + read-only + + + PCDET + Port connect detected + 1 + 1 + read-write + + + PENA + Port enable + 2 + 1 + read-write + + + PENCHNG + Port enable/disable change + 3 + 1 + read-write + + + POCA + Port overcurrent active + 4 + 1 + read-only + + + POCCHNG + Port overcurrent change + 5 + 1 + read-write + + + PRES + Port resume + 6 + 1 + read-write + + + PSUSP + Port suspend + 7 + 1 + read-write + + + PRST + Port reset + 8 + 1 + read-write + + + PLSTS + Port line status + 10 + 2 + read-only + + + PPWR + Port power + 12 + 1 + read-write + + + PTCTL + Port test control + 13 + 4 + read-write + + + PSPD + Port speed + 17 + 2 + read-only + + + + + OTG_HS_HCCHAR0 + OTG_HS_HCCHAR0 + OTG_HS host channel-0 characteristics + register + 0x100 + 32 + read-write + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MC + Multi Count (MC) / Error Count + (EC) + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + OTG_HS_HCCHAR1 + OTG_HS_HCCHAR1 + OTG_HS host channel-1 characteristics + register + 0x120 + 32 + read-write + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MC + Multi Count (MC) / Error Count + (EC) + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + OTG_HS_HCCHAR2 + OTG_HS_HCCHAR2 + OTG_HS host channel-2 characteristics + register + 0x140 + 32 + read-write + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MC + Multi Count (MC) / Error Count + (EC) + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + OTG_HS_HCCHAR3 + OTG_HS_HCCHAR3 + OTG_HS host channel-3 characteristics + register + 0x160 + 32 + read-write + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MC + Multi Count (MC) / Error Count + (EC) + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + OTG_HS_HCCHAR4 + OTG_HS_HCCHAR4 + OTG_HS host channel-4 characteristics + register + 0x180 + 32 + read-write + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MC + Multi Count (MC) / Error Count + (EC) + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + OTG_HS_HCCHAR5 + OTG_HS_HCCHAR5 + OTG_HS host channel-5 characteristics + register + 0x1A0 + 32 + read-write + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MC + Multi Count (MC) / Error Count + (EC) + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + OTG_HS_HCCHAR6 + OTG_HS_HCCHAR6 + OTG_HS host channel-6 characteristics + register + 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OTG_HS_HCCHAR8 + OTG_HS host channel-8 characteristics + register + 0x200 + 32 + read-write + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MC + Multi Count (MC) / Error Count + (EC) + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + OTG_HS_HCCHAR9 + OTG_HS_HCCHAR9 + OTG_HS host channel-9 characteristics + register + 0x220 + 32 + read-write + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MC + Multi Count (MC) / Error Count + (EC) + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + 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ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + OTG_HS_HCSPLT0 + OTG_HS_HCSPLT0 + OTG_HS host channel-0 split control + register + 0x104 + 32 + read-write + 0x0 + + + PRTADDR + Port address + 0 + 7 + + + HUBADDR + Hub address + 7 + 7 + + + XACTPOS + XACTPOS + 14 + 2 + + + COMPLSPLT + Do complete split + 16 + 1 + + + SPLITEN + Split enable + 31 + 1 + + + + + OTG_HS_HCSPLT1 + OTG_HS_HCSPLT1 + OTG_HS host channel-1 split control + register + 0x124 + 32 + read-write + 0x0 + + + PRTADDR + Port address + 0 + 7 + + + HUBADDR + Hub address + 7 + 7 + + + XACTPOS + XACTPOS + 14 + 2 + + + COMPLSPLT + Do complete split + 16 + 1 + + + SPLITEN + Split enable + 31 + 1 + + + + + OTG_HS_HCSPLT2 + OTG_HS_HCSPLT2 + OTG_HS host channel-2 split control + register + 0x144 + 32 + read-write + 0x0 + + + PRTADDR + Port address + 0 + 7 + + + HUBADDR + Hub address + 7 + 7 + + + XACTPOS + XACTPOS + 14 + 2 + + + COMPLSPLT + Do complete split + 16 + 1 + + + SPLITEN + Split enable + 31 + 1 + + + + + OTG_HS_HCSPLT3 + OTG_HS_HCSPLT3 + OTG_HS host channel-3 split control + register + 0x164 + 32 + read-write + 0x0 + + + PRTADDR + Port address + 0 + 7 + + + HUBADDR + Hub address + 7 + 7 + + + XACTPOS + XACTPOS + 14 + 2 + + + COMPLSPLT + Do complete split + 16 + 1 + + + SPLITEN + Split enable + 31 + 1 + + + + + OTG_HS_HCSPLT4 + OTG_HS_HCSPLT4 + OTG_HS host channel-4 split control + register + 0x184 + 32 + read-write + 0x0 + + + PRTADDR + Port address + 0 + 7 + + + HUBADDR + Hub address + 7 + 7 + + + XACTPOS + XACTPOS + 14 + 2 + + + COMPLSPLT + Do complete split + 16 + 1 + + + SPLITEN + Split enable + 31 + 1 + + + + + OTG_HS_HCSPLT5 + OTG_HS_HCSPLT5 + OTG_HS host channel-5 split control + register + 0x1A4 + 32 + read-write + 0x0 + + + PRTADDR + Port address + 0 + 7 + + + HUBADDR + Hub address + 7 + 7 + + + XACTPOS + XACTPOS + 14 + 2 + + + COMPLSPLT + Do complete split + 16 + 1 + + + SPLITEN + Split enable + 31 + 1 + + + + + OTG_HS_HCSPLT6 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1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + OTG_HS_HCINTMSK3 + OTG_HS_HCINTMSK3 + OTG_HS host channel-3 interrupt mask + register + 0x16C + 32 + read-write + 0x0 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + OTG_HS_HCINTMSK4 + OTG_HS_HCINTMSK4 + OTG_HS host channel-4 interrupt mask + register + 0x18C + 32 + read-write + 0x0 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + OTG_HS_HCINTMSK5 + OTG_HS_HCINTMSK5 + OTG_HS host channel-5 interrupt mask + register + 0x1AC + 32 + read-write + 0x0 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + OTG_HS_HCINTMSK6 + OTG_HS_HCINTMSK6 + OTG_HS host channel-6 interrupt mask + register + 0x1CC + 32 + read-write + 0x0 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + OTG_HS_HCINTMSK7 + OTG_HS_HCINTMSK7 + OTG_HS host channel-7 interrupt mask + register + 0x1EC + 32 + read-write + 0x0 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + OTG_HS_HCINTMSK8 + OTG_HS_HCINTMSK8 + OTG_HS host channel-8 interrupt mask + register + 0x20C + 32 + read-write + 0x0 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + OTG_HS_HCINTMSK9 + OTG_HS_HCINTMSK9 + OTG_HS host channel-9 interrupt mask + register + 0x22C + 32 + read-write + 0x0 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + OTG_HS_HCINTMSK10 + OTG_HS_HCINTMSK10 + OTG_HS host channel-10 interrupt mask + register + 0x24C + 32 + read-write + 0x0 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + OTG_HS_HCINTMSK11 + OTG_HS_HCINTMSK11 + OTG_HS host channel-11 interrupt mask + register + 0x26C + 32 + read-write + 0x0 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + OTG_HS_HCTSIZ0 + OTG_HS_HCTSIZ0 + OTG_HS host channel-11 transfer size + register + 0x110 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + OTG_HS_HCTSIZ1 + OTG_HS_HCTSIZ1 + OTG_HS host channel-1 transfer size + register + 0x130 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + OTG_HS_HCTSIZ2 + OTG_HS_HCTSIZ2 + OTG_HS host channel-2 transfer size + register + 0x150 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + OTG_HS_HCTSIZ3 + OTG_HS_HCTSIZ3 + OTG_HS host channel-3 transfer size + register + 0x170 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + OTG_HS_HCTSIZ4 + OTG_HS_HCTSIZ4 + OTG_HS host channel-4 transfer size + register + 0x190 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + OTG_HS_HCTSIZ5 + OTG_HS_HCTSIZ5 + OTG_HS host channel-5 transfer size + register + 0x1B0 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + OTG_HS_HCTSIZ6 + OTG_HS_HCTSIZ6 + OTG_HS host channel-6 transfer size + register + 0x1D0 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + OTG_HS_HCTSIZ7 + OTG_HS_HCTSIZ7 + OTG_HS host channel-7 transfer size + register + 0x1F0 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + OTG_HS_HCTSIZ8 + OTG_HS_HCTSIZ8 + OTG_HS host channel-8 transfer size + register + 0x210 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + OTG_HS_HCTSIZ9 + OTG_HS_HCTSIZ9 + OTG_HS host channel-9 transfer size + register + 0x230 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + OTG_HS_HCTSIZ10 + OTG_HS_HCTSIZ10 + OTG_HS host channel-10 transfer size + register + 0x250 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + OTG_HS_HCTSIZ11 + OTG_HS_HCTSIZ11 + OTG_HS host channel-11 transfer size + register + 0x270 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + OTG_HS_HCDMA0 + OTG_HS_HCDMA0 + OTG_HS host channel-0 DMA address + register + 0x114 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_HCDMA1 + OTG_HS_HCDMA1 + OTG_HS host channel-1 DMA address + register + 0x134 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_HCDMA2 + OTG_HS_HCDMA2 + OTG_HS host channel-2 DMA address + register + 0x154 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_HCDMA3 + OTG_HS_HCDMA3 + OTG_HS host channel-3 DMA address + register + 0x174 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_HCDMA4 + OTG_HS_HCDMA4 + OTG_HS host channel-4 DMA address + register + 0x194 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_HCDMA5 + OTG_HS_HCDMA5 + OTG_HS host channel-5 DMA address + register + 0x1B4 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_HCDMA6 + OTG_HS_HCDMA6 + OTG_HS host channel-6 DMA address + register + 0x1D4 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_HCDMA7 + OTG_HS_HCDMA7 + OTG_HS host channel-7 DMA address + register + 0x1F4 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_HCDMA8 + OTG_HS_HCDMA8 + OTG_HS host channel-8 DMA address + register + 0x214 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_HCDMA9 + OTG_HS_HCDMA9 + OTG_HS host channel-9 DMA address + register + 0x234 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_HCDMA10 + OTG_HS_HCDMA10 + OTG_HS host channel-10 DMA address + register + 0x254 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_HCDMA11 + OTG_HS_HCDMA11 + OTG_HS host channel-11 DMA address + register + 0x274 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_HCCHAR12 + OTG_HS_HCCHAR12 + OTG_HS host channel-12 characteristics + register + 0x278 + 32 + read-write + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MC + Multi Count (MC) / Error Count + (EC) + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + OTG_HS_HCSPLT12 + OTG_HS_HCSPLT12 + OTG_HS host channel-12 split control + register + 0x27C + 32 + read-write + 0x0 + + + PRTADDR + Port address + 0 + 7 + + + HUBADDR + Hub address + 7 + 7 + + + XACTPOS + XACTPOS + 14 + 2 + + + COMPLSPLT + Do complete split + 16 + 1 + + + SPLITEN + Split enable + 31 + 1 + + + + + OTG_HS_HCINT12 + OTG_HS_HCINT12 + OTG_HS host channel-12 interrupt + register + 0x280 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + Response received + interrupt + 6 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + OTG_HS_HCINTMSK12 + OTG_HS_HCINTMSK12 + OTG_HS host channel-12 interrupt mask + register + 0x284 + 32 + read-write + 0x0 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + Response received + interrupt + 6 + 1 + + + TXERRM + Transaction error + 7 + 1 + + + BBERRM + Babble error + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + OTG_HS_HCTSIZ12 + OTG_HS_HCTSIZ12 + OTG_HS host channel-12 transfer size + register + 0x288 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + OTG_HS_HCDMA12 + OTG_HS_HCDMA12 + OTG_HS host channel-12 DMA address + register + 0x28C + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_HCCHAR13 + OTG_HS_HCCHAR13 + OTG_HS host channel-13 characteristics + register + 0x290 + 32 + read-write + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MC + Multi Count (MC) / Error Count + (EC) + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + OTG_HS_HCSPLT13 + OTG_HS_HCSPLT13 + OTG_HS host channel-13 split control + register + 0x294 + 32 + read-write + 0x0 + + + PRTADDR + Port address + 0 + 7 + + + HUBADDR + Hub address + 7 + 7 + + + XACTPOS + XACTPOS + 14 + 2 + + + COMPLSPLT + Do complete split + 16 + 1 + + + SPLITEN + Split enable + 31 + 1 + + + + + OTG_HS_HCINT13 + OTG_HS_HCINT13 + OTG_HS host channel-13 interrupt + register + 0x298 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + Response received + interrupt + 6 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + OTG_HS_HCINTMSK13 + OTG_HS_HCINTMSK13 + OTG_HS host channel-13 interrupt mask + register + 0x29C + 32 + read-write + 0x0 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALLM + STALLM response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + Response received + interrupt + 6 + 1 + + + TXERRM + Transaction error + 7 + 1 + + + BBERRM + Babble error + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + OTG_HS_HCTSIZ13 + OTG_HS_HCTSIZ13 + OTG_HS host channel-13 transfer size + register + 0x2A0 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + OTG_HS_HCDMA13 + OTG_HS_HCDMA13 + OTG_HS host channel-13 DMA address + register + 0x2A4 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_HCCHAR14 + OTG_HS_HCCHAR14 + OTG_HS host channel-14 characteristics + register + 0x2A8 + 32 + read-write + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MC + Multi Count (MC) / Error Count + (EC) + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + OTG_HS_HCSPLT14 + OTG_HS_HCSPLT14 + OTG_HS host channel-14 split control + register + 0x2AC + 32 + read-write + 0x0 + + + PRTADDR + Port address + 0 + 7 + + + HUBADDR + Hub address + 7 + 7 + + + XACTPOS + XACTPOS + 14 + 2 + + + COMPLSPLT + Do complete split + 16 + 1 + + + SPLITEN + Split enable + 31 + 1 + + + + + OTG_HS_HCINT14 + OTG_HS_HCINT14 + OTG_HS host channel-14 interrupt + register + 0x2B0 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + Response received + interrupt + 6 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + OTG_HS_HCINTMSK14 + OTG_HS_HCINTMSK14 + OTG_HS host channel-14 interrupt mask + register + 0x2B4 + 32 + read-write + 0x0 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAKM response received interrupt + mask + 4 + 1 + + + ACKM + ACKM response received/transmitted + interrupt mask + 5 + 1 + + + NYET + Response received + interrupt + 6 + 1 + + + TXERRM + Transaction error + 7 + 1 + + + BBERRM + Babble error + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + OTG_HS_HCTSIZ14 + OTG_HS_HCTSIZ14 + OTG_HS host channel-14 transfer size + register + 0x2B8 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + OTG_HS_HCDMA14 + OTG_HS_HCDMA14 + OTG_HS host channel-14 DMA address + register + 0x2BC + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_HCCHAR15 + OTG_HS_HCCHAR15 + OTG_HS host channel-15 characteristics + register + 0x2C0 + 32 + read-write + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MC + Multi Count (MC) / Error Count + (EC) + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + OTG_HS_HCSPLT15 + OTG_HS_HCSPLT15 + OTG_HS host channel-15 split control + register + 0x2C4 + 32 + read-write + 0x0 + + + PRTADDR + Port address + 0 + 7 + + + HUBADDR + Hub address + 7 + 7 + + + XACTPOS + XACTPOS + 14 + 2 + + + COMPLSPLT + Do complete split + 16 + 1 + + + SPLITEN + Split enable + 31 + 1 + + + + + OTG_HS_HCINT15 + OTG_HS_HCINT15 + OTG_HS host channel-15 interrupt + register + 0x2C8 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + Response received + interrupt + 6 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + OTG_HS_HCINTMSK15 + OTG_HS_HCINTMSK15 + OTG_HS host channel-15 interrupt mask + register + 0x2CC + 32 + read-write + 0x0 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALL + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + Response received + interrupt + 6 + 1 + + + TXERRM + Transaction error + 7 + 1 + + + BBERRM + Babble error + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + OTG_HS_HCTSIZ15 + OTG_HS_HCTSIZ15 + OTG_HS host channel-15 transfer size + register + 0x2D0 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + OTG_HS_HCDMA15 + OTG_HS_HCDMA15 + OTG_HS host channel-15 DMA address + register + 0x2D4 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + + + OTG2_HS_HOST + 0x40080400 + + + OTG1_HS_DEVICE + USB 1 on the go high speed + USB_OTG_HS + 0x40040800 + + 0x0 + 0x400 + registers + + + + OTG_HS_DCFG + OTG_HS_DCFG + OTG_HS device configuration + register + 0x0 + 32 + read-write + 0x02200000 + + + DSPD + Device speed + 0 + 2 + + + NZLSOHSK + Nonzero-length status OUT + handshake + 2 + 1 + + + DAD + Device address + 4 + 7 + + + PFIVL + Periodic (micro)frame + interval + 11 + 2 + + + PERSCHIVL + Periodic scheduling + interval + 24 + 2 + + + + + OTG_HS_DCTL + OTG_HS_DCTL + OTG_HS device control register + 0x4 + 32 + 0x0 + + + RWUSIG + Remote wakeup signaling + 0 + 1 + read-write + + + SDIS + Soft disconnect + 1 + 1 + read-write + + + GINSTS + Global IN NAK status + 2 + 1 + read-only + + + GONSTS + Global OUT NAK status + 3 + 1 + read-only + + + TCTL + Test control + 4 + 3 + read-write + + + SGINAK + Set global IN NAK + 7 + 1 + write-only + + + CGINAK + Clear global IN NAK + 8 + 1 + write-only + + + SGONAK + Set global OUT NAK + 9 + 1 + write-only + + + CGONAK + Clear global OUT NAK + 10 + 1 + write-only + + + POPRGDNE + Power-on programming done + 11 + 1 + read-write + + + + + OTG_HS_DSTS + OTG_HS_DSTS + OTG_HS device status register + 0x8 + 32 + read-only + 0x00000010 + + + SUSPSTS + Suspend status + 0 + 1 + + + ENUMSPD + Enumerated speed + 1 + 2 + + + EERR + Erratic error + 3 + 1 + + + FNSOF + Frame number of the received + SOF + 8 + 14 + + + + + OTG_HS_DIEPMSK + OTG_HS_DIEPMSK + OTG_HS device IN endpoint common interrupt + mask register + 0x10 + 32 + read-write + 0x0 + + + XFRCM + Transfer completed interrupt + mask + 0 + 1 + + + EPDM + Endpoint disabled interrupt + mask + 1 + 1 + + + TOM + Timeout condition mask (nonisochronous + endpoints) + 3 + 1 + + + ITTXFEMSK + IN token received when TxFIFO empty + mask + 4 + 1 + + + INEPNMM + IN token received with EP mismatch + mask + 5 + 1 + + + INEPNEM + IN endpoint NAK effective + mask + 6 + 1 + + + TXFURM + FIFO underrun mask + 8 + 1 + + + BIM + BNA interrupt mask + 9 + 1 + + + + + OTG_HS_DOEPMSK + OTG_HS_DOEPMSK + OTG_HS device OUT endpoint common interrupt + mask register + 0x14 + 32 + read-write + 0x0 + + + XFRCM + Transfer completed interrupt + mask + 0 + 1 + + + EPDM + Endpoint disabled interrupt + mask + 1 + 1 + + + STUPM + SETUP phase done mask + 3 + 1 + + + OTEPDM + OUT token received when endpoint + disabled mask + 4 + 1 + + + B2BSTUP + Back-to-back SETUP packets received + mask + 6 + 1 + + + OPEM + OUT packet error mask + 8 + 1 + + + BOIM + BNA interrupt mask + 9 + 1 + + + + + OTG_HS_DAINT + OTG_HS_DAINT + OTG_HS device all endpoints interrupt + register + 0x18 + 32 + read-only + 0x0 + + + IEPINT + IN endpoint interrupt bits + 0 + 16 + + + OEPINT + OUT endpoint interrupt + bits + 16 + 16 + + + + + OTG_HS_DAINTMSK + OTG_HS_DAINTMSK + OTG_HS all endpoints interrupt mask + register + 0x1C + 32 + read-write + 0x0 + + + IEPM + IN EP interrupt mask bits + 0 + 16 + + + OEPM + OUT EP interrupt mask bits + 16 + 16 + + + + + OTG_HS_DVBUSDIS + OTG_HS_DVBUSDIS + OTG_HS device VBUS discharge time + register + 0x28 + 32 + read-write + 0x000017D7 + + + VBUSDT + Device VBUS discharge time + 0 + 16 + + + + + OTG_HS_DVBUSPULSE + OTG_HS_DVBUSPULSE + OTG_HS device VBUS pulsing time + register + 0x2C + 32 + read-write + 0x000005B8 + + + DVBUSP + Device VBUS pulsing time + 0 + 12 + + + + + OTG_HS_DTHRCTL + OTG_HS_DTHRCTL + OTG_HS Device threshold control + register + 0x30 + 32 + read-write + 0x0 + + + NONISOTHREN + Nonisochronous IN endpoints threshold + enable + 0 + 1 + + + ISOTHREN + ISO IN endpoint threshold + enable + 1 + 1 + + + TXTHRLEN + Transmit threshold length + 2 + 9 + + + RXTHREN + Receive threshold enable + 16 + 1 + + + RXTHRLEN + Receive threshold length + 17 + 9 + + + ARPEN + Arbiter parking enable + 27 + 1 + + + + + OTG_HS_DIEPEMPMSK + OTG_HS_DIEPEMPMSK + OTG_HS device IN endpoint FIFO empty + interrupt mask register + 0x34 + 32 + read-write + 0x0 + + + INEPTXFEM + IN EP Tx FIFO empty interrupt mask + bits + 0 + 16 + + + + + OTG_HS_DEACHINT + OTG_HS_DEACHINT + OTG_HS device each endpoint interrupt + register + 0x38 + 32 + read-write + 0x0 + + + IEP1INT + IN endpoint 1interrupt bit + 1 + 1 + + + OEP1INT + OUT endpoint 1 interrupt + bit + 17 + 1 + + + + + OTG_HS_DEACHINTMSK + OTG_HS_DEACHINTMSK + OTG_HS device each endpoint interrupt + register mask + 0x3C + 32 + read-write + 0x0 + + + IEP1INTM + IN Endpoint 1 interrupt mask + bit + 1 + 1 + + + OEP1INTM + OUT Endpoint 1 interrupt mask + bit + 17 + 1 + + + + + OTG_HS_DIEPCTL0 + OTG_HS_DIEPCTL0 + OTG device endpoint-0 control + register + 0x100 + 32 + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + read-write + + + USBAEP + USB active endpoint + 15 + 1 + read-write + + + EONUM_DPID + Even/odd frame + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYP + Endpoint type + 18 + 2 + read-write + + + Stall + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + Set DATA0 PID + 28 + 1 + write-only + + + SODDFRM + Set odd frame + 29 + 1 + write-only + + + EPDIS + Endpoint disable + 30 + 1 + read-write + + + EPENA + Endpoint enable + 31 + 1 + read-write + + + + + OTG_HS_DIEPCTL1 + OTG_HS_DIEPCTL1 + OTG device endpoint-1 control + register + 0x120 + 32 + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + read-write + + + USBAEP + USB active endpoint + 15 + 1 + read-write + + + EONUM_DPID + Even/odd frame + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYP + Endpoint type + 18 + 2 + read-write + + + Stall + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + Set DATA0 PID + 28 + 1 + write-only + + + SODDFRM + Set odd frame + 29 + 1 + write-only + + + EPDIS + Endpoint disable + 30 + 1 + read-write + + + EPENA + Endpoint enable + 31 + 1 + read-write + + + + + OTG_HS_DIEPCTL2 + OTG_HS_DIEPCTL2 + OTG device endpoint-2 control + register + 0x140 + 32 + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + read-write + + + USBAEP + USB active endpoint + 15 + 1 + read-write + + + EONUM_DPID + Even/odd frame + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYP + Endpoint type + 18 + 2 + read-write + + + Stall + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + Set DATA0 PID + 28 + 1 + write-only + + + SODDFRM + Set odd frame + 29 + 1 + write-only + + + EPDIS + Endpoint disable + 30 + 1 + read-write + + + EPENA + Endpoint enable + 31 + 1 + read-write + + + + + OTG_HS_DIEPCTL3 + OTG_HS_DIEPCTL3 + OTG device endpoint-3 control + register + 0x160 + 32 + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + read-write + + + USBAEP + USB active endpoint + 15 + 1 + read-write + + + EONUM_DPID + Even/odd frame + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYP + Endpoint type + 18 + 2 + read-write + + + Stall + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + Set DATA0 PID + 28 + 1 + write-only + + + SODDFRM + Set odd frame + 29 + 1 + write-only + + + EPDIS + Endpoint disable + 30 + 1 + read-write + + + EPENA + Endpoint enable + 31 + 1 + read-write + + + + + OTG_HS_DIEPCTL4 + OTG_HS_DIEPCTL4 + OTG device endpoint-4 control + register + 0x180 + 32 + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + read-write + + + USBAEP + USB active endpoint + 15 + 1 + read-write + + + EONUM_DPID + Even/odd frame + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYP + Endpoint type + 18 + 2 + read-write + + + Stall + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + Set DATA0 PID + 28 + 1 + write-only + + + SODDFRM + Set odd frame + 29 + 1 + write-only + + + EPDIS + Endpoint disable + 30 + 1 + read-write + + + EPENA + Endpoint enable + 31 + 1 + read-write + + + + + OTG_HS_DIEPCTL5 + OTG_HS_DIEPCTL5 + OTG device endpoint-5 control + register + 0x1A0 + 32 + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + read-write + + + USBAEP + USB active endpoint + 15 + 1 + read-write + + + EONUM_DPID + Even/odd frame + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYP + Endpoint type + 18 + 2 + read-write + + + Stall + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + Set DATA0 PID + 28 + 1 + write-only + + + SODDFRM + Set odd frame + 29 + 1 + write-only + + + EPDIS + Endpoint disable + 30 + 1 + read-write + + + EPENA + Endpoint enable + 31 + 1 + read-write + + + + + OTG_HS_DIEPCTL6 + OTG_HS_DIEPCTL6 + OTG device endpoint-6 control + register + 0x1C0 + 32 + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + read-write + + + USBAEP + USB active endpoint + 15 + 1 + read-write + + + EONUM_DPID + Even/odd frame + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYP + Endpoint type + 18 + 2 + read-write + + + Stall + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + Set DATA0 PID + 28 + 1 + write-only + + + SODDFRM + Set odd frame + 29 + 1 + write-only + + + EPDIS + Endpoint disable + 30 + 1 + read-write + + + EPENA + Endpoint enable + 31 + 1 + read-write + + + + + OTG_HS_DIEPCTL7 + OTG_HS_DIEPCTL7 + OTG device endpoint-7 control + register + 0x1E0 + 32 + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + read-write + + + USBAEP + USB active endpoint + 15 + 1 + read-write + + + EONUM_DPID + Even/odd frame + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYP + Endpoint type + 18 + 2 + read-write + + + Stall + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + Set DATA0 PID + 28 + 1 + write-only + + + SODDFRM + Set odd frame + 29 + 1 + write-only + + + EPDIS + Endpoint disable + 30 + 1 + read-write + + + EPENA + Endpoint enable + 31 + 1 + read-write + + + + + OTG_HS_DIEPINT0 + OTG_HS_DIEPINT0 + OTG device endpoint-0 interrupt + register + 0x108 + 32 + 0x00000080 + + + XFRC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TOC + Timeout condition + 3 + 1 + read-write + + + ITTXFE + IN token received when TxFIFO is + empty + 4 + 1 + read-write + + + INEPNE + IN endpoint NAK effective + 6 + 1 + read-write + + + TXFE + Transmit FIFO empty + 7 + 1 + read-only + + + TXFIFOUDRN + Transmit Fifo Underrun + 8 + 1 + read-write + + + BNA + Buffer not available + interrupt + 9 + 1 + read-write + + + PKTDRPSTS + Packet dropped status + 11 + 1 + read-write + + + BERR + Babble error interrupt + 12 + 1 + read-write + + + NAK + NAK interrupt + 13 + 1 + read-write + + + + + OTG_HS_DIEPINT1 + OTG_HS_DIEPINT1 + OTG device endpoint-1 interrupt + register + 0x128 + 32 + 0x0 + + + XFRC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TOC + Timeout condition + 3 + 1 + read-write + + + ITTXFE + IN token received when TxFIFO is + empty + 4 + 1 + read-write + + + INEPNE + IN endpoint NAK effective + 6 + 1 + read-write + + + TXFE + Transmit FIFO empty + 7 + 1 + read-only + + + TXFIFOUDRN + Transmit Fifo Underrun + 8 + 1 + read-write + + + BNA + Buffer not available + interrupt + 9 + 1 + read-write + + + PKTDRPSTS + Packet dropped status + 11 + 1 + read-write + + + BERR + Babble error interrupt + 12 + 1 + read-write + + + NAK + NAK interrupt + 13 + 1 + read-write + + + + + OTG_HS_DIEPINT2 + OTG_HS_DIEPINT2 + OTG device endpoint-2 interrupt + register + 0x148 + 32 + 0x0 + + + XFRC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TOC + Timeout condition + 3 + 1 + read-write + + + ITTXFE + IN token received when TxFIFO is + empty + 4 + 1 + read-write + + + INEPNE + IN endpoint NAK effective + 6 + 1 + read-write + + + TXFE + Transmit FIFO empty + 7 + 1 + read-only + + + TXFIFOUDRN + Transmit Fifo Underrun + 8 + 1 + read-write + + + BNA + Buffer not available + interrupt + 9 + 1 + read-write + + + PKTDRPSTS + Packet dropped status + 11 + 1 + read-write + + + BERR + Babble error interrupt + 12 + 1 + read-write + + + NAK + NAK interrupt + 13 + 1 + read-write + + + + + OTG_HS_DIEPINT3 + OTG_HS_DIEPINT3 + OTG device endpoint-3 interrupt + register + 0x168 + 32 + 0x0 + + + XFRC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TOC + Timeout condition + 3 + 1 + read-write + + + ITTXFE + IN token received when TxFIFO is + empty + 4 + 1 + read-write + + + INEPNE + IN endpoint NAK effective + 6 + 1 + read-write + + + TXFE + Transmit FIFO empty + 7 + 1 + read-only + + + TXFIFOUDRN + Transmit Fifo Underrun + 8 + 1 + read-write + + + BNA + Buffer not available + interrupt + 9 + 1 + read-write + + + PKTDRPSTS + Packet dropped status + 11 + 1 + read-write + + + BERR + Babble error interrupt + 12 + 1 + read-write + + + NAK + NAK interrupt + 13 + 1 + read-write + + + + + OTG_HS_DIEPINT4 + OTG_HS_DIEPINT4 + OTG device endpoint-4 interrupt + register + 0x188 + 32 + 0x0 + + + XFRC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TOC + Timeout condition + 3 + 1 + read-write + + + ITTXFE + IN token received when TxFIFO is + empty + 4 + 1 + read-write + + + INEPNE + IN endpoint NAK effective + 6 + 1 + read-write + + + TXFE + Transmit FIFO empty + 7 + 1 + read-only + + + TXFIFOUDRN + Transmit Fifo Underrun + 8 + 1 + read-write + + + BNA + Buffer not available + interrupt + 9 + 1 + read-write + + + PKTDRPSTS + Packet dropped status + 11 + 1 + read-write + + + BERR + Babble error interrupt + 12 + 1 + read-write + + + NAK + NAK interrupt + 13 + 1 + read-write + + + + + OTG_HS_DIEPINT5 + OTG_HS_DIEPINT5 + OTG device endpoint-5 interrupt + register + 0x1A8 + 32 + 0x0 + + + XFRC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TOC + Timeout condition + 3 + 1 + read-write + + + ITTXFE + IN token received when TxFIFO is + empty + 4 + 1 + read-write + + + INEPNE + IN endpoint NAK effective + 6 + 1 + read-write + + + TXFE + Transmit FIFO empty + 7 + 1 + read-only + + + TXFIFOUDRN + Transmit Fifo Underrun + 8 + 1 + read-write + + + BNA + Buffer not available + interrupt + 9 + 1 + read-write + + + PKTDRPSTS + Packet dropped status + 11 + 1 + read-write + + + BERR + Babble error interrupt + 12 + 1 + read-write + + + NAK + NAK interrupt + 13 + 1 + read-write + + + + + OTG_HS_DIEPINT6 + OTG_HS_DIEPINT6 + OTG device endpoint-6 interrupt + register + 0x1C8 + 32 + 0x0 + + + XFRC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TOC + Timeout condition + 3 + 1 + read-write + + + ITTXFE + IN token received when TxFIFO is + empty + 4 + 1 + read-write + + + INEPNE + IN endpoint NAK effective + 6 + 1 + read-write + + + TXFE + Transmit FIFO empty + 7 + 1 + read-only + + + TXFIFOUDRN + Transmit Fifo Underrun + 8 + 1 + read-write + + + BNA + Buffer not available + interrupt + 9 + 1 + read-write + + + PKTDRPSTS + Packet dropped status + 11 + 1 + read-write + + + BERR + Babble error interrupt + 12 + 1 + read-write + + + NAK + NAK interrupt + 13 + 1 + read-write + + + + + OTG_HS_DIEPINT7 + OTG_HS_DIEPINT7 + OTG device endpoint-7 interrupt + register + 0x1E8 + 32 + 0x0 + + + XFRC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TOC + Timeout condition + 3 + 1 + read-write + + + ITTXFE + IN token received when TxFIFO is + empty + 4 + 1 + read-write + + + INEPNE + IN endpoint NAK effective + 6 + 1 + read-write + + + TXFE + Transmit FIFO empty + 7 + 1 + read-only + + + TXFIFOUDRN + Transmit Fifo Underrun + 8 + 1 + read-write + + + BNA + Buffer not available + interrupt + 9 + 1 + read-write + + + PKTDRPSTS + Packet dropped status + 11 + 1 + read-write + + + BERR + Babble error interrupt + 12 + 1 + read-write + + + NAK + NAK interrupt + 13 + 1 + read-write + + + + + OTG_HS_DIEPTSIZ0 + OTG_HS_DIEPTSIZ0 + OTG_HS device IN endpoint 0 transfer size + register + 0x110 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 7 + + + PKTCNT + Packet count + 19 + 2 + + + + + OTG_HS_DIEPDMA1 + OTG_HS_DIEPDMA1 + OTG_HS device endpoint-1 DMA address + register + 0x114 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_DIEPDMA2 + OTG_HS_DIEPDMA2 + OTG_HS device endpoint-2 DMA address + register + 0x134 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_DIEPDMA3 + OTG_HS_DIEPDMA3 + OTG_HS device endpoint-3 DMA address + register + 0x154 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_DIEPDMA4 + OTG_HS_DIEPDMA4 + OTG_HS device endpoint-4 DMA address + register + 0x174 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_DIEPDMA5 + OTG_HS_DIEPDMA5 + OTG_HS device endpoint-5 DMA address + register + 0x194 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_DTXFSTS0 + OTG_HS_DTXFSTS0 + OTG_HS device IN endpoint transmit FIFO + status register + 0x118 + 32 + read-only + 0x0 + + + INEPTFSAV + IN endpoint TxFIFO space + avail + 0 + 16 + + + + + OTG_HS_DTXFSTS1 + OTG_HS_DTXFSTS1 + OTG_HS device IN endpoint transmit FIFO + status register + 0x138 + 32 + read-only + 0x0 + + + INEPTFSAV + IN endpoint TxFIFO space + avail + 0 + 16 + + + + + OTG_HS_DTXFSTS2 + OTG_HS_DTXFSTS2 + OTG_HS device IN endpoint transmit FIFO + status register + 0x158 + 32 + read-only + 0x0 + + + INEPTFSAV + IN endpoint TxFIFO space + avail + 0 + 16 + + + + + OTG_HS_DTXFSTS3 + OTG_HS_DTXFSTS3 + OTG_HS device IN endpoint transmit FIFO + status register + 0x178 + 32 + read-only + 0x0 + + + INEPTFSAV + IN endpoint TxFIFO space + avail + 0 + 16 + + + + + OTG_HS_DTXFSTS4 + OTG_HS_DTXFSTS4 + OTG_HS device IN endpoint transmit FIFO + status register + 0x198 + 32 + read-only + 0x0 + + + INEPTFSAV + IN endpoint TxFIFO space + avail + 0 + 16 + + + + + OTG_HS_DTXFSTS5 + OTG_HS_DTXFSTS5 + OTG_HS device IN endpoint transmit FIFO + status register + 0x1B8 + 32 + read-only + 0x0 + + + INEPTFSAV + IN endpoint TxFIFO space + avail + 0 + 16 + + + + + OTG_HS_DIEPTSIZ1 + OTG_HS_DIEPTSIZ1 + OTG_HS device endpoint transfer size + register + 0x130 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MCNT + Multi count + 29 + 2 + + + + + OTG_HS_DIEPTSIZ2 + OTG_HS_DIEPTSIZ2 + OTG_HS device endpoint transfer size + register + 0x150 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MCNT + Multi count + 29 + 2 + + + + + OTG_HS_DIEPTSIZ3 + OTG_HS_DIEPTSIZ3 + OTG_HS device endpoint transfer size + register + 0x170 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MCNT + Multi count + 29 + 2 + + + + + OTG_HS_DIEPTSIZ4 + OTG_HS_DIEPTSIZ4 + OTG_HS device endpoint transfer size + register + 0x190 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MCNT + Multi count + 29 + 2 + + + + + OTG_HS_DIEPTSIZ5 + OTG_HS_DIEPTSIZ5 + OTG_HS device endpoint transfer size + register + 0x1B0 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MCNT + Multi count + 29 + 2 + + + + + OTG_HS_DOEPCTL0 + OTG_HS_DOEPCTL0 + OTG_HS device control OUT endpoint 0 control + register + 0x300 + 32 + 0x00008000 + + + MPSIZ + Maximum packet size + 0 + 2 + read-only + + + USBAEP + USB active endpoint + 15 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYP + Endpoint type + 18 + 2 + read-only + + + SNPM + Snoop mode + 20 + 1 + read-write + + + Stall + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPDIS + Endpoint disable + 30 + 1 + read-only + + + EPENA + Endpoint enable + 31 + 1 + write-only + + + + + OTG_HS_DOEPCTL1 + OTG_HS_DOEPCTL1 + OTG device endpoint-1 control + register + 0x320 + 32 + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + read-write + + + USBAEP + USB active endpoint + 15 + 1 + read-write + + + EONUM_DPID + Even odd frame/Endpoint data + PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYP + Endpoint type + 18 + 2 + read-write + + + SNPM + Snoop mode + 20 + 1 + read-write + + + Stall + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + Set DATA0 PID/Set even + frame + 28 + 1 + write-only + + + SODDFRM + Set odd frame + 29 + 1 + write-only + + + EPDIS + Endpoint disable + 30 + 1 + read-write + + + EPENA + Endpoint enable + 31 + 1 + read-write + + + + + OTG_HS_DOEPCTL2 + OTG_HS_DOEPCTL2 + OTG device endpoint-2 control + register + 0x340 + 32 + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + read-write + + + USBAEP + USB active endpoint + 15 + 1 + read-write + + + EONUM_DPID + Even odd frame/Endpoint data + PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYP + Endpoint type + 18 + 2 + read-write + + + SNPM + Snoop mode + 20 + 1 + read-write + + + Stall + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + Set DATA0 PID/Set even + frame + 28 + 1 + write-only + + + SODDFRM + Set odd frame + 29 + 1 + write-only + + + EPDIS + Endpoint disable + 30 + 1 + read-write + + + EPENA + Endpoint enable + 31 + 1 + read-write + + + + + OTG_HS_DOEPCTL3 + OTG_HS_DOEPCTL3 + OTG device endpoint-3 control + register + 0x360 + 32 + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + read-write + + + USBAEP + USB active endpoint + 15 + 1 + read-write + + + EONUM_DPID + Even odd frame/Endpoint data + PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYP + Endpoint type + 18 + 2 + read-write + + + SNPM + Snoop mode + 20 + 1 + read-write + + + Stall + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + Set DATA0 PID/Set even + frame + 28 + 1 + write-only + + + SODDFRM + Set odd frame + 29 + 1 + write-only + + + EPDIS + Endpoint disable + 30 + 1 + read-write + + + EPENA + Endpoint enable + 31 + 1 + read-write + + + + + OTG_HS_DOEPINT0 + OTG_HS_DOEPINT0 + OTG_HS device endpoint-0 interrupt + register + 0x308 + 32 + read-write + 0x00000080 + + + XFRC + Transfer completed + interrupt + 0 + 1 + + + EPDISD + Endpoint disabled + interrupt + 1 + 1 + + + STUP + SETUP phase done + 3 + 1 + + + OTEPDIS + OUT token received when endpoint + disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP packets + received + 6 + 1 + + + NYET + NYET interrupt + 14 + 1 + + + + + OTG_HS_DOEPINT1 + OTG_HS_DOEPINT1 + OTG_HS device endpoint-1 interrupt + register + 0x328 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + interrupt + 0 + 1 + + + EPDISD + Endpoint disabled + interrupt + 1 + 1 + + + STUP + SETUP phase done + 3 + 1 + + + OTEPDIS + OUT token received when endpoint + disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP packets + received + 6 + 1 + + + NYET + NYET interrupt + 14 + 1 + + + + + OTG_HS_DOEPINT2 + OTG_HS_DOEPINT2 + OTG_HS device endpoint-2 interrupt + register + 0x348 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + interrupt + 0 + 1 + + + EPDISD + Endpoint disabled + interrupt + 1 + 1 + + + STUP + SETUP phase done + 3 + 1 + + + OTEPDIS + OUT token received when endpoint + disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP packets + received + 6 + 1 + + + NYET + NYET interrupt + 14 + 1 + + + + + OTG_HS_DOEPINT3 + OTG_HS_DOEPINT3 + OTG_HS device endpoint-3 interrupt + register + 0x368 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + interrupt + 0 + 1 + + + EPDISD + Endpoint disabled + interrupt + 1 + 1 + + + STUP + SETUP phase done + 3 + 1 + + + OTEPDIS + OUT token received when endpoint + disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP packets + received + 6 + 1 + + + NYET + NYET interrupt + 14 + 1 + + + + + OTG_HS_DOEPINT4 + OTG_HS_DOEPINT4 + OTG_HS device endpoint-4 interrupt + register + 0x388 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + interrupt + 0 + 1 + + + EPDISD + Endpoint disabled + interrupt + 1 + 1 + + + STUP + SETUP phase done + 3 + 1 + + + OTEPDIS + OUT token received when endpoint + disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP packets + received + 6 + 1 + + + NYET + NYET interrupt + 14 + 1 + + + + + OTG_HS_DOEPINT5 + OTG_HS_DOEPINT5 + OTG_HS device endpoint-5 interrupt + register + 0x3A8 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + interrupt + 0 + 1 + + + EPDISD + Endpoint disabled + interrupt + 1 + 1 + + + STUP + SETUP phase done + 3 + 1 + + + OTEPDIS + OUT token received when endpoint + disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP packets + received + 6 + 1 + + + NYET + NYET interrupt + 14 + 1 + + + + + OTG_HS_DOEPINT6 + OTG_HS_DOEPINT6 + OTG_HS device endpoint-6 interrupt + register + 0x3C8 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + interrupt + 0 + 1 + + + EPDISD + Endpoint disabled + interrupt + 1 + 1 + + + STUP + SETUP phase done + 3 + 1 + + + OTEPDIS + OUT token received when endpoint + disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP packets + received + 6 + 1 + + + NYET + NYET interrupt + 14 + 1 + + + + + OTG_HS_DOEPINT7 + OTG_HS_DOEPINT7 + OTG_HS device endpoint-7 interrupt + register + 0x3E8 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + interrupt + 0 + 1 + + + EPDISD + Endpoint disabled + interrupt + 1 + 1 + + + STUP + SETUP phase done + 3 + 1 + + + OTEPDIS + OUT token received when endpoint + disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP packets + received + 6 + 1 + + + NYET + NYET interrupt + 14 + 1 + + + + + OTG_HS_DOEPTSIZ0 + OTG_HS_DOEPTSIZ0 + OTG_HS device endpoint-0 transfer size + register + 0x310 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 7 + + + PKTCNT + Packet count + 19 + 1 + + + STUPCNT + SETUP packet count + 29 + 2 + + + + + OTG_HS_DOEPTSIZ1 + OTG_HS_DOEPTSIZ1 + OTG_HS device endpoint-1 transfer size + register + 0x330 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID_STUPCNT + Received data PID/SETUP packet + count + 29 + 2 + + + + + OTG_HS_DOEPTSIZ2 + OTG_HS_DOEPTSIZ2 + OTG_HS device endpoint-2 transfer size + register + 0x350 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID_STUPCNT + Received data PID/SETUP packet + count + 29 + 2 + + + + + OTG_HS_DOEPTSIZ3 + OTG_HS_DOEPTSIZ3 + OTG_HS device endpoint-3 transfer size + register + 0x370 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID_STUPCNT + Received data PID/SETUP packet + count + 29 + 2 + + + + + OTG_HS_DOEPTSIZ4 + OTG_HS_DOEPTSIZ4 + OTG_HS device endpoint-4 transfer size + register + 0x390 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID_STUPCNT + Received data PID/SETUP packet + count + 29 + 2 + + + + + OTG_HS_DIEPTSIZ6 + OTG_HS_DIEPTSIZ6 + OTG_HS device endpoint transfer size + register + OTG_HS_DIEPCTL5 + 0x1A0 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MCNT + Multi count + 29 + 2 + + + + + OTG_HS_DTXFSTS6 + OTG_HS_DTXFSTS6 + OTG_HS device IN endpoint transmit FIFO + status register + 0x1A4 + 32 + read-write + 0x0 + + + INEPTFSAV + IN endpoint TxFIFO space + avail + 0 + 16 + + + + + OTG_HS_DIEPTSIZ7 + OTG_HS_DIEPTSIZ7 + OTG_HS device endpoint transfer size + register + OTG_HS_DIEPINT5 + 0x1A8 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MCNT + Multi count + 29 + 2 + + + + + OTG_HS_DTXFSTS7 + OTG_HS_DTXFSTS7 + OTG_HS device IN endpoint transmit FIFO + status register + 0x1AC + 32 + read-write + 0x0 + + + INEPTFSAV + IN endpoint TxFIFO space + avail + 0 + 16 + + + + + OTG_HS_DOEPCTL4 + OTG_HS_DOEPCTL4 + OTG device endpoint-4 control + register + 0x380 + 32 + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + read-write + + + USBAEP + USB active endpoint + 15 + 1 + read-write + + + EONUM_DPID + Even odd frame/Endpoint data + PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYP + Endpoint type + 18 + 2 + read-write + + + SNPM + Snoop mode + 20 + 1 + read-write + + + Stall + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + Set DATA0 PID/Set even + frame + 28 + 1 + write-only + + + SODDFRM + Set odd frame + 29 + 1 + write-only + + + EPDIS + Endpoint disable + 30 + 1 + read-write + + + EPENA + Endpoint enable + 31 + 1 + read-write + + + + + OTG_HS_DOEPCTL5 + OTG_HS_DOEPCTL5 + OTG device endpoint-5 control + register + 0x3A0 + 32 + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + read-write + + + USBAEP + USB active endpoint + 15 + 1 + read-write + + + EONUM_DPID + Even odd frame/Endpoint data + PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYP + Endpoint type + 18 + 2 + read-write + + + SNPM + Snoop mode + 20 + 1 + read-write + + + Stall + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + Set DATA0 PID/Set even + frame + 28 + 1 + write-only + + + SODDFRM + Set odd frame + 29 + 1 + write-only + + + EPDIS + Endpoint disable + 30 + 1 + read-write + + + EPENA + Endpoint enable + 31 + 1 + read-write + + + + + OTG_HS_DOEPCTL6 + OTG_HS_DOEPCTL6 + OTG device endpoint-6 control + register + 0x3C0 + 32 + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + read-write + + + USBAEP + USB active endpoint + 15 + 1 + read-write + + + EONUM_DPID + Even odd frame/Endpoint data + PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYP + Endpoint type + 18 + 2 + read-write + + + SNPM + Snoop mode + 20 + 1 + read-write + + + Stall + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + Set DATA0 PID/Set even + frame + 28 + 1 + write-only + + + SODDFRM + Set odd frame + 29 + 1 + write-only + + + EPDIS + Endpoint disable + 30 + 1 + read-write + + + EPENA + Endpoint enable + 31 + 1 + read-write + + + + + OTG_HS_DOEPCTL7 + OTG_HS_DOEPCTL7 + OTG device endpoint-7 control + register + 0x3E0 + 32 + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + read-write + + + USBAEP + USB active endpoint + 15 + 1 + read-write + + + EONUM_DPID + Even odd frame/Endpoint data + PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYP + Endpoint type + 18 + 2 + read-write + + + SNPM + Snoop mode + 20 + 1 + read-write + + + Stall + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + Set DATA0 PID/Set even + frame + 28 + 1 + write-only + + + SODDFRM + Set odd frame + 29 + 1 + write-only + + + EPDIS + Endpoint disable + 30 + 1 + read-write + + + EPENA + Endpoint enable + 31 + 1 + read-write + + + + + OTG_HS_DOEPTSIZ5 + OTG_HS_DOEPTSIZ5 + OTG_HS device endpoint-5 transfer size + register + 0x3B0 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID_STUPCNT + Received data PID/SETUP packet + count + 29 + 2 + + + + + OTG_HS_DOEPTSIZ6 + OTG_HS_DOEPTSIZ6 + OTG_HS device endpoint-6 transfer size + register + 0x3D0 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID_STUPCNT + Received data PID/SETUP packet + count + 29 + 2 + + + + + OTG_HS_DOEPTSIZ7 + OTG_HS_DOEPTSIZ7 + OTG_HS device endpoint-7 transfer size + register + 0x3F0 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID_STUPCNT + Received data PID/SETUP packet + count + 29 + 2 + + + + + + + OTG2_HS_DEVICE + 0x40080800 + + + OTG1_HS_PWRCLK + USB 1 on the go high speed + USB_OTG_HS + 0x40040E00 + + 0x0 + 0x3F200 + registers + + + + OTG_HS_PCGCR + OTG_HS_PCGCR + Power and clock gating control + register + 0x0 + 32 + read-write + 0x0 + + + STPPCLK + Stop PHY clock + 0 + 1 + + + GATEHCLK + Gate HCLK + 1 + 1 + + + PHYSUSP + PHY suspended + 4 + 1 + + + + + + + OTG2_HS_PWRCLK + 0x40080E00 + + + Ethernet_DMA + Ethernet: DMA mode register (DMA) + Ethernet + 0x40029000 + + 0x0 + 0x400 + registers + + + + DMAMR + DMAMR + DMA mode register + 0x0 + 0x20 + 0x00000000 + + + SWR + Software Reset + 0 + 1 + read-write + + + DA + DMA Tx or Rx Arbitration + Scheme + 1 + 1 + read-only + + + TXPR + Transmit priority + 11 + 1 + read-only + + + PR + Priority ratio + 12 + 3 + read-only + + + INTM + Interrupt Mode + 16 + 1 + read-write + + + + + DMASBMR + DMASBMR + System bus mode register + 0x04 + 0x20 + 0x01010000 + + + FB + Fixed Burst Length + 0 + 1 + read-write + + + AAL + Address-Aligned Beats + 12 + 1 + read-write + + + MB + Mixed Burst + 14 + 1 + read-only + + + RB + Rebuild INCRx Burst + 15 + 1 + read-only + + + + + DMAISR + DMAISR + Interrupt status register + 0x08 + 0x20 + read-only + 0x00000000 + + + DC0IS + DMA Channel Interrupt + Status + 0 + 1 + + + MTLIS + MTL Interrupt Status + 16 + 1 + + + MACIS + MAC Interrupt Status + 17 + 1 + + + + + DMADSR + DMADSR + Debug status register + 0x0C + 0x20 + read-only + 0x00000000 + + + AXWHSTS + AHB Master Write Channel + 0 + 1 + + + RPS0 + DMA Channel Receive Process + State + 8 + 4 + + + TPS0 + DMA Channel Transmit Process + State + 12 + 4 + + + + + DMACCR + DMACCR + Channel control register + 0x100 + 0x20 + read-write + 0x00000000 + + + MSS + Maximum Segment Size + 0 + 14 + + + PBLX8 + 8xPBL mode + 16 + 1 + + + DSL + Descriptor Skip Length + 18 + 3 + + + + + DMACTxCR + DMACTxCR + Channel transmit control + register + 0x104 + 0x20 + read-write + 0x00000000 + + + ST + Start or Stop Transmission + Command + 0 + 1 + + + OSF + Operate on Second Packet + 4 + 1 + + + TSE + TCP Segmentation Enabled + 12 + 1 + + + TXPBL + Transmit Programmable Burst + Length + 16 + 6 + + + + + DMACRxCR + DMACRxCR + Channel receive control + register + 0x108 + 0x20 + read-write + 0x00000000 + + + SR + Start or Stop Receive + Command + 0 + 1 + + + RBSZ + Receive Buffer size + 1 + 14 + + + RXPBL + RXPBL + 16 + 6 + + + RPF + DMA Rx Channel Packet + Flush + 31 + 1 + + + + + DMACTxDLAR + DMACTxDLAR + Channel Tx descriptor list address + register + 0x114 + 0x20 + read-write + 0x00000000 + + + TDESLA + Start of Transmit List + 2 + 30 + + + + + DMACRxDLAR + DMACRxDLAR + Channel Rx descriptor list address + register + 0x11C + 0x20 + read-write + 0x00000000 + + + RDESLA + Start of Receive List + 2 + 30 + + + + + DMACTxDTPR + DMACTxDTPR + Channel Tx descriptor tail pointer + register + 0x120 + 0x20 + read-write + 0x00000000 + + + TDT + Transmit Descriptor Tail + Pointer + 2 + 30 + + + + + DMACRxDTPR + DMACRxDTPR + Channel Rx descriptor tail pointer + register + 0x128 + 0x20 + read-write + 0x00000000 + + + RDT + Receive Descriptor Tail + Pointer + 2 + 30 + + + + + DMACTxRLR + DMACTxRLR + Channel Tx descriptor ring length + register + 0x12C + 0x20 + read-write + 0x00000000 + + + TDRL + Transmit Descriptor Ring + Length + 0 + 10 + + + + + DMACRxRLR + DMACRxRLR + Channel Rx descriptor ring length + register + 0x130 + 0x20 + read-write + 0x00000000 + + + RDRL + Receive Descriptor Ring + Length + 0 + 10 + + + + + DMACIER + DMACIER + Channel interrupt enable + register + 0x134 + 0x20 + read-write + 0x00000000 + + + TIE + Transmit Interrupt Enable + 0 + 1 + + + TXSE + Transmit Stopped Enable + 1 + 1 + + + TBUE + Transmit Buffer Unavailable + Enable + 2 + 1 + + + RIE + Receive Interrupt Enable + 6 + 1 + + + RBUE + Receive Buffer Unavailable + Enable + 7 + 1 + + + RSE + Receive Stopped Enable + 8 + 1 + + + RWTE + Receive Watchdog Timeout + Enable + 9 + 1 + + + ETIE + Early Transmit Interrupt + Enable + 10 + 1 + + + ERIE + Early Receive Interrupt + Enable + 11 + 1 + + + FBEE + Fatal Bus Error Enable + 12 + 1 + + + CDEE + Context Descriptor Error + Enable + 13 + 1 + + + AIE + Abnormal Interrupt Summary + Enable + 14 + 1 + + + NIE + Normal Interrupt Summary + Enable + 15 + 1 + + + + + DMACRxIWTR + DMACRxIWTR + Channel Rx interrupt watchdog timer + register + 0x138 + 0x20 + read-write + 0x00000000 + + + RWT + Receive Interrupt Watchdog Timer + Count + 0 + 8 + + + + + DMACCATxDR + DMACCATxDR + Channel current application transmit + descriptor register + 0x144 + 0x20 + read-only + 0x00000000 + + + CURTDESAPTR + Application Transmit Descriptor Address + Pointer + 0 + 32 + + + + + DMACCARxDR + DMACCARxDR + Channel current application receive + descriptor register + 0x14C + 0x20 + read-only + 0x00000000 + + + CURRDESAPTR + Application Receive Descriptor Address + Pointer + 0 + 32 + + + + + DMACCATxBR + DMACCATxBR + Channel current application transmit buffer + register + 0x154 + 0x20 + read-only + 0x00000000 + + + CURTBUFAPTR + Application Transmit Buffer Address + Pointer + 0 + 32 + + + + + DMACCARxBR + DMACCARxBR + Channel current application receive buffer + register + 0x15C + 0x20 + read-only + 0x00000000 + + + CURRBUFAPTR + Application Receive Buffer Address + Pointer + 0 + 32 + + + + + DMACSR + DMACSR + Channel status register + 0x160 + 0x20 + 0x00000000 + + + TI + Transmit Interrupt + 0 + 1 + read-write + + + TPS + Transmit Process Stopped + 1 + 1 + read-write + + + TBU + Transmit Buffer + Unavailable + 2 + 1 + read-write + + + RI + Receive Interrupt + 6 + 1 + read-write + + + RBU + Receive Buffer Unavailable + 7 + 1 + read-write + + + RPS + Receive Process Stopped + 8 + 1 + read-write + + + RWT + Receive Watchdog Timeout + 9 + 1 + read-write + + + ET + Early Transmit Interrupt + 10 + 1 + read-write + + + ER + Early Receive Interrupt + 11 + 1 + read-write + + + FBE + Fatal Bus Error + 12 + 1 + read-write + + + CDE + Context Descriptor Error + 13 + 1 + read-write + + + AIS + Abnormal Interrupt Summary + 14 + 1 + read-write + + + NIS + Normal Interrupt Summary + 15 + 1 + read-write + + + TEB + Tx DMA Error Bits + 16 + 3 + read-only + + + REB + Rx DMA Error Bits + 19 + 3 + read-only + + + + + DMACMFCR + DMACMFCR + Channel missed frame count + register + 0x16C + 0x20 + read-only + 0x00000000 + + + MFC + Dropped Packet Counters + 0 + 11 + + + MFCO + Overflow status of the MFC + Counter + 15 + 1 + + + + + + + Ethernet_MTL + Ethernet: MTL mode register (MTL) + Ethernet + 0x40028C00 + + 0x0 + 0x200 + registers + + + + MTLOMR + MTLOMR + Operating mode Register + 0x0 + 0x20 + read-write + 0x00000000 + + + DTXSTS + DTXSTS + 1 + 1 + + + CNTPRST + CNTPRST + 8 + 1 + + + CNTCLR + CNTCLR + 9 + 1 + + + + + MTLISR + MTLISR + Interrupt status Register + 0x20 + 0x20 + read-only + 0x00000000 + + + Q0IS + Queue interrupt status + 0 + 1 + + + + + MTLTxQOMR + MTLTxQOMR + Tx queue operating mode + Register + 0x100 + 0x20 + 0x00070008 + + + FTQ + Flush Transmit Queue + 0 + 1 + read-write + + + TSF + Transmit Store and Forward + 1 + 1 + read-write + + + TXQEN + Transmit Queue Enable + 2 + 2 + read-only + + + TTC + Transmit Threshold Control + 4 + 3 + read-write + + + TQS + Transmit Queue Size + 16 + 3 + read-write + + + + + MTLTxQUR + MTLTxQUR + Tx queue underflow register + 0x104 + 0x20 + read-only + 0x00000000 + + + UFFRMCNT + Underflow Packet Counter + 0 + 11 + + + UFCNTOVF + UFCNTOVF + 11 + 1 + + + + + MTLTxQDR + MTLTxQDR + Tx queue debug Register + 0x108 + 0x20 + read-only + 0x00000000 + + + TXQPAUSED + TXQPAUSED + 0 + 1 + + + TRCSTS + TRCSTS + 1 + 2 + + + TWCSTS + TWCSTS + 3 + 1 + + + TXQSTS + TXQSTS + 4 + 1 + + + TXSTSFSTS + TXSTSFSTS + 5 + 1 + + + PTXQ + PTXQ + 16 + 3 + + + STXSTSF + STXSTSF + 20 + 3 + + + + + MTLQICSR + MTLQICSR + Queue interrupt control status + Register + 0x12C + 0x20 + read-write + 0x00000000 + + + TXUNFIS + TXUNFIS + 0 + 1 + + + TXUIE + TXUIE + 8 + 1 + + + RXOVFIS + RXOVFIS + 16 + 1 + + + RXOIE + RXOIE + 24 + 1 + + + + + MTLRxQOMR + MTLRxQOMR + Rx queue operating mode + register + 0x130 + 0x20 + 0x00700000 + + + RTC + RTC + 0 + 2 + read-write + + + FUP + FUP + 3 + 1 + read-write + + + FEP + FEP + 4 + 1 + read-write + + + RSF + RSF + 5 + 1 + read-write + + + DIS_TCP_EF + DIS_TCP_EF + 6 + 1 + read-write + + + EHFC + EHFC + 7 + 1 + read-write + + + RFA + RFA + 8 + 3 + read-write + + + RFD + RFD + 14 + 3 + read-write + + + RQS + RQS + 20 + 3 + read-only + + + + + MTLRxQMPOCR + MTLRxQMPOCR + Rx queue missed packet and overflow counter + register + 0x134 + 0x20 + read-only + 0x00000000 + + + OVFPKTCNT + OVFPKTCNT + 0 + 11 + + + OVFCNTOVF + OVFCNTOVF + 11 + 1 + + + MISPKTCNT + MISPKTCNT + 16 + 11 + + + MISCNTOVF + MISCNTOVF + 27 + 1 + + + + + MTLRxQDR + MTLRxQDR + Rx queue debug register + 0x138 + 0x20 + read-only + 0x00000000 + + + RWCSTS + RWCSTS + 0 + 1 + + + RRCSTS + RRCSTS + 1 + 2 + + + RXQSTS + RXQSTS + 4 + 2 + + + PRXQ + PRXQ + 16 + 14 + + + + + + + Ethernet_MAC + Ethernet: media access control (MAC) + Ethernet + 0x40028000 + + 0x0 + 0xBDF + registers + + + ETH + Ethernet global interrupt + 61 + + + + MACCR + MACCR + Operating mode configuration + register + 0x0 + 0x20 + read-write + 0x00000000 + + + RE + Receiver Enable + 0 + 1 + + + TE + TE + 1 + 1 + + + PRELEN + PRELEN + 2 + 2 + + + DC + DC + 4 + 1 + + + BL + BL + 5 + 2 + + + DR + DR + 8 + 1 + + + DCRS + DCRS + 9 + 1 + + + DO + DO + 10 + 1 + + + ECRSFD + ECRSFD + 11 + 1 + + + LM + LM + 12 + 1 + + + DM + DM + 13 + 1 + + + FES + FES + 14 + 1 + + + JE + JE + 16 + 1 + + + JD + JD + 17 + 1 + + + WD + WD + 19 + 1 + + + ACS + ACS + 20 + 1 + + + CST + CST + 21 + 1 + + + S2KP + S2KP + 22 + 1 + + + GPSLCE + GPSLCE + 23 + 1 + + + IPG + IPG + 24 + 3 + + + IPC + IPC + 27 + 1 + + + SARC + SARC + 28 + 3 + + + ARPEN + ARPEN + 31 + 1 + + + + + MACECR + MACECR + Extended operating mode configuration + register + 0x4 + 0x20 + read-write + 0x00000000 + + + GPSL + GPSL + 0 + 14 + + + DCRCC + DCRCC + 16 + 1 + + + SPEN + SPEN + 17 + 1 + + + USP + USP + 18 + 1 + + + EIPGEN + EIPGEN + 24 + 1 + + + EIPG + EIPG + 25 + 5 + + + + + MACPFR + MACPFR + Packet filtering control + register + 0x8 + 0x20 + read-write + 0x00000000 + + + PR + PR + 0 + 1 + + + HUC + HUC + 1 + 1 + + + HMC + HMC + 2 + 1 + + + DAIF + DAIF + 3 + 1 + + + PM + PM + 4 + 1 + + + DBF + DBF + 5 + 1 + + + PCF + PCF + 6 + 2 + + + SAIF + SAIF + 8 + 1 + + + SAF + SAF + 9 + 1 + + + HPF + HPF + 10 + 1 + + + VTFE + VTFE + 16 + 1 + + + IPFE + IPFE + 20 + 1 + + + DNTU + DNTU + 21 + 1 + + + RA + RA + 31 + 1 + + + + + MACWTR + MACWTR + Watchdog timeout register + 0xC + 0x20 + read-write + 0x00000000 + + + WTO + WTO + 0 + 4 + + + PWE + PWE + 8 + 1 + + + + + MACHT0R + MACHT0R + Hash Table 0 register + 0x10 + 0x20 + read-write + 0x00000000 + + + HT31T0 + HT31T0 + 0 + 32 + + + + + MACHT1R + MACHT1R + Hash Table 1 register + 0x14 + 0x20 + read-write + 0x00000000 + + + HT63T32 + HT63T32 + 0 + 32 + + + + + MACVTR + MACVTR + VLAN tag register + 0x50 + 0x20 + read-write + 0x00000000 + + + VL + VL + 0 + 16 + + + ETV + ETV + 16 + 1 + + + VTIM + VTIM + 17 + 1 + + + ESVL + ESVL + 18 + 1 + + + ERSVLM + ERSVLM + 19 + 1 + + + DOVLTC + DOVLTC + 20 + 1 + + + EVLS + EVLS + 21 + 2 + + + EVLRXS + EVLRXS + 24 + 1 + + + VTHM + VTHM + 25 + 1 + + + EDVLP + EDVLP + 26 + 1 + + + ERIVLT + ERIVLT + 27 + 1 + + + EIVLS + EIVLS + 28 + 2 + + + EIVLRXS + EIVLRXS + 31 + 1 + + + + + MACVHTR + MACVHTR + VLAN Hash table register + 0x58 + 0x20 + read-write + 0x00000000 + + + VLHT + VLHT + 0 + 16 + + + + + MACVIR + MACVIR + VLAN inclusion register + 0x60 + 0x20 + read-write + 0x00000000 + + + VLT + VLT + 0 + 16 + + + VLC + VLC + 16 + 2 + + + VLP + VLP + 18 + 1 + + + CSVL + CSVL + 19 + 1 + + + VLTI + VLTI + 20 + 1 + + + + + MACIVIR + MACIVIR + Inner VLAN inclusion register + 0x64 + 0x20 + read-write + 0x00000000 + + + VLT + VLT + 0 + 16 + + + VLC + VLC + 16 + 2 + + + VLP + VLP + 18 + 1 + + + CSVL + CSVL + 19 + 1 + + + VLTI + VLTI + 20 + 1 + + + + + MACQTxFCR + MACQTxFCR + Tx Queue flow control register + 0x70 + 0x20 + read-write + 0x00000000 + + + FCB_BPA + FCB_BPA + 0 + 1 + + + TFE + TFE + 1 + 1 + + + PLT + PLT + 4 + 3 + + + DZPQ + DZPQ + 7 + 1 + + + PT + PT + 16 + 16 + + + + + MACRxFCR + MACRxFCR + Rx flow control register + 0x90 + 0x20 + read-write + 0x00000000 + + + RFE + RFE + 0 + 1 + + + UP + UP + 1 + 1 + + + + + MACISR + MACISR + Interrupt status register + 0xB0 + 0x20 + read-only + 0x00000000 + + + PHYIS + PHYIS + 3 + 1 + + + PMTIS + PMTIS + 4 + 1 + + + LPIIS + LPIIS + 5 + 1 + + + MMCIS + MMCIS + 8 + 1 + + + MMCRXIS + MMCRXIS + 9 + 1 + + + MMCTXIS + MMCTXIS + 10 + 1 + + + TSIS + TSIS + 12 + 1 + + + TXSTSIS + TXSTSIS + 13 + 1 + + + RXSTSIS + RXSTSIS + 14 + 1 + + + + + MACIER + MACIER + Interrupt enable register + 0xB4 + 0x20 + read-write + 0x00000000 + + + PHYIE + PHYIE + 3 + 1 + + + PMTIE + PMTIE + 4 + 1 + + + LPIIE + LPIIE + 5 + 1 + + + TSIE + TSIE + 12 + 1 + + + TXSTSIE + TXSTSIE + 13 + 1 + + + RXSTSIE + RXSTSIE + 14 + 1 + + + + + MACRxTxSR + MACRxTxSR + Rx Tx status register + 0xB8 + 0x20 + read-only + 0x00000000 + + + TJT + TJT + 0 + 1 + + + NCARR + NCARR + 1 + 1 + + + LCARR + LCARR + 2 + 1 + + + EXDEF + EXDEF + 3 + 1 + + + LCOL + LCOL + 4 + 1 + + + EXCOL + LCOL + 5 + 1 + + + RWT + RWT + 8 + 1 + + + + + MACPCSR + MACPCSR + PMT control status register + 0xC0 + 0x20 + 0x00000000 + + + PWRDWN + PWRDWN + 0 + 1 + read-write + + + MGKPKTEN + MGKPKTEN + 1 + 1 + read-write + + + RWKPKTEN + RWKPKTEN + 2 + 1 + read-write + + + MGKPRCVD + MGKPRCVD + 5 + 1 + read-only + + + RWKPRCVD + RWKPRCVD + 6 + 1 + read-only + + + GLBLUCAST + GLBLUCAST + 9 + 1 + read-write + + + RWKPFE + RWKPFE + 10 + 1 + read-write + + + RWKPTR + RWKPTR + 24 + 5 + read-write + + + RWKFILTRST + RWKFILTRST + 31 + 1 + read-write + + + + + MACRWKPFR + MACRWKPFR + Remove wakeup packet filter + register + 0xC4 + 0x20 + read-write + 0x00000000 + + + MACRWKPFR + MACRWKPFR + 0 + 32 + + + + + MACLCSR + MACLCSR + LPI control status register + 0xD0 + 0x20 + 0x00000000 + + + TLPIEN + TLPIEN + 0 + 1 + read-only + + + TLPIEX + TLPIEX + 1 + 1 + read-only + + + RLPIEN + RLPIEN + 2 + 1 + read-only + + + RLPIEX + RLPIEX + 3 + 1 + read-only + + + TLPIST + TLPIST + 8 + 1 + read-only + + + RLPIST + RLPIST + 9 + 1 + read-only + + + LPIEN + LPIEN + 16 + 1 + read-write + + + PLS + PLS + 17 + 1 + read-write + + + PLSEN + PLSEN + 18 + 1 + read-write + + + LPITXA + LPITXA + 19 + 1 + read-write + + + LPITE + LPITE + 20 + 1 + read-write + + + + + MACLTCR + MACLTCR + LPI timers control register + 0xD4 + 0x20 + read-write + 0x03E80000 + + + TWT + TWT + 0 + 16 + + + LST + LST + 16 + 10 + + + + + MACLETR + MACLETR + LPI entry timer register + 0xD8 + 0x20 + read-write + 0x00000000 + + + LPIET + LPIET + 0 + 17 + + + + + MAC1USTCR + MAC1USTCR + 1-microsecond-tick counter + register + 0xDC + 0x20 + read-write + 0x00000000 + + + TIC_1US_CNTR + TIC_1US_CNTR + 0 + 12 + + + + + MACVR + MACVR + Version register + 0x110 + 0x20 + read-only + 0x00003041 + + + SNPSVER + SNPSVER + 0 + 8 + + + USERVER + USERVER + 8 + 8 + + + + + MACDR + MACDR + Debug register + 0x114 + 0x20 + read-only + 0x00000000 + + + RPESTS + RPESTS + 0 + 1 + + + RFCFCSTS + RFCFCSTS + 1 + 2 + + + TPESTS + TPESTS + 16 + 1 + + + TFCSTS + TFCSTS + 17 + 2 + + + + + MACHWF1R + MACHWF1R + HW feature 1 register + 0x120 + 0x20 + read-only + 0x11841904 + + + RXFIFOSIZE + RXFIFOSIZE + 0 + 5 + + + TXFIFOSIZE + TXFIFOSIZE + 6 + 5 + + + OSTEN + OSTEN + 11 + 1 + + + PTOEN + PTOEN + 12 + 1 + + + ADVTHWORD + ADVTHWORD + 13 + 1 + + + ADDR64 + ADDR64 + 14 + 2 + + + DCBEN + DCBEN + 16 + 1 + + + SPHEN + SPHEN + 17 + 1 + + + TSOEN + TSOEN + 18 + 1 + + + DBGMEMA + DBGMEMA + 19 + 1 + + + AVSEL + AVSEL + 20 + 1 + + + HASHTBLSZ + HASHTBLSZ + 24 + 2 + + + L3L4FNUM + L3L4FNUM + 27 + 4 + + + + + MACHWF2R + MACHWF2R + HW feature 2 register + 0x124 + 0x20 + read-only + 0x41000000 + + + RXQCNT + RXQCNT + 0 + 4 + + + TXQCNT + TXQCNT + 6 + 4 + + + RXCHCNT + RXCHCNT + 12 + 4 + + + TXCHCNT + TXCHCNT + 18 + 4 + + + PPSOUTNUM + PPSOUTNUM + 24 + 3 + + + AUXSNAPNUM + AUXSNAPNUM + 28 + 3 + + + + + MACMDIOAR + MACMDIOAR + MDIO address register + 0x200 + 0x20 + read-write + 0x00000000 + + + MB + MB + 0 + 1 + + + C45E + C45E + 1 + 1 + + + GOC + GOC + 2 + 2 + + + SKAP + SKAP + 4 + 1 + + + CR + CR + 8 + 4 + + + NTC + NTC + 12 + 3 + + + RDA + RDA + 16 + 5 + + + PA + PA + 21 + 5 + + + BTB + BTB + 26 + 1 + + + PSE + PSE + 27 + 1 + + + + + MACMDIODR + MACMDIODR + MDIO data register + 0x204 + 0x20 + read-write + 0x00000000 + + + MD + MD + 0 + 16 + + + RA + RA + 16 + 16 + + + + + MACARPAR + MACARPAR + ARP address register + 0xAE0 + 0x20 + read-write + 0x00000000 + + + ARPPA + ARPPA + 0 + 32 + + + + + MACA0HR + MACA0HR + Address 0 high register + 0x300 + 0x20 + 0x8000FFFF + + + ADDRHI + ADDRHI + 0 + 16 + read-write + + + AE + AE + 31 + 1 + read-only + + + + + MACA0LR + MACA0LR + Address 0 low register + 0x304 + 0x20 + read-write + 0xFFFFFFFF + + + ADDRLO + ADDRLO + 0 + 32 + + + + + MACA1LR + MACA1LR + Address 1 low register + 0x30C + 0x20 + read-write + 0xFFFFFFFF + + + ADDRLO + ADDRLO + 0 + 32 + + + + + MACA2LR + MACA2LR + Address 2 low register + 0x314 + 0x20 + read-write + 0xFFFFFFFF + + + ADDRLO + ADDRLO + 0 + 32 + + + + + MACA1HR + MACA1HR + Address 1 high register + 0x308 + 0x20 + read-write + 0x0000FFFF + + + ADDRHI + ADDRHI + 0 + 16 + + + MBC + MBC + 24 + 6 + + + SA + SA + 30 + 1 + + + AE + AE + 31 + 1 + + + + + MACA2HR + MACA2HR + Address 2 high register + 0x310 + 0x20 + read-write + 0x0000FFFF + + + ADDRHI + ADDRHI + 0 + 16 + + + MBC + MBC + 24 + 6 + + + SA + SA + 30 + 1 + + + AE + AE + 31 + 1 + + + + + MACA3HR + MACA3HR + Address 3 high register + 0x318 + 0x20 + read-write + 0x0000FFFF + + + ADDRHI + ADDRHI + 0 + 16 + + + MBC + MBC + 24 + 6 + + + SA + SA + 30 + 1 + + + AE + AE + 31 + 1 + + + + + MACA3LR + MACA3LR + Address 3 low register + 0x31C + 0x20 + read-write + 0xFFFFFFFF + + + ADDRLO + ADDRLO + 0 + 32 + + + + + MMC_CONTROL + MMC_CONTROL + MMC control register + 0x700 + 0x20 + read-write + 0x00000000 + + + CNTRST + CNTRST + 0 + 1 + + + CNTSTOPRO + CNTSTOPRO + 1 + 1 + + + RSTONRD + RSTONRD + 2 + 1 + + + CNTFREEZ + CNTFREEZ + 3 + 1 + + + CNTPRST + CNTPRST + 4 + 1 + + + CNTPRSTLVL + CNTPRSTLVL + 5 + 1 + + + UCDBC + UCDBC + 8 + 1 + + + + + MMC_RX_INTERRUPT + MMC_RX_INTERRUPT + MMC Rx interrupt register + 0x704 + 0x20 + read-only + 0x00000000 + + + RXCRCERPIS + RXCRCERPIS + 5 + 1 + + + RXALGNERPIS + RXALGNERPIS + 6 + 1 + + + RXUCGPIS + RXUCGPIS + 17 + 1 + + + RXLPIUSCIS + RXLPIUSCIS + 26 + 1 + + + RXLPITRCIS + RXLPITRCIS + 27 + 1 + + + + + MMC_TX_INTERRUPT + MMC_TX_INTERRUPT + MMC Tx interrupt register + 0x708 + 0x20 + read-only + 0x00000000 + + + TXSCOLGPIS + TXSCOLGPIS + 14 + 1 + + + TXMCOLGPIS + TXMCOLGPIS + 15 + 1 + + + TXGPKTIS + TXGPKTIS + 21 + 1 + + + TXLPIUSCIS + TXLPIUSCIS + 26 + 1 + + + TXLPITRCIS + TXLPITRCIS + 27 + 1 + + + + + MMC_RX_INTERRUPT_MASK + MMC_RX_INTERRUPT_MASK + MMC Rx interrupt mask register + 0x70C + 0x20 + 0x00000000 + + + RXCRCERPIM + RXCRCERPIM + 5 + 1 + read-write + + + RXALGNERPIM + RXALGNERPIM + 6 + 1 + read-write + + + RXUCGPIM + RXUCGPIM + 17 + 1 + read-write + + + RXLPIUSCIM + RXLPIUSCIM + 26 + 1 + read-write + + + RXLPITRCIM + RXLPITRCIM + 27 + 1 + read-only + + + + + MMC_TX_INTERRUPT_MASK + MMC_TX_INTERRUPT_MASK + MMC Tx interrupt mask register + 0x710 + 0x20 + 0x00000000 + + + TXSCOLGPIM + TXSCOLGPIM + 14 + 1 + read-write + + + TXMCOLGPIM + TXMCOLGPIM + 15 + 1 + read-write + + + TXGPKTIM + TXGPKTIM + 21 + 1 + read-write + + + TXLPIUSCIM + TXLPIUSCIM + 26 + 1 + read-write + + + TXLPITRCIM + TXLPITRCIM + 27 + 1 + read-only + + + + + TX_SINGLE_COLLISION_GOOD_PACKETS + + TX_SINGLE_COLLISION_GOOD_PACKETS + Tx single collision good packets + register + 0x74C + 0x20 + read-only + 0x00000000 + + + TXSNGLCOLG + TXSNGLCOLG + 0 + 32 + + + + + TX_MULTIPLE_COLLISION_GOOD_PACKETS + + TX_MULTIPLE_COLLISION_GOOD_PACKETS + Tx multiple collision good packets + register + 0x750 + 0x20 + read-only + 0x00000000 + + + TXMULTCOLG + TXMULTCOLG + 0 + 32 + + + + + TX_PACKET_COUNT_GOOD + TX_PACKET_COUNT_GOOD + Tx packet count good register + 0x768 + 0x20 + read-only + 0x00000000 + + + TXPKTG + TXPKTG + 0 + 32 + + + + + RX_CRC_ERROR_PACKETS + RX_CRC_ERROR_PACKETS + Rx CRC error packets register + 0x794 + 0x20 + read-only + 0x00000000 + + + RXCRCERR + RXCRCERR + 0 + 32 + + + + + RX_ALIGNMENT_ERROR_PACKETS + RX_ALIGNMENT_ERROR_PACKETS + Rx alignment error packets + register + 0x798 + 0x20 + read-only + 0x00000000 + + + RXALGNERR + RXALGNERR + 0 + 32 + + + + + RX_UNICAST_PACKETS_GOOD + RX_UNICAST_PACKETS_GOOD + Rx unicast packets good + register + 0x7C4 + 0x20 + read-only + 0x00000000 + + + RXUCASTG + RXUCASTG + 0 + 32 + + + + + TX_LPI_USEC_CNTR + TX_LPI_USEC_CNTR + Tx LPI microsecond timer + register + 0x7EC + 0x20 + read-only + 0x00000000 + + + TXLPIUSC + TXLPIUSC + 0 + 32 + + + + + TX_LPI_TRAN_CNTR + TX_LPI_TRAN_CNTR + Tx LPI transition counter + register + 0x7F0 + 0x20 + read-only + 0x00000000 + + + TXLPITRC + TXLPITRC + 0 + 32 + + + + + RX_LPI_USEC_CNTR + RX_LPI_USEC_CNTR + Rx LPI microsecond counter + register + 0x7F4 + 0x20 + read-only + 0x00000000 + + + RXLPIUSC + RXLPIUSC + 0 + 32 + + + + + RX_LPI_TRAN_CNTR + RX_LPI_TRAN_CNTR + Rx LPI transition counter + register + 0x7F8 + 0x20 + read-only + 0x00000000 + + + RXLPITRC + RXLPITRC + 0 + 32 + + + + + MACL3L4C0R + MACL3L4C0R + L3 and L4 control 0 register + 0x900 + 0x20 + read-write + 0x00000000 + + + L3PEN0 + L3PEN0 + 0 + 1 + + + L3SAM0 + L3SAM0 + 2 + 1 + + + L3SAIM0 + L3SAIM0 + 3 + 1 + + + L3DAM0 + L3DAM0 + 4 + 1 + + + L3DAIM0 + L3DAIM0 + 5 + 1 + + + L3HSBM0 + L3HSBM0 + 6 + 5 + + + L3HDBM0 + L3HDBM0 + 11 + 5 + + + L4PEN0 + L4PEN0 + 16 + 1 + + + L4SPM0 + L4SPM0 + 18 + 1 + + + L4SPIM0 + L4SPIM0 + 19 + 1 + + + L4DPM0 + L4DPM0 + 20 + 1 + + + L4DPIM0 + L4DPIM0 + 21 + 1 + + + + + MACL4A0R + MACL4A0R + Layer4 address filter 0 + register + 0x904 + 0x20 + read-write + 0x00000000 + + + L4SP0 + L4SP0 + 0 + 16 + + + L4DP0 + L4DP0 + 16 + 16 + + + + + MACL3A00R + MACL3A00R + MACL3A00R + 0x910 + 0x20 + read-write + 0x00000000 + + + L3A00 + L3A00 + 0 + 32 + + + + + MACL3A10R + MACL3A10R + Layer3 address 1 filter 0 + register + 0x914 + 0x20 + read-write + 0x00000000 + + + L3A10 + L3A10 + 0 + 32 + + + + + MACL3A20 + MACL3A20 + Layer3 Address 2 filter 0 + register + 0x918 + 0x20 + read-write + 0x00000000 + + + L3A20 + L3A20 + 0 + 32 + + + + + MACL3A30 + MACL3A30 + Layer3 Address 3 filter 0 + register + 0x91C + 0x20 + read-write + 0x00000000 + + + L3A30 + L3A30 + 0 + 32 + + + + + MACL3L4C1R + MACL3L4C1R + L3 and L4 control 1 register + 0x930 + 0x20 + read-write + 0x00000000 + + + L3PEN1 + L3PEN1 + 0 + 1 + + + L3SAM1 + L3SAM1 + 2 + 1 + + + L3SAIM1 + L3SAIM1 + 3 + 1 + + + L3DAM1 + L3DAM1 + 4 + 1 + + + L3DAIM1 + L3DAIM1 + 5 + 1 + + + L3HSBM1 + L3HSBM1 + 6 + 5 + + + L3HDBM1 + L3HDBM1 + 11 + 5 + + + L4PEN1 + L4PEN1 + 16 + 1 + + + L4SPM1 + L4SPM1 + 18 + 1 + + + L4SPIM1 + L4SPIM1 + 19 + 1 + + + L4DPM1 + L4DPM1 + 20 + 1 + + + L4DPIM1 + L4DPIM1 + 21 + 1 + + + + + MACL4A1R + MACL4A1R + Layer 4 address filter 1 + register + 0x934 + 0x20 + read-write + 0x00000000 + + + L4SP1 + L4SP1 + 0 + 16 + + + L4DP1 + L4DP1 + 16 + 16 + + + + + MACL3A01R + MACL3A01R + Layer3 address 0 filter 1 + Register + 0x940 + 0x20 + read-write + 0x00000000 + + + L3A01 + L3A01 + 0 + 32 + + + + + MACL3A11R + MACL3A11R + Layer3 address 1 filter 1 + register + 0x944 + 0x20 + read-write + 0x00000000 + + + L3A11 + L3A11 + 0 + 32 + + + + + MACL3A21R + MACL3A21R + Layer3 address 2 filter 1 + Register + 0x948 + 0x20 + read-write + 0x00000000 + + + L3A21 + L3A21 + 0 + 32 + + + + + MACL3A31R + MACL3A31R + Layer3 address 3 filter 1 + register + 0x94C + 0x20 + read-write + 0x00000000 + + + L3A31 + L3A31 + 0 + 32 + + + + + MACTSCR + MACTSCR + Timestamp control Register + 0xB00 + 0x20 + 0x00000200 + + + TSENA + TSENA + 0 + 1 + read-write + + + TSCFUPDT + TSCFUPDT + 1 + 1 + read-write + + + TSINIT + TSINIT + 2 + 1 + read-write + + + TSUPDT + TSUPDT + 3 + 1 + read-write + + + TSADDREG + TSADDREG + 5 + 1 + read-write + + + TSENALL + TSENALL + 8 + 1 + read-write + + + TSCTRLSSR + TSCTRLSSR + 9 + 1 + read-write + + + TSVER2ENA + TSVER2ENA + 10 + 1 + read-write + + + TSIPENA + TSIPENA + 11 + 1 + read-write + + + TSIPV6ENA + TSIPV6ENA + 12 + 1 + read-write + + + TSIPV4ENA + TSIPV4ENA + 13 + 1 + read-write + + + TSEVNTENA + TSEVNTENA + 14 + 1 + read-write + + + TSMSTRENA + TSMSTRENA + 15 + 1 + read-write + + + SNAPTYPSEL + SNAPTYPSEL + 16 + 2 + read-write + + + TSENMACADDR + TSENMACADDR + 18 + 1 + read-write + + + CSC + CSC + 19 + 1 + read-only + + + TXTSSTSM + TXTSSTSM + 24 + 1 + read-write + + + + + MACSSIR + MACSSIR + Sub-second increment register + 0xB04 + 0x20 + read-write + 0x00000000 + + + SNSINC + SNSINC + 8 + 8 + + + SSINC + SSINC + 16 + 8 + + + + + MACSTSR + MACSTSR + System time seconds register + 0xB08 + 0x20 + read-only + 0x00000000 + + + TSS + TSS + 0 + 32 + + + + + MACSTNR + MACSTNR + System time nanoseconds + register + 0xB0C + 0x20 + read-only + 0x00000000 + + + TSSS + TSSS + 0 + 31 + + + + + MACSTSUR + MACSTSUR + System time seconds update + register + 0xB10 + 0x20 + read-write + 0x00000000 + + + TSS + TSS + 0 + 32 + + + + + MACSTNUR + MACSTNUR + System time nanoseconds update + register + 0xB14 + 0x20 + read-write + 0x00000000 + + + TSSS + TSSS + 0 + 31 + + + ADDSUB + ADDSUB + 31 + 1 + + + + + MACTSAR + MACTSAR + Timestamp addend register + 0xB18 + 0x20 + read-write + 0x00000000 + + + TSAR + TSAR + 0 + 32 + + + + + MACTSSR + MACTSSR + Timestamp status register + 0xB20 + 0x20 + read-only + 0x00000000 + + + TSSOVF + TSSOVF + 0 + 1 + + + TSTARGT0 + TSTARGT0 + 1 + 1 + + + AUXTSTRIG + AUXTSTRIG + 2 + 1 + + + TSTRGTERR0 + TSTRGTERR0 + 3 + 1 + + + TXTSSIS + TXTSSIS + 15 + 1 + + + ATSSTN + ATSSTN + 16 + 4 + + + ATSSTM + ATSSTM + 24 + 1 + + + ATSNS + ATSNS + 25 + 5 + + + + + MACTxTSSNR + MACTxTSSNR + Tx timestamp status nanoseconds + register + 0xB30 + 0x20 + read-only + 0x00000000 + + + TXTSSLO + TXTSSLO + 0 + 31 + + + TXTSSMIS + TXTSSMIS + 31 + 1 + + + + + MACTxTSSSR + MACTxTSSSR + Tx timestamp status seconds + register + 0xB34 + 0x20 + read-only + 0x00000000 + + + TXTSSHI + TXTSSHI + 0 + 32 + + + + + MACACR + MACACR + Auxiliary control register + 0xB40 + 0x20 + read-write + 0x00000000 + + + ATSFC + ATSFC + 0 + 1 + + + ATSEN0 + ATSEN0 + 4 + 1 + + + ATSEN1 + ATSEN1 + 5 + 1 + + + ATSEN2 + ATSEN2 + 6 + 1 + + + ATSEN3 + ATSEN3 + 7 + 1 + + + + + MACATSNR + MACATSNR + Auxiliary timestamp nanoseconds + register + 0xB48 + 0x20 + read-only + 0x00000000 + + + AUXTSLO + AUXTSLO + 0 + 31 + + + + + MACATSSR + MACATSSR + Auxiliary timestamp seconds + register + 0xB4C + 0x20 + read-only + 0x00000000 + + + AUXTSHI + AUXTSHI + 0 + 32 + + + + + MACTSIACR + MACTSIACR + Timestamp Ingress asymmetric correction + register + 0xB50 + 0x20 + read-write + 0x00000000 + + + OSTIAC + OSTIAC + 0 + 32 + + + + + MACTSEACR + MACTSEACR + Timestamp Egress asymmetric correction + register + 0xB54 + 0x20 + read-write + 0x00000000 + + + OSTEAC + OSTEAC + 0 + 32 + + + + + MACTSICNR + MACTSICNR + Timestamp Ingress correction nanosecond + register + 0xB58 + 0x20 + read-write + 0x00000000 + + + TSIC + TSIC + 0 + 32 + + + + + MACTSECNR + MACTSECNR + Timestamp Egress correction nanosecond + register + 0xB5C + 0x20 + read-write + 0x00000000 + + + TSEC + TSEC + 0 + 32 + + + + + MACPPSCR + MACPPSCR + PPS control register + 0xB70 + 0x20 + read-write + 0x00000000 + + + PPSCTRL + PPSCTRL + 0 + 4 + + + PPSEN0 + PPSEN0 + 4 + 1 + + + TRGTMODSEL0 + TRGTMODSEL0 + 5 + 2 + + + + + MACPPSTTSR + MACPPSTTSR + PPS target time seconds + register + 0xB80 + 0x20 + read-write + 0x00000000 + + + TSTRH0 + TSTRH0 + 0 + 31 + + + + + MACPPSTTNR + MACPPSTTNR + PPS target time nanoseconds + register + 0xB84 + 0x20 + read-write + 0x00000000 + + + TTSL0 + TTSL0 + 0 + 31 + + + TRGTBUSY0 + TRGTBUSY0 + 31 + 1 + + + + + MACPPSIR + MACPPSIR + PPS interval register + 0xB88 + 0x20 + read-write + 0x00000000 + + + PPSINT0 + PPSINT0 + 0 + 32 + + + + + MACPPSWR + MACPPSWR + PPS width register + 0xB8C + 0x20 + read-write + 0x00000000 + + + PPSWIDTH0 + PPSWIDTH0 + 0 + 32 + + + + + MACPOCR + MACPOCR + PTP Offload control register + 0xBC0 + 0x20 + read-write + 0x00000000 + + + PTOEN + PTOEN + 0 + 1 + + + ASYNCEN + ASYNCEN + 1 + 1 + + + APDREQEN + APDREQEN + 2 + 1 + + + ASYNCTRIG + ASYNCTRIG + 4 + 1 + + + APDREQTRIG + APDREQTRIG + 5 + 1 + + + DRRDIS + DRRDIS + 6 + 1 + + + DN + DN + 8 + 8 + + + + + MACSPI0R + MACSPI0R + PTP Source Port Identity 0 + Register + 0xBC4 + 0x20 + read-write + 0x00000000 + + + SPI0 + SPI0 + 0 + 32 + + + + + MACSPI1R + MACSPI1R + PTP Source port identity 1 + register + 0xBC8 + 0x20 + read-write + 0x00000000 + + + SPI1 + SPI1 + 0 + 32 + + + + + MACSPI2R + MACSPI2R + PTP Source port identity 2 + register + 0xBCC + 0x20 + read-write + 0x00000000 + + + SPI2 + SPI2 + 0 + 16 + + + + + MACLMIR + MACLMIR + Log message interval register + 0xBD0 + 0x20 + read-write + 0x00000000 + + + LSI + LSI + 0 + 8 + + + DRSYNCR + DRSYNCR + 8 + 3 + + + LMPDRI + LMPDRI + 24 + 8 + + + + + + + DMA1 + DMA controller + DMA + 0x40020000 + + 0x0 + 0x400 + registers + + + DMA_STR0 + DMA1 Stream0 + 11 + + + DMA_STR1 + DMA1 Stream1 + 12 + + + DMA1_STR7 + DMA1 Stream7 + 47 + + + + LISR + LISR + low interrupt status register + 0x0 + 0x20 + read-only + 0x00000000 + + + TCIF3 + Stream x transfer complete interrupt + flag (x = 3..0) + 27 + 1 + + + HTIF3 + Stream x half transfer interrupt flag + (x=3..0) + 26 + 1 + + + TEIF3 + Stream x transfer error interrupt flag + (x=3..0) + 25 + 1 + + + DMEIF3 + Stream x direct mode error interrupt + flag (x=3..0) + 24 + 1 + + + FEIF3 + Stream x FIFO error interrupt flag + (x=3..0) + 22 + 1 + + + TCIF2 + Stream x transfer complete interrupt + flag (x = 3..0) + 21 + 1 + + + HTIF2 + Stream x half transfer interrupt flag + (x=3..0) + 20 + 1 + + + TEIF2 + Stream x transfer error interrupt flag + (x=3..0) + 19 + 1 + + + DMEIF2 + Stream x direct mode error interrupt + flag (x=3..0) + 18 + 1 + + + FEIF2 + Stream x FIFO error interrupt flag + (x=3..0) + 16 + 1 + + + TCIF1 + Stream x transfer complete interrupt + flag (x = 3..0) + 11 + 1 + + + HTIF1 + Stream x half transfer interrupt flag + (x=3..0) + 10 + 1 + + + TEIF1 + Stream x transfer error interrupt flag + (x=3..0) + 9 + 1 + + + DMEIF1 + Stream x direct mode error interrupt + flag (x=3..0) + 8 + 1 + + + FEIF1 + Stream x FIFO error interrupt flag + (x=3..0) + 6 + 1 + + + TCIF0 + Stream x transfer complete interrupt + flag (x = 3..0) + 5 + 1 + + + HTIF0 + Stream x half transfer interrupt flag + (x=3..0) + 4 + 1 + + + TEIF0 + Stream x transfer error interrupt flag + (x=3..0) + 3 + 1 + + + DMEIF0 + Stream x direct mode error interrupt + flag (x=3..0) + 2 + 1 + + + FEIF0 + Stream x FIFO error interrupt flag + (x=3..0) + 0 + 1 + + + + + HISR + HISR + high interrupt status register + 0x4 + 0x20 + read-only + 0x00000000 + + + TCIF7 + Stream x transfer complete interrupt + flag (x=7..4) + 27 + 1 + + + HTIF7 + Stream x half transfer interrupt flag + (x=7..4) + 26 + 1 + + + TEIF7 + Stream x transfer error interrupt flag + (x=7..4) + 25 + 1 + + + DMEIF7 + Stream x direct mode error interrupt + flag (x=7..4) + 24 + 1 + + + FEIF7 + Stream x FIFO error interrupt flag + (x=7..4) + 22 + 1 + + + TCIF6 + Stream x transfer complete interrupt + flag (x=7..4) + 21 + 1 + + + HTIF6 + Stream x half transfer interrupt flag + (x=7..4) + 20 + 1 + + + TEIF6 + Stream x transfer error interrupt flag + (x=7..4) + 19 + 1 + + + DMEIF6 + Stream x direct mode error interrupt + flag (x=7..4) + 18 + 1 + + + FEIF6 + Stream x FIFO error interrupt flag + (x=7..4) + 16 + 1 + + + TCIF5 + Stream x transfer complete interrupt + flag (x=7..4) + 11 + 1 + + + HTIF5 + Stream x half transfer interrupt flag + (x=7..4) + 10 + 1 + + + TEIF5 + Stream x transfer error interrupt flag + (x=7..4) + 9 + 1 + + + DMEIF5 + Stream x direct mode error interrupt + flag (x=7..4) + 8 + 1 + + + FEIF5 + Stream x FIFO error interrupt flag + (x=7..4) + 6 + 1 + + + TCIF4 + Stream x transfer complete interrupt + flag (x=7..4) + 5 + 1 + + + HTIF4 + Stream x half transfer interrupt flag + (x=7..4) + 4 + 1 + + + TEIF4 + Stream x transfer error interrupt flag + (x=7..4) + 3 + 1 + + + DMEIF4 + Stream x direct mode error interrupt + flag (x=7..4) + 2 + 1 + + + FEIF4 + Stream x FIFO error interrupt flag + (x=7..4) + 0 + 1 + + + + + LIFCR + LIFCR + low interrupt flag clear + register + 0x8 + 0x20 + read-write + 0x00000000 + + + CTCIF3 + Stream x clear transfer complete + interrupt flag (x = 3..0) + 27 + 1 + + + CHTIF3 + Stream x clear half transfer interrupt + flag (x = 3..0) + 26 + 1 + + + CTEIF3 + Stream x clear transfer error interrupt + flag (x = 3..0) + 25 + 1 + + + CDMEIF3 + Stream x clear direct mode error + interrupt flag (x = 3..0) + 24 + 1 + + + CFEIF3 + Stream x clear FIFO error interrupt flag + (x = 3..0) + 22 + 1 + + + CTCIF2 + Stream x clear transfer complete + interrupt flag (x = 3..0) + 21 + 1 + + + CHTIF2 + Stream x clear half transfer interrupt + flag (x = 3..0) + 20 + 1 + + + CTEIF2 + Stream x clear transfer error interrupt + flag (x = 3..0) + 19 + 1 + + + CDMEIF2 + Stream x clear direct mode error + interrupt flag (x = 3..0) + 18 + 1 + + + CFEIF2 + Stream x clear FIFO error interrupt flag + (x = 3..0) + 16 + 1 + + + CTCIF1 + Stream x clear transfer complete + interrupt flag (x = 3..0) + 11 + 1 + + + CHTIF1 + Stream x clear half transfer interrupt + flag (x = 3..0) + 10 + 1 + + + CTEIF1 + Stream x clear transfer error interrupt + flag (x = 3..0) + 9 + 1 + + + CDMEIF1 + Stream x clear direct mode error + interrupt flag (x = 3..0) + 8 + 1 + + + CFEIF1 + Stream x clear FIFO error interrupt flag + (x = 3..0) + 6 + 1 + + + CTCIF0 + Stream x clear transfer complete + interrupt flag (x = 3..0) + 5 + 1 + + + CHTIF0 + Stream x clear half transfer interrupt + flag (x = 3..0) + 4 + 1 + + + CTEIF0 + Stream x clear transfer error interrupt + flag (x = 3..0) + 3 + 1 + + + CDMEIF0 + Stream x clear direct mode error + interrupt flag (x = 3..0) + 2 + 1 + + + CFEIF0 + Stream x clear FIFO error interrupt flag + (x = 3..0) + 0 + 1 + + + + + HIFCR + HIFCR + high interrupt flag clear + register + 0xC + 0x20 + read-write + 0x00000000 + + + CTCIF7 + Stream x clear transfer complete + interrupt flag (x = 7..4) + 27 + 1 + + + CHTIF7 + Stream x clear half transfer interrupt + flag (x = 7..4) + 26 + 1 + + + CTEIF7 + Stream x clear transfer error interrupt + flag (x = 7..4) + 25 + 1 + + + CDMEIF7 + Stream x clear direct mode error + interrupt flag (x = 7..4) + 24 + 1 + + + CFEIF7 + Stream x clear FIFO error interrupt flag + (x = 7..4) + 22 + 1 + + + CTCIF6 + Stream x clear transfer complete + interrupt flag (x = 7..4) + 21 + 1 + + + CHTIF6 + Stream x clear half transfer interrupt + flag (x = 7..4) + 20 + 1 + + + CTEIF6 + Stream x clear transfer error interrupt + flag (x = 7..4) + 19 + 1 + + + CDMEIF6 + Stream x clear direct mode error + interrupt flag (x = 7..4) + 18 + 1 + + + CFEIF6 + Stream x clear FIFO error interrupt flag + (x = 7..4) + 16 + 1 + + + CTCIF5 + Stream x clear transfer complete + interrupt flag (x = 7..4) + 11 + 1 + + + CHTIF5 + Stream x clear half transfer interrupt + flag (x = 7..4) + 10 + 1 + + + CTEIF5 + Stream x clear transfer error interrupt + flag (x = 7..4) + 9 + 1 + + + CDMEIF5 + Stream x clear direct mode error + interrupt flag (x = 7..4) + 8 + 1 + + + CFEIF5 + Stream x clear FIFO error interrupt flag + (x = 7..4) + 6 + 1 + + + CTCIF4 + Stream x clear transfer complete + interrupt flag (x = 7..4) + 5 + 1 + + + CHTIF4 + Stream x clear half transfer interrupt + flag (x = 7..4) + 4 + 1 + + + CTEIF4 + Stream x clear transfer error interrupt + flag (x = 7..4) + 3 + 1 + + + CDMEIF4 + Stream x clear direct mode error + interrupt flag (x = 7..4) + 2 + 1 + + + CFEIF4 + Stream x clear FIFO error interrupt flag + (x = 7..4) + 0 + 1 + + + + + S0CR + S0CR + stream x configuration + register + 0x10 + 0x20 + read-write + 0x00000000 + + + MBURST + Memory burst transfer + configuration + 23 + 2 + + + PBURST + Peripheral burst transfer + configuration + 21 + 2 + + + CT + Current target (only in double buffer + mode) + 19 + 1 + + + DBM + Double buffer mode + 18 + 1 + + + PL + Priority level + 16 + 2 + + + PINCOS + Peripheral increment offset + size + 15 + 1 + + + MSIZE + Memory data size + 13 + 2 + + + PSIZE + Peripheral data size + 11 + 2 + + + MINC + Memory increment mode + 10 + 1 + + + PINC + Peripheral increment mode + 9 + 1 + + + CIRC + Circular mode + 8 + 1 + + + DIR + Data transfer direction + 6 + 2 + + + PFCTRL + Peripheral flow controller + 5 + 1 + + + TCIE + Transfer complete interrupt + enable + 4 + 1 + + + HTIE + Half transfer interrupt + enable + 3 + 1 + + + TEIE + Transfer error interrupt + enable + 2 + 1 + + + DMEIE + Direct mode error interrupt + enable + 1 + 1 + + + EN + Stream enable / flag stream ready when + read low + 0 + 1 + + + + + S0NDTR + S0NDTR + stream x number of data + register + 0x14 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data items to + transfer + 0 + 16 + + + + + S0PAR + S0PAR + stream x peripheral address + register + 0x18 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + S0M0AR + S0M0AR + stream x memory 0 address + register + 0x1C + 0x20 + read-write + 0x00000000 + + + M0A + Memory 0 address + 0 + 32 + + + + + S0M1AR + S0M1AR + stream x memory 1 address + register + 0x20 + 0x20 + read-write + 0x00000000 + + + M1A + Memory 1 address (used in case of Double + buffer mode) + 0 + 32 + + + + + S0FCR + S0FCR + stream x FIFO control register + 0x24 + 0x20 + 0x00000021 + + + FEIE + FIFO error interrupt + enable + 7 + 1 + read-write + + + FS + FIFO status + 3 + 3 + read-only + + + DMDIS + Direct mode disable + 2 + 1 + read-write + + + FTH + FIFO threshold selection + 0 + 2 + read-write + + + + + S1CR + S1CR + stream x configuration + register + 0x28 + 0x20 + read-write + 0x00000000 + + + MBURST + Memory burst transfer + configuration + 23 + 2 + + + PBURST + Peripheral burst transfer + configuration + 21 + 2 + + + ACK + ACK + 20 + 1 + + + CT + Current target (only in double buffer + mode) + 19 + 1 + + + DBM + Double buffer mode + 18 + 1 + + + PL + Priority level + 16 + 2 + + + PINCOS + Peripheral increment offset + size + 15 + 1 + + + MSIZE + Memory data size + 13 + 2 + + + PSIZE + Peripheral data size + 11 + 2 + + + MINC + Memory increment mode + 10 + 1 + + + PINC + Peripheral increment mode + 9 + 1 + + + CIRC + Circular mode + 8 + 1 + + + DIR + Data transfer direction + 6 + 2 + + + PFCTRL + Peripheral flow controller + 5 + 1 + + + TCIE + Transfer complete interrupt + enable + 4 + 1 + + + HTIE + Half transfer interrupt + enable + 3 + 1 + + + TEIE + Transfer error interrupt + enable + 2 + 1 + + + DMEIE + Direct mode error interrupt + enable + 1 + 1 + + + EN + Stream enable / flag stream ready when + read low + 0 + 1 + + + + + S1NDTR + S1NDTR + stream x number of data + register + 0x2C + 0x20 + read-write + 0x00000000 + + + NDT + Number of data items to + transfer + 0 + 16 + + + + + S1PAR + S1PAR + stream x peripheral address + register + 0x30 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + S1M0AR + S1M0AR + stream x memory 0 address + register + 0x34 + 0x20 + read-write + 0x00000000 + + + M0A + Memory 0 address + 0 + 32 + + + + + S1M1AR + S1M1AR + stream x memory 1 address + register + 0x38 + 0x20 + read-write + 0x00000000 + + + M1A + Memory 1 address (used in case of Double + buffer mode) + 0 + 32 + + + + + S1FCR + S1FCR + stream x FIFO control register + 0x3C + 0x20 + 0x00000021 + + + FEIE + FIFO error interrupt + enable + 7 + 1 + read-write + + + FS + FIFO status + 3 + 3 + read-only + + + DMDIS + Direct mode disable + 2 + 1 + read-write + + + FTH + FIFO threshold selection + 0 + 2 + read-write + + + + + S2CR + S2CR + stream x configuration + register + 0x40 + 0x20 + read-write + 0x00000000 + + + MBURST + Memory burst transfer + configuration + 23 + 2 + + + PBURST + Peripheral burst transfer + configuration + 21 + 2 + + + ACK + ACK + 20 + 1 + + + CT + Current target (only in double buffer + mode) + 19 + 1 + + + DBM + Double buffer mode + 18 + 1 + + + PL + Priority level + 16 + 2 + + + PINCOS + Peripheral increment offset + size + 15 + 1 + + + MSIZE + Memory data size + 13 + 2 + + + PSIZE + Peripheral data size + 11 + 2 + + + MINC + Memory increment mode + 10 + 1 + + + PINC + Peripheral increment mode + 9 + 1 + + + CIRC + Circular mode + 8 + 1 + + + DIR + Data transfer direction + 6 + 2 + + + PFCTRL + Peripheral flow controller + 5 + 1 + + + TCIE + Transfer complete interrupt + enable + 4 + 1 + + + HTIE + Half transfer interrupt + enable + 3 + 1 + + + TEIE + Transfer error interrupt + enable + 2 + 1 + + + DMEIE + Direct mode error interrupt + enable + 1 + 1 + + + EN + Stream enable / flag stream ready when + read low + 0 + 1 + + + + + S2NDTR + S2NDTR + stream x number of data + register + 0x44 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data items to + transfer + 0 + 16 + + + + + S2PAR + S2PAR + stream x peripheral address + register + 0x48 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + S2M0AR + S2M0AR + stream x memory 0 address + register + 0x4C + 0x20 + read-write + 0x00000000 + + + M0A + Memory 0 address + 0 + 32 + + + + + S2M1AR + S2M1AR + stream x memory 1 address + register + 0x50 + 0x20 + read-write + 0x00000000 + + + M1A + Memory 1 address (used in case of Double + buffer mode) + 0 + 32 + + + + + S2FCR + S2FCR + stream x FIFO control register + 0x54 + 0x20 + 0x00000021 + + + FEIE + FIFO error interrupt + enable + 7 + 1 + read-write + + + FS + FIFO status + 3 + 3 + read-only + + + DMDIS + Direct mode disable + 2 + 1 + read-write + + + FTH + FIFO threshold selection + 0 + 2 + read-write + + + + + S3CR + S3CR + stream x configuration + register + 0x58 + 0x20 + read-write + 0x00000000 + + + MBURST + Memory burst transfer + configuration + 23 + 2 + + + PBURST + Peripheral burst transfer + configuration + 21 + 2 + + + ACK + ACK + 20 + 1 + + + CT + Current target (only in double buffer + mode) + 19 + 1 + + + DBM + Double buffer mode + 18 + 1 + + + PL + Priority level + 16 + 2 + + + PINCOS + Peripheral increment offset + size + 15 + 1 + + + MSIZE + Memory data size + 13 + 2 + + + PSIZE + Peripheral data size + 11 + 2 + + + MINC + Memory increment mode + 10 + 1 + + + PINC + Peripheral increment mode + 9 + 1 + + + CIRC + Circular mode + 8 + 1 + + + DIR + Data transfer direction + 6 + 2 + + + PFCTRL + Peripheral flow controller + 5 + 1 + + + TCIE + Transfer complete interrupt + enable + 4 + 1 + + + HTIE + Half transfer interrupt + enable + 3 + 1 + + + TEIE + Transfer error interrupt + enable + 2 + 1 + + + DMEIE + Direct mode error interrupt + enable + 1 + 1 + + + EN + Stream enable / flag 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compare + 2 + 14 + 1 + + + AD2TAPER + ADC trigger 2 on Timer A + Period + 13 + 1 + + + AD2TAC4 + ADC trigger 2 on Timer A compare + 4 + 12 + 1 + + + AD2TAC3 + ADC trigger 2 on Timer A compare + 3 + 11 + 1 + + + AD2TAC2 + ADC trigger 2 on Timer A compare + 2 + 10 + 1 + + + AD2EEV10 + ADC trigger 2 on External Event + 10 + 9 + 1 + + + AD2EEV9 + ADC trigger 2 on External Event + 9 + 8 + 1 + + + AD2EEV8 + ADC trigger 2 on External Event + 8 + 7 + 1 + + + AD2EEV7 + ADC trigger 2 on External Event + 7 + 6 + 1 + + + AD2EEV6 + ADC trigger 2 on External Event + 6 + 5 + 1 + + + AD2MPER + ADC trigger 2 on Master + Period + 4 + 1 + + + AD2MC4 + ADC trigger 2 on Master Compare + 4 + 3 + 1 + + + AD2MC3 + ADC trigger 2 on Master Compare + 3 + 2 + 1 + + + AD2MC2 + ADC trigger 2 on Master Compare + 2 + 1 + 1 + + + AD2MC1 + ADC trigger 2 on Master Compare + 1 + 0 + 1 + + + + + ADC3R + ADC3R + ADC Trigger 3 Register + 0x44 + 0x20 + read-write + 0x00000000 + + + AD1TEPER + AD1TEPER + 31 + 1 + + + AD1TEC4 + AD1TEC4 + 30 + 1 + + + AD1TEC3 + AD1TEC3 + 29 + 1 + + + AD1TEC2 + AD1TEC2 + 28 + 1 + + + AD1TDPER + AD1TDPER + 27 + 1 + + + AD1TDC4 + AD1TDC4 + 26 + 1 + + + AD1TDC3 + AD1TDC3 + 25 + 1 + + + AD1TDC2 + AD1TDC2 + 24 + 1 + + + AD1TCPER + AD1TCPER + 23 + 1 + + + AD1TCC4 + AD1TCC4 + 22 + 1 + + + AD1TCC3 + AD1TCC3 + 21 + 1 + + + AD1TCC2 + AD1TCC2 + 20 + 1 + + + AD1TBRST + AD1TBRST + 19 + 1 + + + AD1TBPER + AD1TBPER + 18 + 1 + + + AD1TBC4 + AD1TBC4 + 17 + 1 + + + AD1TBC3 + AD1TBC3 + 16 + 1 + + + AD1TBC2 + AD1TBC2 + 15 + 1 + + + AD1TARST + AD1TARST + 14 + 1 + + + AD1TAPER + AD1TAPER + 13 + 1 + + + AD1TAC4 + AD1TAC4 + 12 + 1 + + + AD1TAC3 + AD1TAC3 + 11 + 1 + + + AD1TAC2 + AD1TAC2 + 10 + 1 + + + AD1EEV5 + AD1EEV5 + 9 + 1 + + + AD1EEV4 + AD1EEV4 + 8 + 1 + + + AD1EEV3 + AD1EEV3 + 7 + 1 + + + AD1EEV2 + AD1EEV2 + 6 + 1 + + + AD1EEV1 + AD1EEV1 + 5 + 1 + + + AD1MPER + AD1MPER + 4 + 1 + + + AD1MC4 + AD1MC4 + 3 + 1 + + + AD1MC3 + AD1MC3 + 2 + 1 + + + AD1MC2 + AD1MC2 + 1 + 1 + + + AD1MC1 + AD1MC1 + 0 + 1 + + + + + ADC4R + ADC4R + ADC Trigger 4 Register + 0x48 + 0x20 + read-write + 0x00000000 + + + AD2TERST + AD2TERST + 31 + 1 + + + AD2TEC4 + AD2TEC4 + 30 + 1 + + + AD2TEC3 + AD2TEC3 + 29 + 1 + + + AD2TEC2 + AD2TEC2 + 28 + 1 + + + AD2TDRST + AD2TDRST + 27 + 1 + + + AD2TDPER + AD2TDPER + 26 + 1 + + + AD2TDC4 + AD2TDC4 + 25 + 1 + + + AD2TDC3 + AD2TDC3 + 24 + 1 + + + AD2TDC2 + AD2TDC2 + 23 + 1 + + + AD2TCRST + AD2TCRST + 22 + 1 + + + AD2TCPER + AD2TCPER + 21 + 1 + + + AD2TCC4 + AD2TCC4 + 20 + 1 + + + AD2TCC3 + AD2TCC3 + 19 + 1 + + + AD2TCC2 + AD2TCC2 + 18 + 1 + + + AD2TBPER + AD2TBPER + 17 + 1 + + + AD2TBC4 + AD2TBC4 + 16 + 1 + + + AD2TBC3 + AD2TBC3 + 15 + 1 + + + AD2TBC2 + AD2TBC2 + 14 + 1 + + + AD2TAPER + AD2TAPER + 13 + 1 + + + AD2TAC4 + AD2TAC4 + 12 + 1 + + + AD2TAC3 + AD2TAC3 + 11 + 1 + + + AD2TAC2 + AD2TAC2 + 10 + 1 + + + AD2EEV10 + AD2EEV10 + 9 + 1 + + + AD2EEV9 + AD2EEV9 + 8 + 1 + + + AD2EEV8 + AD2EEV8 + 7 + 1 + + + AD2EEV7 + AD2EEV7 + 6 + 1 + + + AD2EEV6 + AD2EEV6 + 5 + 1 + + + AD2MPER + AD2MPER + 4 + 1 + + + AD2MC4 + AD2MC4 + 3 + 1 + + + AD2MC3 + AD2MC3 + 2 + 1 + + + AD2MC2 + AD2MC2 + 1 + 1 + + + AD2MC1 + AD2MC1 + 0 + 1 + + + + + DLLCR + DLLCR + DLL Control Register + 0x4C + 0x20 + read-write + 0x00000000 + + + CALRTE + DLL Calibration rate + 2 + 2 + + + CALEN + DLL Calibration Enable + 1 + 1 + + + CAL + DLL Calibration Start + 0 + 1 + + + + + FLTINR1 + FLTINR1 + HRTIM Fault Input Register 1 + 0x50 + 0x20 + read-write + 0x00000000 + + + FLT4LCK + FLT4LCK + 31 + 1 + + + FLT4F + FLT4F + 27 + 4 + + + FLT4SRC + FLT4SRC + 26 + 1 + + + FLT4P + FLT4P + 25 + 1 + + + FLT4E + FLT4E + 24 + 1 + + + FLT3LCK + FLT3LCK + 23 + 1 + + + FLT3F + FLT3F + 19 + 4 + + + FLT3SRC + FLT3SRC + 18 + 1 + + + FLT3P + FLT3P + 17 + 1 + + + FLT3E + FLT3E + 16 + 1 + + + FLT2LCK + FLT2LCK + 15 + 1 + + + FLT2F + FLT2F + 11 + 4 + + + FLT2SRC + FLT2SRC + 10 + 1 + + + FLT2P + FLT2P + 9 + 1 + + + FLT2E + FLT2E + 8 + 1 + + + FLT1LCK + FLT1LCK + 7 + 1 + + + FLT1F + FLT1F + 3 + 4 + + + FLT1SRC + FLT1SRC + 2 + 1 + + + FLT1P + FLT1P + 1 + 1 + + + FLT1E + FLT1E + 0 + 1 + + + + + FLTINR2 + FLTINR2 + HRTIM Fault Input Register 2 + 0x54 + 0x20 + read-write + 0x00000000 + + + FLTSD + FLTSD + 24 + 2 + + + FLT5LCK + FLT5LCK + 7 + 1 + + + FLT5F + FLT5F + 3 + 4 + + + FLT5SRC + FLT5SRC + 2 + 1 + + + FLT5P + FLT5P + 1 + 1 + + + FLT5E + FLT5E + 0 + 1 + + + + + BDMUPDR + BDMUPDR + BDMUPDR + 0x58 + 0x20 + read-write + 0x00000000 + + + MCMP4 + MCMP4 + 9 + 1 + + + MCMP3 + MCMP3 + 8 + 1 + + + MCMP2 + MCMP2 + 7 + 1 + + + MCMP1 + MCMP1 + 6 + 1 + + + MREP + MREP + 5 + 1 + + + MPER + MPER + 4 + 1 + + + MCNT + MCNT + 3 + 1 + + + MDIER + MDIER + 2 + 1 + + + MICR + MICR + 1 + 1 + + + MCR + MCR + 0 + 1 + + + + + BDTxUPR + BDTxUPR + Burst DMA Timerx update + Register + 0x5C + 0x20 + read-write + 0x00000000 + + + TIMxFLTR + HRTIM_FLTxR register update + enable + 20 + 1 + + + TIMxOUTR + HRTIM_OUTxR register update + enable + 19 + 1 + + + TIMxCHPR + HRTIM_CHPxR register update + enable + 18 + 1 + + + TIMxRSTR + HRTIM_RSTxR register update + enable + 17 + 1 + + + TIMxEEFR2 + HRTIM_EEFxR2 register update + enable + 16 + 1 + + + TIMxEEFR1 + HRTIM_EEFxR1 register update + enable + 15 + 1 + + + TIMxRST2R + HRTIM_RST2xR register update + enable + 14 + 1 + + + TIMxSET2R + HRTIM_SET2xR register update + enable + 13 + 1 + + + TIMxRST1R + HRTIM_RST1xR register update + enable + 12 + 1 + + + TIMxSET1R + HRTIM_SET1xR register update + enable + 11 + 1 + + + TIMx_DTxR + HRTIM_DTxR register update + enable + 10 + 1 + + + TIMxCMP4 + HRTIM_CMP4xR register update + enable + 9 + 1 + + + TIMxCMP3 + HRTIM_CMP3xR register update + enable + 8 + 1 + + + TIMxCMP2 + HRTIM_CMP2xR register update + enable + 7 + 1 + + + TIMxCMP1 + HRTIM_CMP1xR register update + enable + 6 + 1 + + + TIMxREP + HRTIM_REPxR register update + enable + 5 + 1 + + + TIMxPER + HRTIM_PERxR register update + enable + 4 + 1 + + + TIMxCNT + HRTIM_CNTxR register update + enable + 3 + 1 + + + TIMxDIER + HRTIM_TIMxDIER register update + enable + 2 + 1 + + + TIMxICR + HRTIM_TIMxICR register update + enable + 1 + 1 + + + TIMxCR + HRTIM_TIMxCR register update + enable + 0 + 1 + + + + + BDMADR + BDMADR + Burst DMA Data Register + 0x60 + 0x20 + read-write + 0x00000000 + + + BDMADR + Burst DMA Data register + 0 + 32 + + + + + + + DFSDM + Digital filter for sigma delta + modulators + DFSDM + 0x40017000 + + 0x0 + 0x400 + registers + + + DFSDM1_FLT0 + DFSDM1 filter 0 interrupt + 110 + + + DFSDM1_FLT1 + DFSDM1 filter 1 interrupt + 111 + + + DFSDM1_FLT2 + DFSDM1 filter 2 interrupt + 112 + + + DFSDM1_FLT3 + DFSDM1 filter 3 interrupt + 113 + + + + DFSDM_CHCFG0R1 + DFSDM_CHCFG0R1 + DFSDM channel configuration 0 register + 1 + 0x0 + 0x20 + read-write + 0x00000000 + + + SITP + Serial interface type for channel + 0 + 0 + 2 + + + SPICKSEL + SPI clock select for channel + 0 + 2 + 2 + + + SCDEN + Short-circuit detector enable on channel + 0 + 5 + 1 + + + CKABEN + Clock absence detector enable on channel + 0 + 6 + 1 + + + CHEN + Channel 0 enable + 7 + 1 + + + CHINSEL + Channel inputs selection + 8 + 1 + + + DATMPX + Input data multiplexer for channel + 0 + 12 + 2 + + + DATPACK + Data packing mode in DFSDM_CHDATINyR + register + 14 + 2 + + + CKOUTDIV + Output serial clock + divider + 16 + 8 + + + CKOUTSRC + Output serial clock source + selection + 30 + 1 + + + DFSDMEN + Global enable for DFSDM + interface + 31 + 1 + + + + + DFSDM_CHCFG1R1 + DFSDM_CHCFG1R1 + DFSDM channel configuration 1 register + 1 + 0x4 + 0x20 + read-write + 0x00000000 + + + SITP + Serial interface type for channel + 1 + 0 + 2 + + + SPICKSEL + SPI clock select for channel + 1 + 2 + 2 + + + SCDEN + Short-circuit detector enable on channel + 1 + 5 + 1 + + + CKABEN + Clock absence detector enable on channel + 1 + 6 + 1 + + + CHEN + Channel 1 enable + 7 + 1 + + + CHINSEL + Channel inputs selection + 8 + 1 + + + DATMPX + Input data multiplexer for channel + 1 + 12 + 2 + + + DATPACK + Data packing mode in DFSDM_CHDATINyR + register + 14 + 2 + + + CKOUTDIV + Output serial clock + divider + 16 + 8 + + + CKOUTSRC + Output serial clock source + selection + 30 + 1 + + + DFSDMEN + Global enable for DFSDM + interface + 31 + 1 + + + + + DFSDM_CHCFG2R1 + DFSDM_CHCFG2R1 + DFSDM channel configuration 2 register + 1 + 0x8 + 0x20 + read-write + 0x00000000 + + + SITP + Serial interface type for channel + 2 + 0 + 2 + + + SPICKSEL + SPI clock select for channel + 2 + 2 + 2 + + + SCDEN + Short-circuit detector enable on channel + 2 + 5 + 1 + + + CKABEN + Clock absence detector enable on channel + 2 + 6 + 1 + + + CHEN + Channel 2 enable + 7 + 1 + + + CHINSEL + Channel inputs selection + 8 + 1 + + + DATMPX + Input data multiplexer for channel + 2 + 12 + 2 + + + DATPACK + Data packing mode in DFSDM_CHDATINyR + register + 14 + 2 + + + CKOUTDIV + Output serial clock + divider + 16 + 8 + + + CKOUTSRC + Output serial clock source + selection + 30 + 1 + + + DFSDMEN + Global enable for DFSDM + interface + 31 + 1 + + + + + DFSDM_CHCFG3R1 + DFSDM_CHCFG3R1 + DFSDM channel configuration 3 register + 1 + 0xC + 0x20 + read-write + 0x00000000 + + + SITP + Serial interface type for channel + 3 + 0 + 2 + + + SPICKSEL + SPI clock select for channel + 3 + 2 + 2 + + + SCDEN + Short-circuit detector enable on channel + 3 + 5 + 1 + + + CKABEN + Clock absence detector enable on channel + 3 + 6 + 1 + + + CHEN + Channel 3 enable + 7 + 1 + + + CHINSEL + Channel inputs selection + 8 + 1 + + + DATMPX + Input data multiplexer for channel + 3 + 12 + 2 + + + DATPACK + Data packing mode in DFSDM_CHDATINyR + register + 14 + 2 + + + CKOUTDIV + Output serial clock + divider + 16 + 8 + + + CKOUTSRC + Output serial clock source + selection + 30 + 1 + + + DFSDMEN + Global enable for DFSDM + interface + 31 + 1 + + + + + DFSDM_CHCFG4R1 + DFSDM_CHCFG4R1 + DFSDM channel configuration 4 register + 1 + 0x10 + 0x20 + read-write + 0x00000000 + + + SITP + Serial interface type for channel + 4 + 0 + 2 + + + SPICKSEL + SPI clock select for channel + 4 + 2 + 2 + + + SCDEN + Short-circuit detector enable on channel + 4 + 5 + 1 + + + CKABEN + Clock absence detector enable on channel + 4 + 6 + 1 + + + CHEN + Channel 4 enable + 7 + 1 + + + CHINSEL + Channel inputs selection + 8 + 1 + + + DATMPX + Input data multiplexer for channel + 4 + 12 + 2 + + + DATPACK + Data packing mode in DFSDM_CHDATINyR + register + 14 + 2 + + + CKOUTDIV + Output serial clock + divider + 16 + 8 + + + CKOUTSRC + Output serial clock source + selection + 30 + 1 + + + DFSDMEN + Global enable for DFSDM + interface + 31 + 1 + + + + + DFSDM_CHCFG5R1 + DFSDM_CHCFG5R1 + DFSDM channel configuration 5 register + 1 + 0x14 + 0x20 + read-write + 0x00000000 + + + SITP + Serial interface type for channel + 5 + 0 + 2 + + + SPICKSEL + SPI clock select for channel + 5 + 2 + 2 + + + SCDEN + Short-circuit detector enable on channel + 5 + 5 + 1 + + + CKABEN + Clock absence detector enable on channel + 5 + 6 + 1 + + + CHEN + Channel 5 enable + 7 + 1 + + + CHINSEL + Channel inputs selection + 8 + 1 + + + DATMPX + Input data multiplexer for channel + 5 + 12 + 2 + + + DATPACK + Data packing mode in DFSDM_CHDATINyR + register + 14 + 2 + + + CKOUTDIV + Output serial clock + divider + 16 + 8 + + + CKOUTSRC + Output serial clock source + selection + 30 + 1 + + + DFSDMEN + Global enable for DFSDM + interface + 31 + 1 + + + + + DFSDM_CHCFG6R1 + DFSDM_CHCFG6R1 + DFSDM channel configuration 6 register + 1 + 0x18 + 0x20 + read-write + 0x00000000 + + + SITP + Serial interface type for channel + 6 + 0 + 2 + + + SPICKSEL + SPI clock select for channel + 6 + 2 + 2 + + + SCDEN + Short-circuit detector enable on channel + 6 + 5 + 1 + + + CKABEN + Clock absence detector enable on channel + 6 + 6 + 1 + + + CHEN + Channel 6 enable + 7 + 1 + + + CHINSEL + Channel inputs selection + 8 + 1 + + + DATMPX + Input data multiplexer for channel + 6 + 12 + 2 + + + DATPACK + Data packing mode in DFSDM_CHDATINyR + register + 14 + 2 + + + CKOUTDIV + Output serial clock + divider + 16 + 8 + + + CKOUTSRC + Output serial clock source + selection + 30 + 1 + + + DFSDMEN + Global enable for DFSDM + interface + 31 + 1 + + + + + DFSDM_CHCFG7R1 + DFSDM_CHCFG7R1 + DFSDM channel configuration 7 register + 1 + 0x1C + 0x20 + read-write + 0x00000000 + + + SITP + Serial interface type for channel + 7 + 0 + 2 + + + SPICKSEL + SPI clock select for channel + 7 + 2 + 2 + + + SCDEN + Short-circuit detector enable on channel + 7 + 5 + 1 + + + CKABEN + Clock absence detector enable on channel + 7 + 6 + 1 + + + CHEN + Channel 7 enable + 7 + 1 + + + CHINSEL + Channel inputs selection + 8 + 1 + + + DATMPX + Input data multiplexer for channel + 7 + 12 + 2 + + + DATPACK + Data packing mode in DFSDM_CHDATINyR + register + 14 + 2 + + + CKOUTDIV + Output serial clock + divider + 16 + 8 + + + CKOUTSRC + Output serial clock source + selection + 30 + 1 + + + DFSDMEN + Global enable for DFSDM + interface + 31 + 1 + + + + + DFSDM_CHCFG0R2 + DFSDM_CHCFG0R2 + DFSDM channel configuration 0 register + 2 + 0x20 + 0x20 + read-write + 0x00000000 + + + DTRBS + Data right bit-shift for channel + 0 + 3 + 5 + + + OFFSET + 24-bit calibration offset for channel + 0 + 8 + 24 + + + + + DFSDM_CHCFG1R2 + DFSDM_CHCFG1R2 + DFSDM channel configuration 1 register + 2 + 0x24 + 0x20 + read-write + 0x00000000 + + + DTRBS + Data right bit-shift for channel + 1 + 3 + 5 + + + OFFSET + 24-bit calibration offset for channel + 1 + 8 + 24 + + + + + DFSDM_CHCFG2R2 + DFSDM_CHCFG2R2 + DFSDM channel configuration 2 register + 2 + 0x28 + 0x20 + read-write + 0x00000000 + + + DTRBS + Data right bit-shift for channel + 2 + 3 + 5 + + + OFFSET + 24-bit calibration offset for channel + 2 + 8 + 24 + + + + + DFSDM_CHCFG3R2 + DFSDM_CHCFG3R2 + DFSDM channel configuration 3 register + 2 + 0x2C + 0x20 + read-write + 0x00000000 + + + DTRBS + Data right bit-shift for channel + 3 + 3 + 5 + + + OFFSET + 24-bit calibration offset for channel + 3 + 8 + 24 + + + + + DFSDM_CHCFG4R2 + DFSDM_CHCFG4R2 + DFSDM channel configuration 4 register + 2 + 0x30 + 0x20 + read-write + 0x00000000 + + + DTRBS + Data right bit-shift for channel + 4 + 3 + 5 + + + OFFSET + 24-bit calibration offset for channel + 4 + 8 + 24 + + + + + DFSDM_CHCFG5R2 + DFSDM_CHCFG5R2 + DFSDM channel configuration 5 register + 2 + 0x34 + 0x20 + read-write + 0x00000000 + + + DTRBS + Data right bit-shift for channel + 5 + 3 + 5 + + + OFFSET + 24-bit calibration offset for channel + 5 + 8 + 24 + + + + + DFSDM_CHCFG6R2 + DFSDM_CHCFG6R2 + DFSDM channel configuration 6 register + 2 + 0x38 + 0x20 + read-write + 0x00000000 + + + DTRBS + Data right bit-shift for channel + 6 + 3 + 5 + + + OFFSET + 24-bit calibration offset for channel + 6 + 8 + 24 + + + + + DFSDM_CHCFG7R2 + DFSDM_CHCFG7R2 + DFSDM channel configuration 7 register + 2 + 0x3C + 0x20 + read-write + 0x00000000 + + + DTRBS + Data right bit-shift for channel + 7 + 3 + 5 + + + OFFSET + 24-bit calibration offset for channel + 7 + 8 + 24 + + + + + DFSDM_AWSCD0R + DFSDM_AWSCD0R + DFSDM analog watchdog and short-circuit + detector register + 0x40 + 0x20 + read-write + 0x00000000 + + + SCDT + short-circuit detector threshold for + channel 0 + 0 + 8 + + + BKSCD + Break signal assignment for + short-circuit detector on channel 0 + 12 + 4 + + + AWFOSR + Analog watchdog filter oversampling + ratio (decimation rate) on channel 0 + 16 + 5 + + + AWFORD + Analog watchdog Sinc filter order on + channel 0 + 22 + 2 + + + + + DFSDM_AWSCD1R + DFSDM_AWSCD1R + DFSDM analog watchdog and short-circuit + detector register + 0x44 + 0x20 + read-write + 0x00000000 + + + SCDT + short-circuit detector threshold for + channel 1 + 0 + 8 + + + BKSCD + Break signal assignment for + short-circuit detector on channel 1 + 12 + 4 + + + AWFOSR + Analog watchdog filter oversampling + ratio (decimation rate) on channel 1 + 16 + 5 + + + AWFORD + Analog watchdog Sinc filter order on + channel 1 + 22 + 2 + + + + + DFSDM_AWSCD2R + DFSDM_AWSCD2R + DFSDM analog watchdog and short-circuit + detector register + 0x48 + 0x20 + read-write + 0x00000000 + + + SCDT + short-circuit detector threshold for + channel 2 + 0 + 8 + + + BKSCD + Break signal assignment for + short-circuit detector on channel 2 + 12 + 4 + + + AWFOSR + Analog watchdog filter oversampling + ratio (decimation rate) on channel 2 + 16 + 5 + + + AWFORD + Analog watchdog Sinc filter order on + channel 2 + 22 + 2 + + + + + DFSDM_AWSCD3R + DFSDM_AWSCD3R + DFSDM analog watchdog and short-circuit + detector register + 0x4C + 0x20 + read-write + 0x00000000 + + + SCDT + short-circuit detector threshold for + channel 3 + 0 + 8 + + + BKSCD + Break signal assignment for + short-circuit detector on channel 3 + 12 + 4 + + + AWFOSR + Analog watchdog filter oversampling + ratio (decimation rate) on channel 3 + 16 + 5 + + + AWFORD + Analog watchdog Sinc filter order on + channel 3 + 22 + 2 + + + + + DFSDM_AWSCD4R + DFSDM_AWSCD4R + DFSDM analog watchdog and short-circuit + detector register + 0x50 + 0x20 + read-write + 0x00000000 + + + SCDT + short-circuit detector threshold for + channel 4 + 0 + 8 + + + BKSCD + Break signal assignment for + short-circuit detector on channel 4 + 12 + 4 + + + AWFOSR + Analog watchdog filter oversampling + ratio (decimation rate) on channel 4 + 16 + 5 + + + AWFORD + Analog watchdog Sinc filter order on + channel 4 + 22 + 2 + + + + + DFSDM_AWSCD5R + DFSDM_AWSCD5R + DFSDM analog watchdog and short-circuit + detector register + 0x54 + 0x20 + read-write + 0x00000000 + + + SCDT + short-circuit detector threshold for + channel 5 + 0 + 8 + + + BKSCD + Break signal assignment for + short-circuit detector on channel 5 + 12 + 4 + + + AWFOSR + Analog watchdog filter oversampling + ratio (decimation rate) on channel 5 + 16 + 5 + + + AWFORD + Analog watchdog Sinc filter order on + channel 5 + 22 + 2 + + + + + DFSDM_AWSCD6R + DFSDM_AWSCD6R + DFSDM analog watchdog and short-circuit + detector register + 0x58 + 0x20 + read-write + 0x00000000 + + + SCDT + short-circuit detector threshold for + channel 6 + 0 + 8 + + + BKSCD + Break signal assignment for + short-circuit detector on channel 6 + 12 + 4 + + + AWFOSR + Analog watchdog filter oversampling + ratio (decimation rate) on channel 6 + 16 + 5 + + + AWFORD + Analog watchdog Sinc filter order on + channel 6 + 22 + 2 + + + + + DFSDM_AWSCD7R + DFSDM_AWSCD7R + DFSDM analog watchdog and short-circuit + detector register + 0x5C + 0x20 + read-write + 0x00000000 + + + SCDT + short-circuit detector threshold for + channel 7 + 0 + 8 + + + BKSCD + Break signal assignment for + short-circuit detector on channel 7 + 12 + 4 + + + AWFOSR + Analog watchdog filter oversampling + ratio (decimation rate) on channel 7 + 16 + 5 + + + AWFORD + Analog watchdog Sinc filter order on + channel 7 + 22 + 2 + + + + + DFSDM_CHWDAT0R + DFSDM_CHWDAT0R + DFSDM channel watchdog filter data + register + 0x60 + 0x20 + read-only + 0x00000000 + + + WDATA + Input channel y watchdog + data + 0 + 16 + + + + + DFSDM_CHWDAT1R + DFSDM_CHWDAT1R + DFSDM channel watchdog filter data + register + 0x64 + 0x20 + read-only + 0x00000000 + + + WDATA + Input channel y watchdog + data + 0 + 16 + + + + + DFSDM_CHWDAT2R + DFSDM_CHWDAT2R + DFSDM channel watchdog filter data + register + 0x68 + 0x20 + read-only + 0x00000000 + + + WDATA + Input channel y watchdog + data + 0 + 16 + + + + + DFSDM_CHWDAT3R + DFSDM_CHWDAT3R + DFSDM channel watchdog filter data + register + 0x6C + 0x20 + read-only + 0x00000000 + + + WDATA + Input channel y watchdog + data + 0 + 16 + + + + + DFSDM_CHWDAT4R + DFSDM_CHWDAT4R + DFSDM channel watchdog filter data + register + 0x70 + 0x20 + read-only + 0x00000000 + + + WDATA + Input channel y watchdog + data + 0 + 16 + + + + + DFSDM_CHWDAT5R + DFSDM_CHWDAT5R + DFSDM channel watchdog filter data + register + 0x74 + 0x20 + read-only + 0x00000000 + + + WDATA + Input channel y watchdog + data + 0 + 16 + + + + + DFSDM_CHWDAT6R + DFSDM_CHWDAT6R + DFSDM channel watchdog filter data + register + 0x78 + 0x20 + read-only + 0x00000000 + + + WDATA + Input channel y watchdog + data + 0 + 16 + + + + + DFSDM_CHWDAT7R + DFSDM_CHWDAT7R + DFSDM channel watchdog filter data + register + 0x7C + 0x20 + read-only + 0x00000000 + + + WDATA + Input channel y watchdog + data + 0 + 16 + + + + + DFSDM_CHDATIN0R + DFSDM_CHDATIN0R + DFSDM channel data input + register + 0x80 + 0x20 + read-write + 0x00000000 + + + INDAT0 + Input data for channel 0 + 0 + 16 + + + INDAT1 + Input data for channel 1 + 16 + 16 + + + + + DFSDM_CHDATIN1R + DFSDM_CHDATIN1R + DFSDM channel data input + register + 0x84 + 0x20 + read-write + 0x00000000 + + + INDAT0 + Input data for channel 1 + 0 + 16 + + + INDAT1 + Input data for channel 2 + 16 + 16 + + + + + DFSDM_CHDATIN2R + DFSDM_CHDATIN2R + DFSDM channel data input + register + 0x88 + 0x20 + read-write + 0x00000000 + + + INDAT0 + Input data for channel 2 + 0 + 16 + + + INDAT1 + Input data for channel 3 + 16 + 16 + + + + + DFSDM_CHDATIN3R + DFSDM_CHDATIN3R + DFSDM channel data input + register + 0x8C + 0x20 + read-write + 0x00000000 + + + INDAT0 + Input data for channel 3 + 0 + 16 + + + INDAT1 + Input data for channel 4 + 16 + 16 + + + + + DFSDM_CHDATIN4R + DFSDM_CHDATIN4R + DFSDM channel data input + register + 0x90 + 0x20 + read-write + 0x00000000 + + + INDAT0 + Input data for channel 4 + 0 + 16 + + + INDAT1 + Input data for channel 5 + 16 + 16 + + + + + DFSDM_CHDATIN5R + DFSDM_CHDATIN5R + DFSDM channel data input + register + 0x94 + 0x20 + read-write + 0x00000000 + + + INDAT0 + Input data for channel 5 + 0 + 16 + + + INDAT1 + Input data for channel 6 + 16 + 16 + + + + + DFSDM_CHDATIN6R + DFSDM_CHDATIN6R + DFSDM channel data input + register + 0x98 + 0x20 + read-write + 0x00000000 + + + INDAT0 + Input data for channel 6 + 0 + 16 + + + INDAT1 + Input data for channel 7 + 16 + 16 + + + + + DFSDM_CHDATIN7R + DFSDM_CHDATIN7R + DFSDM channel data input + register + 0x9C + 0x20 + read-write + 0x00000000 + + + INDAT0 + Input data for channel 7 + 0 + 16 + + + INDAT1 + Input data for channel 8 + 16 + 16 + + + + + DFSDM0_CR1 + DFSDM0_CR1 + DFSDM control register 1 + 0xA0 + 0x20 + read-write + 0x00000000 + + + DFEN + DFSDM enable + 0 + 1 + + + JSWSTART + Start a conversion of the injected group + of channels + 1 + 1 + + + JSYNC + Launch an injected conversion + synchronously with the DFSDM0 JSWSTART + trigger + 3 + 1 + + + JSCAN + Scanning conversion mode for injected + conversions + 4 + 1 + + + JDMAEN + DMA channel enabled to read data for the + injected channel group + 5 + 1 + + + JEXTSEL + Trigger signal selection for launching + injected conversions + 8 + 5 + + + JEXTEN + Trigger enable and trigger edge + selection for injected conversions + 13 + 2 + + + RSWSTART + Software start of a conversion on the + regular channel + 17 + 1 + + + RCONT + Continuous mode selection for regular + conversions + 18 + 1 + + + RSYNC + Launch regular conversion synchronously + with DFSDM0 + 19 + 1 + + + RDMAEN + DMA channel enabled to read data for the + regular conversion + 21 + 1 + + + RCH + Regular channel selection + 24 + 3 + + + FAST + Fast conversion mode selection for + regular conversions + 29 + 1 + + + AWFSEL + Analog watchdog fast mode + select + 30 + 1 + + + + + DFSDM1_CR1 + DFSDM1_CR1 + DFSDM control register 1 + 0xA4 + 0x20 + read-write + 0x00000000 + + + DFEN + DFSDM enable + 0 + 1 + + + JSWSTART + Start a conversion of the injected group + of channels + 1 + 1 + + + JSYNC + Launch an injected conversion + synchronously with the DFSDM0 JSWSTART + trigger + 3 + 1 + + + JSCAN + Scanning conversion mode for injected + conversions + 4 + 1 + + + JDMAEN + DMA channel enabled to read data for the + injected channel group + 5 + 1 + + + JEXTSEL + Trigger signal selection for launching + injected conversions + 8 + 5 + + + JEXTEN + Trigger enable and trigger edge + selection for injected conversions + 13 + 2 + + + RSWSTART + Software start of a conversion on the + regular channel + 17 + 1 + + + RCONT + Continuous mode selection for regular + conversions + 18 + 1 + + + RSYNC + Launch regular conversion synchronously + with DFSDM0 + 19 + 1 + + + RDMAEN + DMA channel enabled to read data for the + regular conversion + 21 + 1 + + + RCH + Regular channel selection + 24 + 3 + + + FAST + Fast conversion mode selection for + regular conversions + 29 + 1 + + + AWFSEL + Analog watchdog fast mode + select + 30 + 1 + + + + + DFSDM2_CR1 + DFSDM2_CR1 + DFSDM control register 1 + 0xA8 + 0x20 + read-write + 0x00000000 + + + DFEN + DFSDM enable + 0 + 1 + + + JSWSTART + Start a conversion of the injected group + of channels + 1 + 1 + + + JSYNC + Launch an injected conversion + synchronously with the DFSDM0 JSWSTART + trigger + 3 + 1 + + + JSCAN + Scanning conversion mode for injected + conversions + 4 + 1 + + + JDMAEN + DMA channel enabled to read data for the + injected channel group + 5 + 1 + + + JEXTSEL + Trigger signal selection for launching + injected conversions + 8 + 5 + + + JEXTEN + Trigger enable and trigger edge + selection for injected conversions + 13 + 2 + + + RSWSTART + Software start of a conversion on the + regular channel + 17 + 1 + + + RCONT + Continuous mode selection for regular + conversions + 18 + 1 + + + RSYNC + Launch regular conversion synchronously + with DFSDM0 + 19 + 1 + + + RDMAEN + DMA channel enabled to read data for the + regular conversion + 21 + 1 + + + RCH + Regular channel selection + 24 + 3 + + + FAST + Fast conversion mode selection for + regular conversions + 29 + 1 + + + AWFSEL + Analog watchdog fast mode + select + 30 + 1 + + + + + DFSDM3_CR1 + DFSDM3_CR1 + DFSDM control register 1 + 0xAC + 0x20 + read-write + 0x00000000 + + + DFEN + DFSDM enable + 0 + 1 + + + JSWSTART + Start a conversion of the injected group + of channels + 1 + 1 + + + JSYNC + Launch an injected conversion + synchronously with the DFSDM0 JSWSTART + trigger + 3 + 1 + + + JSCAN + Scanning conversion mode for injected + conversions + 4 + 1 + + + JDMAEN + DMA channel enabled to read data for the + injected channel group + 5 + 1 + + + JEXTSEL + Trigger signal selection for launching + injected conversions + 8 + 5 + + + JEXTEN + Trigger enable and trigger edge + selection for injected conversions + 13 + 2 + + + RSWSTART + Software start of a conversion on the + regular channel + 17 + 1 + + + RCONT + Continuous mode selection for regular + conversions + 18 + 1 + + + RSYNC + Launch regular conversion synchronously + with DFSDM0 + 19 + 1 + + + RDMAEN + DMA channel enabled to read data for the + regular conversion + 21 + 1 + + + RCH + Regular channel selection + 24 + 3 + + + FAST + Fast conversion mode selection for + regular conversions + 29 + 1 + + + AWFSEL + Analog watchdog fast mode + select + 30 + 1 + + + + + DFSDM0_CR2 + DFSDM0_CR2 + DFSDM control register 2 + 0xB0 + 0x20 + read-write + 0x00000000 + + + JEOCIE + Injected end of conversion interrupt + enable + 0 + 1 + + + REOCIE + Regular end of conversion interrupt + enable + 1 + 1 + + + JOVRIE + Injected data overrun interrupt + enable + 2 + 1 + + + ROVRIE + Regular data overrun interrupt + enable + 3 + 1 + + + AWDIE + Analog watchdog interrupt + enable + 4 + 1 + + + SCDIE + Short-circuit detector interrupt + enable + 5 + 1 + + + CKABIE + Clock absence interrupt + enable + 6 + 1 + + + EXCH + Extremes detector channel + selection + 8 + 8 + + + AWDCH + Analog watchdog channel + selection + 16 + 8 + + + + + DFSDM1_CR2 + DFSDM1_CR2 + DFSDM control register 2 + 0xB4 + 0x20 + read-write + 0x00000000 + + + JEOCIE + Injected end of conversion interrupt + enable + 0 + 1 + + + REOCIE + Regular end of conversion interrupt + enable + 1 + 1 + + + JOVRIE + Injected data overrun interrupt + enable + 2 + 1 + + + ROVRIE + Regular data overrun interrupt + enable + 3 + 1 + + + AWDIE + Analog watchdog interrupt + enable + 4 + 1 + + + SCDIE + Short-circuit detector interrupt + enable + 5 + 1 + + + CKABIE + Clock absence interrupt + enable + 6 + 1 + + + EXCH + Extremes detector channel + selection + 8 + 8 + + + AWDCH + Analog watchdog channel + selection + 16 + 8 + + + + + DFSDM2_CR2 + DFSDM2_CR2 + DFSDM control register 2 + 0xB8 + 0x20 + read-write + 0x00000000 + + + JEOCIE + Injected end of conversion interrupt + enable + 0 + 1 + + + REOCIE + Regular end of conversion interrupt + enable + 1 + 1 + + + JOVRIE + Injected data overrun interrupt + enable + 2 + 1 + + + ROVRIE + Regular data overrun interrupt + enable + 3 + 1 + + + AWDIE + Analog watchdog interrupt + enable + 4 + 1 + + + SCDIE + Short-circuit detector interrupt + enable + 5 + 1 + + + CKABIE + Clock absence interrupt + enable + 6 + 1 + + + EXCH + Extremes detector channel + selection + 8 + 8 + + + AWDCH + Analog watchdog channel + selection + 16 + 8 + + + + + DFSDM3_CR2 + DFSDM3_CR2 + DFSDM control register 2 + 0xBC + 0x20 + read-write + 0x00000000 + + + JEOCIE + Injected end of conversion interrupt + enable + 0 + 1 + + + REOCIE + Regular end of conversion interrupt + enable + 1 + 1 + + + JOVRIE + Injected data overrun interrupt + enable + 2 + 1 + + + ROVRIE + Regular data overrun interrupt + enable + 3 + 1 + + + AWDIE + Analog watchdog interrupt + enable + 4 + 1 + + + SCDIE + Short-circuit detector interrupt + enable + 5 + 1 + + + CKABIE + Clock absence interrupt + enable + 6 + 1 + + + EXCH + Extremes detector channel + selection + 8 + 8 + + + AWDCH + Analog watchdog channel + selection + 16 + 8 + + + + + DFSDM0_ISR + DFSDM0_ISR + DFSDM interrupt and status + register + 0xC0 + 0x20 + read-only + 0x00000000 + + + JEOCF + End of injected conversion + flag + 0 + 1 + + + REOCF + End of regular conversion + flag + 1 + 1 + + + JOVRF + Injected conversion overrun + flag + 2 + 1 + + + ROVRF + Regular conversion overrun + flag + 3 + 1 + + + AWDF + Analog watchdog + 4 + 1 + + + JCIP + Injected conversion in progress + status + 13 + 1 + + + RCIP + Regular conversion in progress + status + 14 + 1 + + + CKABF + Clock absence flag + 16 + 8 + + + SCDF + short-circuit detector + flag + 24 + 8 + + + + + DFSDM1_ISR + DFSDM1_ISR + DFSDM interrupt and status + register + 0xC4 + 0x20 + read-only + 0x00000000 + + + JEOCF + End of injected conversion + flag + 0 + 1 + + + REOCF + End of regular conversion + flag + 1 + 1 + + + JOVRF + Injected conversion overrun + flag + 2 + 1 + + + ROVRF + Regular conversion overrun + flag + 3 + 1 + + + AWDF + Analog watchdog + 4 + 1 + + + JCIP + Injected conversion in progress + status + 13 + 1 + + + RCIP + Regular conversion in progress + status + 14 + 1 + + + CKABF + Clock absence flag + 16 + 8 + + + SCDF + short-circuit detector + flag + 24 + 8 + + + + + DFSDM2_ISR + DFSDM2_ISR + DFSDM interrupt and status + register + 0xC8 + 0x20 + read-only + 0x00000000 + + + JEOCF + End of injected conversion + flag + 0 + 1 + + + REOCF + End of regular conversion + flag + 1 + 1 + + + JOVRF + Injected conversion overrun + flag + 2 + 1 + + + ROVRF + Regular conversion overrun + flag + 3 + 1 + + + AWDF + Analog watchdog + 4 + 1 + + + JCIP + Injected conversion in progress + status + 13 + 1 + + + RCIP + Regular conversion in progress + status + 14 + 1 + + + CKABF + Clock absence flag + 16 + 8 + + + SCDF + short-circuit detector + flag + 24 + 8 + + + + + DFSDM3_ISR + DFSDM3_ISR + DFSDM interrupt and status + register + 0xCC + 0x20 + read-only + 0x00000000 + + + JEOCF + End of injected conversion + flag + 0 + 1 + + + REOCF + End of regular conversion + flag + 1 + 1 + + + JOVRF + Injected conversion overrun + flag + 2 + 1 + + + ROVRF + Regular conversion overrun + flag + 3 + 1 + + + AWDF + Analog watchdog + 4 + 1 + + + JCIP + Injected conversion in progress + status + 13 + 1 + + + RCIP + Regular conversion in progress + status + 14 + 1 + + + CKABF + Clock absence flag + 16 + 8 + + + SCDF + short-circuit detector + flag + 24 + 8 + + + + + DFSDM0_ICR + DFSDM0_ICR + DFSDM interrupt flag clear + register + 0xD0 + 0x20 + read-write + 0x00000000 + + + CLRJOVRF + Clear the injected conversion overrun + flag + 2 + 1 + + + CLRROVRF + Clear the regular conversion overrun + flag + 3 + 1 + + + CLRCKABF + Clear the clock absence + flag + 16 + 8 + + + CLRSCDF + Clear the short-circuit detector + flag + 24 + 8 + + + + + DFSDM1_ICR + DFSDM1_ICR + DFSDM interrupt flag clear + register + 0xD4 + 0x20 + read-write + 0x00000000 + + + CLRJOVRF + Clear the injected conversion overrun + flag + 2 + 1 + + + CLRROVRF + Clear the regular conversion overrun + flag + 3 + 1 + + + CLRCKABF + Clear the clock absence + flag + 16 + 8 + + + CLRSCDF + Clear the short-circuit detector + flag + 24 + 8 + + + + + DFSDM2_ICR + DFSDM2_ICR + DFSDM interrupt flag clear + register + 0xD8 + 0x20 + read-write + 0x00000000 + + + CLRJOVRF + Clear the injected conversion overrun + flag + 2 + 1 + + + CLRROVRF + Clear the regular conversion overrun + flag + 3 + 1 + + + CLRCKABF + Clear the clock absence + flag + 16 + 8 + + + CLRSCDF + Clear the short-circuit detector + flag + 24 + 8 + + + + + DFSDM3_ICR + DFSDM3_ICR + DFSDM interrupt flag clear + register + 0xDC + 0x20 + read-write + 0x00000000 + + + CLRJOVRF + Clear the injected conversion overrun + flag + 2 + 1 + + + CLRROVRF + Clear the regular conversion overrun + flag + 3 + 1 + + + CLRCKABF + Clear the clock absence + flag + 16 + 8 + + + CLRSCDF + Clear the short-circuit detector + flag + 24 + 8 + + + + + DFSDM0_JCHGR + DFSDM0_JCHGR + DFSDM injected channel group selection + register + 0xE0 + 0x20 + read-write + 0x00000000 + + + JCHG + Injected channel group + selection + 0 + 8 + + + + + DFSDM1_JCHGR + DFSDM1_JCHGR + DFSDM injected channel group selection + register + 0xE4 + 0x20 + read-write + 0x00000000 + + + JCHG + Injected channel group + selection + 0 + 8 + + + + + DFSDM2_JCHGR + DFSDM2_JCHGR + DFSDM injected channel group selection + register + 0xE8 + 0x20 + read-write + 0x00000000 + + + JCHG + Injected channel group + selection + 0 + 8 + + + + + DFSDM3_JCHGR + DFSDM3_JCHGR + DFSDM injected channel group selection + register + 0xEC + 0x20 + read-write + 0x00000000 + + + JCHG + Injected channel group + selection + 0 + 8 + + + + + DFSDM0_FCR + DFSDM0_FCR + DFSDM filter control register + 0xF0 + 0x20 + read-write + 0x00000000 + + + IOSR + Integrator oversampling ratio (averaging + length) + 0 + 8 + + + FOSR + Sinc filter oversampling ratio + (decimation rate) + 16 + 10 + + + FORD + Sinc filter order + 29 + 3 + + + + + DFSDM1_FCR + DFSDM1_FCR + DFSDM filter control register + 0xF4 + 0x20 + read-write + 0x00000000 + + + IOSR + Integrator oversampling ratio (averaging + length) + 0 + 8 + + + FOSR + Sinc filter oversampling ratio + (decimation rate) + 16 + 10 + + + FORD + Sinc filter order + 29 + 3 + + + + + DFSDM2_FCR + DFSDM2_FCR + DFSDM filter control register + 0xF8 + 0x20 + read-write + 0x00000000 + + + IOSR + Integrator oversampling ratio (averaging + length) + 0 + 8 + + + FOSR + Sinc filter oversampling ratio + (decimation rate) + 16 + 10 + + + FORD + Sinc filter order + 29 + 3 + + + + + DFSDM3_FCR + DFSDM3_FCR + DFSDM filter control register + 0xFC + 0x20 + read-write + 0x00000000 + + + IOSR + Integrator oversampling ratio (averaging + length) + 0 + 8 + + + FOSR + Sinc filter oversampling ratio + (decimation rate) + 16 + 10 + + + FORD + Sinc filter order + 29 + 3 + + + + + DFSDM0_JDATAR + DFSDM0_JDATAR + DFSDM data register for injected + group + 0x100 + 0x20 + read-only + 0x00000000 + + + JDATACH + Injected channel most recently + converted + 0 + 3 + + + JDATA + Injected group conversion + data + 8 + 24 + + + + + DFSDM1_JDATAR + DFSDM1_JDATAR + DFSDM data register for injected + group + 0x104 + 0x20 + read-only + 0x00000000 + + + JDATACH + Injected channel most recently + converted + 0 + 3 + + + JDATA + Injected group conversion + data + 8 + 24 + + + + + DFSDM2_JDATAR + DFSDM2_JDATAR + DFSDM data register for injected + group + 0x108 + 0x20 + read-only + 0x00000000 + + + JDATACH + Injected channel most recently + converted + 0 + 3 + + + JDATA + Injected group conversion + data + 8 + 24 + + + + + DFSDM3_JDATAR + DFSDM3_JDATAR + DFSDM data register for injected + group + 0x10C + 0x20 + read-only + 0x00000000 + + + JDATACH + Injected channel most recently + converted + 0 + 3 + + + JDATA + Injected group conversion + data + 8 + 24 + + + + + DFSDM0_RDATAR + DFSDM0_RDATAR + DFSDM data register for the regular + channel + 0x110 + 0x20 + read-only + 0x00000000 + + + RDATACH + Regular channel most recently + converted + 0 + 3 + + + RPEND + Regular channel pending + data + 4 + 1 + + + RDATA + Regular channel conversion + data + 8 + 24 + + + + + DFSDM1_RDATAR + DFSDM1_RDATAR + DFSDM data register for the regular + channel + 0x114 + 0x20 + read-only + 0x00000000 + + + RDATACH + Regular channel most recently + converted + 0 + 3 + + + RPEND + Regular channel pending + data + 4 + 1 + + + RDATA + Regular channel conversion + data + 8 + 24 + + + + + DFSDM2_RDATAR + DFSDM2_RDATAR + DFSDM data register for the regular + channel + 0x118 + 0x20 + read-only + 0x00000000 + + + RDATACH + Regular channel most recently + converted + 0 + 3 + + + RPEND + Regular channel pending + data + 4 + 1 + + + RDATA + Regular channel conversion + data + 8 + 24 + + + + + DFSDM3_RDATAR + DFSDM3_RDATAR + DFSDM data register for the regular + channel + 0x11C + 0x20 + read-only + 0x00000000 + + + RDATACH + Regular channel most recently + converted + 0 + 3 + + + RPEND + Regular channel pending + data + 4 + 1 + + + RDATA + Regular channel conversion + data + 8 + 24 + + + + + DFSDM0_AWHTR + DFSDM0_AWHTR + DFSDM analog watchdog high threshold + register + 0x120 + 0x20 + read-write + 0x00000000 + + + BKAWH + Break signal assignment to analog + watchdog high threshold event + 0 + 4 + + + AWHT + Analog watchdog high + threshold + 8 + 24 + + + + + DFSDM1_AWHTR + DFSDM1_AWHTR + DFSDM analog watchdog high threshold + register + 0x124 + 0x20 + read-write + 0x00000000 + + + BKAWH + Break signal assignment to analog + watchdog high threshold event + 0 + 4 + + + AWHT + Analog watchdog high + threshold + 8 + 24 + + + + + DFSDM2_AWHTR + DFSDM2_AWHTR + DFSDM analog watchdog high threshold + register + 0x128 + 0x20 + read-write + 0x00000000 + + + BKAWH + Break signal assignment to analog + watchdog high threshold event + 0 + 4 + + + AWHT + Analog watchdog high + threshold + 8 + 24 + + + + + DFSDM3_AWHTR + DFSDM3_AWHTR + DFSDM analog watchdog high threshold + register + 0x12C + 0x20 + read-write + 0x00000000 + + + BKAWH + Break signal assignment to analog + watchdog high threshold event + 0 + 4 + + + AWHT + Analog watchdog high + threshold + 8 + 24 + + + + + DFSDM0_AWLTR + DFSDM0_AWLTR + DFSDM analog watchdog low threshold + register + 0x130 + 0x20 + read-write + 0x00000000 + + + BKAWL + Break signal assignment to analog + watchdog low threshold event + 0 + 4 + + + AWLT + Analog watchdog low + threshold + 8 + 24 + + + + + DFSDM1_AWLTR + DFSDM1_AWLTR + DFSDM analog watchdog low threshold + register + 0x134 + 0x20 + read-write + 0x00000000 + + + BKAWL + Break signal assignment to analog + watchdog low threshold event + 0 + 4 + + + AWLT + Analog watchdog low + threshold + 8 + 24 + + + + + DFSDM2_AWLTR + DFSDM2_AWLTR + DFSDM analog watchdog low threshold + register + 0x138 + 0x20 + read-write + 0x00000000 + + + BKAWL + Break signal assignment to analog + watchdog low threshold event + 0 + 4 + + + AWLT + Analog watchdog low + threshold + 8 + 24 + + + + + DFSDM3_AWLTR + DFSDM3_AWLTR + DFSDM analog watchdog low threshold + register + 0x13C + 0x20 + read-write + 0x00000000 + + + BKAWL + Break signal assignment to analog + watchdog low threshold event + 0 + 4 + + + AWLT + Analog watchdog low + threshold + 8 + 24 + + + + + DFSDM0_AWSR + DFSDM0_AWSR + DFSDM analog watchdog status + register + 0x140 + 0x20 + read-only + 0x00000000 + + + AWLTF + Analog watchdog low threshold + flag + 0 + 8 + + + AWHTF + Analog watchdog high threshold + flag + 8 + 8 + + + + + DFSDM1_AWSR + DFSDM1_AWSR + DFSDM analog watchdog status + register + 0x144 + 0x20 + read-only + 0x00000000 + + + AWLTF + Analog watchdog low threshold + flag + 0 + 8 + + + AWHTF + Analog watchdog high threshold + flag + 8 + 8 + + + + + DFSDM2_AWSR + DFSDM2_AWSR + DFSDM analog watchdog status + register + 0x148 + 0x20 + read-only + 0x00000000 + + + AWLTF + Analog watchdog low threshold + flag + 0 + 8 + + + AWHTF + Analog watchdog high threshold + flag + 8 + 8 + + + + + DFSDM3_AWSR + DFSDM3_AWSR + DFSDM analog watchdog status + register + 0x14C + 0x20 + read-only + 0x00000000 + + + AWLTF + Analog watchdog low threshold + flag + 0 + 8 + + + AWHTF + Analog watchdog high threshold + flag + 8 + 8 + + + + + DFSDM0_AWCFR + DFSDM0_AWCFR + DFSDM analog watchdog clear flag + register + 0x150 + 0x20 + read-write + 0x00000000 + + + CLRAWLTF + Clear the analog watchdog low threshold + flag + 0 + 8 + + + CLRAWHTF + Clear the analog watchdog high threshold + flag + 8 + 8 + + + + + DFSDM1_AWCFR + DFSDM1_AWCFR + DFSDM analog watchdog clear flag + register + 0x154 + 0x20 + read-write + 0x00000000 + + + CLRAWLTF + Clear the analog watchdog low threshold + flag + 0 + 8 + + + CLRAWHTF + Clear the analog watchdog high threshold + flag + 8 + 8 + + + + + DFSDM2_AWCFR + DFSDM2_AWCFR + DFSDM analog watchdog clear flag + register + 0x158 + 0x20 + read-write + 0x00000000 + + + CLRAWLTF + Clear the analog watchdog low threshold + flag + 0 + 8 + + + CLRAWHTF + Clear the analog watchdog high threshold + flag + 8 + 8 + + + + + DFSDM3_AWCFR + DFSDM3_AWCFR + DFSDM analog watchdog clear flag + register + 0x15C + 0x20 + read-write + 0x00000000 + + + CLRAWLTF + Clear the analog watchdog low threshold + flag + 0 + 8 + + + CLRAWHTF + Clear the analog watchdog high threshold + flag + 8 + 8 + + + + + DFSDM0_EXMAX + DFSDM0_EXMAX + DFSDM Extremes detector maximum + register + 0x160 + 0x20 + read-only + 0x00000000 + + + EXMAXCH + Extremes detector maximum data + channel + 0 + 3 + + + EXMAX + Extremes detector maximum + value + 8 + 24 + + + + + DFSDM1_EXMAX + DFSDM1_EXMAX + DFSDM Extremes detector maximum + register + 0x164 + 0x20 + read-only + 0x00000000 + + + EXMAXCH + Extremes detector maximum data + channel + 0 + 3 + + + EXMAX + Extremes detector maximum + value + 8 + 24 + + + + + DFSDM2_EXMAX + DFSDM2_EXMAX + DFSDM Extremes detector maximum + register + 0x168 + 0x20 + read-only + 0x00000000 + + + EXMAXCH + Extremes detector maximum data + channel + 0 + 3 + + + EXMAX + Extremes detector maximum + value + 8 + 24 + + + + + DFSDM3_EXMAX + DFSDM3_EXMAX + DFSDM Extremes detector maximum + register + 0x16C + 0x20 + read-only + 0x00000000 + + + EXMAXCH + Extremes detector maximum data + channel + 0 + 3 + + + EXMAX + Extremes detector maximum + value + 8 + 24 + + + + + DFSDM0_EXMIN + DFSDM0_EXMIN + DFSDM Extremes detector minimum + register + 0x170 + 0x20 + read-only + 0x00000000 + + + EXMINCH + Extremes detector minimum data + channel + 0 + 3 + + + EXMIN + Extremes detector minimum + value + 8 + 24 + + + + + DFSDM1_EXMIN + DFSDM1_EXMIN + DFSDM Extremes detector minimum + register + 0x174 + 0x20 + read-only + 0x00000000 + + + EXMINCH + Extremes detector minimum data + channel + 0 + 3 + + + EXMIN + Extremes detector minimum + value + 8 + 24 + + + + + DFSDM2_EXMIN + DFSDM2_EXMIN + DFSDM Extremes detector minimum + register + 0x178 + 0x20 + read-only + 0x00000000 + + + EXMINCH + Extremes detector minimum data + channel + 0 + 3 + + + EXMIN + Extremes detector minimum + value + 8 + 24 + + + + + DFSDM3_EXMIN + DFSDM3_EXMIN + DFSDM Extremes detector minimum + register + 0x17C + 0x20 + read-only + 0x00000000 + + + EXMINCH + Extremes detector minimum data + channel + 0 + 3 + + + EXMIN + Extremes detector minimum + value + 8 + 24 + + + + + DFSDM0_CNVTIMR + DFSDM0_CNVTIMR + DFSDM conversion timer + register + 0x180 + 0x20 + read-only + 0x00000000 + + + CNVCNT + 28-bit timer counting conversion + time + 4 + 28 + + + + + DFSDM1_CNVTIMR + DFSDM1_CNVTIMR + DFSDM conversion timer + register + 0x184 + 0x20 + read-only + 0x00000000 + + + CNVCNT + 28-bit timer counting conversion + time + 4 + 28 + + + + + DFSDM2_CNVTIMR + DFSDM2_CNVTIMR + DFSDM conversion timer + register + 0x188 + 0x20 + read-only + 0x00000000 + + + CNVCNT + 28-bit timer counting conversion + time + 4 + 28 + + + + + DFSDM3_CNVTIMR + DFSDM3_CNVTIMR + DFSDM conversion timer + register + 0x18C + 0x20 + read-only + 0x00000000 + + + CNVCNT + 28-bit timer counting conversion + time + 4 + 28 + + + + + + + TIM16 + General-purpose-timers + TIMs + 0x40014400 + + 0x0 + 0x400 + registers + + + TIM16 + TIM16 global interrupt + 117 + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + CEN + Counter enable + 0 + 1 + + + UDIS + Update disable + 1 + 1 + + + URS + Update request source + 2 + 1 + + + OPM + One-pulse mode + 3 + 1 + + + ARPE + Auto-reload preload enable + 7 + 1 + + + CKD + Clock division + 8 + 2 + + + UIFREMAP + UIF status bit remapping + 11 + 1 + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + OIS1N + Output Idle state 1 + 9 + 1 + + + OIS1 + Output Idle state 1 + 8 + 1 + + + CCDS + Capture/compare DMA + selection + 3 + 1 + + + CCUS + Capture/compare control update + selection + 2 + 1 + + + CCPC + Capture/compare preloaded + control + 0 + 1 + + + + + DIER + DIER + DMA/Interrupt enable register + 0xC + 0x20 + read-write + 0x0000 + + + UIE + Update interrupt enable + 0 + 1 + + + CC1IE + Capture/Compare 1 interrupt + enable + 1 + 1 + + + COMIE + COM interrupt enable + 5 + 1 + + + BIE + Break interrupt enable + 7 + 1 + + + UDE + Update DMA request enable + 8 + 1 + + + CC1DE + Capture/Compare 1 DMA request + enable + 9 + 1 + + + COMDE + COM DMA request enable + 13 + 1 + + + + + SR + SR + status register + 0x10 + 0x20 + read-write + 0x0000 + + + CC1OF + Capture/Compare 1 overcapture + flag + 9 + 1 + + + BIF + Break interrupt flag + 7 + 1 + + + COMIF + COM interrupt flag + 5 + 1 + + + CC1IF + Capture/compare 1 interrupt + flag + 1 + 1 + + + UIF + Update interrupt flag + 0 + 1 + + + + + EGR + EGR + event generation register + 0x14 + 0x20 + write-only + 0x0000 + + + BG + Break generation + 7 + 1 + + + COMG + Capture/Compare control update + generation + 5 + 1 + + + CC1G + Capture/compare 1 + generation + 1 + 1 + + + UG + Update generation + 0 + 1 + + + + + CCMR1_Output + CCMR1_Output + capture/compare mode register (output + mode) + 0x18 + 0x20 + read-write + 0x00000000 + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + OC1FE + Output Compare 1 fast + enable + 2 + 1 + + + OC1PE + Output Compare 1 preload + enable + 3 + 1 + + + OC1M + Output Compare 1 mode + 4 + 3 + + + OC1M_3 + Output Compare 1 mode + 16 + 1 + + + + + CCMR1_Input + CCMR1_Input + capture/compare mode register 1 (input + mode) + CCMR1_Output + 0x18 + 0x20 + read-write + 0x00000000 + + + IC1F + Input capture 1 filter + 4 + 4 + + + IC1PSC + Input capture 1 prescaler + 2 + 2 + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + + + CCER + CCER + capture/compare enable + register + 0x20 + 0x20 + read-write + 0x0000 + + + CC1NP + Capture/Compare 1 output + Polarity + 3 + 1 + + + CC1NE + Capture/Compare 1 complementary output + enable + 2 + 1 + + + CC1P + Capture/Compare 1 output + Polarity + 1 + 1 + + + CC1E + Capture/Compare 1 output + enable + 0 + 1 + + + + + CNT + CNT + counter + 0x24 + 0x20 + 0x00000000 + + + CNT + counter value + 0 + 16 + read-write + + + UIFCPY + UIF Copy + 31 + 1 + read-only + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x0000 + + + PSC + Prescaler value + 0 + 16 + + + + + ARR + ARR + auto-reload register + 0x2C + 0x20 + read-write + 0x00000000 + + + ARR + Auto-reload value + 0 + 16 + + + + + RCR + RCR + repetition counter register + 0x30 + 0x20 + read-write + 0x0000 + + + REP + Repetition counter value + 0 + 8 + + + + + CCR1 + CCR1 + capture/compare register 1 + 0x34 + 0x20 + read-write + 0x00000000 + + + CCR1 + Capture/Compare 1 value + 0 + 16 + + + + + BDTR + BDTR + break and dead-time register + 0x44 + 0x20 + read-write + 0x0000 + + + DTG + Dead-time generator setup + 0 + 8 + + + LOCK + Lock configuration + 8 + 2 + + + OSSI + Off-state selection for Idle + mode + 10 + 1 + + + OSSR + Off-state selection for Run + mode + 11 + 1 + + + BKE + Break enable + 12 + 1 + + + BKP + Break polarity + 13 + 1 + + + AOE + Automatic output enable + 14 + 1 + + + MOE + Main output enable + 15 + 1 + + + BKF + Break filter + 16 + 4 + + + + + DCR + DCR + DMA control register + 0x48 + 0x20 + read-write + 0x0000 + + + DBL + DMA burst length + 8 + 5 + + + DBA + DMA base address + 0 + 5 + + + + + DMAR + DMAR + DMA address for full transfer + 0x4C + 0x20 + read-write + 0x0000 + + + DMAB + DMA register for burst + accesses + 0 + 16 + + + + + TIM16_AF1 + TIM16_AF1 + TIM16 alternate function register + 1 + 0x60 + 0x20 + read-write + 0x0000 + + + BKINE + BRK BKIN input enable + 0 + 1 + + + BKCMP1E + BRK COMP1 enable + 1 + 1 + + + BKCMP2E + BRK COMP2 enable + 2 + 1 + + + BKDFBK1E + BRK dfsdm1_break[1] enable + 8 + 1 + + + BKINP + BRK BKIN input polarity + 9 + 1 + + + BKCMP1P + BRK COMP1 input polarity + 10 + 1 + + + BKCMP2P + BRK COMP2 input polarity + 11 + 1 + + + + + TIM16_TISEL + TIM16_TISEL + TIM16 input selection register + 0x68 + 0x20 + read-write + 0x0000 + + + TI1SEL + selects TI1[0] to TI1[15] + input + 0 + 4 + + + + + + + TIM17 + General-purpose-timers + TIMs + 0x40014800 + + 0x0 + 0x400 + registers + + + TIM17 + TIM17 global interrupt + 118 + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + CEN + Counter enable + 0 + 1 + + + UDIS + Update disable + 1 + 1 + + + URS + Update request source + 2 + 1 + + + OPM + One-pulse mode + 3 + 1 + + + ARPE + Auto-reload preload enable + 7 + 1 + + + CKD + Clock division + 8 + 2 + + + UIFREMAP + UIF status bit remapping + 11 + 1 + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + OIS1N + Output Idle state 1 + 9 + 1 + + + OIS1 + Output Idle state 1 + 8 + 1 + + + CCDS + Capture/compare DMA + selection + 3 + 1 + + + CCUS + Capture/compare control update + selection + 2 + 1 + + + CCPC + Capture/compare preloaded + control + 0 + 1 + + + + + DIER + DIER + DMA/Interrupt enable register + 0xC + 0x20 + read-write + 0x0000 + + + UIE + Update interrupt enable + 0 + 1 + + + CC1IE + Capture/Compare 1 interrupt + enable + 1 + 1 + + + COMIE + COM interrupt enable + 5 + 1 + + + BIE + Break interrupt enable + 7 + 1 + + + UDE + Update DMA request enable + 8 + 1 + + + CC1DE + Capture/Compare 1 DMA request + enable + 9 + 1 + + + COMDE + COM DMA request enable + 13 + 1 + + + + + SR + SR + status register + 0x10 + 0x20 + read-write + 0x0000 + + + CC1OF + Capture/Compare 1 overcapture + flag + 9 + 1 + + + BIF + Break interrupt flag + 7 + 1 + + + COMIF + COM interrupt flag + 5 + 1 + + + CC1IF + Capture/compare 1 interrupt + flag + 1 + 1 + + + UIF + Update interrupt flag + 0 + 1 + + + + + EGR + EGR + event generation register + 0x14 + 0x20 + write-only + 0x0000 + + + BG + Break generation + 7 + 1 + + + COMG + Capture/Compare control update + generation + 5 + 1 + + + CC1G + Capture/compare 1 + generation + 1 + 1 + + + UG + Update generation + 0 + 1 + + + + + CCMR1_Output + CCMR1_Output + capture/compare mode register (output + mode) + 0x18 + 0x20 + read-write + 0x00000000 + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + OC1FE + Output Compare 1 fast + enable + 2 + 1 + + + OC1PE + Output Compare 1 preload + enable + 3 + 1 + + + OC1M + Output Compare 1 mode + 4 + 3 + + + OC1M_3 + Output Compare 1 mode + 16 + 1 + + + + + CCMR1_Input + CCMR1_Input + capture/compare mode register 1 (input + mode) + CCMR1_Output + 0x18 + 0x20 + read-write + 0x00000000 + + + IC1F + Input capture 1 filter + 4 + 4 + + + IC1PSC + Input capture 1 prescaler + 2 + 2 + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + + + CCER + CCER + capture/compare enable + register + 0x20 + 0x20 + read-write + 0x0000 + + + CC1NP + Capture/Compare 1 output + Polarity + 3 + 1 + + + CC1NE + Capture/Compare 1 complementary output + enable + 2 + 1 + + + CC1P + Capture/Compare 1 output + Polarity + 1 + 1 + + + CC1E + Capture/Compare 1 output + enable + 0 + 1 + + + + + CNT + CNT + counter + 0x24 + 0x20 + 0x00000000 + + + CNT + counter value + 0 + 16 + read-write + + + UIFCPY + UIF Copy + 31 + 1 + read-only + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x0000 + + + PSC + Prescaler value + 0 + 16 + + + + + ARR + ARR + auto-reload register + 0x2C + 0x20 + read-write + 0x00000000 + + + ARR + Auto-reload value + 0 + 16 + + + + + RCR + RCR + repetition counter register + 0x30 + 0x20 + read-write + 0x0000 + + + REP + Repetition counter value + 0 + 8 + + + + + CCR1 + CCR1 + capture/compare register 1 + 0x34 + 0x20 + read-write + 0x00000000 + + + CCR1 + Capture/Compare 1 value + 0 + 16 + + + + + BDTR + BDTR + break and dead-time register + 0x44 + 0x20 + read-write + 0x0000 + + + DTG + Dead-time generator setup + 0 + 8 + + + LOCK + Lock configuration + 8 + 2 + + + OSSI + Off-state selection for Idle + mode + 10 + 1 + + + OSSR + Off-state selection for Run + mode + 11 + 1 + + + BKE + Break enable + 12 + 1 + + + BKP + Break polarity + 13 + 1 + + + AOE + Automatic output enable + 14 + 1 + + + MOE + Main output enable + 15 + 1 + + + BKF + Break filter + 16 + 4 + + + + + DCR + DCR + DMA control register + 0x48 + 0x20 + read-write + 0x0000 + + + DBL + DMA burst length + 8 + 5 + + + DBA + DMA base address + 0 + 5 + + + + + DMAR + DMAR + DMA address for full transfer + 0x4C + 0x20 + read-write + 0x0000 + + + DMAB + DMA register for burst + accesses + 0 + 16 + + + + + TIM17_AF1 + TIM17_AF1 + TIM17 alternate function register + 1 + 0x60 + 0x20 + read-write + 0x0000 + + + BKINE + BRK BKIN input enable + 0 + 1 + + + BKCMP1E + BRK COMP1 enable + 1 + 1 + + + BKCMP2E + BRK COMP2 enable + 2 + 1 + + + BKDFBK1E + BRK dfsdm1_break[1] enable + 8 + 1 + + + BKINP + BRK BKIN input polarity + 9 + 1 + + + BKCMP1P + BRK COMP1 input polarity + 10 + 1 + + + BKCMP2P + BRK COMP2 input polarity + 11 + 1 + + + + + TIM17_TISEL + TIM17_TISEL + TIM17 input selection register + 0x68 + 0x20 + read-write + 0x0000 + + + TI1SEL + selects TI1[0] to TI1[15] + input + 0 + 4 + + + + + + + TIM15 + General purpose timers + TIMs + 0x40014000 + + 0x0 + 0x400 + registers + + + TIM15 + TIM15 global interrupt + 116 + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + CEN + Counter enable + 0 + 1 + + + UDIS + Update disable + 1 + 1 + + + URS + Update request source + 2 + 1 + + + OPM + One-pulse mode + 3 + 1 + + + ARPE + Auto-reload preload enable + 7 + 1 + + + CKD + Clock division + 8 + 2 + + + UIFREMAP + UIF status bit remapping + 11 + 1 + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + CCPC + Capture/compare preloaded + control + 0 + 1 + + + CCUS + Capture/compare control update + selection + 2 + 1 + + + CCDS + Capture/compare DMA + selection + 3 + 1 + + + MMS + Master mode selection + 4 + 3 + + + TI1S + TI1 selection + 7 + 1 + + + OIS1 + Output Idle state 1 + 8 + 1 + + + OIS1N + Output Idle state 1 + 9 + 1 + + + OIS2 + Output Idle state 2 + 10 + 1 + + + + + SMCR + SMCR + slave mode control register + 0x8 + 0x20 + read-write + 0x0000 + + + SMS + Slave mode selection + 0 + 3 + + + TS_2_0 + Trigger selection + 4 + 3 + + + MSM + Master/Slave mode + 7 + 1 + + + SMS_3 + Slave mode selection bit 3 + 16 + 1 + + + TS_4_3 + Trigger selection - bit + 4:3 + 20 + 2 + + + + + DIER + DIER + DMA/Interrupt enable register + 0xC + 0x20 + read-write + 0x0000 + + + UIE + Update interrupt enable + 0 + 1 + + + CC1IE + Capture/Compare 1 interrupt + enable + 1 + 1 + + + CC2IE + Capture/Compare 2 interrupt + enable + 2 + 1 + + + COMIE + COM interrupt enable + 5 + 1 + + + TIE + Trigger interrupt enable + 6 + 1 + + + BIE + Break interrupt enable + 7 + 1 + + + UDE + Update DMA request enable + 8 + 1 + + + CC1DE + Capture/Compare 1 DMA request + enable + 9 + 1 + + + CC2DE + Capture/Compare 2 DMA request + enable + 10 + 1 + + + COMDE + COM DMA request enable + 13 + 1 + + + TDE + Trigger DMA request enable + 14 + 1 + + + + + SR + SR + status register + 0x10 + 0x20 + read-write + 0x0000 + + + CC2OF + Capture/compare 2 overcapture + flag + 10 + 1 + + + CC1OF + Capture/Compare 1 overcapture + flag + 9 + 1 + + + BIF + Break interrupt flag + 7 + 1 + + + TIF + Trigger interrupt flag + 6 + 1 + + + COMIF + COM interrupt flag + 5 + 1 + + + CC2IF + Capture/Compare 2 interrupt + flag + 2 + 1 + + + CC1IF + Capture/compare 1 interrupt + flag + 1 + 1 + + + UIF + Update interrupt flag + 0 + 1 + + + + + EGR + EGR + event generation register + 0x14 + 0x20 + write-only + 0x0000 + + + BG + Break generation + 7 + 1 + + + TG + Trigger generation + 6 + 1 + + + COMG + Capture/Compare control update + generation + 5 + 1 + + + CC2G + Capture/compare 2 + generation + 2 + 1 + + + CC1G + Capture/compare 1 + generation + 1 + 1 + + + UG + Update generation + 0 + 1 + + + + + CCMR1_Output + CCMR1_Output + capture/compare mode register (output + mode) + 0x18 + 0x20 + read-write + 0x00000000 + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + OC1FE + Output Compare 1 fast + enable + 2 + 1 + + + OC1PE + Output Compare 1 preload + enable + 3 + 1 + + + OC1M + Output Compare 1 mode + 4 + 3 + + + CC2S + Capture/Compare 2 + selection + 8 + 2 + + + OC2FE + Output Compare 2 fast + enable + 10 + 1 + + + OC2PE + Output Compare 2 preload + enable + 11 + 1 + + + OC2M + Output Compare 2 mode + 12 + 3 + + + OC1M_3 + Output Compare 1 mode bit + 3 + 16 + 1 + + + OC2M_3 + Output Compare 2 mode bit + 3 + 24 + 1 + + + + + CCMR1_Input + CCMR1_Input + capture/compare mode register 1 (input + mode) + CCMR1_Output + 0x18 + 0x20 + read-write + 0x00000000 + + + IC2F + Input capture 2 filter + 12 + 4 + + + IC2PSC + Input capture 2 prescaler + 10 + 2 + + + CC2S + Capture/Compare 2 + selection + 8 + 2 + + + IC1F + Input capture 1 filter + 4 + 4 + + + IC1PSC + Input capture 1 prescaler + 2 + 2 + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + + + CCER + CCER + capture/compare enable + register + 0x20 + 0x20 + read-write + 0x0000 + + + CC2NP + Capture/Compare 2 output + Polarity + 7 + 1 + + + CC2P + Capture/Compare 2 output + Polarity + 5 + 1 + + + CC2E + Capture/Compare 2 output + enable + 4 + 1 + + + CC1NP + Capture/Compare 1 output + Polarity + 3 + 1 + + + CC1NE + Capture/Compare 1 complementary output + enable + 2 + 1 + + + CC1P + Capture/Compare 1 output + Polarity + 1 + 1 + + + CC1E + Capture/Compare 1 output + enable + 0 + 1 + + + + + CNT + CNT + counter + 0x24 + 0x20 + 0x00000000 + + + CNT + counter value + 0 + 16 + read-write + + + UIFCPY + UIF copy + 31 + 1 + read-only + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x0000 + + + PSC + Prescaler value + 0 + 16 + + + + + ARR + ARR + auto-reload register + 0x2C + 0x20 + read-write + 0x00000000 + + + ARR + Auto-reload value + 0 + 16 + + + + + RCR + RCR + repetition counter register + 0x30 + 0x20 + read-write + 0x0000 + + + REP + Repetition counter value + 0 + 8 + + + + + CCR1 + CCR1 + capture/compare register 1 + 0x34 + 0x20 + read-write + 0x00000000 + + + CCR1 + Capture/Compare 1 value + 0 + 16 + + + + + CCR2 + CCR2 + capture/compare register 2 + 0x38 + 0x20 + read-write + 0x00000000 + + + CCR2 + Capture/Compare 2 value + 0 + 16 + + + + + BDTR + BDTR + break and dead-time register + 0x44 + 0x20 + read-write + 0x0000 + + + MOE + Main output enable + 15 + 1 + + + AOE + Automatic output enable + 14 + 1 + + + BKP + Break polarity + 13 + 1 + + + BKE + Break enable + 12 + 1 + + + OSSR + Off-state selection for Run + mode + 11 + 1 + + + OSSI + Off-state selection for Idle + mode + 10 + 1 + + + LOCK + Lock configuration + 8 + 2 + + + DTG + Dead-time generator setup + 0 + 8 + + + BKF + Break filter + 16 + 4 + + + + + DCR + DCR + DMA control register + 0x48 + 0x20 + read-write + 0x0000 + + + DBL + DMA burst length + 8 + 5 + + + DBA + DMA base address + 0 + 5 + + + + + DMAR + DMAR + DMA address for full transfer + 0x4C + 0x20 + read-write + 0x0000 + + + DMAB + DMA register for burst + accesses + 0 + 16 + + + + + AF1 + AF1 + TIM15 alternate fdfsdm1_breakon register + 1 + 0x60 + 0x20 + read-write + 0x0000 + + + BKINE + BRK BKIN input enable + 0 + 1 + + + BKCMP1E + BRK COMP1 enable + 1 + 1 + + + BKCMP2E + BRK COMP2 enable + 2 + 1 + + + BKDF1BK0E + BRK dfsdm1_break[0] enable + 8 + 1 + + + BKINP + BRK BKIN input polarity + 9 + 1 + + + BKCMP1P + BRK COMP1 input polarity + 10 + 1 + + + BKCMP2P + BRK COMP2 input polarity + 11 + 1 + + + + + TISEL + TISEL + TIM15 input selection register + 0x68 + 0x20 + read-write + 0x0000 + + + TI1SEL + selects TI1[0] to TI1[15] + input + 0 + 4 + + + TI2SEL + selects TI2[0] to TI2[15] + input + 8 + 4 + + + + + + + USART1 + Universal synchronous asynchronous receiver + transmitter + USART + 0x40011000 + + 0x0 + 0x400 + registers + + + + CR1 + CR1 + Control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + RXFFIE + RXFIFO Full interrupt + enable + 31 + 1 + + + TXFEIE + TXFIFO empty interrupt + enable + 30 + 1 + + + FIFOEN + FIFO mode enable + 29 + 1 + + + M1 + Word length + 28 + 1 + + + EOBIE + End of Block interrupt + enable + 27 + 1 + + + RTOIE + Receiver timeout interrupt + enable + 26 + 1 + + + DEAT4 + Driver Enable assertion + time + 25 + 1 + + + DEAT3 + DEAT3 + 24 + 1 + + + DEAT2 + DEAT2 + 23 + 1 + + + DEAT1 + DEAT1 + 22 + 1 + + + DEAT0 + DEAT0 + 21 + 1 + + + DEDT4 + Driver Enable de-assertion + time + 20 + 1 + + + DEDT3 + DEDT3 + 19 + 1 + + + DEDT2 + DEDT2 + 18 + 1 + + + DEDT1 + DEDT1 + 17 + 1 + + + DEDT0 + DEDT0 + 16 + 1 + + + OVER8 + Oversampling mode + 15 + 1 + + + CMIE + Character match interrupt + enable + 14 + 1 + + + MME + Mute mode enable + 13 + 1 + + + M0 + Word length + 12 + 1 + + + WAKE + Receiver wakeup method + 11 + 1 + + + PCE + Parity control enable + 10 + 1 + + + PS + Parity selection + 9 + 1 + + + PEIE + PE interrupt enable + 8 + 1 + + + TXEIE + interrupt enable + 7 + 1 + + + TCIE + Transmission complete interrupt + enable + 6 + 1 + + + RXNEIE + RXNE interrupt enable + 5 + 1 + + + IDLEIE + IDLE interrupt enable + 4 + 1 + + + TE + Transmitter enable + 3 + 1 + + + RE + Receiver enable + 2 + 1 + + + UESM + USART enable in Stop mode + 1 + 1 + + + UE + USART enable + 0 + 1 + + + + + CR2 + CR2 + Control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + ADD4_7 + Address of the USART node + 28 + 4 + + + ADD0_3 + Address of the USART node + 24 + 4 + + + RTOEN + Receiver timeout enable + 23 + 1 + + + ABRMOD1 + Auto baud rate mode + 22 + 1 + + + ABRMOD0 + ABRMOD0 + 21 + 1 + + + ABREN + Auto baud rate enable + 20 + 1 + + + MSBFIRST + Most significant bit first + 19 + 1 + + + TAINV + Binary data inversion + 18 + 1 + + + TXINV + TX pin active level + inversion + 17 + 1 + + + RXINV + RX pin active level + inversion + 16 + 1 + + + SWAP + Swap TX/RX pins + 15 + 1 + + + LINEN + LIN mode enable + 14 + 1 + + + STOP + STOP bits + 12 + 2 + + + CLKEN + Clock enable + 11 + 1 + + + CPOL + Clock polarity + 10 + 1 + + + CPHA + Clock phase + 9 + 1 + + + LBCL + Last bit clock pulse + 8 + 1 + + + LBDIE + LIN break detection interrupt + enable + 6 + 1 + + + LBDL + LIN break detection length + 5 + 1 + + + ADDM7 + 7-bit Address Detection/4-bit Address + Detection + 4 + 1 + + + DIS_NSS + When the DSI_NSS bit is set, the NSS pin + input is ignored + 3 + 1 + + + SLVEN + Synchronous Slave mode + enable + 0 + 1 + + + + + CR3 + CR3 + Control register 3 + 0x8 + 0x20 + read-write + 0x0000 + + + TXFTCFG + TXFIFO threshold + configuration + 29 + 3 + + + RXFTIE + RXFIFO threshold interrupt + enable + 28 + 1 + + + RXFTCFG + Receive FIFO threshold + configuration + 25 + 3 + + + TCBGTIE + Transmission Complete before guard time, + interrupt enable + 24 + 1 + + + TXFTIE + TXFIFO threshold interrupt + enable + 23 + 1 + + + WUFIE + Wakeup from Stop mode interrupt + enable + 22 + 1 + + + WUS + Wakeup from Stop mode interrupt flag + selection + 20 + 2 + + + SCARCNT + Smartcard auto-retry count + 17 + 3 + + + DEP + Driver enable polarity + selection + 15 + 1 + + + DEM + Driver enable mode + 14 + 1 + + + DDRE + DMA Disable on Reception + Error + 13 + 1 + + + OVRDIS + Overrun Disable + 12 + 1 + + + ONEBIT + One sample bit method + enable + 11 + 1 + + + CTSIE + CTS interrupt enable + 10 + 1 + + + CTSE + CTS enable + 9 + 1 + + + RTSE + RTS enable + 8 + 1 + + + DMAT + DMA enable transmitter + 7 + 1 + + + DMAR + DMA enable receiver + 6 + 1 + + + SCEN + Smartcard mode enable + 5 + 1 + + + NACK + Smartcard NACK enable + 4 + 1 + + + HDSEL + Half-duplex selection + 3 + 1 + + + IRLP + Ir low-power + 2 + 1 + + + IREN + Ir mode enable + 1 + 1 + + + EIE + Error interrupt enable + 0 + 1 + + + + + BRR + BRR + Baud rate register + 0xC + 0x20 + read-write + 0x0000 + + + BRR_4_15 + DIV_Mantissa + 4 + 12 + + + BRR_0_3 + DIV_Fraction + 0 + 4 + + + + + GTPR + GTPR + Guard time and prescaler + register + 0x10 + 0x20 + read-write + 0x0000 + + + GT + Guard time value + 8 + 8 + + + PSC + Prescaler value + 0 + 8 + + + + + RTOR + RTOR + Receiver timeout register + 0x14 + 0x20 + read-write + 0x0000 + + + BLEN + Block Length + 24 + 8 + + + RTO + Receiver timeout value + 0 + 24 + + + + + RQR + RQR + Request register + 0x18 + 0x20 + write-only + 0x0000 + + + TXFRQ + Transmit data flush + request + 4 + 1 + + + RXFRQ + Receive data flush request + 3 + 1 + + + MMRQ + Mute mode request + 2 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+ + TDR + TDR + Transmit data register + 0x28 + 0x20 + read-write + 0x0000 + + + TDR + Transmit data value + 0 + 9 + + + + + PRESC + PRESC + USART prescaler register + 0x2C + 0x20 + read-write + 0x0000 + + + PRESCALER + Clock prescaler + 0 + 4 + + + + + + + USART2 + 0x40004400 + + USART1 + USART1 global interrupt + 37 + + + + USART3 + 0x40004800 + + USART2 + USART2 global interrupt + 38 + + + + UART4 + 0x40004C00 + + USART3 + USART3 global interrupt + 39 + + + UART4 + UART4 global interrupt + 52 + + + + UART5 + 0x40005000 + + UART5 + UART5 global interrupt + 53 + + + + USART6 + 0x40011400 + + USART6 + USART6 global interrupt + 71 + + + + UART7 + 0x40007800 + + UART7 + UART7 global interrupt + 82 + + + + UART8 + 0x40007C00 + + UART8 + UART8 global interrupt + 83 + + + + TIM1 + Advanced-timers + TIM + 0x40010000 + + 0x0 + 0x400 + registers + + + TIM1_BRK + TIM1 break interrupt + 24 + + + TIM1_UP + TIM1 update interrupt + 25 + + + TIM1_TRG_COM + TIM1 trigger and commutation + 26 + + + TIM_CC + TIM1 capture / compare + 27 + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + CEN + Counter enable + 0 + 1 + + + UDIS + Update disable + 1 + 1 + + + URS + Update request source + 2 + 1 + + + OPM + One-pulse mode + 3 + 1 + + + DIR + Direction + 4 + 1 + + + CMS + Center-aligned mode + selection + 5 + 2 + + + ARPE + Auto-reload preload enable + 7 + 1 + + + CKD + Clock division + 8 + 2 + + + UIFREMAP + UIF status bit remapping + 11 + 1 + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + MMS2 + Master mode selection 2 + 20 + 4 + + + OIS6 + Output Idle state 6 + 18 + 1 + + + OIS5 + Output Idle state 5 + 16 + 1 + + + OIS4 + Output Idle state 4 + 14 + 1 + + + OIS3N + Output Idle state 3 + 13 + 1 + + + OIS3 + Output Idle state 3 + 12 + 1 + + + OIS2N + Output Idle state 2 + 11 + 1 + + + OIS2 + Output Idle state 2 + 10 + 1 + + + OIS1N + Output Idle state 1 + 9 + 1 + + + OIS1 + Output Idle state 1 + 8 + 1 + + + TI1S + TI1 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Capture/Compare 3 DMA request + enable + 11 + 1 + + + CC2DE + Capture/Compare 2 DMA request + enable + 10 + 1 + + + CC1DE + Capture/Compare 1 DMA request + enable + 9 + 1 + + + UDE + Update DMA request enable + 8 + 1 + + + TIE + Trigger interrupt enable + 6 + 1 + + + CC4IE + Capture/Compare 4 interrupt + enable + 4 + 1 + + + CC3IE + Capture/Compare 3 interrupt + enable + 3 + 1 + + + CC2IE + Capture/Compare 2 interrupt + enable + 2 + 1 + + + CC1IE + Capture/Compare 1 interrupt + enable + 1 + 1 + + + UIE + Update interrupt enable + 0 + 1 + + + BIE + Break interrupt enable + 7 + 1 + + + COMIE + COM interrupt enable + 5 + 1 + + + + + SR + SR + status register + 0x10 + 0x20 + read-write + 0x0000 + + + CC6IF + Compare 6 interrupt flag + 17 + 1 + + + CC5IF + Compare 5 interrupt flag + 16 + 1 + + + SBIF + System Break interrupt + flag + 13 + 1 + + + CC4OF + Capture/Compare 4 overcapture + flag + 12 + 1 + + + CC3OF + Capture/Compare 3 overcapture + flag + 11 + 1 + + + CC2OF + Capture/compare 2 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capture 2 prescaler + 10 + 2 + + + CC2S + Capture/Compare 2 + selection + 8 + 2 + + + IC1F + Input capture 1 filter + 4 + 4 + + + ICPCS + Input capture 1 prescaler + 2 + 2 + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + + + CCMR2_Output + CCMR2_Output + capture/compare mode register 2 (output + mode) + 0x1C + 0x20 + read-write + 0x00000000 + + + CC3S + Capture/Compare 3 + selection + 0 + 2 + + + OC3FE + Output compare 3 fast + enable + 2 + 1 + + + OC3PE + Output compare 3 preload + enable + 3 + 1 + + + OC3M + Output compare 3 mode + 4 + 3 + + + OC3CE + Output compare 3 clear + enable + 7 + 1 + + + CC4S + Capture/Compare 4 + selection + 8 + 2 + + + OC4FE + Output compare 4 fast + enable + 10 + 1 + + + OC4PE + Output compare 4 preload + enable + 11 + 1 + + + OC4M + Output compare 4 mode + 12 + 3 + + + OC4CE + Output compare 4 clear + enable + 15 + 1 + + + OC3M_3 + Output Compare 3 mode - bit + 3 + 16 + 1 + + + OC4M_4 + Output Compare 4 mode - bit + 3 + 24 + 1 + + + + + CCMR2_Input + CCMR2_Input + capture/compare mode register 2 (input + mode) + CCMR2_Output + 0x1C + 0x20 + read-write + 0x00000000 + + + IC4F + Input capture 4 filter + 12 + 4 + + + IC4PSC + Input capture 4 prescaler + 10 + 2 + + + CC4S + Capture/Compare 4 + selection + 8 + 2 + + + IC3F + Input capture 3 filter + 4 + 4 + + + IC3PSC + Input capture 3 prescaler + 2 + 2 + + + CC3S + Capture/compare 3 + selection + 0 + 2 + + + + + CCER + CCER + capture/compare enable + register + 0x20 + 0x20 + read-write + 0x0000 + + + CC1E + Capture/Compare 1 output + enable + 0 + 1 + + + CC1P + Capture/Compare 1 output + Polarity + 1 + 1 + + + CC1NE + Capture/Compare 1 complementary output + enable + 2 + 1 + + + CC1NP + Capture/Compare 1 output + Polarity + 3 + 1 + + + CC2E + Capture/Compare 2 output + enable + 4 + 1 + + + CC2P + Capture/Compare 2 output + Polarity + 5 + 1 + + + CC2NE + Capture/Compare 2 complementary output + enable + 6 + 1 + + + CC2NP + Capture/Compare 2 output + Polarity + 7 + 1 + + + CC3E + Capture/Compare 3 output + enable + 8 + 1 + + + CC3P + Capture/Compare 3 output + Polarity + 9 + 1 + + + CC3NE + Capture/Compare 3 complementary output + enable + 10 + 1 + + + CC3NP + Capture/Compare 3 output + Polarity + 11 + 1 + + + CC4E + Capture/Compare 4 output + enable + 12 + 1 + + + CC4P + Capture/Compare 3 output + Polarity + 13 + 1 + + + CC4NP + Capture/Compare 4 complementary output + polarity + 15 + 1 + + + CC5E + Capture/Compare 5 output + enable + 16 + 1 + + + CC5P + Capture/Compare 5 output + polarity + 17 + 1 + + + CC6E + Capture/Compare 6 output + enable + 20 + 1 + + + CC6P + Capture/Compare 6 output + polarity + 21 + 1 + + + + + CNT + CNT + counter + 0x24 + 0x20 + 0x00000000 + + + CNT + counter value + 0 + 16 + read-write + + + UIFCPY + UIF copy + 31 + 1 + read-only + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x0000 + + + PSC + Prescaler value + 0 + 16 + + + + + ARR + ARR + auto-reload register + 0x2C + 0x20 + read-write + 0x00000000 + + + ARR + Auto-reload value + 0 + 16 + + + + + CCR1 + CCR1 + capture/compare register 1 + 0x34 + 0x20 + read-write + 0x00000000 + + + CCR1 + Capture/Compare 1 value + 0 + 16 + + + + + CCR2 + CCR2 + capture/compare register 2 + 0x38 + 0x20 + read-write + 0x00000000 + + + CCR2 + Capture/Compare 2 value + 0 + 16 + + + + + CCR3 + CCR3 + capture/compare register 3 + 0x3C + 0x20 + read-write + 0x00000000 + + + CCR3 + Capture/Compare value + 0 + 16 + + + + + CCR4 + CCR4 + capture/compare register 4 + 0x40 + 0x20 + read-write + 0x00000000 + + + CCR4 + Capture/Compare value + 0 + 16 + + + + + DCR + DCR + DMA control register + 0x48 + 0x20 + read-write + 0x0000 + + + DBL + DMA burst length + 8 + 5 + + + DBA + DMA base address + 0 + 5 + + + + + DMAR + DMAR + DMA address for full transfer + 0x4C + 0x20 + read-write + 0x0000 + + + DMAB + DMA register for burst + accesses + 0 + 16 + + + + + RCR + RCR + repetition counter register + 0x30 + 0x20 + read-write + 0x0000 + + + REP + Repetition counter value + 0 + 8 + + + + + BDTR + BDTR + break and dead-time register + 0x44 + 0x20 + read-write + 0x0000 + + + DTG + Dead-time generator setup + 0 + 8 + + + LOCK + Lock configuration + 8 + 2 + + + OSSI + Off-state selection for Idle + mode + 10 + 1 + + + OSSR + Off-state selection for Run + mode + 11 + 1 + + + BKE + Break enable + 12 + 1 + + + BKP + Break polarity + 13 + 1 + + + AOE + Automatic output enable + 14 + 1 + + + MOE + Main output enable + 15 + 1 + + + BKF + Break filter + 16 + 4 + + + BK2F + Break 2 filter + 20 + 4 + + + BK2E + Break 2 enable + 24 + 1 + + + BK2P + Break 2 polarity + 25 + 1 + + + + + CCMR3_Output + CCMR3_Output + capture/compare mode register 3 (output + mode) + 0x54 + 0x20 + read-write + 0x0000 + + + OC5FE + Output compare 5 fast + enable + 2 + 1 + + + OC5PE + Output compare 5 preload + enable + 3 + 1 + + + OC5M + Output compare 5 mode + 4 + 3 + + + OC5CE + Output compare 5 clear + enable + 7 + 1 + + + OC6FE + Output compare 6 fast + enable + 10 + 1 + + + OC6PE + Output compare 6 preload + enable + 11 + 1 + + + OC6M + Output compare 6 mode + 12 + 3 + + + OC6CE + Output compare 6 clear + enable + 15 + 1 + + + OC5M3 + Output Compare 5 mode + 16 + 1 + + + OC6M3 + Output Compare 6 mode + 24 + 1 + + + + + CCR5 + CCR5 + capture/compare register 5 + 0x58 + 0x20 + read-write + 0x0000 + + + CCR5 + Capture/Compare 5 value + 0 + 16 + + + GC5C1 + Group Channel 5 and Channel + 1 + 29 + 1 + + + GC5C2 + Group Channel 5 and Channel + 2 + 30 + 1 + + + GC5C3 + Group Channel 5 and Channel + 3 + 31 + 1 + + + + + CRR6 + CRR6 + capture/compare register 6 + 0x5C + 0x20 + read-write + 0x0000 + + + CCR6 + Capture/Compare 6 value + 0 + 16 + + + + + AF1 + AF1 + TIM1 alternate function option register + 1 + 0x60 + 0x20 + read-write + 0x0000 + + + BKINE + BRK BKIN input enable + 0 + 1 + + + BKCMP1E + BRK COMP1 enable + 1 + 1 + + + BKCMP2E + BRK COMP2 enable + 2 + 1 + + + BKDF1BK0E + BRK dfsdm1_break[0] enable + 8 + 1 + + + BKINP + BRK BKIN input polarity + 9 + 1 + + + BKCMP1P + BRK COMP1 input polarity + 10 + 1 + + + BKCMP2P + BRK COMP2 input polarity + 11 + 1 + + + ETRSEL + ETR source selection + 14 + 4 + + + + + AF2 + AF2 + TIM1 Alternate function odfsdm1_breakster + 2 + 0x64 + 0x20 + read-write + 0x0000 + + + BK2INE + BRK2 BKIN input enable + 0 + 1 + + + BK2CMP1E + BRK2 COMP1 enable + 1 + 1 + + + BK2CMP2E + BRK2 COMP2 enable + 2 + 1 + + + BK2DF1BK1E + BRK2 dfsdm1_break[1] + enable + 8 + 1 + + + BK2INP + BRK2 BKIN2 input polarity + 9 + 1 + + + BK2CMP1P + BRK2 COMP1 input polarit + 10 + 1 + + + BK2CMP2P + BRK2 COMP2 input polarity + 11 + 1 + + + + + TISEL + TISEL + TIM1 timer input selection + register + 0x68 + 0x20 + read-write + 0x0000 + + + TI1SEL + selects TI1[0] to TI1[15] + input + 0 + 4 + + + TI2SEL + selects TI2[0] to TI2[15] + input + 8 + 4 + + + TI3SEL + selects TI3[0] to TI3[15] + input + 16 + 4 + + + TI4SEL + selects TI4[0] to TI4[15] + input + 24 + 4 + + + + + + + TIM8 + 0x40010400 + + TIM8_CC + TIM8 capture / compare + 46 + + + + FDCAN1 + FDCAN1 + FDCAN + 0x4000A000 + + 0x0 + 0x400 + registers + + + FDCAN1_IT0 + FDCAN1 Interrupt 0 + 19 + + + FDCAN1_IT1 + FDCAN1 Interrupt 1 + 21 + + + FDCAN_CAL + CAN2TX interrupts + 63 + + + + FDCAN_CREL + FDCAN_CREL + FDCAN Core Release Register + 0x0 + 0x20 + read-only + 0x00000000 + + + REL + Core release + 28 + 4 + + + STEP + Step of Core release + 24 + 4 + + + SUBSTEP + Sub-step of Core release + 20 + 4 + + + YEAR + Timestamp Year + 16 + 4 + + + MON + Timestamp Month + 8 + 8 + + + DAY + Timestamp Day + 0 + 8 + + + + + FDCAN_ENDN + FDCAN_ENDN + FDCAN Core Release Register + 0x4 + 0x20 + read-only + 0x00000000 + + + ETV + Endiannes Test Value + 0 + 32 + + + + + FDCAN_DBTP + FDCAN_DBTP + FDCAN Data Bit Timing and Prescaler + Register + 0xC + 0x20 + read-only + 0x00000000 + + + DSJW + Synchronization Jump Width + 0 + 4 + + + DTSEG2 + Data time segment after sample + point + 4 + 4 + + + DTSEG1 + Data time segment after sample + point + 8 + 5 + + + DBRP + Data BIt Rate Prescaler + 16 + 5 + + + TDC + Transceiver Delay + Compensation + 23 + 1 + + + + + FDCAN_TEST + FDCAN_TEST + FDCAN Test Register + 0x10 + 0x20 + read-only + 0x00000000 + + + LBCK + Loop Back mode + 4 + 1 + + + TX + Loop Back mode + 5 + 2 + + + RX + Control of Transmit Pin + 7 + 1 + + + + + FDCAN_RWD + FDCAN_RWD + FDCAN RAM Watchdog Register + 0x14 + 0x20 + read-only + 0x00000000 + + + WDV + Watchdog value + 8 + 8 + + + WDC + Watchdog configuration + 0 + 8 + + + + + FDCAN_CCCR + FDCAN_CCCR + FDCAN CC Control Register + 0x18 + 0x20 + read-write + 0x00000000 + + + INIT + Initialization + 0 + 1 + + + CCE + Configuration Change + Enable + 1 + 1 + + + ASM + ASM Restricted Operation + Mode + 2 + 1 + + + CSA + Clock Stop Acknowledge + 3 + 1 + + + CSR + Clock Stop Request + 4 + 1 + + + MON + Bus Monitoring Mode + 5 + 1 + + + DAR + Disable Automatic + Retransmission + 6 + 1 + + + TEST + Test Mode Enable + 7 + 1 + + + FDOE + FD Operation Enable + 8 + 1 + + + BSE + FDCAN Bit Rate Switching + 9 + 1 + + + PXHD + Protocol Exception Handling + Disable + 12 + 1 + + + EFBI + Edge Filtering during Bus + Integration + 13 + 1 + + + TXP + TXP + 14 + 1 + + + NISO + Non ISO Operation + 15 + 1 + + + + + FDCAN_NBTP + FDCAN_NBTP + FDCAN Nominal Bit Timing and Prescaler + Register + 0x1C + 0x20 + read-write + 0x00000000 + + + NSJW + NSJW: Nominal (Re)Synchronization Jump + Width + 25 + 7 + + + NBRP + Bit Rate Prescaler + 16 + 9 + + + NTSEG1 + Nominal Time segment before sample + point + 8 + 8 + + + TSEG2 + Nominal Time segment after sample + point + 0 + 7 + + + + + FDCAN_TSCC + FDCAN_TSCC + FDCAN Timestamp Counter Configuration + Register + 0x20 + 0x20 + read-write + 0x00000000 + + + TCP + Timestamp Counter + Prescaler + 16 + 4 + + + TSS + Timestamp Select + 0 + 2 + + + + + FDCAN_TSCV + FDCAN_TSCV + FDCAN Timestamp Counter Value + Register + 0x24 + 0x20 + read-write + 0x00000000 + + + TSC + Timestamp Counter + 0 + 16 + + + + + FDCAN_TOCC + FDCAN_TOCC + FDCAN Timeout Counter Configuration + Register + 0x28 + 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Core Release + Register + 0x0 + 0x20 + read-write + 0x00000000 + + + DAY + Time Stamp Day + 0 + 8 + + + MON + Time Stamp Month + 8 + 8 + + + YEAR + Time Stamp Year + 16 + 4 + + + SUBSTEP + Sub-step of Core Release + 20 + 4 + + + STEP + Step of Core Release + 24 + 4 + + + REL + Core Release + 28 + 4 + + + + + CCFG + CCFG + Calibration Configuration + Register + 0x4 + 0x20 + read-write + 0x00000000 + + + TQBT + Time Quanta per Bit Time + 0 + 5 + + + BCC + Bypass Clock Calibration + 6 + 1 + + + CFL + Calibration Field Length + 7 + 1 + + + OCPM + Oscillator Clock Periods + Minimum + 8 + 8 + + + CDIV + Clock Divider + 16 + 4 + + + SWR + Software Reset + 31 + 1 + + + + + CSTAT + CSTAT + Calibration Status Register + 0x8 + 0x20 + read-write + 0x00000000 + + + OCPC + Oscillator Clock Period + Counter + 0 + 18 + + + TQC + Time Quanta Counter + 18 + 11 + + + CALS + Calibration State + 30 + 2 + + + + + CWD + CWD + Calibration Watchdog Register + 0xC + 0x20 + read-write + 0x00000000 + + + WDC + WDC + 0 + 16 + + + WDV + WDV + 16 + 16 + + + + + IR + IR + Clock Calibration Unit Interrupt + Register + 0x10 + 0x20 + read-write + 0x00000000 + + + CWE + Calibration Watchdog Event + 0 + 1 + + + CSC + Calibration State Changed + 1 + 1 + + + + + IE + IE + Clock Calibration Unit Interrupt Enable + Register + 0x14 + 0x20 + read-write + 0x00000000 + + + CWEE + Calibration Watchdog Event + Enable + 0 + 1 + + + CSCE + Calibration State Changed + Enable + 1 + 1 + + + + + + + MDIOS + Management data input/output slave + MDIOS + 0x40009400 + + 0x0 + 0x400 + registers + + + MDIOS_WKUP + MDIOS wakeup + 119 + + + MDIOS + MDIOS global interrupt + 120 + + + + CR + CR + MDIOS configuration register + 0x0 + 0x20 + read-write + 0x00000000 + + + EN + Peripheral enable + 0 + 1 + + + WRIE + Register write interrupt + enable + 1 + 1 + + + RDIE + Register Read Interrupt + Enable + 2 + 1 + + + EIE + Error interrupt enable + 3 + 1 + + + DPC + Disable Preamble Check + 7 + 1 + + + PORT_ADDRESS + Slaves's address + 8 + 5 + + + + + WRFR + WRFR + MDIOS write flag register + 0x4 + 0x20 + read-only + 0x00000000 + + + WRF + Write flags for MDIO registers 0 to + 31 + 0 + 32 + + + + + CWRFR + CWRFR + MDIOS clear write flag + register + 0x8 + 0x20 + read-write + 0x00000000 + + + CWRF + Clear the write flag + 0 + 32 + + + + + RDFR + RDFR + MDIOS read flag register + 0xC + 0x20 + read-only + 0x00000000 + + + RDF + Read flags for MDIO registers 0 to + 31 + 0 + 32 + + + + + CRDFR + CRDFR + MDIOS clear read flag register + 0x10 + 0x20 + read-write + 0x00000000 + + + CRDF + Clear the read flag + 0 + 32 + + + + + SR + SR + MDIOS status register + 0x14 + 0x20 + read-only + 0x00000000 + + + PERF + Preamble error flag + 0 + 1 + + + SERF + Start error flag + 1 + 1 + + + TERF + Turnaround error flag + 2 + 1 + + + + + CLRFR + CLRFR + MDIOS clear flag register + 0x18 + 0x20 + read-write + 0x00000000 + + + CPERF + Clear the preamble error + flag + 0 + 1 + + + CSERF + Clear the start error flag + 1 + 1 + + + CTERF + Clear the turnaround error + flag + 2 + 1 + + + + + DINR0 + DINR0 + MDIOS input data register 0 + 0x1C + 0x20 + read-only + 0x00000000 + + + DIN0 + Input data received from MDIO Master + during write frames + 0 + 16 + + + + + DINR1 + DINR1 + MDIOS input data register 1 + 0x20 + 0x20 + read-only + 0x00000000 + + + DIN1 + Input data received from MDIO Master + during write frames + 0 + 16 + + + + + DINR2 + DINR2 + MDIOS input data register 2 + 0x24 + 0x20 + read-only + 0x00000000 + + + DIN2 + Input data received from MDIO Master + during write frames + 0 + 16 + + + + + DINR3 + DINR3 + MDIOS input data register 3 + 0x28 + 0x20 + read-only + 0x00000000 + + + DIN3 + Input data received from MDIO Master + during write frames + 0 + 16 + + + + + DINR4 + DINR4 + MDIOS input data register 4 + 0x2C + 0x20 + read-only + 0x00000000 + + + DIN4 + Input data received from MDIO Master + during write frames + 0 + 16 + + + + + DINR5 + DINR5 + MDIOS input data register 5 + 0x30 + 0x20 + read-only + 0x00000000 + + + DIN5 + Input data received from MDIO Master + during write frames + 0 + 16 + + + + + DINR6 + DINR6 + MDIOS input data register 6 + 0x34 + 0x20 + read-only + 0x00000000 + + + DIN6 + Input data received from MDIO Master + during write frames + 0 + 16 + + + + + DINR7 + DINR7 + MDIOS input data register 7 + 0x38 + 0x20 + read-only + 0x00000000 + + + DIN7 + Input data received from MDIO Master + during write frames + 0 + 16 + + + + + DINR8 + DINR8 + MDIOS input data register 8 + 0x3C + 0x20 + read-only + 0x00000000 + + + DIN8 + Input data received from MDIO Master + during write frames + 0 + 16 + + + + + DINR9 + DINR9 + MDIOS input data register 9 + 0x40 + 0x20 + read-only + 0x00000000 + + + DIN9 + Input data received from MDIO Master + during write frames + 0 + 16 + + + + + DINR10 + DINR10 + MDIOS input data register 10 + 0x44 + 0x20 + read-only + 0x00000000 + + + DIN10 + Input data received from MDIO Master + during write frames + 0 + 16 + + + + + DINR11 + DINR11 + MDIOS input data register 11 + 0x48 + 0x20 + read-only + 0x00000000 + + + DIN11 + Input data received from MDIO Master + during write frames + 0 + 16 + + + + + DINR12 + DINR12 + MDIOS input data register 12 + 0x4C + 0x20 + read-only + 0x00000000 + + + DIN12 + Input data received from MDIO Master + during write frames + 0 + 16 + + + + + DINR13 + DINR13 + MDIOS input data register 13 + 0x50 + 0x20 + read-only + 0x00000000 + + + DIN13 + Input data received from MDIO Master + during write frames + 0 + 16 + + + + + DINR14 + DINR14 + MDIOS input data register 14 + 0x54 + 0x20 + read-only + 0x00000000 + + + DIN14 + Input data received from MDIO Master + during write frames + 0 + 16 + + + + + DINR15 + DINR15 + MDIOS input data register 15 + 0x58 + 0x20 + read-only + 0x00000000 + + + DIN15 + Input data received from MDIO Master + during write frames + 0 + 16 + + + + + DINR16 + DINR16 + MDIOS input data register 16 + 0x5C + 0x20 + read-only + 0x00000000 + + + DIN16 + Input data received from MDIO Master + during write frames + 0 + 16 + + + + + DINR17 + DINR17 + MDIOS input data register 17 + 0x60 + 0x20 + read-only + 0x00000000 + + + DIN17 + Input data received from MDIO Master + during write frames + 0 + 16 + + + + + DINR18 + DINR18 + MDIOS input data register 18 + 0x64 + 0x20 + read-only + 0x00000000 + + + DIN18 + Input data received from MDIO Master + during write frames + 0 + 16 + + + + + DINR19 + DINR19 + MDIOS input data register 19 + 0x68 + 0x20 + read-only + 0x00000000 + + + DIN19 + Input data received from MDIO Master + during write frames + 0 + 16 + + + + + DINR20 + DINR20 + MDIOS input data register 20 + 0x6C + 0x20 + read-only + 0x00000000 + + + DIN20 + Input data received from MDIO Master + during write frames + 0 + 16 + + + + + DINR21 + DINR21 + MDIOS input data register 21 + 0x70 + 0x20 + read-only + 0x00000000 + + + DIN21 + Input data received from MDIO Master + during write frames + 0 + 16 + + + + + DINR22 + DINR22 + MDIOS input data register 22 + 0x74 + 0x20 + read-only + 0x00000000 + + + DIN22 + Input data received from MDIO Master + during write frames + 0 + 16 + + + + + DINR23 + DINR23 + MDIOS input data register 23 + 0x78 + 0x20 + read-only + 0x00000000 + + + DIN23 + Input data received from MDIO Master + during write frames + 0 + 16 + + + + + DINR24 + DINR24 + MDIOS input data register 24 + 0x7C + 0x20 + read-only + 0x00000000 + + + DIN24 + Input data received from MDIO Master + during write frames + 0 + 16 + + + + + DINR25 + DINR25 + MDIOS input data register 25 + 0x80 + 0x20 + read-only + 0x00000000 + + + DIN25 + Input data received from MDIO Master + during write frames + 0 + 16 + + + + + DINR26 + DINR26 + MDIOS input data register 26 + 0x84 + 0x20 + read-only + 0x00000000 + + + DIN26 + Input data received from MDIO Master + during write frames + 0 + 16 + + + + + DINR27 + DINR27 + MDIOS input data register 27 + 0x88 + 0x20 + read-only + 0x00000000 + + + DIN27 + Input data received from MDIO Master + during write frames + 0 + 16 + + + + + DINR28 + DINR28 + MDIOS input data register 28 + 0x8C + 0x20 + read-only + 0x00000000 + + + DIN28 + Input data received from MDIO Master + during write frames + 0 + 16 + + + + + DINR29 + DINR29 + MDIOS input data register 29 + 0x90 + 0x20 + read-only + 0x00000000 + + + DIN29 + Input data received from MDIO Master + during write frames + 0 + 16 + + + + + DINR30 + DINR30 + MDIOS input data register 30 + 0x94 + 0x20 + read-only + 0x00000000 + + + DIN30 + Input data received from MDIO Master + during write frames + 0 + 16 + + + + + DINR31 + DINR31 + MDIOS input data register 31 + 0x98 + 0x20 + read-only + 0x00000000 + + + DIN31 + Input data received from MDIO Master + during write frames + 0 + 16 + + + + + DOUTR0 + DOUTR0 + MDIOS output data register 0 + 0x9C + 0x20 + read-write + 0x00000000 + + + DOUT0 + Output data sent to MDIO Master during + read frames + 0 + 16 + + + + + DOUTR1 + DOUTR1 + MDIOS output data register 1 + 0xA0 + 0x20 + read-write + 0x00000000 + + + DOUT1 + Output data sent to MDIO Master during + read frames + 0 + 16 + + + + + DOUTR2 + DOUTR2 + MDIOS output data register 2 + 0xA4 + 0x20 + read-write + 0x00000000 + + + DOUT2 + Output data sent to MDIO Master during + read frames + 0 + 16 + + + + + DOUTR3 + DOUTR3 + MDIOS output data register 3 + 0xA8 + 0x20 + read-write + 0x00000000 + + + DOUT3 + Output data sent to MDIO Master during + read frames + 0 + 16 + + + + + DOUTR4 + DOUTR4 + MDIOS output data register 4 + 0xAC + 0x20 + read-write + 0x00000000 + + + DOUT4 + Output data sent to MDIO Master during + read frames + 0 + 16 + + + + + DOUTR5 + DOUTR5 + MDIOS output data register 5 + 0xB0 + 0x20 + read-write + 0x00000000 + + + DOUT5 + Output data sent to MDIO Master during + read frames + 0 + 16 + + + + + DOUTR6 + DOUTR6 + MDIOS output data register 6 + 0xB4 + 0x20 + read-write + 0x00000000 + + + DOUT6 + Output data sent to MDIO Master during + read frames + 0 + 16 + + + + + DOUTR7 + DOUTR7 + MDIOS output data register 7 + 0xB8 + 0x20 + read-write + 0x00000000 + + + DOUT7 + Output data sent to MDIO Master during + read frames + 0 + 16 + + + + + DOUTR8 + DOUTR8 + MDIOS output data register 8 + 0xBC + 0x20 + read-write + 0x00000000 + + + DOUT8 + Output data sent to MDIO Master during + read frames + 0 + 16 + + + + + DOUTR9 + DOUTR9 + MDIOS output data register 9 + 0xC0 + 0x20 + read-write + 0x00000000 + + + DOUT9 + Output data sent to MDIO Master during + read frames + 0 + 16 + + + + + DOUTR10 + DOUTR10 + MDIOS output data register 10 + 0xC4 + 0x20 + read-write + 0x00000000 + + + DOUT10 + Output data sent to MDIO Master during + read frames + 0 + 16 + + + + + DOUTR11 + DOUTR11 + MDIOS output data register 11 + 0xC8 + 0x20 + read-write + 0x00000000 + + + DOUT11 + Output data sent to MDIO Master during + read frames + 0 + 16 + + + + + DOUTR12 + DOUTR12 + MDIOS output data register 12 + 0xCC + 0x20 + read-write + 0x00000000 + + + DOUT12 + Output data sent to MDIO Master during + read frames + 0 + 16 + + + + + DOUTR13 + DOUTR13 + MDIOS output data register 13 + 0xD0 + 0x20 + read-write + 0x00000000 + + + DOUT13 + Output data sent to MDIO Master during + read frames + 0 + 16 + + + + + DOUTR14 + DOUTR14 + MDIOS output data register 14 + 0xD4 + 0x20 + read-write + 0x00000000 + + + DOUT14 + Output data sent to MDIO Master during + read frames + 0 + 16 + + + + + DOUTR15 + DOUTR15 + MDIOS output data register 15 + 0xD8 + 0x20 + read-write + 0x00000000 + + + DOUT15 + Output data sent to MDIO Master during + read frames + 0 + 16 + + + + + DOUTR16 + DOUTR16 + MDIOS output data register 16 + 0xDC + 0x20 + read-write + 0x00000000 + + + DOUT16 + Output data sent to MDIO Master during + read frames + 0 + 16 + + + + + DOUTR17 + DOUTR17 + MDIOS output data register 17 + 0xE0 + 0x20 + read-write + 0x00000000 + + + DOUT17 + Output data sent to MDIO Master during + read frames + 0 + 16 + + + + + DOUTR18 + DOUTR18 + MDIOS output data register 18 + 0xE4 + 0x20 + read-write + 0x00000000 + + + DOUT18 + Output data sent to MDIO Master during + read frames + 0 + 16 + + + + + DOUTR19 + DOUTR19 + MDIOS output data register 19 + 0xE8 + 0x20 + read-write + 0x00000000 + + + DOUT19 + Output data sent to MDIO Master during + read frames + 0 + 16 + + + + + DOUTR20 + DOUTR20 + MDIOS output data register 20 + 0xEC + 0x20 + read-write + 0x00000000 + + + DOUT20 + Output data sent to MDIO Master during + read frames + 0 + 16 + + + + + DOUTR21 + DOUTR21 + MDIOS output data register 21 + 0xF0 + 0x20 + read-write + 0x00000000 + + + DOUT21 + Output data sent to MDIO Master during + read frames + 0 + 16 + + + + + DOUTR22 + DOUTR22 + MDIOS output data register 22 + 0xF4 + 0x20 + read-write + 0x00000000 + + + DOUT22 + Output data sent to MDIO Master during + read frames + 0 + 16 + + + + + DOUTR23 + DOUTR23 + MDIOS output data register 23 + 0xF8 + 0x20 + read-write + 0x00000000 + + + DOUT23 + Output data sent to MDIO Master during + read frames + 0 + 16 + + + + + DOUTR24 + DOUTR24 + MDIOS output data register 24 + 0xFC + 0x20 + read-write + 0x00000000 + + + DOUT24 + Output data sent to MDIO Master during + read frames + 0 + 16 + + + + + DOUTR25 + DOUTR25 + MDIOS output data register 25 + 0x100 + 0x20 + read-write + 0x00000000 + + + DOUT25 + Output data sent to MDIO Master during + read frames + 0 + 16 + + + + + DOUTR26 + DOUTR26 + MDIOS output data register 26 + 0x104 + 0x20 + read-write + 0x00000000 + + + DOUT26 + Output data sent to MDIO Master during + read frames + 0 + 16 + + + + + DOUTR27 + DOUTR27 + MDIOS output data register 27 + 0x108 + 0x20 + read-write + 0x00000000 + + + DOUT27 + Output data sent to MDIO Master during + read frames + 0 + 16 + + + + + DOUTR28 + DOUTR28 + MDIOS output data register 28 + 0x10C + 0x20 + read-write + 0x00000000 + + + DOUT28 + Output data sent to MDIO Master during + read frames + 0 + 16 + + + + + DOUTR29 + DOUTR29 + MDIOS output data register 29 + 0x110 + 0x20 + read-write + 0x00000000 + + + DOUT29 + Output data sent to MDIO Master during + read frames + 0 + 16 + + + + + DOUTR30 + DOUTR30 + MDIOS output data register 30 + 0x114 + 0x20 + read-write + 0x00000000 + + + DOUT30 + Output data sent to MDIO Master during + read frames + 0 + 16 + + + + + DOUTR31 + DOUTR31 + MDIOS output data register 31 + 0x118 + 0x20 + read-write + 0x00000000 + + + DOUT31 + Output data sent to MDIO Master during + read frames + 0 + 16 + + + + + + + OPAMP + Operational amplifiers + OPAMP + 0x40009000 + + 0x0 + 0x400 + registers + + + + OPAMP1_CSR + OPAMP1_CSR + OPAMP1 control/status register + 0x0 + 0x20 + read-write + 0x00000000 + + + OPAEN + Operational amplifier + Enable + 0 + 1 + + + FORCE_VP + Force internal reference on VP (reserved + for test + 1 + 1 + + + VP_SEL + Operational amplifier PGA + mode + 2 + 2 + + + VM_SEL + Inverting input selection + 5 + 2 + + + OPAHSM + Operational amplifier high-speed + mode + 8 + 1 + + + CALON + Calibration mode enabled + 11 + 1 + + + CALSEL + Calibration selection + 12 + 2 + + + PGA_GAIN + allows to switch from AOP offset trimmed + values to AOP offset + 14 + 4 + + + USERTRIM + User trimming enable + 18 + 1 + + + TSTREF + OPAMP calibration reference voltage + output control (reserved for test) + 29 + 1 + + + CALOUT + Operational amplifier calibration + output + 30 + 1 + + + + + OPAMP1_OTR + OPAMP1_OTR + OPAMP1 offset trimming register in normal + mode + 0x4 + 0x20 + read-write + 0x00000000 + + + TRIMOFFSETN + Trim for NMOS differential + pairs + 0 + 5 + + + TRIMOFFSETP + Trim for PMOS differential + pairs + 8 + 5 + + + + + OPAMP1_HSOTR + OPAMP1_HSOTR + OPAMP1 offset trimming register in low-power + mode + 0x8 + 0x20 + read-write + 0x00000000 + + + TRIMLPOFFSETN + Trim for NMOS differential + pairs + 0 + 5 + + + TRIMLPOFFSETP + Trim for PMOS differential + pairs + 8 + 5 + + + + + OPAMP2_CSR + OPAMP2_CSR + OPAMP2 control/status register + 0x10 + 0x20 + read-write + 0x00000000 + + + OPAEN + Operational amplifier + Enable + 0 + 1 + + + FORCE_VP + Force internal reference on VP (reserved + for test) + 1 + 1 + + + VM_SEL + Inverting input selection + 5 + 2 + + + OPAHSM + Operational amplifier high-speed + mode + 8 + 1 + + + CALON + Calibration mode enabled + 11 + 1 + + + CALSEL + Calibration selection + 12 + 2 + + + PGA_GAIN + Operational amplifier Programmable + amplifier gain value + 14 + 4 + + + USERTRIM + User trimming enable + 18 + 1 + + + TSTREF + OPAMP calibration reference voltage + output control (reserved for test) + 29 + 1 + + + CALOUT + Operational amplifier calibration + output + 30 + 1 + + + + + OPAMP2_OTR + OPAMP2_OTR + OPAMP2 offset trimming register in normal + mode + 0x14 + 0x20 + read-write + 0x00000000 + + + TRIMOFFSETN + Trim for NMOS differential + pairs + 0 + 5 + + + TRIMOFFSETP + Trim for PMOS differential + pairs + 8 + 5 + + + + + OPAMP2_HSOTR + OPAMP2_HSOTR + OPAMP2 offset trimming register in low-power + mode + 0x18 + 0x20 + read-write + 0x00000000 + + + TRIMLPOFFSETN + Trim for NMOS differential + pairs + 0 + 5 + + + TRIMLPOFFSETP + Trim for PMOS differential + pairs + 8 + 5 + + + + + + + SWPMI + Single Wire Protocol Master + Interface + SWPMI + 0x40008800 + + 0x0 + 0x400 + registers + + + + CR + CR + SWPMI Configuration/Control + register + 0x0 + 0x20 + read-write + 0x00000000 + + + RXDMA + Reception DMA enable + 0 + 1 + + + TXDMA + Transmission DMA enable + 1 + 1 + + + RXMODE + Reception buffering mode + 2 + 1 + + + TXMODE + Transmission buffering + mode + 3 + 1 + + + LPBK + Loopback mode enable + 4 + 1 + + + SWPACT + Single wire protocol master interface + activate + 5 + 1 + + + DEACT + Single wire protocol master interface + deactivate + 10 + 1 + + + SWPTEN + Single wire protocol master transceiver + enable + 11 + 1 + + + + + BRR + BRR + SWPMI Bitrate register + 0x4 + 0x20 + read-write + 0x00000001 + + + BR + Bitrate prescaler + 0 + 8 + + + + + ISR + ISR + SWPMI Interrupt and Status + register + 0xC + 0x20 + read-only + 0x000002C2 + + + RXBFF + Receive buffer full flag + 0 + 1 + + + TXBEF + Transmit buffer empty flag + 1 + 1 + + + RXBERF + Receive CRC error flag + 2 + 1 + + + RXOVRF + Receive overrun error flag + 3 + 1 + + + TXUNRF + Transmit underrun error + flag + 4 + 1 + + + RXNE + Receive data register not + empty + 5 + 1 + + + TXE + Transmit data register + empty + 6 + 1 + + + TCF + Transfer complete flag + 7 + 1 + + + SRF + Slave resume flag + 8 + 1 + + + SUSP + SUSPEND flag + 9 + 1 + + + DEACTF + DEACTIVATED flag + 10 + 1 + + + RDYF + transceiver ready flag + 11 + 1 + + + + + ICR + ICR + SWPMI Interrupt Flag Clear + register + 0x10 + 0x20 + write-only + 0x00000000 + + + CRXBFF + Clear receive buffer full + flag + 0 + 1 + + + CTXBEF + Clear transmit buffer empty + flag + 1 + 1 + + + CRXBERF + Clear receive CRC error + flag + 2 + 1 + + + CRXOVRF + Clear receive overrun error + flag + 3 + 1 + + + CTXUNRF + Clear transmit underrun error + flag + 4 + 1 + + + CTCF + Clear transfer complete + flag + 7 + 1 + + + CSRF + Clear slave resume flag + 8 + 1 + + + CRDYF + Clear transceiver ready + flag + 11 + 1 + + + + + IER + IER + SWPMI Interrupt Enable + register + 0x14 + 0x20 + read-write + 0x00000000 + + + RXBFIE + Receive buffer full interrupt + enable + 0 + 1 + + + TXBEIE + Transmit buffer empty interrupt + enable + 1 + 1 + + + RXBERIE + Receive CRC error interrupt + enable + 2 + 1 + + + RXOVRIE + Receive overrun error interrupt + enable + 3 + 1 + + + TXUNRIE + Transmit underrun error interrupt + enable + 4 + 1 + + + RIE + Receive interrupt enable + 5 + 1 + + + TIE + Transmit interrupt enable + 6 + 1 + + + TCIE + Transmit complete interrupt + enable + 7 + 1 + + + SRIE + Slave resume interrupt + enable + 8 + 1 + + + RDYIE + Transceiver ready interrupt + enable + 11 + 1 + + + + + RFL + RFL + SWPMI Receive Frame Length + register + 0x18 + 0x20 + read-only + 0x00000000 + + + RFL + Receive frame length + 0 + 5 + + + + + TDR + TDR + SWPMI Transmit data register + 0x1C + 0x20 + write-only + 0x00000000 + + + TD + Transmit data + 0 + 32 + + + + + RDR + RDR + SWPMI Receive data register + 0x20 + 0x20 + read-only + 0x00000000 + + + RD + received data + 0 + 32 + + + + + OR + OR + SWPMI Option register + 0x24 + 0x20 + read-write + 0x00000000 + + + SWP_TBYP + SWP transceiver bypass + 0 + 1 + + + SWP_CLASS + SWP class selection + 1 + 1 + + + + + + + TIM2 + General purpose timers + TIM + 0x40000000 + + 0x0 + 0x400 + registers + + + TIM2 + TIM2 global interrupt + 28 + + + SWPMI1 + SWPMI global interrupt + 115 + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + UIFREMAP + UIF status bit remapping + 11 + 1 + + + CKD + Clock division + 8 + 2 + + + ARPE + Auto-reload preload enable + 7 + 1 + + + CMS + Center-aligned mode + selection + 5 + 2 + + + DIR + Direction + 4 + 1 + + + OPM + One-pulse mode + 3 + 1 + + + URS + Update request source + 2 + 1 + + + UDIS + Update disable + 1 + 1 + + + CEN + Counter enable + 0 + 1 + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + TI1S + TI1 selection + 7 + 1 + + + MMS + Master mode selection + 4 + 3 + + + CCDS + Capture/compare DMA + selection + 3 + 1 + + + + + SMCR + SMCR + slave mode control register + 0x8 + 0x20 + read-write + 0x0000 + + + TS_4_3 + Trigger selection + 20 + 2 + + + SMS_3 + Slave mode selection - bit + 3 + 16 + 1 + + + ETP + External trigger polarity + 15 + 1 + + + ECE + External clock enable + 14 + 1 + + + ETPS + External trigger prescaler + 12 + 2 + + + ETF + External trigger filter + 8 + 4 + + + MSM + Master/Slave mode + 7 + 1 + + + TS + Trigger selection + 4 + 3 + + + SMS + Slave mode selection + 0 + 3 + + + + + DIER + DIER + DMA/Interrupt enable register + 0xC + 0x20 + read-write + 0x0000 + + + TDE + Trigger DMA request enable + 14 + 1 + + + CC4DE + Capture/Compare 4 DMA request + enable + 12 + 1 + + + CC3DE + Capture/Compare 3 DMA request + enable + 11 + 1 + + + CC2DE + Capture/Compare 2 DMA request + enable + 10 + 1 + + + CC1DE + Capture/Compare 1 DMA request + enable + 9 + 1 + + + UDE + Update DMA request enable + 8 + 1 + + + TIE + Trigger interrupt enable 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IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR1 + IPR1 + Interrupt Priority Register + 0x304 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR2 + IPR2 + Interrupt Priority Register + 0x308 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR3 + IPR3 + Interrupt Priority Register + 0x30C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR4 + IPR4 + Interrupt Priority Register + 0x310 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR5 + IPR5 + Interrupt Priority Register + 0x314 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR6 + IPR6 + Interrupt Priority Register + 0x318 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR7 + IPR7 + Interrupt Priority Register + 0x31C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR8 + IPR8 + Interrupt Priority Register + 0x320 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR9 + IPR9 + Interrupt Priority Register + 0x324 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR10 + IPR10 + Interrupt Priority Register + 0x328 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR11 + IPR11 + Interrupt Priority Register + 0x32C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR12 + IPR12 + Interrupt Priority Register + 0x330 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR13 + IPR13 + Interrupt Priority Register + 0x334 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR14 + IPR14 + Interrupt Priority Register + 0x338 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR15 + IPR15 + Interrupt Priority Register + 0x33C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR16 + IPR16 + Interrupt Priority Register + 0x340 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR17 + IPR17 + Interrupt Priority Register + 0x344 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR18 + IPR18 + Interrupt Priority Register + 0x348 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR19 + IPR19 + Interrupt Priority Register + 0x34C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR20 + IPR20 + Interrupt Priority Register + 0x350 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR21 + IPR21 + Interrupt Priority Register + 0x354 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR22 + IPR22 + Interrupt Priority Register + 0x358 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR23 + IPR23 + Interrupt Priority Register + 0x35C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR24 + IPR24 + Interrupt Priority Register + 0x360 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR25 + IPR25 + Interrupt Priority Register + 0x364 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR26 + IPR26 + Interrupt Priority Register + 0x368 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR27 + IPR27 + Interrupt Priority Register + 0x36C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR28 + IPR28 + Interrupt Priority Register + 0x370 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR29 + IPR29 + Interrupt Priority Register + 0x374 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR30 + IPR30 + Interrupt Priority Register + 0x378 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR31 + IPR31 + Interrupt Priority Register + 0x37C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR32 + IPR32 + Interrupt Priority Register + 0x380 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR33 + IPR33 + Interrupt Priority Register + 0x384 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR34 + IPR34 + Interrupt Priority Register + 0x388 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR35 + IPR35 + Interrupt Priority Register + 0x38C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR36 + IPR36 + Interrupt Priority Register + 0x390 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR37 + IPR37 + Interrupt Priority Register + 0x394 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR38 + IPR38 + Interrupt Priority Register + 0x398 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR39 + IPR39 + Interrupt Priority Register + 0x39C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + ISER3 + ISER3 + Interrupt Set-Enable Register + 0xC + 0x20 + read-write + 0x00000000 + + + ISER4 + ISER4 + Interrupt Set-Enable Register + 0x10 + 0x20 + read-write + 0x00000000 + + + ICER3 + ICER3 + Interrupt Clear-Enable + Register + 0x8C + 0x20 + read-write + 0x00000000 + + + ICER4 + ICER4 + Interrupt Clear-Enable + Register + 0x90 + 0x20 + read-write + 0x00000000 + + + ISPR3 + ISPR3 + Interrupt Set-Pending Register + 0x10C + 0x20 + read-write + 0x00000000 + + + ISPR4 + ISPR4 + Interrupt Set-Pending Register + 0x110 + 0x20 + read-write + 0x00000000 + + + ICPR3 + ICPR3 + Interrupt Clear-Pending + Register + 0x1C0 + 0x20 + read-write + 0x00000000 + + + ICPR4 + ICPR4 + Interrupt Clear-Pending + Register + 0x1C4 + 0x20 + read-write + 0x00000000 + + + IABR3 + IABR3 + Interrupt Active Bit Register + 0x20C + 0x20 + read-write + 0x00000000 + + + IABR4 + IABR4 + Interrupt Active Bit Register + 0x210 + 0x20 + read-write + 0x00000000 + + + + + DBGMCU + Microcontroller Debug Unit + DBGMCU + 0x5C001000 + + 0x0 + 0x400 + registers + + + + IDC + IDC + DBGMCU Identity Code Register + 0x0 + 0x20 + read-only + 0x10006450 + + + DEV_ID + Device ID + 0 + 12 + + + REV_ID + Revision + 16 + 16 + + + + + CR + CR + DBGMCU Configuration Register + 0x4 + 0x20 + read-write + 0x00000000 + + + DBGSLEEP_D1 + Allow D1 domain debug in Sleep mode + 0 + 1 + + + DBGSTOP_D1 + Allow D1 domain debug in Stop mode + 1 + 1 + + + DBGSTBY_D1 + Allow D1 domain debug in Standby mode + 2 + 1 + + + DBGSLEEP_D2 + Allow D2 domain debug in Sleep mode + 3 + 1 + + + DBGSTOP_D2 + Allow D2 domain debug in Stop mode + 4 + 1 + + + DBGSTBY_D2 + Allow D2 domain debug in Standby mode + 5 + 1 + + + DBGSTOP_D3 + Allow debug in D3 Stop mode + 7 + 1 + + + DBGSTBY_D3 + Allow debug in D3 Standby mode + 8 + 1 + + + TRACECLKEN + Trace port clock enable + 20 + 1 + + + D1DBGCKEN + D1 debug clock enable + 21 + 1 + + + D3DBGCKEN + D3 debug clock enable + 22 + 1 + + + TRGOEN + External trigger output enable + 28 + 1 + + + + + APB3FZ1 + APB3FZ1 + DBGMCU APB3 peripheral freeze register + 0x34 + 0x20 + read-write + 0x00000000 + + + WWDG1 + WWDG1 stop in debug + 6 + 1 + + + + + APB1LFZ1 + APB1LFZ1 + DBGMCU APB1L peripheral freeze register + 0x3C + 0x20 + read-write + 0x00000000 + + + DBG_TIM2 + TIM2 stop in debug + 0 + 1 + + + DBG_TIM3 + TIM3 stop in debug + 1 + 1 + + + DBG_TIM4 + TIM4 stop in debug + 2 + 1 + + + DBG_TIM5 + TIM5 stop in debug + 3 + 1 + + + DBG_TIM6 + TIM6 stop in debug + 4 + 1 + + + DBG_TIM7 + TIM7 stop in debug + 5 + 1 + + + DBG_TIM12 + TIM12 stop in debug + 6 + 1 + + + DBG_TIM13 + TIM13 stop in debug + 7 + 1 + + + DBG_TIM14 + TIM14 stop in debug + 8 + 1 + + + DBG_LPTIM1 + LPTIM1 stop in debug + 9 + 1 + + + DBG_I2C1 + I2C1 SMBUS timeout stop in debug + 21 + 1 + + + DBG_I2C2 + I2C2 SMBUS timeout stop in debug + 22 + 1 + + + DBG_I2C3 + I2C3 SMBUS timeout stop in debug + 23 + 1 + + + + + APB2FZ1 + APB2FZ1 + DBGMCU APB2 peripheral freeze register + 0x4C + 0x20 + read-write + 0x00000000 + + + DBG_TIM1 + TIM1 stop in debug + 0 + 1 + + + DBG_TIM8 + TIM8 stop in debug + 1 + 1 + + + DBG_TIM15 + TIM15 stop in debug + 16 + 1 + + + DBG_TIM16 + TIM16 stop in debug + 17 + 1 + + + DBG_TIM17 + TIM17 stop in debug + 18 + 1 + + + DBG_HRTIM + HRTIM stop in debug + 29 + 1 + + + + + APB4FZ1 + APB4FZ1 + DBGMCU APB4 peripheral freeze register + 0x54 + 0x20 + read-write + 0x00000000 + + + DBG_I2C4 + I2C4 SMBUS timeout stop in debug + 7 + 1 + + + DBG_LPTIM2 + LPTIM2 stop in debug + 9 + 1 + + + DBG_LPTIM3 + LPTIM2 stop in debug + 10 + 1 + + + DBG_LPTIM4 + LPTIM4 stop in debug + 11 + 1 + + + DBG_LPTIM5 + LPTIM5 stop in debug + 12 + 1 + + + DBG_RTC + RTC stop in debug + 16 + 1 + + + DBG_IWDG1 + Independent watchdog for D1 stop in debug + 18 + 1 + + + + + + + MPU + Memory protection unit + MPU + 0xE000ED90 + + 0x0 + 0x15 + registers + + + + MPU_TYPER + MPU_TYPER + MPU type register + 0x0 + 0x20 + read-only + 0X00000800 + + + SEPARATE + Separate flag + 0 + 1 + + + DREGION + Number of MPU data regions + 8 + 8 + + + IREGION + Number of MPU instruction + regions + 16 + 8 + + + + + MPU_CTRL + MPU_CTRL + MPU control register + 0x4 + 0x20 + read-write + 0X00000000 + + + ENABLE + Enables the MPU + 0 + 1 + + + HFNMIENA + Enables the operation of MPU during hard + fault + 1 + 1 + + + PRIVDEFENA + Enable priviliged software access to + default memory map + 2 + 1 + + + + + MPU_RNR + MPU_RNR + MPU region number register + 0x8 + 0x20 + read-write + 0X00000000 + + + REGION + MPU region + 0 + 8 + + + + + MPU_RBAR + MPU_RBAR + MPU region base address + register + 0xC + 0x20 + read-write + 0X00000000 + + + REGION + MPU region field + 0 + 4 + + + VALID + MPU region number valid + 4 + 1 + + + ADDR + Region base address field + 5 + 27 + + + + + MPU_RASR + MPU_RASR + MPU region attribute and size + register + 0x10 + 0x20 + read-write + 0X00000000 + + + ENABLE + Region enable bit. + 0 + 1 + + + SIZE + Size of the MPU protection + region + 1 + 5 + + + SRD + Subregion disable bits + 8 + 8 + + + B + memory attribute + 16 + 1 + + + C + memory attribute + 17 + 1 + + + S + Shareable memory attribute + 18 + 1 + + + TEX + memory attribute + 19 + 3 + + + AP + Access permission + 24 + 3 + + + XN + Instruction access disable + bit + 28 + 1 + + + + + + + STK + SysTick timer + STK + 0xE000E010 + + 0x0 + 0x11 + registers + + + + CSR + CSR + SysTick control and status + register + 0x0 + 0x20 + read-write + 0X00000000 + + + ENABLE + Counter enable + 0 + 1 + + + TICKINT + SysTick exception request + enable + 1 + 1 + + + CLKSOURCE + Clock source selection + 2 + 1 + + + COUNTFLAG + COUNTFLAG + 16 + 1 + + + + + RVR + RVR + SysTick reload value register + 0x4 + 0x20 + read-write + 0X00000000 + + + RELOAD + RELOAD value + 0 + 24 + + + + + CVR + CVR + SysTick current value register + 0x8 + 0x20 + read-write + 0X00000000 + + + CURRENT + Current counter value + 0 + 24 + + + + + CALIB + CALIB + SysTick calibration value + register + 0xC + 0x20 + read-write + 0X00000000 + + + TENMS + Calibration value + 0 + 24 + + + SKEW + SKEW flag: Indicates whether the TENMS + value is exact + 30 + 1 + + + NOREF + NOREF flag. Reads as zero + 31 + 1 + + + + + + + NVIC_STIR + Nested vectored interrupt + controller + NVIC + 0xE000EF00 + + 0x0 + 0x5 + registers + + + + STIR + STIR + Software trigger interrupt + register + 0x0 + 0x20 + read-write + 0x00000000 + + + INTID + Software generated interrupt + ID + 0 + 9 + + + + + + + FPU_CPACR + Floating point unit CPACR + FPU + 0xE000ED88 + + 0x0 + 0x5 + registers + + + + CPACR + CPACR + Coprocessor access control + register + 0x0 + 0x20 + read-write + 0x0000000 + + + CP + CP + 20 + 4 + + + + + + + SCB_ACTRL + System control block ACTLR + SCB + 0xE000E008 + + 0x0 + 0x5 + registers + + + + ACTRL + ACTRL + Auxiliary control register + 0x0 + 0x20 + read-write + 0x00000000 + + + DISFOLD + DISFOLD + 2 + 1 + + + FPEXCODIS + FPEXCODIS + 10 + 1 + + + DISRAMODE + DISRAMODE + 11 + 1 + + + DISITMATBFLUSH + DISITMATBFLUSH + 12 + 1 + + + + + + + FPU + Floting point unit + FPU + 0xE000EF34 + + 0x0 + 0xD + registers + + + FPU + Floating point unit interrupt + 81 + + + + FPCCR + FPCCR + Floating-point context control + register + 0x0 + 0x20 + read-write + 0x00000000 + + + LSPACT + LSPACT + 0 + 1 + + + USER + USER + 1 + 1 + + + THREAD + THREAD + 3 + 1 + + + HFRDY + HFRDY + 4 + 1 + + + MMRDY + MMRDY + 5 + 1 + + + BFRDY + BFRDY + 6 + 1 + + + MONRDY + MONRDY + 8 + 1 + + + LSPEN + LSPEN + 30 + 1 + + + ASPEN + ASPEN + 31 + 1 + + + + + FPCAR + FPCAR + Floating-point context address + register + 0x4 + 0x20 + read-write + 0x00000000 + + + ADDRESS + Location of unpopulated + floating-point + 3 + 29 + + + + + FPSCR + FPSCR + Floating-point status control + register + 0x8 + 0x20 + read-write + 0x00000000 + + + IOC + Invalid operation cumulative exception + bit + 0 + 1 + + + DZC + Division by zero cumulative exception + bit. + 1 + 1 + + + OFC + Overflow cumulative exception + bit + 2 + 1 + + + UFC + Underflow cumulative exception + bit + 3 + 1 + + + IXC + Inexact cumulative exception + bit + 4 + 1 + + + IDC + Input denormal cumulative exception + bit. + 7 + 1 + + + RMode + Rounding Mode control + field + 22 + 2 + + + FZ + Flush-to-zero mode control + bit: + 24 + 1 + + + DN + Default NaN mode control + bit + 25 + 1 + + + AHP + Alternative half-precision control + bit + 26 + 1 + + + V + Overflow condition code + flag + 28 + 1 + + + C + Carry condition code flag + 29 + 1 + + + Z + Zero condition code flag + 30 + 1 + + + N + Negative condition code + flag + 31 + 1 + + + + + + + SCB + System control block + SCB + 0xE000ED00 + + 0x0 + 0x41 + registers + + + + CPUID + CPUID + CPUID base register + 0x0 + 0x20 + read-only + 0x410FC241 + + + Revision + Revision number + 0 + 4 + + + PartNo + Part number of the + processor + 4 + 12 + + + Constant + Reads as 0xF + 16 + 4 + + + Variant + Variant number + 20 + 4 + + + Implementer + Implementer code + 24 + 8 + + + + + ICSR + ICSR + Interrupt control and state + register + 0x4 + 0x20 + read-write + 0x00000000 + + + VECTACTIVE + Active vector + 0 + 9 + + + RETTOBASE + Return to base level + 11 + 1 + + + VECTPENDING + Pending vector + 12 + 7 + + + ISRPENDING + Interrupt pending flag + 22 + 1 + + + PENDSTCLR + SysTick exception clear-pending + bit + 25 + 1 + + + PENDSTSET + SysTick exception set-pending + bit + 26 + 1 + + + PENDSVCLR + PendSV clear-pending bit + 27 + 1 + + + PENDSVSET + PendSV set-pending bit + 28 + 1 + + + NMIPENDSET + NMI set-pending bit. + 31 + 1 + + + + + VTOR + VTOR + Vector table offset register + 0x8 + 0x20 + read-write + 0x00000000 + + + TBLOFF + Vector table base offset + field + 9 + 21 + + + + + AIRCR + AIRCR + Application interrupt and reset control + register + 0xC + 0x20 + read-write + 0x00000000 + + + VECTRESET + VECTRESET + 0 + 1 + + + VECTCLRACTIVE + VECTCLRACTIVE + 1 + 1 + + + SYSRESETREQ + SYSRESETREQ + 2 + 1 + + + PRIGROUP + PRIGROUP + 8 + 3 + + + ENDIANESS + ENDIANESS + 15 + 1 + + + VECTKEYSTAT + Register key + 16 + 16 + + + + + SCR + SCR + System control register + 0x10 + 0x20 + read-write + 0x00000000 + + + SLEEPONEXIT + SLEEPONEXIT + 1 + 1 + + + SLEEPDEEP + SLEEPDEEP + 2 + 1 + + + SEVEONPEND + Send Event on Pending bit + 4 + 1 + + + + + CCR + CCR + Configuration and control + register + 0x14 + 0x20 + read-write + 0x00000000 + + + NONBASETHRDENA + Configures how the processor enters + Thread mode + 0 + 1 + + + USERSETMPEND + USERSETMPEND + 1 + 1 + + + UNALIGN__TRP + UNALIGN_ TRP + 3 + 1 + + + DIV_0_TRP + DIV_0_TRP + 4 + 1 + + + BFHFNMIGN + BFHFNMIGN + 8 + 1 + + + STKALIGN + STKALIGN + 9 + 1 + + + DC + DC + 16 + 1 + + + IC + IC + 17 + 1 + + + BP + BP + 18 + 1 + + + + + SHPR1 + SHPR1 + System handler priority + registers + 0x18 + 0x20 + read-write + 0x00000000 + + + PRI_4 + Priority of system handler + 4 + 0 + 8 + + + PRI_5 + Priority of system handler + 5 + 8 + 8 + + + PRI_6 + Priority of system handler + 6 + 16 + 8 + + + + + SHPR2 + SHPR2 + System handler priority + registers + 0x1C + 0x20 + read-write + 0x00000000 + + + PRI_11 + Priority of system handler + 11 + 24 + 8 + + + + + SHPR3 + SHPR3 + System handler priority + registers + 0x20 + 0x20 + read-write + 0x00000000 + + + PRI_14 + Priority of system handler + 14 + 16 + 8 + + + PRI_15 + Priority of system handler + 15 + 24 + 8 + + + + + SHCSR + SHCSR + System handler control and state + register + 0x24 + 0x20 + read-write + 0x00000000 + + + MEMFAULTACT + Memory management fault exception active + bit + 0 + 1 + + + BUSFAULTACT + Bus fault exception active + bit + 1 + 1 + + + USGFAULTACT + Usage fault exception active + bit + 3 + 1 + + + SVCALLACT + SVC call active bit + 7 + 1 + + + MONITORACT + Debug monitor active bit + 8 + 1 + + + PENDSVACT + PendSV exception active + bit + 10 + 1 + + + SYSTICKACT + SysTick exception active + bit + 11 + 1 + + + USGFAULTPENDED + Usage fault exception pending + bit + 12 + 1 + + + MEMFAULTPENDED + Memory management fault exception + pending bit + 13 + 1 + + + BUSFAULTPENDED + Bus fault exception pending + bit + 14 + 1 + + + SVCALLPENDED + SVC call pending bit + 15 + 1 + + + MEMFAULTENA + Memory management fault enable + bit + 16 + 1 + + + BUSFAULTENA + Bus fault enable bit + 17 + 1 + + + USGFAULTENA + Usage fault enable bit + 18 + 1 + + + + + CFSR_UFSR_BFSR_MMFSR + CFSR_UFSR_BFSR_MMFSR + Configurable fault status + register + 0x28 + 0x20 + read-write + 0x00000000 + + + IACCVIOL + IACCVIOL + 0 + 1 + + + DACCVIOL + DACCVIOL + 1 + 1 + + + MUNSTKERR + MUNSTKERR + 3 + 1 + + + MSTKERR + MSTKERR + 4 + 1 + + + MLSPERR + MLSPERR + 5 + 1 + + + MMARVALID + MMARVALID + 7 + 1 + + + IBUSERR + Instruction bus error + 8 + 1 + + + PRECISERR + Precise data bus error + 9 + 1 + + + IMPRECISERR + Imprecise data bus error + 10 + 1 + + + UNSTKERR + Bus fault on unstacking for a return + from exception + 11 + 1 + + + STKERR + Bus fault on stacking for exception + entry + 12 + 1 + + + LSPERR + Bus fault on floating-point lazy state + preservation + 13 + 1 + + + BFARVALID + Bus Fault Address Register (BFAR) valid + flag + 15 + 1 + + + UNDEFINSTR + Undefined instruction usage + fault + 16 + 1 + + + INVSTATE + Invalid state usage fault + 17 + 1 + + + INVPC + Invalid PC load usage + fault + 18 + 1 + + + NOCP + No coprocessor usage + fault. + 19 + 1 + + + UNALIGNED + Unaligned access usage + fault + 24 + 1 + + + DIVBYZERO + Divide by zero usage fault + 25 + 1 + + + + + HFSR + HFSR + Hard fault status register + 0x2C + 0x20 + read-write + 0x00000000 + + + VECTTBL + Vector table hard fault + 1 + 1 + + + FORCED + Forced hard fault + 30 + 1 + + + DEBUG_VT + Reserved for Debug use + 31 + 1 + + + + + MMFAR + MMFAR + Memory management fault address + register + 0x34 + 0x20 + read-write + 0x00000000 + + + ADDRESS + Memory management fault + address + 0 + 32 + + + + + BFAR + BFAR + Bus fault address register + 0x38 + 0x20 + read-write + 0x00000000 + + + ADDRESS + Bus fault address + 0 + 32 + + + + + + + PF + Processor features + PF + 0xE000ED78 + + 0x0 + 0xD + registers + + + + CLIDR + CLIDR + Cache Level ID register + 0x0 + 0x20 + read-only + 0x09000003 + + + CL1 + CL1 + 0 + 3 + + + CL2 + CL2 + 3 + 3 + + + CL3 + CL3 + 6 + 3 + + + CL4 + CL4 + 9 + 3 + + + CL5 + CL5 + 12 + 3 + + + CL6 + CL6 + 15 + 3 + + + CL7 + CL7 + 18 + 3 + + + LoUIS + LoUIS + 21 + 3 + + + LoC + LoC + 24 + 3 + + + LoU + LoU + 27 + 3 + + + + + CTR + CTR + Cache Type register + 0x4 + 0x20 + read-only + 0X8303C003 + + + _IminLine + IminLine + 0 + 4 + + + DMinLine + DMinLine + 16 + 4 + + + ERG + ERG + 20 + 4 + + + CWG + CWG + 24 + 4 + + + Format + Format + 29 + 3 + + + + + CCSIDR + CCSIDR + Cache Size ID register + 0x8 + 0x20 + read-only + 0X00000000 + + + LineSize + LineSize + 0 + 3 + + + Associativity + Associativity + 3 + 10 + + + NumSets + NumSets + 13 + 15 + + + WA + WA + 28 + 1 + + + RA + RA + 29 + 1 + + + WB + WB + 30 + 1 + + + WT + WT + 31 + 1 + + + + + + + AC + Access control + AC + 0xE000EF90 + + 0x0 + 0x1D + registers + + + + ITCMCR + ITCMCR + Instruction and Data Tightly-Coupled Memory + Control Registers + 0x0 + 0x20 + read-write + 0X00000000 + + + EN + EN + 0 + 1 + + + RMW + RMW + 1 + 1 + + + RETEN + RETEN + 2 + 1 + + + SZ + SZ + 3 + 4 + + + + + DTCMCR + DTCMCR + Instruction and Data Tightly-Coupled Memory + Control Registers + 0x4 + 0x20 + read-write + 0X00000000 + + + EN + EN + 0 + 1 + + + RMW + RMW + 1 + 1 + + + RETEN + RETEN + 2 + 1 + + + SZ + SZ + 3 + 4 + + + + + AHBPCR + AHBPCR + AHBP Control register + 0x8 + 0x20 + read-write + 0X00000000 + + + EN + EN + 0 + 1 + + + SZ + SZ + 1 + 3 + + + + + CACR + CACR + Auxiliary Cache Control + register + 0xC + 0x20 + read-write + 0X00000000 + + + SIWT + SIWT + 0 + 1 + + + ECCEN + ECCEN + 1 + 1 + + + FORCEWT + FORCEWT + 2 + 1 + + + + + AHBSCR + AHBSCR + AHB Slave Control register + 0x10 + 0x20 + read-write + 0X00000000 + + + CTL + CTL + 0 + 2 + + + TPRI + TPRI + 2 + 9 + + + INITCOUNT + INITCOUNT + 11 + 5 + + + + + ABFSR + ABFSR + Auxiliary Bus Fault Status + register + 0x18 + 0x20 + read-write + 0X00000000 + + + ITCM + ITCM + 0 + 1 + + + DTCM + DTCM + 1 + 1 + + + AHBP + AHBP + 2 + 1 + + + AXIM + AXIM + 3 + 1 + + + EPPB + EPPB + 4 + 1 + + + AXIMTYPE + AXIMTYPE + 8 + 2 + + + + + + + diff --git a/misc/eclipse/fsfw-stm32h7-freertos-debug.launch b/misc/eclipse/fsfw-stm32h7-freertos-debug.launch index 673b121..5694441 100644 --- a/misc/eclipse/fsfw-stm32h7-freertos-debug.launch +++ b/misc/eclipse/fsfw-stm32h7-freertos-debug.launch @@ -1,5 +1,6 @@ + @@ -22,7 +23,7 @@ - +