diff --git a/CMakeLists.txt b/CMakeLists.txt
index 6196444..a7f8a89 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -15,10 +15,7 @@ set(STM32_CMAKE_PATH "${CMAKE_SCRIPT_PATH}/stm32-cmake")
set(STM32_CUBE_H7_PATH STM32CubeH7)
set(STM32_TOOLCHAIN_PATH $ENV{STM32_TOOLCHAIN_PATH})
set(TARGET_TRIPLET "arm-none-eabi")
-
-if(NOT OS_FSFW)
- set(OS_FSFW host CACHE STRING "OS for the FSFW.")
-endif()
+set(OS_FSFW freertos CACHE STRING "OS for the FSFW")
# This call has to come before the project call
set(CMAKE_TOOLCHAIN_FILE ${STM32_CMAKE_PATH}/cmake/stm32_gcc.cmake)
@@ -37,8 +34,14 @@ find_package(CMSIS COMPONENTS STM32H743ZI STM32H7_M7 RTOS REQUIRED)
find_package(FreeRTOS COMPONENTS STM32H7 ARM_CM7 REQUIRED)
find_package(HAL COMPONENTS STM32H7M7 STM32H743ZI RCC GPIO CORTEX REQUIRED)
+set(TGT_BSP "arm/stm32h743zi-nucleo")
set(FREERTOS_NAMESPACE FreeRTOS::STM32::H7::M7)
+# These need to be set for the FSFW so the sources are compiled with the ABI flags
+# and to compile FreeRTOS first
+set(LIB_OS_NAME ${FREERTOS_NAMESPACE}::ARM_CM7)
+set(FSFW_ADDITIONAL_LINK_LIBS CMSIS::STM32::H743ZI::M7)
+
# Set names and variables
set(TARGET_NAME ${CMAKE_PROJECT_NAME})
set(LIB_FSFW_NAME fsfw)
@@ -52,6 +55,8 @@ set(LIB_FSFW_HAL_PATH fsfw_hal)
set(BSP_PATH "bsp_stm32h7_freertos")
set(COMMON_CONFIG_PATH "${COMMON_PATH}/config")
set(FSFW_CONFIG_PATH "${BSP_PATH}/fsfwconfig")
+set(BSP_NUCLEO_PATH "${BSP_PATH}/NUCLEO-H743ZI")
+
set(FSFW_ADDITIONAL_INC_PATHS
"${COMMON_CONFIG_PATH}"
"${CMAKE_CURRENT_BINARY_DIR}"
@@ -62,6 +67,8 @@ set(FSFW_ADDITIONAL_INC_PATHS
configure_file(${COMMON_CONFIG_PATH}/commonConfig.h.in commonConfig.h)
configure_file(${FSFW_CONFIG_PATH}/FSFWConfig.h.in FSFWConfig.h)
configure_file(${FSFW_CONFIG_PATH}/OBSWConfig.h.in OBSWConfig.h)
+configure_file(${BSP_NUCLEO_PATH}/Inc/FreeRTOSConfig.h.in FreeRTOSConfig.h)
+configure_file(${BSP_NUCLEO_PATH}/Inc/lwipopts.h.in lwipopts.h)
if(CMAKE_CXX_COMPILER_ID STREQUAL "GNU")
set(WARNING_FLAGS
@@ -104,11 +111,11 @@ target_link_libraries(${TARGET_NAME} PRIVATE
HAL::STM32::H7::M7::GPIO
HAL::STM32::H7::M7::CORTEX
CMSIS::STM32::H743ZI::M7
+ CMSIS::STM32::H7::M7::RTOS
STM32::NoSys
STM32::Nano
STM32::Nano::FloatPrint
STM32::Nano::FloatScan
- CMSIS::STM32::H7::M7::RTOS
)
# Add include paths for all sources.
diff --git a/bsp_stm32h7_freertos/CMakeLists.txt b/bsp_stm32h7_freertos/CMakeLists.txt
index df84d30..0b66dbe 100644
--- a/bsp_stm32h7_freertos/CMakeLists.txt
+++ b/bsp_stm32h7_freertos/CMakeLists.txt
@@ -16,4 +16,4 @@ add_subdirectory(core)
add_subdirectory(utility)
add_subdirectory(fsfwconfig)
add_subdirectory(boardtest)
-
+add_subdirectory(NUCLEO-H743ZI)
diff --git a/bsp_stm32h7_freertos/NUCLEO-H743ZI/Inc/FreeRTOSConfig.h b/bsp_stm32h7_freertos/NUCLEO-H743ZI/Inc/FreeRTOSConfig.h.in
similarity index 100%
rename from bsp_stm32h7_freertos/NUCLEO-H743ZI/Inc/FreeRTOSConfig.h
rename to bsp_stm32h7_freertos/NUCLEO-H743ZI/Inc/FreeRTOSConfig.h.in
diff --git a/bsp_stm32h7_freertos/NUCLEO-H743ZI/Inc/lwipopts.h b/bsp_stm32h7_freertos/NUCLEO-H743ZI/Inc/lwipopts.h.in
similarity index 100%
rename from bsp_stm32h7_freertos/NUCLEO-H743ZI/Inc/lwipopts.h
rename to bsp_stm32h7_freertos/NUCLEO-H743ZI/Inc/lwipopts.h.in
diff --git a/bsp_stm32h7_freertos/NUCLEO-H743ZI/Inc/stm32h743xx.h b/bsp_stm32h7_freertos/NUCLEO-H743ZI/Inc/stm32h743xx.h
deleted file mode 100644
index ddc887a..0000000
--- a/bsp_stm32h7_freertos/NUCLEO-H743ZI/Inc/stm32h743xx.h
+++ /dev/null
@@ -1,26287 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h743xx.h
- * @author MCD Application Team
- * @brief CMSIS STM32H743xx Device Peripheral Access Layer Header File.
- *
- * This file contains:
- * - Data structures and the address mapping for all peripherals
- * - Peripheral's registers declarations and bits definition
- * - Macros to access peripheral's registers hardware
- *
- ******************************************************************************
- * @attention
- *
- *
© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/** @addtogroup CMSIS_Device
- * @{
- */
-
-/** @addtogroup stm32h743xx
- * @{
- */
-
-#ifndef STM32H743xx_H
-#define STM32H743xx_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif /* __cplusplus */
-
-/** @addtogroup Peripheral_interrupt_number_definition
- * @{
- */
-
-/**
- * @brief STM32H7XX Interrupt Number Definition, according to the selected device
- * in @ref Library_configuration_section
- */
-typedef enum
-{
-/****** Cortex-M Processor Exceptions Numbers *****************************************************************/
- NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
- HardFault_IRQn = -13, /*!< 4 Cortex-M Memory Management Interrupt */
- MemoryManagement_IRQn = -12, /*!< 4 Cortex-M Memory Management Interrupt */
- BusFault_IRQn = -11, /*!< 5 Cortex-M Bus Fault Interrupt */
- UsageFault_IRQn = -10, /*!< 6 Cortex-M Usage Fault Interrupt */
- SVCall_IRQn = -5, /*!< 11 Cortex-M SV Call Interrupt */
- DebugMonitor_IRQn = -4, /*!< 12 Cortex-M Debug Monitor Interrupt */
- PendSV_IRQn = -2, /*!< 14 Cortex-M Pend SV Interrupt */
- SysTick_IRQn = -1, /*!< 15 Cortex-M System Tick Interrupt */
-/****** STM32 specific Interrupt Numbers **********************************************************************/
- WWDG_IRQn = 0, /*!< Window WatchDog Interrupt ( wwdg1_it, wwdg2_it) */
- PVD_AVD_IRQn = 1, /*!< PVD/AVD through EXTI Line detection Interrupt */
- TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
- RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
- FLASH_IRQn = 4, /*!< FLASH global Interrupt */
- RCC_IRQn = 5, /*!< RCC global Interrupt */
- EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
- EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
- EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
- EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
- EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
- DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
- DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
- DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
- DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
- DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
- DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
- DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
- ADC_IRQn = 18, /*!< ADC1 and ADC2 global Interrupts */
- FDCAN1_IT0_IRQn = 19, /*!< FDCAN1 Interrupt line 0 */
- FDCAN2_IT0_IRQn = 20, /*!< FDCAN2 Interrupt line 0 */
- FDCAN1_IT1_IRQn = 21, /*!< FDCAN1 Interrupt line 1 */
- FDCAN2_IT1_IRQn = 22, /*!< FDCAN2 Interrupt line 1 */
- EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
- TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */
- TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */
- TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */
- TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
- TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
- TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
- TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
- I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
- I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
- I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
- I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
- SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
- SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
- USART1_IRQn = 37, /*!< USART1 global Interrupt */
- USART2_IRQn = 38, /*!< USART2 global Interrupt */
- USART3_IRQn = 39, /*!< USART3 global Interrupt */
- EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
- RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
- TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
- TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
- TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
- TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
- DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
- FMC_IRQn = 48, /*!< FMC global Interrupt */
- SDMMC1_IRQn = 49, /*!< SDMMC1 global Interrupt */
- TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
- SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
- UART4_IRQn = 52, /*!< UART4 global Interrupt */
- UART5_IRQn = 53, /*!< UART5 global Interrupt */
- TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
- TIM7_IRQn = 55, /*!< TIM7 global interrupt */
- DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
- DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
- DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
- DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
- DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
- ETH_IRQn = 61, /*!< Ethernet global Interrupt */
- ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */
- FDCAN_CAL_IRQn = 63, /*!< FDCAN Calibration unit Interrupt */
- DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
- DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
- DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
- USART6_IRQn = 71, /*!< USART6 global interrupt */
- I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
- I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
- OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
- OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
- OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
- OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
- DCMI_IRQn = 78, /*!< DCMI global interrupt */
- RNG_IRQn = 80, /*!< RNG global interrupt */
- FPU_IRQn = 81, /*!< FPU global interrupt */
- UART7_IRQn = 82, /*!< UART7 global interrupt */
- UART8_IRQn = 83, /*!< UART8 global interrupt */
- SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
- SPI5_IRQn = 85, /*!< SPI5 global Interrupt */
- SPI6_IRQn = 86, /*!< SPI6 global Interrupt */
- SAI1_IRQn = 87, /*!< SAI1 global Interrupt */
- LTDC_IRQn = 88, /*!< LTDC global Interrupt */
- LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */
- DMA2D_IRQn = 90, /*!< DMA2D global Interrupt */
- SAI2_IRQn = 91, /*!< SAI2 global Interrupt */
- QUADSPI_IRQn = 92, /*!< Quad SPI global interrupt */
- LPTIM1_IRQn = 93, /*!< LP TIM1 interrupt */
- CEC_IRQn = 94, /*!< HDMI-CEC global Interrupt */
- I2C4_EV_IRQn = 95, /*!< I2C4 Event Interrupt */
- I2C4_ER_IRQn = 96, /*!< I2C4 Error Interrupt */
- SPDIF_RX_IRQn = 97, /*!< SPDIF-RX global Interrupt */
- OTG_FS_EP1_OUT_IRQn = 98, /*!< USB OTG HS2 global interrupt */
- OTG_FS_EP1_IN_IRQn = 99, /*!< USB OTG HS2 End Point 1 Out global interrupt */
- OTG_FS_WKUP_IRQn = 100, /*!< USB OTG HS2 End Point 1 In global interrupt */
- OTG_FS_IRQn = 101, /*!< USB OTG HS2 Wakeup through EXTI interrupt */
- DMAMUX1_OVR_IRQn = 102, /*!
-
-/** @addtogroup Peripheral_registers_structures
- * @{
- */
-
-/**
- * @brief Analog to Digital Converter
- */
-
-typedef struct
-{
- __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */
- __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */
- __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */
- __IO uint32_t CFGR; /*!< ADC Configuration register, Address offset: 0x0C */
- __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset: 0x10 */
- __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */
- __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */
- __IO uint32_t PCSEL; /*!< ADC pre-channel selection, Address offset: 0x1C */
- __IO uint32_t LTR1; /*!< ADC watchdog Lower threshold register 1, Address offset: 0x20 */
- __IO uint32_t HTR1; /*!< ADC watchdog higher threshold register 1, Address offset: 0x24 */
- uint32_t RESERVED1; /*!< Reserved, 0x028 */
- uint32_t RESERVED2; /*!< Reserved, 0x02C */
- __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */
- __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */
- __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */
- __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */
- __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */
- uint32_t RESERVED3; /*!< Reserved, 0x044 */
- uint32_t RESERVED4; /*!< Reserved, 0x048 */
- __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */
- uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C */
- __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */
- __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */
- __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */
- __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */
- uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C */
- __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */
- __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */
- __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */
- __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */
- uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */
- __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */
- __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */
- uint32_t RESERVED8; /*!< Reserved, 0x0A8 */
- uint32_t RESERVED9; /*!< Reserved, 0x0AC */
- __IO uint32_t LTR2; /*!< ADC watchdog Lower threshold register 2, Address offset: 0xB0 */
- __IO uint32_t HTR2; /*!< ADC watchdog Higher threshold register 2, Address offset: 0xB4 */
- __IO uint32_t LTR3; /*!< ADC watchdog Lower threshold register 3, Address offset: 0xB8 */
- __IO uint32_t HTR3; /*!< ADC watchdog Higher threshold register 3, Address offset: 0xBC */
- __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xC0 */
- __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xC4 */
- __IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */
-} ADC_TypeDef;
-
-
-typedef struct
-{
-__IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */
-uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */
-__IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */
-__IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */
-__IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */
-
-} ADC_Common_TypeDef;
-
-
-/**
- * @brief VREFBUF
- */
-
-typedef struct
-{
- __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */
- __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */
-} VREFBUF_TypeDef;
-
-
-/**
- * @brief FD Controller Area Network
- */
-
-typedef struct
-{
- __IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */
- __IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */
- __IO uint32_t RESERVED1; /*!< Reserved, 0x008 */
- __IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */
- __IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */
- __IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */
- __IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */
- __IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */
- __IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */
- __IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */
- __IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */
- __IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */
- __IO uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */
- __IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */
- __IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */
- __IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */
- __IO uint32_t RESERVED3; /*!< Reserved, 0x04C */
- __IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */
- __IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */
- __IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */
- __IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */
- __IO uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */
- __IO uint32_t GFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */
- __IO uint32_t SIDFC; /*!< FDCAN Standard ID Filter Configuration register, Address offset: 0x084 */
- __IO uint32_t XIDFC; /*!< FDCAN Extended ID Filter Configuration register, Address offset: 0x088 */
- __IO uint32_t RESERVED5; /*!< Reserved, 0x08C */
- __IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x090 */
- __IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x094 */
- __IO uint32_t NDAT1; /*!< FDCAN New Data 1 register, Address offset: 0x098 */
- __IO uint32_t NDAT2; /*!< FDCAN New Data 2 register, Address offset: 0x09C */
- __IO uint32_t RXF0C; /*!< FDCAN Rx FIFO 0 Configuration register, Address offset: 0x0A0 */
- __IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x0A4 */
- __IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x0A8 */
- __IO uint32_t RXBC; /*!< FDCAN Rx Buffer Configuration register, Address offset: 0x0AC */
- __IO uint32_t RXF1C; /*!< FDCAN Rx FIFO 1 Configuration register, Address offset: 0x0B0 */
- __IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x0B4 */
- __IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x0B8 */
- __IO uint32_t RXESC; /*!< FDCAN Rx Buffer/FIFO Element Size Configuration register, Address offset: 0x0BC */
- __IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */
- __IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */
- __IO uint32_t TXESC; /*!< FDCAN Tx Buffer Element Size Configuration register, Address offset: 0x0C8 */
- __IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0CC */
- __IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0D0 */
- __IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D4 */
- __IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D8 */
- __IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0DC */
- __IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0E0 */
- __IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E4 */
- __IO uint32_t RESERVED6[2]; /*!< Reserved, 0x0E8 - 0x0EC */
- __IO uint32_t TXEFC; /*!< FDCAN Tx Event FIFO Configuration register, Address offset: 0x0F0 */
- __IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0F4 */
- __IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0F8 */
- __IO uint32_t RESERVED7; /*!< Reserved, 0x0FC */
-} FDCAN_GlobalTypeDef;
-
-/**
- * @brief TTFD Controller Area Network
- */
-
-typedef struct
-{
- __IO uint32_t TTTMC; /*!< TT Trigger Memory Configuration register, Address offset: 0x100 */
- __IO uint32_t TTRMC; /*!< TT Reference Message Configuration register, Address offset: 0x104 */
- __IO uint32_t TTOCF; /*!< TT Operation Configuration register, Address offset: 0x108 */
- __IO uint32_t TTMLM; /*!< TT Matrix Limits register, Address offset: 0x10C */
- __IO uint32_t TURCF; /*!< TUR Configuration register, Address offset: 0x110 */
- __IO uint32_t TTOCN; /*!< TT Operation Control register, Address offset: 0x114 */
- __IO uint32_t TTGTP; /*!< TT Global Time Preset register, Address offset: 0x118 */
- __IO uint32_t TTTMK; /*!< TT Time Mark register, Address offset: 0x11C */
- __IO uint32_t TTIR; /*!< TT Interrupt register, Address offset: 0x120 */
- __IO uint32_t TTIE; /*!< TT Interrupt Enable register, Address offset: 0x124 */
- __IO uint32_t TTILS; /*!< TT Interrupt Line Select register, Address offset: 0x128 */
- __IO uint32_t TTOST; /*!< TT Operation Status register, Address offset: 0x12C */
- __IO uint32_t TURNA; /*!< TT TUR Numerator Actual register, Address offset: 0x130 */
- __IO uint32_t TTLGT; /*!< TT Local and Global Time register, Address offset: 0x134 */
- __IO uint32_t TTCTC; /*!< TT Cycle Time and Count register, Address offset: 0x138 */
- __IO uint32_t TTCPT; /*!< TT Capture Time register, Address offset: 0x13C */
- __IO uint32_t TTCSM; /*!< TT Cycle Sync Mark register, Address offset: 0x140 */
- __IO uint32_t RESERVED1[111]; /*!< Reserved, 0x144 - 0x2FC */
- __IO uint32_t TTTS; /*!< TT Trigger Select register, Address offset: 0x300 */
-} TTCAN_TypeDef;
-
-/**
- * @brief FD Controller Area Network
- */
-
-typedef struct
-{
- __IO uint32_t CREL; /*!< Clock Calibration Unit Core Release register, Address offset: 0x00 */
- __IO uint32_t CCFG; /*!< Calibration Configuration register, Address offset: 0x04 */
- __IO uint32_t CSTAT; /*!< Calibration Status register, Address offset: 0x08 */
- __IO uint32_t CWD; /*!< Calibration Watchdog register, Address offset: 0x0C */
- __IO uint32_t IR; /*!< CCU Interrupt register, Address offset: 0x10 */
- __IO uint32_t IE; /*!< CCU Interrupt Enable register, Address offset: 0x14 */
-} FDCAN_ClockCalibrationUnit_TypeDef;
-
-
-/**
- * @brief Consumer Electronics Control
- */
-
-typedef struct
-{
- __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */
- __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */
- __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */
- __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */
- __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */
- __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */
-}CEC_TypeDef;
-
-/**
- * @brief CRC calculation unit
- */
-
-typedef struct
-{
- __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
- __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
- __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
- uint32_t RESERVED2; /*!< Reserved, 0x0C */
- __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
- __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
-} CRC_TypeDef;
-
-
-/**
- * @brief Clock Recovery System
- */
-typedef struct
-{
-__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */
-__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */
-__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */
-__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */
-} CRS_TypeDef;
-
-
-/**
- * @brief Digital to Analog Converter
- */
-
-typedef struct
-{
- __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
- __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
- __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
- __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
- __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
- __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
- __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
- __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
- __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
- __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
- __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
- __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
- __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
- __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
- __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */
- __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */
- __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */
- __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */
- __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */
- __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */
-} DAC_TypeDef;
-
-/**
- * @brief DFSDM module registers
- */
-typedef struct
-{
- __IO uint32_t FLTCR1; /*!< DFSDM control register1, Address offset: 0x100 */
- __IO uint32_t FLTCR2; /*!< DFSDM control register2, Address offset: 0x104 */
- __IO uint32_t FLTISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */
- __IO uint32_t FLTICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */
- __IO uint32_t FLTJCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */
- __IO uint32_t FLTFCR; /*!< DFSDM filter control register, Address offset: 0x114 */
- __IO uint32_t FLTJDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */
- __IO uint32_t FLTRDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */
- __IO uint32_t FLTAWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */
- __IO uint32_t FLTAWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */
- __IO uint32_t FLTAWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */
- __IO uint32_t FLTAWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */
- __IO uint32_t FLTEXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */
- __IO uint32_t FLTEXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */
- __IO uint32_t FLTCNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */
-} DFSDM_Filter_TypeDef;
-
-/**
- * @brief DFSDM channel configuration registers
- */
-typedef struct
-{
- __IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */
- __IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */
- __IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and
- short circuit detector register, Address offset: 0x08 */
- __IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */
- __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */
-} DFSDM_Channel_TypeDef;
-
-/**
- * @brief Debug MCU
- */
-typedef struct
-{
- __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
- __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
- uint32_t RESERVED4[11]; /*!< Reserved, Address offset: 0x08 */
- __IO uint32_t APB3FZ1; /*!< Debug MCU APB3FZ1 freeze register, Address offset: 0x34 */
- uint32_t RESERVED5; /*!< Reserved, Address offset: 0x38 */
- __IO uint32_t APB1LFZ1; /*!< Debug MCU APB1LFZ1 freeze register, Address offset: 0x3C */
- uint32_t RESERVED6; /*!< Reserved, Address offset: 0x40 */
- __IO uint32_t APB1HFZ1; /*!< Debug MCU APB1LFZ1 freeze register, Address offset: 0x44 */
- uint32_t RESERVED7; /*!< Reserved, Address offset: 0x48 */
- __IO uint32_t APB2FZ1; /*!< Debug MCU APB2FZ1 freeze register, Address offset: 0x4C */
- uint32_t RESERVED8; /*!< Reserved, Address offset: 0x50 */
- __IO uint32_t APB4FZ1; /*!< Debug MCU APB4FZ1 freeze register, Address offset: 0x54 */
-}DBGMCU_TypeDef;
-/**
- * @brief DCMI
- */
-
-typedef struct
-{
- __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */
- __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */
- __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */
- __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */
- __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */
- __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */
- __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */
- __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
- __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */
- __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */
- __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */
-} DCMI_TypeDef;
-
-/**
- * @brief DMA Controller
- */
-
-typedef struct
-{
- __IO uint32_t CR; /*!< DMA stream x configuration register */
- __IO uint32_t NDTR; /*!< DMA stream x number of data register */
- __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
- __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
- __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
- __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
-} DMA_Stream_TypeDef;
-
-typedef struct
-{
- __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
- __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
- __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
- __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
-} DMA_TypeDef;
-
-typedef struct
-{
- __IO uint32_t CCR; /*!< DMA channel x configuration register */
- __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
- __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
- __IO uint32_t CM0AR; /*!< DMA channel x memory 0 address register */
- __IO uint32_t CM1AR; /*!< DMA channel x memory 1 address register */
-} BDMA_Channel_TypeDef;
-
-typedef struct
-{
- __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
- __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
-} BDMA_TypeDef;
-
-typedef struct
-{
- __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register */
-}DMAMUX_Channel_TypeDef;
-
-typedef struct
-{
- __IO uint32_t CSR; /*!< DMA Channel Status Register */
- __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register */
-}DMAMUX_ChannelStatus_TypeDef;
-
-typedef struct
-{
- __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register */
-}DMAMUX_RequestGen_TypeDef;
-
-typedef struct
-{
- __IO uint32_t RGSR; /*!< DMA Request Generator Status Register */
- __IO uint32_t RGCFR; /*!< DMA Request Generator Clear Flag Register */
-}DMAMUX_RequestGenStatus_TypeDef;
-
-/**
- * @brief MDMA Controller
- */
-typedef struct
-{
- __IO uint32_t GISR0; /*!< MDMA Global Interrupt/Status Register 0, Address offset: 0x00 */
-}MDMA_TypeDef;
-
-typedef struct
-{
- __IO uint32_t CISR; /*!< MDMA channel x interrupt/status register, Address offset: 0x40 */
- __IO uint32_t CIFCR; /*!< MDMA channel x interrupt flag clear register, Address offset: 0x44 */
- __IO uint32_t CESR; /*!< MDMA Channel x error status register, Address offset: 0x48 */
- __IO uint32_t CCR; /*!< MDMA channel x control register, Address offset: 0x4C */
- __IO uint32_t CTCR; /*!< MDMA channel x Transfer Configuration register, Address offset: 0x50 */
- __IO uint32_t CBNDTR; /*!< MDMA Channel x block number of data register, Address offset: 0x54 */
- __IO uint32_t CSAR; /*!< MDMA channel x source address register, Address offset: 0x58 */
- __IO uint32_t CDAR; /*!< MDMA channel x destination address register, Address offset: 0x5C */
- __IO uint32_t CBRUR; /*!< MDMA channel x Block Repeat address Update register, Address offset: 0x60 */
- __IO uint32_t CLAR; /*!< MDMA channel x Link Address register, Address offset: 0x64 */
- __IO uint32_t CTBR; /*!< MDMA channel x Trigger and Bus selection Register, Address offset: 0x68 */
- uint32_t RESERVED0; /*!< Reserved, 0x68 */
- __IO uint32_t CMAR; /*!< MDMA channel x Mask address register, Address offset: 0x70 */
- __IO uint32_t CMDR; /*!< MDMA channel x Mask Data register, Address offset: 0x74 */
-}MDMA_Channel_TypeDef;
-
-/**
- * @brief DMA2D Controller
- */
-
-typedef struct
-{
- __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */
- __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */
- __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */
- __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */
- __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */
- __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */
- __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */
- __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */
- __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */
- __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */
- __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */
- __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */
- __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */
- __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */
- __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */
- __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */
- __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */
- __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */
- __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */
- __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */
- uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */
- __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */
- __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */
-} DMA2D_TypeDef;
-
-
-/**
- * @brief Ethernet MAC
- */
-typedef struct
-{
- __IO uint32_t MACCR;
- __IO uint32_t MACECR;
- __IO uint32_t MACPFR;
- __IO uint32_t MACWTR;
- __IO uint32_t MACHT0R;
- __IO uint32_t MACHT1R;
- uint32_t RESERVED1[14];
- __IO uint32_t MACVTR;
- uint32_t RESERVED2;
- __IO uint32_t MACVHTR;
- uint32_t RESERVED3;
- __IO uint32_t MACVIR;
- __IO uint32_t MACIVIR;
- uint32_t RESERVED4[2];
- __IO uint32_t MACTFCR;
- uint32_t RESERVED5[7];
- __IO uint32_t MACRFCR;
- uint32_t RESERVED6[7];
- __IO uint32_t MACISR;
- __IO uint32_t MACIER;
- __IO uint32_t MACRXTXSR;
- uint32_t RESERVED7;
- __IO uint32_t MACPCSR;
- __IO uint32_t MACRWKPFR;
- uint32_t RESERVED8[2];
- __IO uint32_t MACLCSR;
- __IO uint32_t MACLTCR;
- __IO uint32_t MACLETR;
- __IO uint32_t MAC1USTCR;
- uint32_t RESERVED9[12];
- __IO uint32_t MACVR;
- __IO uint32_t MACDR;
- uint32_t RESERVED10;
- __IO uint32_t MACHWF0R;
- __IO uint32_t MACHWF1R;
- __IO uint32_t MACHWF2R;
- uint32_t RESERVED11[54];
- __IO uint32_t MACMDIOAR;
- __IO uint32_t MACMDIODR;
- uint32_t RESERVED12[2];
- __IO uint32_t MACARPAR;
- uint32_t RESERVED13[59];
- __IO uint32_t MACA0HR;
- __IO uint32_t MACA0LR;
- __IO uint32_t MACA1HR;
- __IO uint32_t MACA1LR;
- __IO uint32_t MACA2HR;
- __IO uint32_t MACA2LR;
- __IO uint32_t MACA3HR;
- __IO uint32_t MACA3LR;
- uint32_t RESERVED14[248];
- __IO uint32_t MMCCR;
- __IO uint32_t MMCRIR;
- __IO uint32_t MMCTIR;
- __IO uint32_t MMCRIMR;
- __IO uint32_t MMCTIMR;
- uint32_t RESERVED15[14];
- __IO uint32_t MMCTSCGPR;
- __IO uint32_t MMCTMCGPR;
- uint32_t RESERVED16[5];
- __IO uint32_t MMCTPCGR;
- uint32_t RESERVED17[10];
- __IO uint32_t MMCRCRCEPR;
- __IO uint32_t MMCRAEPR;
- uint32_t RESERVED18[10];
- __IO uint32_t MMCRUPGR;
- uint32_t RESERVED19[9];
- __IO uint32_t MMCTLPIMSTR;
- __IO uint32_t MMCTLPITCR;
- __IO uint32_t MMCRLPIMSTR;
- __IO uint32_t MMCRLPITCR;
- uint32_t RESERVED20[65];
- __IO uint32_t MACL3L4C0R;
- __IO uint32_t MACL4A0R;
- uint32_t RESERVED21[2];
- __IO uint32_t MACL3A0R0R;
- __IO uint32_t MACL3A1R0R;
- __IO uint32_t MACL3A2R0R;
- __IO uint32_t MACL3A3R0R;
- uint32_t RESERVED22[4];
- __IO uint32_t MACL3L4C1R;
- __IO uint32_t MACL4A1R;
- uint32_t RESERVED23[2];
- __IO uint32_t MACL3A0R1R;
- __IO uint32_t MACL3A1R1R;
- __IO uint32_t MACL3A2R1R;
- __IO uint32_t MACL3A3R1R;
- uint32_t RESERVED24[108];
- __IO uint32_t MACTSCR;
- __IO uint32_t MACSSIR;
- __IO uint32_t MACSTSR;
- __IO uint32_t MACSTNR;
- __IO uint32_t MACSTSUR;
- __IO uint32_t MACSTNUR;
- __IO uint32_t MACTSAR;
- uint32_t RESERVED25;
- __IO uint32_t MACTSSR;
- uint32_t RESERVED26[3];
- __IO uint32_t MACTTSSNR;
- __IO uint32_t MACTTSSSR;
- uint32_t RESERVED27[2];
- __IO uint32_t MACACR;
- uint32_t RESERVED28;
- __IO uint32_t MACATSNR;
- __IO uint32_t MACATSSR;
- __IO uint32_t MACTSIACR;
- __IO uint32_t MACTSEACR;
- __IO uint32_t MACTSICNR;
- __IO uint32_t MACTSECNR;
- uint32_t RESERVED29[4];
- __IO uint32_t MACPPSCR;
- uint32_t RESERVED30[3];
- __IO uint32_t MACPPSTTSR;
- __IO uint32_t MACPPSTTNR;
- __IO uint32_t MACPPSIR;
- __IO uint32_t MACPPSWR;
- uint32_t RESERVED31[12];
- __IO uint32_t MACPOCR;
- __IO uint32_t MACSPI0R;
- __IO uint32_t MACSPI1R;
- __IO uint32_t MACSPI2R;
- __IO uint32_t MACLMIR;
- uint32_t RESERVED32[11];
- __IO uint32_t MTLOMR;
- uint32_t RESERVED33[7];
- __IO uint32_t MTLISR;
- uint32_t RESERVED34[55];
- __IO uint32_t MTLTQOMR;
- __IO uint32_t MTLTQUR;
- __IO uint32_t MTLTQDR;
- uint32_t RESERVED35[8];
- __IO uint32_t MTLQICSR;
- __IO uint32_t MTLRQOMR;
- __IO uint32_t MTLRQMPOCR;
- __IO uint32_t MTLRQDR;
- uint32_t RESERVED36[177];
- __IO uint32_t DMAMR;
- __IO uint32_t DMASBMR;
- __IO uint32_t DMAISR;
- __IO uint32_t DMADSR;
- uint32_t RESERVED37[60];
- __IO uint32_t DMACCR;
- __IO uint32_t DMACTCR;
- __IO uint32_t DMACRCR;
- uint32_t RESERVED38[2];
- __IO uint32_t DMACTDLAR;
- uint32_t RESERVED39;
- __IO uint32_t DMACRDLAR;
- __IO uint32_t DMACTDTPR;
- uint32_t RESERVED40;
- __IO uint32_t DMACRDTPR;
- __IO uint32_t DMACTDRLR;
- __IO uint32_t DMACRDRLR;
- __IO uint32_t DMACIER;
- __IO uint32_t DMACRIWTR;
-__IO uint32_t DMACSFCSR;
- uint32_t RESERVED41;
- __IO uint32_t DMACCATDR;
- uint32_t RESERVED42;
- __IO uint32_t DMACCARDR;
- uint32_t RESERVED43;
- __IO uint32_t DMACCATBR;
- uint32_t RESERVED44;
- __IO uint32_t DMACCARBR;
- __IO uint32_t DMACSR;
-uint32_t RESERVED45[2];
-__IO uint32_t DMACMFCR;
-}ETH_TypeDef;
-/**
- * @brief External Interrupt/Event Controller
- */
-
-typedef struct
-{
-__IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register, Address offset: 0x00 */
-__IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register, Address offset: 0x04 */
-__IO uint32_t SWIER1; /*!< EXTI Software interrupt event register, Address offset: 0x08 */
-__IO uint32_t D3PMR1; /*!< EXTI D3 Pending mask register, (same register as to SRDPMR1) Address offset: 0x0C */
-__IO uint32_t D3PCR1L; /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR1L) Address offset: 0x10 */
-__IO uint32_t D3PCR1H; /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR1H) Address offset: 0x14 */
-uint32_t RESERVED1[2]; /*!< Reserved, 0x18 to 0x1C */
-__IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x20 */
-__IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x24 */
-__IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x28 */
-__IO uint32_t D3PMR2; /*!< EXTI D3 Pending mask register, (same register as to SRDPMR2) Address offset: 0x2C */
-__IO uint32_t D3PCR2L; /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR2L) Address offset: 0x30 */
-__IO uint32_t D3PCR2H; /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR2H) Address offset: 0x34 */
-uint32_t RESERVED2[2]; /*!< Reserved, 0x38 to 0x3C */
-__IO uint32_t RTSR3; /*!< EXTI Rising trigger selection register, Address offset: 0x40 */
-__IO uint32_t FTSR3; /*!< EXTI Falling trigger selection register, Address offset: 0x44 */
-__IO uint32_t SWIER3; /*!< EXTI Software interrupt event register, Address offset: 0x48 */
-__IO uint32_t D3PMR3; /*!< EXTI D3 Pending mask register, (same register as to SRDPMR3) Address offset: 0x4C */
-__IO uint32_t D3PCR3L; /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR3L) Address offset: 0x50 */
-__IO uint32_t D3PCR3H; /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR3H) Address offset: 0x54 */
-uint32_t RESERVED3[10]; /*!< Reserved, 0x58 to 0x7C */
-__IO uint32_t IMR1; /*!< EXTI Interrupt mask register, Address offset: 0x80 */
-__IO uint32_t EMR1; /*!< EXTI Event mask register, Address offset: 0x84 */
-__IO uint32_t PR1; /*!< EXTI Pending register, Address offset: 0x88 */
-uint32_t RESERVED4; /*!< Reserved, 0x8C */
-__IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x90 */
-__IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x94 */
-__IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x98 */
-uint32_t RESERVED5; /*!< Reserved, 0x9C */
-__IO uint32_t IMR3; /*!< EXTI Interrupt mask register, Address offset: 0xA0 */
-__IO uint32_t EMR3; /*!< EXTI Event mask register, Address offset: 0xA4 */
-__IO uint32_t PR3; /*!< EXTI Pending register, Address offset: 0xA8 */
-}EXTI_TypeDef;
-
-typedef struct
-{
-__IO uint32_t IMR1; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
-__IO uint32_t EMR1; /*!< EXTI Event mask register, Address offset: 0x04 */
-__IO uint32_t PR1; /*!< EXTI Pending register, Address offset: 0x08 */
-uint32_t RESERVED1; /*!< Reserved, 0x0C */
-__IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x10 */
-__IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x14 */
-__IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x18 */
-uint32_t RESERVED2; /*!< Reserved, 0x1C */
-__IO uint32_t IMR3; /*!< EXTI Interrupt mask register, Address offset: 0x20 */
-__IO uint32_t EMR3; /*!< EXTI Event mask register, Address offset: 0x24 */
-__IO uint32_t PR3; /*!< EXTI Pending register, Address offset: 0x28 */
-}EXTI_Core_TypeDef;
-
-
-/**
- * @brief FLASH Registers
- */
-
-typedef struct
-{
- __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
- __IO uint32_t KEYR1; /*!< Flash Key Register for bank1, Address offset: 0x04 */
- __IO uint32_t OPTKEYR; /*!< Flash Option Key Register, Address offset: 0x08 */
- __IO uint32_t CR1; /*!< Flash Control Register for bank1, Address offset: 0x0C */
- __IO uint32_t SR1; /*!< Flash Status Register for bank1, Address offset: 0x10 */
- __IO uint32_t CCR1; /*!< Flash Control Register for bank1, Address offset: 0x14 */
- __IO uint32_t OPTCR; /*!< Flash Option Control Register, Address offset: 0x18 */
- __IO uint32_t OPTSR_CUR; /*!< Flash Option Status Current Register, Address offset: 0x1C */
- __IO uint32_t OPTSR_PRG; /*!< Flash Option Status to Program Register, Address offset: 0x20 */
- __IO uint32_t OPTCCR; /*!< Flash Option Clear Control Register, Address offset: 0x24 */
- __IO uint32_t PRAR_CUR1; /*!< Flash Current Protection Address Register for bank1, Address offset: 0x28 */
- __IO uint32_t PRAR_PRG1; /*!< Flash Protection Address to Program Register for bank1, Address offset: 0x2C */
- __IO uint32_t SCAR_CUR1; /*!< Flash Current Secure Address Register for bank1, Address offset: 0x30 */
- __IO uint32_t SCAR_PRG1; /*!< Flash Secure Address to Program Register for bank1, Address offset: 0x34 */
- __IO uint32_t WPSN_CUR1; /*!< Flash Current Write Protection Register on bank1, Address offset: 0x38 */
- __IO uint32_t WPSN_PRG1; /*!< Flash Write Protection to Program Register on bank1, Address offset: 0x3C */
- __IO uint32_t BOOT_CUR; /*!< Flash Current Boot Address for Pelican Core Register, Address offset: 0x40 */
- __IO uint32_t BOOT_PRG; /*!< Flash Boot Address to Program for Pelican Core Register, Address offset: 0x44 */
- uint32_t RESERVED0[2]; /*!< Reserved, 0x48 to 0x4C */
- __IO uint32_t CRCCR1; /*!< Flash CRC Control register For Bank1 Register , Address offset: 0x50 */
- __IO uint32_t CRCSADD1; /*!< Flash CRC Start Address Register for Bank1 , Address offset: 0x54 */
- __IO uint32_t CRCEADD1; /*!< Flash CRC End Address Register for Bank1 , Address offset: 0x58 */
- __IO uint32_t CRCDATA; /*!< Flash CRC Data Register for Bank1 , Address offset: 0x5C */
- __IO uint32_t ECC_FA1; /*!< Flash ECC Fail Address For Bank1 Register , Address offset: 0x60 */
- uint32_t RESERVED1[40]; /*!< Reserved, 0x64 to 0x100 */
- __IO uint32_t KEYR2; /*!< Flash Key Register for bank2, Address offset: 0x104 */
- uint32_t RESERVED2; /*!< Reserved, 0x108 */
- __IO uint32_t CR2; /*!< Flash Control Register for bank2, Address offset: 0x10C */
- __IO uint32_t SR2; /*!< Flash Status Register for bank2, Address offset: 0x110 */
- __IO uint32_t CCR2; /*!< Flash Status Register for bank2, Address offset: 0x114 */
- uint32_t RESERVED3[4]; /*!< Reserved, 0x118 to 0x124 */
- __IO uint32_t PRAR_CUR2; /*!< Flash Current Protection Address Register for bank2, Address offset: 0x128 */
- __IO uint32_t PRAR_PRG2; /*!< Flash Protection Address to Program Register for bank2, Address offset: 0x12C */
- __IO uint32_t SCAR_CUR2; /*!< Flash Current Secure Address Register for bank2, Address offset: 0x130 */
- __IO uint32_t SCAR_PRG2; /*!< Flash Secure Address Register for bank2, Address offset: 0x134 */
- __IO uint32_t WPSN_CUR2; /*!< Flash Current Write Protection Register on bank2, Address offset: 0x138 */
- __IO uint32_t WPSN_PRG2; /*!< Flash Write Protection to Program Register on bank2, Address offset: 0x13C */
- uint32_t RESERVED4[4]; /*!< Reserved, 0x140 to 0x14C */
- __IO uint32_t CRCCR2; /*!< Flash CRC Control register For Bank2 Register , Address offset: 0x150 */
- __IO uint32_t CRCSADD2; /*!< Flash CRC Start Address Register for Bank2 , Address offset: 0x154 */
- __IO uint32_t CRCEADD2; /*!< Flash CRC End Address Register for Bank2 , Address offset: 0x158 */
- __IO uint32_t CRCDATA2; /*!< Flash CRC Data Register for Bank2 , Address offset: 0x15C */
- __IO uint32_t ECC_FA2; /*!< Flash ECC Fail Address For Bank2 Register , Address offset: 0x160 */
-} FLASH_TypeDef;
-
-/**
- * @brief Flexible Memory Controller
- */
-
-typedef struct
-{
- __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
-} FMC_Bank1_TypeDef;
-
-/**
- * @brief Flexible Memory Controller Bank1E
- */
-
-typedef struct
-{
- __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
-} FMC_Bank1E_TypeDef;
-
-/**
- * @brief Flexible Memory Controller Bank2
- */
-
-typedef struct
-{
- __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */
- __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */
- __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */
- __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
- uint32_t RESERVED0; /*!< Reserved, 0x70 */
- __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */
-} FMC_Bank2_TypeDef;
-
-/**
- * @brief Flexible Memory Controller Bank3
- */
-
-typedef struct
-{
- __IO uint32_t PCR; /*!< NAND Flash control register 3, Address offset: 0x80 */
- __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */
- __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */
- __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
- uint32_t RESERVED; /*!< Reserved, 0x90 */
- __IO uint32_t ECCR; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */
-} FMC_Bank3_TypeDef;
-
-/**
- * @brief Flexible Memory Controller Bank5 and 6
- */
-
-
-typedef struct
-{
- __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */
- __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */
- __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */
- __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */
- __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */
-} FMC_Bank5_6_TypeDef;
-
-/**
- * @brief General Purpose I/O
- */
-
-typedef struct
-{
- __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
- __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
- __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
- __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
- __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
- __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
- __IO uint32_t BSRR; /*!< GPIO port bit set/reset, Address offset: 0x18 */
- __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
- __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
-} GPIO_TypeDef;
-
-/**
- * @brief Operational Amplifier (OPAMP)
- */
-
-typedef struct
-{
- __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */
- __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */
- __IO uint32_t HSOTR; /*!< OPAMP offset trimming register for high speed mode, Address offset: 0x08 */
-} OPAMP_TypeDef;
-
-/**
- * @brief System configuration controller
- */
-
-typedef struct
-{
- uint32_t RESERVED1; /*!< Reserved, Address offset: 0x00 */
- __IO uint32_t PMCR; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
- __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
- __IO uint32_t CFGR; /*!< SYSCFG configuration registers, Address offset: 0x18 */
- uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */
- __IO uint32_t CCCSR; /*!< SYSCFG compensation cell control/status register, Address offset: 0x20 */
- __IO uint32_t CCVR; /*!< SYSCFG compensation cell value register, Address offset: 0x24 */
- __IO uint32_t CCCR; /*!< SYSCFG compensation cell code register, Address offset: 0x28 */
- __IO uint32_t PWRCR; /*!< PWR control register, Address offset: 0x2C */
- uint32_t RESERVED3[61]; /*!< Reserved, 0x30-0x120 */
- __IO uint32_t PKGR; /*!< SYSCFG package register, Address offset: 0x124 */
- uint32_t RESERVED4[118]; /*!< Reserved, 0x128-0x2FC */
- __IO uint32_t UR0; /*!< SYSCFG user register 0, Address offset: 0x300 */
- __IO uint32_t UR1; /*!< SYSCFG user register 1, Address offset: 0x304 */
- __IO uint32_t UR2; /*!< SYSCFG user register 2, Address offset: 0x308 */
- __IO uint32_t UR3; /*!< SYSCFG user register 3, Address offset: 0x30C */
- __IO uint32_t UR4; /*!< SYSCFG user register 4, Address offset: 0x310 */
- __IO uint32_t UR5; /*!< SYSCFG user register 5, Address offset: 0x314 */
- __IO uint32_t UR6; /*!< SYSCFG user register 6, Address offset: 0x318 */
- __IO uint32_t UR7; /*!< SYSCFG user register 7, Address offset: 0x31C */
- __IO uint32_t UR8; /*!< SYSCFG user register 8, Address offset: 0x320 */
- __IO uint32_t UR9; /*!< SYSCFG user register 9, Address offset: 0x324 */
- __IO uint32_t UR10; /*!< SYSCFG user register 10, Address offset: 0x328 */
- __IO uint32_t UR11; /*!< SYSCFG user register 11, Address offset: 0x32C */
- __IO uint32_t UR12; /*!< SYSCFG user register 12, Address offset: 0x330 */
- __IO uint32_t UR13; /*!< SYSCFG user register 13, Address offset: 0x334 */
- __IO uint32_t UR14; /*!< SYSCFG user register 14, Address offset: 0x338 */
- __IO uint32_t UR15; /*!< SYSCFG user register 15, Address offset: 0x33C */
- __IO uint32_t UR16; /*!< SYSCFG user register 16, Address offset: 0x340 */
- __IO uint32_t UR17; /*!< SYSCFG user register 17, Address offset: 0x344 */
-
-} SYSCFG_TypeDef;
-
-/**
- * @brief Inter-integrated Circuit Interface
- */
-
-typedef struct
-{
- __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
- __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
- __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
- __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
- __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
- __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
- __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
- __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
- __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
- __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
- __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
-} I2C_TypeDef;
-
-/**
- * @brief Independent WATCHDOG
- */
-
-typedef struct
-{
- __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
- __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
- __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
- __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
- __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
-} IWDG_TypeDef;
-
-
-/**
- * @brief JPEG Codec
- */
-typedef struct
-{
- __IO uint32_t CONFR0; /*!< JPEG Codec Control Register (JPEG_CONFR0), Address offset: 00h */
- __IO uint32_t CONFR1; /*!< JPEG Codec Control Register (JPEG_CONFR1), Address offset: 04h */
- __IO uint32_t CONFR2; /*!< JPEG Codec Control Register (JPEG_CONFR2), Address offset: 08h */
- __IO uint32_t CONFR3; /*!< JPEG Codec Control Register (JPEG_CONFR3), Address offset: 0Ch */
- __IO uint32_t CONFR4; /*!< JPEG Codec Control Register (JPEG_CONFR4), Address offset: 10h */
- __IO uint32_t CONFR5; /*!< JPEG Codec Control Register (JPEG_CONFR5), Address offset: 14h */
- __IO uint32_t CONFR6; /*!< JPEG Codec Control Register (JPEG_CONFR6), Address offset: 18h */
- __IO uint32_t CONFR7; /*!< JPEG Codec Control Register (JPEG_CONFR7), Address offset: 1Ch */
- uint32_t Reserved20[4]; /* Reserved Address offset: 20h-2Ch */
- __IO uint32_t CR; /*!< JPEG Control Register (JPEG_CR), Address offset: 30h */
- __IO uint32_t SR; /*!< JPEG Status Register (JPEG_SR), Address offset: 34h */
- __IO uint32_t CFR; /*!< JPEG Clear Flag Register (JPEG_CFR), Address offset: 38h */
- uint32_t Reserved3c; /* Reserved Address offset: 3Ch */
- __IO uint32_t DIR; /*!< JPEG Data Input Register (JPEG_DIR), Address offset: 40h */
- __IO uint32_t DOR; /*!< JPEG Data Output Register (JPEG_DOR), Address offset: 44h */
- uint32_t Reserved48[2]; /* Reserved Address offset: 48h-4Ch */
- __IO uint32_t QMEM0[16]; /*!< JPEG quantization tables 0, Address offset: 50h-8Ch */
- __IO uint32_t QMEM1[16]; /*!< JPEG quantization tables 1, Address offset: 90h-CCh */
- __IO uint32_t QMEM2[16]; /*!< JPEG quantization tables 2, Address offset: D0h-10Ch */
- __IO uint32_t QMEM3[16]; /*!< JPEG quantization tables 3, Address offset: 110h-14Ch */
- __IO uint32_t HUFFMIN[16]; /*!< JPEG HuffMin tables, Address offset: 150h-18Ch */
- __IO uint32_t HUFFBASE[32]; /*!< JPEG HuffSymb tables, Address offset: 190h-20Ch */
- __IO uint32_t HUFFSYMB[84]; /*!< JPEG HUFFSYMB tables, Address offset: 210h-35Ch */
- __IO uint32_t DHTMEM[103]; /*!< JPEG DHTMem tables, Address offset: 360h-4F8h */
- uint32_t Reserved4FC; /* Reserved Address offset: 4FCh */
- __IO uint32_t HUFFENC_AC0[88]; /*!< JPEG encodor, AC Huffman table 0, Address offset: 500h-65Ch */
- __IO uint32_t HUFFENC_AC1[88]; /*!< JPEG encodor, AC Huffman table 1, Address offset: 660h-7BCh */
- __IO uint32_t HUFFENC_DC0[8]; /*!< JPEG encodor, DC Huffman table 0, Address offset: 7C0h-7DCh */
- __IO uint32_t HUFFENC_DC1[8]; /*!< JPEG encodor, DC Huffman table 1, Address offset: 7E0h-7FCh */
-
-} JPEG_TypeDef;
-
-/**
- * @brief LCD-TFT Display Controller
- */
-
-typedef struct
-{
- uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */
- __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */
- __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */
- __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */
- __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */
- __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */
- uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */
- __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */
- uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */
- __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */
- uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */
- __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */
- __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */
- __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */
- __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */
- __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */
- __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */
-} LTDC_TypeDef;
-
-/**
- * @brief LCD-TFT Display layer x Controller
- */
-
-typedef struct
-{
- __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */
- __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */
- __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */
- __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */
- __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */
- __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */
- __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */
- __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */
- uint32_t RESERVED0[2]; /*!< Reserved */
- __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */
- __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */
- __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */
- uint32_t RESERVED1[3]; /*!< Reserved */
- __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */
-
-} LTDC_Layer_TypeDef;
-
-/**
- * @brief Power Control
- */
-
-typedef struct
-{
- __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */
- __IO uint32_t CSR1; /*!< PWR power control status register 1, Address offset: 0x04 */
- __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x08 */
- __IO uint32_t CR3; /*!< PWR power control register 3, Address offset: 0x0C */
- __IO uint32_t CPUCR; /*!< PWR CPU control register, Address offset: 0x10 */
- uint32_t RESERVED0; /*!< Reserved, Address offset: 0x14 */
- __IO uint32_t D3CR; /*!< PWR D3 domain control register, Address offset: 0x18 */
- uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */
- __IO uint32_t WKUPCR; /*!< PWR wakeup clear register, Address offset: 0x20 */
- __IO uint32_t WKUPFR; /*!< PWR wakeup flag register, Address offset: 0x24 */
- __IO uint32_t WKUPEPR; /*!< PWR wakeup enable and polarity register, Address offset: 0x28 */
-} PWR_TypeDef;
-
-/**
- * @brief Reset and Clock Control
- */
-
-typedef struct
-{
- __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
- __IO uint32_t HSICFGR; /*!< HSI Clock Calibration Register, Address offset: 0x04 */
- __IO uint32_t CRRCR; /*!< Clock Recovery RC Register, Address offset: 0x08 */
- __IO uint32_t CSICFGR; /*!< CSI Clock Calibration Register, Address offset: 0x0C */
- __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x10 */
- uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
- __IO uint32_t D1CFGR; /*!< RCC Domain 1 configuration register, Address offset: 0x18 */
- __IO uint32_t D2CFGR; /*!< RCC Domain 2 configuration register, Address offset: 0x1C */
- __IO uint32_t D3CFGR; /*!< RCC Domain 3 configuration register, Address offset: 0x20 */
- uint32_t RESERVED2; /*!< Reserved, Address offset: 0x24 */
- __IO uint32_t PLLCKSELR; /*!< RCC PLLs Clock Source Selection Register, Address offset: 0x28 */
- __IO uint32_t PLLCFGR; /*!< RCC PLLs Configuration Register, Address offset: 0x2C */
- __IO uint32_t PLL1DIVR; /*!< RCC PLL1 Dividers Configuration Register, Address offset: 0x30 */
- __IO uint32_t PLL1FRACR; /*!< RCC PLL1 Fractional Divider Configuration Register, Address offset: 0x34 */
- __IO uint32_t PLL2DIVR; /*!< RCC PLL2 Dividers Configuration Register, Address offset: 0x38 */
- __IO uint32_t PLL2FRACR; /*!< RCC PLL2 Fractional Divider Configuration Register, Address offset: 0x3C */
- __IO uint32_t PLL3DIVR; /*!< RCC PLL3 Dividers Configuration Register, Address offset: 0x40 */
- __IO uint32_t PLL3FRACR; /*!< RCC PLL3 Fractional Divider Configuration Register, Address offset: 0x44 */
- uint32_t RESERVED3; /*!< Reserved, Address offset: 0x48 */
- __IO uint32_t D1CCIPR; /*!< RCC Domain 1 Kernel Clock Configuration Register Address offset: 0x4C */
- __IO uint32_t D2CCIP1R; /*!< RCC Domain 2 Kernel Clock Configuration Register Address offset: 0x50 */
- __IO uint32_t D2CCIP2R; /*!< RCC Domain 2 Kernel Clock Configuration Register Address offset: 0x54 */
- __IO uint32_t D3CCIPR; /*!< RCC Domain 3 Kernel Clock Configuration Register Address offset: 0x58 */
- uint32_t RESERVED4; /*!< Reserved, Address offset: 0x5C */
- __IO uint32_t CIER; /*!< RCC Clock Source Interrupt Enable Register Address offset: 0x60 */
- __IO uint32_t CIFR; /*!< RCC Clock Source Interrupt Flag Register Address offset: 0x64 */
- __IO uint32_t CICR; /*!< RCC Clock Source Interrupt Clear Register Address offset: 0x68 */
- uint32_t RESERVED5; /*!< Reserved, Address offset: 0x6C */
- __IO uint32_t BDCR; /*!< RCC Vswitch Backup Domain Control Register, Address offset: 0x70 */
- __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
- uint32_t RESERVED6; /*!< Reserved, Address offset: 0x78 */
- __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x7C */
- __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x80 */
- __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x84 */
- __IO uint32_t AHB4RSTR; /*!< RCC AHB4 peripheral reset register, Address offset: 0x88 */
- __IO uint32_t APB3RSTR; /*!< RCC APB3 peripheral reset register, Address offset: 0x8C */
- __IO uint32_t APB1LRSTR; /*!< RCC APB1 peripheral reset Low Word register, Address offset: 0x90 */
- __IO uint32_t APB1HRSTR; /*!< RCC APB1 peripheral reset High Word register, Address offset: 0x94 */
- __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x98 */
- __IO uint32_t APB4RSTR; /*!< RCC APB4 peripheral reset register, Address offset: 0x9C */
- __IO uint32_t GCR; /*!< RCC RCC Global Control Register, Address offset: 0xA0 */
- uint32_t RESERVED8; /*!< Reserved, Address offset: 0xA4 */
- __IO uint32_t D3AMR; /*!< RCC Domain 3 Autonomous Mode Register, Address offset: 0xA8 */
- uint32_t RESERVED11[9]; /*!< Reserved, 0xAC-0xCC Address offset: 0xAC */
- __IO uint32_t RSR; /*!< RCC Reset status register, Address offset: 0xD0 */
- __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0xD4 */
- __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0xD8 */
- __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0xDC */
- __IO uint32_t AHB4ENR; /*!< RCC AHB4 peripheral clock register, Address offset: 0xE0 */
- __IO uint32_t APB3ENR; /*!< RCC APB3 peripheral clock register, Address offset: 0xE4 */
- __IO uint32_t APB1LENR; /*!< RCC APB1 peripheral clock Low Word register, Address offset: 0xE8 */
- __IO uint32_t APB1HENR; /*!< RCC APB1 peripheral clock High Word register, Address offset: 0xEC */
- __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock register, Address offset: 0xF0 */
- __IO uint32_t APB4ENR; /*!< RCC APB4 peripheral clock register, Address offset: 0xF4 */
- uint32_t RESERVED12; /*!< Reserved, Address offset: 0xF8 */
- __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral sleep clock register, Address offset: 0xFC */
- __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral sleep clock register, Address offset: 0x100 */
- __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral sleep clock register, Address offset: 0x104 */
- __IO uint32_t AHB4LPENR; /*!< RCC AHB4 peripheral sleep clock register, Address offset: 0x108 */
- __IO uint32_t APB3LPENR; /*!< RCC APB3 peripheral sleep clock register, Address offset: 0x10C */
- __IO uint32_t APB1LLPENR; /*!< RCC APB1 peripheral sleep clock Low Word register, Address offset: 0x110 */
- __IO uint32_t APB1HLPENR; /*!< RCC APB1 peripheral sleep clock High Word register, Address offset: 0x114 */
- __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral sleep clock register, Address offset: 0x118 */
- __IO uint32_t APB4LPENR; /*!< RCC APB4 peripheral sleep clock register, Address offset: 0x11C */
- uint32_t RESERVED13[4]; /*!< Reserved, 0x120-0x12C Address offset: 0x120 */
-
-} RCC_TypeDef;
-
-
-/**
- * @brief Real-Time Clock
- */
-typedef struct
-{
- __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
- __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
- __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
- __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
- __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
- __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
- uint32_t RESERVED; /*!< Reserved, Address offset: 0x18 */
- __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
- __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
- __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
- __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
- __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
- __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
- __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
- __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
- __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
- __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */
- __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
- __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */
- __IO uint32_t OR; /*!< RTC option register, Address offset: 0x4C */
- __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
- __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
- __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
- __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
- __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
- __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
- __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
- __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
- __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
- __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
- __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
- __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
- __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
- __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
- __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
- __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
- __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
- __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
- __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
- __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
- __IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */
- __IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */
- __IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */
- __IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */
- __IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */
- __IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */
- __IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */
- __IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */
- __IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */
- __IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */
- __IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */
- __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */
-} RTC_TypeDef;
-
-/**
- * @brief Serial Audio Interface
- */
-
-typedef struct
-{
- __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
- uint32_t RESERVED0[16]; /*!< Reserved, 0x04 - 0x43 */
- __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */
- __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */
-} SAI_TypeDef;
-
-typedef struct
-{
- __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */
- __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */
- __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */
- __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */
- __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */
- __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */
- __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */
- __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */
-} SAI_Block_TypeDef;
-
-/**
- * @brief SPDIF-RX Interface
- */
-
-typedef struct
-{
- __IO uint32_t CR; /*!< Control register, Address offset: 0x00 */
- __IO uint32_t IMR; /*!< Interrupt mask register, Address offset: 0x04 */
- __IO uint32_t SR; /*!< Status register, Address offset: 0x08 */
- __IO uint32_t IFCR; /*!< Interrupt Flag Clear register, Address offset: 0x0C */
- __IO uint32_t DR; /*!< Data input register, Address offset: 0x10 */
- __IO uint32_t CSR; /*!< Channel Status register, Address offset: 0x14 */
- __IO uint32_t DIR; /*!< Debug Information register, Address offset: 0x18 */
- uint32_t RESERVED2; /*!< Reserved, 0x1A */
-} SPDIFRX_TypeDef;
-
-
-/**
- * @brief Secure digital input/output Interface
- */
-
-typedef struct
-{
- __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */
- __IO uint32_t CLKCR; /*!< SDMMC clock control register, Address offset: 0x04 */
- __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */
- __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */
- __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */
- __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */
- __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */
- __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */
- __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */
- __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */
- __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */
- __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */
- __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */
- __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */
- __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */
- __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */
- __IO uint32_t ACKTIME; /*!< SDMMC Acknowledgement timer register, Address offset: 0x40 */
- uint32_t RESERVED0[3]; /*!< Reserved, 0x44 - 0x4C - 0x4C */
- __IO uint32_t IDMACTRL; /*!< SDMMC DMA control register, Address offset: 0x50 */
- __IO uint32_t IDMABSIZE; /*!< SDMMC DMA buffer size register, Address offset: 0x54 */
- __IO uint32_t IDMABASE0; /*!< SDMMC DMA buffer 0 base address register, Address offset: 0x58 */
- __IO uint32_t IDMABASE1; /*!< SDMMC DMA buffer 1 base address register, Address offset: 0x5C */
- uint32_t RESERVED1[8]; /*!< Reserved, 0x60-0x7C */
- __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */
- uint32_t RESERVED2[222]; /*!< Reserved, 0x84-0x3F8 */
- __IO uint32_t IPVR; /*!< SDMMC data FIFO register, Address offset: 0x3FC */
-} SDMMC_TypeDef;
-
-
-/**
- * @brief Delay Block DLYB
- */
-
-typedef struct
-{
- __IO uint32_t CR; /*!< DELAY BLOCK control register, Address offset: 0x00 */
- __IO uint32_t CFGR; /*!< DELAY BLOCK configuration register, Address offset: 0x04 */
-} DLYB_TypeDef;
-
-/**
- * @brief HW Semaphore HSEM
- */
-
-typedef struct
-{
- __IO uint32_t R[32]; /*!< 2-step write lock and read back registers, Address offset: 00h-7Ch */
- __IO uint32_t RLR[32]; /*!< 1-step read lock registers, Address offset: 80h-FCh */
- __IO uint32_t C1IER; /*!< HSEM Interrupt enable register , Address offset: 100h */
- __IO uint32_t C1ICR; /*!< HSEM Interrupt clear register , Address offset: 104h */
- __IO uint32_t C1ISR; /*!< HSEM Interrupt Status register , Address offset: 108h */
- __IO uint32_t C1MISR; /*!< HSEM Interrupt Masked Status register , Address offset: 10Ch */
- uint32_t Reserved[12]; /* Reserved Address offset: 110h-13Ch */
- __IO uint32_t CR; /*!< HSEM Semaphore clear register , Address offset: 140h */
- __IO uint32_t KEYR; /*!< HSEM Semaphore clear key register , Address offset: 144h */
-
-} HSEM_TypeDef;
-
-typedef struct
-{
- __IO uint32_t IER; /*!< HSEM interrupt enable register , Address offset: 0h */
- __IO uint32_t ICR; /*!< HSEM interrupt clear register , Address offset: 4h */
- __IO uint32_t ISR; /*!< HSEM interrupt status register , Address offset: 8h */
- __IO uint32_t MISR; /*!< HSEM masked interrupt status register , Address offset: Ch */
-} HSEM_Common_TypeDef;
-
-/**
- * @brief Serial Peripheral Interface
- */
-
-typedef struct
-{
- __IO uint32_t CR1; /*!< SPI/I2S Control register 1, Address offset: 0x00 */
- __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
- __IO uint32_t CFG1; /*!< SPI Configuration register 1, Address offset: 0x08 */
- __IO uint32_t CFG2; /*!< SPI Configuration register 2, Address offset: 0x0C */
- __IO uint32_t IER; /*!< SPI/I2S Interrupt Enable register, Address offset: 0x10 */
- __IO uint32_t SR; /*!< SPI/I2S Status register, Address offset: 0x14 */
- __IO uint32_t IFCR; /*!< SPI/I2S Interrupt/Status flags clear register, Address offset: 0x18 */
- uint32_t RESERVED0; /*!< Reserved, 0x1C */
- __IO uint32_t TXDR; /*!< SPI/I2S Transmit data register, Address offset: 0x20 */
- uint32_t RESERVED1[3]; /*!< Reserved, 0x24-0x2C */
- __IO uint32_t RXDR; /*!< SPI/I2S Receive data register, Address offset: 0x30 */
- uint32_t RESERVED2[3]; /*!< Reserved, 0x34-0x3C */
- __IO uint32_t CRCPOLY; /*!< SPI CRC Polynomial register, Address offset: 0x40 */
- __IO uint32_t TXCRC; /*!< SPI Transmitter CRC register, Address offset: 0x44 */
- __IO uint32_t RXCRC; /*!< SPI Receiver CRC register, Address offset: 0x48 */
- __IO uint32_t UDRDR; /*!< SPI Underrun data register, Address offset: 0x4C */
- __IO uint32_t I2SCFGR; /*!< I2S Configuration register, Address offset: 0x50 */
-
-} SPI_TypeDef;
-/**
- * @brief QUAD Serial Peripheral Interface
- */
-
-typedef struct
-{
- __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */
- __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */
- __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */
- __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */
- __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */
- __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */
- __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */
- __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */
- __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */
- __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */
- __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */
- __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */
- __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */
-} QUADSPI_TypeDef;
-
-/**
- * @brief TIM
- */
-
-typedef struct
-{
- __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
- __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
- __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
- __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
- __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
- __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
- __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
- __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
- __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
- __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
- __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
- __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
- __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
- __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
- __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
- __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
- __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
- __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
- __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
- __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
- uint32_t RESERVED1; /*!< Reserved, 0x50 */
- __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */
- __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */
- __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */
- __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */
- __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */
- __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x68 */
-} TIM_TypeDef;
-
-/**
- * @brief LPTIMIMER
- */
-typedef struct
-{
- __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
- __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
- __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
- __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
- __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
- __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
- __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
- __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
- uint32_t RESERVED1; /*!< Reserved, 0x20 */
- __IO uint32_t CFGR2; /*!< LPTIM Configuration register, Address offset: 0x24 */
-} LPTIM_TypeDef;
-
-/**
- * @brief Comparator
- */
-typedef struct
-{
- __IO uint32_t SR; /*!< Comparator status register, Address offset: 0x00 */
- __IO uint32_t ICFR; /*!< Comparator interrupt clear flag register, Address offset: 0x04 */
- __IO uint32_t OR; /*!< Comparator option register, Address offset: 0x08 */
-} COMPOPT_TypeDef;
-
-typedef struct
-{
- __IO uint32_t CFGR; /*!< Comparator configuration register , Address offset: 0x00 */
-} COMP_TypeDef;
-
-typedef struct
-{
- __IO uint32_t CFGR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
-} COMP_Common_TypeDef;
-/**
- * @brief Universal Synchronous Asynchronous Receiver Transmitter
- */
-
-typedef struct
-{
- __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
- __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
- __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
- __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
- __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
- __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
- __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
- __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
- __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
- __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
- __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
- __IO uint32_t PRESC; /*!< USART clock Prescaler register, Address offset: 0x2C */
-} USART_TypeDef;
-
-/**
- * @brief Single Wire Protocol Master Interface SPWMI
- */
-typedef struct
-{
- __IO uint32_t CR; /*!< SWPMI Configuration/Control register, Address offset: 0x00 */
- __IO uint32_t BRR; /*!< SWPMI bitrate register, Address offset: 0x04 */
- uint32_t RESERVED1; /*!< Reserved, 0x08 */
- __IO uint32_t ISR; /*!< SWPMI Interrupt and Status register, Address offset: 0x0C */
- __IO uint32_t ICR; /*!< SWPMI Interrupt Flag Clear register, Address offset: 0x10 */
- __IO uint32_t IER; /*!< SWPMI Interrupt Enable register, Address offset: 0x14 */
- __IO uint32_t RFL; /*!< SWPMI Receive Frame Length register, Address offset: 0x18 */
- __IO uint32_t TDR; /*!< SWPMI Transmit data register, Address offset: 0x1C */
- __IO uint32_t RDR; /*!< SWPMI Receive data register, Address offset: 0x20 */
- __IO uint32_t OR; /*!< SWPMI Option register, Address offset: 0x24 */
-} SWPMI_TypeDef;
-
-/**
- * @brief Window WATCHDOG
- */
-
-typedef struct
-{
- __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
- __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
- __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
-} WWDG_TypeDef;
-
-
-/**
- * @brief RAM_ECC_Specific_Registers
- */
-typedef struct
-{
- __IO uint32_t CR; /*!< RAMECC monitor configuration register */
- __IO uint32_t SR; /*!< RAMECC monitor status register */
- __IO uint32_t FAR; /*!< RAMECC monitor failing address register */
- __IO uint32_t FDRL; /*!< RAMECC monitor failing data low register */
- __IO uint32_t FDRH; /*!< RAMECC monitor failing data high register */
- __IO uint32_t FECR; /*!< RAMECC monitor failing ECC error code register */
-} RAMECC_MonitorTypeDef;
-
-typedef struct
-{
- __IO uint32_t IER; /*!< RAMECC interrupt enable register */
-} RAMECC_TypeDef;
-/**
- * @}
- */
-
-
-
-/**
- * @brief High resolution Timer (HRTIM)
- */
-/* HRTIM master registers definition */
-typedef struct
-{
- __IO uint32_t MCR; /*!< HRTIM Master Timer control register, Address offset: 0x00 */
- __IO uint32_t MISR; /*!< HRTIM Master Timer interrupt status register, Address offset: 0x04 */
- __IO uint32_t MICR; /*!< HRTIM Master Timer interupt clear register, Address offset: 0x08 */
- __IO uint32_t MDIER; /*!< HRTIM Master Timer DMA/interrupt enable register Address offset: 0x0C */
- __IO uint32_t MCNTR; /*!< HRTIM Master Timer counter register, Address offset: 0x10 */
- __IO uint32_t MPER; /*!< HRTIM Master Timer period register, Address offset: 0x14 */
- __IO uint32_t MREP; /*!< HRTIM Master Timer repetition register, Address offset: 0x18 */
- __IO uint32_t MCMP1R; /*!< HRTIM Master Timer compare 1 register, Address offset: 0x1C */
- uint32_t RESERVED0; /*!< Reserved, 0x20 */
- __IO uint32_t MCMP2R; /*!< HRTIM Master Timer compare 2 register, Address offset: 0x24 */
- __IO uint32_t MCMP3R; /*!< HRTIM Master Timer compare 3 register, Address offset: 0x28 */
- __IO uint32_t MCMP4R; /*!< HRTIM Master Timer compare 4 register, Address offset: 0x2C */
- uint32_t RESERVED1[20]; /*!< Reserved, 0x30..0x7C */
-}HRTIM_Master_TypeDef;
-
-/* HRTIM Timer A to E registers definition */
-typedef struct
-{
- __IO uint32_t TIMxCR; /*!< HRTIM Timerx control register, Address offset: 0x00 */
- __IO uint32_t TIMxISR; /*!< HRTIM Timerx interrupt status register, Address offset: 0x04 */
- __IO uint32_t TIMxICR; /*!< HRTIM Timerx interrupt clear register, Address offset: 0x08 */
- __IO uint32_t TIMxDIER; /*!< HRTIM Timerx DMA/interrupt enable register, Address offset: 0x0C */
- __IO uint32_t CNTxR; /*!< HRTIM Timerx counter register, Address offset: 0x10 */
- __IO uint32_t PERxR; /*!< HRTIM Timerx period register, Address offset: 0x14 */
- __IO uint32_t REPxR; /*!< HRTIM Timerx repetition register, Address offset: 0x18 */
- __IO uint32_t CMP1xR; /*!< HRTIM Timerx compare 1 register, Address offset: 0x1C */
- __IO uint32_t CMP1CxR; /*!< HRTIM Timerx compare 1 compound register, Address offset: 0x20 */
- __IO uint32_t CMP2xR; /*!< HRTIM Timerx compare 2 register, Address offset: 0x24 */
- __IO uint32_t CMP3xR; /*!< HRTIM Timerx compare 3 register, Address offset: 0x28 */
- __IO uint32_t CMP4xR; /*!< HRTIM Timerx compare 4 register, Address offset: 0x2C */
- __IO uint32_t CPT1xR; /*!< HRTIM Timerx capture 1 register, Address offset: 0x30 */
- __IO uint32_t CPT2xR; /*!< HRTIM Timerx capture 2 register, Address offset: 0x34 */
- __IO uint32_t DTxR; /*!< HRTIM Timerx dead time register, Address offset: 0x38 */
- __IO uint32_t SETx1R; /*!< HRTIM Timerx output 1 set register, Address offset: 0x3C */
- __IO uint32_t RSTx1R; /*!< HRTIM Timerx output 1 reset register, Address offset: 0x40 */
- __IO uint32_t SETx2R; /*!< HRTIM Timerx output 2 set register, Address offset: 0x44 */
- __IO uint32_t RSTx2R; /*!< HRTIM Timerx output 2 reset register, Address offset: 0x48 */
- __IO uint32_t EEFxR1; /*!< HRTIM Timerx external event filtering 1 register, Address offset: 0x4C */
- __IO uint32_t EEFxR2; /*!< HRTIM Timerx external event filtering 2 register, Address offset: 0x50 */
- __IO uint32_t RSTxR; /*!< HRTIM Timerx Reset register, Address offset: 0x54 */
- __IO uint32_t CHPxR; /*!< HRTIM Timerx Chopper register, Address offset: 0x58 */
- __IO uint32_t CPT1xCR; /*!< HRTIM Timerx Capture 1 register, Address offset: 0x5C */
- __IO uint32_t CPT2xCR; /*!< HRTIM Timerx Capture 2 register, Address offset: 0x60 */
- __IO uint32_t OUTxR; /*!< HRTIM Timerx Output register, Address offset: 0x64 */
- __IO uint32_t FLTxR; /*!< HRTIM Timerx Fault register, Address offset: 0x68 */
- uint32_t RESERVED0[5]; /*!< Reserved, 0x6C..0x7C */
-}HRTIM_Timerx_TypeDef;
-
-/* HRTIM common register definition */
-typedef struct
-{
- __IO uint32_t CR1; /*!< HRTIM control register1, Address offset: 0x00 */
- __IO uint32_t CR2; /*!< HRTIM control register2, Address offset: 0x04 */
- __IO uint32_t ISR; /*!< HRTIM interrupt status register, Address offset: 0x08 */
- __IO uint32_t ICR; /*!< HRTIM interrupt clear register, Address offset: 0x0C */
- __IO uint32_t IER; /*!< HRTIM interrupt enable register, Address offset: 0x10 */
- __IO uint32_t OENR; /*!< HRTIM Output enable register, Address offset: 0x14 */
- __IO uint32_t ODISR; /*!< HRTIM Output disable register, Address offset: 0x18 */
- __IO uint32_t ODSR; /*!< HRTIM Output disable status register, Address offset: 0x1C */
- __IO uint32_t BMCR; /*!< HRTIM Burst mode control register, Address offset: 0x20 */
- __IO uint32_t BMTRGR; /*!< HRTIM Busrt mode trigger register, Address offset: 0x24 */
- __IO uint32_t BMCMPR; /*!< HRTIM Burst mode compare register, Address offset: 0x28 */
- __IO uint32_t BMPER; /*!< HRTIM Burst mode period register, Address offset: 0x2C */
- __IO uint32_t EECR1; /*!< HRTIM Timer external event control register1, Address offset: 0x30 */
- __IO uint32_t EECR2; /*!< HRTIM Timer external event control register2, Address offset: 0x34 */
- __IO uint32_t EECR3; /*!< HRTIM Timer external event control register3, Address offset: 0x38 */
- __IO uint32_t ADC1R; /*!< HRTIM ADC Trigger 1 register, Address offset: 0x3C */
- __IO uint32_t ADC2R; /*!< HRTIM ADC Trigger 2 register, Address offset: 0x40 */
- __IO uint32_t ADC3R; /*!< HRTIM ADC Trigger 3 register, Address offset: 0x44 */
- __IO uint32_t ADC4R; /*!< HRTIM ADC Trigger 4 register, Address offset: 0x48 */
- __IO uint32_t RESERVED0; /*!< Reserved, Address offset: 0x4C */
- __IO uint32_t FLTINR1; /*!< HRTIM Fault input register1, Address offset: 0x50 */
- __IO uint32_t FLTINR2; /*!< HRTIM Fault input register2, Address offset: 0x54 */
- __IO uint32_t BDMUPR; /*!< HRTIM Burst DMA Master Timer update register, Address offset: 0x58 */
- __IO uint32_t BDTAUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x5C */
- __IO uint32_t BDTBUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x60 */
- __IO uint32_t BDTCUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x64 */
- __IO uint32_t BDTDUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x68 */
- __IO uint32_t BDTEUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x6C */
- __IO uint32_t BDMADR; /*!< HRTIM Burst DMA Master Data register, Address offset: 0x70 */
-}HRTIM_Common_TypeDef;
-
-/* HRTIM register definition */
-typedef struct {
- HRTIM_Master_TypeDef sMasterRegs;
- HRTIM_Timerx_TypeDef sTimerxRegs[5];
- uint32_t RESERVED0[32];
- HRTIM_Common_TypeDef sCommonRegs;
-}HRTIM_TypeDef;
-/**
- * @brief RNG
- */
-
-typedef struct
-{
- __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
- __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
- __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
-} RNG_TypeDef;
-
-/**
- * @brief MDIOS
- */
-
-typedef struct
-{
- __IO uint32_t CR;
- __IO uint32_t WRFR;
- __IO uint32_t CWRFR;
- __IO uint32_t RDFR;
- __IO uint32_t CRDFR;
- __IO uint32_t SR;
- __IO uint32_t CLRFR;
- uint32_t RESERVED[57];
- __IO uint32_t DINR0;
- __IO uint32_t DINR1;
- __IO uint32_t DINR2;
- __IO uint32_t DINR3;
- __IO uint32_t DINR4;
- __IO uint32_t DINR5;
- __IO uint32_t DINR6;
- __IO uint32_t DINR7;
- __IO uint32_t DINR8;
- __IO uint32_t DINR9;
- __IO uint32_t DINR10;
- __IO uint32_t DINR11;
- __IO uint32_t DINR12;
- __IO uint32_t DINR13;
- __IO uint32_t DINR14;
- __IO uint32_t DINR15;
- __IO uint32_t DINR16;
- __IO uint32_t DINR17;
- __IO uint32_t DINR18;
- __IO uint32_t DINR19;
- __IO uint32_t DINR20;
- __IO uint32_t DINR21;
- __IO uint32_t DINR22;
- __IO uint32_t DINR23;
- __IO uint32_t DINR24;
- __IO uint32_t DINR25;
- __IO uint32_t DINR26;
- __IO uint32_t DINR27;
- __IO uint32_t DINR28;
- __IO uint32_t DINR29;
- __IO uint32_t DINR30;
- __IO uint32_t DINR31;
- __IO uint32_t DOUTR0;
- __IO uint32_t DOUTR1;
- __IO uint32_t DOUTR2;
- __IO uint32_t DOUTR3;
- __IO uint32_t DOUTR4;
- __IO uint32_t DOUTR5;
- __IO uint32_t DOUTR6;
- __IO uint32_t DOUTR7;
- __IO uint32_t DOUTR8;
- __IO uint32_t DOUTR9;
- __IO uint32_t DOUTR10;
- __IO uint32_t DOUTR11;
- __IO uint32_t DOUTR12;
- __IO uint32_t DOUTR13;
- __IO uint32_t DOUTR14;
- __IO uint32_t DOUTR15;
- __IO uint32_t DOUTR16;
- __IO uint32_t DOUTR17;
- __IO uint32_t DOUTR18;
- __IO uint32_t DOUTR19;
- __IO uint32_t DOUTR20;
- __IO uint32_t DOUTR21;
- __IO uint32_t DOUTR22;
- __IO uint32_t DOUTR23;
- __IO uint32_t DOUTR24;
- __IO uint32_t DOUTR25;
- __IO uint32_t DOUTR26;
- __IO uint32_t DOUTR27;
- __IO uint32_t DOUTR28;
- __IO uint32_t DOUTR29;
- __IO uint32_t DOUTR30;
- __IO uint32_t DOUTR31;
-} MDIOS_TypeDef;
-
-
-/**
- * @brief USB_OTG_Core_Registers
- */
-typedef struct
-{
- __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */
- __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */
- __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */
- __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */
- __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */
- __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */
- __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */
- __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */
- __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */
- __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */
- __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */
- __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */
- uint32_t Reserved30[2]; /*!< Reserved 030h */
- __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */
- __IO uint32_t CID; /*!< User ID Register 03Ch */
- __IO uint32_t GSNPSID; /* USB_OTG core ID 040h*/
- __IO uint32_t GHWCFG1; /* User HW config1 044h*/
- __IO uint32_t GHWCFG2; /* User HW config2 048h*/
- __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */
- uint32_t Reserved6; /*!< Reserved 050h */
- __IO uint32_t GLPMCFG; /*!< LPM Register 054h */
- __IO uint32_t GPWRDN; /*!< Power Down Register 058h */
- __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */
- __IO uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register 60Ch */
- uint32_t Reserved43[39]; /*!< Reserved 058h-0FFh */
- __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */
- __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
-} USB_OTG_GlobalTypeDef;
-
-
-/**
- * @brief USB_OTG_device_Registers
- */
-typedef struct
-{
- __IO uint32_t DCFG; /*!< dev Configuration Register 800h */
- __IO uint32_t DCTL; /*!< dev Control Register 804h */
- __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */
- uint32_t Reserved0C; /*!< Reserved 80Ch */
- __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */
- __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */
- __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */
- __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */
- uint32_t Reserved20; /*!< Reserved 820h */
- uint32_t Reserved9; /*!< Reserved 824h */
- __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */
- __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */
- __IO uint32_t DTHRCTL; /*!< dev threshold 830h */
- __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */
- __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */
- __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */
- uint32_t Reserved40; /*!< dedicated EP mask 840h */
- __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */
- uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */
- __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */
-} USB_OTG_DeviceTypeDef;
-
-
-/**
- * @brief USB_OTG_IN_Endpoint-Specific_Register
- */
-typedef struct
-{
- __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
- uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */
- __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
- uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */
- __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
- __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
- __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
- uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
-} USB_OTG_INEndpointTypeDef;
-
-
-/**
- * @brief USB_OTG_OUT_Endpoint-Specific_Registers
- */
-typedef struct
-{
- __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */
- uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */
- __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */
- uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */
- __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */
- __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */
- uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
-} USB_OTG_OUTEndpointTypeDef;
-
-
-/**
- * @brief USB_OTG_Host_Mode_Register_Structures
- */
-typedef struct
-{
- __IO uint32_t HCFG; /*!< Host Configuration Register 400h */
- __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */
- __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */
- uint32_t Reserved40C; /*!< Reserved 40Ch */
- __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */
- __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */
- __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */
-} USB_OTG_HostTypeDef;
-
-/**
- * @brief USB_OTG_Host_Channel_Specific_Registers
- */
-typedef struct
-{
- __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */
- __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */
- __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */
- __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */
- __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */
- __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */
- uint32_t Reserved[2]; /*!< Reserved */
-} USB_OTG_HostChannelTypeDef;
-/**
- * @}
- */
-
-
-/** @addtogroup Peripheral_memory_map
- * @{
- */
-#define D1_ITCMRAM_BASE (0x00000000UL) /*!< Base address of : 64KB RAM reserved for CPU execution/instruction accessible over ITCM */
-#define D1_ITCMICP_BASE (0x00100000UL) /*!< Base address of : (up to 128KB) embedded Test FLASH memory accessible over ITCM */
-#define D1_DTCMRAM_BASE (0x20000000UL) /*!< Base address of : 128KB system data RAM accessible over DTCM */
-#define D1_AXIFLASH_BASE (0x08000000UL) /*!< Base address of : (up to 2 MB) embedded FLASH memory accessible over AXI */
-#define D1_AXIICP_BASE (0x1FF00000UL) /*!< Base address of : (up to 128KB) embedded Test FLASH memory accessible over AXI */
-#define D1_AXISRAM_BASE (0x24000000UL) /*!< Base address of : (up to 512KB) system data RAM accessible over over AXI */
-
-#define D2_AXISRAM_BASE (0x10000000UL) /*!< Base address of : (up to 288KB) system data RAM accessible over over AXI */
-#define D2_AHBSRAM_BASE (0x30000000UL) /*!< Base address of : (up to 288KB) system data RAM accessible over over AXI->AHB Bridge */
-
-#define D3_BKPSRAM_BASE (0x38800000UL) /*!< Base address of : Backup SRAM(4 KB) over AXI->AHB Bridge */
-#define D3_SRAM_BASE (0x38000000UL) /*!< Base address of : Backup SRAM(64 KB) over AXI->AHB Bridge */
-
-#define PERIPH_BASE (0x40000000UL) /*!< Base address of : AHB/APB Peripherals */
-#define QSPI_BASE (0x90000000UL) /*!< Base address of : QSPI memories accessible over AXI */
-
-#define FLASH_BANK1_BASE (0x08000000UL) /*!< Base address of : (up to 1 MB) Flash Bank1 accessible over AXI */
-#define FLASH_BANK2_BASE (0x08100000UL) /*!< Base address of : (up to 1 MB) Flash Bank2 accessible over AXI */
-#define FLASH_END (0x081FFFFFUL) /*!< FLASH end address */
-
-/* Legacy define */
-#define FLASH_BASE FLASH_BANK1_BASE
-
-/*!< Device electronic signature memory map */
-#define UID_BASE (0x1FF1E800UL) /*!< Unique device ID register base address */
-#define FLASHSIZE_BASE (0x1FF1E880UL) /*!< FLASH Size register base address */
-
-
-/*!< Peripheral memory map */
-#define D2_APB1PERIPH_BASE PERIPH_BASE
-#define D2_APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)
-#define D2_AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL)
-#define D2_AHB2PERIPH_BASE (PERIPH_BASE + 0x08020000UL)
-
-#define D1_APB1PERIPH_BASE (PERIPH_BASE + 0x10000000UL)
-#define D1_AHB1PERIPH_BASE (PERIPH_BASE + 0x12000000UL)
-
-#define D3_APB1PERIPH_BASE (PERIPH_BASE + 0x18000000UL)
-#define D3_AHB1PERIPH_BASE (PERIPH_BASE + 0x18020000UL)
-
-/*!< Legacy Peripheral memory map */
-#define APB1PERIPH_BASE PERIPH_BASE
-#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)
-#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL)
-#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL)
-
-
-/*!< D1_AHB1PERIPH peripherals */
-
-#define MDMA_BASE (D1_AHB1PERIPH_BASE + 0x0000UL)
-#define DMA2D_BASE (D1_AHB1PERIPH_BASE + 0x1000UL)
-#define JPGDEC_BASE (D1_AHB1PERIPH_BASE + 0x3000UL)
-#define FLASH_R_BASE (D1_AHB1PERIPH_BASE + 0x2000UL)
-#define FMC_R_BASE (D1_AHB1PERIPH_BASE + 0x4000UL)
-#define QSPI_R_BASE (D1_AHB1PERIPH_BASE + 0x5000UL)
-#define DLYB_QSPI_BASE (D1_AHB1PERIPH_BASE + 0x6000UL)
-#define SDMMC1_BASE (D1_AHB1PERIPH_BASE + 0x7000UL)
-#define DLYB_SDMMC1_BASE (D1_AHB1PERIPH_BASE + 0x8000UL)
-#define RAMECC1_BASE (D1_AHB1PERIPH_BASE + 0x9000UL)
-
-/*!< D2_AHB1PERIPH peripherals */
-
-#define DMA1_BASE (D2_AHB1PERIPH_BASE + 0x0000UL)
-#define DMA2_BASE (D2_AHB1PERIPH_BASE + 0x0400UL)
-#define DMAMUX1_BASE (D2_AHB1PERIPH_BASE + 0x0800UL)
-#define ADC1_BASE (D2_AHB1PERIPH_BASE + 0x2000UL)
-#define ADC2_BASE (D2_AHB1PERIPH_BASE + 0x2100UL)
-#define ADC12_COMMON_BASE (D2_AHB1PERIPH_BASE + 0x2300UL)
-#define ETH_BASE (D2_AHB1PERIPH_BASE + 0x8000UL)
-#define ETH_MAC_BASE (ETH_BASE)
-
-/*!< USB registers base address */
-#define USB1_OTG_HS_PERIPH_BASE (0x40040000UL)
-#define USB2_OTG_FS_PERIPH_BASE (0x40080000UL)
-#define USB_OTG_GLOBAL_BASE (0x000UL)
-#define USB_OTG_DEVICE_BASE (0x800UL)
-#define USB_OTG_IN_ENDPOINT_BASE (0x900UL)
-#define USB_OTG_OUT_ENDPOINT_BASE (0xB00UL)
-#define USB_OTG_EP_REG_SIZE (0x20UL)
-#define USB_OTG_HOST_BASE (0x400UL)
-#define USB_OTG_HOST_PORT_BASE (0x440UL)
-#define USB_OTG_HOST_CHANNEL_BASE (0x500UL)
-#define USB_OTG_HOST_CHANNEL_SIZE (0x20UL)
-#define USB_OTG_PCGCCTL_BASE (0xE00UL)
-#define USB_OTG_FIFO_BASE (0x1000UL)
-#define USB_OTG_FIFO_SIZE (0x1000UL)
-
-/*!< D2_AHB2PERIPH peripherals */
-
-#define DCMI_BASE (D2_AHB2PERIPH_BASE + 0x0000UL)
-#define RNG_BASE (D2_AHB2PERIPH_BASE + 0x1800UL)
-#define SDMMC2_BASE (D2_AHB2PERIPH_BASE + 0x2400UL)
-#define DLYB_SDMMC2_BASE (D2_AHB2PERIPH_BASE + 0x2800UL)
-#define RAMECC2_BASE (D2_AHB2PERIPH_BASE + 0x3000UL)
-
-/*!< D3_AHB1PERIPH peripherals */
-#define GPIOA_BASE (D3_AHB1PERIPH_BASE + 0x0000UL)
-#define GPIOB_BASE (D3_AHB1PERIPH_BASE + 0x0400UL)
-#define GPIOC_BASE (D3_AHB1PERIPH_BASE + 0x0800UL)
-#define GPIOD_BASE (D3_AHB1PERIPH_BASE + 0x0C00UL)
-#define GPIOE_BASE (D3_AHB1PERIPH_BASE + 0x1000UL)
-#define GPIOF_BASE (D3_AHB1PERIPH_BASE + 0x1400UL)
-#define GPIOG_BASE (D3_AHB1PERIPH_BASE + 0x1800UL)
-#define GPIOH_BASE (D3_AHB1PERIPH_BASE + 0x1C00UL)
-#define GPIOI_BASE (D3_AHB1PERIPH_BASE + 0x2000UL)
-#define GPIOJ_BASE (D3_AHB1PERIPH_BASE + 0x2400UL)
-#define GPIOK_BASE (D3_AHB1PERIPH_BASE + 0x2800UL)
-#define RCC_BASE (D3_AHB1PERIPH_BASE + 0x4400UL)
-#define PWR_BASE (D3_AHB1PERIPH_BASE + 0x4800UL)
-#define CRC_BASE (D3_AHB1PERIPH_BASE + 0x4C00UL)
-#define BDMA_BASE (D3_AHB1PERIPH_BASE + 0x5400UL)
-#define DMAMUX2_BASE (D3_AHB1PERIPH_BASE + 0x5800UL)
-#define ADC3_BASE (D3_AHB1PERIPH_BASE + 0x6000UL)
-#define ADC3_COMMON_BASE (D3_AHB1PERIPH_BASE + 0x6300UL)
-#define HSEM_BASE (D3_AHB1PERIPH_BASE + 0x6400UL)
-#define RAMECC3_BASE (D3_AHB1PERIPH_BASE + 0x7000UL)
-
-/*!< D1_APB1PERIPH peripherals */
-#define LTDC_BASE (D1_APB1PERIPH_BASE + 0x1000UL)
-#define LTDC_Layer1_BASE (LTDC_BASE + 0x84UL)
-#define LTDC_Layer2_BASE (LTDC_BASE + 0x104UL)
-#define WWDG1_BASE (D1_APB1PERIPH_BASE + 0x3000UL)
-
-/*!< D2_APB1PERIPH peripherals */
-#define TIM2_BASE (D2_APB1PERIPH_BASE + 0x0000UL)
-#define TIM3_BASE (D2_APB1PERIPH_BASE + 0x0400UL)
-#define TIM4_BASE (D2_APB1PERIPH_BASE + 0x0800UL)
-#define TIM5_BASE (D2_APB1PERIPH_BASE + 0x0C00UL)
-#define TIM6_BASE (D2_APB1PERIPH_BASE + 0x1000UL)
-#define TIM7_BASE (D2_APB1PERIPH_BASE + 0x1400UL)
-#define TIM12_BASE (D2_APB1PERIPH_BASE + 0x1800UL)
-#define TIM13_BASE (D2_APB1PERIPH_BASE + 0x1C00UL)
-#define TIM14_BASE (D2_APB1PERIPH_BASE + 0x2000UL)
-#define LPTIM1_BASE (D2_APB1PERIPH_BASE + 0x2400UL)
-
-
-#define SPI2_BASE (D2_APB1PERIPH_BASE + 0x3800UL)
-#define SPI3_BASE (D2_APB1PERIPH_BASE + 0x3C00UL)
-#define SPDIFRX_BASE (D2_APB1PERIPH_BASE + 0x4000UL)
-#define USART2_BASE (D2_APB1PERIPH_BASE + 0x4400UL)
-#define USART3_BASE (D2_APB1PERIPH_BASE + 0x4800UL)
-#define UART4_BASE (D2_APB1PERIPH_BASE + 0x4C00UL)
-#define UART5_BASE (D2_APB1PERIPH_BASE + 0x5000UL)
-#define I2C1_BASE (D2_APB1PERIPH_BASE + 0x5400UL)
-#define I2C2_BASE (D2_APB1PERIPH_BASE + 0x5800UL)
-#define I2C3_BASE (D2_APB1PERIPH_BASE + 0x5C00UL)
-#define CEC_BASE (D2_APB1PERIPH_BASE + 0x6C00UL)
-#define DAC1_BASE (D2_APB1PERIPH_BASE + 0x7400UL)
-#define UART7_BASE (D2_APB1PERIPH_BASE + 0x7800UL)
-#define UART8_BASE (D2_APB1PERIPH_BASE + 0x7C00UL)
-#define CRS_BASE (D2_APB1PERIPH_BASE + 0x8400UL)
-#define SWPMI1_BASE (D2_APB1PERIPH_BASE + 0x8800UL)
-#define OPAMP_BASE (D2_APB1PERIPH_BASE + 0x9000UL)
-#define OPAMP1_BASE (D2_APB1PERIPH_BASE + 0x9000UL)
-#define OPAMP2_BASE (D2_APB1PERIPH_BASE + 0x9010UL)
-#define MDIOS_BASE (D2_APB1PERIPH_BASE + 0x9400UL)
-#define FDCAN1_BASE (D2_APB1PERIPH_BASE + 0xA000UL)
-#define FDCAN2_BASE (D2_APB1PERIPH_BASE + 0xA400UL)
-#define FDCAN_CCU_BASE (D2_APB1PERIPH_BASE + 0xA800UL)
-#define SRAMCAN_BASE (D2_APB1PERIPH_BASE + 0xAC00UL)
-
-/*!< D2_APB2PERIPH peripherals */
-
-#define TIM1_BASE (D2_APB2PERIPH_BASE + 0x0000UL)
-#define TIM8_BASE (D2_APB2PERIPH_BASE + 0x0400UL)
-#define USART1_BASE (D2_APB2PERIPH_BASE + 0x1000UL)
-#define USART6_BASE (D2_APB2PERIPH_BASE + 0x1400UL)
-#define SPI1_BASE (D2_APB2PERIPH_BASE + 0x3000UL)
-#define SPI4_BASE (D2_APB2PERIPH_BASE + 0x3400UL)
-#define TIM15_BASE (D2_APB2PERIPH_BASE + 0x4000UL)
-#define TIM16_BASE (D2_APB2PERIPH_BASE + 0x4400UL)
-#define TIM17_BASE (D2_APB2PERIPH_BASE + 0x4800UL)
-#define SPI5_BASE (D2_APB2PERIPH_BASE + 0x5000UL)
-#define SAI1_BASE (D2_APB2PERIPH_BASE + 0x5800UL)
-#define SAI1_Block_A_BASE (SAI1_BASE + 0x004UL)
-#define SAI1_Block_B_BASE (SAI1_BASE + 0x024UL)
-#define SAI2_BASE (D2_APB2PERIPH_BASE + 0x5C00UL)
-#define SAI2_Block_A_BASE (SAI2_BASE + 0x004UL)
-#define SAI2_Block_B_BASE (SAI2_BASE + 0x024UL)
-#define SAI3_BASE (D2_APB2PERIPH_BASE + 0x6000UL)
-#define SAI3_Block_A_BASE (SAI3_BASE + 0x004UL)
-#define SAI3_Block_B_BASE (SAI3_BASE + 0x024UL)
-#define DFSDM1_BASE (D2_APB2PERIPH_BASE + 0x7000UL)
-#define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00UL)
-#define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20UL)
-#define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40UL)
-#define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x60UL)
-#define DFSDM1_Channel4_BASE (DFSDM1_BASE + 0x80UL)
-#define DFSDM1_Channel5_BASE (DFSDM1_BASE + 0xA0UL)
-#define DFSDM1_Channel6_BASE (DFSDM1_BASE + 0xC0UL)
-#define DFSDM1_Channel7_BASE (DFSDM1_BASE + 0xE0UL)
-#define DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x100UL)
-#define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x180UL)
-#define DFSDM1_Filter2_BASE (DFSDM1_BASE + 0x200UL)
-#define DFSDM1_Filter3_BASE (DFSDM1_BASE + 0x280UL)
-#define HRTIM1_BASE (D2_APB2PERIPH_BASE + 0x7400UL)
-#define HRTIM1_TIMA_BASE (HRTIM1_BASE + 0x00000080UL)
-#define HRTIM1_TIMB_BASE (HRTIM1_BASE + 0x00000100UL)
-#define HRTIM1_TIMC_BASE (HRTIM1_BASE + 0x00000180UL)
-#define HRTIM1_TIMD_BASE (HRTIM1_BASE + 0x00000200UL)
-#define HRTIM1_TIME_BASE (HRTIM1_BASE + 0x00000280UL)
-#define HRTIM1_COMMON_BASE (HRTIM1_BASE + 0x00000380UL)
-
-
-/*!< D3_APB1PERIPH peripherals */
-#define EXTI_BASE (D3_APB1PERIPH_BASE + 0x0000UL)
-#define EXTI_D1_BASE (EXTI_BASE + 0x0080UL)
-#define EXTI_D2_BASE (EXTI_BASE + 0x00C0UL)
-#define SYSCFG_BASE (D3_APB1PERIPH_BASE + 0x0400UL)
-#define LPUART1_BASE (D3_APB1PERIPH_BASE + 0x0C00UL)
-#define SPI6_BASE (D3_APB1PERIPH_BASE + 0x1400UL)
-#define I2C4_BASE (D3_APB1PERIPH_BASE + 0x1C00UL)
-#define LPTIM2_BASE (D3_APB1PERIPH_BASE + 0x2400UL)
-#define LPTIM3_BASE (D3_APB1PERIPH_BASE + 0x2800UL)
-#define LPTIM4_BASE (D3_APB1PERIPH_BASE + 0x2C00UL)
-#define LPTIM5_BASE (D3_APB1PERIPH_BASE + 0x3000UL)
-#define COMP12_BASE (D3_APB1PERIPH_BASE + 0x3800UL)
-#define COMP1_BASE (COMP12_BASE + 0x0CUL)
-#define COMP2_BASE (COMP12_BASE + 0x10UL)
-#define VREFBUF_BASE (D3_APB1PERIPH_BASE + 0x3C00UL)
-#define RTC_BASE (D3_APB1PERIPH_BASE + 0x4000UL)
-#define IWDG1_BASE (D3_APB1PERIPH_BASE + 0x4800UL)
-
-
-#define SAI4_BASE (D3_APB1PERIPH_BASE + 0x5400UL)
-#define SAI4_Block_A_BASE (SAI4_BASE + 0x004UL)
-#define SAI4_Block_B_BASE (SAI4_BASE + 0x024UL)
-
-
-
-
-#define BDMA_Channel0_BASE (BDMA_BASE + 0x0008UL)
-#define BDMA_Channel1_BASE (BDMA_BASE + 0x001CUL)
-#define BDMA_Channel2_BASE (BDMA_BASE + 0x0030UL)
-#define BDMA_Channel3_BASE (BDMA_BASE + 0x0044UL)
-#define BDMA_Channel4_BASE (BDMA_BASE + 0x0058UL)
-#define BDMA_Channel5_BASE (BDMA_BASE + 0x006CUL)
-#define BDMA_Channel6_BASE (BDMA_BASE + 0x0080UL)
-#define BDMA_Channel7_BASE (BDMA_BASE + 0x0094UL)
-
-#define DMAMUX2_Channel0_BASE (DMAMUX2_BASE)
-#define DMAMUX2_Channel1_BASE (DMAMUX2_BASE + 0x0004UL)
-#define DMAMUX2_Channel2_BASE (DMAMUX2_BASE + 0x0008UL)
-#define DMAMUX2_Channel3_BASE (DMAMUX2_BASE + 0x000CUL)
-#define DMAMUX2_Channel4_BASE (DMAMUX2_BASE + 0x0010UL)
-#define DMAMUX2_Channel5_BASE (DMAMUX2_BASE + 0x0014UL)
-#define DMAMUX2_Channel6_BASE (DMAMUX2_BASE + 0x0018UL)
-#define DMAMUX2_Channel7_BASE (DMAMUX2_BASE + 0x001CUL)
-
-#define DMAMUX2_RequestGenerator0_BASE (DMAMUX2_BASE + 0x0100UL)
-#define DMAMUX2_RequestGenerator1_BASE (DMAMUX2_BASE + 0x0104UL)
-#define DMAMUX2_RequestGenerator2_BASE (DMAMUX2_BASE + 0x0108UL)
-#define DMAMUX2_RequestGenerator3_BASE (DMAMUX2_BASE + 0x010CUL)
-#define DMAMUX2_RequestGenerator4_BASE (DMAMUX2_BASE + 0x0110UL)
-#define DMAMUX2_RequestGenerator5_BASE (DMAMUX2_BASE + 0x0114UL)
-#define DMAMUX2_RequestGenerator6_BASE (DMAMUX2_BASE + 0x0118UL)
-#define DMAMUX2_RequestGenerator7_BASE (DMAMUX2_BASE + 0x011CUL)
-
-#define DMAMUX2_ChannelStatus_BASE (DMAMUX2_BASE + 0x0080UL)
-#define DMAMUX2_RequestGenStatus_BASE (DMAMUX2_BASE + 0x0140UL)
-
-#define DMA1_Stream0_BASE (DMA1_BASE + 0x010UL)
-#define DMA1_Stream1_BASE (DMA1_BASE + 0x028UL)
-#define DMA1_Stream2_BASE (DMA1_BASE + 0x040UL)
-#define DMA1_Stream3_BASE (DMA1_BASE + 0x058UL)
-#define DMA1_Stream4_BASE (DMA1_BASE + 0x070UL)
-#define DMA1_Stream5_BASE (DMA1_BASE + 0x088UL)
-#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0UL)
-#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8UL)
-
-#define DMA2_Stream0_BASE (DMA2_BASE + 0x010UL)
-#define DMA2_Stream1_BASE (DMA2_BASE + 0x028UL)
-#define DMA2_Stream2_BASE (DMA2_BASE + 0x040UL)
-#define DMA2_Stream3_BASE (DMA2_BASE + 0x058UL)
-#define DMA2_Stream4_BASE (DMA2_BASE + 0x070UL)
-#define DMA2_Stream5_BASE (DMA2_BASE + 0x088UL)
-#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0UL)
-#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8UL)
-
-#define DMAMUX1_Channel0_BASE (DMAMUX1_BASE)
-#define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x0004UL)
-#define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x0008UL)
-#define DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x000CUL)
-#define DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x0010UL)
-#define DMAMUX1_Channel5_BASE (DMAMUX1_BASE + 0x0014UL)
-#define DMAMUX1_Channel6_BASE (DMAMUX1_BASE + 0x0018UL)
-#define DMAMUX1_Channel7_BASE (DMAMUX1_BASE + 0x001CUL)
-#define DMAMUX1_Channel8_BASE (DMAMUX1_BASE + 0x0020UL)
-#define DMAMUX1_Channel9_BASE (DMAMUX1_BASE + 0x0024UL)
-#define DMAMUX1_Channel10_BASE (DMAMUX1_BASE + 0x0028UL)
-#define DMAMUX1_Channel11_BASE (DMAMUX1_BASE + 0x002CUL)
-#define DMAMUX1_Channel12_BASE (DMAMUX1_BASE + 0x0030UL)
-#define DMAMUX1_Channel13_BASE (DMAMUX1_BASE + 0x0034UL)
-#define DMAMUX1_Channel14_BASE (DMAMUX1_BASE + 0x0038UL)
-#define DMAMUX1_Channel15_BASE (DMAMUX1_BASE + 0x003CUL)
-
-#define DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x0100UL)
-#define DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x0104UL)
-#define DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x0108UL)
-#define DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x010CUL)
-#define DMAMUX1_RequestGenerator4_BASE (DMAMUX1_BASE + 0x0110UL)
-#define DMAMUX1_RequestGenerator5_BASE (DMAMUX1_BASE + 0x0114UL)
-#define DMAMUX1_RequestGenerator6_BASE (DMAMUX1_BASE + 0x0118UL)
-#define DMAMUX1_RequestGenerator7_BASE (DMAMUX1_BASE + 0x011CUL)
-
-#define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x0080UL)
-#define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x0140UL)
-
-/*!< FMC Banks registers base address */
-#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000UL)
-#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104UL)
-#define FMC_Bank2_R_BASE (FMC_R_BASE + 0x0060UL)
-#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080UL)
-#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140UL)
-
-/* Debug MCU registers base address */
-#define DBGMCU_BASE (0x5C001000UL)
-
-#define MDMA_Channel0_BASE (MDMA_BASE + 0x00000040UL)
-#define MDMA_Channel1_BASE (MDMA_BASE + 0x00000080UL)
-#define MDMA_Channel2_BASE (MDMA_BASE + 0x000000C0UL)
-#define MDMA_Channel3_BASE (MDMA_BASE + 0x00000100UL)
-#define MDMA_Channel4_BASE (MDMA_BASE + 0x00000140UL)
-#define MDMA_Channel5_BASE (MDMA_BASE + 0x00000180UL)
-#define MDMA_Channel6_BASE (MDMA_BASE + 0x000001C0UL)
-#define MDMA_Channel7_BASE (MDMA_BASE + 0x00000200UL)
-#define MDMA_Channel8_BASE (MDMA_BASE + 0x00000240UL)
-#define MDMA_Channel9_BASE (MDMA_BASE + 0x00000280UL)
-#define MDMA_Channel10_BASE (MDMA_BASE + 0x000002C0UL)
-#define MDMA_Channel11_BASE (MDMA_BASE + 0x00000300UL)
-#define MDMA_Channel12_BASE (MDMA_BASE + 0x00000340UL)
-#define MDMA_Channel13_BASE (MDMA_BASE + 0x00000380UL)
-#define MDMA_Channel14_BASE (MDMA_BASE + 0x000003C0UL)
-#define MDMA_Channel15_BASE (MDMA_BASE + 0x00000400UL)
-
-#define RAMECC1_Monitor1_BASE (RAMECC1_BASE + 0x20UL)
-#define RAMECC1_Monitor2_BASE (RAMECC1_BASE + 0x40UL)
-#define RAMECC1_Monitor3_BASE (RAMECC1_BASE + 0x60UL)
-#define RAMECC1_Monitor4_BASE (RAMECC1_BASE + 0x80UL)
-#define RAMECC1_Monitor5_BASE (RAMECC1_BASE + 0xA0UL)
-
-#define RAMECC2_Monitor1_BASE (RAMECC2_BASE + 0x20UL)
-#define RAMECC2_Monitor2_BASE (RAMECC2_BASE + 0x40UL)
-#define RAMECC2_Monitor3_BASE (RAMECC2_BASE + 0x60UL)
-#define RAMECC2_Monitor4_BASE (RAMECC2_BASE + 0x80UL)
-#define RAMECC2_Monitor5_BASE (RAMECC2_BASE + 0xA0UL)
-
-#define RAMECC3_Monitor1_BASE (RAMECC3_BASE + 0x20UL)
-#define RAMECC3_Monitor2_BASE (RAMECC3_BASE + 0x40UL)
-
-
-/**
- * @}
- */
-
-/** @addtogroup Peripheral_declaration
- * @{
- */
-#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
-#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
-#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
-#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
-#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
-#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
-#define TIM13 ((TIM_TypeDef *) TIM13_BASE)
-#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
-#define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE)
-#define RTC ((RTC_TypeDef *) RTC_BASE)
-#define WWDG1 ((WWDG_TypeDef *) WWDG1_BASE)
-
-
-#define IWDG1 ((IWDG_TypeDef *) IWDG1_BASE)
-#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
-#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
-#define SPI4 ((SPI_TypeDef *) SPI4_BASE)
-#define SPI5 ((SPI_TypeDef *) SPI5_BASE)
-#define SPI6 ((SPI_TypeDef *) SPI6_BASE)
-#define USART2 ((USART_TypeDef *) USART2_BASE)
-#define USART3 ((USART_TypeDef *) USART3_BASE)
-#define USART6 ((USART_TypeDef *) USART6_BASE)
-#define UART7 ((USART_TypeDef *) UART7_BASE)
-#define UART8 ((USART_TypeDef *) UART8_BASE)
-#define CRS ((CRS_TypeDef *) CRS_BASE)
-#define UART4 ((USART_TypeDef *) UART4_BASE)
-#define UART5 ((USART_TypeDef *) UART5_BASE)
-#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
-#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
-#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
-#define I2C4 ((I2C_TypeDef *) I2C4_BASE)
-#define FDCAN1 ((FDCAN_GlobalTypeDef *) FDCAN1_BASE)
-#define FDCAN2 ((FDCAN_GlobalTypeDef *) FDCAN2_BASE)
-#define FDCAN_CCU ((FDCAN_ClockCalibrationUnit_TypeDef *) FDCAN_CCU_BASE)
-#define CEC ((CEC_TypeDef *) CEC_BASE)
-#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
-#define PWR ((PWR_TypeDef *) PWR_BASE)
-#define DAC1 ((DAC_TypeDef *) DAC1_BASE)
-#define LPUART1 ((USART_TypeDef *) LPUART1_BASE)
-#define SWPMI1 ((SWPMI_TypeDef *) SWPMI1_BASE)
-#define LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE)
-#define LPTIM3 ((LPTIM_TypeDef *) LPTIM3_BASE)
-#define LPTIM4 ((LPTIM_TypeDef *) LPTIM4_BASE)
-#define LPTIM5 ((LPTIM_TypeDef *) LPTIM5_BASE)
-
-#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
-#define COMP12 ((COMPOPT_TypeDef *) COMP12_BASE)
-#define COMP1 ((COMP_TypeDef *) COMP1_BASE)
-#define COMP2 ((COMP_TypeDef *) COMP2_BASE)
-#define COMP12_COMMON ((COMP_Common_TypeDef *) COMP2_BASE)
-#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
-#define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE)
-#define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)
-
-
-#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
-#define EXTI_D1 ((EXTI_Core_TypeDef *) EXTI_D1_BASE)
-#define EXTI_D2 ((EXTI_Core_TypeDef *) EXTI_D2_BASE)
-#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
-#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
-#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
-#define USART1 ((USART_TypeDef *) USART1_BASE)
-#define TIM12 ((TIM_TypeDef *) TIM12_BASE)
-#define TIM15 ((TIM_TypeDef *) TIM15_BASE)
-#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
-#define TIM17 ((TIM_TypeDef *) TIM17_BASE)
-#define HRTIM1 ((HRTIM_TypeDef *) HRTIM1_BASE)
-#define HRTIM1_TIMA ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMA_BASE)
-#define HRTIM1_TIMB ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMB_BASE)
-#define HRTIM1_TIMC ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMC_BASE)
-#define HRTIM1_TIMD ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMD_BASE)
-#define HRTIM1_TIME ((HRTIM_Timerx_TypeDef *) HRTIM1_TIME_BASE)
-#define HRTIM1_COMMON ((HRTIM_Common_TypeDef *) HRTIM1_COMMON_BASE)
-#define SAI1 ((SAI_TypeDef *) SAI1_BASE)
-#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
-#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
-#define SAI2 ((SAI_TypeDef *) SAI2_BASE)
-#define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)
-#define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
-#define SAI3 ((SAI_TypeDef *) SAI3_BASE)
-#define SAI3_Block_A ((SAI_Block_TypeDef *)SAI3_Block_A_BASE)
-#define SAI3_Block_B ((SAI_Block_TypeDef *)SAI3_Block_B_BASE)
-#define SAI4 ((SAI_TypeDef *) SAI4_BASE)
-#define SAI4_Block_A ((SAI_Block_TypeDef *)SAI4_Block_A_BASE)
-#define SAI4_Block_B ((SAI_Block_TypeDef *)SAI4_Block_B_BASE)
-
-#define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE)
-#define DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)
-#define DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)
-#define DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)
-#define DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)
-#define DFSDM1_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE)
-#define DFSDM1_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE)
-#define DFSDM1_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE)
-#define DFSDM1_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE)
-#define DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)
-#define DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)
-#define DFSDM1_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE)
-#define DFSDM1_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE)
-#define DMA2D ((DMA2D_TypeDef *) DMA2D_BASE)
-#define DCMI ((DCMI_TypeDef *) DCMI_BASE)
-#define RCC ((RCC_TypeDef *) RCC_BASE)
-#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
-#define CRC ((CRC_TypeDef *) CRC_BASE)
-
-#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
-#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
-#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
-#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
-#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
-#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
-#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
-#define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)
-#define GPIOK ((GPIO_TypeDef *) GPIOK_BASE)
-
-#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
-#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
-#define ADC3 ((ADC_TypeDef *) ADC3_BASE)
-#define ADC3_COMMON ((ADC_Common_TypeDef *) ADC3_COMMON_BASE)
-#define ADC12_COMMON ((ADC_Common_TypeDef *) ADC12_COMMON_BASE)
-
-#define RNG ((RNG_TypeDef *) RNG_BASE)
-#define SDMMC2 ((SDMMC_TypeDef *) SDMMC2_BASE)
-#define DLYB_SDMMC2 ((DLYB_TypeDef *) DLYB_SDMMC2_BASE)
-
-#define BDMA ((BDMA_TypeDef *) BDMA_BASE)
-#define BDMA_Channel0 ((BDMA_Channel_TypeDef *) BDMA_Channel0_BASE)
-#define BDMA_Channel1 ((BDMA_Channel_TypeDef *) BDMA_Channel1_BASE)
-#define BDMA_Channel2 ((BDMA_Channel_TypeDef *) BDMA_Channel2_BASE)
-#define BDMA_Channel3 ((BDMA_Channel_TypeDef *) BDMA_Channel3_BASE)
-#define BDMA_Channel4 ((BDMA_Channel_TypeDef *) BDMA_Channel4_BASE)
-#define BDMA_Channel5 ((BDMA_Channel_TypeDef *) BDMA_Channel5_BASE)
-#define BDMA_Channel6 ((BDMA_Channel_TypeDef *) BDMA_Channel6_BASE)
-#define BDMA_Channel7 ((BDMA_Channel_TypeDef *) BDMA_Channel7_BASE)
-
-#define RAMECC1 ((RAMECC_TypeDef *)RAMECC1_BASE)
-#define RAMECC1_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor1_BASE)
-#define RAMECC1_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor2_BASE)
-#define RAMECC1_Monitor3 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor3_BASE)
-#define RAMECC1_Monitor4 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor4_BASE)
-#define RAMECC1_Monitor5 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor5_BASE)
-
-#define RAMECC2 ((RAMECC_TypeDef *)RAMECC2_BASE)
-#define RAMECC2_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor1_BASE)
-#define RAMECC2_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor2_BASE)
-#define RAMECC2_Monitor3 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor3_BASE)
-#define RAMECC2_Monitor4 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor4_BASE)
-#define RAMECC2_Monitor5 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor5_BASE)
-
-#define RAMECC3 ((RAMECC_TypeDef *)RAMECC3_BASE)
-#define RAMECC3_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor1_BASE)
-#define RAMECC3_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor2_BASE)
-
-#define DMAMUX2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_BASE)
-#define DMAMUX2_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel0_BASE)
-#define DMAMUX2_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel1_BASE)
-#define DMAMUX2_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel2_BASE)
-#define DMAMUX2_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel3_BASE)
-#define DMAMUX2_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel4_BASE)
-#define DMAMUX2_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel5_BASE)
-#define DMAMUX2_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel6_BASE)
-#define DMAMUX2_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel7_BASE)
-
-
-#define DMAMUX2_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator0_BASE)
-#define DMAMUX2_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator1_BASE)
-#define DMAMUX2_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator2_BASE)
-#define DMAMUX2_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator3_BASE)
-#define DMAMUX2_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator4_BASE)
-#define DMAMUX2_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator5_BASE)
-#define DMAMUX2_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator6_BASE)
-#define DMAMUX2_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator7_BASE)
-
-#define DMAMUX2_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX2_ChannelStatus_BASE)
-#define DMAMUX2_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX2_RequestGenStatus_BASE)
-
-#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
-#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
-#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
-#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
-#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
-#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
-#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
-#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
-#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
-
-#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
-#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
-#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
-#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
-#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
-#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
-#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
-#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
-#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
-
-
-#define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)
-#define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)
-#define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)
-#define DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE)
-#define DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE)
-#define DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE)
-#define DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE)
-#define DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE)
-#define DMAMUX1_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE)
-#define DMAMUX1_Channel8 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE)
-#define DMAMUX1_Channel9 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE)
-#define DMAMUX1_Channel10 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE)
-#define DMAMUX1_Channel11 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE)
-#define DMAMUX1_Channel12 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE)
-#define DMAMUX1_Channel13 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE)
-#define DMAMUX1_Channel14 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel14_BASE)
-#define DMAMUX1_Channel15 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel15_BASE)
-
-#define DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE)
-#define DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE)
-#define DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE)
-#define DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE)
-#define DMAMUX1_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator4_BASE)
-#define DMAMUX1_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator5_BASE)
-#define DMAMUX1_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator6_BASE)
-#define DMAMUX1_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator7_BASE)
-
-#define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE)
-#define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)
-
-
-#define FMC_Bank1_R ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
-#define FMC_Bank1E_R ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
-#define FMC_Bank2_R ((FMC_Bank2_TypeDef *) FMC_Bank2_R_BASE)
-#define FMC_Bank3_R ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
-#define FMC_Bank5_6_R ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
-
-
-#define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
-#define DLYB_QUADSPI ((DLYB_TypeDef *) DLYB_QSPI_BASE)
-#define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE)
-#define DLYB_SDMMC1 ((DLYB_TypeDef *) DLYB_SDMMC1_BASE)
-
-#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
-
-#define JPEG ((JPEG_TypeDef *) JPGDEC_BASE)
-#define HSEM ((HSEM_TypeDef *) HSEM_BASE)
-#define HSEM_COMMON ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x100UL))
-
-#define LTDC ((LTDC_TypeDef *)LTDC_BASE)
-#define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
-#define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
-
-#define MDIOS ((MDIOS_TypeDef *) MDIOS_BASE)
-
-#define ETH ((ETH_TypeDef *)ETH_BASE)
-#define MDMA ((MDMA_TypeDef *)MDMA_BASE)
-#define MDMA_Channel0 ((MDMA_Channel_TypeDef *)MDMA_Channel0_BASE)
-#define MDMA_Channel1 ((MDMA_Channel_TypeDef *)MDMA_Channel1_BASE)
-#define MDMA_Channel2 ((MDMA_Channel_TypeDef *)MDMA_Channel2_BASE)
-#define MDMA_Channel3 ((MDMA_Channel_TypeDef *)MDMA_Channel3_BASE)
-#define MDMA_Channel4 ((MDMA_Channel_TypeDef *)MDMA_Channel4_BASE)
-#define MDMA_Channel5 ((MDMA_Channel_TypeDef *)MDMA_Channel5_BASE)
-#define MDMA_Channel6 ((MDMA_Channel_TypeDef *)MDMA_Channel6_BASE)
-#define MDMA_Channel7 ((MDMA_Channel_TypeDef *)MDMA_Channel7_BASE)
-#define MDMA_Channel8 ((MDMA_Channel_TypeDef *)MDMA_Channel8_BASE)
-#define MDMA_Channel9 ((MDMA_Channel_TypeDef *)MDMA_Channel9_BASE)
-#define MDMA_Channel10 ((MDMA_Channel_TypeDef *)MDMA_Channel10_BASE)
-#define MDMA_Channel11 ((MDMA_Channel_TypeDef *)MDMA_Channel11_BASE)
-#define MDMA_Channel12 ((MDMA_Channel_TypeDef *)MDMA_Channel12_BASE)
-#define MDMA_Channel13 ((MDMA_Channel_TypeDef *)MDMA_Channel13_BASE)
-#define MDMA_Channel14 ((MDMA_Channel_TypeDef *)MDMA_Channel14_BASE)
-#define MDMA_Channel15 ((MDMA_Channel_TypeDef *)MDMA_Channel15_BASE)
-
-
-#define USB1_OTG_HS ((USB_OTG_GlobalTypeDef *) USB1_OTG_HS_PERIPH_BASE)
-#define USB2_OTG_FS ((USB_OTG_GlobalTypeDef *) USB2_OTG_FS_PERIPH_BASE)
-
-/* Legacy defines */
-#define USB_OTG_HS USB1_OTG_HS
-#define USB_OTG_HS_PERIPH_BASE USB1_OTG_HS_PERIPH_BASE
-#define USB_OTG_FS USB2_OTG_FS
-#define USB_OTG_FS_PERIPH_BASE USB2_OTG_FS_PERIPH_BASE
-
-/**
- * @}
- */
-
-/** @addtogroup Exported_constants
- * @{
- */
-
- /** @addtogroup Peripheral_Registers_Bits_Definition
- * @{
- */
-
-/******************************************************************************/
-/* Peripheral Registers_Bits_Definition */
-/******************************************************************************/
-
-/******************************************************************************/
-/* */
-/* Analog to Digital Converter */
-/* */
-/******************************************************************************/
-/******************************* ADC VERSION ********************************/
-#define ADC_VER_V5_X
-/******************** Bit definition for ADC_ISR register ********************/
-#define ADC_ISR_ADRDY_Pos (0U)
-#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */
-#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready (ADRDY) flag */
-#define ADC_ISR_EOSMP_Pos (1U)
-#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */
-#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC End of Sampling flag */
-#define ADC_ISR_EOC_Pos (2U)
-#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */
-#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC End of Regular Conversion flag */
-#define ADC_ISR_EOS_Pos (3U)
-#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */
-#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC End of Regular sequence of Conversions flag */
-#define ADC_ISR_OVR_Pos (4U)
-#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */
-#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC overrun flag */
-#define ADC_ISR_JEOC_Pos (5U)
-#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */
-#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC End of Injected Conversion flag */
-#define ADC_ISR_JEOS_Pos (6U)
-#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */
-#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC End of Injected sequence of Conversions flag */
-#define ADC_ISR_AWD1_Pos (7U)
-#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */
-#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC Analog watchdog 1 flag */
-#define ADC_ISR_AWD2_Pos (8U)
-#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */
-#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC Analog watchdog 2 flag */
-#define ADC_ISR_AWD3_Pos (9U)
-#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */
-#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC Analog watchdog 3 flag */
-#define ADC_ISR_JQOVF_Pos (10U)
-#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */
-#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */
-
-/******************** Bit definition for ADC_IER register ********************/
-#define ADC_IER_ADRDYIE_Pos (0U)
-#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */
-#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC Ready (ADRDY) interrupt source */
-#define ADC_IER_EOSMPIE_Pos (1U)
-#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */
-#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC End of Sampling interrupt source */
-#define ADC_IER_EOCIE_Pos (2U)
-#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */
-#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC End of Regular Conversion interrupt source */
-#define ADC_IER_EOSIE_Pos (3U)
-#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */
-#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC End of Regular sequence of Conversions interrupt source */
-#define ADC_IER_OVRIE_Pos (4U)
-#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */
-#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC overrun interrupt source */
-#define ADC_IER_JEOCIE_Pos (5U)
-#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */
-#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC End of Injected Conversion interrupt source */
-#define ADC_IER_JEOSIE_Pos (6U)
-#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */
-#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC End of Injected sequence of Conversions interrupt source */
-#define ADC_IER_AWD1IE_Pos (7U)
-#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */
-#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC Analog watchdog 1 interrupt source */
-#define ADC_IER_AWD2IE_Pos (8U)
-#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */
-#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC Analog watchdog 2 interrupt source */
-#define ADC_IER_AWD3IE_Pos (9U)
-#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */
-#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC Analog watchdog 3 interrupt source */
-#define ADC_IER_JQOVFIE_Pos (10U)
-#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */
-#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC Injected Context Queue Overflow interrupt source */
-
-/******************** Bit definition for ADC_CR register ********************/
-#define ADC_CR_ADEN_Pos (0U)
-#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */
-#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC Enable control */
-#define ADC_CR_ADDIS_Pos (1U)
-#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */
-#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC Disable command */
-#define ADC_CR_ADSTART_Pos (2U)
-#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */
-#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC Start of Regular conversion */
-#define ADC_CR_JADSTART_Pos (3U)
-#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */
-#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC Start of injected conversion */
-#define ADC_CR_ADSTP_Pos (4U)
-#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */
-#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC Stop of Regular conversion */
-#define ADC_CR_JADSTP_Pos (5U)
-#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */
-#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC Stop of injected conversion */
-#define ADC_CR_BOOST_Pos (8U)
-#define ADC_CR_BOOST_Msk (0x3UL << ADC_CR_BOOST_Pos) /*!< 0x00000300 */
-#define ADC_CR_BOOST ADC_CR_BOOST_Msk /*!< ADC Boost Mode configuration */
-#define ADC_CR_BOOST_0 (0x1UL << ADC_CR_BOOST_Pos) /*!< 0x00000100 */
-#define ADC_CR_BOOST_1 (0x2UL << ADC_CR_BOOST_Pos) /*!< 0x00000200 */
-#define ADC_CR_ADCALLIN_Pos (16U)
-#define ADC_CR_ADCALLIN_Msk (0x1UL << ADC_CR_ADCALLIN_Pos) /*!< 0x00010000 */
-#define ADC_CR_ADCALLIN ADC_CR_ADCALLIN_Msk /*!< ADC Linearity calibration */
-#define ADC_CR_LINCALRDYW1_Pos (22U)
-#define ADC_CR_LINCALRDYW1_Msk (0x1UL << ADC_CR_LINCALRDYW1_Pos) /*!< 0x00400000 */
-#define ADC_CR_LINCALRDYW1 ADC_CR_LINCALRDYW1_Msk /*!< ADC Linearity calibration ready Word 1 */
-#define ADC_CR_LINCALRDYW2_Pos (23U)
-#define ADC_CR_LINCALRDYW2_Msk (0x1UL << ADC_CR_LINCALRDYW2_Pos) /*!< 0x00800000 */
-#define ADC_CR_LINCALRDYW2 ADC_CR_LINCALRDYW2_Msk /*!< ADC Linearity calibration ready Word 2 */
-#define ADC_CR_LINCALRDYW3_Pos (24U)
-#define ADC_CR_LINCALRDYW3_Msk (0x1UL << ADC_CR_LINCALRDYW3_Pos) /*!< 0x01000000 */
-#define ADC_CR_LINCALRDYW3 ADC_CR_LINCALRDYW3_Msk /*!< ADC Linearity calibration ready Word 3 */
-#define ADC_CR_LINCALRDYW4_Pos (25U)
-#define ADC_CR_LINCALRDYW4_Msk (0x1UL << ADC_CR_LINCALRDYW4_Pos) /*!< 0x02000000 */
-#define ADC_CR_LINCALRDYW4 ADC_CR_LINCALRDYW4_Msk /*!< ADC Linearity calibration ready Word 4 */
-#define ADC_CR_LINCALRDYW5_Pos (26U)
-#define ADC_CR_LINCALRDYW5_Msk (0x1UL << ADC_CR_LINCALRDYW5_Pos) /*!< 0x04000000 */
-#define ADC_CR_LINCALRDYW5 ADC_CR_LINCALRDYW5_Msk /*!< ADC Linearity calibration ready Word 5 */
-#define ADC_CR_LINCALRDYW6_Pos (27U)
-#define ADC_CR_LINCALRDYW6_Msk (0x1UL << ADC_CR_LINCALRDYW6_Pos) /*!< 0x08000000 */
-#define ADC_CR_LINCALRDYW6 ADC_CR_LINCALRDYW6_Msk /*!< ADC Linearity calibration ready Word 6 */
-#define ADC_CR_ADVREGEN_Pos (28U)
-#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */
-#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC Voltage regulator Enable */
-#define ADC_CR_DEEPPWD_Pos (29U)
-#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */
-#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC Deep power down Enable */
-#define ADC_CR_ADCALDIF_Pos (30U)
-#define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */
-#define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC Differential Mode for calibration */
-#define ADC_CR_ADCAL_Pos (31U)
-#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */
-#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC Calibration */
-
-/******************** Bit definition for ADC_CFGR register ********************/
-#define ADC_CFGR_DMNGT_Pos (0U)
-#define ADC_CFGR_DMNGT_Msk (0x3UL << ADC_CFGR_DMNGT_Pos) /*!< 0x00000003 */
-#define ADC_CFGR_DMNGT ADC_CFGR_DMNGT_Msk /*!< ADC Data Management configuration */
-#define ADC_CFGR_DMNGT_0 (0x1UL << ADC_CFGR_DMNGT_Pos) /*!< 0x00000001 */
-#define ADC_CFGR_DMNGT_1 (0x2UL << ADC_CFGR_DMNGT_Pos) /*!< 0x00000002 */
-
-#define ADC_CFGR_RES_Pos (2U)
-#define ADC_CFGR_RES_Msk (0x7UL << ADC_CFGR_RES_Pos) /*!< 0x0000001C */
-#define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC Data resolution */
-#define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos) /*!< 0x00000004 */
-#define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos) /*!< 0x00000008 */
-#define ADC_CFGR_RES_2 (0x4UL << ADC_CFGR_RES_Pos) /*!< 0x00000010 */
-
-#define ADC_CFGR_EXTSEL_Pos (5U)
-#define ADC_CFGR_EXTSEL_Msk (0x1FUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003E0 */
-#define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC External trigger selection for regular group */
-#define ADC_CFGR_EXTSEL_0 (0x01UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000020 */
-#define ADC_CFGR_EXTSEL_1 (0x02UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */
-#define ADC_CFGR_EXTSEL_2 (0x04UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */
-#define ADC_CFGR_EXTSEL_3 (0x08UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */
-#define ADC_CFGR_EXTSEL_4 (0x10UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */
-
-#define ADC_CFGR_EXTEN_Pos (10U)
-#define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */
-#define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC External trigger enable and polarity selection for regular channels */
-#define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */
-#define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */
-
-#define ADC_CFGR_OVRMOD_Pos (12U)
-#define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */
-#define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC overrun mode */
-#define ADC_CFGR_CONT_Pos (13U)
-#define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */
-#define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC Single/continuous conversion mode for regular conversion */
-#define ADC_CFGR_AUTDLY_Pos (14U)
-#define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */
-#define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC Delayed conversion mode */
-
-#define ADC_CFGR_DISCEN_Pos (16U)
-#define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */
-#define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC Discontinuous mode for regular channels */
-
-#define ADC_CFGR_DISCNUM_Pos (17U)
-#define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */
-#define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC Discontinuous mode channel count */
-#define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */
-#define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */
-#define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */
-
-#define ADC_CFGR_JDISCEN_Pos (20U)
-#define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */
-#define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC Discontinuous mode on injected channels */
-#define ADC_CFGR_JQM_Pos (21U)
-#define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */
-#define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC JSQR Queue mode */
-#define ADC_CFGR_AWD1SGL_Pos (22U)
-#define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */
-#define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< Enable the watchdog 1 on a single channel or on all channels */
-#define ADC_CFGR_AWD1EN_Pos (23U)
-#define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */
-#define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC Analog watchdog 1 enable on regular Channels */
-#define ADC_CFGR_JAWD1EN_Pos (24U)
-#define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */
-#define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC Analog watchdog 1 enable on injected Channels */
-#define ADC_CFGR_JAUTO_Pos (25U)
-#define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */
-#define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC Automatic injected group conversion */
-
-#define ADC_CFGR_AWD1CH_Pos (26U)
-#define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */
-#define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC Analog watchdog 1 Channel selection */
-#define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */
-#define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */
-#define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */
-#define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */
-#define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */
-
-#define ADC_CFGR_JQDIS_Pos (31U)
-#define ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */
-#define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC Injected queue disable */
-
-/******************** Bit definition for ADC_CFGR2 register ********************/
-#define ADC_CFGR2_ROVSE_Pos (0U)
-#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */
-#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC Regular group oversampler enable */
-#define ADC_CFGR2_JOVSE_Pos (1U)
-#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */
-#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC Injected group oversampler enable */
-
-#define ADC_CFGR2_OVSS_Pos (5U)
-#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */
-#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC Regular Oversampling shift */
-#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */
-#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */
-#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */
-#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */
-
-#define ADC_CFGR2_TROVS_Pos (9U)
-#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */
-#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC Triggered regular Oversampling */
-#define ADC_CFGR2_ROVSM_Pos (10U)
-#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */
-#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC Regular oversampling mode */
-
-#define ADC_CFGR2_RSHIFT1_Pos (11U)
-#define ADC_CFGR2_RSHIFT1_Msk (0x1UL << ADC_CFGR2_RSHIFT1_Pos) /*!< 0x00000800 */
-#define ADC_CFGR2_RSHIFT1 ADC_CFGR2_RSHIFT1_Msk /*!< ADC Right-shift data after Offset 1 correction */
-#define ADC_CFGR2_RSHIFT2_Pos (12U)
-#define ADC_CFGR2_RSHIFT2_Msk (0x1UL << ADC_CFGR2_RSHIFT2_Pos) /*!< 0x00001000 */
-#define ADC_CFGR2_RSHIFT2 ADC_CFGR2_RSHIFT2_Msk /*!< ADC Right-shift data after Offset 2 correction */
-#define ADC_CFGR2_RSHIFT3_Pos (13U)
-#define ADC_CFGR2_RSHIFT3_Msk (0x1UL << ADC_CFGR2_RSHIFT3_Pos) /*!< 0x00002000 */
-#define ADC_CFGR2_RSHIFT3 ADC_CFGR2_RSHIFT3_Msk /*!< ADC Right-shift data after Offset 3 correction */
-#define ADC_CFGR2_RSHIFT4_Pos (14U)
-#define ADC_CFGR2_RSHIFT4_Msk (0x1UL << ADC_CFGR2_RSHIFT4_Pos) /*!< 0x00004000 */
-#define ADC_CFGR2_RSHIFT4 ADC_CFGR2_RSHIFT4_Msk /*!< ADC Right-shift data after Offset 4 correction */
-
-#define ADC_CFGR2_OVSR_Pos (16U)
-#define ADC_CFGR2_OVSR_Msk (0x3FFUL << ADC_CFGR2_OVSR_Pos) /*!< 0x03FF0000 */
-#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling Ratio */
-#define ADC_CFGR2_OVSR_0 (0x001UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00010000 */
-#define ADC_CFGR2_OVSR_1 (0x002UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00020000 */
-#define ADC_CFGR2_OVSR_2 (0x004UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00040000 */
-#define ADC_CFGR2_OVSR_3 (0x008UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00080000 */
-#define ADC_CFGR2_OVSR_4 (0x010UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00100000 */
-#define ADC_CFGR2_OVSR_5 (0x020UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00200000 */
-#define ADC_CFGR2_OVSR_6 (0x040UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00400000 */
-#define ADC_CFGR2_OVSR_7 (0x080UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00800000 */
-#define ADC_CFGR2_OVSR_8 (0x100UL << ADC_CFGR2_OVSR_Pos) /*!< 0x01000000 */
-#define ADC_CFGR2_OVSR_9 (0x200UL << ADC_CFGR2_OVSR_Pos) /*!< 0x02000000 */
-
-#define ADC_CFGR2_LSHIFT_Pos (28U)
-#define ADC_CFGR2_LSHIFT_Msk (0xFUL << ADC_CFGR2_LSHIFT_Pos) /*!< 0xF0000000 */
-#define ADC_CFGR2_LSHIFT ADC_CFGR2_LSHIFT_Msk /*!< ADC Left shift factor */
-#define ADC_CFGR2_LSHIFT_0 (0x1UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x10000000 */
-#define ADC_CFGR2_LSHIFT_1 (0x2UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x20000000 */
-#define ADC_CFGR2_LSHIFT_2 (0x4UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x40000000 */
-#define ADC_CFGR2_LSHIFT_3 (0x8UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x80000000 */
-
-/******************** Bit definition for ADC_SMPR1 register ********************/
-#define ADC_SMPR1_SMP0_Pos (0U)
-#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */
-#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC Channel 0 Sampling time selection */
-#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */
-#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */
-#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */
-
-#define ADC_SMPR1_SMP1_Pos (3U)
-#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */
-#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC Channel 1 Sampling time selection */
-#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */
-#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */
-#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */
-
-#define ADC_SMPR1_SMP2_Pos (6U)
-#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */
-#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC Channel 2 Sampling time selection */
-#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */
-#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */
-#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */
-
-#define ADC_SMPR1_SMP3_Pos (9U)
-#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */
-#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC Channel 3 Sampling time selection */
-#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */
-#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */
-#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */
-
-#define ADC_SMPR1_SMP4_Pos (12U)
-#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */
-#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC Channel 4 Sampling time selection */
-#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */
-#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */
-#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */
-
-#define ADC_SMPR1_SMP5_Pos (15U)
-#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */
-#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC Channel 5 Sampling time selection */
-#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */
-#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */
-#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */
-
-#define ADC_SMPR1_SMP6_Pos (18U)
-#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */
-#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC Channel 6 Sampling time selection */
-#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */
-#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */
-#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */
-
-#define ADC_SMPR1_SMP7_Pos (21U)
-#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */
-#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC Channel 7 Sampling time selection */
-#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */
-#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */
-#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */
-
-#define ADC_SMPR1_SMP8_Pos (24U)
-#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */
-#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC Channel 8 Sampling time selection */
-#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */
-#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */
-#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */
-
-#define ADC_SMPR1_SMP9_Pos (27U)
-#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */
-#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC Channel 9 Sampling time selection */
-#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */
-#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */
-#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */
-
-/******************** Bit definition for ADC_SMPR2 register ********************/
-#define ADC_SMPR2_SMP10_Pos (0U)
-#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */
-#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC Channel 10 Sampling time selection */
-#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */
-#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */
-#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */
-
-#define ADC_SMPR2_SMP11_Pos (3U)
-#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */
-#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC Channel 11 Sampling time selection */
-#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */
-#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */
-#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */
-
-#define ADC_SMPR2_SMP12_Pos (6U)
-#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */
-#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC Channel 12 Sampling time selection */
-#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */
-#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */
-#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */
-
-#define ADC_SMPR2_SMP13_Pos (9U)
-#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */
-#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC Channel 13 Sampling time selection */
-#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */
-#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */
-#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */
-
-#define ADC_SMPR2_SMP14_Pos (12U)
-#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */
-#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC Channel 14 Sampling time selection */
-#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */
-#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */
-#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */
-
-#define ADC_SMPR2_SMP15_Pos (15U)
-#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */
-#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC Channel 15 Sampling time selection */
-#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */
-#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */
-#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */
-
-#define ADC_SMPR2_SMP16_Pos (18U)
-#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */
-#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC Channel 16 Sampling time selection */
-#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */
-#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */
-#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */
-
-#define ADC_SMPR2_SMP17_Pos (21U)
-#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */
-#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC Channel 17 Sampling time selection */
-#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */
-#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */
-#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */
-
-#define ADC_SMPR2_SMP18_Pos (24U)
-#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */
-#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC Channel 18 Sampling time selection */
-#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */
-#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */
-#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */
-
-#define ADC_SMPR2_SMP19_Pos (27U)
-#define ADC_SMPR2_SMP19_Msk (0x7UL << ADC_SMPR2_SMP19_Pos) /*!< 0x38000000 */
-#define ADC_SMPR2_SMP19 ADC_SMPR2_SMP19_Msk /*!< ADC Channel 19 Sampling time selection */
-#define ADC_SMPR2_SMP19_0 (0x1UL << ADC_SMPR2_SMP19_Pos) /*!< 0x08000000 */
-#define ADC_SMPR2_SMP19_1 (0x2UL << ADC_SMPR2_SMP19_Pos) /*!< 0x10000000 */
-#define ADC_SMPR2_SMP19_2 (0x4UL << ADC_SMPR2_SMP19_Pos) /*!< 0x20000000 */
-
-/******************** Bit definition for ADC_PCSEL register ********************/
-#define ADC_PCSEL_PCSEL_Pos (0U)
-#define ADC_PCSEL_PCSEL_Msk (0xFFFFFUL << ADC_PCSEL_PCSEL_Pos) /*!< 0x000FFFFF */
-#define ADC_PCSEL_PCSEL ADC_PCSEL_PCSEL_Msk /*!< ADC pre channel selection */
-#define ADC_PCSEL_PCSEL_0 (0x00001UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000001 */
-#define ADC_PCSEL_PCSEL_1 (0x00002UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000002 */
-#define ADC_PCSEL_PCSEL_2 (0x00004UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000004 */
-#define ADC_PCSEL_PCSEL_3 (0x00008UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000008 */
-#define ADC_PCSEL_PCSEL_4 (0x00010UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000010 */
-#define ADC_PCSEL_PCSEL_5 (0x00020UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000020 */
-#define ADC_PCSEL_PCSEL_6 (0x00040UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000040 */
-#define ADC_PCSEL_PCSEL_7 (0x00080UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000080 */
-#define ADC_PCSEL_PCSEL_8 (0x00100UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000100 */
-#define ADC_PCSEL_PCSEL_9 (0x00200UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000200 */
-#define ADC_PCSEL_PCSEL_10 (0x00400UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000400 */
-#define ADC_PCSEL_PCSEL_11 (0x00800UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000800 */
-#define ADC_PCSEL_PCSEL_12 (0x01000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00001000 */
-#define ADC_PCSEL_PCSEL_13 (0x02000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00002000 */
-#define ADC_PCSEL_PCSEL_14 (0x04000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00004000 */
-#define ADC_PCSEL_PCSEL_15 (0x08000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00008000 */
-#define ADC_PCSEL_PCSEL_16 (0x10000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00010000 */
-#define ADC_PCSEL_PCSEL_17 (0x20000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00020000 */
-#define ADC_PCSEL_PCSEL_18 (0x40000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00040000 */
-#define ADC_PCSEL_PCSEL_19 (0x80000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00080000 */
-
-/***************** Bit definition for ADC_LTR1, 2, 3 registers *****************/
-#define ADC_LTR_LT_Pos (0U)
-#define ADC_LTR_LT_Msk (0x3FFFFFFUL << ADC_LTR_LT_Pos) /*!< 0x03FFFFFF */
-#define ADC_LTR_LT ADC_LTR_LT_Msk /*!< ADC Analog watchdog 1, 2 and 3 lower threshold */
-
-/***************** Bit definition for ADC_HTR1, 2, 3 registers ****************/
-#define ADC_HTR_HT_Pos (0U)
-#define ADC_HTR_HT_Msk (0x3FFFFFFUL << ADC_HTR_HT_Pos) /*!< 0x03FFFFFF */
-#define ADC_HTR_HT ADC_HTR_HT_Msk /*!< ADC Analog watchdog 1,2 and 3 higher threshold */
-
-
-/******************** Bit definition for ADC_SQR1 register ********************/
-#define ADC_SQR1_L_Pos (0U)
-#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */
-#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC regular channel sequence lenght */
-#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */
-#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */
-#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */
-#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */
-
-#define ADC_SQR1_SQ1_Pos (6U)
-#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */
-#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC 1st conversion in regular sequence */
-#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */
-#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */
-#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */
-#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */
-#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */
-
-#define ADC_SQR1_SQ2_Pos (12U)
-#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */
-#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC 2nd conversion in regular sequence */
-#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */
-#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */
-#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */
-#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */
-#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */
-
-#define ADC_SQR1_SQ3_Pos (18U)
-#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */
-#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC 3rd conversion in regular sequence */
-#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */
-#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */
-#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */
-#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */
-#define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */
-
-#define ADC_SQR1_SQ4_Pos (24U)
-#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */
-#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC 4th conversion in regular sequence */
-#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */
-#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */
-#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */
-#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */
-#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */
-
-/******************** Bit definition for ADC_SQR2 register ********************/
-#define ADC_SQR2_SQ5_Pos (0U)
-#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */
-#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC 5th conversion in regular sequence */
-#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */
-#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */
-#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */
-#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */
-#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */
-
-#define ADC_SQR2_SQ6_Pos (6U)
-#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */
-#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC 6th conversion in regular sequence */
-#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */
-#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */
-#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */
-#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */
-#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */
-
-#define ADC_SQR2_SQ7_Pos (12U)
-#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */
-#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC 7th conversion in regular sequence */
-#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */
-#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */
-#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */
-#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */
-#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */
-
-#define ADC_SQR2_SQ8_Pos (18U)
-#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */
-#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC 8th conversion in regular sequence */
-#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */
-#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */
-#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */
-#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */
-#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */
-
-#define ADC_SQR2_SQ9_Pos (24U)
-#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */
-#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC 9th conversion in regular sequence */
-#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */
-#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */
-#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */
-#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */
-#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */
-
-/******************** Bit definition for ADC_SQR3 register ********************/
-#define ADC_SQR3_SQ10_Pos (0U)
-#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */
-#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC 10th conversion in regular sequence */
-#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */
-#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */
-#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */
-#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */
-#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */
-
-#define ADC_SQR3_SQ11_Pos (6U)
-#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */
-#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC 11th conversion in regular sequence */
-#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */
-#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */
-#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */
-#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */
-#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */
-
-#define ADC_SQR3_SQ12_Pos (12U)
-#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */
-#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC 12th conversion in regular sequence */
-#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */
-#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */
-#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */
-#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */
-#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */
-
-#define ADC_SQR3_SQ13_Pos (18U)
-#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */
-#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC 13th conversion in regular sequence */
-#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */
-#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */
-#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */
-#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */
-#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */
-
-#define ADC_SQR3_SQ14_Pos (24U)
-#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */
-#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC 14th conversion in regular sequence */
-#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */
-#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */
-#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */
-#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */
-#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */
-
-/******************** Bit definition for ADC_SQR4 register ********************/
-#define ADC_SQR4_SQ15_Pos (0U)
-#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */
-#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC 15th conversion in regular sequence */
-#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */
-#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */
-#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */
-#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */
-#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */
-
-#define ADC_SQR4_SQ16_Pos (6U)
-#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */
-#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC 16th conversion in regular sequence */
-#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */
-#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */
-#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */
-#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */
-#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */
-/******************** Bit definition for ADC_DR register ********************/
-#define ADC_DR_RDATA_Pos (0U)
-#define ADC_DR_RDATA_Msk (0xFFFFFFFFUL << ADC_DR_RDATA_Pos) /*!< 0xFFFFFFFF */
-#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC regular Data converted */
-
-/******************** Bit definition for ADC_JSQR register ********************/
-#define ADC_JSQR_JL_Pos (0U)
-#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */
-#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC injected channel sequence length */
-#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */
-#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */
-
-#define ADC_JSQR_JEXTSEL_Pos (2U)
-#define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */
-#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC external trigger selection for injected group */
-#define ADC_JSQR_JEXTSEL_0 (0x01UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */
-#define ADC_JSQR_JEXTSEL_1 (0x02UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */
-#define ADC_JSQR_JEXTSEL_2 (0x04UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */
-#define ADC_JSQR_JEXTSEL_3 (0x08UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */
-#define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */
-
-#define ADC_JSQR_JEXTEN_Pos (7U)
-#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */
-#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC external trigger enable and polarity selection for injected channels */
-#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */
-#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */
-
-#define ADC_JSQR_JSQ1_Pos (9U)
-#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */
-#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC 1st conversion in injected sequence */
-#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */
-#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */
-#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */
-#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */
-#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */
-
-#define ADC_JSQR_JSQ2_Pos (15U)
-#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x000F8000 */
-#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC 2nd conversion in injected sequence */
-#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */
-#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */
-#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */
-#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */
-#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00080000 */
-
-#define ADC_JSQR_JSQ3_Pos (21U)
-#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */
-#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC 3rd conversion in injected sequence */
-#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */
-#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */
-#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */
-#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */
-#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */
-
-#define ADC_JSQR_JSQ4_Pos (27U)
-#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */
-#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC 4th conversion in injected sequence */
-#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */
-#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */
-#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */
-#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */
-#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */
-
-/******************** Bit definition for ADC_OFR1 register ********************/
-#define ADC_OFR1_OFFSET1_Pos (0U)
-#define ADC_OFR1_OFFSET1_Msk (0x3FFFFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x03FFFFFF */
-#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */
-#define ADC_OFR1_OFFSET1_0 (0x0000001UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */
-#define ADC_OFR1_OFFSET1_1 (0x0000002UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */
-#define ADC_OFR1_OFFSET1_2 (0x0000004UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */
-#define ADC_OFR1_OFFSET1_3 (0x0000008UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */
-#define ADC_OFR1_OFFSET1_4 (0x0000010UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */
-#define ADC_OFR1_OFFSET1_5 (0x0000020UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */
-#define ADC_OFR1_OFFSET1_6 (0x0000040UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */
-#define ADC_OFR1_OFFSET1_7 (0x0000080UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */
-#define ADC_OFR1_OFFSET1_8 (0x0000100UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */
-#define ADC_OFR1_OFFSET1_9 (0x0000200UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */
-#define ADC_OFR1_OFFSET1_10 (0x0000400UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */
-#define ADC_OFR1_OFFSET1_11 (0x0000800UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */
-#define ADC_OFR1_OFFSET1_12 (0x0001000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00001000 */
-#define ADC_OFR1_OFFSET1_13 (0x0002000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00002000 */
-#define ADC_OFR1_OFFSET1_14 (0x0004000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00004000 */
-#define ADC_OFR1_OFFSET1_15 (0x0008000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00008000 */
-#define ADC_OFR1_OFFSET1_16 (0x0010000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00010000 */
-#define ADC_OFR1_OFFSET1_17 (0x0020000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00020000 */
-#define ADC_OFR1_OFFSET1_18 (0x0040000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00040000 */
-#define ADC_OFR1_OFFSET1_19 (0x0080000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00080000 */
-#define ADC_OFR1_OFFSET1_20 (0x0100000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00100000 */
-#define ADC_OFR1_OFFSET1_21 (0x0200000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00200000 */
-#define ADC_OFR1_OFFSET1_22 (0x0400000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00400000 */
-#define ADC_OFR1_OFFSET1_23 (0x0800000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00800000 */
-#define ADC_OFR1_OFFSET1_24 (0x1000000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x01000000 */
-#define ADC_OFR1_OFFSET1_25 (0x2000000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x02000000 */
-
-#define ADC_OFR1_OFFSET1_CH_Pos (26U)
-#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */
-#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC Channel selection for the data offset 1 */
-#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */
-#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */
-#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */
-#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */
-#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */
-
-#define ADC_OFR1_SSATE_Pos (31U)
-#define ADC_OFR1_SSATE_Msk (0x1UL << ADC_OFR1_SSATE_Pos) /*!< 0x80000000 */
-#define ADC_OFR1_SSATE ADC_OFR1_SSATE_Msk /*!< ADC Signed saturation Enable */
-
-
-/******************** Bit definition for ADC_OFR2 register ********************/
-#define ADC_OFR2_OFFSET2_Pos (0U)
-#define ADC_OFR2_OFFSET2_Msk (0x3FFFFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x03FFFFFF */
-#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0] */
-#define ADC_OFR2_OFFSET2_0 (0x0000001UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */
-#define ADC_OFR2_OFFSET2_1 (0x0000002UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */
-#define ADC_OFR2_OFFSET2_2 (0x0000004UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */
-#define ADC_OFR2_OFFSET2_3 (0x0000008UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */
-#define ADC_OFR2_OFFSET2_4 (0x0000010UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */
-#define ADC_OFR2_OFFSET2_5 (0x0000020UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */
-#define ADC_OFR2_OFFSET2_6 (0x0000040UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */
-#define ADC_OFR2_OFFSET2_7 (0x0000080UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */
-#define ADC_OFR2_OFFSET2_8 (0x0000100UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */
-#define ADC_OFR2_OFFSET2_9 (0x0000200UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */
-#define ADC_OFR2_OFFSET2_10 (0x0000400UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */
-#define ADC_OFR2_OFFSET2_11 (0x0000800UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */
-#define ADC_OFR2_OFFSET2_12 (0x0001000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00001000 */
-#define ADC_OFR2_OFFSET2_13 (0x0002000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00002000 */
-#define ADC_OFR2_OFFSET2_14 (0x0004000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00004000 */
-#define ADC_OFR2_OFFSET2_15 (0x0008000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00008000 */
-#define ADC_OFR2_OFFSET2_16 (0x0010000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00010000 */
-#define ADC_OFR2_OFFSET2_17 (0x0020000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00020000 */
-#define ADC_OFR2_OFFSET2_18 (0x0040000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00040000 */
-#define ADC_OFR2_OFFSET2_19 (0x0080000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00080000 */
-#define ADC_OFR2_OFFSET2_20 (0x0100000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00100000 */
-#define ADC_OFR2_OFFSET2_21 (0x0200000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00200000 */
-#define ADC_OFR2_OFFSET2_22 (0x0400000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00400000 */
-#define ADC_OFR2_OFFSET2_23 (0x0800000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00800000 */
-#define ADC_OFR2_OFFSET2_24 (0x1000000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x01000000 */
-#define ADC_OFR2_OFFSET2_25 (0x2000000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x02000000 */
-
-#define ADC_OFR2_OFFSET2_CH_Pos (26U)
-#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */
-#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC Channel selection for the data offset 2 */
-#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */
-#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */
-#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */
-#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */
-#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */
-
-#define ADC_OFR2_SSATE_Pos (31U)
-#define ADC_OFR2_SSATE_Msk (0x1UL << ADC_OFR2_SSATE_Pos) /*!< 0x80000000 */
-#define ADC_OFR2_SSATE ADC_OFR2_SSATE_Msk /*!< ADC Signed saturation Enable */
-
-
-/******************** Bit definition for ADC_OFR3 register ********************/
-#define ADC_OFR3_OFFSET3_Pos (0U)
-#define ADC_OFR3_OFFSET3_Msk (0x3FFFFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x03FFFFFF */
-#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0] */
-#define ADC_OFR3_OFFSET3_0 (0x0000001UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */
-#define ADC_OFR3_OFFSET3_1 (0x0000002UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */
-#define ADC_OFR3_OFFSET3_2 (0x0000004UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */
-#define ADC_OFR3_OFFSET3_3 (0x0000008UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */
-#define ADC_OFR3_OFFSET3_4 (0x0000010UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */
-#define ADC_OFR3_OFFSET3_5 (0x0000020UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */
-#define ADC_OFR3_OFFSET3_6 (0x0000040UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */
-#define ADC_OFR3_OFFSET3_7 (0x0000080UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */
-#define ADC_OFR3_OFFSET3_8 (0x0000100UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */
-#define ADC_OFR3_OFFSET3_9 (0x0000200UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */
-#define ADC_OFR3_OFFSET3_10 (0x0000400UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */
-#define ADC_OFR3_OFFSET3_11 (0x0000800UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */
-#define ADC_OFR3_OFFSET3_12 (0x0001000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00001000 */
-#define ADC_OFR3_OFFSET3_13 (0x0002000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00002000 */
-#define ADC_OFR3_OFFSET3_14 (0x0004000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00004000 */
-#define ADC_OFR3_OFFSET3_15 (0x0008000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00008000 */
-#define ADC_OFR3_OFFSET3_16 (0x0010000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00010000 */
-#define ADC_OFR3_OFFSET3_17 (0x0020000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00020000 */
-#define ADC_OFR3_OFFSET3_18 (0x0040000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00040000 */
-#define ADC_OFR3_OFFSET3_19 (0x0080000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00080000 */
-#define ADC_OFR3_OFFSET3_20 (0x0100000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00100000 */
-#define ADC_OFR3_OFFSET3_21 (0x0200000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00200000 */
-#define ADC_OFR3_OFFSET3_22 (0x0400000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00400000 */
-#define ADC_OFR3_OFFSET3_23 (0x0800000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00800000 */
-#define ADC_OFR3_OFFSET3_24 (0x1000000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x01000000 */
-#define ADC_OFR3_OFFSET3_25 (0x2000000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x02000000 */
-
-#define ADC_OFR3_OFFSET3_CH_Pos (26U)
-#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */
-#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC Channel selection for the data offset 3 */
-#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */
-#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */
-#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */
-#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */
-#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */
-
-#define ADC_OFR3_SSATE_Pos (31U)
-#define ADC_OFR3_SSATE_Msk (0x1UL << ADC_OFR3_SSATE_Pos) /*!< 0x80000000 */
-#define ADC_OFR3_SSATE ADC_OFR3_SSATE_Msk /*!< ADC Signed saturation Enable */
-
-
-/******************** Bit definition for ADC_OFR4 register ********************/
-#define ADC_OFR4_OFFSET4_Pos (0U)
-#define ADC_OFR4_OFFSET4_Msk (0x3FFFFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x03FFFFFF */
-#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0] */
-#define ADC_OFR4_OFFSET4_0 (0x0000001UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */
-#define ADC_OFR4_OFFSET4_1 (0x0000002UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */
-#define ADC_OFR4_OFFSET4_2 (0x0000004UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */
-#define ADC_OFR4_OFFSET4_3 (0x0000008UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */
-#define ADC_OFR4_OFFSET4_4 (0x0000010UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */
-#define ADC_OFR4_OFFSET4_5 (0x0000020UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */
-#define ADC_OFR4_OFFSET4_6 (0x0000040UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */
-#define ADC_OFR4_OFFSET4_7 (0x0000080UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */
-#define ADC_OFR4_OFFSET4_8 (0x0000100UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */
-#define ADC_OFR4_OFFSET4_9 (0x0000200UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */
-#define ADC_OFR4_OFFSET4_10 (0x0000400UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */
-#define ADC_OFR4_OFFSET4_11 (0x0000800UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */
-#define ADC_OFR4_OFFSET4_12 (0x0001000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00001000 */
-#define ADC_OFR4_OFFSET4_13 (0x0002000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00002000 */
-#define ADC_OFR4_OFFSET4_14 (0x0004000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00004000 */
-#define ADC_OFR4_OFFSET4_15 (0x0008000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00008000 */
-#define ADC_OFR4_OFFSET4_16 (0x0010000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00010000 */
-#define ADC_OFR4_OFFSET4_17 (0x0020000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00020000 */
-#define ADC_OFR4_OFFSET4_18 (0x0040000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00040000 */
-#define ADC_OFR4_OFFSET4_19 (0x0080000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00080000 */
-#define ADC_OFR4_OFFSET4_20 (0x0100000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00100000 */
-#define ADC_OFR4_OFFSET4_21 (0x0200000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00200000 */
-#define ADC_OFR4_OFFSET4_22 (0x0400000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00400000 */
-#define ADC_OFR4_OFFSET4_23 (0x0800000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00800000 */
-#define ADC_OFR4_OFFSET4_24 (0x1000000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x01000000 */
-#define ADC_OFR4_OFFSET4_25 (0x2000000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x02000000 */
-
-#define ADC_OFR4_OFFSET4_CH_Pos (26U)
-#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */
-#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC Channel selection for the data offset 4 */
-#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */
-#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */
-#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */
-#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */
-#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */
-
-#define ADC_OFR4_SSATE_Pos (31U)
-#define ADC_OFR4_SSATE_Msk (0x1UL << ADC_OFR4_SSATE_Pos) /*!< 0x80000000 */
-#define ADC_OFR4_SSATE ADC_OFR4_SSATE_Msk /*!< ADC Signed saturation Enable */
-
-
-/******************** Bit definition for ADC_JDR1 register ********************/
-#define ADC_JDR1_JDATA_Pos (0U)
-#define ADC_JDR1_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0xFFFFFFFF */
-#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC Injected DATA */
-#define ADC_JDR1_JDATA_0 (0x00000001UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */
-#define ADC_JDR1_JDATA_1 (0x00000002UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */
-#define ADC_JDR1_JDATA_2 (0x00000004UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */
-#define ADC_JDR1_JDATA_3 (0x00000008UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */
-#define ADC_JDR1_JDATA_4 (0x00000010UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */
-#define ADC_JDR1_JDATA_5 (0x00000020UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */
-#define ADC_JDR1_JDATA_6 (0x00000040UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */
-#define ADC_JDR1_JDATA_7 (0x00000080UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */
-#define ADC_JDR1_JDATA_8 (0x00000100UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */
-#define ADC_JDR1_JDATA_9 (0x00000200UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */
-#define ADC_JDR1_JDATA_10 (0x00000400UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */
-#define ADC_JDR1_JDATA_11 (0x00000800UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */
-#define ADC_JDR1_JDATA_12 (0x00001000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */
-#define ADC_JDR1_JDATA_13 (0x00002000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */
-#define ADC_JDR1_JDATA_14 (0x00004000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */
-#define ADC_JDR1_JDATA_15 (0x00008000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */
-#define ADC_JDR1_JDATA_16 (0x00010000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00010000 */
-#define ADC_JDR1_JDATA_17 (0x00020000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00020000 */
-#define ADC_JDR1_JDATA_18 (0x00040000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00040000 */
-#define ADC_JDR1_JDATA_19 (0x00080000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00080000 */
-#define ADC_JDR1_JDATA_20 (0x00100000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00100000 */
-#define ADC_JDR1_JDATA_21 (0x00200000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00200000 */
-#define ADC_JDR1_JDATA_22 (0x00400000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00400000 */
-#define ADC_JDR1_JDATA_23 (0x00800000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00800000 */
-#define ADC_JDR1_JDATA_24 (0x01000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x01000000 */
-#define ADC_JDR1_JDATA_25 (0x02000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x02000000 */
-#define ADC_JDR1_JDATA_26 (0x04000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x04000000 */
-#define ADC_JDR1_JDATA_27 (0x08000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x08000000 */
-#define ADC_JDR1_JDATA_28 (0x10000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x10000000 */
-#define ADC_JDR1_JDATA_29 (0x20000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x20000000 */
-#define ADC_JDR1_JDATA_30 (0x40000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x40000000 */
-#define ADC_JDR1_JDATA_31 (0x80000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x80000000 */
-
-/******************** Bit definition for ADC_JDR2 register ********************/
-#define ADC_JDR2_JDATA_Pos (0U)
-#define ADC_JDR2_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0xFFFFFFFF */
-#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC Injected DATA */
-#define ADC_JDR2_JDATA_0 (0x00000001UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */
-#define ADC_JDR2_JDATA_1 (0x00000002UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */
-#define ADC_JDR2_JDATA_2 (0x00000004UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */
-#define ADC_JDR2_JDATA_3 (0x00000008UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */
-#define ADC_JDR2_JDATA_4 (0x00000010UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */
-#define ADC_JDR2_JDATA_5 (0x00000020UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */
-#define ADC_JDR2_JDATA_6 (0x00000040UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */
-#define ADC_JDR2_JDATA_7 (0x00000080UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */
-#define ADC_JDR2_JDATA_8 (0x00000100UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */
-#define ADC_JDR2_JDATA_9 (0x00000200UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */
-#define ADC_JDR2_JDATA_10 (0x00000400UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */
-#define ADC_JDR2_JDATA_11 (0x00000800UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */
-#define ADC_JDR2_JDATA_12 (0x00001000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */
-#define ADC_JDR2_JDATA_13 (0x00002000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */
-#define ADC_JDR2_JDATA_14 (0x00004000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */
-#define ADC_JDR2_JDATA_15 (0x00008000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */
-#define ADC_JDR2_JDATA_16 (0x00010000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00010000 */
-#define ADC_JDR2_JDATA_17 (0x00020000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00020000 */
-#define ADC_JDR2_JDATA_18 (0x00040000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00040000 */
-#define ADC_JDR2_JDATA_19 (0x00080000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00080000 */
-#define ADC_JDR2_JDATA_20 (0x00100000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00100000 */
-#define ADC_JDR2_JDATA_21 (0x00200000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00200000 */
-#define ADC_JDR2_JDATA_22 (0x00400000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00400000 */
-#define ADC_JDR2_JDATA_23 (0x00800000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00800000 */
-#define ADC_JDR2_JDATA_24 (0x01000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x01000000 */
-#define ADC_JDR2_JDATA_25 (0x02000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x02000000 */
-#define ADC_JDR2_JDATA_26 (0x04000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x04000000 */
-#define ADC_JDR2_JDATA_27 (0x08000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x08000000 */
-#define ADC_JDR2_JDATA_28 (0x10000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x10000000 */
-#define ADC_JDR2_JDATA_29 (0x20000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x20000000 */
-#define ADC_JDR2_JDATA_30 (0x40000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x40000000 */
-#define ADC_JDR2_JDATA_31 (0x80000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x80000000 */
-
-/******************** Bit definition for ADC_JDR3 register ********************/
-#define ADC_JDR3_JDATA_Pos (0U)
-#define ADC_JDR3_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0xFFFFFFFF */
-#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC Injected DATA */
-#define ADC_JDR3_JDATA_0 (0x00000001UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */
-#define ADC_JDR3_JDATA_1 (0x00000002UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */
-#define ADC_JDR3_JDATA_2 (0x00000004UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */
-#define ADC_JDR3_JDATA_3 (0x00000008UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */
-#define ADC_JDR3_JDATA_4 (0x00000010UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */
-#define ADC_JDR3_JDATA_5 (0x00000020UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */
-#define ADC_JDR3_JDATA_6 (0x00000040UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */
-#define ADC_JDR3_JDATA_7 (0x00000080UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */
-#define ADC_JDR3_JDATA_8 (0x00000100UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */
-#define ADC_JDR3_JDATA_9 (0x00000200UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */
-#define ADC_JDR3_JDATA_10 (0x00000400UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */
-#define ADC_JDR3_JDATA_11 (0x00000800UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */
-#define ADC_JDR3_JDATA_12 (0x00001000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */
-#define ADC_JDR3_JDATA_13 (0x00002000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */
-#define ADC_JDR3_JDATA_14 (0x00004000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */
-#define ADC_JDR3_JDATA_15 (0x00008000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */
-#define ADC_JDR3_JDATA_16 (0x00010000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00010000 */
-#define ADC_JDR3_JDATA_17 (0x00020000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00020000 */
-#define ADC_JDR3_JDATA_18 (0x00040000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00040000 */
-#define ADC_JDR3_JDATA_19 (0x00080000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00080000 */
-#define ADC_JDR3_JDATA_20 (0x00100000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00100000 */
-#define ADC_JDR3_JDATA_21 (0x00200000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00200000 */
-#define ADC_JDR3_JDATA_22 (0x00400000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00400000 */
-#define ADC_JDR3_JDATA_23 (0x00800000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00800000 */
-#define ADC_JDR3_JDATA_24 (0x01000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x01000000 */
-#define ADC_JDR3_JDATA_25 (0x02000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x02000000 */
-#define ADC_JDR3_JDATA_26 (0x04000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x04000000 */
-#define ADC_JDR3_JDATA_27 (0x08000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x08000000 */
-#define ADC_JDR3_JDATA_28 (0x10000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x10000000 */
-#define ADC_JDR3_JDATA_29 (0x20000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x20000000 */
-#define ADC_JDR3_JDATA_30 (0x40000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x40000000 */
-#define ADC_JDR3_JDATA_31 (0x80000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x80000000 */
-
-/******************** Bit definition for ADC_JDR4 register ********************/
-#define ADC_JDR4_JDATA_Pos (0U)
-#define ADC_JDR4_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0xFFFFFFFF */
-#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC Injected DATA */
-#define ADC_JDR4_JDATA_0 (0x00000001UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */
-#define ADC_JDR4_JDATA_1 (0x00000002UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */
-#define ADC_JDR4_JDATA_2 (0x00000004UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */
-#define ADC_JDR4_JDATA_3 (0x00000008UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */
-#define ADC_JDR4_JDATA_4 (0x00000010UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */
-#define ADC_JDR4_JDATA_5 (0x00000020UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */
-#define ADC_JDR4_JDATA_6 (0x00000040UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */
-#define ADC_JDR4_JDATA_7 (0x00000080UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */
-#define ADC_JDR4_JDATA_8 (0x00000100UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */
-#define ADC_JDR4_JDATA_9 (0x00000200UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */
-#define ADC_JDR4_JDATA_10 (0x00000400UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */
-#define ADC_JDR4_JDATA_11 (0x00000800UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */
-#define ADC_JDR4_JDATA_12 (0x00001000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */
-#define ADC_JDR4_JDATA_13 (0x00002000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */
-#define ADC_JDR4_JDATA_14 (0x00004000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */
-#define ADC_JDR4_JDATA_15 (0x00008000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */
-#define ADC_JDR4_JDATA_16 (0x00010000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00010000 */
-#define ADC_JDR4_JDATA_17 (0x00020000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00020000 */
-#define ADC_JDR4_JDATA_18 (0x00040000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00040000 */
-#define ADC_JDR4_JDATA_19 (0x00080000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00080000 */
-#define ADC_JDR4_JDATA_20 (0x00100000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00100000 */
-#define ADC_JDR4_JDATA_21 (0x00200000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00200000 */
-#define ADC_JDR4_JDATA_22 (0x00400000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00400000 */
-#define ADC_JDR4_JDATA_23 (0x00800000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00800000 */
-#define ADC_JDR4_JDATA_24 (0x01000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x01000000 */
-#define ADC_JDR4_JDATA_25 (0x02000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x02000000 */
-#define ADC_JDR4_JDATA_26 (0x04000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x04000000 */
-#define ADC_JDR4_JDATA_27 (0x08000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x08000000 */
-#define ADC_JDR4_JDATA_28 (0x10000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x10000000 */
-#define ADC_JDR4_JDATA_29 (0x20000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x20000000 */
-#define ADC_JDR4_JDATA_30 (0x40000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x40000000 */
-#define ADC_JDR4_JDATA_31 (0x80000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x80000000 */
-
-/******************** Bit definition for ADC_AWD2CR register ********************/
-#define ADC_AWD2CR_AWD2CH_Pos (0U)
-#define ADC_AWD2CR_AWD2CH_Msk (0xFFFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x000FFFFF */
-#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC Analog watchdog 2 channel selection */
-#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */
-#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */
-#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */
-#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */
-#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */
-#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */
-#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */
-#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */
-#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */
-#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */
-#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */
-#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */
-#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */
-#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */
-#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */
-#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */
-#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */
-#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */
-#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */
-#define ADC_AWD2CR_AWD2CH_19 (0x80000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00080000 */
-
-/******************** Bit definition for ADC_AWD3CR register ********************/
-#define ADC_AWD3CR_AWD3CH_Pos (0U)
-#define ADC_AWD3CR_AWD3CH_Msk (0xFFFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x000FFFFF */
-#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC Analog watchdog 2 channel selection */
-#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */
-#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */
-#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */
-#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */
-#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */
-#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */
-#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */
-#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */
-#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */
-#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */
-#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */
-#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */
-#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */
-#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */
-#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */
-#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */
-#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */
-#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */
-#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */
-#define ADC_AWD3CR_AWD3CH_19 (0x80000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00080000 */
-
-/******************** Bit definition for ADC_DIFSEL register ********************/
-#define ADC_DIFSEL_DIFSEL_Pos (0U)
-#define ADC_DIFSEL_DIFSEL_Msk (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x000FFFFF */
-#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC differential modes for channels 1 to 18 */
-#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */
-#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */
-#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */
-#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */
-#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */
-#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */
-#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */
-#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */
-#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */
-#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */
-#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */
-#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */
-#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */
-#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */
-#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */
-#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */
-#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */
-#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */
-#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */
-#define ADC_DIFSEL_DIFSEL_19 (0x80000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00080000 */
-
-/******************** Bit definition for ADC_CALFACT register ********************/
-#define ADC_CALFACT_CALFACT_S_Pos (0U)
-#define ADC_CALFACT_CALFACT_S_Msk (0x7FFUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x000007FF */
-#define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factors in single-ended mode */
-#define ADC_CALFACT_CALFACT_S_0 (0x001UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */
-#define ADC_CALFACT_CALFACT_S_1 (0x002UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */
-#define ADC_CALFACT_CALFACT_S_2 (0x004UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */
-#define ADC_CALFACT_CALFACT_S_3 (0x008UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */
-#define ADC_CALFACT_CALFACT_S_4 (0x010UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */
-#define ADC_CALFACT_CALFACT_S_5 (0x020UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */
-#define ADC_CALFACT_CALFACT_S_6 (0x040UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */
-#define ADC_CALFACT_CALFACT_S_7 (0x080UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000080 */
-#define ADC_CALFACT_CALFACT_S_8 (0x100UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000100 */
-#define ADC_CALFACT_CALFACT_S_9 (0x200UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000200 */
-#define ADC_CALFACT_CALFACT_S_10 (0x400UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000400 */
-#define ADC_CALFACT_CALFACT_D_Pos (16U)
-#define ADC_CALFACT_CALFACT_D_Msk (0x7FFUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x07FF0000 */
-#define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factors in differential mode */
-#define ADC_CALFACT_CALFACT_D_0 (0x001UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */
-#define ADC_CALFACT_CALFACT_D_1 (0x002UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */
-#define ADC_CALFACT_CALFACT_D_2 (0x004UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */
-#define ADC_CALFACT_CALFACT_D_3 (0x008UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */
-#define ADC_CALFACT_CALFACT_D_4 (0x010UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */
-#define ADC_CALFACT_CALFACT_D_5 (0x020UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */
-#define ADC_CALFACT_CALFACT_D_6 (0x040UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */
-#define ADC_CALFACT_CALFACT_D_7 (0x080UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00800000 */
-#define ADC_CALFACT_CALFACT_D_8 (0x100UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x01000000 */
-#define ADC_CALFACT_CALFACT_D_9 (0x200UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x02000000 */
-#define ADC_CALFACT_CALFACT_D_10 (0x400UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x04000000 */
-
-/******************** Bit definition for ADC_CALFACT2 register ********************/
-#define ADC_CALFACT2_LINCALFACT_Pos (0U)
-#define ADC_CALFACT2_LINCALFACT_Msk (0x3FFFFFFFUL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x3FFFFFFF */
-#define ADC_CALFACT2_LINCALFACT ADC_CALFACT2_LINCALFACT_Msk /*!< ADC Linearity calibration factors */
-#define ADC_CALFACT2_LINCALFACT_0 (0x00000001UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000001 */
-#define ADC_CALFACT2_LINCALFACT_1 (0x00000002UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000002 */
-#define ADC_CALFACT2_LINCALFACT_2 (0x00000004UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000004 */
-#define ADC_CALFACT2_LINCALFACT_3 (0x00000008UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000008 */
-#define ADC_CALFACT2_LINCALFACT_4 (0x00000010UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000010 */
-#define ADC_CALFACT2_LINCALFACT_5 (0x00000020UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000020 */
-#define ADC_CALFACT2_LINCALFACT_6 (0x00000040UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000040 */
-#define ADC_CALFACT2_LINCALFACT_7 (0x00000080UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000080 */
-#define ADC_CALFACT2_LINCALFACT_8 (0x00000100UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000100 */
-#define ADC_CALFACT2_LINCALFACT_9 (0x00000200UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000200 */
-#define ADC_CALFACT2_LINCALFACT_10 (0x00000400UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000400 */
-#define ADC_CALFACT2_LINCALFACT_11 (0x00000800UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000800 */
-#define ADC_CALFACT2_LINCALFACT_12 (0x00001000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00001000 */
-#define ADC_CALFACT2_LINCALFACT_13 (0x00002000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00002000 */
-#define ADC_CALFACT2_LINCALFACT_14 (0x00004000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00004000 */
-#define ADC_CALFACT2_LINCALFACT_15 (0x00008000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00008000 */
-#define ADC_CALFACT2_LINCALFACT_16 (0x00010000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00010000 */
-#define ADC_CALFACT2_LINCALFACT_17 (0x00020000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00020000 */
-#define ADC_CALFACT2_LINCALFACT_18 (0x00040000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00040000 */
-#define ADC_CALFACT2_LINCALFACT_19 (0x00080000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00080000 */
-#define ADC_CALFACT2_LINCALFACT_20 (0x00100000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00100000 */
-#define ADC_CALFACT2_LINCALFACT_21 (0x00200000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00200000 */
-#define ADC_CALFACT2_LINCALFACT_22 (0x00400000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00400000 */
-#define ADC_CALFACT2_LINCALFACT_23 (0x00800000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00800000 */
-#define ADC_CALFACT2_LINCALFACT_24 (0x01000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x01000000 */
-#define ADC_CALFACT2_LINCALFACT_25 (0x02000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x02000000 */
-#define ADC_CALFACT2_LINCALFACT_26 (0x04000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x04000000 */
-#define ADC_CALFACT2_LINCALFACT_27 (0x08000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x08000000 */
-#define ADC_CALFACT2_LINCALFACT_28 (0x10000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x10000000 */
-#define ADC_CALFACT2_LINCALFACT_29 (0x20000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x20000000 */
-
-/************************* ADC Common registers *****************************/
-/******************** Bit definition for ADC_CSR register ********************/
-#define ADC_CSR_ADRDY_MST_Pos (0U)
-#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */
-#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< Master ADC ready */
-#define ADC_CSR_EOSMP_MST_Pos (1U)
-#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */
-#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< End of sampling phase flag of the master ADC */
-#define ADC_CSR_EOC_MST_Pos (2U)
-#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */
-#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< End of regular conversion of the master ADC */
-#define ADC_CSR_EOS_MST_Pos (3U)
-#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */
-#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< End of regular sequence flag of the master ADC */
-#define ADC_CSR_OVR_MST_Pos (4U)
-#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */
-#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< Overrun flag of the master ADC */
-#define ADC_CSR_JEOC_MST_Pos (5U)
-#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */
-#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< End of injected conversion of the master ADC */
-#define ADC_CSR_JEOS_MST_Pos (6U)
-#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */
-#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< End of injected sequence flag of the master ADC */
-#define ADC_CSR_AWD1_MST_Pos (7U)
-#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */
-#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< Analog watchdog 1 flag of the master ADC */
-#define ADC_CSR_AWD2_MST_Pos (8U)
-#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */
-#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< Analog watchdog 2 flag of the master ADC */
-#define ADC_CSR_AWD3_MST_Pos (9U)
-#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */
-#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< Analog watchdog 3 flag of the master ADC */
-#define ADC_CSR_JQOVF_MST_Pos (10U)
-#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */
-#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< Injected context queue overflow flag of the master ADC */
-#define ADC_CSR_ADRDY_SLV_Pos (16U)
-#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */
-#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< Slave ADC ready */
-#define ADC_CSR_EOSMP_SLV_Pos (17U)
-#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */
-#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< End of sampling phase flag of the slave ADC */
-#define ADC_CSR_EOC_SLV_Pos (18U)
-#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */
-#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< End of regular conversion of the slave ADC */
-#define ADC_CSR_EOS_SLV_Pos (19U)
-#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */
-#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC */
-#define ADC_CSR_OVR_SLV_Pos (20U)
-#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */
-#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */
-#define ADC_CSR_JEOC_SLV_Pos (21U)
-#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */
-#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< End of injected conversion of the slave ADC */
-#define ADC_CSR_JEOS_SLV_Pos (22U)
-#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */
-#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< End of injected sequence flag of the slave ADC */
-#define ADC_CSR_AWD1_SLV_Pos (23U)
-#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */
-#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< Analog watchdog 1 flag of the slave ADC */
-#define ADC_CSR_AWD2_SLV_Pos (24U)
-#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */
-#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< Analog watchdog 2 flag of the slave ADC */
-#define ADC_CSR_AWD3_SLV_Pos (25U)
-#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */
-#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< Analog watchdog 3 flag of the slave ADC */
-#define ADC_CSR_JQOVF_SLV_Pos (26U)
-#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */
-#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< Injected context queue overflow flag of the slave ADC */
-
-/******************** Bit definition for ADC_CCR register ********************/
-#define ADC_CCR_DUAL_Pos (0U)
-#define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */
-#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< Dual ADC mode selection */
-#define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */
-#define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */
-#define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */
-#define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */
-#define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */
-
-#define ADC_CCR_DELAY_Pos (8U)
-#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */
-#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< Delay between 2 sampling phases */
-#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */
-#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */
-#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */
-#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */
-
-
-#define ADC_CCR_DAMDF_Pos (14U)
-#define ADC_CCR_DAMDF_Msk (0x3UL << ADC_CCR_DAMDF_Pos) /*!< 0x0000C000 */
-#define ADC_CCR_DAMDF ADC_CCR_DAMDF_Msk /*!< Dual ADC mode Data format */
-#define ADC_CCR_DAMDF_0 (0x1UL << ADC_CCR_DAMDF_Pos) /*!< 0x00004000 */
-#define ADC_CCR_DAMDF_1 (0x2UL << ADC_CCR_DAMDF_Pos) /*!< 0x00008000 */
-
-#define ADC_CCR_CKMODE_Pos (16U)
-#define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */
-#define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC clock mode */
-#define ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */
-#define ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */
-
-#define ADC_CCR_PRESC_Pos (18U)
-#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */
-#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC prescaler */
-#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */
-#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */
-#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */
-#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */
-
-#define ADC_CCR_VREFEN_Pos (22U)
-#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */
-#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< VREFINT enable */
-#define ADC_CCR_TSEN_Pos (23U)
-#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */
-#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< Temperature sensor enable */
-#define ADC_CCR_VBATEN_Pos (24U)
-#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */
-#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< VBAT enable */
-
-/******************** Bit definition for ADC_CDR register *******************/
-#define ADC_CDR_RDATA_MST_Pos (0U)
-#define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */
-#define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */
-
-#define ADC_CDR_RDATA_SLV_Pos (16U)
-#define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */
-#define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */
-
-/******************** Bit definition for ADC_CDR2 register ******************/
-#define ADC_CDR2_RDATA_ALT_Pos (0U)
-#define ADC_CDR2_RDATA_ALT_Msk (0xFFFFFFFFUL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0xFFFFFFFF */
-#define ADC_CDR2_RDATA_ALT ADC_CDR2_RDATA_ALT_Msk /*!< Regular data of the master/slave alternated ADCs */
-
-
-/******************************************************************************/
-/* */
-/* VREFBUF */
-/* */
-/******************************************************************************/
-/******************* Bit definition for VREFBUF_CSR register ****************/
-#define VREFBUF_CSR_ENVR_Pos (0U)
-#define VREFBUF_CSR_ENVR_Msk (0x1UL << VREFBUF_CSR_ENVR_Pos) /*!< 0x00000001 */
-#define VREFBUF_CSR_ENVR VREFBUF_CSR_ENVR_Msk /*!*/
-#define DAC_CR_CEN1_Pos (14U)
-#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */
-#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/
-
-#define DAC_CR_EN2_Pos (16U)
-#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */
-#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/
-#define DAC_CR_CEN2_Pos (30U)
-#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */
-#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/
-
-/***************** Bit definition for DAC_SWTRIGR register ******************/
-#define DAC_SWTRIGR_SWTRIG1_Pos (0U)
-#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */
-#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!> 1) /* 1 MB */
-#define FLASH_SECTOR_SIZE 0x00020000UL /* 128 KB */
-#define FLASH_LATENCY_DEFAULT FLASH_ACR_LATENCY_7WS /* FLASH Seven Latency cycles */
-#define FLASH_NB_32BITWORD_IN_FLASHWORD 8U /* 256 bits */
-#define DUAL_BANK /* Dual-bank Flash */
-
-/******************* Bits definition for FLASH_ACR register **********************/
-#define FLASH_ACR_LATENCY_Pos (0U)
-#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */
-#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Read Latency */
-#define FLASH_ACR_LATENCY_0WS (0x00000000UL)
-#define FLASH_ACR_LATENCY_1WS (0x00000001UL)
-#define FLASH_ACR_LATENCY_2WS (0x00000002UL)
-#define FLASH_ACR_LATENCY_3WS (0x00000003UL)
-#define FLASH_ACR_LATENCY_4WS (0x00000004UL)
-#define FLASH_ACR_LATENCY_5WS (0x00000005UL)
-#define FLASH_ACR_LATENCY_6WS (0x00000006UL)
-#define FLASH_ACR_LATENCY_7WS (0x00000007UL)
-#define FLASH_ACR_LATENCY_8WS (0x00000008UL)
-#define FLASH_ACR_LATENCY_9WS (0x00000009UL)
-#define FLASH_ACR_LATENCY_10WS (0x0000000AUL)
-#define FLASH_ACR_LATENCY_11WS (0x0000000BUL)
-#define FLASH_ACR_LATENCY_12WS (0x0000000CUL)
-#define FLASH_ACR_LATENCY_13WS (0x0000000DUL)
-#define FLASH_ACR_LATENCY_14WS (0x0000000EUL)
-#define FLASH_ACR_LATENCY_15WS (0x0000000FUL)
-#define FLASH_ACR_WRHIGHFREQ_Pos (4U)
-#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */
-#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */
-#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */
-#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */
-
-/******************* Bits definition for FLASH_CR register ***********************/
-#define FLASH_CR_LOCK_Pos (0U)
-#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x00000001 */
-#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk /*!< Configuration lock bit */
-#define FLASH_CR_PG_Pos (1U)
-#define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos) /*!< 0x00000002 */
-#define FLASH_CR_PG FLASH_CR_PG_Msk /*!< Internal buffer control bit */
-#define FLASH_CR_SER_Pos (2U)
-#define FLASH_CR_SER_Msk (0x1UL << FLASH_CR_SER_Pos) /*!< 0x00000004 */
-#define FLASH_CR_SER FLASH_CR_SER_Msk /*!< Sector erase request */
-#define FLASH_CR_BER_Pos (3U)
-#define FLASH_CR_BER_Msk (0x1UL << FLASH_CR_BER_Pos) /*!< 0x00000008 */
-#define FLASH_CR_BER FLASH_CR_BER_Msk /*!< Bank erase request */
-#define FLASH_CR_PSIZE_Pos (4U)
-#define FLASH_CR_PSIZE_Msk (0x3UL << FLASH_CR_PSIZE_Pos) /*!< 0x00000030 */
-#define FLASH_CR_PSIZE FLASH_CR_PSIZE_Msk /*!< Program size */
-#define FLASH_CR_PSIZE_0 (0x1UL << FLASH_CR_PSIZE_Pos) /*!< 0x00000010 */
-#define FLASH_CR_PSIZE_1 (0x2UL << FLASH_CR_PSIZE_Pos) /*!< 0x00000020 */
-#define FLASH_CR_FW_Pos (6U)
-#define FLASH_CR_FW_Msk (0x1UL << FLASH_CR_FW_Pos) /*!< 0x00000040 */
-#define FLASH_CR_FW FLASH_CR_FW_Msk /*!< Write forcing control bit */
-#define FLASH_CR_START_Pos (7U)
-#define FLASH_CR_START_Msk (0x1UL << FLASH_CR_START_Pos) /*!< 0x00000080 */
-#define FLASH_CR_START FLASH_CR_START_Msk /*!< Erase start control bit */
-#define FLASH_CR_SNB_Pos (8U)
-#define FLASH_CR_SNB_Msk (0x7UL << FLASH_CR_SNB_Pos) /*!< 0x00000700 */
-#define FLASH_CR_SNB FLASH_CR_SNB_Msk /*!< Sector erase selection number */
-#define FLASH_CR_SNB_0 (0x1UL << FLASH_CR_SNB_Pos) /*!< 0x00000100 */
-#define FLASH_CR_SNB_1 (0x2UL << FLASH_CR_SNB_Pos) /*!< 0x00000200 */
-#define FLASH_CR_SNB_2 (0x4UL << FLASH_CR_SNB_Pos) /*!< 0x00000400 */
-#define FLASH_CR_CRC_EN_Pos (15U)
-#define FLASH_CR_CRC_EN_Msk (0x1UL << FLASH_CR_CRC_EN_Pos) /*!< 0x00008000 */
-#define FLASH_CR_CRC_EN FLASH_CR_CRC_EN_Msk /*!< CRC control bit */
-#define FLASH_CR_EOPIE_Pos (16U)
-#define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x00010000 */
-#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk /*!< End-of-program interrupt control bit */
-#define FLASH_CR_WRPERRIE_Pos (17U)
-#define FLASH_CR_WRPERRIE_Msk (0x1UL << FLASH_CR_WRPERRIE_Pos) /*!< 0x00020000 */
-#define FLASH_CR_WRPERRIE FLASH_CR_WRPERRIE_Msk /*!< Write protection error interrupt enable bit */
-#define FLASH_CR_PGSERRIE_Pos (18U)
-#define FLASH_CR_PGSERRIE_Msk (0x1UL << FLASH_CR_PGSERRIE_Pos) /*!< 0x00040000 */
-#define FLASH_CR_PGSERRIE FLASH_CR_PGSERRIE_Msk /*!< Programming sequence error interrupt enable bit */
-#define FLASH_CR_STRBERRIE_Pos (19U)
-#define FLASH_CR_STRBERRIE_Msk (0x1UL << FLASH_CR_STRBERRIE_Pos) /*!< 0x00080000 */
-#define FLASH_CR_STRBERRIE FLASH_CR_STRBERRIE_Msk /*!< Strobe error interrupt enable bit */
-#define FLASH_CR_INCERRIE_Pos (21U)
-#define FLASH_CR_INCERRIE_Msk (0x1UL << FLASH_CR_INCERRIE_Pos) /*!< 0x00200000 */
-#define FLASH_CR_INCERRIE FLASH_CR_INCERRIE_Msk /*!< Inconsistency error interrupt enable bit */
-#define FLASH_CR_OPERRIE_Pos (22U)
-#define FLASH_CR_OPERRIE_Msk (0x1UL << FLASH_CR_OPERRIE_Pos) /*!< 0x00400000 */
-#define FLASH_CR_OPERRIE FLASH_CR_OPERRIE_Msk /*!< Write/erase error interrupt enable bit */
-#define FLASH_CR_RDPERRIE_Pos (23U)
-#define FLASH_CR_RDPERRIE_Msk (0x1UL << FLASH_CR_RDPERRIE_Pos) /*!< 0x00800000 */
-#define FLASH_CR_RDPERRIE FLASH_CR_RDPERRIE_Msk /*!< Read protection error interrupt enable bit */
-#define FLASH_CR_RDSERRIE_Pos (24U)
-#define FLASH_CR_RDSERRIE_Msk (0x1UL << FLASH_CR_RDSERRIE_Pos) /*!< 0x01000000 */
-#define FLASH_CR_RDSERRIE FLASH_CR_RDSERRIE_Msk /*!< Secure error interrupt enable bit */
-#define FLASH_CR_SNECCERRIE_Pos (25U)
-#define FLASH_CR_SNECCERRIE_Msk (0x1UL << FLASH_CR_SNECCERRIE_Pos) /*!< 0x02000000 */
-#define FLASH_CR_SNECCERRIE FLASH_CR_SNECCERRIE_Msk /*!< ECC single correction error interrupt enable bit */
-#define FLASH_CR_DBECCERRIE_Pos (26U)
-#define FLASH_CR_DBECCERRIE_Msk (0x1UL << FLASH_CR_DBECCERRIE_Pos) /*!< 0x04000000 */
-#define FLASH_CR_DBECCERRIE FLASH_CR_DBECCERRIE_Msk /*!< ECC double detection error interrupt enable bit */
-#define FLASH_CR_CRCENDIE_Pos (27U)
-#define FLASH_CR_CRCENDIE_Msk (0x1UL << FLASH_CR_CRCENDIE_Pos) /*!< 0x08000000 */
-#define FLASH_CR_CRCENDIE FLASH_CR_CRCENDIE_Msk /*!< CRC end of calculation interrupt enable bit */
-#define FLASH_CR_CRCRDERRIE_Pos (28U)
-#define FLASH_CR_CRCRDERRIE_Msk (0x1UL << FLASH_CR_CRCRDERRIE_Pos) /*!< 0x10000000 */
-#define FLASH_CR_CRCRDERRIE FLASH_CR_CRCRDERRIE_Msk /*!< CRC read error interrupt enable bit */
-
-/******************* Bits definition for FLASH_SR register ***********************/
-#define FLASH_SR_BSY_Pos (0U)
-#define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) /*!< 0x00000001 */
-#define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy flag */
-#define FLASH_SR_WBNE_Pos (1U)
-#define FLASH_SR_WBNE_Msk (0x1UL << FLASH_SR_WBNE_Pos) /*!< 0x00000002 */
-#define FLASH_SR_WBNE FLASH_SR_WBNE_Msk /*!< Write buffer not empty flag */
-#define FLASH_SR_QW_Pos (2U)
-#define FLASH_SR_QW_Msk (0x1UL << FLASH_SR_QW_Pos) /*!< 0x00000004 */
-#define FLASH_SR_QW FLASH_SR_QW_Msk /*!< Wait queue flag */
-#define FLASH_SR_CRC_BUSY_Pos (3U)
-#define FLASH_SR_CRC_BUSY_Msk (0x1UL << FLASH_SR_CRC_BUSY_Pos) /*!< 0x00000008 */
-#define FLASH_SR_CRC_BUSY FLASH_SR_CRC_BUSY_Msk /*!< CRC busy flag */
-#define FLASH_SR_EOP_Pos (16U)
-#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00010000 */
-#define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End-of-program flag */
-#define FLASH_SR_WRPERR_Pos (17U)
-#define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00020000 */
-#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk /*!< Write protection error flag */
-#define FLASH_SR_PGSERR_Pos (18U)
-#define FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos) /*!< 0x00040000 */
-#define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk /*!< Programming sequence error flag */
-#define FLASH_SR_STRBERR_Pos (19U)
-#define FLASH_SR_STRBERR_Msk (0x1UL << FLASH_SR_STRBERR_Pos) /*!< 0x00080000 */
-#define FLASH_SR_STRBERR FLASH_SR_STRBERR_Msk /*!< Strobe error flag */
-#define FLASH_SR_INCERR_Pos (21U)
-#define FLASH_SR_INCERR_Msk (0x1UL << FLASH_SR_INCERR_Pos) /*!< 0x00200000 */
-#define FLASH_SR_INCERR FLASH_SR_INCERR_Msk /*!< Inconsistency error flag */
-#define FLASH_SR_OPERR_Pos (22U)
-#define FLASH_SR_OPERR_Msk (0x1UL << FLASH_SR_OPERR_Pos) /*!< 0x00400000 */
-#define FLASH_SR_OPERR FLASH_SR_OPERR_Msk /*!< Write/erase error flag */
-#define FLASH_SR_RDPERR_Pos (23U)
-#define FLASH_SR_RDPERR_Msk (0x1UL << FLASH_SR_RDPERR_Pos) /*!< 0x00800000 */
-#define FLASH_SR_RDPERR FLASH_SR_RDPERR_Msk /*!< Read protection error flag */
-#define FLASH_SR_RDSERR_Pos (24U)
-#define FLASH_SR_RDSERR_Msk (0x1UL << FLASH_SR_RDSERR_Pos) /*!< 0x01000000 */
-#define FLASH_SR_RDSERR FLASH_SR_RDSERR_Msk /*!< Secure error flag */
-#define FLASH_SR_SNECCERR_Pos (25U)
-#define FLASH_SR_SNECCERR_Msk (0x1UL << FLASH_SR_SNECCERR_Pos) /*!< 0x02000000 */
-#define FLASH_SR_SNECCERR FLASH_SR_SNECCERR_Msk /*!< Single correction error flag */
-#define FLASH_SR_DBECCERR_Pos (26U)
-#define FLASH_SR_DBECCERR_Msk (0x1UL << FLASH_SR_DBECCERR_Pos) /*!< 0x04000000 */
-#define FLASH_SR_DBECCERR FLASH_SR_DBECCERR_Msk /*!< ECC double detection error flag */
-#define FLASH_SR_CRCEND_Pos (27U)
-#define FLASH_SR_CRCEND_Msk (0x1UL << FLASH_SR_CRCEND_Pos) /*!< 0x08000000 */
-#define FLASH_SR_CRCEND FLASH_SR_CRCEND_Msk /*!< CRC end of calculation flag */
-#define FLASH_SR_CRCRDERR_Pos (28U)
-#define FLASH_SR_CRCRDERR_Msk (0x1UL << FLASH_SR_CRCRDERR_Pos) /*!< 0x10000000 */
-#define FLASH_SR_CRCRDERR FLASH_SR_CRCRDERR_Msk /*!< CRC read error flag */
-
-/******************* Bits definition for FLASH_CCR register *******************/
-#define FLASH_CCR_CLR_EOP_Pos (16U)
-#define FLASH_CCR_CLR_EOP_Msk (0x1UL << FLASH_CCR_CLR_EOP_Pos) /*!< 0x00010000 */
-#define FLASH_CCR_CLR_EOP FLASH_CCR_CLR_EOP_Msk /*!< EOP flag clear bit */
-#define FLASH_CCR_CLR_WRPERR_Pos (17U)
-#define FLASH_CCR_CLR_WRPERR_Msk (0x1UL << FLASH_CCR_CLR_WRPERR_Pos) /*!< 0x00020000 */
-#define FLASH_CCR_CLR_WRPERR FLASH_CCR_CLR_WRPERR_Msk /*!< WRPERR flag clear bit */
-#define FLASH_CCR_CLR_PGSERR_Pos (18U)
-#define FLASH_CCR_CLR_PGSERR_Msk (0x1UL << FLASH_CCR_CLR_PGSERR_Pos) /*!< 0x00040000 */
-#define FLASH_CCR_CLR_PGSERR FLASH_CCR_CLR_PGSERR_Msk /*!< PGSERR flag clear bit */
-#define FLASH_CCR_CLR_STRBERR_Pos (19U)
-#define FLASH_CCR_CLR_STRBERR_Msk (0x1UL << FLASH_CCR_CLR_STRBERR_Pos) /*!< 0x00080000 */
-#define FLASH_CCR_CLR_STRBERR FLASH_CCR_CLR_STRBERR_Msk /*!< STRBERR flag clear bit */
-#define FLASH_CCR_CLR_INCERR_Pos (21U)
-#define FLASH_CCR_CLR_INCERR_Msk (0x1UL << FLASH_CCR_CLR_INCERR_Pos) /*!< 0x00200000 */
-#define FLASH_CCR_CLR_INCERR FLASH_CCR_CLR_INCERR_Msk /*!< INCERR flag clear bit */
-#define FLASH_CCR_CLR_OPERR_Pos (22U)
-#define FLASH_CCR_CLR_OPERR_Msk (0x1UL << FLASH_CCR_CLR_OPERR_Pos) /*!< 0x00400000 */
-#define FLASH_CCR_CLR_OPERR FLASH_CCR_CLR_OPERR_Msk /*!< OPERR flag clear bit */
-#define FLASH_CCR_CLR_RDPERR_Pos (23U)
-#define FLASH_CCR_CLR_RDPERR_Msk (0x1UL << FLASH_CCR_CLR_RDPERR_Pos) /*!< 0x00800000 */
-#define FLASH_CCR_CLR_RDPERR FLASH_CCR_CLR_RDPERR_Msk /*!< RDPERR flag clear bit */
-#define FLASH_CCR_CLR_RDSERR_Pos (24U)
-#define FLASH_CCR_CLR_RDSERR_Msk (0x1UL << FLASH_CCR_CLR_RDSERR_Pos) /*!< 0x01000000 */
-#define FLASH_CCR_CLR_RDSERR FLASH_CCR_CLR_RDSERR_Msk /*!< RDSERR flag clear bit */
-#define FLASH_CCR_CLR_SNECCERR_Pos (25U)
-#define FLASH_CCR_CLR_SNECCERR_Msk (0x1UL << FLASH_CCR_CLR_SNECCERR_Pos) /*!< 0x02000000 */
-#define FLASH_CCR_CLR_SNECCERR FLASH_CCR_CLR_SNECCERR_Msk /*!< SNECCERR flag clear bit */
-#define FLASH_CCR_CLR_DBECCERR_Pos (26U)
-#define FLASH_CCR_CLR_DBECCERR_Msk (0x1UL << FLASH_CCR_CLR_DBECCERR_Pos) /*!< 0x04000000 */
-#define FLASH_CCR_CLR_DBECCERR FLASH_CCR_CLR_DBECCERR_Msk /*!< DBECCERR flag clear bit */
-#define FLASH_CCR_CLR_CRCEND_Pos (27U)
-#define FLASH_CCR_CLR_CRCEND_Msk (0x1UL << FLASH_CCR_CLR_CRCEND_Pos) /*!< 0x08000000 */
-#define FLASH_CCR_CLR_CRCEND FLASH_CCR_CLR_CRCEND_Msk /*!< CRCEND flag clear bit */
-#define FLASH_CCR_CLR_CRCRDERR_Pos (28U)
-#define FLASH_CCR_CLR_CRCRDERR_Msk (0x1UL << FLASH_CCR_CLR_CRCRDERR_Pos) /*!< 0x10000000 */
-#define FLASH_CCR_CLR_CRCRDERR FLASH_CCR_CLR_CRCRDERR_Msk /*!< CRCRDERR flag clear bit */
-
-/******************* Bits definition for FLASH_OPTCR register *******************/
-#define FLASH_OPTCR_OPTLOCK_Pos (0U)
-#define FLASH_OPTCR_OPTLOCK_Msk (0x1UL << FLASH_OPTCR_OPTLOCK_Pos) /*!< 0x00000001 */
-#define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk /*!< FLASH_OPTCR lock option configuration bit */
-#define FLASH_OPTCR_OPTSTART_Pos (1U)
-#define FLASH_OPTCR_OPTSTART_Msk (0x1UL << FLASH_OPTCR_OPTSTART_Pos) /*!< 0x00000002 */
-#define FLASH_OPTCR_OPTSTART FLASH_OPTCR_OPTSTART_Msk /*!< Option byte start change option configuration bit */
-#define FLASH_OPTCR_MER_Pos (4U)
-#define FLASH_OPTCR_MER_Msk (0x1UL << FLASH_OPTCR_MER_Pos) /*!< 0x00000010 */
-#define FLASH_OPTCR_MER FLASH_OPTCR_MER_Msk /*!< Mass erase request */
-#define FLASH_OPTCR_OPTCHANGEERRIE_Pos (30U)
-#define FLASH_OPTCR_OPTCHANGEERRIE_Msk (0x1UL << FLASH_OPTCR_OPTCHANGEERRIE_Pos) /*!< 0x40000000 */
-#define FLASH_OPTCR_OPTCHANGEERRIE FLASH_OPTCR_OPTCHANGEERRIE_Msk /*!< Option byte change error interrupt enable bit */
-#define FLASH_OPTCR_SWAP_BANK_Pos (31U)
-#define FLASH_OPTCR_SWAP_BANK_Msk (0x1UL << FLASH_OPTCR_SWAP_BANK_Pos) /*!< 0x80000000 */
-#define FLASH_OPTCR_SWAP_BANK FLASH_OPTCR_SWAP_BANK_Msk /*!< Bank swapping option configuration bit */
-
-/******************* Bits definition for FLASH_OPTSR register ***************/
-#define FLASH_OPTSR_OPT_BUSY_Pos (0U)
-#define FLASH_OPTSR_OPT_BUSY_Msk (0x1UL << FLASH_OPTSR_OPT_BUSY_Pos) /*!< 0x00000001 */
-#define FLASH_OPTSR_OPT_BUSY FLASH_OPTSR_OPT_BUSY_Msk /*!< Option byte change ongoing flag */
-#define FLASH_OPTSR_BOR_LEV_Pos (2U)
-#define FLASH_OPTSR_BOR_LEV_Msk (0x3UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x0000000C */
-#define FLASH_OPTSR_BOR_LEV FLASH_OPTSR_BOR_LEV_Msk /*!< Brownout level option status bit */
-#define FLASH_OPTSR_BOR_LEV_0 (0x1UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000004 */
-#define FLASH_OPTSR_BOR_LEV_1 (0x2UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000008 */
-#define FLASH_OPTSR_IWDG1_SW_Pos (4U)
-#define FLASH_OPTSR_IWDG1_SW_Msk (0x1UL << FLASH_OPTSR_IWDG1_SW_Pos) /*!< 0x00000010 */
-#define FLASH_OPTSR_IWDG1_SW FLASH_OPTSR_IWDG1_SW_Msk /*!< IWDG1 control mode option status bit */
-#define FLASH_OPTSR_NRST_STOP_D1_Pos (6U)
-#define FLASH_OPTSR_NRST_STOP_D1_Msk (0x1UL << FLASH_OPTSR_NRST_STOP_D1_Pos) /*!< 0x00000040 */
-#define FLASH_OPTSR_NRST_STOP_D1 FLASH_OPTSR_NRST_STOP_D1_Msk /*!< D1 domain DStop entry reset option status bit */
-#define FLASH_OPTSR_NRST_STBY_D1_Pos (7U)
-#define FLASH_OPTSR_NRST_STBY_D1_Msk (0x1UL << FLASH_OPTSR_NRST_STBY_D1_Pos) /*!< 0x00000080 */
-#define FLASH_OPTSR_NRST_STBY_D1 FLASH_OPTSR_NRST_STBY_D1_Msk /*!< D1 domain DStandby entry reset option status bit */
-#define FLASH_OPTSR_RDP_Pos (8U)
-#define FLASH_OPTSR_RDP_Msk (0xFFUL << FLASH_OPTSR_RDP_Pos) /*!< 0x0000FF00 */
-#define FLASH_OPTSR_RDP FLASH_OPTSR_RDP_Msk /*!< Readout protection level option status byte */
-#define FLASH_OPTSR_FZ_IWDG_STOP_Pos (17U)
-#define FLASH_OPTSR_FZ_IWDG_STOP_Msk (0x1UL << FLASH_OPTSR_FZ_IWDG_STOP_Pos) /*!< 0x00020000 */
-#define FLASH_OPTSR_FZ_IWDG_STOP FLASH_OPTSR_FZ_IWDG_STOP_Msk /*!< IWDG Stop mode freeze option status bit */
-#define FLASH_OPTSR_FZ_IWDG_SDBY_Pos (18U)
-#define FLASH_OPTSR_FZ_IWDG_SDBY_Msk (0x1UL << FLASH_OPTSR_FZ_IWDG_SDBY_Pos) /*!< 0x00040000 */
-#define FLASH_OPTSR_FZ_IWDG_SDBY FLASH_OPTSR_FZ_IWDG_SDBY_Msk /*!< IWDG Standby mode freeze option status bit */
-#define FLASH_OPTSR_ST_RAM_SIZE_Pos (19U)
-#define FLASH_OPTSR_ST_RAM_SIZE_Msk (0x3UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00180000 */
-#define FLASH_OPTSR_ST_RAM_SIZE FLASH_OPTSR_ST_RAM_SIZE_Msk /*!< ST RAM size option status */
-#define FLASH_OPTSR_ST_RAM_SIZE_0 (0x1UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00080000 */
-#define FLASH_OPTSR_ST_RAM_SIZE_1 (0x2UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00100000 */
-#define FLASH_OPTSR_SECURITY_Pos (21U)
-#define FLASH_OPTSR_SECURITY_Msk (0x1UL << FLASH_OPTSR_SECURITY_Pos) /*!< 0x00200000 */
-#define FLASH_OPTSR_SECURITY FLASH_OPTSR_SECURITY_Msk /*!< Security enable option status bit */
-#define FLASH_OPTSR_IO_HSLV_Pos (29U)
-#define FLASH_OPTSR_IO_HSLV_Msk (0x1UL << FLASH_OPTSR_IO_HSLV_Pos) /*!< 0x20000000 */
-#define FLASH_OPTSR_IO_HSLV FLASH_OPTSR_IO_HSLV_Msk /*!< I/O high-speed at low-voltage status bit */
-#define FLASH_OPTSR_OPTCHANGEERR_Pos (30U)
-#define FLASH_OPTSR_OPTCHANGEERR_Msk (0x1UL << FLASH_OPTSR_OPTCHANGEERR_Pos) /*!< 0x40000000 */
-#define FLASH_OPTSR_OPTCHANGEERR FLASH_OPTSR_OPTCHANGEERR_Msk /*!< Option byte change error flag */
-#define FLASH_OPTSR_SWAP_BANK_OPT_Pos (31U)
-#define FLASH_OPTSR_SWAP_BANK_OPT_Msk (0x1UL << FLASH_OPTSR_SWAP_BANK_OPT_Pos) /*!< 0x80000000 */
-#define FLASH_OPTSR_SWAP_BANK_OPT FLASH_OPTSR_SWAP_BANK_OPT_Msk /*!< Bank swapping option status bit */
-
-/******************* Bits definition for FLASH_OPTCCR register *******************/
-#define FLASH_OPTCCR_CLR_OPTCHANGEERR_Pos (30U)
-#define FLASH_OPTCCR_CLR_OPTCHANGEERR_Msk (0x1UL << FLASH_OPTCCR_CLR_OPTCHANGEERR_Pos) /*!< 0x40000000 */
-#define FLASH_OPTCCR_CLR_OPTCHANGEERR FLASH_OPTCCR_CLR_OPTCHANGEERR_Msk /*!< OPTCHANGEERR reset bit */
-
-/******************* Bits definition for FLASH_PRAR register *********************/
-#define FLASH_PRAR_PROT_AREA_START_Pos (0U)
-#define FLASH_PRAR_PROT_AREA_START_Msk (0xFFFUL << FLASH_PRAR_PROT_AREA_START_Pos) /*!< 0x00000FFF */
-#define FLASH_PRAR_PROT_AREA_START FLASH_PRAR_PROT_AREA_START_Msk /*!< PCROP area start status bits */
-#define FLASH_PRAR_PROT_AREA_END_Pos (16U)
-#define FLASH_PRAR_PROT_AREA_END_Msk (0xFFFUL << FLASH_PRAR_PROT_AREA_END_Pos) /*!< 0x0FFF0000 */
-#define FLASH_PRAR_PROT_AREA_END FLASH_PRAR_PROT_AREA_END_Msk /*!< PCROP area end status bits */
-#define FLASH_PRAR_DMEP_Pos (31U)
-#define FLASH_PRAR_DMEP_Msk (0x1UL << FLASH_PRAR_DMEP_Pos) /*!< 0x80000000 */
-#define FLASH_PRAR_DMEP FLASH_PRAR_DMEP_Msk /*!< PCROP protected erase enable option status bit */
-
-/******************* Bits definition for FLASH_SCAR register *********************/
-#define FLASH_SCAR_SEC_AREA_START_Pos (0U)
-#define FLASH_SCAR_SEC_AREA_START_Msk (0xFFFUL << FLASH_SCAR_SEC_AREA_START_Pos) /*!< 0x00000FFF */
-#define FLASH_SCAR_SEC_AREA_START FLASH_SCAR_SEC_AREA_START_Msk /*!< Secure-only area start status bits */
-#define FLASH_SCAR_SEC_AREA_END_Pos (16U)
-#define FLASH_SCAR_SEC_AREA_END_Msk (0xFFFUL << FLASH_SCAR_SEC_AREA_END_Pos) /*!< 0x0FFF0000 */
-#define FLASH_SCAR_SEC_AREA_END FLASH_SCAR_SEC_AREA_END_Msk /*!< Secure-only area end status bits */
-#define FLASH_SCAR_DMES_Pos (31U)
-#define FLASH_SCAR_DMES_Msk (0x1UL << FLASH_SCAR_DMES_Pos) /*!< 0x80000000 */
-#define FLASH_SCAR_DMES FLASH_SCAR_DMES_Msk /*!< Secure access protected erase enable option status bit */
-
-/******************* Bits definition for FLASH_WPSN register *********************/
-#define FLASH_WPSN_WRPSN_Pos (0U)
-#define FLASH_WPSN_WRPSN_Msk (0xFFUL << FLASH_WPSN_WRPSN_Pos) /*!< 0x000000FF */
-#define FLASH_WPSN_WRPSN FLASH_WPSN_WRPSN_Msk /*!< Sector write protection option status byte */
-
-/******************* Bits definition for FLASH_BOOT_CUR register ****************/
-#define FLASH_BOOT_ADD0_Pos (0U)
-#define FLASH_BOOT_ADD0_Msk (0xFFFFUL << FLASH_BOOT_ADD0_Pos) /*!< 0x0000FFFF */
-#define FLASH_BOOT_ADD0 FLASH_BOOT_ADD0_Msk /*!< Arm Cortex-M7 boot address 0 */
-#define FLASH_BOOT_ADD1_Pos (16U)
-#define FLASH_BOOT_ADD1_Msk (0xFFFFUL << FLASH_BOOT_ADD1_Pos) /*!< 0xFFFF0000 */
-#define FLASH_BOOT_ADD1 FLASH_BOOT_ADD1_Msk /*!< Arm Cortex-M7 boot address 1 */
-
-
-/******************* Bits definition for FLASH_CRCCR register ********************/
-#define FLASH_CRCCR_CRC_SECT_Pos (0U)
-#define FLASH_CRCCR_CRC_SECT_Msk (0x7UL << FLASH_CRCCR_CRC_SECT_Pos) /*!< 0x00000007 */
-#define FLASH_CRCCR_CRC_SECT FLASH_CRCCR_CRC_SECT_Msk /*!< CRC sector number */
-#define FLASH_CRCCR_CRC_BY_SECT_Pos (8U)
-#define FLASH_CRCCR_CRC_BY_SECT_Msk (0x1UL << FLASH_CRCCR_CRC_BY_SECT_Pos) /*!< 0x00000100 */
-#define FLASH_CRCCR_CRC_BY_SECT FLASH_CRCCR_CRC_BY_SECT_Msk /*!< CRC sector mode select bit */
-#define FLASH_CRCCR_ADD_SECT_Pos (9U)
-#define FLASH_CRCCR_ADD_SECT_Msk (0x1UL << FLASH_CRCCR_ADD_SECT_Pos) /*!< 0x00000200 */
-#define FLASH_CRCCR_ADD_SECT FLASH_CRCCR_ADD_SECT_Msk /*!< CRC sector select bit */
-#define FLASH_CRCCR_CLEAN_SECT_Pos (10U)
-#define FLASH_CRCCR_CLEAN_SECT_Msk (0x1UL << FLASH_CRCCR_CLEAN_SECT_Pos) /*!< 0x00000400 */
-#define FLASH_CRCCR_CLEAN_SECT FLASH_CRCCR_CLEAN_SECT_Msk /*!< CRC sector list clear bit */
-#define FLASH_CRCCR_START_CRC_Pos (16U)
-#define FLASH_CRCCR_START_CRC_Msk (0x1UL << FLASH_CRCCR_START_CRC_Pos) /*!< 0x00010000 */
-#define FLASH_CRCCR_START_CRC FLASH_CRCCR_START_CRC_Msk /*!< CRC start bit */
-#define FLASH_CRCCR_CLEAN_CRC_Pos (17U)
-#define FLASH_CRCCR_CLEAN_CRC_Msk (0x1UL << FLASH_CRCCR_CLEAN_CRC_Pos) /*!< 0x00020000 */
-#define FLASH_CRCCR_CLEAN_CRC FLASH_CRCCR_CLEAN_CRC_Msk /*!< CRC clear bit */
-#define FLASH_CRCCR_CRC_BURST_Pos (20U)
-#define FLASH_CRCCR_CRC_BURST_Msk (0x3UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00300000 */
-#define FLASH_CRCCR_CRC_BURST FLASH_CRCCR_CRC_BURST_Msk /*!< CRC burst size */
-#define FLASH_CRCCR_CRC_BURST_0 (0x1UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00100000 */
-#define FLASH_CRCCR_CRC_BURST_1 (0x2UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00200000 */
-#define FLASH_CRCCR_ALL_BANK_Pos (22U)
-#define FLASH_CRCCR_ALL_BANK_Msk (0x1UL << FLASH_CRCCR_ALL_BANK_Pos) /*!< 0x00400000 */
-#define FLASH_CRCCR_ALL_BANK FLASH_CRCCR_ALL_BANK_Msk /*!< CRC select bit */
-
-/******************* Bits definition for FLASH_CRCSADD register ****************/
-#define FLASH_CRCSADD_CRC_START_ADDR_Pos (0U)
-#define FLASH_CRCSADD_CRC_START_ADDR_Msk (0xFFFFFFFFUL << FLASH_CRCSADD_CRC_START_ADDR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_CRCSADD_CRC_START_ADDR FLASH_CRCSADD_CRC_START_ADDR_Msk /*!< CRC start address */
-
-/******************* Bits definition for FLASH_CRCEADD register ****************/
-#define FLASH_CRCEADD_CRC_END_ADDR_Pos (0U)
-#define FLASH_CRCEADD_CRC_END_ADDR_Msk (0xFFFFFFFFUL << FLASH_CRCEADD_CRC_END_ADDR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_CRCEADD_CRC_END_ADDR FLASH_CRCEADD_CRC_END_ADDR_Msk /*!< CRC end address */
-
-/******************* Bits definition for FLASH_CRCDATA register ***************/
-#define FLASH_CRCDATA_CRC_DATA_Pos (0U)
-#define FLASH_CRCDATA_CRC_DATA_Msk (0xFFFFFFFFUL << FLASH_CRCDATA_CRC_DATA_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_CRCDATA_CRC_DATA FLASH_CRCDATA_CRC_DATA_Msk /*!< CRC result */
-
-/******************* Bits definition for FLASH_ECC_FA register *******************/
-#define FLASH_ECC_FA_FAIL_ECC_ADDR_Pos (0U)
-#define FLASH_ECC_FA_FAIL_ECC_ADDR_Msk (0x7FFFUL << FLASH_ECC_FA_FAIL_ECC_ADDR_Pos) /*!< 0x00007FFF */
-#define FLASH_ECC_FA_FAIL_ECC_ADDR FLASH_ECC_FA_FAIL_ECC_ADDR_Msk /*!< ECC error address */
-
-/******************************************************************************/
-/* */
-/* Flexible Memory Controller */
-/* */
-/******************************************************************************/
-/****************** Bit definition for FMC_BCR1 register *******************/
-#define FMC_BCR1_CCLKEN_Pos (20U)
-#define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */
-#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/** @addtogroup CMSIS
- * @{
- */
-
-/** @addtogroup stm32h7xx
- * @{
- */
-
-#ifndef STM32H7xx_H
-#define STM32H7xx_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif /* __cplusplus */
-
-/** @addtogroup Library_configuration_section
- * @{
- */
-
-/**
- * @brief STM32 Family
- */
-#if !defined (STM32H7)
-#define STM32H7
-#endif /* STM32H7 */
-
-
-/* Uncomment the line below according to the target STM32H7 device used in your
- application
- */
-
-#if !defined (STM32H743xx) && !defined (STM32H753xx) && !defined (STM32H750xx) && !defined (STM32H742xx) && \
- !defined (STM32H745xx) && !defined (STM32H755xx) && !defined (STM32H747xx) && !defined (STM32H757xx) && \
- !defined (STM32H7A3xx) && !defined (STM32H7A3xxQ) && !defined (STM32H7B3xx) && !defined (STM32H7B3xxQ) && !defined (STM32H7B0xx) && !defined (STM32H7B0xxQ) && \
- !defined (STM32H735xx) && !defined (STM32H733xx) && !defined (STM32H730xx) && !defined (STM32H730xxQ) && !defined (STM32H725xx) && !defined (STM32H723xx)
- /* #define STM32H742xx */ /*!< STM32H742VI, STM32H742ZI, STM32H742AI, STM32H742II, STM32H742BI, STM32H742XI Devices */
- /* #define STM32H743xx */ /*!< STM32H743VI, STM32H743ZI, STM32H743AI, STM32H743II, STM32H743BI, STM32H743XI Devices */
- /* #define STM32H753xx */ /*!< STM32H753VI, STM32H753ZI, STM32H753AI, STM32H753II, STM32H753BI, STM32H753XI Devices */
- /* #define STM32H750xx */ /*!< STM32H750V, STM32H750I, STM32H750X Devices */
- /* #define STM32H747xx */ /*!< STM32H747ZI, STM32H747AI, STM32H747II, STM32H747BI, STM32H747XI Devices */
- /* #define STM32H757xx */ /*!< STM32H757ZI, STM32H757AI, STM32H757II, STM32H757BI, STM32H757XI Devices */
- /* #define STM32H745xx */ /*!< STM32H745ZI, STM32H745II, STM32H745BI, STM32H745XI Devices */
- /* #define STM32H755xx */ /*!< STM32H755ZI, STM32H755II, STM32H755BI, STM32H755XI Devices */
- /* #define STM32H7B0xx */ /*!< STM32H7B0ABIxQ, STM32H7B0IBTx, STM32H7B0RBTx, STM32H7B0VBTx, STM32H7B0ZBTx, STM32H7B0IBKxQ */
- /* #define STM32H7A3xx */ /*!< STM32H7A3IIK6, STM32H7A3IIT6, STM32H7A3NIH6, STM32H7A3RIT6, STM32H7A3VIH6, STM32H7A3VIT6, STM32H7A3ZIT6 */
- /* #define STM32H7A3xxQ */ /*!< STM32H7A3QIY6Q, STM32H7A3IIK6Q, STM32H7A3IIT6Q, STM32H7A3LIH6Q, STM32H7A3VIH6Q, STM32H7A3VIT6Q, STM32H7A3AII6Q, STM32H7A3ZIT6Q */
- /* #define STM32H7B3xx */ /*!< STM32H7B3IIK6, STM32H7B3IIT6, STM32H7B3NIH6, STM32H7B3RIT6, STM32H7B3VIH6, STM32H7B3VIT6, STM32H7B3ZIT6 */
- /* #define STM32H7B3xxQ */ /*!< STM32H7B3QIY6Q, STM32H7B3IIK6Q, STM32H7B3IIT6Q, STM32H7B3LIH6Q, STM32H7B3VIH6Q, STM32H7B3VIT6Q, STM32H7B3AII6Q, STM32H7B3ZIT6Q */
- /* #define STM32H735xx */ /*!< STM32H735AGI6, STM32H735IGK6, STM32H735RGV6, STM32H735VGT6, STM32H735VGY6, STM32H735ZGT6 Devices */
- /* #define STM32H733xx */ /*!< STM32H733VGH6, STM32H733VGT6, STM32H733ZGI6, STM32H733ZGT6, Devices */
- /* #define STM32H730xx */ /*!< STM32H730VBH6, STM32H730VBT6, STM32H730ZBT6, STM32H730ZBI6 Devices */
- /* #define STM32H730xxQ */ /*!< STM32H730IBT6Q, STM32H730ABI6Q, STM32H730IBK6Q Devices */
- /* #define STM32H725xx */ /*!< STM32H725AGI6, STM32H725IGK6, STM32H725IGT6, STM32H725RGV6, STM32H725VGT6, STM32H725VGY6, STM32H725ZGT6, STM32H725REV6, SM32H725VET6, STM32H725ZET6, STM32H725AEI6, STM32H725IET6, STM32H725IEK6 Devices */
- /* #define STM32H723xx */ /*!< STM32H723VGH6, STM32H723VGT6, STM32H723ZGI6, STM32H723ZGT6, STM32H723VET6, STM32H723VEH6, STM32H723ZET6, STM32H723ZEI6 Devices */
-#endif
-
-/* Tip: To avoid modifying this file each time you need to switch between these
- devices, you can define the device in your toolchain compiler preprocessor.
- */
-
-#if defined(DUAL_CORE) && !defined(CORE_CM4) && !defined(CORE_CM7)
- #error "Dual core device, please select CORE_CM4 or CORE_CM7"
-#endif
-
-#if !defined (USE_HAL_DRIVER)
-/**
- * @brief Comment the line below if you will not use the peripherals drivers.
- In this case, these drivers will not be included and the application code will
- be based on direct access to peripherals registers
- */
- /*#define USE_HAL_DRIVER */
-#endif /* USE_HAL_DRIVER */
-
-/**
- * @brief CMSIS Device version number V1.9.0
- */
-#define __STM32H7xx_CMSIS_DEVICE_VERSION_MAIN (0x01) /*!< [31:24] main version */
-#define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB1 (0x09) /*!< [23:16] sub1 version */
-#define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
-#define __STM32H7xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
-#define __STM32H7xx_CMSIS_DEVICE_VERSION ((__CMSIS_DEVICE_VERSION_MAIN << 24)\
- |(__CMSIS_DEVICE_HAL_VERSION_SUB1 << 16)\
- |(__CMSIS_DEVICE_HAL_VERSION_SUB2 << 8 )\
- |(__CMSIS_DEVICE_HAL_VERSION_RC))
-
-/**
- * @}
- */
-
-/** @addtogroup Device_Included
- * @{
- */
-
-#if defined(STM32H743xx)
- #include "stm32h743xx.h"
-#elif defined(STM32H753xx)
- #include "stm32h753xx.h"
-#elif defined(STM32H750xx)
- #include "stm32h750xx.h"
-#elif defined(STM32H742xx)
- #include "stm32h742xx.h"
-#elif defined(STM32H745xx)
- #include "stm32h745xx.h"
-#elif defined(STM32H755xx)
- #include "stm32h755xx.h"
-#elif defined(STM32H747xx)
- #include "stm32h747xx.h"
-#elif defined(STM32H757xx)
- #include "stm32h757xx.h"
-#elif defined(STM32H7B0xx)
- #include "stm32h7b0xx.h"
-#elif defined(STM32H7B0xxQ)
- #include "stm32h7b0xxq.h"
-#elif defined(STM32H7A3xx)
- #include "stm32h7a3xx.h"
-#elif defined(STM32H7B3xx)
- #include "stm32h7b3xx.h"
-#elif defined(STM32H7A3xxQ)
- #include "stm32h7a3xxq.h"
-#elif defined(STM32H7B3xxQ)
- #include "stm32h7b3xxq.h"
-#elif defined(STM32H735xx)
- #include "stm32h735xx.h"
-#elif defined(STM32H733xx)
- #include "stm32h733xx.h"
-#elif defined(STM32H730xx)
- #include "stm32h730xx.h"
-#elif defined(STM32H730xxQ)
- #include "stm32h730xxq.h"
-#elif defined(STM32H725xx)
- #include "stm32h725xx.h"
-#elif defined(STM32H723xx)
- #include "stm32h723xx.h"
-#else
- #error "Please select first the target STM32H7xx device used in your application (in stm32h7xx.h file)"
-#endif
-
-/**
- * @}
- */
-
-/** @addtogroup Exported_types
- * @{
- */
-typedef enum
-{
- RESET = 0,
- SET = !RESET
-} FlagStatus, ITStatus;
-
-typedef enum
-{
- DISABLE = 0,
- ENABLE = !DISABLE
-} FunctionalState;
-#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
-
-typedef enum
-{
- SUCCESS = 0,
- ERROR = !SUCCESS
-} ErrorStatus;
-
-/**
- * @}
- */
-
-
-/** @addtogroup Exported_macros
- * @{
- */
-#define SET_BIT(REG, BIT) ((REG) |= (BIT))
-
-#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
-
-#define READ_BIT(REG, BIT) ((REG) & (BIT))
-
-#define CLEAR_REG(REG) ((REG) = (0x0))
-
-#define WRITE_REG(REG, VAL) ((REG) = (VAL))
-
-#define READ_REG(REG) ((REG))
-
-#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
-
-#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
-
-
-/**
- * @}
- */
-
-#if defined (USE_HAL_DRIVER)
- #include "stm32h7xx_hal.h"
-#endif /* USE_HAL_DRIVER */
-
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* STM32H7xx_H */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp_stm32h7_freertos/NUCLEO-H743ZI/Inc/stm32h7xx_nucleo.h b/bsp_stm32h7_freertos/NUCLEO-H743ZI/Inc/stm32h7xx_nucleo.h
new file mode 100644
index 0000000..5608b9c
--- /dev/null
+++ b/bsp_stm32h7_freertos/NUCLEO-H743ZI/Inc/stm32h7xx_nucleo.h
@@ -0,0 +1,338 @@
+/**
+ ******************************************************************************
+ * @file stm32h7xx_nucleo.h
+ * @author MCD Application Team
+ * @brief This file contains definitions for:
+ * - LEDs and push-button available on STM32H7xx-Nucleo Kit
+ * from STMicroelectronics
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7XX_NUCLEO_H
+#define STM32H7XX_NUCLEO_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_nucleo_conf.h"
+#include "stm32h7xx_nucleo_errno.h"
+
+#if (USE_BSP_COM_FEATURE > 0)
+ #if (USE_COM_LOG > 0)
+ #ifndef __GNUC__
+ #include
+ #endif
+ #endif
+#endif
+
+/** @addtogroup BSP
+ * @{
+ */
+
+/** @defgroup STM32H7XX_NUCLEO STM32H7XX_NUCLEO
+ * @{
+ */
+
+/** @defgroup STM32H7XX_NUCLEO_LOW_LEVEL LOW LEVEL
+ * @{
+ */
+
+/**
+ * @brief Define for STM32H7XX_NUCLEO board
+ */
+#if !defined (USE_STM32H7XX_NUCLEO)
+ #define USE_STM32H7XX_NUCLEO
+#endif
+
+#if !defined (USE_NUCLEO_144)
+ #error "Board Pin number not defined!! Add USE_NUCLEO_144 define within stm32h7xx_nucleo_conf.h file"
+#endif
+
+#if !defined (USE_NUCLEO_H745ZI_Q) && !defined (USE_NUCLEO_H743ZI) && !defined (USE_NUCLEO_H743ZI2) &&\
+ !defined (USE_NUCLEO_H7A3ZI_Q) && !defined (USE_NUCLEO_H723ZG)
+ #error "Board Part number not defined!! Add one of the following define within stm32h7xx_nucleo_conf.h file:\
+ USE_NUCLEO_H745ZI_Q, USE_NUCLEO_H743ZI, USE_NUCLEO_H743ZI2, USE_NUCLEO_H7A3ZI_Q, USE_NUCLEO_H723ZG"
+#endif
+
+/** @defgroup STM32H7XX_NUCLEO_LOW_LEVEL_Exported_Types LOW LEVEL Exported Types
+ * @{
+ */
+#if defined (USE_NUCLEO_H745ZI_Q) || defined (USE_NUCLEO_H743ZI2) || defined (USE_NUCLEO_H7A3ZI_Q) || defined (USE_NUCLEO_H723ZG)
+typedef enum
+{
+ LED1 = 0,
+ LED_GREEN = LED1,
+ LED2 = 1,
+ LED_YELLOW = LED2,
+ LED3 = 2,
+ LED_RED = LED3,
+ LEDn
+}Led_TypeDef;
+#else /* USE_NUCLEO_H743ZI */
+typedef enum
+{
+ LED1 = 0,
+ LED_GREEN = LED1,
+ LED2 = 1,
+ LED_BLUE = LED2,
+ LED3 = 2,
+ LED_RED = LED3,
+ LEDn
+}Led_TypeDef;
+#endif
+
+typedef enum
+{
+ BUTTON_USER = 0U,
+ BUTTONn
+}Button_TypeDef;
+
+typedef enum
+{
+ BUTTON_MODE_GPIO = 0,
+ BUTTON_MODE_EXTI = 1
+}ButtonMode_TypeDef;
+
+#if (USE_BSP_COM_FEATURE > 0)
+typedef enum
+{
+ COM1 = 0U,
+ COMn
+}COM_TypeDef;
+
+typedef enum
+{
+ COM_STOPBITS_1 = UART_STOPBITS_1,
+ COM_STOPBITS_2 = UART_STOPBITS_2,
+}COM_StopBitsTypeDef;
+
+typedef enum
+{
+ COM_PARITY_NONE = UART_PARITY_NONE,
+ COM_PARITY_EVEN = UART_PARITY_EVEN,
+ COM_PARITY_ODD = UART_PARITY_ODD,
+}COM_ParityTypeDef;
+
+typedef enum
+{
+ COM_HWCONTROL_NONE = UART_HWCONTROL_NONE,
+ COM_HWCONTROL_RTS = UART_HWCONTROL_RTS,
+ COM_HWCONTROL_CTS = UART_HWCONTROL_CTS,
+ COM_HWCONTROL_RTS_CTS = UART_HWCONTROL_RTS_CTS,
+}COM_HwFlowCtlTypeDef;
+
+typedef enum
+{
+ COM_WORDLENGTH_7B = UART_WORDLENGTH_7B,
+ COM_WORDLENGTH_8B = UART_WORDLENGTH_8B,
+ COM_WORDLENGTH_9B = UART_WORDLENGTH_9B,
+}COM_WordLengthTypeDef;
+
+typedef struct
+{
+ uint32_t BaudRate;
+ COM_WordLengthTypeDef WordLength;
+ COM_StopBitsTypeDef StopBits;
+ COM_ParityTypeDef Parity;
+ COM_HwFlowCtlTypeDef HwFlowCtl;
+}COM_InitTypeDef;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+typedef struct
+{
+ void (* pMspInitCb)(UART_HandleTypeDef *);
+ void (* pMspDeInitCb)(UART_HandleTypeDef *);
+}BSP_COM_Cb_t;
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS == 1) */
+
+#define MX_UART_InitTypeDef COM_InitTypeDef
+#endif
+
+/**
+ * @}
+ */
+
+/** @defgroup STM32H7XX_NUCLEO_LOW_LEVEL_Exported_Constants LOW LEVEL Exported Constants
+ * @{
+ */
+
+/**
+ * @brief STM32H7XX NUCLEO BSP Driver version number V1.3.0
+ */
+#define STM32H7XX_NUCLEO_BSP_VERSION_MAIN (0x01U) /*!< [31:24] main version */
+#define STM32H7XX_NUCLEO_BSP_VERSION_SUB1 (0x03U) /*!< [23:16] sub1 version */
+#define STM32H7XX_NUCLEO_BSP_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */
+#define STM32H7XX_NUCLEO_BSP_VERSION_RC (0x00U) /*!< [7:0] release candidate */
+#define STM32H7XX_NUCLEO_BSP_VERSION ((STM32H7XX_NUCLEO_BSP_VERSION_MAIN << 24)\
+ |(STM32H7XX_NUCLEO_BSP_VERSION_SUB1 << 16)\
+ |(STM32H7XX_NUCLEO_BSP_VERSION_SUB2 << 8 )\
+ |(STM32H7XX_NUCLEO_BSP_VERSION_RC))
+
+/** @defgroup STM32H7XX_NUCLEO_LOW_LEVEL_LED LOW LEVEL LED
+ * @{
+ */
+#define LEDn 3U
+
+#define LED1_PIN GPIO_PIN_0
+#define LED1_GPIO_PORT GPIOB
+#define LED1_GPIO_CLK_ENABLE() __HAL_RCC_GPIOB_CLK_ENABLE()
+#define LED1_GPIO_CLK_DISABLE() __HAL_RCC_GPIOB_CLK_DISABLE()
+
+#if defined (USE_NUCLEO_H745ZI_Q) || defined (USE_NUCLEO_H743ZI2) || defined (USE_NUCLEO_H7A3ZI_Q) || defined (USE_NUCLEO_H723ZG)
+#define LED2_PIN GPIO_PIN_1
+#define LED2_GPIO_PORT GPIOE
+#define LED2_GPIO_CLK_ENABLE() __HAL_RCC_GPIOE_CLK_ENABLE()
+#define LED2_GPIO_CLK_DISABLE() __HAL_RCC_GPIOE_CLK_DISABLE()
+#else /* USE_NUCLEO_H743ZI */
+#define LED2_PIN GPIO_PIN_7
+#define LED2_GPIO_PORT GPIOB
+#define LED2_GPIO_CLK_ENABLE() __HAL_RCC_GPIOB_CLK_ENABLE()
+#define LED2_GPIO_CLK_DISABLE() __HAL_RCC_GPIOB_CLK_DISABLE()
+#endif
+
+#define LED3_PIN GPIO_PIN_14
+#define LED3_GPIO_PORT GPIOB
+#define LED3_GPIO_CLK_ENABLE() __HAL_RCC_GPIOB_CLK_ENABLE()
+#define LED3_GPIO_CLK_DISABLE() __HAL_RCC_GPIOB_CLK_DISABLE()
+
+/**
+ * @}
+ */
+
+/** @defgroup STM32H7XX_NUCLEO_LOW_LEVEL_BUTTON LOW LEVEL BUTTON
+ * @{
+ */
+/* Button state */
+#define BUTTON_RELEASED 0U
+#define BUTTON_PRESSED 1U
+#define BUTTONn 1U
+
+/**
+ * @brief Key push-button
+ */
+#define BUTTON_USER_PIN GPIO_PIN_13
+#define BUTTON_USER_GPIO_PORT GPIOC
+#define BUTTON_USER_GPIO_CLK_ENABLE() __HAL_RCC_GPIOC_CLK_ENABLE()
+#define BUTTON_USER_GPIO_CLK_DISABLE() __HAL_RCC_GPIOC_CLK_DISABLE()
+#define BUTTON_USER_EXTI_IRQn EXTI15_10_IRQn
+#define BUTTON_USER_EXTI_LINE EXTI_LINE_13
+
+/**
+ * @}
+ */
+
+/** @defgroup STM32H7XX_NUCLEO_LOW_LEVEL_COM LOW LEVEL COM
+ * @{
+ */
+/**
+ * @brief Definition for COM port1, connected to USART3
+ */
+#if (USE_BSP_COM_FEATURE > 0)
+
+#define COMn 1U
+#define COM1_UART USART3
+#define COM1_CLK_ENABLE() __HAL_RCC_USART3_CLK_ENABLE()
+#define COM1_CLK_DISABLE() __HAL_RCC_USART3_CLK_DISABLE()
+
+#define COM1_TX_PIN GPIO_PIN_8
+#define COM1_TX_GPIO_PORT GPIOD
+#define COM1_TX_GPIO_CLK_ENABLE() __HAL_RCC_GPIOD_CLK_ENABLE()
+#define COM1_TX_GPIO_CLK_DISABLE() __HAL_RCC_GPIOD_CLK_DISABLE()
+#define COM1_TX_AF GPIO_AF7_USART3
+
+#define COM1_RX_PIN GPIO_PIN_9
+#define COM1_RX_GPIO_PORT GPIOD
+#define COM1_RX_GPIO_CLK_ENABLE() __HAL_RCC_GPIOD_CLK_ENABLE()
+#define COM1_RX_GPIO_CLK_DISABLE() __HAL_RCC_GPIOD_CLK_DISABLE()
+#define COM1_RX_AF GPIO_AF7_USART3
+#define COM_POLL_TIMEOUT 1000
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32H7XX_NUCLEO_LOW_LEVEL_Exported_Variables
+ * @{
+ */
+extern EXTI_HandleTypeDef hpb_exti[];
+#if (USE_BSP_COM_FEATURE > 0)
+extern UART_HandleTypeDef hcom_uart[];
+extern USART_TypeDef* COM_USART[];
+#endif
+
+/**
+ * @}
+ */
+
+/** @defgroup STM32H7XX_NUCLEO_LOW_LEVEL_Exported_FunctionsPrototypes LOW LEVEL Exported Functions Prototypes
+ * @{
+ */
+int32_t BSP_GetVersion(void);
+int32_t BSP_LED_Init(Led_TypeDef Led);
+int32_t BSP_LED_DeInit(Led_TypeDef Led);
+int32_t BSP_LED_On(Led_TypeDef Led);
+int32_t BSP_LED_Off(Led_TypeDef Led);
+int32_t BSP_LED_Toggle(Led_TypeDef Led);
+int32_t BSP_LED_GetState (Led_TypeDef Led);
+int32_t BSP_PB_Init(Button_TypeDef Button, ButtonMode_TypeDef ButtonMode);
+int32_t BSP_PB_DeInit(Button_TypeDef Button);
+int32_t BSP_PB_GetState(Button_TypeDef Button);
+void BSP_PB_IRQHandler(Button_TypeDef Button);
+void BSP_PB_Callback(Button_TypeDef Button);
+
+#if (USE_BSP_COM_FEATURE > 0)
+int32_t BSP_COM_Init(COM_TypeDef COM, COM_InitTypeDef *COM_Init);
+int32_t BSP_COM_DeInit(COM_TypeDef COM);
+#if (USE_COM_LOG > 0)
+int32_t BSP_COM_SelectLogPort (COM_TypeDef COM);
+#endif
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+int32_t BSP_COM_RegisterDefaultMspCallbacks(COM_TypeDef COM);
+int32_t BSP_COM_RegisterMspCallbacks(COM_TypeDef COM , BSP_COM_Cb_t *Callback);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+HAL_StatusTypeDef MX_USART3_Init(UART_HandleTypeDef *huart, MX_UART_InitTypeDef *COM_Init);
+#endif /* USE_BSP_COM_FEATURE */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7XX_NUCLEO_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp_stm32h7_freertos/NUCLEO-H743ZI/Inc/stm32h7xx_nucleo_errno.h b/bsp_stm32h7_freertos/NUCLEO-H743ZI/Inc/stm32h7xx_nucleo_errno.h
new file mode 100644
index 0000000..8fc1334
--- /dev/null
+++ b/bsp_stm32h7_freertos/NUCLEO-H743ZI/Inc/stm32h7xx_nucleo_errno.h
@@ -0,0 +1,48 @@
+/**
+ ******************************************************************************
+ * @file stm32h7xx_nucleo_errno.h
+ * @author MCD Application Team
+ * @brief Error Code.
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7XX_NUCLEO_ERRNO_H
+#define STM32H7XX_NUCLEO_ERRNO_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Common Error codes */
+#define BSP_ERROR_NONE 0
+#define BSP_ERROR_NO_INIT -1
+#define BSP_ERROR_WRONG_PARAM -2
+#define BSP_ERROR_BUSY -3
+#define BSP_ERROR_PERIPH_FAILURE -4
+#define BSP_ERROR_COMPONENT_FAILURE -5
+#define BSP_ERROR_UNKNOWN_FAILURE -6
+#define BSP_ERROR_UNKNOWN_COMPONENT -7
+#define BSP_ERROR_BUS_FAILURE -8
+#define BSP_ERROR_CLOCK_FAILURE -9
+#define BSP_ERROR_MSP_FAILURE -10
+#define BSP_ERROR_FEATURE_NOT_SUPPORTED -11
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7XX_NUCLEO_ERRNO_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp_stm32h7_freertos/NUCLEO-H743ZI/Inc/system_stm32h7xx.h b/bsp_stm32h7_freertos/NUCLEO-H743ZI/Inc/system_stm32h7xx.h
deleted file mode 100644
index 34f8495..0000000
--- a/bsp_stm32h7_freertos/NUCLEO-H743ZI/Inc/system_stm32h7xx.h
+++ /dev/null
@@ -1,105 +0,0 @@
-/**
- ******************************************************************************
- * @file system_stm32h7xx.h
- * @author MCD Application Team
- * @brief CMSIS Cortex-Mx Device System Source File for STM32H7xx devices.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/** @addtogroup CMSIS
- * @{
- */
-
-/** @addtogroup stm32h7xx_system
- * @{
- */
-
-/**
- * @brief Define to prevent recursive inclusion
- */
-#ifndef SYSTEM_STM32H7XX_H
-#define SYSTEM_STM32H7XX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/** @addtogroup STM32H7xx_System_Includes
- * @{
- */
-
-/**
- * @}
- */
-
-
-/** @addtogroup STM32H7xx_System_Exported_types
- * @{
- */
- /* This variable is updated in three ways:
- 1) by calling CMSIS function SystemCoreClockUpdate()
- 2) by calling HAL API function HAL_RCC_GetSysClockFreq()
- 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
- Note: If you use this function to configure the system clock; then there
- is no need to call the 2 first functions listed above, since SystemCoreClock
- variable is updated automatically.
- */
-extern uint32_t SystemCoreClock; /*!< System Domain1 Clock Frequency */
-extern uint32_t SystemD2Clock; /*!< System Domain2 Clock Frequency */
-extern const uint8_t D1CorePrescTable[16] ; /*!< D1CorePrescTable prescalers table values */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32H7xx_System_Exported_Constants
- * @{
- */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32H7xx_System_Exported_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32H7xx_System_Exported_Functions
- * @{
- */
-
-extern void SystemInit(void);
-extern void SystemCoreClockUpdate(void);
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* SYSTEM_STM32H7XX_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp_stm32h7_freertos/NUCLEO-H743ZI/Src/CMakeLists.txt b/bsp_stm32h7_freertos/NUCLEO-H743ZI/Src/CMakeLists.txt
index 7febc45..8800514 100644
--- a/bsp_stm32h7_freertos/NUCLEO-H743ZI/Src/CMakeLists.txt
+++ b/bsp_stm32h7_freertos/NUCLEO-H743ZI/Src/CMakeLists.txt
@@ -2,6 +2,7 @@ target_sources(${TARGET_NAME} PRIVATE
freertos.c
hardware_init.c
stm32h7xx_hal_timebase_tim.c
+ stm32h7xx_nucleo.c
stm32h7xx_it.c
syscalls.c
)
\ No newline at end of file
diff --git a/bsp_stm32h7_freertos/NUCLEO-H743ZI/Src/freertos.c b/bsp_stm32h7_freertos/NUCLEO-H743ZI/Src/freertos.c
index 5cda11e..fd8ca61 100644
--- a/bsp_stm32h7_freertos/NUCLEO-H743ZI/Src/freertos.c
+++ b/bsp_stm32h7_freertos/NUCLEO-H743ZI/Src/freertos.c
@@ -47,9 +47,9 @@
*/
/* Includes ------------------------------------------------------------------*/
-#include "freertos/FreeRTOS.h"
-#include "freertos/task.h"
-#include
+#include "FreeRTOS.h"
+#include "task.h"
+#include "portmacro.h"
/* USER CODE BEGIN Includes */
void vRequestContextSwitchFromISR() {
diff --git a/bsp_stm32h7_freertos/NUCLEO-H743ZI/Src/hardware_init.c b/bsp_stm32h7_freertos/NUCLEO-H743ZI/Src/hardware_init.c
index 1c42a2e..29f02ac 100644
--- a/bsp_stm32h7_freertos/NUCLEO-H743ZI/Src/hardware_init.c
+++ b/bsp_stm32h7_freertos/NUCLEO-H743ZI/Src/hardware_init.c
@@ -1,15 +1,18 @@
#include "hardware_init.h"
+#include "OBSWConfig.h"
-#include
-#include
-#include
+#include "stm32h743xx.h"
+#include "stm32h7xx_hal_rcc_ex.h"
+#include "stm32h7xx_nucleo.h"
+#if OBSW_ADD_LWIP_COMPONENTS == 1
#include
-#include
+#include "example_common/stm32h7/networking/ethernetif.h"
#include
#include
#include
#include
+#endif
#include
#include
@@ -27,7 +30,9 @@ void MX_USART3_UART_Init(uint32_t baudRate);
*/
UART_HandleTypeDef huart3;
GPIO_InitTypeDef gpio_uart_init_struct;
+#if OBSW_ADD_LWIP_COMPONENTS == 1
struct netif gnetif;
+#endif
bool debugAvailable = false;
void performHardwareInit() {
@@ -229,6 +234,7 @@ void BSP_Config(void)
BSP_LED_Init(LED3);
}
+#if OBSW_ADD_LWIP_COMPONENTS == 1
void Netif_Config(void)
{
@@ -264,4 +270,5 @@ void Netif_Config(void)
#endif
}
+#endif /* OBSW_ADD_LWIP_COMPONENTS == 1 */
diff --git a/bsp_stm32h7_freertos/NUCLEO-H743ZI/Src/stm32h7xx_nucleo.c b/bsp_stm32h7_freertos/NUCLEO-H743ZI/Src/stm32h7xx_nucleo.c
new file mode 100644
index 0000000..c872fec
--- /dev/null
+++ b/bsp_stm32h7_freertos/NUCLEO-H743ZI/Src/stm32h7xx_nucleo.c
@@ -0,0 +1,693 @@
+/**
+ ******************************************************************************
+ * @file stm32h7xx_nucleo.c
+ * @author MCD Application Team
+ * @brief This file provides set of firmware functions to manage:
+ * - LEDs and push-button available on STM32H7xx-Nucleo Kit
+ * from STMicroelectronics
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2018 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_nucleo.h"
+
+/** @addtogroup BSP
+ * @{
+ */
+
+/** @addtogroup STM32H7XX_NUCLEO
+ * @{
+ */
+
+/** @addtogroup STM32H7XX_NUCLEO_LOW_LEVEL
+ * @brief This file provides set of firmware functions to manage Leds and push-button
+ * available on STM32H7xx-Nucleo Kit from STMicroelectronics.
+ * @{
+ */
+
+/** @defgroup STM32H7XX_NUCLEO_LOW_LEVEL_Private_Defines LOW LEVEL Private Defines
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup STM32H7XX_NUCLEO_LOW_LEVEL_Private_TypesDefinitions LOW LEVEL Private Typedef
+ * @{
+ */
+typedef void (* BSP_EXTI_LineCallback) (void);
+/**
+ * @}
+ */
+
+/** @defgroup STM32H7XX_NUCLEO_LOW_LEVEL_Exported_Variables LOW LEVEL Exported Variables
+ * @{
+ */
+EXTI_HandleTypeDef hpb_exti[BUTTONn];
+#if (USE_BSP_COM_FEATURE > 0)
+UART_HandleTypeDef hcom_uart[COMn];
+USART_TypeDef* COM_USART[COMn] = {COM1_UART};
+#endif
+/**
+ * @}
+ */
+/** @defgroup STM32H7XX_NUCLEO_LOW_LEVEL_Private_Variables LOW LEVEL Private Variables
+ * @{
+ */
+static GPIO_TypeDef* LED_PORT[LEDn] = {LED1_GPIO_PORT,
+ LED2_GPIO_PORT,
+ LED3_GPIO_PORT};
+
+static const uint16_t LED_PIN[LEDn] = {LED1_PIN,
+ LED2_PIN,
+ LED3_PIN};
+
+static GPIO_TypeDef* BUTTON_PORT[BUTTONn] = {BUTTON_USER_GPIO_PORT};
+static const uint16_t BUTTON_PIN[BUTTONn] = {BUTTON_USER_PIN};
+static const IRQn_Type BUTTON_IRQn[BUTTONn] = {BUTTON_USER_EXTI_IRQn};
+
+
+
+#if (USE_BSP_COM_FEATURE > 0)
+ #if (USE_COM_LOG > 0)
+ static COM_TypeDef COM_ActiveLogPort = COM1;
+ #endif
+ #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ static uint32_t IsComMspCbValid[COMn] = {0};
+ #endif
+#endif
+
+/**
+ * @}
+ */
+
+/** @defgroup STM32H7XX_NUCLEO_LOW_LEVEL_Private_FunctionPrototypes LOW LEVEL Private functions Prototypes
+ * @{
+ */
+static void BUTTON_USER_EXTI_Callback(void);
+#if (USE_BSP_COM_FEATURE > 0)
+static void COM1_MspInit(UART_HandleTypeDef *huart);
+static void COM1_MspDeInit(UART_HandleTypeDef *huart);
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup STM32H7XX_NUCLEO_LOW_LEVEL_Exported_Functions LOW LEVEL Exported Functions
+ * @{
+ */
+
+/**
+ * @brief This method returns the STM32H7XX NUCLEO BSP Driver revision
+ * @retval version: 0xXYZR (8bits for each decimal, R for RC)
+ */
+int32_t BSP_GetVersion(void)
+{
+ return (int32_t)STM32H7XX_NUCLEO_BSP_VERSION;
+}
+
+/**
+ * @brief Configures LED GPIO.
+ * @param Led Specifies the Led to be configured.
+ * This parameter can be one of following parameters:
+ * @arg LED1
+ * @arg LED2
+ * @arg LED3
+ * @retval BSP status
+ */
+int32_t BSP_LED_Init(Led_TypeDef Led)
+{
+ int32_t ret = BSP_ERROR_NONE;
+ GPIO_InitTypeDef gpio_init_structure;
+
+ if((Led != LED1) && (Led != LED2) && (Led != LED3))
+ {
+ ret = BSP_ERROR_WRONG_PARAM;
+ }
+ else
+ {
+ /* Enable the GPIO LED Clock */
+ if(Led == LED1)
+ {
+ LED1_GPIO_CLK_ENABLE();
+ }
+ else if(Led == LED2)
+ {
+ LED2_GPIO_CLK_ENABLE();
+ }
+ else
+ {
+ LED3_GPIO_CLK_ENABLE();
+ }
+ /* Configure the GPIO_LED pin */
+ gpio_init_structure.Pin = LED_PIN[Led];
+ gpio_init_structure.Mode = GPIO_MODE_OUTPUT_PP;
+ gpio_init_structure.Pull = GPIO_NOPULL;
+ gpio_init_structure.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+
+ HAL_GPIO_Init(LED_PORT[Led], &gpio_init_structure);
+ HAL_GPIO_WritePin(LED_PORT[Led], LED_PIN[Led], GPIO_PIN_RESET);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief DeInit LEDs.
+ * @param Led LED to be de-init.
+ * This parameter can be one of the following values:
+ * @arg LED1
+ * @arg LED2
+ * @arg LED3
+ * @note Led DeInit does not disable the GPIO clock nor disable the Mfx
+ * @retval BSP status
+ */
+int32_t BSP_LED_DeInit(Led_TypeDef Led)
+{
+ int32_t ret = BSP_ERROR_NONE;
+ GPIO_InitTypeDef gpio_init_structure;
+
+ if((Led != LED1) && (Led != LED2) && (Led != LED3))
+ {
+ ret = BSP_ERROR_WRONG_PARAM;
+ }
+ else
+ {
+ /* Turn off LED */
+ HAL_GPIO_WritePin(LED_PORT[Led], LED_PIN[Led], GPIO_PIN_RESET);
+ /* DeInit the GPIO_LED pin */
+ gpio_init_structure.Pin = LED_PIN[Led];
+ HAL_GPIO_DeInit(LED_PORT[Led], gpio_init_structure.Pin);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Turns selected LED On.
+ * @param Led Specifies the Led to be set on.
+ * This parameter can be one of following parameters:
+ * @arg LED1
+ * @arg LED2
+ * @arg LED3
+ * @retval BSP status
+ */
+int32_t BSP_LED_On(Led_TypeDef Led)
+{
+ int32_t ret = BSP_ERROR_NONE;
+
+ if((Led != LED1) && (Led != LED2) && (Led != LED3))
+ {
+ ret = BSP_ERROR_WRONG_PARAM;
+ }
+ else
+ {
+ HAL_GPIO_WritePin(LED_PORT[Led], LED_PIN[Led], GPIO_PIN_SET);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Turns selected LED Off.
+ * @param Led: Specifies the Led to be set off.
+ * This parameter can be one of following parameters:
+ * @arg LED1
+ * @arg LED2
+ * @arg LED3
+ * @retval BSP status
+ */
+int32_t BSP_LED_Off(Led_TypeDef Led)
+{
+ int32_t ret = BSP_ERROR_NONE;
+
+ if((Led != LED1) && (Led != LED2) && (Led != LED3))
+ {
+ ret = BSP_ERROR_WRONG_PARAM;
+ }
+ else
+ {
+ HAL_GPIO_WritePin(LED_PORT[Led], LED_PIN[Led], GPIO_PIN_RESET);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Toggles the selected LED.
+ * @param Led Specifies the Led to be toggled.
+ * This parameter can be one of following parameters:
+ * @arg LED1
+ * @arg LED2
+ * @arg LED3
+ * @retval BSP status
+ */
+int32_t BSP_LED_Toggle(Led_TypeDef Led)
+{
+ int32_t ret = BSP_ERROR_NONE;
+
+ if((Led != LED1) && (Led != LED2) && (Led != LED3))
+ {
+ ret = BSP_ERROR_WRONG_PARAM;
+ }
+ else
+ {
+ HAL_GPIO_TogglePin(LED_PORT[Led], LED_PIN[Led]);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Get the state of the selected LED.
+ * @param Led LED to get its state
+ * This parameter can be one of following parameters:
+ * @arg LED1
+ * @arg LED2
+ * @arg LED3
+ * @retval LED status
+ */
+int32_t BSP_LED_GetState (Led_TypeDef Led)
+{
+ int32_t ret;
+
+ if((Led != LED1) && (Led != LED2) && (Led != LED3))
+ {
+ ret = BSP_ERROR_WRONG_PARAM;
+ }
+ else
+ {
+ ret = (int32_t)HAL_GPIO_ReadPin (LED_PORT [Led], LED_PIN [Led]);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Configures button GPIO and EXTI Line.
+ * @param Button Button to be configured
+ * This parameter can be one of the following values:
+ * @arg BUTTON_USER: Wakeup Push Button
+ * @param ButtonMode Button mode
+ * This parameter can be one of the following values:
+ * @arg BUTTON_MODE_GPIO: Button will be used as simple IO
+ * @arg BUTTON_MODE_EXTI: Button will be connected to EXTI line
+ * with interrupt generation capability
+ */
+int32_t BSP_PB_Init(Button_TypeDef Button, ButtonMode_TypeDef ButtonMode)
+{
+ GPIO_InitTypeDef gpio_init_structure;
+ static BSP_EXTI_LineCallback ButtonCallback[BUTTONn] = {BUTTON_USER_EXTI_Callback};
+ static uint32_t BSP_BUTTON_PRIO [BUTTONn] = {BSP_BUTTON_USER_IT_PRIORITY};
+ static const uint32_t BUTTON_EXTI_LINE[BUTTONn] = {BUTTON_USER_EXTI_LINE};
+
+ /* Enable the BUTTON clock */
+ BUTTON_USER_GPIO_CLK_ENABLE();
+
+ gpio_init_structure.Pin = BUTTON_PIN [Button];
+ gpio_init_structure.Pull = GPIO_PULLDOWN;
+ gpio_init_structure.Speed = GPIO_SPEED_FREQ_HIGH;
+
+ if(ButtonMode == BUTTON_MODE_GPIO)
+ {
+ /* Configure Button pin as input */
+ gpio_init_structure.Mode = GPIO_MODE_INPUT;
+ HAL_GPIO_Init(BUTTON_PORT [Button], &gpio_init_structure);
+ }
+ else /* (ButtonMode == BUTTON_MODE_EXTI) */
+ {
+ /* Configure Button pin as input with External interrupt */
+ gpio_init_structure.Mode = GPIO_MODE_IT_RISING;
+
+ HAL_GPIO_Init(BUTTON_PORT[Button], &gpio_init_structure);
+
+ (void)HAL_EXTI_GetHandle(&hpb_exti[Button], BUTTON_EXTI_LINE[Button]);
+ (void)HAL_EXTI_RegisterCallback(&hpb_exti[Button], HAL_EXTI_COMMON_CB_ID, ButtonCallback[Button]);
+
+ /* Enable and set Button EXTI Interrupt to the lowest priority */
+ HAL_NVIC_SetPriority((BUTTON_IRQn[Button]), BSP_BUTTON_PRIO[Button], 0x00);
+ HAL_NVIC_EnableIRQ((BUTTON_IRQn[Button]));
+ }
+
+ return BSP_ERROR_NONE;
+}
+
+/**
+ * @brief Push Button DeInit.
+ * @param Button Button to be configured
+ * This parameter can be one of the following values:
+ * @arg BUTTON_USER: Wakeup Push Button
+ * @note PB DeInit does not disable the GPIO clock
+ */
+int32_t BSP_PB_DeInit(Button_TypeDef Button)
+{
+ GPIO_InitTypeDef gpio_init_structure;
+
+ gpio_init_structure.Pin = BUTTON_PIN[Button];
+ HAL_NVIC_DisableIRQ((IRQn_Type)(BUTTON_IRQn[Button]));
+ HAL_GPIO_DeInit(BUTTON_PORT[Button], gpio_init_structure.Pin);
+
+ return BSP_ERROR_NONE;
+}
+
+/**
+ * @brief Returns the selected button state.
+ * @param Button Button to be checked
+ * This parameter can be one of the following values:
+ * @arg BUTTON_USER: Wakeup Push Button
+ * @retval The Button GPIO pin value (GPIO_PIN_RESET = button pressed)
+ */
+int32_t BSP_PB_GetState(Button_TypeDef Button)
+{
+ return (int32_t)HAL_GPIO_ReadPin(BUTTON_PORT[Button], BUTTON_PIN[Button]);
+}
+
+/**
+ * @brief BSP Button IRQ handler
+ * @param Button Can only be BUTTON_USER
+ * @retval None
+ */
+void BSP_PB_IRQHandler(Button_TypeDef Button)
+{
+ HAL_EXTI_IRQHandler(&hpb_exti[Button]);
+}
+
+/**
+ * @brief BSP Push Button callback
+ * @param Button Specifies the pin connected EXTI line
+ * @retval None
+ */
+__weak void BSP_PB_Callback(Button_TypeDef Button)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(Button);
+
+ /* This function should be implemented by the user application.
+ It is called into this driver when an event on Button is triggered. */
+}
+
+#if (USE_BSP_COM_FEATURE > 0)
+/**
+ * @brief Configures COM port.
+ * @param COM COM port to be configured.
+ * This parameter can be COM1
+ * @param COM_Init Pointer to a UART_HandleTypeDef structure that contains the
+ * configuration information for the specified USART peripheral.
+ * @retval BSP error code
+ */
+int32_t BSP_COM_Init(COM_TypeDef COM, COM_InitTypeDef *COM_Init)
+{
+ int32_t ret = BSP_ERROR_NONE;
+
+ if(COM >= COMn)
+ {
+ ret = BSP_ERROR_WRONG_PARAM;
+ }
+ else
+ {
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 0)
+ /* Init the UART Msp */
+ COM1_MspInit(&hcom_uart[COM]);
+#else
+ if(IsComMspCbValid[COM] == 0U)
+ {
+ if(BSP_COM_RegisterDefaultMspCallbacks(COM) != BSP_ERROR_NONE)
+ {
+ return BSP_ERROR_MSP_FAILURE;
+ }
+ }
+#endif
+
+ if(MX_USART3_Init(&hcom_uart[COM], COM_Init) != HAL_OK)
+ {
+ ret = BSP_ERROR_PERIPH_FAILURE;
+ }
+ }
+
+ return ret;
+}
+
+/**
+ * @brief DeInit COM port.
+ * @param COM COM port to be configured.
+ * This parameter can be COM1
+ * @retval BSP status
+ */
+int32_t BSP_COM_DeInit(COM_TypeDef COM)
+{
+ int32_t ret = BSP_ERROR_NONE;
+
+ if(COM >= COMn)
+ {
+ ret = BSP_ERROR_WRONG_PARAM;
+ }
+ else
+ {
+ /* USART configuration */
+ hcom_uart[COM].Instance = COM_USART[COM];
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 0)
+ COM1_MspDeInit(&hcom_uart[COM]);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS == 0) */
+
+ if(HAL_UART_DeInit(&hcom_uart[COM]) != HAL_OK)
+ {
+ ret = BSP_ERROR_PERIPH_FAILURE;
+ }
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Configures COM port.
+ * @param huart USART handle
+ * @param COM_Init Pointer to a UART_HandleTypeDef structure that contains the
+ * configuration information for the specified USART peripheral.
+ * @retval HAL error code
+ */
+__weak HAL_StatusTypeDef MX_USART3_Init(UART_HandleTypeDef *huart, MX_UART_InitTypeDef *COM_Init)
+{
+ /* USART configuration */
+ huart->Instance = COM_USART[COM1];
+ huart->Init.BaudRate = COM_Init->BaudRate;
+ huart->Init.Mode = UART_MODE_TX_RX;
+ huart->Init.Parity = (uint32_t)COM_Init->Parity;
+ huart->Init.WordLength = (uint32_t)COM_Init->WordLength;
+ huart->Init.StopBits = (uint32_t)COM_Init->StopBits;
+ huart->Init.HwFlowCtl = (uint32_t)COM_Init->HwFlowCtl;
+ huart->Init.OverSampling = UART_OVERSAMPLING_8;
+
+ return HAL_UART_Init(huart);
+}
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register Default COM Msp Callbacks
+ * @param COM COM port to be configured.
+ * This parameter can be COM1
+ * @retval BSP status
+ */
+int32_t BSP_COM_RegisterDefaultMspCallbacks(COM_TypeDef COM)
+{
+ int32_t ret = BSP_ERROR_NONE;
+
+ if(COM >= COMn)
+ {
+ ret = BSP_ERROR_WRONG_PARAM;
+ }
+ else
+ {
+ __HAL_UART_RESET_HANDLE_STATE(&hcom_uart[COM]);
+
+ /* Register default MspInit/MspDeInit Callback */
+ if(HAL_UART_RegisterCallback(&hcom_uart[COM], HAL_UART_MSPINIT_CB_ID, COM1_MspInit) != HAL_OK)
+ {
+ ret = BSP_ERROR_PERIPH_FAILURE;
+ }
+ else if(HAL_UART_RegisterCallback(&hcom_uart[COM], HAL_UART_MSPDEINIT_CB_ID, COM1_MspDeInit) != HAL_OK)
+ {
+ ret = BSP_ERROR_PERIPH_FAILURE;
+ }
+ else
+ {
+ IsComMspCbValid[COM] = 1U;
+ }
+ }
+
+ /* BSP status */
+ return ret;
+}
+
+/**
+ * @brief Register COM Msp Callback registering
+ * @param COM COM port to be configured.
+ * This parameter can be COM1
+ * @param Callbacks pointer to COM1 MspInit/MspDeInit callback functions
+ * @retval BSP status
+ */
+int32_t BSP_COM_RegisterMspCallbacks(COM_TypeDef COM , BSP_COM_Cb_t *Callback)
+{
+ int32_t ret = BSP_ERROR_NONE;
+
+ if(COM >= COMn)
+ {
+ ret = BSP_ERROR_WRONG_PARAM;
+ }
+ else
+ {
+ __HAL_UART_RESET_HANDLE_STATE(&hcom_uart[COM]);
+
+ /* Register MspInit/MspDeInit Callbacks */
+ if(HAL_UART_RegisterCallback(&hcom_uart[COM], HAL_UART_MSPINIT_CB_ID, Callback->pMspInitCb) != HAL_OK)
+ {
+ ret = BSP_ERROR_PERIPH_FAILURE;
+ }
+ else if(HAL_UART_RegisterCallback(&hcom_uart[COM], HAL_UART_MSPDEINIT_CB_ID, Callback->pMspDeInitCb) != HAL_OK)
+ {
+ ret = BSP_ERROR_PERIPH_FAILURE;
+ }
+ else
+ {
+ IsComMspCbValid[COM] = 1U;
+ }
+ }
+ /* BSP status */
+ return ret;
+}
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+
+#if (USE_COM_LOG > 0)
+/**
+ * @brief Select the active COM port.
+ * @param COM COM port to be activated.
+ * This parameter can be COM1
+ * @retval BSP status
+ */
+int32_t BSP_COM_SelectLogPort(COM_TypeDef COM)
+{
+ if(COM_ActiveLogPort != COM)
+ {
+ COM_ActiveLogPort = COM;
+ }
+ return BSP_ERROR_NONE;
+}
+
+/**
+ * @brief Redirect console output to COM
+ */
+ #ifdef __GNUC__
+ int __io_putchar (int ch)
+ #else
+ int fputc (int ch, FILE *f)
+ #endif /* __GNUC__ */
+{
+ HAL_UART_Transmit (&hcom_uart [COM_ActiveLogPort], (uint8_t *) &ch, 1, COM_POLL_TIMEOUT);
+ return ch;
+}
+#endif /* USE_COM_LOG */
+#endif /* USE_BSP_COM_FEATURE */
+
+/**
+ * @}
+ */
+
+/** @defgroup STM32H7XX_NUCLEO_LOW_LEVEL_Private_Functions LOW LEVEL Private functions
+ * @{
+ */
+/**
+ * @brief Key EXTI line detection callbacks.
+ * @retval BSP status
+ */
+static void BUTTON_USER_EXTI_Callback(void)
+{
+ BSP_PB_Callback(BUTTON_USER);
+}
+
+#if (USE_BSP_COM_FEATURE > 0)
+/**
+ * @brief Initializes UART MSP.
+ * @param huart UART handle
+ * @retval BSP status
+ */
+static void COM1_MspInit(UART_HandleTypeDef *huart)
+{
+ GPIO_InitTypeDef gpio_init_structure;
+
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(huart);
+
+ /* Enable GPIO clock */
+ COM1_TX_GPIO_CLK_ENABLE();
+ COM1_RX_GPIO_CLK_ENABLE();
+
+ /* Enable USART clock */
+ COM1_CLK_ENABLE();
+
+ /* Configure USART Tx as alternate function */
+ gpio_init_structure.Pin = COM1_TX_PIN;
+ gpio_init_structure.Mode = GPIO_MODE_AF_PP;
+ gpio_init_structure.Speed = GPIO_SPEED_FREQ_HIGH;
+ gpio_init_structure.Pull = GPIO_PULLUP;
+ gpio_init_structure.Alternate = COM1_TX_AF;
+ HAL_GPIO_Init(COM1_TX_GPIO_PORT, &gpio_init_structure);
+
+ /* Configure USART Rx as alternate function */
+ gpio_init_structure.Pin = COM1_RX_PIN;
+ gpio_init_structure.Mode = GPIO_MODE_AF_PP;
+ gpio_init_structure.Alternate = COM1_RX_AF;
+ HAL_GPIO_Init(COM1_RX_GPIO_PORT, &gpio_init_structure);
+}
+
+/**
+ * @brief Initialize USART3 Msp part
+ * @param huart UART handle
+ * @retval BSP status
+ */
+static void COM1_MspDeInit(UART_HandleTypeDef *huart)
+{
+ GPIO_InitTypeDef gpio_init_structure;
+
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(huart);
+
+ /* COM GPIO pin configuration */
+ gpio_init_structure.Pin = COM1_TX_PIN;
+ HAL_GPIO_DeInit(COM1_TX_GPIO_PORT, gpio_init_structure.Pin);
+
+ gpio_init_structure.Pin = COM1_RX_PIN;
+ HAL_GPIO_DeInit(COM1_RX_GPIO_PORT, gpio_init_structure.Pin);
+
+ /* Disable USART clock */
+ COM1_CLK_DISABLE();
+}
+#endif /* USE_BSP_COM_FEATURE */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp_stm32h7_freertos/core/InitMission.cpp b/bsp_stm32h7_freertos/core/InitMission.cpp
index 068df10..82836c1 100644
--- a/bsp_stm32h7_freertos/core/InitMission.cpp
+++ b/bsp_stm32h7_freertos/core/InitMission.cpp
@@ -1,8 +1,6 @@
#include "InitMission.h"
-
-#include
-
-#include
+#include "OBSWConfig.h"
+#include "FreeRTOS.h"
#include
#include
@@ -32,6 +30,7 @@ void InitMission::createTasks() {
task::printInitError("TM funnel", objects::TM_FUNNEL);
}
+#if OBSW_ADD_LWIP_COMPONENTS == 1
/* UDP bridge */
PeriodicTaskIF* udpBridgeTask = TaskFactory::instance()->createPeriodicTask(
"UDP_UNIX_BRIDGE", 6, 1024 * 2, 0.2, nullptr);
@@ -45,6 +44,7 @@ void InitMission::createTasks() {
if(result != HasReturnvaluesIF::RETURN_OK) {
task::printInitError("UDP polling task", objects::UDP_POLLING_TASK);
}
+#endif /* OBSW_ADD_LWIP_COMPONENTS == 1 */
PeriodicTaskIF* eventManagerTask = TaskFactory::instance()->createPeriodicTask(
"EVENT_MGMT", 4, 1024 * 2, 0.1, nullptr);
@@ -146,8 +146,10 @@ void InitMission::createTasks() {
#if OBSW_ADD_CORE_COMPONENTS == 1
distributerTask->startTask();
eventManagerTask->startTask();
+#if OBSW_ADD_LWIP_COMPONENTS == 1
udpBridgeTask->startTask();
udpPollingTask->startTask();
+#endif /* OBSW_ADD_LWIP_COMPONENTS == 1 */
#endif /* OBSW_ADD_CORE_COMPONENTS == 1 */
#if OBSW_ADD_PUS_STACK == 1
diff --git a/bsp_stm32h7_freertos/core/ObjectFactory.cpp b/bsp_stm32h7_freertos/core/ObjectFactory.cpp
index 3935aa6..71d8281 100644
--- a/bsp_stm32h7_freertos/core/ObjectFactory.cpp
+++ b/bsp_stm32h7_freertos/core/ObjectFactory.cpp
@@ -1,23 +1,25 @@
#include "ObjectFactory.h"
-
-#include
+#include "OBSWConfig.h"
#include
#include
#include
-#include
-#include
-#include
+#if OBSW_ADD_LWIP_COMPONENTS == 1
+#include "example_common/stm32h7/networking/UdpTcLwIpPollingTask.h"
+#include "example_common/stm32h7/networking/TmTcLwIpUdpBridge.h"
+#endif /* OBSW_ADD_LWIP_COMPONENTS == 1 */
+
+#include "example_common/stm32h7/STM32TestTask.h"
#include
#include
#include
-#include
+#include
#include
#include
-void ObjectFactory::produce() {
+void ObjectFactory::produce(void* args) {
/* Located inside GenericFactory source file */
Factory::setStaticFrameworkObjectIds();
@@ -43,10 +45,12 @@ void ObjectFactory::produce() {
new PoolManager(objects::IPC_STORE, poolCfg);
}
+#if OBSW_ADD_LWIP_COMPONENTS == 1
/* UDP Server */
new TmTcLwIpUdpBridge(objects::UDP_BRIDGE,
objects::CCSDS_DISTRIBUTOR, objects::TM_STORE, objects::TC_STORE);
new UdpTcLwIpPollingTask(objects::UDP_POLLING_TASK, objects::UDP_BRIDGE);
+#endif /* OBSW_ADD_LWIP_COMPONENTS == 1 */
#endif /* OBSW_ADD_CORE_COMPONENTS == 1 */
ObjectFactory::produceGenericObjects();
diff --git a/bsp_stm32h7_freertos/core/ObjectFactory.h b/bsp_stm32h7_freertos/core/ObjectFactory.h
index 0d78319..1151a9e 100644
--- a/bsp_stm32h7_freertos/core/ObjectFactory.h
+++ b/bsp_stm32h7_freertos/core/ObjectFactory.h
@@ -4,7 +4,7 @@
namespace ObjectFactory {
void setStatics();
- void produce();
+ void produce(void* args);
};
#endif /* MISSION_CORE_OBJECTFACTORY_H_ */
diff --git a/bsp_stm32h7_freertos/fsfwconfig/OBSWConfig.h.in b/bsp_stm32h7_freertos/fsfwconfig/OBSWConfig.h.in
index 0c88fcf..a1bd1b7 100644
--- a/bsp_stm32h7_freertos/fsfwconfig/OBSWConfig.h.in
+++ b/bsp_stm32h7_freertos/fsfwconfig/OBSWConfig.h.in
@@ -6,10 +6,14 @@
#ifndef FSFWCONFIG_OBSWCONFIG_H_
#define FSFWCONFIG_OBSWCONFIG_H_
-//! Specify whether TMTC commanding via Ethernet is possible
+// Specify whether lwIP components are added. TMTC commanding is not possible without them
+#define OBSW_ADD_LWIP_COMPONENTS 1
+
+// Specify whether TMTC commanding via Ethernet is possible
#define OBSW_ETHERNET_TMTC_COMMANDING 1
-//! Only applies if TMTC commanding is enabled.
-//! Specify whether LEDs are used to display Ethernet connection status.
+
+// Only applies if TMTC commanding is enabled.
+// Specify whether LEDs are used to display Ethernet connection status.
#define OBSW_ETHERNET_USE_LED1_LED2 0
#define OBSW_ATTEMPT_DHCP_CONN 1
@@ -25,7 +29,7 @@
#include "events/subsystemIdRanges.h"
#include "objects/systemObjectList.h"
-#include
+#include "commonConfig.h"
namespace config {
#endif
diff --git a/bsp_stm32h7_freertos/fsfwconfig/events/subsystemIdRanges.h b/bsp_stm32h7_freertos/fsfwconfig/events/subsystemIdRanges.h
index 809bc6f..c41aa68 100644
--- a/bsp_stm32h7_freertos/fsfwconfig/events/subsystemIdRanges.h
+++ b/bsp_stm32h7_freertos/fsfwconfig/events/subsystemIdRanges.h
@@ -1,7 +1,7 @@
#ifndef FSFWCONFIG_TMTC_SUBSYSTEMIDRANGES_H_
#define FSFWCONFIG_TMTC_SUBSYSTEMIDRANGES_H_
-#include
+#include "commonSubsystemIds.h"
namespace SUBSYSTEM_ID {
enum subsystemId: uint8_t {
diff --git a/bsp_stm32h7_freertos/fsfwconfig/pollingsequence/pollingSequenceFactory.h b/bsp_stm32h7_freertos/fsfwconfig/pollingsequence/pollingSequenceFactory.h
index 87dd281..b696b78 100644
--- a/bsp_stm32h7_freertos/fsfwconfig/pollingsequence/pollingSequenceFactory.h
+++ b/bsp_stm32h7_freertos/fsfwconfig/pollingsequence/pollingSequenceFactory.h
@@ -1,7 +1,7 @@
#ifndef POLLINGSEQUENCE_POLLINGSEQUENCFACTORY_H_
#define POLLINGSEQUENCE_POLLINGSEQUENCFACTORY_H_
-#include
+#include "OBSWConfig.h"
#include
class FixedTimeslotTaskIF;
diff --git a/bsp_stm32h7_freertos/main.cpp b/bsp_stm32h7_freertos/main.cpp
index 08b2843..d464d4b 100644
--- a/bsp_stm32h7_freertos/main.cpp
+++ b/bsp_stm32h7_freertos/main.cpp
@@ -2,12 +2,15 @@
#include "boardconfig.h"
#include "OBSWVersion.h"
#include "OBSWConfig.h"
+
+#if OBSW_ADD_LWIP_COMPONENTS == 1
#include
+#endif
#include "core/InitMission.h"
#include "core/ObjectFactory.h"
-#include
+#include "example_common/utility/utility.h"
#include
#include
@@ -34,8 +37,6 @@ ServiceInterfaceStream sif::warning("WARNING", true);
ServiceInterfaceStream sif::error("ERROR", true);
#endif
-ObjectManagerIF *objectManager = nullptr;
-
void initTask(void *parameters);
/**
@@ -57,11 +58,13 @@ int main() {
}
void initTask(void *parameters) {
+#if OBSW_ADD_LWIP_COMPONENTS == 1
/* Initialize the LwIP stack */
lwip_init();
/* Configure the Network interface */
Netif_Config();
+#endif
utility::commonInitPrint("FreeRTOS", BOARD_NAME);
@@ -71,8 +74,10 @@ void initTask(void *parameters) {
sif::printInfo("Creating objects..\n\r");
#endif
- objectManager = new ObjectManager(ObjectFactory::produce);
- objectManager->initialize();
+ ObjectManager* objManager = ObjectManager::instance();
+ objManager->setObjectFactoryFunction(ObjectFactory::produce, nullptr);
+ objManager->initialize();
+
#if FSFW_CPP_OSTREAM_ENABLED == 1
sif::info << "Creating tasks.." << std::endl;
#else
diff --git a/cmake/stm32-cmake b/cmake/stm32-cmake
index 89c68c6..ae93e9f 160000
--- a/cmake/stm32-cmake
+++ b/cmake/stm32-cmake
@@ -1 +1 @@
-Subproject commit 89c68c69a17435035a4a48712936e06118bed3fb
+Subproject commit ae93e9f49b911a1f4c49bb2fe228928f72c8cddf
diff --git a/example_common b/example_common
index ff6025d..20842a2 160000
--- a/example_common
+++ b/example_common
@@ -1 +1 @@
-Subproject commit ff6025d04d2b3abd278d909c2844bd808bee06b4
+Subproject commit 20842a26af4050b3176d915fac6e86bdb32fba3a
diff --git a/fsfw b/fsfw
index b00bfe4..ff63a34 160000
--- a/fsfw
+++ b/fsfw
@@ -1 +1 @@
-Subproject commit b00bfe4bdaa34cd8d608a39cec622803be65eee1
+Subproject commit ff63a3438410e4bed2f7c02e6f4a460135f32d00
diff --git a/misc/eclipse/.cproject b/misc/eclipse/.cproject
index 1451558..fa4f877 100644
--- a/misc/eclipse/.cproject
+++ b/misc/eclipse/.cproject
@@ -2,10 +2,10 @@
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diff --git a/misc/eclipse/fsfw-stm32-freertos-debug.launch b/misc/eclipse/fsfw-stm32-freertos-debug.launch
new file mode 100644
index 0000000..c344afd
--- /dev/null
+++ b/misc/eclipse/fsfw-stm32-freertos-debug.launch
@@ -0,0 +1,64 @@
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diff --git a/misc/eclipse/fsfw-stm32-freertos-release.launch b/misc/eclipse/fsfw-stm32-freertos-release.launch
new file mode 100644
index 0000000..930287b
--- /dev/null
+++ b/misc/eclipse/fsfw-stm32-freertos-release.launch
@@ -0,0 +1,64 @@
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