105058 lines
3.7 MiB
105058 lines
3.7 MiB
<?xml version="1.0" encoding="utf-8" standalone="no"?>
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<!--
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Copyright (c) 2021 STMicroelectronics.
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SPDX-License-Identifier: Apache-2.0
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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-->
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<device schemaVersion="1.1"
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xmlns:xs="http://www.w3.org/2001/XMLSchema-instance"
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xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
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<name>STM32H743</name>
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<version>1.4</version>
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<description>STM32H743</description>
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<cpu>
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<name>CM7</name>
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<revision>r0p1</revision>
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<endian>little</endian>
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<mpuPresent>true</mpuPresent>
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<fpuPresent>true</fpuPresent>
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<nvicPrioBits>4</nvicPrioBits>
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<vendorSystickConfig>false</vendorSystickConfig>
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</cpu>
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<!--Bus Interface Properties-->
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<!--Cortex-M3 is byte addressable-->
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<addressUnitBits>8</addressUnitBits>
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<!--the maximum data bit width accessible within a single transfer-->
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<width>32</width>
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<!--Register Default Properties-->
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<size>0x20</size>
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<resetValue>0x0</resetValue>
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<resetMask>0xFFFFFFFF</resetMask>
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<peripherals>
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<peripheral>
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<name>COMP1</name>
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<description>COMP1</description>
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<groupName>COMP1</groupName>
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<baseAddress>0x58003800</baseAddress>
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<addressBlock>
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<offset>0x0</offset>
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<size>0x400</size>
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<usage>registers</usage>
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</addressBlock>
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<interrupt>
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<name>COMP</name>
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<description>COMP1 and COMP2</description>
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<value>137</value>
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</interrupt>
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<registers>
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<register>
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<name>SR</name>
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<displayName>SR</displayName>
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<description>Comparator status register</description>
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<addressOffset>0x0</addressOffset>
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<size>0x20</size>
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<access>read-only</access>
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<resetValue>0x00000000</resetValue>
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<fields>
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<field>
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<name>C1VAL</name>
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<description>COMP channel 1 output status
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bit</description>
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<bitOffset>0</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>C2VAL</name>
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<description>COMP channel 2 output status
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bit</description>
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<bitOffset>1</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>C1IF</name>
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<description>COMP channel 1 Interrupt
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Flag</description>
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<bitOffset>16</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>C2IF</name>
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<description>COMP channel 2 Interrupt
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Flag</description>
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<bitOffset>17</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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</fields>
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</register>
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<register>
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<name>ICFR</name>
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<displayName>ICFR</displayName>
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<description>Comparator interrupt clear flag
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register</description>
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<addressOffset>0x4</addressOffset>
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<size>0x20</size>
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<access>write-only</access>
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<resetValue>0x00000000</resetValue>
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<fields>
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<field>
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<name>CC1IF</name>
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<description>Clear COMP channel 1 Interrupt
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Flag</description>
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<bitOffset>16</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>CC2IF</name>
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<description>Clear COMP channel 2 Interrupt
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Flag</description>
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<bitOffset>17</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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</fields>
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</register>
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<register>
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<name>OR</name>
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<displayName>OR</displayName>
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<description>Comparator option register</description>
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<addressOffset>0x8</addressOffset>
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<size>0x20</size>
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<access>read-write</access>
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<resetValue>0x00000000</resetValue>
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<fields>
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<field>
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<name>AFOP</name>
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<description>Selection of source for alternate
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function of output ports</description>
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<bitOffset>0</bitOffset>
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<bitWidth>11</bitWidth>
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</field>
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<field>
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<name>OR</name>
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<description>Option Register</description>
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<bitOffset>11</bitOffset>
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<bitWidth>21</bitWidth>
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</field>
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</fields>
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</register>
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<register>
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<name>CFGR1</name>
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<displayName>CFGR1</displayName>
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<description>Comparator configuration register
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1</description>
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<addressOffset>0xC</addressOffset>
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<size>0x20</size>
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<access>read-write</access>
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<resetValue>0x00000000</resetValue>
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<fields>
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<field>
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<name>EN</name>
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<description>COMP channel 1 enable bit</description>
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<bitOffset>0</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>BRGEN</name>
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<description>Scaler bridge enable</description>
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<bitOffset>1</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>SCALEN</name>
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<description>Voltage scaler enable bit</description>
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<bitOffset>2</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>POLARITY</name>
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<description>COMP channel 1 polarity selection
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bit</description>
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<bitOffset>3</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>ITEN</name>
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<description>COMP channel 1 interrupt
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enable</description>
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<bitOffset>6</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>HYST</name>
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<description>COMP channel 1 hysteresis selection
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bits</description>
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<bitOffset>8</bitOffset>
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<bitWidth>2</bitWidth>
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</field>
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<field>
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<name>PWRMODE</name>
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<description>Power Mode of the COMP channel
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1</description>
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<bitOffset>12</bitOffset>
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<bitWidth>2</bitWidth>
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</field>
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<field>
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<name>INMSEL</name>
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<description>COMP channel 1 inverting input selection
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field</description>
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<bitOffset>16</bitOffset>
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<bitWidth>3</bitWidth>
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</field>
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<field>
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<name>INPSEL</name>
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<description>COMP channel 1 non-inverting input
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selection bit</description>
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<bitOffset>20</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>BLANKING</name>
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<description>COMP channel 1 blanking source selection
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bits</description>
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<bitOffset>24</bitOffset>
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<bitWidth>4</bitWidth>
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</field>
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<field>
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<name>LOCK</name>
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<description>Lock bit</description>
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<bitOffset>31</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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</fields>
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</register>
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<register>
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<name>CFGR2</name>
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<displayName>CFGR2</displayName>
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<description>Comparator configuration register
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2</description>
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<addressOffset>0x10</addressOffset>
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<size>0x20</size>
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<access>read-write</access>
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<resetValue>0x00000000</resetValue>
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<fields>
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<field>
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<name>EN</name>
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<description>COMP channel 1 enable bit</description>
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<bitOffset>0</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>BRGEN</name>
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<description>Scaler bridge enable</description>
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<bitOffset>1</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>SCALEN</name>
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<description>Voltage scaler enable bit</description>
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<bitOffset>2</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>POLARITY</name>
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<description>COMP channel 1 polarity selection
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bit</description>
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<bitOffset>3</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>WINMODE</name>
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<description>Window comparator mode selection
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bit</description>
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<bitOffset>4</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>ITEN</name>
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<description>COMP channel 1 interrupt
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enable</description>
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<bitOffset>6</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>HYST</name>
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<description>COMP channel 1 hysteresis selection
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bits</description>
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<bitOffset>8</bitOffset>
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<bitWidth>2</bitWidth>
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</field>
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<field>
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<name>PWRMODE</name>
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<description>Power Mode of the COMP channel
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1</description>
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<bitOffset>12</bitOffset>
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<bitWidth>2</bitWidth>
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</field>
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<field>
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<name>INMSEL</name>
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<description>COMP channel 1 inverting input selection
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field</description>
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<bitOffset>16</bitOffset>
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<bitWidth>3</bitWidth>
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</field>
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<field>
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<name>INPSEL</name>
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<description>COMP channel 1 non-inverting input
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selection bit</description>
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<bitOffset>20</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>BLANKING</name>
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<description>COMP channel 1 blanking source selection
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bits</description>
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<bitOffset>24</bitOffset>
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<bitWidth>4</bitWidth>
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</field>
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<field>
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<name>LOCK</name>
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<description>Lock bit</description>
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<bitOffset>31</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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</fields>
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</register>
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</registers>
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</peripheral>
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<peripheral>
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<name>CRS</name>
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<description>CRS</description>
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<groupName>CRS</groupName>
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<baseAddress>0x40008400</baseAddress>
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<addressBlock>
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<offset>0x0</offset>
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<size>0x400</size>
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<usage>registers</usage>
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</addressBlock>
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<interrupt>
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<name>CRS</name>
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<description>Clock Recovery System globa</description>
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<value>144</value>
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</interrupt>
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<registers>
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<register>
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<name>CR</name>
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<displayName>CR</displayName>
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<description>CRS control register</description>
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<addressOffset>0x0</addressOffset>
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<size>0x20</size>
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<resetValue>0x00002000</resetValue>
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<fields>
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<field>
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<name>SYNCOKIE</name>
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<description>SYNC event OK interrupt
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enable</description>
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<bitOffset>0</bitOffset>
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<bitWidth>1</bitWidth>
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<access>read-write</access>
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</field>
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<field>
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<name>SYNCWARNIE</name>
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<description>SYNC warning interrupt
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enable</description>
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<bitOffset>1</bitOffset>
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<bitWidth>1</bitWidth>
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<access>read-write</access>
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</field>
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<field>
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<name>ERRIE</name>
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<description>Synchronization or trimming error
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interrupt enable</description>
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<bitOffset>2</bitOffset>
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<bitWidth>1</bitWidth>
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<access>read-write</access>
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</field>
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<field>
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<name>ESYNCIE</name>
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<description>Expected SYNC interrupt
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enable</description>
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<bitOffset>3</bitOffset>
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<bitWidth>1</bitWidth>
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<access>read-write</access>
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</field>
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<field>
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<name>CEN</name>
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<description>Frequency error counter enable This bit
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enables the oscillator clock for the frequency error
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counter. When this bit is set, the CRS_CFGR register
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is write-protected and cannot be
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modified.</description>
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<bitOffset>5</bitOffset>
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<bitWidth>1</bitWidth>
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<access>read-write</access>
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</field>
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<field>
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<name>AUTOTRIMEN</name>
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<description>Automatic trimming enable This bit
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enables the automatic hardware adjustment of TRIM
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bits according to the measured frequency error
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between two SYNC events. If this bit is set, the TRIM
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bits are read-only. The TRIM value can be adjusted by
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hardware by one or two steps at a time, depending on
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the measured frequency error value. Refer to
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Section7.3.4: Frequency error evaluation and
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automatic trimming for more details.</description>
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<bitOffset>6</bitOffset>
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<bitWidth>1</bitWidth>
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<access>read-write</access>
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</field>
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<field>
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<name>SWSYNC</name>
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<description>Generate software SYNC event This bit is
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set by software in order to generate a software SYNC
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event. It is automatically cleared by
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hardware.</description>
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<bitOffset>7</bitOffset>
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<bitWidth>1</bitWidth>
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<access>read-only</access>
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</field>
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<field>
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<name>TRIM</name>
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<description>HSI48 oscillator smooth trimming These
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bits provide a user-programmable trimming value to
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the HSI48 oscillator. They can be programmed to
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adjust to variations in voltage and temperature that
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influence the frequency of the HSI48. The default
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value is 32, which corresponds to the middle of the
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trimming interval. The trimming step is around 67 kHz
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between two consecutive TRIM steps. A higher TRIM
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value corresponds to a higher output frequency. When
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the AUTOTRIMEN bit is set, this field is controlled
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by hardware and is read-only.</description>
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<bitOffset>8</bitOffset>
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<bitWidth>6</bitWidth>
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<access>read-write</access>
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</field>
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</fields>
|
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</register>
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<register>
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<name>CFGR</name>
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<displayName>CFGR</displayName>
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<description>This register can be written only when the
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|
frequency error counter is disabled (CEN bit is cleared
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in CRS_CR). When the counter is enabled, this register is
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write-protected.</description>
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|
<addressOffset>0x4</addressOffset>
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|
<size>0x20</size>
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<access>read-write</access>
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|
<resetValue>0x2022BB7F</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RELOAD</name>
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|
<description>Counter reload value RELOAD is the value
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|
to be loaded in the frequency error counter with each
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SYNC event. Refer to Section7.3.3: Frequency error
|
|
measurement for more details about counter
|
|
behavior.</description>
|
|
<bitOffset>0</bitOffset>
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|
<bitWidth>16</bitWidth>
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|
</field>
|
|
<field>
|
|
<name>FELIM</name>
|
|
<description>Frequency error limit FELIM contains the
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value to be used to evaluate the captured frequency
|
|
error value latched in the FECAP[15:0] bits of the
|
|
CRS_ISR register. Refer to Section7.3.4: Frequency
|
|
error evaluation and automatic trimming for more
|
|
details about FECAP evaluation.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SYNCDIV</name>
|
|
<description>SYNC divider These bits are set and
|
|
cleared by software to control the division factor of
|
|
the SYNC signal.</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SYNCSRC</name>
|
|
<description>SYNC signal source selection These bits
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|
are set and cleared by software to select the SYNC
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|
signal source. Note: When using USB LPM (Link Power
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|
Management) and the device is in Sleep mode, the
|
|
periodic USB SOF will not be generated by the host.
|
|
No SYNC signal will therefore be provided to the CRS
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|
to calibrate the HSI48 on the run. To guarantee the
|
|
required clock precision after waking up from Sleep
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|
mode, the LSE or reference clock on the GPIOs should
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|
be used as SYNC signal.</description>
|
|
<bitOffset>28</bitOffset>
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|
<bitWidth>2</bitWidth>
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|
</field>
|
|
<field>
|
|
<name>SYNCPOL</name>
|
|
<description>SYNC polarity selection This bit is set
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|
and cleared by software to select the input polarity
|
|
for the SYNC signal source.</description>
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|
<bitOffset>31</bitOffset>
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|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ISR</name>
|
|
<displayName>ISR</displayName>
|
|
<description>CRS interrupt and status
|
|
register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SYNCOKF</name>
|
|
<description>SYNC event OK flag This flag is set by
|
|
hardware when the measured frequency error is smaller
|
|
than FELIM * 3. This means that either no adjustment
|
|
of the TRIM value is needed or that an adjustment by
|
|
one trimming step is enough to compensate the
|
|
frequency error. An interrupt is generated if the
|
|
SYNCOKIE bit is set in the CRS_CR register. It is
|
|
cleared by software by setting the SYNCOKC bit in the
|
|
CRS_ICR register.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SYNCWARNF</name>
|
|
<description>SYNC warning flag This flag is set by
|
|
hardware when the measured frequency error is greater
|
|
than or equal to FELIM * 3, but smaller than FELIM *
|
|
128. This means that to compensate the frequency
|
|
error, the TRIM value must be adjusted by two steps
|
|
or more. An interrupt is generated if the SYNCWARNIE
|
|
bit is set in the CRS_CR register. It is cleared by
|
|
software by setting the SYNCWARNC bit in the CRS_ICR
|
|
register.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ERRF</name>
|
|
<description>Error flag This flag is set by hardware
|
|
in case of any synchronization or trimming error. It
|
|
is the logical OR of the TRIMOVF, SYNCMISS and
|
|
SYNCERR bits. An interrupt is generated if the ERRIE
|
|
bit is set in the CRS_CR register. It is cleared by
|
|
software in reaction to setting the ERRC bit in the
|
|
CRS_ICR register, which clears the TRIMOVF, SYNCMISS
|
|
and SYNCERR bits.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ESYNCF</name>
|
|
<description>Expected SYNC flag This flag is set by
|
|
hardware when the frequency error counter reached a
|
|
zero value. An interrupt is generated if the ESYNCIE
|
|
bit is set in the CRS_CR register. It is cleared by
|
|
software by setting the ESYNCC bit in the CRS_ICR
|
|
register.</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SYNCERR</name>
|
|
<description>SYNC error This flag is set by hardware
|
|
when the SYNC pulse arrives before the ESYNC event
|
|
and the measured frequency error is greater than or
|
|
equal to FELIM * 128. This means that the frequency
|
|
error is too big (internal frequency too low) to be
|
|
compensated by adjusting the TRIM value, and that
|
|
some other action should be taken. An interrupt is
|
|
generated if the ERRIE bit is set in the CRS_CR
|
|
register. It is cleared by software by setting the
|
|
ERRC bit in the CRS_ICR register.</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SYNCMISS</name>
|
|
<description>SYNC missed This flag is set by hardware
|
|
when the frequency error counter reached value FELIM
|
|
* 128 and no SYNC was detected, meaning either that a
|
|
SYNC pulse was missed or that the frequency error is
|
|
too big (internal frequency too high) to be
|
|
compensated by adjusting the TRIM value, and that
|
|
some other action should be taken. At this point, the
|
|
frequency error counter is stopped (waiting for a
|
|
next SYNC) and an interrupt is generated if the ERRIE
|
|
bit is set in the CRS_CR register. It is cleared by
|
|
software by setting the ERRC bit in the CRS_ICR
|
|
register.</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TRIMOVF</name>
|
|
<description>Trimming overflow or underflow This flag
|
|
is set by hardware when the automatic trimming tries
|
|
to over- or under-flow the TRIM value. An interrupt
|
|
is generated if the ERRIE bit is set in the CRS_CR
|
|
register. It is cleared by software by setting the
|
|
ERRC bit in the CRS_ICR register.</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FEDIR</name>
|
|
<description>Frequency error direction FEDIR is the
|
|
counting direction of the frequency error counter
|
|
latched in the time of the last SYNC event. It shows
|
|
whether the actual frequency is below or above the
|
|
target.</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FECAP</name>
|
|
<description>Frequency error capture FECAP is the
|
|
frequency error counter value latched in the time of
|
|
the last SYNC event. Refer to Section7.3.4: Frequency
|
|
error evaluation and automatic trimming for more
|
|
details about FECAP usage.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ICR</name>
|
|
<displayName>ICR</displayName>
|
|
<description>CRS interrupt flag clear
|
|
register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SYNCOKC</name>
|
|
<description>SYNC event OK clear flag Writing 1 to
|
|
this bit clears the SYNCOKF flag in the CRS_ISR
|
|
register.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SYNCWARNC</name>
|
|
<description>SYNC warning clear flag Writing 1 to
|
|
this bit clears the SYNCWARNF flag in the CRS_ISR
|
|
register.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ERRC</name>
|
|
<description>Error clear flag Writing 1 to this bit
|
|
clears TRIMOVF, SYNCMISS and SYNCERR bits and
|
|
consequently also the ERRF flag in the CRS_ISR
|
|
register.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ESYNCC</name>
|
|
<description>Expected SYNC clear flag Writing 1 to
|
|
this bit clears the ESYNCF flag in the CRS_ISR
|
|
register.</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>DAC</name>
|
|
<description>DAC</description>
|
|
<groupName>DAC</groupName>
|
|
<baseAddress>0x40007400</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>CR</name>
|
|
<displayName>CR</displayName>
|
|
<description>DAC control register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EN1</name>
|
|
<description>DAC channel1 enable This bit is set and
|
|
cleared by software to enable/disable DAC
|
|
channel1.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TEN1</name>
|
|
<description>DAC channel1 trigger
|
|
enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TSEL1</name>
|
|
<description>DAC channel1 trigger selection These
|
|
bits select the external event used to trigger DAC
|
|
channel1. Note: Only used if bit TEN1 = 1 (DAC
|
|
channel1 trigger enabled).</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WAVE1</name>
|
|
<description>DAC channel1 noise/triangle wave
|
|
generation enable These bits are set and cleared by
|
|
software. Note: Only used if bit TEN1 = 1 (DAC
|
|
channel1 trigger enabled).</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MAMP1</name>
|
|
<description>DAC channel1 mask/amplitude selector
|
|
These bits are written by software to select mask in
|
|
wave generation mode or amplitude in triangle
|
|
generation mode. = 1011: Unmask bits[11:0] of LFSR/
|
|
triangle amplitude equal to 4095</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DMAEN1</name>
|
|
<description>DAC channel1 DMA enable This bit is set
|
|
and cleared by software.</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DMAUDRIE1</name>
|
|
<description>DAC channel1 DMA Underrun Interrupt
|
|
enable This bit is set and cleared by
|
|
software.</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CEN1</name>
|
|
<description>DAC Channel 1 calibration enable This
|
|
bit is set and cleared by software to enable/disable
|
|
DAC channel 1 calibration, it can be written only if
|
|
bit EN1=0 into DAC_CR (the calibration mode can be
|
|
entered/exit only when the DAC channel is disabled)
|
|
Otherwise, the write operation is
|
|
ignored.</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EN2</name>
|
|
<description>DAC channel2 enable This bit is set and
|
|
cleared by software to enable/disable DAC
|
|
channel2.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TEN2</name>
|
|
<description>DAC channel2 trigger
|
|
enable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TSEL2</name>
|
|
<description>DAC channel2 trigger selection These
|
|
bits select the external event used to trigger DAC
|
|
channel2 Note: Only used if bit TEN2 = 1 (DAC
|
|
channel2 trigger enabled).</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WAVE2</name>
|
|
<description>DAC channel2 noise/triangle wave
|
|
generation enable These bits are set/reset by
|
|
software. 1x: Triangle wave generation enabled Note:
|
|
Only used if bit TEN2 = 1 (DAC channel2 trigger
|
|
enabled)</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MAMP2</name>
|
|
<description>DAC channel2 mask/amplitude selector
|
|
These bits are written by software to select mask in
|
|
wave generation mode or amplitude in triangle
|
|
generation mode. = 1011: Unmask bits[11:0] of LFSR/
|
|
triangle amplitude equal to 4095</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DMAEN2</name>
|
|
<description>DAC channel2 DMA enable This bit is set
|
|
and cleared by software.</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DMAUDRIE2</name>
|
|
<description>DAC channel2 DMA underrun interrupt
|
|
enable This bit is set and cleared by
|
|
software.</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CEN2</name>
|
|
<description>DAC Channel 2 calibration enable This
|
|
bit is set and cleared by software to enable/disable
|
|
DAC channel 2 calibration, it can be written only if
|
|
bit EN2=0 into DAC_CR (the calibration mode can be
|
|
entered/exit only when the DAC channel is disabled)
|
|
Otherwise, the write operation is
|
|
ignored.</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SWTRGR</name>
|
|
<displayName>SWTRGR</displayName>
|
|
<description>DAC software trigger register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SWTRIG1</name>
|
|
<description>DAC channel1 software trigger This bit
|
|
is set by software to trigger the DAC in software
|
|
trigger mode. Note: This bit is cleared by hardware
|
|
(one APB1 clock cycle later) once the DAC_DHR1
|
|
register value has been loaded into the DAC_DOR1
|
|
register.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWTRIG2</name>
|
|
<description>DAC channel2 software trigger This bit
|
|
is set by software to trigger the DAC in software
|
|
trigger mode. Note: This bit is cleared by hardware
|
|
(one APB1 clock cycle later) once the DAC_DHR2
|
|
register value has been loaded into the DAC_DOR2
|
|
register.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DHR12R1</name>
|
|
<displayName>DHR12R1</displayName>
|
|
<description>DAC channel1 12-bit right-aligned data
|
|
holding register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DACC1DHR</name>
|
|
<description>DAC channel1 12-bit right-aligned data
|
|
These bits are written by software which specifies
|
|
12-bit data for DAC channel1.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DHR12L1</name>
|
|
<displayName>DHR12L1</displayName>
|
|
<description>DAC channel1 12-bit left aligned data
|
|
holding register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DACC1DHR</name>
|
|
<description>DAC channel1 12-bit left-aligned data
|
|
These bits are written by software which specifies
|
|
12-bit data for DAC channel1.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DHR8R1</name>
|
|
<displayName>DHR8R1</displayName>
|
|
<description>DAC channel1 8-bit right aligned data
|
|
holding register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DACC1DHR</name>
|
|
<description>DAC channel1 8-bit right-aligned data
|
|
These bits are written by software which specifies
|
|
8-bit data for DAC channel1.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DHR12R2</name>
|
|
<displayName>DHR12R2</displayName>
|
|
<description>DAC channel2 12-bit right aligned data
|
|
holding register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DACC2DHR</name>
|
|
<description>DAC channel2 12-bit right-aligned data
|
|
These bits are written by software which specifies
|
|
12-bit data for DAC channel2.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DHR12L2</name>
|
|
<displayName>DHR12L2</displayName>
|
|
<description>DAC channel2 12-bit left aligned data
|
|
holding register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DACC2DHR</name>
|
|
<description>DAC channel2 12-bit left-aligned data
|
|
These bits are written by software which specify
|
|
12-bit data for DAC channel2.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DHR8R2</name>
|
|
<displayName>DHR8R2</displayName>
|
|
<description>DAC channel2 8-bit right-aligned data
|
|
holding register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DACC2DHR</name>
|
|
<description>DAC channel2 8-bit right-aligned data
|
|
These bits are written by software which specifies
|
|
8-bit data for DAC channel2.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DHR12RD</name>
|
|
<displayName>DHR12RD</displayName>
|
|
<description>Dual DAC 12-bit right-aligned data holding
|
|
register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DACC1DHR</name>
|
|
<description>DAC channel1 12-bit right-aligned data
|
|
These bits are written by software which specifies
|
|
12-bit data for DAC channel1.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DACC2DHR</name>
|
|
<description>DAC channel2 12-bit right-aligned data
|
|
These bits are written by software which specifies
|
|
12-bit data for DAC channel2.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DHR12LD</name>
|
|
<displayName>DHR12LD</displayName>
|
|
<description>DUAL DAC 12-bit left aligned data holding
|
|
register</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DACC1DHR</name>
|
|
<description>DAC channel1 12-bit left-aligned data
|
|
These bits are written by software which specifies
|
|
12-bit data for DAC channel1.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DACC2DHR</name>
|
|
<description>DAC channel2 12-bit left-aligned data
|
|
These bits are written by software which specifies
|
|
12-bit data for DAC channel2.</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DHR8RD</name>
|
|
<displayName>DHR8RD</displayName>
|
|
<description>DUAL DAC 8-bit right aligned data holding
|
|
register</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DACC1DHR</name>
|
|
<description>DAC channel1 8-bit right-aligned data
|
|
These bits are written by software which specifies
|
|
8-bit data for DAC channel1.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DACC2DHR</name>
|
|
<description>DAC channel2 8-bit right-aligned data
|
|
These bits are written by software which specifies
|
|
8-bit data for DAC channel2.</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DOR1</name>
|
|
<displayName>DOR1</displayName>
|
|
<description>DAC channel1 data output
|
|
register</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DACC1DOR</name>
|
|
<description>DAC channel1 data output These bits are
|
|
read-only, they contain data output for DAC
|
|
channel1.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DOR2</name>
|
|
<displayName>DOR2</displayName>
|
|
<description>DAC channel2 data output
|
|
register</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DACC2DOR</name>
|
|
<description>DAC channel2 data output These bits are
|
|
read-only, they contain data output for DAC
|
|
channel2.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SR</name>
|
|
<displayName>SR</displayName>
|
|
<description>DAC status register</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DMAUDR1</name>
|
|
<description>DAC channel1 DMA underrun flag This bit
|
|
is set by hardware and cleared by software (by
|
|
writing it to 1).</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CAL_FLAG1</name>
|
|
<description>DAC Channel 1 calibration offset status
|
|
This bit is set and cleared by hardware</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BWST1</name>
|
|
<description>DAC Channel 1 busy writing sample time
|
|
flag This bit is systematically set just after Sample
|
|
& Hold mode enable and is set each time the
|
|
software writes the register DAC_SHSR1, It is cleared
|
|
by hardware when the write operation of DAC_SHSR1 is
|
|
complete. (It takes about 3LSI periods of
|
|
synchronization).</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DMAUDR2</name>
|
|
<description>DAC channel2 DMA underrun flag This bit
|
|
is set by hardware and cleared by software (by
|
|
writing it to 1).</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CAL_FLAG2</name>
|
|
<description>DAC Channel 2 calibration offset status
|
|
This bit is set and cleared by hardware</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BWST2</name>
|
|
<description>DAC Channel 2 busy writing sample time
|
|
flag This bit is systematically set just after Sample
|
|
& Hold mode enable and is set each time the
|
|
software writes the register DAC_SHSR2, It is cleared
|
|
by hardware when the write operation of DAC_SHSR2 is
|
|
complete. (It takes about 3 LSI periods of
|
|
synchronization).</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCR</name>
|
|
<displayName>CCR</displayName>
|
|
<description>DAC calibration control
|
|
register</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OTRIM1</name>
|
|
<description>DAC Channel 1 offset trimming
|
|
value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OTRIM2</name>
|
|
<description>DAC Channel 2 offset trimming
|
|
value</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MCR</name>
|
|
<displayName>MCR</displayName>
|
|
<description>DAC mode control register</description>
|
|
<addressOffset>0x3C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MODE1</name>
|
|
<description>DAC Channel 1 mode These bits can be
|
|
written only when the DAC is disabled and not in the
|
|
calibration mode (when bit EN1=0 and bit CEN1 =0 in
|
|
the DAC_CR register). If EN1=1 or CEN1 =1 the write
|
|
operation is ignored. They can be set and cleared by
|
|
software to select the DAC Channel 1 mode: DAC
|
|
Channel 1 in normal Mode DAC Channel 1 in sample
|
|
&amp; hold mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODE2</name>
|
|
<description>DAC Channel 2 mode These bits can be
|
|
written only when the DAC is disabled and not in the
|
|
calibration mode (when bit EN2=0 and bit CEN2 =0 in
|
|
the DAC_CR register). If EN2=1 or CEN2 =1 the write
|
|
operation is ignored. They can be set and cleared by
|
|
software to select the DAC Channel 2 mode: DAC
|
|
Channel 2 in normal Mode DAC Channel 2 in sample
|
|
&amp; hold mode</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SHSR1</name>
|
|
<displayName>SHSR1</displayName>
|
|
<description>DAC Sample and Hold sample time register
|
|
1</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TSAMPLE1</name>
|
|
<description>DAC Channel 1 sample Time (only valid in
|
|
sample &amp; hold mode) These bits can be written
|
|
when the DAC channel1 is disabled or also during
|
|
normal operation. in the latter case, the write can
|
|
be done only when BWSTx of DAC_SR register is low, If
|
|
BWSTx=1, the write operation is
|
|
ignored.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SHSR2</name>
|
|
<displayName>SHSR2</displayName>
|
|
<description>DAC Sample and Hold sample time register
|
|
2</description>
|
|
<addressOffset>0x44</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TSAMPLE2</name>
|
|
<description>DAC Channel 2 sample Time (only valid in
|
|
sample &amp; hold mode) These bits can be written
|
|
when the DAC channel2 is disabled or also during
|
|
normal operation. in the latter case, the write can
|
|
be done only when BWSTx of DAC_SR register is low, if
|
|
BWSTx=1, the write operation is
|
|
ignored.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SHHR</name>
|
|
<displayName>SHHR</displayName>
|
|
<description>DAC Sample and Hold hold time
|
|
register</description>
|
|
<addressOffset>0x48</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00010001</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>THOLD1</name>
|
|
<description>DAC Channel 1 hold Time (only valid in
|
|
sample &amp; hold mode) Hold time= (THOLD[9:0]) x
|
|
T LSI</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>THOLD2</name>
|
|
<description>DAC Channel 2 hold time (only valid in
|
|
sample &amp; hold mode). Hold time= (THOLD[9:0])
|
|
x T LSI</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SHRR</name>
|
|
<displayName>SHRR</displayName>
|
|
<description>DAC Sample and Hold refresh time
|
|
register</description>
|
|
<addressOffset>0x4C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00010001</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TREFRESH1</name>
|
|
<description>DAC Channel 1 refresh Time (only valid
|
|
in sample &amp; hold mode) Refresh time=
|
|
(TREFRESH[7:0]) x T LSI</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TREFRESH2</name>
|
|
<description>DAC Channel 2 refresh Time (only valid
|
|
in sample &amp; hold mode) Refresh time=
|
|
(TREFRESH[7:0]) x T LSI</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>BDMA</name>
|
|
<description>BDMA</description>
|
|
<groupName>BDMA</groupName>
|
|
<baseAddress>0x58025400</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>BDMA_CH1</name>
|
|
<description>BDMA channel 1 interrupt</description>
|
|
<value>129</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>BDMA_CH2</name>
|
|
<description>BDMA channel 2 interrupt</description>
|
|
<value>130</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>BDMA_CH3</name>
|
|
<description>BDMA channel 3 interrupt</description>
|
|
<value>131</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>BDMA_CH4</name>
|
|
<description>BDMA channel 4 interrupt</description>
|
|
<value>132</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>BDMA_CH5</name>
|
|
<description>BDMA channel 5 interrupt</description>
|
|
<value>133</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>BDMA_CH6</name>
|
|
<description>BDMA channel 6 interrupt</description>
|
|
<value>134</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>BDMA_CH7</name>
|
|
<description>BDMA channel 7 interrupt</description>
|
|
<value>135</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>BDMA_CH8</name>
|
|
<description>BDMA channel 8 interrupt</description>
|
|
<value>136</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>ISR</name>
|
|
<displayName>ISR</displayName>
|
|
<description>DMA interrupt status register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>GIF1</name>
|
|
<description>Channel x global interrupt flag (x =
|
|
1..8) This bit is set by hardware. It is cleared by
|
|
software writing 1 to the corresponding bit in the
|
|
DMA_IFCR register.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCIF1</name>
|
|
<description>Channel x transfer complete flag (x =
|
|
1..8) This bit is set by hardware. It is cleared by
|
|
software writing 1 to the corresponding bit in the
|
|
DMA_IFCR register.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HTIF1</name>
|
|
<description>Channel x half transfer flag (x = 1..8)
|
|
This bit is set by hardware. It is cleared by
|
|
software writing 1 to the corresponding bit in the
|
|
DMA_IFCR register.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TEIF1</name>
|
|
<description>Channel x transfer error flag (x = 1..8)
|
|
This bit is set by hardware. It is cleared by
|
|
software writing 1 to the corresponding bit in the
|
|
DMA_IFCR register.</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GIF2</name>
|
|
<description>Channel x global interrupt flag (x =
|
|
1..8) This bit is set by hardware. It is cleared by
|
|
software writing 1 to the corresponding bit in the
|
|
DMA_IFCR register.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCIF2</name>
|
|
<description>Channel x transfer complete flag (x =
|
|
1..8) This bit is set by hardware. It is cleared by
|
|
software writing 1 to the corresponding bit in the
|
|
DMA_IFCR register.</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HTIF2</name>
|
|
<description>Channel x half transfer flag (x = 1..8)
|
|
This bit is set by hardware. It is cleared by
|
|
software writing 1 to the corresponding bit in the
|
|
DMA_IFCR register.</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TEIF2</name>
|
|
<description>Channel x transfer error flag (x = 1..8)
|
|
This bit is set by hardware. It is cleared by
|
|
software writing 1 to the corresponding bit in the
|
|
DMA_IFCR register.</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GIF3</name>
|
|
<description>Channel x global interrupt flag (x =
|
|
1..8) This bit is set by hardware. It is cleared by
|
|
software writing 1 to the corresponding bit in the
|
|
DMA_IFCR register.</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCIF3</name>
|
|
<description>Channel x transfer complete flag (x =
|
|
1..8) This bit is set by hardware. It is cleared by
|
|
software writing 1 to the corresponding bit in the
|
|
DMA_IFCR register.</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HTIF3</name>
|
|
<description>Channel x half transfer flag (x = 1..8)
|
|
This bit is set by hardware. It is cleared by
|
|
software writing 1 to the corresponding bit in the
|
|
DMA_IFCR register.</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TEIF3</name>
|
|
<description>Channel x transfer error flag (x = 1..8)
|
|
This bit is set by hardware. It is cleared by
|
|
software writing 1 to the corresponding bit in the
|
|
DMA_IFCR register.</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GIF4</name>
|
|
<description>Channel x global interrupt flag (x =
|
|
1..8) This bit is set by hardware. It is cleared by
|
|
software writing 1 to the corresponding bit in the
|
|
DMA_IFCR register.</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCIF4</name>
|
|
<description>Channel x transfer complete flag (x =
|
|
1..8) This bit is set by hardware. It is cleared by
|
|
software writing 1 to the corresponding bit in the
|
|
DMA_IFCR register.</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HTIF4</name>
|
|
<description>Channel x half transfer flag (x = 1..8)
|
|
This bit is set by hardware. It is cleared by
|
|
software writing 1 to the corresponding bit in the
|
|
DMA_IFCR register.</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TEIF4</name>
|
|
<description>Channel x transfer error flag (x = 1..8)
|
|
This bit is set by hardware. It is cleared by
|
|
software writing 1 to the corresponding bit in the
|
|
DMA_IFCR register.</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GIF5</name>
|
|
<description>Channel x global interrupt flag (x =
|
|
1..8) This bit is set by hardware. It is cleared by
|
|
software writing 1 to the corresponding bit in the
|
|
DMA_IFCR register.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCIF5</name>
|
|
<description>Channel x transfer complete flag (x =
|
|
1..8) This bit is set by hardware. It is cleared by
|
|
software writing 1 to the corresponding bit in the
|
|
DMA_IFCR register.</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HTIF5</name>
|
|
<description>Channel x half transfer flag (x = 1..8)
|
|
This bit is set by hardware. It is cleared by
|
|
software writing 1 to the corresponding bit in the
|
|
DMA_IFCR register.</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TEIF5</name>
|
|
<description>Channel x transfer error flag (x = 1..8)
|
|
This bit is set by hardware. It is cleared by
|
|
software writing 1 to the corresponding bit in the
|
|
DMA_IFCR register.</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GIF6</name>
|
|
<description>Channel x global interrupt flag (x =
|
|
1..8) This bit is set by hardware. It is cleared by
|
|
software writing 1 to the corresponding bit in the
|
|
DMA_IFCR register.</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCIF6</name>
|
|
<description>Channel x transfer complete flag (x =
|
|
1..8) This bit is set by hardware. It is cleared by
|
|
software writing 1 to the corresponding bit in the
|
|
DMA_IFCR register.</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HTIF6</name>
|
|
<description>Channel x half transfer flag (x = 1..8)
|
|
This bit is set by hardware. It is cleared by
|
|
software writing 1 to the corresponding bit in the
|
|
DMA_IFCR register.</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TEIF6</name>
|
|
<description>Channel x transfer error flag (x = 1..8)
|
|
This bit is set by hardware. It is cleared by
|
|
software writing 1 to the corresponding bit in the
|
|
DMA_IFCR register.</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GIF7</name>
|
|
<description>Channel x global interrupt flag (x =
|
|
1..8) This bit is set by hardware. It is cleared by
|
|
software writing 1 to the corresponding bit in the
|
|
DMA_IFCR register.</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCIF7</name>
|
|
<description>Channel x transfer complete flag (x =
|
|
1..8) This bit is set by hardware. It is cleared by
|
|
software writing 1 to the corresponding bit in the
|
|
DMA_IFCR register.</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HTIF7</name>
|
|
<description>Channel x half transfer flag (x = 1..8)
|
|
This bit is set by hardware. It is cleared by
|
|
software writing 1 to the corresponding bit in the
|
|
DMA_IFCR register.</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TEIF7</name>
|
|
<description>Channel x transfer error flag (x = 1..8)
|
|
This bit is set by hardware. It is cleared by
|
|
software writing 1 to the corresponding bit in the
|
|
DMA_IFCR register.</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GIF8</name>
|
|
<description>Channel x global interrupt flag (x =
|
|
1..8) This bit is set by hardware. It is cleared by
|
|
software writing 1 to the corresponding bit in the
|
|
DMA_IFCR register.</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCIF8</name>
|
|
<description>Channel x transfer complete flag (x =
|
|
1..8) This bit is set by hardware. It is cleared by
|
|
software writing 1 to the corresponding bit in the
|
|
DMA_IFCR register.</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HTIF8</name>
|
|
<description>Channel x half transfer flag (x = 1..8)
|
|
This bit is set by hardware. It is cleared by
|
|
software writing 1 to the corresponding bit in the
|
|
DMA_IFCR register.</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TEIF8</name>
|
|
<description>Channel x transfer error flag (x = 1..8)
|
|
This bit is set by hardware. It is cleared by
|
|
software writing 1 to the corresponding bit in the
|
|
DMA_IFCR register.</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IFCR</name>
|
|
<displayName>IFCR</displayName>
|
|
<description>DMA interrupt flag clear
|
|
register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CGIF1</name>
|
|
<description>Channel x global interrupt clear This
|
|
bit is set and cleared by software.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTCIF1</name>
|
|
<description>Channel x transfer complete clear This
|
|
bit is set and cleared by software.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHTIF1</name>
|
|
<description>Channel x half transfer clear This bit
|
|
is set and cleared by software.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTEIF1</name>
|
|
<description>Channel x transfer error clear This bit
|
|
is set and cleared by software.</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CGIF2</name>
|
|
<description>Channel x global interrupt clear This
|
|
bit is set and cleared by software.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTCIF2</name>
|
|
<description>Channel x transfer complete clear This
|
|
bit is set and cleared by software.</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHTIF2</name>
|
|
<description>Channel x half transfer clear This bit
|
|
is set and cleared by software.</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTEIF2</name>
|
|
<description>Channel x transfer error clear This bit
|
|
is set and cleared by software.</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CGIF3</name>
|
|
<description>Channel x global interrupt clear This
|
|
bit is set and cleared by software.</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTCIF3</name>
|
|
<description>Channel x transfer complete clear This
|
|
bit is set and cleared by software.</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHTIF3</name>
|
|
<description>Channel x half transfer clear This bit
|
|
is set and cleared by software.</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTEIF3</name>
|
|
<description>Channel x transfer error clear This bit
|
|
is set and cleared by software.</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CGIF4</name>
|
|
<description>Channel x global interrupt clear This
|
|
bit is set and cleared by software.</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTCIF4</name>
|
|
<description>Channel x transfer complete clear This
|
|
bit is set and cleared by software.</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHTIF4</name>
|
|
<description>Channel x half transfer clear This bit
|
|
is set and cleared by software.</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTEIF4</name>
|
|
<description>Channel x transfer error clear This bit
|
|
is set and cleared by software.</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CGIF5</name>
|
|
<description>Channel x global interrupt clear This
|
|
bit is set and cleared by software.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTCIF5</name>
|
|
<description>Channel x transfer complete clear This
|
|
bit is set and cleared by software.</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHTIF5</name>
|
|
<description>Channel x half transfer clear This bit
|
|
is set and cleared by software.</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTEIF5</name>
|
|
<description>Channel x transfer error clear This bit
|
|
is set and cleared by software.</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CGIF6</name>
|
|
<description>Channel x global interrupt clear This
|
|
bit is set and cleared by software.</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTCIF6</name>
|
|
<description>Channel x transfer complete clear This
|
|
bit is set and cleared by software.</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHTIF6</name>
|
|
<description>Channel x half transfer clear This bit
|
|
is set and cleared by software.</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTEIF6</name>
|
|
<description>Channel x transfer error clear This bit
|
|
is set and cleared by software.</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CGIF7</name>
|
|
<description>Channel x global interrupt clear This
|
|
bit is set and cleared by software.</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTCIF7</name>
|
|
<description>Channel x transfer complete clear This
|
|
bit is set and cleared by software.</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHTIF7</name>
|
|
<description>Channel x half transfer clear This bit
|
|
is set and cleared by software.</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTEIF7</name>
|
|
<description>Channel x transfer error clear This bit
|
|
is set and cleared by software.</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CGIF8</name>
|
|
<description>Channel x global interrupt clear This
|
|
bit is set and cleared by software.</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTCIF8</name>
|
|
<description>Channel x transfer complete clear This
|
|
bit is set and cleared by software.</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHTIF8</name>
|
|
<description>Channel x half transfer clear This bit
|
|
is set and cleared by software.</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTEIF8</name>
|
|
<description>Channel x transfer error clear This bit
|
|
is set and cleared by software.</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCR1</name>
|
|
<displayName>CCR1</displayName>
|
|
<description>DMA channel x configuration
|
|
register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EN</name>
|
|
<description>Channel enable This bit is set and
|
|
cleared by software.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCIE</name>
|
|
<description>Transfer complete interrupt enable This
|
|
bit is set and cleared by software.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HTIE</name>
|
|
<description>Half transfer interrupt enable This bit
|
|
is set and cleared by software.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TEIE</name>
|
|
<description>Transfer error interrupt enable This bit
|
|
is set and cleared by software.</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DIR</name>
|
|
<description>Data transfer direction This bit is set
|
|
and cleared by software.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CIRC</name>
|
|
<description>Circular mode This bit is set and
|
|
cleared by software.</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PINC</name>
|
|
<description>Peripheral increment mode This bit is
|
|
set and cleared by software.</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MINC</name>
|
|
<description>Memory increment mode This bit is set
|
|
and cleared by software.</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PSIZE</name>
|
|
<description>Peripheral size These bits are set and
|
|
cleared by software.</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSIZE</name>
|
|
<description>Memory size These bits are set and
|
|
cleared by software.</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PL</name>
|
|
<description>Channel priority level These bits are
|
|
set and cleared by software.</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MEM2MEM</name>
|
|
<description>Memory to memory mode This bit is set
|
|
and cleared by software.</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNDTR1</name>
|
|
<displayName>CNDTR1</displayName>
|
|
<description>DMA channel x number of data
|
|
register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>NDT</name>
|
|
<description>Number of data to transfer Number of
|
|
data to be transferred (0 up to 65535). This register
|
|
can only be written when the channel is disabled.
|
|
Once the channel is enabled, this register is
|
|
read-only, indicating the remaining bytes to be
|
|
transmitted. This register decrements after each DMA
|
|
transfer. Once the transfer is completed, this
|
|
register can either stay at zero or be reloaded
|
|
automatically by the value previously programmed if
|
|
the channel is configured in auto-reload mode. If
|
|
this register is zero, no transaction can be served
|
|
whether the channel is enabled or not.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CPAR1</name>
|
|
<displayName>CPAR1</displayName>
|
|
<description>This register must not be written when the
|
|
channel is enabled.</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PA</name>
|
|
<description>Peripheral address Base address of the
|
|
peripheral data register from/to which the data will
|
|
be read/written. When PSIZE is 01 (16-bit), the PA[0]
|
|
bit is ignored. Access is automatically aligned to a
|
|
half-word address. When PSIZE is 10 (32-bit), PA[1:0]
|
|
are ignored. Access is automatically aligned to a
|
|
word address.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMAR1</name>
|
|
<displayName>CMAR1</displayName>
|
|
<description>This register must not be written when the
|
|
channel is enabled.</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MA</name>
|
|
<description>Memory address Base address of the
|
|
memory area from/to which the data will be
|
|
read/written. When MSIZE is 01 (16-bit), the MA[0]
|
|
bit is ignored. Access is automatically aligned to a
|
|
half-word address. When MSIZE is 10 (32-bit), MA[1:0]
|
|
are ignored. Access is automatically aligned to a
|
|
word address.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCR2</name>
|
|
<displayName>CCR2</displayName>
|
|
<description>DMA channel x configuration
|
|
register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EN</name>
|
|
<description>Channel enable This bit is set and
|
|
cleared by software.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCIE</name>
|
|
<description>Transfer complete interrupt enable This
|
|
bit is set and cleared by software.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HTIE</name>
|
|
<description>Half transfer interrupt enable This bit
|
|
is set and cleared by software.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TEIE</name>
|
|
<description>Transfer error interrupt enable This bit
|
|
is set and cleared by software.</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DIR</name>
|
|
<description>Data transfer direction This bit is set
|
|
and cleared by software.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CIRC</name>
|
|
<description>Circular mode This bit is set and
|
|
cleared by software.</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PINC</name>
|
|
<description>Peripheral increment mode This bit is
|
|
set and cleared by software.</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MINC</name>
|
|
<description>Memory increment mode This bit is set
|
|
and cleared by software.</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PSIZE</name>
|
|
<description>Peripheral size These bits are set and
|
|
cleared by software.</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSIZE</name>
|
|
<description>Memory size These bits are set and
|
|
cleared by software.</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PL</name>
|
|
<description>Channel priority level These bits are
|
|
set and cleared by software.</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MEM2MEM</name>
|
|
<description>Memory to memory mode This bit is set
|
|
and cleared by software.</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNDTR2</name>
|
|
<displayName>CNDTR2</displayName>
|
|
<description>DMA channel x number of data
|
|
register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>NDT</name>
|
|
<description>Number of data to transfer Number of
|
|
data to be transferred (0 up to 65535). This register
|
|
can only be written when the channel is disabled.
|
|
Once the channel is enabled, this register is
|
|
read-only, indicating the remaining bytes to be
|
|
transmitted. This register decrements after each DMA
|
|
transfer. Once the transfer is completed, this
|
|
register can either stay at zero or be reloaded
|
|
automatically by the value previously programmed if
|
|
the channel is configured in auto-reload mode. If
|
|
this register is zero, no transaction can be served
|
|
whether the channel is enabled or not.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CPAR2</name>
|
|
<displayName>CPAR2</displayName>
|
|
<description>This register must not be written when the
|
|
channel is enabled.</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PA</name>
|
|
<description>Peripheral address Base address of the
|
|
peripheral data register from/to which the data will
|
|
be read/written. When PSIZE is 01 (16-bit), the PA[0]
|
|
bit is ignored. Access is automatically aligned to a
|
|
half-word address. When PSIZE is 10 (32-bit), PA[1:0]
|
|
are ignored. Access is automatically aligned to a
|
|
word address.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMAR2</name>
|
|
<displayName>CMAR2</displayName>
|
|
<description>This register must not be written when the
|
|
channel is enabled.</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MA</name>
|
|
<description>Memory address Base address of the
|
|
memory area from/to which the data will be
|
|
read/written. When MSIZE is 01 (16-bit), the MA[0]
|
|
bit is ignored. Access is automatically aligned to a
|
|
half-word address. When MSIZE is 10 (32-bit), MA[1:0]
|
|
are ignored. Access is automatically aligned to a
|
|
word address.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCR3</name>
|
|
<displayName>CCR3</displayName>
|
|
<description>DMA channel x configuration
|
|
register</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EN</name>
|
|
<description>Channel enable This bit is set and
|
|
cleared by software.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCIE</name>
|
|
<description>Transfer complete interrupt enable This
|
|
bit is set and cleared by software.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HTIE</name>
|
|
<description>Half transfer interrupt enable This bit
|
|
is set and cleared by software.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TEIE</name>
|
|
<description>Transfer error interrupt enable This bit
|
|
is set and cleared by software.</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DIR</name>
|
|
<description>Data transfer direction This bit is set
|
|
and cleared by software.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CIRC</name>
|
|
<description>Circular mode This bit is set and
|
|
cleared by software.</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PINC</name>
|
|
<description>Peripheral increment mode This bit is
|
|
set and cleared by software.</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MINC</name>
|
|
<description>Memory increment mode This bit is set
|
|
and cleared by software.</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PSIZE</name>
|
|
<description>Peripheral size These bits are set and
|
|
cleared by software.</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSIZE</name>
|
|
<description>Memory size These bits are set and
|
|
cleared by software.</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PL</name>
|
|
<description>Channel priority level These bits are
|
|
set and cleared by software.</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MEM2MEM</name>
|
|
<description>Memory to memory mode This bit is set
|
|
and cleared by software.</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNDTR3</name>
|
|
<displayName>CNDTR3</displayName>
|
|
<description>DMA channel x number of data
|
|
register</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>NDT</name>
|
|
<description>Number of data to transfer Number of
|
|
data to be transferred (0 up to 65535). This register
|
|
can only be written when the channel is disabled.
|
|
Once the channel is enabled, this register is
|
|
read-only, indicating the remaining bytes to be
|
|
transmitted. This register decrements after each DMA
|
|
transfer. Once the transfer is completed, this
|
|
register can either stay at zero or be reloaded
|
|
automatically by the value previously programmed if
|
|
the channel is configured in auto-reload mode. If
|
|
this register is zero, no transaction can be served
|
|
whether the channel is enabled or not.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CPAR3</name>
|
|
<displayName>CPAR3</displayName>
|
|
<description>This register must not be written when the
|
|
channel is enabled.</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PA</name>
|
|
<description>Peripheral address Base address of the
|
|
peripheral data register from/to which the data will
|
|
be read/written. When PSIZE is 01 (16-bit), the PA[0]
|
|
bit is ignored. Access is automatically aligned to a
|
|
half-word address. When PSIZE is 10 (32-bit), PA[1:0]
|
|
are ignored. Access is automatically aligned to a
|
|
word address.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMAR3</name>
|
|
<displayName>CMAR3</displayName>
|
|
<description>This register must not be written when the
|
|
channel is enabled.</description>
|
|
<addressOffset>0x3C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MA</name>
|
|
<description>Memory address Base address of the
|
|
memory area from/to which the data will be
|
|
read/written. When MSIZE is 01 (16-bit), the MA[0]
|
|
bit is ignored. Access is automatically aligned to a
|
|
half-word address. When MSIZE is 10 (32-bit), MA[1:0]
|
|
are ignored. Access is automatically aligned to a
|
|
word address.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCR4</name>
|
|
<displayName>CCR4</displayName>
|
|
<description>DMA channel x configuration
|
|
register</description>
|
|
<addressOffset>0x44</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EN</name>
|
|
<description>Channel enable This bit is set and
|
|
cleared by software.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCIE</name>
|
|
<description>Transfer complete interrupt enable This
|
|
bit is set and cleared by software.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HTIE</name>
|
|
<description>Half transfer interrupt enable This bit
|
|
is set and cleared by software.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TEIE</name>
|
|
<description>Transfer error interrupt enable This bit
|
|
is set and cleared by software.</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DIR</name>
|
|
<description>Data transfer direction This bit is set
|
|
and cleared by software.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CIRC</name>
|
|
<description>Circular mode This bit is set and
|
|
cleared by software.</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PINC</name>
|
|
<description>Peripheral increment mode This bit is
|
|
set and cleared by software.</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MINC</name>
|
|
<description>Memory increment mode This bit is set
|
|
and cleared by software.</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PSIZE</name>
|
|
<description>Peripheral size These bits are set and
|
|
cleared by software.</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSIZE</name>
|
|
<description>Memory size These bits are set and
|
|
cleared by software.</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PL</name>
|
|
<description>Channel priority level These bits are
|
|
set and cleared by software.</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MEM2MEM</name>
|
|
<description>Memory to memory mode This bit is set
|
|
and cleared by software.</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNDTR4</name>
|
|
<displayName>CNDTR4</displayName>
|
|
<description>DMA channel x number of data
|
|
register</description>
|
|
<addressOffset>0x48</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>NDT</name>
|
|
<description>Number of data to transfer Number of
|
|
data to be transferred (0 up to 65535). This register
|
|
can only be written when the channel is disabled.
|
|
Once the channel is enabled, this register is
|
|
read-only, indicating the remaining bytes to be
|
|
transmitted. This register decrements after each DMA
|
|
transfer. Once the transfer is completed, this
|
|
register can either stay at zero or be reloaded
|
|
automatically by the value previously programmed if
|
|
the channel is configured in auto-reload mode. If
|
|
this register is zero, no transaction can be served
|
|
whether the channel is enabled or not.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CPAR4</name>
|
|
<displayName>CPAR4</displayName>
|
|
<description>This register must not be written when the
|
|
channel is enabled.</description>
|
|
<addressOffset>0x4C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PA</name>
|
|
<description>Peripheral address Base address of the
|
|
peripheral data register from/to which the data will
|
|
be read/written. When PSIZE is 01 (16-bit), the PA[0]
|
|
bit is ignored. Access is automatically aligned to a
|
|
half-word address. When PSIZE is 10 (32-bit), PA[1:0]
|
|
are ignored. Access is automatically aligned to a
|
|
word address.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMAR4</name>
|
|
<displayName>CMAR4</displayName>
|
|
<description>This register must not be written when the
|
|
channel is enabled.</description>
|
|
<addressOffset>0x50</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MA</name>
|
|
<description>Memory address Base address of the
|
|
memory area from/to which the data will be
|
|
read/written. When MSIZE is 01 (16-bit), the MA[0]
|
|
bit is ignored. Access is automatically aligned to a
|
|
half-word address. When MSIZE is 10 (32-bit), MA[1:0]
|
|
are ignored. Access is automatically aligned to a
|
|
word address.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCR5</name>
|
|
<displayName>CCR5</displayName>
|
|
<description>DMA channel x configuration
|
|
register</description>
|
|
<addressOffset>0x58</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EN</name>
|
|
<description>Channel enable This bit is set and
|
|
cleared by software.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCIE</name>
|
|
<description>Transfer complete interrupt enable This
|
|
bit is set and cleared by software.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HTIE</name>
|
|
<description>Half transfer interrupt enable This bit
|
|
is set and cleared by software.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TEIE</name>
|
|
<description>Transfer error interrupt enable This bit
|
|
is set and cleared by software.</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DIR</name>
|
|
<description>Data transfer direction This bit is set
|
|
and cleared by software.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CIRC</name>
|
|
<description>Circular mode This bit is set and
|
|
cleared by software.</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PINC</name>
|
|
<description>Peripheral increment mode This bit is
|
|
set and cleared by software.</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MINC</name>
|
|
<description>Memory increment mode This bit is set
|
|
and cleared by software.</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PSIZE</name>
|
|
<description>Peripheral size These bits are set and
|
|
cleared by software.</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSIZE</name>
|
|
<description>Memory size These bits are set and
|
|
cleared by software.</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PL</name>
|
|
<description>Channel priority level These bits are
|
|
set and cleared by software.</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MEM2MEM</name>
|
|
<description>Memory to memory mode This bit is set
|
|
and cleared by software.</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNDTR5</name>
|
|
<displayName>CNDTR5</displayName>
|
|
<description>DMA channel x number of data
|
|
register</description>
|
|
<addressOffset>0x5C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>NDT</name>
|
|
<description>Number of data to transfer Number of
|
|
data to be transferred (0 up to 65535). This register
|
|
can only be written when the channel is disabled.
|
|
Once the channel is enabled, this register is
|
|
read-only, indicating the remaining bytes to be
|
|
transmitted. This register decrements after each DMA
|
|
transfer. Once the transfer is completed, this
|
|
register can either stay at zero or be reloaded
|
|
automatically by the value previously programmed if
|
|
the channel is configured in auto-reload mode. If
|
|
this register is zero, no transaction can be served
|
|
whether the channel is enabled or not.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CPAR5</name>
|
|
<displayName>CPAR5</displayName>
|
|
<description>This register must not be written when the
|
|
channel is enabled.</description>
|
|
<addressOffset>0x60</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PA</name>
|
|
<description>Peripheral address Base address of the
|
|
peripheral data register from/to which the data will
|
|
be read/written. When PSIZE is 01 (16-bit), the PA[0]
|
|
bit is ignored. Access is automatically aligned to a
|
|
half-word address. When PSIZE is 10 (32-bit), PA[1:0]
|
|
are ignored. Access is automatically aligned to a
|
|
word address.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMAR5</name>
|
|
<displayName>CMAR5</displayName>
|
|
<description>This register must not be written when the
|
|
channel is enabled.</description>
|
|
<addressOffset>0x64</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MA</name>
|
|
<description>Memory address Base address of the
|
|
memory area from/to which the data will be
|
|
read/written. When MSIZE is 01 (16-bit), the MA[0]
|
|
bit is ignored. Access is automatically aligned to a
|
|
half-word address. When MSIZE is 10 (32-bit), MA[1:0]
|
|
are ignored. Access is automatically aligned to a
|
|
word address.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCR6</name>
|
|
<displayName>CCR6</displayName>
|
|
<description>DMA channel x configuration
|
|
register</description>
|
|
<addressOffset>0x6C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EN</name>
|
|
<description>Channel enable This bit is set and
|
|
cleared by software.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCIE</name>
|
|
<description>Transfer complete interrupt enable This
|
|
bit is set and cleared by software.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HTIE</name>
|
|
<description>Half transfer interrupt enable This bit
|
|
is set and cleared by software.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TEIE</name>
|
|
<description>Transfer error interrupt enable This bit
|
|
is set and cleared by software.</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DIR</name>
|
|
<description>Data transfer direction This bit is set
|
|
and cleared by software.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CIRC</name>
|
|
<description>Circular mode This bit is set and
|
|
cleared by software.</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PINC</name>
|
|
<description>Peripheral increment mode This bit is
|
|
set and cleared by software.</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MINC</name>
|
|
<description>Memory increment mode This bit is set
|
|
and cleared by software.</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PSIZE</name>
|
|
<description>Peripheral size These bits are set and
|
|
cleared by software.</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSIZE</name>
|
|
<description>Memory size These bits are set and
|
|
cleared by software.</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PL</name>
|
|
<description>Channel priority level These bits are
|
|
set and cleared by software.</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MEM2MEM</name>
|
|
<description>Memory to memory mode This bit is set
|
|
and cleared by software.</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNDTR6</name>
|
|
<displayName>CNDTR6</displayName>
|
|
<description>DMA channel x number of data
|
|
register</description>
|
|
<addressOffset>0x70</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>NDT</name>
|
|
<description>Number of data to transfer Number of
|
|
data to be transferred (0 up to 65535). This register
|
|
can only be written when the channel is disabled.
|
|
Once the channel is enabled, this register is
|
|
read-only, indicating the remaining bytes to be
|
|
transmitted. This register decrements after each DMA
|
|
transfer. Once the transfer is completed, this
|
|
register can either stay at zero or be reloaded
|
|
automatically by the value previously programmed if
|
|
the channel is configured in auto-reload mode. If
|
|
this register is zero, no transaction can be served
|
|
whether the channel is enabled or not.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CPAR6</name>
|
|
<displayName>CPAR6</displayName>
|
|
<description>This register must not be written when the
|
|
channel is enabled.</description>
|
|
<addressOffset>0x74</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PA</name>
|
|
<description>Peripheral address Base address of the
|
|
peripheral data register from/to which the data will
|
|
be read/written. When PSIZE is 01 (16-bit), the PA[0]
|
|
bit is ignored. Access is automatically aligned to a
|
|
half-word address. When PSIZE is 10 (32-bit), PA[1:0]
|
|
are ignored. Access is automatically aligned to a
|
|
word address.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMAR6</name>
|
|
<displayName>CMAR6</displayName>
|
|
<description>This register must not be written when the
|
|
channel is enabled.</description>
|
|
<addressOffset>0x78</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MA</name>
|
|
<description>Memory address Base address of the
|
|
memory area from/to which the data will be
|
|
read/written. When MSIZE is 01 (16-bit), the MA[0]
|
|
bit is ignored. Access is automatically aligned to a
|
|
half-word address. When MSIZE is 10 (32-bit), MA[1:0]
|
|
are ignored. Access is automatically aligned to a
|
|
word address.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCR7</name>
|
|
<displayName>CCR7</displayName>
|
|
<description>DMA channel x configuration
|
|
register</description>
|
|
<addressOffset>0x80</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EN</name>
|
|
<description>Channel enable This bit is set and
|
|
cleared by software.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCIE</name>
|
|
<description>Transfer complete interrupt enable This
|
|
bit is set and cleared by software.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HTIE</name>
|
|
<description>Half transfer interrupt enable This bit
|
|
is set and cleared by software.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TEIE</name>
|
|
<description>Transfer error interrupt enable This bit
|
|
is set and cleared by software.</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DIR</name>
|
|
<description>Data transfer direction This bit is set
|
|
and cleared by software.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CIRC</name>
|
|
<description>Circular mode This bit is set and
|
|
cleared by software.</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PINC</name>
|
|
<description>Peripheral increment mode This bit is
|
|
set and cleared by software.</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MINC</name>
|
|
<description>Memory increment mode This bit is set
|
|
and cleared by software.</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PSIZE</name>
|
|
<description>Peripheral size These bits are set and
|
|
cleared by software.</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSIZE</name>
|
|
<description>Memory size These bits are set and
|
|
cleared by software.</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PL</name>
|
|
<description>Channel priority level These bits are
|
|
set and cleared by software.</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MEM2MEM</name>
|
|
<description>Memory to memory mode This bit is set
|
|
and cleared by software.</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNDTR7</name>
|
|
<displayName>CNDTR7</displayName>
|
|
<description>DMA channel x number of data
|
|
register</description>
|
|
<addressOffset>0x84</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>NDT</name>
|
|
<description>Number of data to transfer Number of
|
|
data to be transferred (0 up to 65535). This register
|
|
can only be written when the channel is disabled.
|
|
Once the channel is enabled, this register is
|
|
read-only, indicating the remaining bytes to be
|
|
transmitted. This register decrements after each DMA
|
|
transfer. Once the transfer is completed, this
|
|
register can either stay at zero or be reloaded
|
|
automatically by the value previously programmed if
|
|
the channel is configured in auto-reload mode. If
|
|
this register is zero, no transaction can be served
|
|
whether the channel is enabled or not.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CPAR7</name>
|
|
<displayName>CPAR7</displayName>
|
|
<description>This register must not be written when the
|
|
channel is enabled.</description>
|
|
<addressOffset>0x88</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PA</name>
|
|
<description>Peripheral address Base address of the
|
|
peripheral data register from/to which the data will
|
|
be read/written. When PSIZE is 01 (16-bit), the PA[0]
|
|
bit is ignored. Access is automatically aligned to a
|
|
half-word address. When PSIZE is 10 (32-bit), PA[1:0]
|
|
are ignored. Access is automatically aligned to a
|
|
word address.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMAR7</name>
|
|
<displayName>CMAR7</displayName>
|
|
<description>This register must not be written when the
|
|
channel is enabled.</description>
|
|
<addressOffset>0x8C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MA</name>
|
|
<description>Memory address Base address of the
|
|
memory area from/to which the data will be
|
|
read/written. When MSIZE is 01 (16-bit), the MA[0]
|
|
bit is ignored. Access is automatically aligned to a
|
|
half-word address. When MSIZE is 10 (32-bit), MA[1:0]
|
|
are ignored. Access is automatically aligned to a
|
|
word address.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCR8</name>
|
|
<displayName>CCR8</displayName>
|
|
<description>DMA channel x configuration
|
|
register</description>
|
|
<addressOffset>0x94</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EN</name>
|
|
<description>Channel enable This bit is set and
|
|
cleared by software.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCIE</name>
|
|
<description>Transfer complete interrupt enable This
|
|
bit is set and cleared by software.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HTIE</name>
|
|
<description>Half transfer interrupt enable This bit
|
|
is set and cleared by software.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TEIE</name>
|
|
<description>Transfer error interrupt enable This bit
|
|
is set and cleared by software.</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DIR</name>
|
|
<description>Data transfer direction This bit is set
|
|
and cleared by software.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CIRC</name>
|
|
<description>Circular mode This bit is set and
|
|
cleared by software.</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PINC</name>
|
|
<description>Peripheral increment mode This bit is
|
|
set and cleared by software.</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MINC</name>
|
|
<description>Memory increment mode This bit is set
|
|
and cleared by software.</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PSIZE</name>
|
|
<description>Peripheral size These bits are set and
|
|
cleared by software.</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSIZE</name>
|
|
<description>Memory size These bits are set and
|
|
cleared by software.</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PL</name>
|
|
<description>Channel priority level These bits are
|
|
set and cleared by software.</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MEM2MEM</name>
|
|
<description>Memory to memory mode This bit is set
|
|
and cleared by software.</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNDTR8</name>
|
|
<displayName>CNDTR8</displayName>
|
|
<description>DMA channel x number of data
|
|
register</description>
|
|
<addressOffset>0x98</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>NDT</name>
|
|
<description>Number of data to transfer Number of
|
|
data to be transferred (0 up to 65535). This register
|
|
can only be written when the channel is disabled.
|
|
Once the channel is enabled, this register is
|
|
read-only, indicating the remaining bytes to be
|
|
transmitted. This register decrements after each DMA
|
|
transfer. Once the transfer is completed, this
|
|
register can either stay at zero or be reloaded
|
|
automatically by the value previously programmed if
|
|
the channel is configured in auto-reload mode. If
|
|
this register is zero, no transaction can be served
|
|
whether the channel is enabled or not.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CPAR8</name>
|
|
<displayName>CPAR8</displayName>
|
|
<description>This register must not be written when the
|
|
channel is enabled.</description>
|
|
<addressOffset>0x9C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PA</name>
|
|
<description>Peripheral address Base address of the
|
|
peripheral data register from/to which the data will
|
|
be read/written. When PSIZE is 01 (16-bit), the PA[0]
|
|
bit is ignored. Access is automatically aligned to a
|
|
half-word address. When PSIZE is 10 (32-bit), PA[1:0]
|
|
are ignored. Access is automatically aligned to a
|
|
word address.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMAR8</name>
|
|
<displayName>CMAR8</displayName>
|
|
<description>This register must not be written when the
|
|
channel is enabled.</description>
|
|
<addressOffset>0xA0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MA</name>
|
|
<description>Memory address Base address of the
|
|
memory area from/to which the data will be
|
|
read/written. When MSIZE is 01 (16-bit), the MA[0]
|
|
bit is ignored. Access is automatically aligned to a
|
|
half-word address. When MSIZE is 10 (32-bit), MA[1:0]
|
|
are ignored. Access is automatically aligned to a
|
|
word address.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>DMA2D</name>
|
|
<description>DMA2D</description>
|
|
<groupName>DMA2D</groupName>
|
|
<baseAddress>0x52001000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>DMA2D</name>
|
|
<description>DMA2D global interrupt</description>
|
|
<value>90</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CR</name>
|
|
<displayName>CR</displayName>
|
|
<description>DMA2D control register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>START</name>
|
|
<description>Start This bit can be used to launch the
|
|
DMA2D according to the parameters loaded in the
|
|
various configuration registers</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SUSP</name>
|
|
<description>Suspend This bit can be used to suspend
|
|
the current transfer. This bit is set and reset by
|
|
software. It is automatically reset by hardware when
|
|
the START bit is reset.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ABORT</name>
|
|
<description>Abort This bit can be used to abort the
|
|
current transfer. This bit is set by software and is
|
|
automatically reset by hardware when the START bit is
|
|
reset.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TEIE</name>
|
|
<description>Transfer error interrupt enable This bit
|
|
is set and cleared by software.</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCIE</name>
|
|
<description>Transfer complete interrupt enable This
|
|
bit is set and cleared by software.</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TWIE</name>
|
|
<description>Transfer watermark interrupt enable This
|
|
bit is set and cleared by software.</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CAEIE</name>
|
|
<description>CLUT access error interrupt enable This
|
|
bit is set and cleared by software.</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTCIE</name>
|
|
<description>CLUT transfer complete interrupt enable
|
|
This bit is set and cleared by
|
|
software.</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CEIE</name>
|
|
<description>Configuration Error Interrupt Enable
|
|
This bit is set and cleared by
|
|
software.</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>DMA2D mode This bit is set and cleared
|
|
by software. It cannot be modified while a transfer
|
|
is ongoing.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ISR</name>
|
|
<displayName>ISR</displayName>
|
|
<description>DMA2D Interrupt Status
|
|
Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TEIF</name>
|
|
<description>Transfer error interrupt flag This bit
|
|
is set when an error occurs during a DMA transfer
|
|
(data transfer or automatic CLUT
|
|
loading).</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCIF</name>
|
|
<description>Transfer complete interrupt flag This
|
|
bit is set when a DMA2D transfer operation is
|
|
complete (data transfer only).</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TWIF</name>
|
|
<description>Transfer watermark interrupt flag This
|
|
bit is set when the last pixel of the watermarked
|
|
line has been transferred.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CAEIF</name>
|
|
<description>CLUT access error interrupt flag This
|
|
bit is set when the CPU accesses the CLUT while the
|
|
CLUT is being automatically copied from a system
|
|
memory to the internal DMA2D.</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTCIF</name>
|
|
<description>CLUT transfer complete interrupt flag
|
|
This bit is set when the CLUT copy from a system
|
|
memory area to the internal DMA2D memory is
|
|
complete.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CEIF</name>
|
|
<description>Configuration error interrupt flag This
|
|
bit is set when the START bit of DMA2D_CR,
|
|
DMA2DFGPFCCR or DMA2D_BGPFCCR is set and a wrong
|
|
configuration has been programmed.</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IFCR</name>
|
|
<displayName>IFCR</displayName>
|
|
<description>DMA2D interrupt flag clear
|
|
register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CTEIF</name>
|
|
<description>Clear Transfer error interrupt flag
|
|
Programming this bit to 1 clears the TEIF flag in the
|
|
DMA2D_ISR register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTCIF</name>
|
|
<description>Clear transfer complete interrupt flag
|
|
Programming this bit to 1 clears the TCIF flag in the
|
|
DMA2D_ISR register</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTWIF</name>
|
|
<description>Clear transfer watermark interrupt flag
|
|
Programming this bit to 1 clears the TWIF flag in the
|
|
DMA2D_ISR register</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CAECIF</name>
|
|
<description>Clear CLUT access error interrupt flag
|
|
Programming this bit to 1 clears the CAEIF flag in
|
|
the DMA2D_ISR register</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CCTCIF</name>
|
|
<description>Clear CLUT transfer complete interrupt
|
|
flag Programming this bit to 1 clears the CTCIF flag
|
|
in the DMA2D_ISR register</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CCEIF</name>
|
|
<description>Clear configuration error interrupt flag
|
|
Programming this bit to 1 clears the CEIF flag in the
|
|
DMA2D_ISR register</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FGMAR</name>
|
|
<displayName>FGMAR</displayName>
|
|
<description>DMA2D foreground memory address
|
|
register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MA</name>
|
|
<description>Memory address Address of the data used
|
|
for the foreground image. This register can only be
|
|
written when data transfers are disabled. Once the
|
|
data transfer has started, this register is
|
|
read-only. The address alignment must match the image
|
|
format selected e.g. a 32-bit per pixel format must
|
|
be 32-bit aligned, a 16-bit per pixel format must be
|
|
16-bit aligned and a 4-bit per pixel format must be
|
|
8-bit aligned.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FGOR</name>
|
|
<displayName>FGOR</displayName>
|
|
<description>DMA2D foreground offset
|
|
register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LO</name>
|
|
<description>Line offset Line offset used for the
|
|
foreground expressed in pixel. This value is used to
|
|
generate the address. It is added at the end of each
|
|
line to determine the starting address of the next
|
|
line. These bits can only be written when data
|
|
transfers are disabled. Once a data transfer has
|
|
started, they become read-only. If the image format
|
|
is 4-bit per pixel, the line offset must be
|
|
even.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>14</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BGMAR</name>
|
|
<displayName>BGMAR</displayName>
|
|
<description>DMA2D background memory address
|
|
register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MA</name>
|
|
<description>Memory address Address of the data used
|
|
for the background image. This register can only be
|
|
written when data transfers are disabled. Once a data
|
|
transfer has started, this register is read-only. The
|
|
address alignment must match the image format
|
|
selected e.g. a 32-bit per pixel format must be
|
|
32-bit aligned, a 16-bit per pixel format must be
|
|
16-bit aligned and a 4-bit per pixel format must be
|
|
8-bit aligned.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BGOR</name>
|
|
<displayName>BGOR</displayName>
|
|
<description>DMA2D background offset
|
|
register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LO</name>
|
|
<description>Line offset Line offset used for the
|
|
background image (expressed in pixel). This value is
|
|
used for the address generation. It is added at the
|
|
end of each line to determine the starting address of
|
|
the next line. These bits can only be written when
|
|
data transfers are disabled. Once data transfer has
|
|
started, they become read-only. If the image format
|
|
is 4-bit per pixel, the line offset must be
|
|
even.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>14</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FGPFCCR</name>
|
|
<displayName>FGPFCCR</displayName>
|
|
<description>DMA2D foreground PFC control
|
|
register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CM</name>
|
|
<description>Color mode These bits defines the color
|
|
format of the foreground image. They can only be
|
|
written when data transfers are disabled. Once the
|
|
transfer has started, they are read-only. others:
|
|
meaningless</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CCM</name>
|
|
<description>CLUT color mode This bit defines the
|
|
color format of the CLUT. It can only be written when
|
|
the transfer is disabled. Once the CLUT transfer has
|
|
started, this bit is read-only.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>START</name>
|
|
<description>Start This bit can be set to start the
|
|
automatic loading of the CLUT. It is automatically
|
|
reset: ** at the end of the transfer ** when the
|
|
transfer is aborted by the user application by
|
|
setting the ABORT bit in DMA2D_CR ** when a transfer
|
|
error occurs ** when the transfer has not started due
|
|
to a configuration error or another transfer
|
|
operation already ongoing (data transfer or automatic
|
|
background CLUT transfer).</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CS</name>
|
|
<description>CLUT size These bits define the size of
|
|
the CLUT used for the foreground image. Once the CLUT
|
|
transfer has started, this field is read-only. The
|
|
number of CLUT entries is equal to CS[7:0] +
|
|
1.</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AM</name>
|
|
<description>Alpha mode These bits select the alpha
|
|
channel value to be used for the foreground image.
|
|
They can only be written data the transfer are
|
|
disabled. Once the transfer has started, they become
|
|
read-only. other configurations are
|
|
meaningless</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CSS</name>
|
|
<description>Chroma Sub-Sampling These bits define
|
|
the chroma sub-sampling mode for YCbCr color mode.
|
|
Once the transfer has started, these bits are
|
|
read-only. others: meaningless</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AI</name>
|
|
<description>Alpha Inverted This bit inverts the
|
|
alpha value. Once the transfer has started, this bit
|
|
is read-only.</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RBS</name>
|
|
<description>Red Blue Swap This bit allows to swap
|
|
the R &amp; B to support BGR or ABGR color
|
|
formats. Once the transfer has started, this bit is
|
|
read-only.</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ALPHA</name>
|
|
<description>Alpha value These bits define a fixed
|
|
alpha channel value which can replace the original
|
|
alpha value or be multiplied by the original alpha
|
|
value according to the alpha mode selected through
|
|
the AM[1:0] bits. These bits can only be written when
|
|
data transfers are disabled. Once a transfer has
|
|
started, they become read-only.</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FGCOLR</name>
|
|
<displayName>FGCOLR</displayName>
|
|
<description>DMA2D foreground color
|
|
register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BLUE</name>
|
|
<description>Blue Value These bits defines the blue
|
|
value for the A4 or A8 mode of the foreground image.
|
|
They can only be written when data transfers are
|
|
disabled. Once the transfer has started, They are
|
|
read-only.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GREEN</name>
|
|
<description>Green Value These bits defines the green
|
|
value for the A4 or A8 mode of the foreground image.
|
|
They can only be written when data transfers are
|
|
disabled. Once the transfer has started, They are
|
|
read-only.</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RED</name>
|
|
<description>Red Value These bits defines the red
|
|
value for the A4 or A8 mode of the foreground image.
|
|
They can only be written when data transfers are
|
|
disabled. Once the transfer has started, they are
|
|
read-only.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BGPFCCR</name>
|
|
<displayName>BGPFCCR</displayName>
|
|
<description>DMA2D background PFC control
|
|
register</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CM</name>
|
|
<description>Color mode These bits define the color
|
|
format of the foreground image. These bits can only
|
|
be written when data transfers are disabled. Once the
|
|
transfer has started, they are read-only. others:
|
|
meaningless</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CCM</name>
|
|
<description>CLUT Color mode These bits define the
|
|
color format of the CLUT. This register can only be
|
|
written when the transfer is disabled. Once the CLUT
|
|
transfer has started, this bit is
|
|
read-only.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>START</name>
|
|
<description>Start This bit is set to start the
|
|
automatic loading of the CLUT. This bit is
|
|
automatically reset: ** at the end of the transfer **
|
|
when the transfer is aborted by the user application
|
|
by setting the ABORT bit in the DMA2D_CR ** when a
|
|
transfer error occurs ** when the transfer has not
|
|
started due to a configuration error or another
|
|
transfer operation already on going (data transfer or
|
|
automatic BackGround CLUT transfer).</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CS</name>
|
|
<description>CLUT size These bits define the size of
|
|
the CLUT used for the BG. Once the CLUT transfer has
|
|
started, this field is read-only. The number of CLUT
|
|
entries is equal to CS[7:0] + 1.</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AM</name>
|
|
<description>Alpha mode These bits define which alpha
|
|
channel value to be used for the background image.
|
|
These bits can only be written when data transfers
|
|
are disabled. Once the transfer has started, they are
|
|
read-only. others: meaningless</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AI</name>
|
|
<description>Alpha Inverted This bit inverts the
|
|
alpha value. Once the transfer has started, this bit
|
|
is read-only.</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RBS</name>
|
|
<description>Red Blue Swap This bit allows to swap
|
|
the R &amp; B to support BGR or ABGR color
|
|
formats. Once the transfer has started, this bit is
|
|
read-only.</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ALPHA</name>
|
|
<description>Alpha value These bits define a fixed
|
|
alpha channel value which can replace the original
|
|
alpha value or be multiplied with the original alpha
|
|
value according to the alpha mode selected with bits
|
|
AM[1: 0]. These bits can only be written when data
|
|
transfers are disabled. Once the transfer has
|
|
started, they are read-only.</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BGCOLR</name>
|
|
<displayName>BGCOLR</displayName>
|
|
<description>DMA2D background color
|
|
register</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BLUE</name>
|
|
<description>Blue Value These bits define the blue
|
|
value for the A4 or A8 mode of the background. These
|
|
bits can only be written when data transfers are
|
|
disabled. Once the transfer has started, they are
|
|
read-only.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GREEN</name>
|
|
<description>Green Value These bits define the green
|
|
value for the A4 or A8 mode of the background. These
|
|
bits can only be written when data transfers are
|
|
disabled. Once the transfer has started, they are
|
|
read-only.</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RED</name>
|
|
<description>Red Value These bits define the red
|
|
value for the A4 or A8 mode of the background. These
|
|
bits can only be written when data transfers are
|
|
disabled. Once the transfer has started, they are
|
|
read-only.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FGCMAR</name>
|
|
<displayName>FGCMAR</displayName>
|
|
<description>DMA2D foreground CLUT memory address
|
|
register</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MA</name>
|
|
<description>Memory Address Address of the data used
|
|
for the CLUT address dedicated to the foreground
|
|
image. This register can only be written when no
|
|
transfer is ongoing. Once the CLUT transfer has
|
|
started, this register is read-only. If the
|
|
foreground CLUT format is 32-bit, the address must be
|
|
32-bit aligned.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BGCMAR</name>
|
|
<displayName>BGCMAR</displayName>
|
|
<description>DMA2D background CLUT memory address
|
|
register</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MA</name>
|
|
<description>Memory address Address of the data used
|
|
for the CLUT address dedicated to the background
|
|
image. This register can only be written when no
|
|
transfer is on going. Once the CLUT transfer has
|
|
started, this register is read-only. If the
|
|
background CLUT format is 32-bit, the address must be
|
|
32-bit aligned.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OPFCCR</name>
|
|
<displayName>OPFCCR</displayName>
|
|
<description>DMA2D output PFC control
|
|
register</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CM</name>
|
|
<description>Color mode These bits define the color
|
|
format of the output image. These bits can only be
|
|
written when data transfers are disabled. Once the
|
|
transfer has started, they are read-only. others:
|
|
meaningless</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AI</name>
|
|
<description>Alpha Inverted This bit inverts the
|
|
alpha value. Once the transfer has started, this bit
|
|
is read-only.</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RBS</name>
|
|
<description>Red Blue Swap This bit allows to swap
|
|
the R &amp; B to support BGR or ABGR color
|
|
formats. Once the transfer has started, this bit is
|
|
read-only.</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OCOLR</name>
|
|
<displayName>OCOLR</displayName>
|
|
<description>DMA2D output color register</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BLUE</name>
|
|
<description>Blue Value These bits define the blue
|
|
value of the output image. These bits can only be
|
|
written when data transfers are disabled. Once the
|
|
transfer has started, they are
|
|
read-only.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GREEN</name>
|
|
<description>Green Value These bits define the green
|
|
value of the output image. These bits can only be
|
|
written when data transfers are disabled. Once the
|
|
transfer has started, they are
|
|
read-only.</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RED</name>
|
|
<description>Red Value These bits define the red
|
|
value of the output image. These bits can only be
|
|
written when data transfers are disabled. Once the
|
|
transfer has started, they are
|
|
read-only.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ALPHA</name>
|
|
<description>Alpha Channel Value These bits define
|
|
the alpha channel of the output color. These bits can
|
|
only be written when data transfers are disabled.
|
|
Once the transfer has started, they are
|
|
read-only.</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OMAR</name>
|
|
<displayName>OMAR</displayName>
|
|
<description>DMA2D output memory address
|
|
register</description>
|
|
<addressOffset>0x3C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MA</name>
|
|
<description>Memory Address Address of the data used
|
|
for the output FIFO. These bits can only be written
|
|
when data transfers are disabled. Once the transfer
|
|
has started, they are read-only. The address
|
|
alignment must match the image format selected e.g. a
|
|
32-bit per pixel format must be 32-bit aligned and a
|
|
16-bit per pixel format must be 16-bit
|
|
aligned.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OOR</name>
|
|
<displayName>OOR</displayName>
|
|
<description>DMA2D output offset register</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LO</name>
|
|
<description>Line Offset Line offset used for the
|
|
output (expressed in pixels). This value is used for
|
|
the address generation. It is added at the end of
|
|
each line to determine the starting address of the
|
|
next line. These bits can only be written when data
|
|
transfers are disabled. Once the transfer has
|
|
started, they are read-only.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>14</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NLR</name>
|
|
<displayName>NLR</displayName>
|
|
<description>DMA2D number of line register</description>
|
|
<addressOffset>0x44</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>NL</name>
|
|
<description>Number of lines Number of lines of the
|
|
area to be transferred. These bits can only be
|
|
written when data transfers are disabled. Once the
|
|
transfer has started, they are
|
|
read-only.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PL</name>
|
|
<description>Pixel per lines Number of pixels per
|
|
lines of the area to be transferred. These bits can
|
|
only be written when data transfers are disabled.
|
|
Once the transfer has started, they are read-only. If
|
|
any of the input image format is 4-bit per pixel,
|
|
pixel per lines must be even.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>14</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LWR</name>
|
|
<displayName>LWR</displayName>
|
|
<description>DMA2D line watermark register</description>
|
|
<addressOffset>0x48</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LW</name>
|
|
<description>Line watermark These bits allow to
|
|
configure the line watermark for interrupt
|
|
generation. An interrupt is raised when the last
|
|
pixel of the watermarked line has been transferred.
|
|
These bits can only be written when data transfers
|
|
are disabled. Once the transfer has started, they are
|
|
read-only.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AMTCR</name>
|
|
<displayName>AMTCR</displayName>
|
|
<description>DMA2D AXI master timer configuration
|
|
register</description>
|
|
<addressOffset>0x4C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EN</name>
|
|
<description>Enable Enables the dead time
|
|
functionality.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DT</name>
|
|
<description>Dead Time Dead time value in the AXI
|
|
clock cycle inserted between two consecutive accesses
|
|
on the AXI master port. These bits represent the
|
|
minimum guaranteed number of cycles between two
|
|
consecutive AXI accesses.</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>DMAMUX2</name>
|
|
<description>DMAMUX</description>
|
|
<groupName>DMAMUX</groupName>
|
|
<baseAddress>0x58025800</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>DMAMUX2_OVR</name>
|
|
<description>DMAMUX2 overrun interrupt</description>
|
|
<value>128</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>C0CR</name>
|
|
<displayName>C0CR</displayName>
|
|
<description>DMAMux - DMA request line multiplexer
|
|
channel x control register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DMAREQ_ID</name>
|
|
<description>Input DMA request line
|
|
selected</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SOIE</name>
|
|
<description>Interrupt enable at synchronization
|
|
event overrun</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EGE</name>
|
|
<description>Event generation
|
|
enable/disable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SE</name>
|
|
<description>Synchronous operating mode
|
|
enable/disable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SPOL</name>
|
|
<description>Synchronization event type selector
|
|
Defines the synchronization event on the selected
|
|
synchronization input:</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NBREQ</name>
|
|
<description>Number of DMA requests to forward
|
|
Defines the number of DMA requests forwarded before
|
|
output event is generated. In synchronous mode, it
|
|
also defines the number of DMA requests to forward
|
|
after a synchronization event, then stop forwarding.
|
|
The actual number of DMA requests forwarded is
|
|
NBREQ+1. Note: This field can only be written when
|
|
both SE and EGE bits are reset.</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SYNC_ID</name>
|
|
<description>Synchronization input
|
|
selected</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>C1CR</name>
|
|
<displayName>C1CR</displayName>
|
|
<description>DMAMux - DMA request line multiplexer
|
|
channel x control register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DMAREQ_ID</name>
|
|
<description>Input DMA request line
|
|
selected</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SOIE</name>
|
|
<description>Interrupt enable at synchronization
|
|
event overrun</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EGE</name>
|
|
<description>Event generation
|
|
enable/disable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SE</name>
|
|
<description>Synchronous operating mode
|
|
enable/disable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SPOL</name>
|
|
<description>Synchronization event type selector
|
|
Defines the synchronization event on the selected
|
|
synchronization input:</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NBREQ</name>
|
|
<description>Number of DMA requests to forward
|
|
Defines the number of DMA requests forwarded before
|
|
output event is generated. In synchronous mode, it
|
|
also defines the number of DMA requests to forward
|
|
after a synchronization event, then stop forwarding.
|
|
The actual number of DMA requests forwarded is
|
|
NBREQ+1. Note: This field can only be written when
|
|
both SE and EGE bits are reset.</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SYNC_ID</name>
|
|
<description>Synchronization input
|
|
selected</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>C2CR</name>
|
|
<displayName>C2CR</displayName>
|
|
<description>DMAMux - DMA request line multiplexer
|
|
channel x control register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DMAREQ_ID</name>
|
|
<description>Input DMA request line
|
|
selected</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SOIE</name>
|
|
<description>Interrupt enable at synchronization
|
|
event overrun</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EGE</name>
|
|
<description>Event generation
|
|
enable/disable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SE</name>
|
|
<description>Synchronous operating mode
|
|
enable/disable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SPOL</name>
|
|
<description>Synchronization event type selector
|
|
Defines the synchronization event on the selected
|
|
synchronization input:</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NBREQ</name>
|
|
<description>Number of DMA requests to forward
|
|
Defines the number of DMA requests forwarded before
|
|
output event is generated. In synchronous mode, it
|
|
also defines the number of DMA requests to forward
|
|
after a synchronization event, then stop forwarding.
|
|
The actual number of DMA requests forwarded is
|
|
NBREQ+1. Note: This field can only be written when
|
|
both SE and EGE bits are reset.</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SYNC_ID</name>
|
|
<description>Synchronization input
|
|
selected</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>C3CR</name>
|
|
<displayName>C3CR</displayName>
|
|
<description>DMAMux - DMA request line multiplexer
|
|
channel x control register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DMAREQ_ID</name>
|
|
<description>Input DMA request line
|
|
selected</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SOIE</name>
|
|
<description>Interrupt enable at synchronization
|
|
event overrun</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EGE</name>
|
|
<description>Event generation
|
|
enable/disable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SE</name>
|
|
<description>Synchronous operating mode
|
|
enable/disable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SPOL</name>
|
|
<description>Synchronization event type selector
|
|
Defines the synchronization event on the selected
|
|
synchronization input:</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NBREQ</name>
|
|
<description>Number of DMA requests to forward
|
|
Defines the number of DMA requests forwarded before
|
|
output event is generated. In synchronous mode, it
|
|
also defines the number of DMA requests to forward
|
|
after a synchronization event, then stop forwarding.
|
|
The actual number of DMA requests forwarded is
|
|
NBREQ+1. Note: This field can only be written when
|
|
both SE and EGE bits are reset.</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SYNC_ID</name>
|
|
<description>Synchronization input
|
|
selected</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>C4CR</name>
|
|
<displayName>C4CR</displayName>
|
|
<description>DMAMux - DMA request line multiplexer
|
|
channel x control register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DMAREQ_ID</name>
|
|
<description>Input DMA request line
|
|
selected</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SOIE</name>
|
|
<description>Interrupt enable at synchronization
|
|
event overrun</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EGE</name>
|
|
<description>Event generation
|
|
enable/disable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SE</name>
|
|
<description>Synchronous operating mode
|
|
enable/disable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SPOL</name>
|
|
<description>Synchronization event type selector
|
|
Defines the synchronization event on the selected
|
|
synchronization input:</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NBREQ</name>
|
|
<description>Number of DMA requests to forward
|
|
Defines the number of DMA requests forwarded before
|
|
output event is generated. In synchronous mode, it
|
|
also defines the number of DMA requests to forward
|
|
after a synchronization event, then stop forwarding.
|
|
The actual number of DMA requests forwarded is
|
|
NBREQ+1. Note: This field can only be written when
|
|
both SE and EGE bits are reset.</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SYNC_ID</name>
|
|
<description>Synchronization input
|
|
selected</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>C5CR</name>
|
|
<displayName>C5CR</displayName>
|
|
<description>DMAMux - DMA request line multiplexer
|
|
channel x control register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DMAREQ_ID</name>
|
|
<description>Input DMA request line
|
|
selected</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SOIE</name>
|
|
<description>Interrupt enable at synchronization
|
|
event overrun</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EGE</name>
|
|
<description>Event generation
|
|
enable/disable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SE</name>
|
|
<description>Synchronous operating mode
|
|
enable/disable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SPOL</name>
|
|
<description>Synchronization event type selector
|
|
Defines the synchronization event on the selected
|
|
synchronization input:</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NBREQ</name>
|
|
<description>Number of DMA requests to forward
|
|
Defines the number of DMA requests forwarded before
|
|
output event is generated. In synchronous mode, it
|
|
also defines the number of DMA requests to forward
|
|
after a synchronization event, then stop forwarding.
|
|
The actual number of DMA requests forwarded is
|
|
NBREQ+1. Note: This field can only be written when
|
|
both SE and EGE bits are reset.</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SYNC_ID</name>
|
|
<description>Synchronization input
|
|
selected</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>C6CR</name>
|
|
<displayName>C6CR</displayName>
|
|
<description>DMAMux - DMA request line multiplexer
|
|
channel x control register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DMAREQ_ID</name>
|
|
<description>Input DMA request line
|
|
selected</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SOIE</name>
|
|
<description>Interrupt enable at synchronization
|
|
event overrun</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EGE</name>
|
|
<description>Event generation
|
|
enable/disable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SE</name>
|
|
<description>Synchronous operating mode
|
|
enable/disable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SPOL</name>
|
|
<description>Synchronization event type selector
|
|
Defines the synchronization event on the selected
|
|
synchronization input:</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NBREQ</name>
|
|
<description>Number of DMA requests to forward
|
|
Defines the number of DMA requests forwarded before
|
|
output event is generated. In synchronous mode, it
|
|
also defines the number of DMA requests to forward
|
|
after a synchronization event, then stop forwarding.
|
|
The actual number of DMA requests forwarded is
|
|
NBREQ+1. Note: This field can only be written when
|
|
both SE and EGE bits are reset.</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SYNC_ID</name>
|
|
<description>Synchronization input
|
|
selected</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>C7CR</name>
|
|
<displayName>C7CR</displayName>
|
|
<description>DMAMux - DMA request line multiplexer
|
|
channel x control register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DMAREQ_ID</name>
|
|
<description>Input DMA request line
|
|
selected</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SOIE</name>
|
|
<description>Interrupt enable at synchronization
|
|
event overrun</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EGE</name>
|
|
<description>Event generation
|
|
enable/disable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SE</name>
|
|
<description>Synchronous operating mode
|
|
enable/disable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SPOL</name>
|
|
<description>Synchronization event type selector
|
|
Defines the synchronization event on the selected
|
|
synchronization input:</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NBREQ</name>
|
|
<description>Number of DMA requests to forward
|
|
Defines the number of DMA requests forwarded before
|
|
output event is generated. In synchronous mode, it
|
|
also defines the number of DMA requests to forward
|
|
after a synchronization event, then stop forwarding.
|
|
The actual number of DMA requests forwarded is
|
|
NBREQ+1. Note: This field can only be written when
|
|
both SE and EGE bits are reset.</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SYNC_ID</name>
|
|
<description>Synchronization input
|
|
selected</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RG0CR</name>
|
|
<displayName>RG0CR</displayName>
|
|
<description>DMAMux - DMA request generator channel x
|
|
control register</description>
|
|
<addressOffset>0x100</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SIG_ID</name>
|
|
<description>DMA request trigger input
|
|
selected</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OIE</name>
|
|
<description>Interrupt enable at trigger event
|
|
overrun</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GE</name>
|
|
<description>DMA request generator channel
|
|
enable/disable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GPOL</name>
|
|
<description>DMA request generator trigger event type
|
|
selection Defines the trigger event on the selected
|
|
DMA request trigger input</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GNBREQ</name>
|
|
<description>Number of DMA requests to generate
|
|
Defines the number of DMA requests generated after a
|
|
trigger event, then stop generating. The actual
|
|
number of generated DMA requests is GNBREQ+1. Note:
|
|
This field can only be written when GE bit is
|
|
reset.</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RG1CR</name>
|
|
<displayName>RG1CR</displayName>
|
|
<description>DMAMux - DMA request generator channel x
|
|
control register</description>
|
|
<addressOffset>0x104</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SIG_ID</name>
|
|
<description>DMA request trigger input
|
|
selected</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OIE</name>
|
|
<description>Interrupt enable at trigger event
|
|
overrun</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GE</name>
|
|
<description>DMA request generator channel
|
|
enable/disable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GPOL</name>
|
|
<description>DMA request generator trigger event type
|
|
selection Defines the trigger event on the selected
|
|
DMA request trigger input</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GNBREQ</name>
|
|
<description>Number of DMA requests to generate
|
|
Defines the number of DMA requests generated after a
|
|
trigger event, then stop generating. The actual
|
|
number of generated DMA requests is GNBREQ+1. Note:
|
|
This field can only be written when GE bit is
|
|
reset.</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RG2CR</name>
|
|
<displayName>RG2CR</displayName>
|
|
<description>DMAMux - DMA request generator channel x
|
|
control register</description>
|
|
<addressOffset>0x108</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SIG_ID</name>
|
|
<description>DMA request trigger input
|
|
selected</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OIE</name>
|
|
<description>Interrupt enable at trigger event
|
|
overrun</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GE</name>
|
|
<description>DMA request generator channel
|
|
enable/disable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GPOL</name>
|
|
<description>DMA request generator trigger event type
|
|
selection Defines the trigger event on the selected
|
|
DMA request trigger input</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GNBREQ</name>
|
|
<description>Number of DMA requests to generate
|
|
Defines the number of DMA requests generated after a
|
|
trigger event, then stop generating. The actual
|
|
number of generated DMA requests is GNBREQ+1. Note:
|
|
This field can only be written when GE bit is
|
|
reset.</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RG3CR</name>
|
|
<displayName>RG3CR</displayName>
|
|
<description>DMAMux - DMA request generator channel x
|
|
control register</description>
|
|
<addressOffset>0x10C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SIG_ID</name>
|
|
<description>DMA request trigger input
|
|
selected</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OIE</name>
|
|
<description>Interrupt enable at trigger event
|
|
overrun</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GE</name>
|
|
<description>DMA request generator channel
|
|
enable/disable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GPOL</name>
|
|
<description>DMA request generator trigger event type
|
|
selection Defines the trigger event on the selected
|
|
DMA request trigger input</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GNBREQ</name>
|
|
<description>Number of DMA requests to generate
|
|
Defines the number of DMA requests generated after a
|
|
trigger event, then stop generating. The actual
|
|
number of generated DMA requests is GNBREQ+1. Note:
|
|
This field can only be written when GE bit is
|
|
reset.</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RG4CR</name>
|
|
<displayName>RG4CR</displayName>
|
|
<description>DMAMux - DMA request generator channel x
|
|
control register</description>
|
|
<addressOffset>0x110</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SIG_ID</name>
|
|
<description>DMA request trigger input
|
|
selected</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OIE</name>
|
|
<description>Interrupt enable at trigger event
|
|
overrun</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GE</name>
|
|
<description>DMA request generator channel
|
|
enable/disable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GPOL</name>
|
|
<description>DMA request generator trigger event type
|
|
selection Defines the trigger event on the selected
|
|
DMA request trigger input</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GNBREQ</name>
|
|
<description>Number of DMA requests to generate
|
|
Defines the number of DMA requests generated after a
|
|
trigger event, then stop generating. The actual
|
|
number of generated DMA requests is GNBREQ+1. Note:
|
|
This field can only be written when GE bit is
|
|
reset.</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RG5CR</name>
|
|
<displayName>RG5CR</displayName>
|
|
<description>DMAMux - DMA request generator channel x
|
|
control register</description>
|
|
<addressOffset>0x114</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SIG_ID</name>
|
|
<description>DMA request trigger input
|
|
selected</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OIE</name>
|
|
<description>Interrupt enable at trigger event
|
|
overrun</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GE</name>
|
|
<description>DMA request generator channel
|
|
enable/disable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GPOL</name>
|
|
<description>DMA request generator trigger event type
|
|
selection Defines the trigger event on the selected
|
|
DMA request trigger input</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GNBREQ</name>
|
|
<description>Number of DMA requests to generate
|
|
Defines the number of DMA requests generated after a
|
|
trigger event, then stop generating. The actual
|
|
number of generated DMA requests is GNBREQ+1. Note:
|
|
This field can only be written when GE bit is
|
|
reset.</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RG6CR</name>
|
|
<displayName>RG6CR</displayName>
|
|
<description>DMAMux - DMA request generator channel x
|
|
control register</description>
|
|
<addressOffset>0x118</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SIG_ID</name>
|
|
<description>DMA request trigger input
|
|
selected</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OIE</name>
|
|
<description>Interrupt enable at trigger event
|
|
overrun</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GE</name>
|
|
<description>DMA request generator channel
|
|
enable/disable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GPOL</name>
|
|
<description>DMA request generator trigger event type
|
|
selection Defines the trigger event on the selected
|
|
DMA request trigger input</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GNBREQ</name>
|
|
<description>Number of DMA requests to generate
|
|
Defines the number of DMA requests generated after a
|
|
trigger event, then stop generating. The actual
|
|
number of generated DMA requests is GNBREQ+1. Note:
|
|
This field can only be written when GE bit is
|
|
reset.</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RG7CR</name>
|
|
<displayName>RG7CR</displayName>
|
|
<description>DMAMux - DMA request generator channel x
|
|
control register</description>
|
|
<addressOffset>0x11C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SIG_ID</name>
|
|
<description>DMA request trigger input
|
|
selected</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OIE</name>
|
|
<description>Interrupt enable at trigger event
|
|
overrun</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GE</name>
|
|
<description>DMA request generator channel
|
|
enable/disable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GPOL</name>
|
|
<description>DMA request generator trigger event type
|
|
selection Defines the trigger event on the selected
|
|
DMA request trigger input</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GNBREQ</name>
|
|
<description>Number of DMA requests to generate
|
|
Defines the number of DMA requests generated after a
|
|
trigger event, then stop generating. The actual
|
|
number of generated DMA requests is GNBREQ+1. Note:
|
|
This field can only be written when GE bit is
|
|
reset.</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RGSR</name>
|
|
<displayName>RGSR</displayName>
|
|
<description>DMAMux - DMA request generator status
|
|
register</description>
|
|
<addressOffset>0x140</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OF</name>
|
|
<description>Trigger event overrun flag The flag is
|
|
set when a trigger event occurs on DMA request
|
|
generator channel x, while the DMA request generator
|
|
counter value is lower than GNBREQ. The flag is
|
|
cleared by writing 1 to the corresponding COFx bit in
|
|
DMAMUX_RGCFR register.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RGCFR</name>
|
|
<displayName>RGCFR</displayName>
|
|
<description>DMAMux - DMA request generator clear flag
|
|
register</description>
|
|
<addressOffset>0x144</addressOffset>
|
|
<size>0x20</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>COF</name>
|
|
<description>Clear trigger event overrun flag Upon
|
|
setting, this bit clears the corresponding overrun
|
|
flag OFx in the DMAMUX_RGCSR register.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CSR</name>
|
|
<displayName>CSR</displayName>
|
|
<description>DMAMUX request line multiplexer interrupt
|
|
channel status register</description>
|
|
<addressOffset>0x80</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SOF</name>
|
|
<description>Synchronization overrun event
|
|
flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CFR</name>
|
|
<displayName>CFR</displayName>
|
|
<description>DMAMUX request line multiplexer interrupt
|
|
clear flag register</description>
|
|
<addressOffset>0x84</addressOffset>
|
|
<size>0x20</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CSOF</name>
|
|
<description>Clear synchronization overrun event
|
|
flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>FMC</name>
|
|
<description>FMC</description>
|
|
<groupName>FMC</groupName>
|
|
<baseAddress>0x52004000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>FMC</name>
|
|
<description>FMC global interrupt</description>
|
|
<value>48</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>BCR1</name>
|
|
<displayName>BCR1</displayName>
|
|
<description>This register contains the control
|
|
information of each memory bank, used for SRAMs, PSRAM
|
|
and NOR Flash memories.</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x000030DB</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MBKEN</name>
|
|
<description>Memory bank enable bit This bit enables
|
|
the memory bank. After reset Bank1 is enabled, all
|
|
others are disabled. Accessing a disabled bank causes
|
|
an ERROR on AXI bus.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MUXEN</name>
|
|
<description>Address/data multiplexing enable bit
|
|
When this bit is set, the address and data values are
|
|
multiplexed on the data bus, valid only with NOR and
|
|
PSRAM memories:</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MTYP</name>
|
|
<description>Memory type These bits define the type
|
|
of external memory attached to the corresponding
|
|
memory bank:</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MWID</name>
|
|
<description>Memory data bus width Defines the
|
|
external memory device width, valid for all type of
|
|
memories.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FACCEN</name>
|
|
<description>Flash access enable This bit enables NOR
|
|
Flash memory access operations.</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BURSTEN</name>
|
|
<description>Burst enable bit This bit
|
|
enables/disables synchronous accesses during read
|
|
operations. It is valid only for synchronous memories
|
|
operating in Burst mode:</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WAITPOL</name>
|
|
<description>Wait signal polarity bit This bit
|
|
defines the polarity of the wait signal from memory
|
|
used for either in synchronous or asynchronous
|
|
mode:</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WAITCFG</name>
|
|
<description>Wait timing configuration The NWAIT
|
|
signal indicates whether the data from the memory are
|
|
valid or if a wait state must be inserted when
|
|
accessing the memory in synchronous mode. This
|
|
configuration bit determines if NWAIT is asserted by
|
|
the memory one clock cycle before the wait state or
|
|
during the wait state:</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WREN</name>
|
|
<description>Write enable bit This bit indicates
|
|
whether write operations are enabled/disabled in the
|
|
bank by the FMC:</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WAITEN</name>
|
|
<description>Wait enable bit This bit
|
|
enables/disables wait-state insertion via the NWAIT
|
|
signal when accessing the memory in synchronous
|
|
mode.</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTMOD</name>
|
|
<description>Extended mode enable. This bit enables
|
|
the FMC to program the write timings for asynchronous
|
|
accesses inside the FMC_BWTR register, thus resulting
|
|
in different timings for read and write operations.
|
|
Note: When the extended mode is disabled, the FMC can
|
|
operate in Mode1 or Mode2 as follows: ** Mode 1 is
|
|
the default mode when the SRAM/PSRAM memory type is
|
|
selected (MTYP =0x0 or 0x01) ** Mode 2 is the default
|
|
mode when the NOR memory type is selected (MTYP =
|
|
0x10).</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ASYNCWAIT</name>
|
|
<description>Wait signal during asynchronous
|
|
transfers This bit enables/disables the FMC to use
|
|
the wait signal even during an asynchronous
|
|
protocol.</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CPSIZE</name>
|
|
<description>CRAM Page Size These are used for
|
|
Cellular RAM 1.5 which does not allow burst access to
|
|
cross the address boundaries between pages. When
|
|
these bits are configured, the FMC controller splits
|
|
automatically the burst access when the memory page
|
|
size is reached (refer to memory datasheet for page
|
|
size). Other configuration: reserved.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CBURSTRW</name>
|
|
<description>Write burst enable For PSRAM (CRAM)
|
|
operating in Burst mode, the bit enables synchronous
|
|
accesses during write operations. The enable bit for
|
|
synchronous read accesses is the BURSTEN bit in the
|
|
FMC_BCRx register.</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CCLKEN</name>
|
|
<description>Continuous Clock Enable This bit enables
|
|
the FMC_CLK clock output to external memory devices.
|
|
Note: The CCLKEN bit of the FMC_BCR2..4 registers is
|
|
dont care. It is only enabled through the FMC_BCR1
|
|
register. Bank 1 must be configured in synchronous
|
|
mode to generate the FMC_CLK continuous clock. If
|
|
CCLKEN bit is set, the FMC_CLK clock ratio is
|
|
specified by CLKDIV value in the FMC_BTR1 register.
|
|
CLKDIV in FMC_BWTR1 is dont care. If the synchronous
|
|
mode is used and CCLKEN bit is set, the synchronous
|
|
memories connected to other banks than Bank 1 are
|
|
clocked by the same clock (the CLKDIV value in the
|
|
FMC_BTR2..4 and FMC_BWTR2..4 registers for other
|
|
banks has no effect.)</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WFDIS</name>
|
|
<description>Write FIFO Disable This bit disables the
|
|
Write FIFO used by the FMC controller. Note: The
|
|
WFDIS bit of the FMC_BCR2..4 registers is dont care.
|
|
It is only enabled through the FMC_BCR1
|
|
register.</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BMAP</name>
|
|
<description>FMC bank mapping These bits allows
|
|
different to remap SDRAM bank2 or swap the FMC
|
|
NOR/PSRAM and SDRAM banks.Refer to Table 10 for Note:
|
|
The BMAP bits of the FMC_BCR2..4 registers are dont
|
|
care. It is only enabled through the FMC_BCR1
|
|
register.</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FMCEN</name>
|
|
<description>FMC controller Enable This bit
|
|
enables/disables the FMC controller. Note: The FMCEN
|
|
bit of the FMC_BCR2..4 registers is dont care. It is
|
|
only enabled through the FMC_BCR1
|
|
register.</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BTR1</name>
|
|
<displayName>BTR1</displayName>
|
|
<description>This register contains the control
|
|
information of each memory bank, used for SRAMs, PSRAM
|
|
and NOR Flash memories.If the EXTMOD bit is set in the
|
|
FMC_BCRx register, then this register is partitioned for
|
|
write and read access, that is, 2 registers are
|
|
available: one to configure read accesses (this register)
|
|
and one to configure write accesses (FMC_BWTRx
|
|
registers).</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0FFFFFFF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ADDSET</name>
|
|
<description>Address setup phase duration These bits
|
|
are written by software to define the duration of the
|
|
address setup phase (refer to Figure81 to Figure93),
|
|
used in SRAMs, ROMs and asynchronous NOR Flash: For
|
|
each access mode address setup phase duration, please
|
|
refer to the respective figure (refer to Figure81 to
|
|
Figure93). Note: In synchronous accesses, this value
|
|
is dont care. In Muxed mode or Mode D, the minimum
|
|
value for ADDSET is 1.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADDHLD</name>
|
|
<description>Address-hold phase duration These bits
|
|
are written by software to define the duration of the
|
|
address hold phase (refer to Figure81 to Figure93),
|
|
used in mode D or multiplexed accesses: For each
|
|
access mode address-hold phase duration, please refer
|
|
to the respective figure (Figure81 to Figure93).
|
|
Note: In synchronous accesses, this value is not
|
|
used, the address hold phase is always 1 memory clock
|
|
period duration.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DATAST</name>
|
|
<description>Data-phase duration These bits are
|
|
written by software to define the duration of the
|
|
data phase (refer to Figure81 to Figure93), used in
|
|
asynchronous accesses: For each memory type and
|
|
access mode data-phase duration, please refer to the
|
|
respective figure (Figure81 to Figure93). Example:
|
|
Mode1, write access, DATAST=1: Data-phase duration=
|
|
DATAST+1 = 2 KCK_FMC clock cycles. Note: In
|
|
synchronous accesses, this value is dont
|
|
care.</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BUSTURN</name>
|
|
<description>Bus turnaround phase duration These bits
|
|
are written by software to add a delay at the end of
|
|
a write-to-read or read-to write transaction. The
|
|
programmed bus turnaround delay is inserted between
|
|
an asynchronous read (in muxed or mode D) or write
|
|
transaction and any other asynchronous /synchronous
|
|
read/write from/to a static bank. If a read operation
|
|
is performed, the bank can be the same or a different
|
|
one, whereas it must be different in case of write
|
|
operation to the bank, except in muxed mode or mode
|
|
D. In some cases, whatever the programmed BUSTRUN
|
|
values, the bus turnaround delay is fixed as follows:
|
|
The bus turnaround delay is not inserted between two
|
|
consecutive asynchronous write transfers to the same
|
|
static memory bank except in muxed mode and mode D.
|
|
There is a bus turnaround delay of 1 FMC clock cycle
|
|
between: Two consecutive asynchronous read transfers
|
|
to the same static memory bank except for modes muxed
|
|
and D. An asynchronous read to an asynchronous or
|
|
synchronous write to any static bank or dynamic bank
|
|
except in modes muxed and D mode. There is a bus
|
|
turnaround delay of 2 FMC clock cycle between: Two
|
|
consecutive synchronous write operations (in Burst or
|
|
Single mode) to the same bank. A synchronous write
|
|
(burst or single) access and an asynchronous write or
|
|
read transfer to or from static memory bank (the bank
|
|
can be the same or a different one in case of a read
|
|
operation. Two consecutive synchronous read
|
|
operations (in Burst or Single mode) followed by any
|
|
synchronous/asynchronous read or write from/to
|
|
another static memory bank. There is a bus turnaround
|
|
delay of 3 FMC clock cycle between: Two consecutive
|
|
synchronous write operations (in Burst or Single
|
|
mode) to different static banks. A synchronous write
|
|
access (in Burst or Single mode) and a synchronous
|
|
read from the same or a different bank. The bus
|
|
turnaround delay allows to match the minimum time
|
|
between consecutive transactions (tEHEL from NEx high
|
|
to NEx low) and the maximum time required by the
|
|
memory to free the data bus after a read access
|
|
(tEHQZ): (BUSTRUN + 1) KCK_FMC period &#8805;
|
|
tEHELmin and (BUSTRUN + 2)KCK_FMC period &#8805;
|
|
tEHQZmax if EXTMOD = 0 (BUSTRUN + 2)KCK_FMC period
|
|
&#8805; max (tEHELmin, tEHQZmax) if EXTMOD = 126.
|
|
...</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CLKDIV</name>
|
|
<description>Clock divide ratio (for FMC_CLK signal)
|
|
These bits define the period of FMC_CLK clock output
|
|
signal, expressed in number of KCK_FMC cycles: In
|
|
asynchronous NOR Flash, SRAM or PSRAM accesses, this
|
|
value is dont care. Note: Refer to Section20.6.5:
|
|
Synchronous transactions for FMC_CLK divider ratio
|
|
formula)</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DATLAT</name>
|
|
<description>Data latency for synchronous memory For
|
|
synchronous access with read write burst mode enabled
|
|
these bits define the number of memory clock
|
|
cycles</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ACCMOD</name>
|
|
<description>Access mode These bits specify the
|
|
asynchronous access modes as shown in the timing
|
|
diagrams. They are taken into account only when the
|
|
EXTMOD bit in the FMC_BCRx register is
|
|
1.</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BCR2</name>
|
|
<displayName>BCR2</displayName>
|
|
<description>This register contains the control
|
|
information of each memory bank, used for SRAMs, PSRAM
|
|
and NOR Flash memories.</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x000030D2</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MBKEN</name>
|
|
<description>Memory bank enable bit This bit enables
|
|
the memory bank. After reset Bank1 is enabled, all
|
|
others are disabled. Accessing a disabled bank causes
|
|
an ERROR on AXI bus.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MUXEN</name>
|
|
<description>Address/data multiplexing enable bit
|
|
When this bit is set, the address and data values are
|
|
multiplexed on the data bus, valid only with NOR and
|
|
PSRAM memories:</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MTYP</name>
|
|
<description>Memory type These bits define the type
|
|
of external memory attached to the corresponding
|
|
memory bank:</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MWID</name>
|
|
<description>Memory data bus width Defines the
|
|
external memory device width, valid for all type of
|
|
memories.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FACCEN</name>
|
|
<description>Flash access enable This bit enables NOR
|
|
Flash memory access operations.</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BURSTEN</name>
|
|
<description>Burst enable bit This bit
|
|
enables/disables synchronous accesses during read
|
|
operations. It is valid only for synchronous memories
|
|
operating in Burst mode:</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WAITPOL</name>
|
|
<description>Wait signal polarity bit This bit
|
|
defines the polarity of the wait signal from memory
|
|
used for either in synchronous or asynchronous
|
|
mode:</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WAITCFG</name>
|
|
<description>Wait timing configuration The NWAIT
|
|
signal indicates whether the data from the memory are
|
|
valid or if a wait state must be inserted when
|
|
accessing the memory in synchronous mode. This
|
|
configuration bit determines if NWAIT is asserted by
|
|
the memory one clock cycle before the wait state or
|
|
during the wait state:</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WREN</name>
|
|
<description>Write enable bit This bit indicates
|
|
whether write operations are enabled/disabled in the
|
|
bank by the FMC:</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WAITEN</name>
|
|
<description>Wait enable bit This bit
|
|
enables/disables wait-state insertion via the NWAIT
|
|
signal when accessing the memory in synchronous
|
|
mode.</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTMOD</name>
|
|
<description>Extended mode enable. This bit enables
|
|
the FMC to program the write timings for asynchronous
|
|
accesses inside the FMC_BWTR register, thus resulting
|
|
in different timings for read and write operations.
|
|
Note: When the extended mode is disabled, the FMC can
|
|
operate in Mode1 or Mode2 as follows: ** Mode 1 is
|
|
the default mode when the SRAM/PSRAM memory type is
|
|
selected (MTYP =0x0 or 0x01) ** Mode 2 is the default
|
|
mode when the NOR memory type is selected (MTYP =
|
|
0x10).</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ASYNCWAIT</name>
|
|
<description>Wait signal during asynchronous
|
|
transfers This bit enables/disables the FMC to use
|
|
the wait signal even during an asynchronous
|
|
protocol.</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CPSIZE</name>
|
|
<description>CRAM Page Size These are used for
|
|
Cellular RAM 1.5 which does not allow burst access to
|
|
cross the address boundaries between pages. When
|
|
these bits are configured, the FMC controller splits
|
|
automatically the burst access when the memory page
|
|
size is reached (refer to memory datasheet for page
|
|
size). Other configuration: reserved.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CBURSTRW</name>
|
|
<description>Write burst enable For PSRAM (CRAM)
|
|
operating in Burst mode, the bit enables synchronous
|
|
accesses during write operations. The enable bit for
|
|
synchronous read accesses is the BURSTEN bit in the
|
|
FMC_BCRx register.</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CCLKEN</name>
|
|
<description>Continuous Clock Enable This bit enables
|
|
the FMC_CLK clock output to external memory devices.
|
|
Note: The CCLKEN bit of the FMC_BCR2..4 registers is
|
|
dont care. It is only enabled through the FMC_BCR1
|
|
register. Bank 1 must be configured in synchronous
|
|
mode to generate the FMC_CLK continuous clock. If
|
|
CCLKEN bit is set, the FMC_CLK clock ratio is
|
|
specified by CLKDIV value in the FMC_BTR1 register.
|
|
CLKDIV in FMC_BWTR1 is dont care. If the synchronous
|
|
mode is used and CCLKEN bit is set, the synchronous
|
|
memories connected to other banks than Bank 1 are
|
|
clocked by the same clock (the CLKDIV value in the
|
|
FMC_BTR2..4 and FMC_BWTR2..4 registers for other
|
|
banks has no effect.)</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WFDIS</name>
|
|
<description>Write FIFO Disable This bit disables the
|
|
Write FIFO used by the FMC controller. Note: The
|
|
WFDIS bit of the FMC_BCR2..4 registers is dont care.
|
|
It is only enabled through the FMC_BCR1
|
|
register.</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BMAP</name>
|
|
<description>FMC bank mapping These bits allows
|
|
different to remap SDRAM bank2 or swap the FMC
|
|
NOR/PSRAM and SDRAM banks.Refer to Table 10 for Note:
|
|
The BMAP bits of the FMC_BCR2..4 registers are dont
|
|
care. It is only enabled through the FMC_BCR1
|
|
register.</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FMCEN</name>
|
|
<description>FMC controller Enable This bit
|
|
enables/disables the FMC controller. Note: The FMCEN
|
|
bit of the FMC_BCR2..4 registers is dont care. It is
|
|
only enabled through the FMC_BCR1
|
|
register.</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BTR2</name>
|
|
<displayName>BTR2</displayName>
|
|
<description>This register contains the control
|
|
information of each memory bank, used for SRAMs, PSRAM
|
|
and NOR Flash memories.If the EXTMOD bit is set in the
|
|
FMC_BCRx register, then this register is partitioned for
|
|
write and read access, that is, 2 registers are
|
|
available: one to configure read accesses (this register)
|
|
and one to configure write accesses (FMC_BWTRx
|
|
registers).</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0FFFFFFF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ADDSET</name>
|
|
<description>Address setup phase duration These bits
|
|
are written by software to define the duration of the
|
|
address setup phase (refer to Figure81 to Figure93),
|
|
used in SRAMs, ROMs and asynchronous NOR Flash: For
|
|
each access mode address setup phase duration, please
|
|
refer to the respective figure (refer to Figure81 to
|
|
Figure93). Note: In synchronous accesses, this value
|
|
is dont care. In Muxed mode or Mode D, the minimum
|
|
value for ADDSET is 1.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADDHLD</name>
|
|
<description>Address-hold phase duration These bits
|
|
are written by software to define the duration of the
|
|
address hold phase (refer to Figure81 to Figure93),
|
|
used in mode D or multiplexed accesses: For each
|
|
access mode address-hold phase duration, please refer
|
|
to the respective figure (Figure81 to Figure93).
|
|
Note: In synchronous accesses, this value is not
|
|
used, the address hold phase is always 1 memory clock
|
|
period duration.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DATAST</name>
|
|
<description>Data-phase duration These bits are
|
|
written by software to define the duration of the
|
|
data phase (refer to Figure81 to Figure93), used in
|
|
asynchronous accesses: For each memory type and
|
|
access mode data-phase duration, please refer to the
|
|
respective figure (Figure81 to Figure93). Example:
|
|
Mode1, write access, DATAST=1: Data-phase duration=
|
|
DATAST+1 = 2 KCK_FMC clock cycles. Note: In
|
|
synchronous accesses, this value is dont
|
|
care.</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BUSTURN</name>
|
|
<description>Bus turnaround phase duration These bits
|
|
are written by software to add a delay at the end of
|
|
a write-to-read or read-to write transaction. The
|
|
programmed bus turnaround delay is inserted between
|
|
an asynchronous read (in muxed or mode D) or write
|
|
transaction and any other asynchronous /synchronous
|
|
read/write from/to a static bank. If a read operation
|
|
is performed, the bank can be the same or a different
|
|
one, whereas it must be different in case of write
|
|
operation to the bank, except in muxed mode or mode
|
|
D. In some cases, whatever the programmed BUSTRUN
|
|
values, the bus turnaround delay is fixed as follows:
|
|
The bus turnaround delay is not inserted between two
|
|
consecutive asynchronous write transfers to the same
|
|
static memory bank except in muxed mode and mode D.
|
|
There is a bus turnaround delay of 1 FMC clock cycle
|
|
between: Two consecutive asynchronous read transfers
|
|
to the same static memory bank except for modes muxed
|
|
and D. An asynchronous read to an asynchronous or
|
|
synchronous write to any static bank or dynamic bank
|
|
except in modes muxed and D mode. There is a bus
|
|
turnaround delay of 2 FMC clock cycle between: Two
|
|
consecutive synchronous write operations (in Burst or
|
|
Single mode) to the same bank. A synchronous write
|
|
(burst or single) access and an asynchronous write or
|
|
read transfer to or from static memory bank (the bank
|
|
can be the same or a different one in case of a read
|
|
operation. Two consecutive synchronous read
|
|
operations (in Burst or Single mode) followed by any
|
|
synchronous/asynchronous read or write from/to
|
|
another static memory bank. There is a bus turnaround
|
|
delay of 3 FMC clock cycle between: Two consecutive
|
|
synchronous write operations (in Burst or Single
|
|
mode) to different static banks. A synchronous write
|
|
access (in Burst or Single mode) and a synchronous
|
|
read from the same or a different bank. The bus
|
|
turnaround delay allows to match the minimum time
|
|
between consecutive transactions (tEHEL from NEx high
|
|
to NEx low) and the maximum time required by the
|
|
memory to free the data bus after a read access
|
|
(tEHQZ): (BUSTRUN + 1) KCK_FMC period &#8805;
|
|
tEHELmin and (BUSTRUN + 2)KCK_FMC period &#8805;
|
|
tEHQZmax if EXTMOD = 0 (BUSTRUN + 2)KCK_FMC period
|
|
&#8805; max (tEHELmin, tEHQZmax) if EXTMOD = 1.
|
|
...</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CLKDIV</name>
|
|
<description>Clock divide ratio (for FMC_CLK signal)
|
|
These bits define the period of FMC_CLK clock output
|
|
signal, expressed in number of KCK_FMC cycles: In
|
|
asynchronous NOR Flash, SRAM or PSRAM accesses, this
|
|
value is dont care. Note: Refer to Section20.6.5:
|
|
Synchronous transactions for FMC_CLK divider ratio
|
|
formula)</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DATLAT</name>
|
|
<description>Data latency for synchronous memory For
|
|
synchronous access with read write burst mode enabled
|
|
these bits define the number of memory clock
|
|
cycles</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ACCMOD</name>
|
|
<description>Access mode These bits specify the
|
|
asynchronous access modes as shown in the timing
|
|
diagrams. They are taken into account only when the
|
|
EXTMOD bit in the FMC_BCRx register is
|
|
1.</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BCR3</name>
|
|
<displayName>BCR3</displayName>
|
|
<description>This register contains the control
|
|
information of each memory bank, used for SRAMs, PSRAM
|
|
and NOR Flash memories.</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x000030D2</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MBKEN</name>
|
|
<description>Memory bank enable bit This bit enables
|
|
the memory bank. After reset Bank1 is enabled, all
|
|
others are disabled. Accessing a disabled bank causes
|
|
an ERROR on AXI bus.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MUXEN</name>
|
|
<description>Address/data multiplexing enable bit
|
|
When this bit is set, the address and data values are
|
|
multiplexed on the data bus, valid only with NOR and
|
|
PSRAM memories:</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MTYP</name>
|
|
<description>Memory type These bits define the type
|
|
of external memory attached to the corresponding
|
|
memory bank:</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MWID</name>
|
|
<description>Memory data bus width Defines the
|
|
external memory device width, valid for all type of
|
|
memories.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FACCEN</name>
|
|
<description>Flash access enable This bit enables NOR
|
|
Flash memory access operations.</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BURSTEN</name>
|
|
<description>Burst enable bit This bit
|
|
enables/disables synchronous accesses during read
|
|
operations. It is valid only for synchronous memories
|
|
operating in Burst mode:</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WAITPOL</name>
|
|
<description>Wait signal polarity bit This bit
|
|
defines the polarity of the wait signal from memory
|
|
used for either in synchronous or asynchronous
|
|
mode:</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WAITCFG</name>
|
|
<description>Wait timing configuration The NWAIT
|
|
signal indicates whether the data from the memory are
|
|
valid or if a wait state must be inserted when
|
|
accessing the memory in synchronous mode. This
|
|
configuration bit determines if NWAIT is asserted by
|
|
the memory one clock cycle before the wait state or
|
|
during the wait state:</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WREN</name>
|
|
<description>Write enable bit This bit indicates
|
|
whether write operations are enabled/disabled in the
|
|
bank by the FMC:</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WAITEN</name>
|
|
<description>Wait enable bit This bit
|
|
enables/disables wait-state insertion via the NWAIT
|
|
signal when accessing the memory in synchronous
|
|
mode.</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTMOD</name>
|
|
<description>Extended mode enable. This bit enables
|
|
the FMC to program the write timings for asynchronous
|
|
accesses inside the FMC_BWTR register, thus resulting
|
|
in different timings for read and write operations.
|
|
Note: When the extended mode is disabled, the FMC can
|
|
operate in Mode1 or Mode2 as follows: ** Mode 1 is
|
|
the default mode when the SRAM/PSRAM memory type is
|
|
selected (MTYP =0x0 or 0x01) ** Mode 2 is the default
|
|
mode when the NOR memory type is selected (MTYP =
|
|
0x10).</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ASYNCWAIT</name>
|
|
<description>Wait signal during asynchronous
|
|
transfers This bit enables/disables the FMC to use
|
|
the wait signal even during an asynchronous
|
|
protocol.</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CPSIZE</name>
|
|
<description>CRAM Page Size These are used for
|
|
Cellular RAM 1.5 which does not allow burst access to
|
|
cross the address boundaries between pages. When
|
|
these bits are configured, the FMC controller splits
|
|
automatically the burst access when the memory page
|
|
size is reached (refer to memory datasheet for page
|
|
size). Other configuration: reserved.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CBURSTRW</name>
|
|
<description>Write burst enable For PSRAM (CRAM)
|
|
operating in Burst mode, the bit enables synchronous
|
|
accesses during write operations. The enable bit for
|
|
synchronous read accesses is the BURSTEN bit in the
|
|
FMC_BCRx register.</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CCLKEN</name>
|
|
<description>Continuous Clock Enable This bit enables
|
|
the FMC_CLK clock output to external memory devices.
|
|
Note: The CCLKEN bit of the FMC_BCR2..4 registers is
|
|
dont care. It is only enabled through the FMC_BCR1
|
|
register. Bank 1 must be configured in synchronous
|
|
mode to generate the FMC_CLK continuous clock. If
|
|
CCLKEN bit is set, the FMC_CLK clock ratio is
|
|
specified by CLKDIV value in the FMC_BTR1 register.
|
|
CLKDIV in FMC_BWTR1 is dont care. If the synchronous
|
|
mode is used and CCLKEN bit is set, the synchronous
|
|
memories connected to other banks than Bank 1 are
|
|
clocked by the same clock (the CLKDIV value in the
|
|
FMC_BTR2..4 and FMC_BWTR2..4 registers for other
|
|
banks has no effect.)</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WFDIS</name>
|
|
<description>Write FIFO Disable This bit disables the
|
|
Write FIFO used by the FMC controller. Note: The
|
|
WFDIS bit of the FMC_BCR2..4 registers is dont care.
|
|
It is only enabled through the FMC_BCR1
|
|
register.</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BMAP</name>
|
|
<description>FMC bank mapping These bits allows
|
|
different to remap SDRAM bank2 or swap the FMC
|
|
NOR/PSRAM and SDRAM banks.Refer to Table 10 for Note:
|
|
The BMAP bits of the FMC_BCR2..4 registers are dont
|
|
care. It is only enabled through the FMC_BCR1
|
|
register.</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FMCEN</name>
|
|
<description>FMC controller Enable This bit
|
|
enables/disables the FMC controller. Note: The FMCEN
|
|
bit of the FMC_BCR2..4 registers is dont care. It is
|
|
only enabled through the FMC_BCR1
|
|
register.</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BTR3</name>
|
|
<displayName>BTR3</displayName>
|
|
<description>This register contains the control
|
|
information of each memory bank, used for SRAMs, PSRAM
|
|
and NOR Flash memories.If the EXTMOD bit is set in the
|
|
FMC_BCRx register, then this register is partitioned for
|
|
write and read access, that is, 2 registers are
|
|
available: one to configure read accesses (this register)
|
|
and one to configure write accesses (FMC_BWTRx
|
|
registers).</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0FFFFFFF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ADDSET</name>
|
|
<description>Address setup phase duration These bits
|
|
are written by software to define the duration of the
|
|
address setup phase (refer to Figure81 to Figure93),
|
|
used in SRAMs, ROMs and asynchronous NOR Flash: For
|
|
each access mode address setup phase duration, please
|
|
refer to the respective figure (refer to Figure81 to
|
|
Figure93). Note: In synchronous accesses, this value
|
|
is dont care. In Muxed mode or Mode D, the minimum
|
|
value for ADDSET is 1.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADDHLD</name>
|
|
<description>Address-hold phase duration These bits
|
|
are written by software to define the duration of the
|
|
address hold phase (refer to Figure81 to Figure93),
|
|
used in mode D or multiplexed accesses: For each
|
|
access mode address-hold phase duration, please refer
|
|
to the respective figure (Figure81 to Figure93).
|
|
Note: In synchronous accesses, this value is not
|
|
used, the address hold phase is always 1 memory clock
|
|
period duration.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DATAST</name>
|
|
<description>Data-phase duration These bits are
|
|
written by software to define the duration of the
|
|
data phase (refer to Figure81 to Figure93), used in
|
|
asynchronous accesses: For each memory type and
|
|
access mode data-phase duration, please refer to the
|
|
respective figure (Figure81 to Figure93). Example:
|
|
Mode1, write access, DATAST=1: Data-phase duration=
|
|
DATAST+1 = 2 KCK_FMC clock cycles. Note: In
|
|
synchronous accesses, this value is dont
|
|
care.</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BUSTURN</name>
|
|
<description>Bus turnaround phase duration These bits
|
|
are written by software to add a delay at the end of
|
|
a write-to-read or read-to write transaction. The
|
|
programmed bus turnaround delay is inserted between
|
|
an asynchronous read (in muxed or mode D) or write
|
|
transaction and any other asynchronous /synchronous
|
|
read/write from/to a static bank. If a read operation
|
|
is performed, the bank can be the same or a different
|
|
one, whereas it must be different in case of write
|
|
operation to the bank, except in muxed mode or mode
|
|
D. In some cases, whatever the programmed BUSTRUN
|
|
values, the bus turnaround delay is fixed as follows:
|
|
The bus turnaround delay is not inserted between two
|
|
consecutive asynchronous write transfers to the same
|
|
static memory bank except in muxed mode and mode D.
|
|
There is a bus turnaround delay of 1 FMC clock cycle
|
|
between: Two consecutive asynchronous read transfers
|
|
to the same static memory bank except for modes muxed
|
|
and D. An asynchronous read to an asynchronous or
|
|
synchronous write to any static bank or dynamic bank
|
|
except in modes muxed and D mode. There is a bus
|
|
turnaround delay of 2 FMC clock cycle between: Two
|
|
consecutive synchronous write operations (in Burst or
|
|
Single mode) to the same bank. A synchronous write
|
|
(burst or single) access and an asynchronous write or
|
|
read transfer to or from static memory bank (the bank
|
|
can be the same or a different one in case of a read
|
|
operation. Two consecutive synchronous read
|
|
operations (in Burst or Single mode) followed by any
|
|
synchronous/asynchronous read or write from/to
|
|
another static memory bank. There is a bus turnaround
|
|
delay of 3 FMC clock cycle between: Two consecutive
|
|
synchronous write operations (in Burst or Single
|
|
mode) to different static banks. A synchronous write
|
|
access (in Burst or Single mode) and a synchronous
|
|
read from the same or a different bank. The bus
|
|
turnaround delay allows to match the minimum time
|
|
between consecutive transactions (tEHEL from NEx high
|
|
to NEx low) and the maximum time required by the
|
|
memory to free the data bus after a read access
|
|
(tEHQZ): (BUSTRUN + 1) KCK_FMC period &#8805;
|
|
tEHELmin and (BUSTRUN + 2)KCK_FMC period &#8805;
|
|
tEHQZmax if EXTMOD = 0 (BUSTRUN + 2)KCK_FMC period
|
|
&#8805; max (tEHELmin, tEHQZmax) if EXTMOD =1.
|
|
...</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CLKDIV</name>
|
|
<description>Clock divide ratio (for FMC_CLK signal)
|
|
These bits define the period of FMC_CLK clock output
|
|
signal, expressed in number of KCK_FMC cycles: In
|
|
asynchronous NOR Flash, SRAM or PSRAM accesses, this
|
|
value is dont care. Note: Refer to Section20.6.5:
|
|
Synchronous transactions for FMC_CLK divider ratio
|
|
formula)</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DATLAT</name>
|
|
<description>Data latency for synchronous memory For
|
|
synchronous access with read write burst mode enabled
|
|
these bits define the number of memory clock
|
|
cycles</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ACCMOD</name>
|
|
<description>Access mode These bits specify the
|
|
asynchronous access modes as shown in the timing
|
|
diagrams. They are taken into account only when the
|
|
EXTMOD bit in the FMC_BCRx register is
|
|
1.</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BCR4</name>
|
|
<displayName>BCR4</displayName>
|
|
<description>This register contains the control
|
|
information of each memory bank, used for SRAMs, PSRAM
|
|
and NOR Flash memories.</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x000030D2</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MBKEN</name>
|
|
<description>Memory bank enable bit This bit enables
|
|
the memory bank. After reset Bank1 is enabled, all
|
|
others are disabled. Accessing a disabled bank causes
|
|
an ERROR on AXI bus.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MUXEN</name>
|
|
<description>Address/data multiplexing enable bit
|
|
When this bit is set, the address and data values are
|
|
multiplexed on the data bus, valid only with NOR and
|
|
PSRAM memories:</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MTYP</name>
|
|
<description>Memory type These bits define the type
|
|
of external memory attached to the corresponding
|
|
memory bank:</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MWID</name>
|
|
<description>Memory data bus width Defines the
|
|
external memory device width, valid for all type of
|
|
memories.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FACCEN</name>
|
|
<description>Flash access enable This bit enables NOR
|
|
Flash memory access operations.</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BURSTEN</name>
|
|
<description>Burst enable bit This bit
|
|
enables/disables synchronous accesses during read
|
|
operations. It is valid only for synchronous memories
|
|
operating in Burst mode:</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WAITPOL</name>
|
|
<description>Wait signal polarity bit This bit
|
|
defines the polarity of the wait signal from memory
|
|
used for either in synchronous or asynchronous
|
|
mode:</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WAITCFG</name>
|
|
<description>Wait timing configuration The NWAIT
|
|
signal indicates whether the data from the memory are
|
|
valid or if a wait state must be inserted when
|
|
accessing the memory in synchronous mode. This
|
|
configuration bit determines if NWAIT is asserted by
|
|
the memory one clock cycle before the wait state or
|
|
during the wait state:</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WREN</name>
|
|
<description>Write enable bit This bit indicates
|
|
whether write operations are enabled/disabled in the
|
|
bank by the FMC:</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WAITEN</name>
|
|
<description>Wait enable bit This bit
|
|
enables/disables wait-state insertion via the NWAIT
|
|
signal when accessing the memory in synchronous
|
|
mode.</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTMOD</name>
|
|
<description>Extended mode enable. This bit enables
|
|
the FMC to program the write timings for asynchronous
|
|
accesses inside the FMC_BWTR register, thus resulting
|
|
in different timings for read and write operations.
|
|
Note: When the extended mode is disabled, the FMC can
|
|
operate in Mode1 or Mode2 as follows: ** Mode 1 is
|
|
the default mode when the SRAM/PSRAM memory type is
|
|
selected (MTYP =0x0 or 0x01) ** Mode 2 is the default
|
|
mode when the NOR memory type is selected (MTYP =
|
|
0x10).</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ASYNCWAIT</name>
|
|
<description>Wait signal during asynchronous
|
|
transfers This bit enables/disables the FMC to use
|
|
the wait signal even during an asynchronous
|
|
protocol.</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CPSIZE</name>
|
|
<description>CRAM Page Size These are used for
|
|
Cellular RAM 1.5 which does not allow burst access to
|
|
cross the address boundaries between pages. When
|
|
these bits are configured, the FMC controller splits
|
|
automatically the burst access when the memory page
|
|
size is reached (refer to memory datasheet for page
|
|
size). Other configuration: reserved.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CBURSTRW</name>
|
|
<description>Write burst enable For PSRAM (CRAM)
|
|
operating in Burst mode, the bit enables synchronous
|
|
accesses during write operations. The enable bit for
|
|
synchronous read accesses is the BURSTEN bit in the
|
|
FMC_BCRx register.</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CCLKEN</name>
|
|
<description>Continuous Clock Enable This bit enables
|
|
the FMC_CLK clock output to external memory devices.
|
|
Note: The CCLKEN bit of the FMC_BCR2..4 registers is
|
|
dont care. It is only enabled through the FMC_BCR1
|
|
register. Bank 1 must be configured in synchronous
|
|
mode to generate the FMC_CLK continuous clock. If
|
|
CCLKEN bit is set, the FMC_CLK clock ratio is
|
|
specified by CLKDIV value in the FMC_BTR1 register.
|
|
CLKDIV in FMC_BWTR1 is dont care. If the synchronous
|
|
mode is used and CCLKEN bit is set, the synchronous
|
|
memories connected to other banks than Bank 1 are
|
|
clocked by the same clock (the CLKDIV value in the
|
|
FMC_BTR2..4 and FMC_BWTR2..4 registers for other
|
|
banks has no effect.)</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WFDIS</name>
|
|
<description>Write FIFO Disable This bit disables the
|
|
Write FIFO used by the FMC controller. Note: The
|
|
WFDIS bit of the FMC_BCR2..4 registers is dont care.
|
|
It is only enabled through the FMC_BCR1
|
|
register.</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BMAP</name>
|
|
<description>FMC bank mapping These bits allows
|
|
different to remap SDRAM bank2 or swap the FMC
|
|
NOR/PSRAM and SDRAM banks.Refer to Table 10 for Note:
|
|
The BMAP bits of the FMC_BCR2..4 registers are dont
|
|
care. It is only enabled through the FMC_BCR1
|
|
register.</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FMCEN</name>
|
|
<description>FMC controller Enable This bit
|
|
enables/disables the FMC controller. Note: The FMCEN
|
|
bit of the FMC_BCR2..4 registers is dont care. It is
|
|
only enabled through the FMC_BCR1
|
|
register.</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BTR4</name>
|
|
<displayName>BTR4</displayName>
|
|
<description>This register contains the control
|
|
information of each memory bank, used for SRAMs, PSRAM
|
|
and NOR Flash memories.If the EXTMOD bit is set in the
|
|
FMC_BCRx register, then this register is partitioned for
|
|
write and read access, that is, 2 registers are
|
|
available: one to configure read accesses (this register)
|
|
and one to configure write accesses (FMC_BWTRx
|
|
registers).</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0FFFFFFF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ADDSET</name>
|
|
<description>Address setup phase duration These bits
|
|
are written by software to define the duration of the
|
|
address setup phase (refer to Figure81 to Figure93),
|
|
used in SRAMs, ROMs and asynchronous NOR Flash: For
|
|
each access mode address setup phase duration, please
|
|
refer to the respective figure (refer to Figure81 to
|
|
Figure93). Note: In synchronous accesses, this value
|
|
is dont care. In Muxed mode or Mode D, the minimum
|
|
value for ADDSET is 1.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADDHLD</name>
|
|
<description>Address-hold phase duration These bits
|
|
are written by software to define the duration of the
|
|
address hold phase (refer to Figure81 to Figure93),
|
|
used in mode D or multiplexed accesses: For each
|
|
access mode address-hold phase duration, please refer
|
|
to the respective figure (Figure81 to Figure93).
|
|
Note: In synchronous accesses, this value is not
|
|
used, the address hold phase is always 1 memory clock
|
|
period duration.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DATAST</name>
|
|
<description>Data-phase duration These bits are
|
|
written by software to define the duration of the
|
|
data phase (refer to Figure81 to Figure93), used in
|
|
asynchronous accesses: For each memory type and
|
|
access mode data-phase duration, please refer to the
|
|
respective figure (Figure81 to Figure93). Example:
|
|
Mode1, write access, DATAST=1: Data-phase duration=
|
|
DATAST+1 = 2 KCK_FMC clock cycles. Note: In
|
|
synchronous accesses, this value is dont
|
|
care.</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BUSTURN</name>
|
|
<description>Bus turnaround phase duration These bits
|
|
are written by software to add a delay at the end of
|
|
a write-to-read or read-to write transaction. The
|
|
programmed bus turnaround delay is inserted between
|
|
an asynchronous read (in muxed or mode D) or write
|
|
transaction and any other asynchronous /synchronous
|
|
read/write from/to a static bank. If a read operation
|
|
is performed, the bank can be the same or a different
|
|
one, whereas it must be different in case of write
|
|
operation to the bank, except in muxed mode or mode
|
|
D. In some cases, whatever the programmed BUSTRUN
|
|
values, the bus turnaround delay is fixed as follows:
|
|
The bus turnaround delay is not inserted between two
|
|
consecutive asynchronous write transfers to the same
|
|
static memory bank except in muxed mode and mode D.
|
|
There is a bus turnaround delay of 1 FMC clock cycle
|
|
between: Two consecutive asynchronous read transfers
|
|
to the same static memory bank except for modes muxed
|
|
and D. An asynchronous read to an asynchronous or
|
|
synchronous write to any static bank or dynamic bank
|
|
except in modes muxed and D mode. There is a bus
|
|
turnaround delay of 2 FMC clock cycle between: Two
|
|
consecutive synchronous write operations (in Burst or
|
|
Single mode) to the same bank. A synchronous write
|
|
(burst or single) access and an asynchronous write or
|
|
read transfer to or from static memory bank (the bank
|
|
can be the same or a different one in case of a read
|
|
operation. Two consecutive synchronous read
|
|
operations (in Burst or Single mode) followed by any
|
|
synchronous/asynchronous read or write from/to
|
|
another static memory bank. There is a bus turnaround
|
|
delay of 3 FMC clock cycle between: Two consecutive
|
|
synchronous write operations (in Burst or Single
|
|
mode) to different static banks. A synchronous write
|
|
access (in Burst or Single mode) and a synchronous
|
|
read from the same or a different bank. The bus
|
|
turnaround delay allows to match the minimum time
|
|
between consecutive transactions (tEHEL from NEx high
|
|
to NEx low) and the maximum time required by the
|
|
memory to free the data bus after a read access
|
|
(tEHQZ): (BUSTRUN + 1) KCK_FMC period &#8805;
|
|
tEHELmin and (BUSTRUN + 2)KCK_FMC period &#8805;
|
|
tEHQZmax if EXTMOD = 0 (BUSTRUN + 2)KCK_FMC period
|
|
&#8805; max (tEHELmin, tEHQZmax) if EXTMOD =1.
|
|
...</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CLKDIV</name>
|
|
<description>Clock divide ratio (for FMC_CLK signal)
|
|
These bits define the period of FMC_CLK clock output
|
|
signal, expressed in number of KCK_FMC cycles: In
|
|
asynchronous NOR Flash, SRAM or PSRAM accesses, this
|
|
value is dont care. Note: Refer to Section20.6.5:
|
|
Synchronous transactions for FMC_CLK divider ratio
|
|
formula)</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DATLAT</name>
|
|
<description>Data latency for synchronous memory For
|
|
synchronous access with read write burst mode enabled
|
|
these bits define the number of memory clock
|
|
cycles</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ACCMOD</name>
|
|
<description>Access mode These bits specify the
|
|
asynchronous access modes as shown in the timing
|
|
diagrams. They are taken into account only when the
|
|
EXTMOD bit in the FMC_BCRx register is
|
|
1.</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR</name>
|
|
<displayName>PCR</displayName>
|
|
<description>NAND Flash control registers</description>
|
|
<addressOffset>0x80</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000018</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PWAITEN</name>
|
|
<description>Wait feature enable bit. This bit
|
|
enables the Wait feature for the NAND Flash memory
|
|
bank:</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PBKEN</name>
|
|
<description>NAND Flash memory bank enable bit. This
|
|
bit enables the memory bank. Accessing a disabled
|
|
memory bank causes an ERROR on AXI bus</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PWID</name>
|
|
<description>Data bus width. These bits define the
|
|
external memory device width.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ECCEN</name>
|
|
<description>ECC computation logic enable
|
|
bit</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCLR</name>
|
|
<description>CLE to RE delay. These bits set time
|
|
from CLE low to RE low in number of KCK_FMC clock
|
|
cycles. The time is give by the following formula:
|
|
t_clr = (TCLR + SET + 2) TKCK_FMC where TKCK_FMC is
|
|
the KCK_FMC clock period Note: Set is MEMSET or
|
|
ATTSET according to the addressed
|
|
space.</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAR</name>
|
|
<description>ALE to RE delay. These bits set time
|
|
from ALE low to RE low in number of KCK_FMC clock
|
|
cycles. Time is: t_ar = (TAR + SET + 2) TKCK_FMC
|
|
where TKCK_FMC is the FMC clock period Note: Set is
|
|
MEMSET or ATTSET according to the addressed
|
|
space.</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ECCPS</name>
|
|
<description>ECC page size. These bits define the
|
|
page size for the extended ECC:</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SR</name>
|
|
<displayName>SR</displayName>
|
|
<description>This register contains information about the
|
|
FIFO status and interrupt. The FMC features a FIFO that
|
|
is used when writing to memories to transfer up to 16
|
|
words of data.This is used to quickly write to the FIFO
|
|
and free the AXI bus for transactions to peripherals
|
|
other than the FMC, while the FMC is draining its FIFO
|
|
into the memory. One of these register bits indicates the
|
|
status of the FIFO, for ECC purposes.The ECC is
|
|
calculated while the data are written to the memory. To
|
|
read the correct ECC, the software must consequently wait
|
|
until the FIFO is empty.</description>
|
|
<addressOffset>0x84</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000040</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IRS</name>
|
|
<description>Interrupt rising edge status The flag is
|
|
set by hardware and reset by software. Note: If this
|
|
bit is written by software to 1 it will be
|
|
set.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ILS</name>
|
|
<description>Interrupt high-level status The flag is
|
|
set by hardware and reset by software.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IFS</name>
|
|
<description>Interrupt falling edge status The flag
|
|
is set by hardware and reset by software. Note: If
|
|
this bit is written by software to 1 it will be
|
|
set.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IREN</name>
|
|
<description>Interrupt rising edge detection enable
|
|
bit</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ILEN</name>
|
|
<description>Interrupt high-level detection enable
|
|
bit</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IFEN</name>
|
|
<description>Interrupt falling edge detection enable
|
|
bit</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FEMPT</name>
|
|
<description>FIFO empty. Read-only bit that provides
|
|
the status of the FIFO</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PMEM</name>
|
|
<displayName>PMEM</displayName>
|
|
<description>The FMC_PMEM read/write register contains
|
|
the timing information for NAND Flash memory bank. This
|
|
information is used to access either the common memory
|
|
space of the NAND Flash for command, address write access
|
|
and data read/write access.</description>
|
|
<addressOffset>0x88</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFCFCFCFC</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MEMSET</name>
|
|
<description>Common memory x setup time These bits
|
|
define the number of KCK_FMC (+1) clock cycles to set
|
|
up the address before the command assertion (NWE,
|
|
NOE), for NAND Flash read or write access to common
|
|
memory space:</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MEMWAIT</name>
|
|
<description>Common memory wait time These bits
|
|
define the minimum number of KCK_FMC (+1) clock
|
|
cycles to assert the command (NWE, NOE), for NAND
|
|
Flash read or write access to common memory space.
|
|
The duration of command assertion is extended if the
|
|
wait signal (NWAIT) is active (low) at the end of the
|
|
programmed value of KCK_FMC:</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MEMHOLD</name>
|
|
<description>Common memory hold time These bits
|
|
define the number of KCK_FMC clock cycles for write
|
|
accesses and KCK_FMC+1 clock cycles for read accesses
|
|
during which the address is held (and data for write
|
|
accesses) after the command is de-asserted (NWE,
|
|
NOE), for NAND Flash read or write access to common
|
|
memory space:</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MEMHIZ</name>
|
|
<description>Common memory x data bus Hi-Z time These
|
|
bits define the number of KCK_FMC clock cycles during
|
|
which the data bus is kept Hi-Z after the start of a
|
|
NAND Flash write access to common memory space. This
|
|
is only valid for write transactions:</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PATT</name>
|
|
<displayName>PATT</displayName>
|
|
<description>The FMC_PATT read/write register contains
|
|
the timing information for NAND Flash memory bank. It is
|
|
used for 8-bit accesses to the attribute memory space of
|
|
the NAND Flash for the last address write access if the
|
|
timing must differ from that of previous accesses (for
|
|
Ready/Busy management, refer to Section20.8.5: NAND Flash
|
|
prewait feature).</description>
|
|
<addressOffset>0x8C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFCFCFCFC</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ATTSET</name>
|
|
<description>Attribute memory setup time These bits
|
|
define the number of KCK_FMC (+1) clock cycles to set
|
|
up address before the command assertion (NWE, NOE),
|
|
for NAND Flash read or write access to attribute
|
|
memory space:</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ATTWAIT</name>
|
|
<description>Attribute memory wait time These bits
|
|
define the minimum number of x KCK_FMC (+1) clock
|
|
cycles to assert the command (NWE, NOE), for NAND
|
|
Flash read or write access to attribute memory space.
|
|
The duration for command assertion is extended if the
|
|
wait signal (NWAIT) is active (low) at the end of the
|
|
programmed value of KCK_FMC:</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ATTHOLD</name>
|
|
<description>Attribute memory hold time These bits
|
|
define the number of KCK_FMC clock cycles during
|
|
which the address is held (and data for write access)
|
|
after the command de-assertion (NWE, NOE), for NAND
|
|
Flash read or write access to attribute memory
|
|
space:</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ATTHIZ</name>
|
|
<description>Attribute memory data bus Hi-Z time
|
|
These bits define the number of KCK_FMC clock cycles
|
|
during which the data bus is kept in Hi-Z after the
|
|
start of a NAND Flash write access to attribute
|
|
memory space on socket. Only valid for writ
|
|
transaction:</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ECCR</name>
|
|
<displayName>ECCR</displayName>
|
|
<description>This register contain the current error
|
|
correction code value computed by the ECC computation
|
|
modules of the FMC NAND controller. When the CPU
|
|
reads/writes the data from a NAND Flash memory page at
|
|
the correct address (refer to Section20.8.6: Computation
|
|
of the error correction code (ECC) in NAND Flash memory),
|
|
the data read/written from/to the NAND Flash memory are
|
|
processed automatically by the ECC computation module.
|
|
When X bytes have been read (according to the ECCPS field
|
|
in the FMC_PCR registers), the CPU must read the computed
|
|
ECC value from the FMC_ECC registers. It then verifies if
|
|
these computed parity data are the same as the parity
|
|
value recorded in the spare area, to determine whether a
|
|
page is valid, and, to correct it otherwise. The FMC_ECCR
|
|
register should be cleared after being read by setting
|
|
the ECCEN bit to 0. To compute a new data block, the
|
|
ECCEN bit must be set to 1.</description>
|
|
<addressOffset>0x94</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ECC</name>
|
|
<description>ECC result This field contains the value
|
|
computed by the ECC computation logic. Table167
|
|
describes the contents of these bit
|
|
fields.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BWTR1</name>
|
|
<displayName>BWTR1</displayName>
|
|
<description>This register contains the control
|
|
information of each memory bank. It is used for SRAMs,
|
|
PSRAMs and NOR Flash memories. When the EXTMOD bit is set
|
|
in the FMC_BCRx register, then this register is active
|
|
for write access.</description>
|
|
<addressOffset>0x104</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0FFFFFFF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ADDSET</name>
|
|
<description>Address setup phase duration. These bits
|
|
are written by software to define the duration of the
|
|
address setup phase in KCK_FMC cycles (refer to
|
|
Figure81 to Figure93), used in asynchronous accesses:
|
|
... Note: In synchronous accesses, this value is not
|
|
used, the address setup phase is always 1 Flash clock
|
|
period duration. In muxed mode, the minimum ADDSET
|
|
value is 1.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADDHLD</name>
|
|
<description>Address-hold phase duration. These bits
|
|
are written by software to define the duration of the
|
|
address hold phase (refer to Figure81 to Figure93),
|
|
used in asynchronous multiplexed accesses: ... Note:
|
|
In synchronous NOR Flash accesses, this value is not
|
|
used, the address hold phase is always 1 Flash clock
|
|
period duration.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DATAST</name>
|
|
<description>Data-phase duration. These bits are
|
|
written by software to define the duration of the
|
|
data phase (refer to Figure81 to Figure93), used in
|
|
asynchronous SRAM, PSRAM and NOR Flash memory
|
|
accesses:</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BUSTURN</name>
|
|
<description>Bus turnaround phase duration These bits
|
|
are written by software to add a delay at the end of
|
|
a write transaction to match the minimum time between
|
|
consecutive transactions (tEHEL from ENx high to ENx
|
|
low): (BUSTRUN + 1) KCK_FMC period &#8805;
|
|
tEHELmin. The programmed bus turnaround delay is
|
|
inserted between a an asynchronous write transfer and
|
|
any other asynchronous /synchronous read or write
|
|
transfer to or from a static bank. If a read
|
|
operation is performed, the bank can be the same or a
|
|
different one, whereas it must be different in case
|
|
of write operation to the bank, except in muxed mode
|
|
or mode D. In some cases, whatever the programmed
|
|
BUSTRUN values, the bus turnaround delay is fixed as
|
|
follows: The bus turnaround delay is not inserted
|
|
between two consecutive asynchronous write transfers
|
|
to the same static memory bank except for muxed mode
|
|
and mode D. There is a bus turnaround delay of 2 FMC
|
|
clock cycle between: Two consecutive synchronous
|
|
write operations (in Burst or Single mode) to the
|
|
same bank A synchronous write transfer ((in Burst or
|
|
Single mode) and an asynchronous write or read
|
|
transfer to or from static memory bank. There is a
|
|
bus turnaround delay of 3 FMC clock cycle between:
|
|
Two consecutive synchronous write operations (in
|
|
Burst or Single mode) to different static banks. A
|
|
synchronous write transfer (in Burst or Single mode)
|
|
and a synchronous read from the same or a different
|
|
bank. ...</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ACCMOD</name>
|
|
<description>Access mode. These bits specify the
|
|
asynchronous access modes as shown in the next timing
|
|
diagrams.These bits are taken into account only when
|
|
the EXTMOD bit in the FMC_BCRx register is
|
|
1.</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BWTR2</name>
|
|
<displayName>BWTR2</displayName>
|
|
<description>This register contains the control
|
|
information of each memory bank. It is used for SRAMs,
|
|
PSRAMs and NOR Flash memories. When the EXTMOD bit is set
|
|
in the FMC_BCRx register, then this register is active
|
|
for write access.</description>
|
|
<addressOffset>0x10C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0FFFFFFF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ADDSET</name>
|
|
<description>Address setup phase duration. These bits
|
|
are written by software to define the duration of the
|
|
address setup phase in KCK_FMC cycles (refer to
|
|
Figure81 to Figure93), used in asynchronous accesses:
|
|
... Note: In synchronous accesses, this value is not
|
|
used, the address setup phase is always 1 Flash clock
|
|
period duration. In muxed mode, the minimum ADDSET
|
|
value is 1.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADDHLD</name>
|
|
<description>Address-hold phase duration. These bits
|
|
are written by software to define the duration of the
|
|
address hold phase (refer to Figure81 to Figure93),
|
|
used in asynchronous multiplexed accesses: ... Note:
|
|
In synchronous NOR Flash accesses, this value is not
|
|
used, the address hold phase is always 1 Flash clock
|
|
period duration.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DATAST</name>
|
|
<description>Data-phase duration. These bits are
|
|
written by software to define the duration of the
|
|
data phase (refer to Figure81 to Figure93), used in
|
|
asynchronous SRAM, PSRAM and NOR Flash memory
|
|
accesses:</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BUSTURN</name>
|
|
<description>Bus turnaround phase duration These bits
|
|
are written by software to add a delay at the end of
|
|
a write transaction to match the minimum time between
|
|
consecutive transactions (tEHEL from ENx high to ENx
|
|
low): (BUSTRUN + 1) KCK_FMC period &#8805;
|
|
tEHELmin. The programmed bus turnaround delay is
|
|
inserted between a an asynchronous write transfer and
|
|
any other asynchronous /synchronous read or write
|
|
transfer to or from a static bank. If a read
|
|
operation is performed, the bank can be the same or a
|
|
different one, whereas it must be different in case
|
|
of write operation to the bank, except in muxed mode
|
|
or mode D. In some cases, whatever the programmed
|
|
BUSTRUN values, the bus turnaround delay is fixed as
|
|
follows: The bus turnaround delay is not inserted
|
|
between two consecutive asynchronous write transfers
|
|
to the same static memory bank except for muxed mode
|
|
and mode D. There is a bus turnaround delay of 2 FMC
|
|
clock cycle between: Two consecutive synchronous
|
|
write operations (in Burst or Single mode) to the
|
|
same bank A synchronous write transfer ((in Burst or
|
|
Single mode) and an asynchronous write or read
|
|
transfer to or from static memory bank. There is a
|
|
bus turnaround delay of 3 FMC clock cycle between:
|
|
Two consecutive synchronous write operations (in
|
|
Burst or Single mode) to different static banks. A
|
|
synchronous write transfer (in Burst or Single mode)
|
|
and a synchronous read from the same or a different
|
|
bank. ...</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ACCMOD</name>
|
|
<description>Access mode. These bits specify the
|
|
asynchronous access modes as shown in the next timing
|
|
diagrams.These bits are taken into account only when
|
|
the EXTMOD bit in the FMC_BCRx register is
|
|
1.</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BWTR3</name>
|
|
<displayName>BWTR3</displayName>
|
|
<description>This register contains the control
|
|
information of each memory bank. It is used for SRAMs,
|
|
PSRAMs and NOR Flash memories. When the EXTMOD bit is set
|
|
in the FMC_BCRx register, then this register is active
|
|
for write access.</description>
|
|
<addressOffset>0x114</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0FFFFFFF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ADDSET</name>
|
|
<description>Address setup phase duration. These bits
|
|
are written by software to define the duration of the
|
|
address setup phase in KCK_FMC cycles (refer to
|
|
Figure81 to Figure93), used in asynchronous accesses:
|
|
... Note: In synchronous accesses, this value is not
|
|
used, the address setup phase is always 1 Flash clock
|
|
period duration. In muxed mode, the minimum ADDSET
|
|
value is 1.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADDHLD</name>
|
|
<description>Address-hold phase duration. These bits
|
|
are written by software to define the duration of the
|
|
address hold phase (refer to Figure81 to Figure93),
|
|
used in asynchronous multiplexed accesses: ... Note:
|
|
In synchronous NOR Flash accesses, this value is not
|
|
used, the address hold phase is always 1 Flash clock
|
|
period duration.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DATAST</name>
|
|
<description>Data-phase duration. These bits are
|
|
written by software to define the duration of the
|
|
data phase (refer to Figure81 to Figure93), used in
|
|
asynchronous SRAM, PSRAM and NOR Flash memory
|
|
accesses:</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BUSTURN</name>
|
|
<description>Bus turnaround phase duration These bits
|
|
are written by software to add a delay at the end of
|
|
a write transaction to match the minimum time between
|
|
consecutive transactions (tEHEL from ENx high to ENx
|
|
low): (BUSTRUN + 1) KCK_FMC period &#8805;
|
|
tEHELmin. The programmed bus turnaround delay is
|
|
inserted between a an asynchronous write transfer and
|
|
any other asynchronous /synchronous read or write
|
|
transfer to or from a static bank. If a read
|
|
operation is performed, the bank can be the same or a
|
|
different one, whereas it must be different in case
|
|
of write operation to the bank, except in muxed mode
|
|
or mode D. In some cases, whatever the programmed
|
|
BUSTRUN values, the bus turnaround delay is fixed as
|
|
follows: The bus turnaround delay is not inserted
|
|
between two consecutive asynchronous write transfers
|
|
to the same static memory bank except for muxed mode
|
|
and mode D. There is a bus turnaround delay of 2 FMC
|
|
clock cycle between: Two consecutive synchronous
|
|
write operations (in Burst or Single mode) to the
|
|
same bank A synchronous write transfer ((in Burst or
|
|
Single mode) and an asynchronous write or read
|
|
transfer to or from static memory bank. There is a
|
|
bus turnaround delay of 3 FMC clock cycle between:
|
|
Two consecutive synchronous write operations (in
|
|
Burst or Single mode) to different static banks. A
|
|
synchronous write transfer (in Burst or Single mode)
|
|
and a synchronous read from the same or a different
|
|
bank. ...</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ACCMOD</name>
|
|
<description>Access mode. These bits specify the
|
|
asynchronous access modes as shown in the next timing
|
|
diagrams.These bits are taken into account only when
|
|
the EXTMOD bit in the FMC_BCRx register is
|
|
1.</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BWTR4</name>
|
|
<displayName>BWTR4</displayName>
|
|
<description>This register contains the control
|
|
information of each memory bank. It is used for SRAMs,
|
|
PSRAMs and NOR Flash memories. When the EXTMOD bit is set
|
|
in the FMC_BCRx register, then this register is active
|
|
for write access.</description>
|
|
<addressOffset>0x11C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0FFFFFFF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ADDSET</name>
|
|
<description>Address setup phase duration. These bits
|
|
are written by software to define the duration of the
|
|
address setup phase in KCK_FMC cycles (refer to
|
|
Figure81 to Figure93), used in asynchronous accesses:
|
|
... Note: In synchronous accesses, this value is not
|
|
used, the address setup phase is always 1 Flash clock
|
|
period duration. In muxed mode, the minimum ADDSET
|
|
value is 1.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADDHLD</name>
|
|
<description>Address-hold phase duration. These bits
|
|
are written by software to define the duration of the
|
|
address hold phase (refer to Figure81 to Figure93),
|
|
used in asynchronous multiplexed accesses: ... Note:
|
|
In synchronous NOR Flash accesses, this value is not
|
|
used, the address hold phase is always 1 Flash clock
|
|
period duration.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DATAST</name>
|
|
<description>Data-phase duration. These bits are
|
|
written by software to define the duration of the
|
|
data phase (refer to Figure81 to Figure93), used in
|
|
asynchronous SRAM, PSRAM and NOR Flash memory
|
|
accesses:</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BUSTURN</name>
|
|
<description>Bus turnaround phase duration These bits
|
|
are written by software to add a delay at the end of
|
|
a write transaction to match the minimum time between
|
|
consecutive transactions (tEHEL from ENx high to ENx
|
|
low): (BUSTRUN + 1) KCK_FMC period &#8805;
|
|
tEHELmin. The programmed bus turnaround delay is
|
|
inserted between a an asynchronous write transfer and
|
|
any other asynchronous /synchronous read or write
|
|
transfer to or from a static bank. If a read
|
|
operation is performed, the bank can be the same or a
|
|
different one, whereas it must be different in case
|
|
of write operation to the bank, except in muxed mode
|
|
or mode D. In some cases, whatever the programmed
|
|
BUSTRUN values, the bus turnaround delay is fixed as
|
|
follows: The bus turnaround delay is not inserted
|
|
between two consecutive asynchronous write transfers
|
|
to the same static memory bank except for muxed mode
|
|
and mode D. There is a bus turnaround delay of 2 FMC
|
|
clock cycle between: Two consecutive synchronous
|
|
write operations (in Burst or Single mode) to the
|
|
same bank A synchronous write transfer ((in Burst or
|
|
Single mode) and an asynchronous write or read
|
|
transfer to or from static memory bank. There is a
|
|
bus turnaround delay of 3 FMC clock cycle between:
|
|
Two consecutive synchronous write operations (in
|
|
Burst or Single mode) to different static banks. A
|
|
synchronous write transfer (in Burst or Single mode)
|
|
and a synchronous read from the same or a different
|
|
bank. ...</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ACCMOD</name>
|
|
<description>Access mode. These bits specify the
|
|
asynchronous access modes as shown in the next timing
|
|
diagrams.These bits are taken into account only when
|
|
the EXTMOD bit in the FMC_BCRx register is
|
|
1.</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SDCR1</name>
|
|
<displayName>SDCR1</displayName>
|
|
<description>This register contains the control
|
|
parameters for each SDRAM memory bank</description>
|
|
<addressOffset>0x140</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x000002D0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>NC</name>
|
|
<description>Number of column address bits These bits
|
|
define the number of bits of a column
|
|
address.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NR</name>
|
|
<description>Number of row address bits These bits
|
|
define the number of bits of a row
|
|
address.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MWID</name>
|
|
<description>Memory data bus width. These bits define
|
|
the memory device width.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NB</name>
|
|
<description>Number of internal banks This bit sets
|
|
the number of internal banks.</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CAS</name>
|
|
<description>CAS Latency This bits sets the SDRAM CAS
|
|
latency in number of memory clock
|
|
cycles</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WP</name>
|
|
<description>Write protection This bit enables write
|
|
mode access to the SDRAM bank.</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SDCLK</name>
|
|
<description>SDRAM clock configuration These bits
|
|
define the SDRAM clock period for both SDRAM banks
|
|
and allow disabling the clock before changing the
|
|
frequency. In this case the SDRAM must be
|
|
re-initialized. Note: The corresponding bits in the
|
|
FMC_SDCR2 register is read only.</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RBURST</name>
|
|
<description>Burst read This bit enables burst read
|
|
mode. The SDRAM controller anticipates the next read
|
|
commands during the CAS latency and stores data in
|
|
the Read FIFO. Note: The corresponding bit in the
|
|
FMC_SDCR2 register is read only.</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RPIPE</name>
|
|
<description>Read pipe These bits define the delay,
|
|
in KCK_FMC clock cycles, for reading data after CAS
|
|
latency. Note: The corresponding bits in the
|
|
FMC_SDCR2 register is read only.</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SDCR2</name>
|
|
<displayName>SDCR2</displayName>
|
|
<description>This register contains the control
|
|
parameters for each SDRAM memory bank</description>
|
|
<addressOffset>0x144</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x000002D0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>NC</name>
|
|
<description>Number of column address bits These bits
|
|
define the number of bits of a column
|
|
address.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NR</name>
|
|
<description>Number of row address bits These bits
|
|
define the number of bits of a row
|
|
address.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MWID</name>
|
|
<description>Memory data bus width. These bits define
|
|
the memory device width.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NB</name>
|
|
<description>Number of internal banks This bit sets
|
|
the number of internal banks.</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CAS</name>
|
|
<description>CAS Latency This bits sets the SDRAM CAS
|
|
latency in number of memory clock
|
|
cycles</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WP</name>
|
|
<description>Write protection This bit enables write
|
|
mode access to the SDRAM bank.</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SDCLK</name>
|
|
<description>SDRAM clock configuration These bits
|
|
define the SDRAM clock period for both SDRAM banks
|
|
and allow disabling the clock before changing the
|
|
frequency. In this case the SDRAM must be
|
|
re-initialized. Note: The corresponding bits in the
|
|
FMC_SDCR2 register is read only.</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RBURST</name>
|
|
<description>Burst read This bit enables burst read
|
|
mode. The SDRAM controller anticipates the next read
|
|
commands during the CAS latency and stores data in
|
|
the Read FIFO. Note: The corresponding bit in the
|
|
FMC_SDCR2 register is read only.</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RPIPE</name>
|
|
<description>Read pipe These bits define the delay,
|
|
in KCK_FMC clock cycles, for reading data after CAS
|
|
latency. Note: The corresponding bits in the
|
|
FMC_SDCR2 register is read only.</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SDTR1</name>
|
|
<displayName>SDTR1</displayName>
|
|
<description>This register contains the timing parameters
|
|
of each SDRAM bank</description>
|
|
<addressOffset>0x148</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0FFFFFFF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TMRD</name>
|
|
<description>Load Mode Register to Active These bits
|
|
define the delay between a Load Mode Register command
|
|
and an Active or Refresh command in number of memory
|
|
clock cycles. ....</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TXSR</name>
|
|
<description>Exit Self-refresh delay These bits
|
|
define the delay from releasing the Self-refresh
|
|
command to issuing the Activate command in number of
|
|
memory clock cycles. .... Note: If two SDRAM devices
|
|
are used, the FMC_SDTR1 and FMC_SDTR2 must be
|
|
programmed with the same TXSR timing corresponding to
|
|
the slowest SDRAM device.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TRAS</name>
|
|
<description>Self refresh time These bits define the
|
|
minimum Self-refresh period in number of memory clock
|
|
cycles. ....</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TRC</name>
|
|
<description>Row cycle delay These bits define the
|
|
delay between the Refresh command and the Activate
|
|
command, as well as the delay between two consecutive
|
|
Refresh commands. It is expressed in number of memory
|
|
clock cycles. The TRC timing is only configured in
|
|
the FMC_SDTR1 register. If two SDRAM devices are
|
|
used, the TRC must be programmed with the timings of
|
|
the slowest device. .... Note: TRC must match the TRC
|
|
and TRFC (Auto Refresh period) timings defined in the
|
|
SDRAM device datasheet. Note: The corresponding bits
|
|
in the FMC_SDTR2 register are dont
|
|
care.</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TWR</name>
|
|
<description>Recovery delay These bits define the
|
|
delay between a Write and a Precharge command in
|
|
number of memory clock cycles. .... Note: TWR must be
|
|
programmed to match the write recovery time (tWR)
|
|
defined in the SDRAM datasheet, and to guarantee
|
|
that: TWR &#8805; TRAS - TRCD and TWR
|
|
&#8805;TRC - TRCD - TRP Example: TRAS= 4 cycles,
|
|
TRCD= 2 cycles. So, TWR &gt;= 2 cycles. TWR must
|
|
be programmed to 0x1. If two SDRAM devices are used,
|
|
the FMC_SDTR1 and FMC_SDTR2 must be programmed with
|
|
the same TWR timing corresponding to the slowest
|
|
SDRAM device.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TRP</name>
|
|
<description>Row precharge delay These bits define
|
|
the delay between a Precharge command and another
|
|
command in number of memory clock cycles. The TRP
|
|
timing is only configured in the FMC_SDTR1 register.
|
|
If two SDRAM devices are used, the TRP must be
|
|
programmed with the timing of the slowest device.
|
|
.... Note: The corresponding bits in the FMC_SDTR2
|
|
register are dont care.</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TRCD</name>
|
|
<description>Row to column delay These bits define
|
|
the delay between the Activate command and a
|
|
Read/Write command in number of memory clock cycles.
|
|
....</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SDTR2</name>
|
|
<displayName>SDTR2</displayName>
|
|
<description>This register contains the timing parameters
|
|
of each SDRAM bank</description>
|
|
<addressOffset>0x14C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0FFFFFFF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TMRD</name>
|
|
<description>Load Mode Register to Active These bits
|
|
define the delay between a Load Mode Register command
|
|
and an Active or Refresh command in number of memory
|
|
clock cycles. ....</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TXSR</name>
|
|
<description>Exit Self-refresh delay These bits
|
|
define the delay from releasing the Self-refresh
|
|
command to issuing the Activate command in number of
|
|
memory clock cycles. .... Note: If two SDRAM devices
|
|
are used, the FMC_SDTR1 and FMC_SDTR2 must be
|
|
programmed with the same TXSR timing corresponding to
|
|
the slowest SDRAM device.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TRAS</name>
|
|
<description>Self refresh time These bits define the
|
|
minimum Self-refresh period in number of memory clock
|
|
cycles. ....</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TRC</name>
|
|
<description>Row cycle delay These bits define the
|
|
delay between the Refresh command and the Activate
|
|
command, as well as the delay between two consecutive
|
|
Refresh commands. It is expressed in number of memory
|
|
clock cycles. The TRC timing is only configured in
|
|
the FMC_SDTR1 register. If two SDRAM devices are
|
|
used, the TRC must be programmed with the timings of
|
|
the slowest device. .... Note: TRC must match the TRC
|
|
and TRFC (Auto Refresh period) timings defined in the
|
|
SDRAM device datasheet. Note: The corresponding bits
|
|
in the FMC_SDTR2 register are dont
|
|
care.</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TWR</name>
|
|
<description>Recovery delay These bits define the
|
|
delay between a Write and a Precharge command in
|
|
number of memory clock cycles. .... Note: TWR must be
|
|
programmed to match the write recovery time (tWR)
|
|
defined in the SDRAM datasheet, and to guarantee
|
|
that: TWR &#8805; TRAS - TRCD and TWR
|
|
&#8805;TRC - TRCD - TRP Example: TRAS= 4 cycles,
|
|
TRCD= 2 cycles. So, TWR &gt;= 2 cycles. TWR must
|
|
be programmed to 0x1. If two SDRAM devices are used,
|
|
the FMC_SDTR1 and FMC_SDTR2 must be programmed with
|
|
the same TWR timing corresponding to the slowest
|
|
SDRAM device.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TRP</name>
|
|
<description>Row precharge delay These bits define
|
|
the delay between a Precharge command and another
|
|
command in number of memory clock cycles. The TRP
|
|
timing is only configured in the FMC_SDTR1 register.
|
|
If two SDRAM devices are used, the TRP must be
|
|
programmed with the timing of the slowest device.
|
|
.... Note: The corresponding bits in the FMC_SDTR2
|
|
register are dont care.</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TRCD</name>
|
|
<description>Row to column delay These bits define
|
|
the delay between the Activate command and a
|
|
Read/Write command in number of memory clock cycles.
|
|
....</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SDCMR</name>
|
|
<displayName>SDCMR</displayName>
|
|
<description>This register contains the command issued
|
|
when the SDRAM device is accessed. This register is used
|
|
to initialize the SDRAM device, and to activate the
|
|
Self-refresh and the Power-down modes. As soon as the
|
|
MODE field is written, the command will be issued only to
|
|
one or to both SDRAM banks according to CTB1 and CTB2
|
|
command bits. This register is the same for both SDRAM
|
|
banks.</description>
|
|
<addressOffset>0x150</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Command mode These bits define the
|
|
command issued to the SDRAM device. Note: When a
|
|
command is issued, at least one Command Target Bank
|
|
bit ( CTB1 or CTB2) must be set otherwise the command
|
|
will be ignored. Note: If two SDRAM banks are used,
|
|
the Auto-refresh and PALL command must be issued
|
|
simultaneously to the two devices with CTB1 and CTB2
|
|
bits set otherwise the command will be ignored. Note:
|
|
If only one SDRAM bank is used and a command is
|
|
issued with its associated CTB bit set, the other CTB
|
|
bit of the unused bank must be kept to
|
|
0.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTB2</name>
|
|
<description>Command Target Bank 2 This bit indicates
|
|
whether the command will be issued to SDRAM Bank 2 or
|
|
not.</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTB1</name>
|
|
<description>Command Target Bank 1 This bit indicates
|
|
whether the command will be issued to SDRAM Bank 1 or
|
|
not.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NRFS</name>
|
|
<description>Number of Auto-refresh These bits define
|
|
the number of consecutive Auto-refresh commands
|
|
issued when MODE = 011. ....</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MRD</name>
|
|
<description>Mode Register definition This 14-bit
|
|
field defines the SDRAM Mode Register content. The
|
|
Mode Register is programmed using the Load Mode
|
|
Register command. The MRD[13:0] bits are also used to
|
|
program the extended mode register for mobile
|
|
SDRAM.</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>14</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SDRTR</name>
|
|
<displayName>SDRTR</displayName>
|
|
<description>This register sets the refresh rate in
|
|
number of SDCLK clock cycles between the refresh cycles
|
|
by configuring the Refresh Timer Count value.Examplewhere
|
|
64 ms is the SDRAM refresh period.The refresh rate must
|
|
be increased by 20 SDRAM clock cycles (as in the above
|
|
example) to obtain a safe margin if an internal refresh
|
|
request occurs when a read request has been accepted. It
|
|
corresponds to a COUNT value of 0000111000000 (448). This
|
|
13-bit field is loaded into a timer which is decremented
|
|
using the SDRAM clock. This timer generates a refresh
|
|
pulse when zero is reached. The COUNT value must be set
|
|
at least to 41 SDRAM clock cycles.As soon as the
|
|
FMC_SDRTR register is programmed, the timer starts
|
|
counting. If the value programmed in the register is 0,
|
|
no refresh is carried out. This register must not be
|
|
reprogrammed after the initialization procedure to avoid
|
|
modifying the refresh rate.Each time a refresh pulse is
|
|
generated, this 13-bit COUNT field is reloaded into the
|
|
counter.If a memory access is in progress, the
|
|
Auto-refresh request is delayed. However, if the memory
|
|
access and Auto-refresh requests are generated
|
|
simultaneously, the Auto-refresh takes precedence. If the
|
|
memory access occurs during a refresh operation, the
|
|
request is buffered to be processed when the refresh is
|
|
complete.This register is common to SDRAM bank 1 and bank
|
|
2.</description>
|
|
<addressOffset>0x154</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CRE</name>
|
|
<description>Clear Refresh error flag This bit is
|
|
used to clear the Refresh Error Flag (RE) in the
|
|
Status Register.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Refresh Timer Count This 13-bit field
|
|
defines the refresh rate of the SDRAM device. It is
|
|
expressed in number of memory clock cycles. It must
|
|
be set at least to 41 SDRAM clock cycles (0x29).
|
|
Refresh rate = (COUNT + 1) x SDRAM frequency clock
|
|
COUNT = (SDRAM refresh period / Number of rows) -
|
|
20</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>13</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>REIE</name>
|
|
<description>RES Interrupt Enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SDSR</name>
|
|
<displayName>SDSR</displayName>
|
|
<description>SDRAM Status register</description>
|
|
<addressOffset>0x158</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RE</name>
|
|
<description>Refresh error flag An interrupt is
|
|
generated if REIE = 1 and RE = 1</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODES1</name>
|
|
<description>Status Mode for Bank 1 These bits define
|
|
the Status Mode of SDRAM Bank 1.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODES2</name>
|
|
<description>Status Mode for Bank 2 These bits define
|
|
the Status Mode of SDRAM Bank 2.</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>CEC</name>
|
|
<description>CEC</description>
|
|
<groupName>CEC</groupName>
|
|
<baseAddress>0x40006C00</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>CEC</name>
|
|
<description>HDMI-CEC global interrupt</description>
|
|
<value>94</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CR</name>
|
|
<displayName>CR</displayName>
|
|
<description>CEC control register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CECEN</name>
|
|
<description>CEC Enable The CECEN bit is set and
|
|
cleared by software. CECEN=1 starts message reception
|
|
and enables the TXSOM control. CECEN=0 disables the
|
|
CEC peripheral, clears all bits of CEC_CR register
|
|
and aborts any on-going reception or
|
|
transmission.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TXSOM</name>
|
|
<description>Tx Start Of Message TXSOM is set by
|
|
software to command transmission of the first byte of
|
|
a CEC message. If the CEC message consists of only
|
|
one byte, TXEOM must be set before of TXSOM.
|
|
Start-Bit is effectively started on the CEC line
|
|
after SFT is counted. If TXSOM is set while a message
|
|
reception is ongoing, transmission will start after
|
|
the end of reception. TXSOM is cleared by hardware
|
|
after the last byte of the message is sent with a
|
|
positive acknowledge (TXEND=1), in case of
|
|
transmission underrun (TXUDR=1), negative acknowledge
|
|
(TXACKE=1), and transmission error (TXERR=1). It is
|
|
also cleared by CECEN=0. It is not cleared and
|
|
transmission is automatically retried in case of
|
|
arbitration lost (ARBLST=1). TXSOM can be also used
|
|
as a status bit informing application whether any
|
|
transmission request is pending or under execution.
|
|
The application can abort a transmission request at
|
|
any time by clearing the CECEN bit. Note: TXSOM must
|
|
be set when CECEN=1 TXSOM must be set when
|
|
transmission data is available into TXDR HEADERs
|
|
first four bits containing own peripheral address are
|
|
taken from TXDR[7:4], not from CEC_CFGR.OAR which is
|
|
used only for reception</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TXEOM</name>
|
|
<description>Tx End Of Message The TXEOM bit is set
|
|
by software to command transmission of the last byte
|
|
of a CEC message. TXEOM is cleared by hardware at the
|
|
same time and under the same conditions as for TXSOM.
|
|
Note: TXEOM must be set when CECEN=1 TXEOM must be
|
|
set before writing transmission data to TXDR If TXEOM
|
|
is set when TXSOM=0, transmitted message will consist
|
|
of 1 byte (HEADER) only (PING message)</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CFGR</name>
|
|
<displayName>CFGR</displayName>
|
|
<description>This register is used to configure the
|
|
HDMI-CEC controller. It is mandatory to write CEC_CFGR
|
|
only when CECEN=0.</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SFT</name>
|
|
<description>Signal Free Time SFT bits are set by
|
|
software. In the SFT=0x0 configuration the number of
|
|
nominal data bit periods waited before transmission
|
|
is ruled by hardware according to the transmission
|
|
history. In all the other configurations the SFT
|
|
number is determined by software. * 0x0 ** 2.5
|
|
Data-Bit periods if CEC is the last bus initiator
|
|
with unsuccessful transmission (ARBLST=1, TXERR=1,
|
|
TXUDR=1 or TXACKE= 1) ** 4 Data-Bit periods if CEC is
|
|
the new bus initiator ** 6 Data-Bit periods if CEC is
|
|
the last bus initiator with successful transmission
|
|
(TXEOM=1) * 0x1: 0.5 nominal data bit periods * 0x2:
|
|
1.5 nominal data bit periods * 0x3: 2.5 nominal data
|
|
bit periods * 0x4: 3.5 nominal data bit periods *
|
|
0x5: 4.5 nominal data bit periods * 0x6: 5.5 nominal
|
|
data bit periods * 0x7: 6.5 nominal data bit
|
|
periods</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXTOL</name>
|
|
<description>Rx-Tolerance The RXTOL bit is set and
|
|
cleared by software. ** Start-Bit, +/- 200 s rise,
|
|
+/- 200 s fall. ** Data-Bit: +/- 200 s rise. +/- 350
|
|
s fall. ** Start-Bit: +/- 400 s rise, +/- 400 s fall
|
|
** Data-Bit: +/-300 s rise, +/- 500 s
|
|
fall</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BRESTP</name>
|
|
<description>Rx-Stop on Bit Rising Error The BRESTP
|
|
bit is set and cleared by software.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BREGEN</name>
|
|
<description>Generate Error-Bit on Bit Rising Error
|
|
The BREGEN bit is set and cleared by software. Note:
|
|
If BRDNOGEN=0, an Error-bit is generated upon BRE
|
|
detection with BRESTP=1 in broadcast even if
|
|
BREGEN=0</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LBPEGEN</name>
|
|
<description>Generate Error-Bit on Long Bit Period
|
|
Error The LBPEGEN bit is set and cleared by software.
|
|
Note: If BRDNOGEN=0, an Error-bit is generated upon
|
|
LBPE detection in broadcast even if
|
|
LBPEGEN=0</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BRDNOGEN</name>
|
|
<description>Avoid Error-Bit Generation in Broadcast
|
|
The BRDNOGEN bit is set and cleared by
|
|
software.</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SFTOPT</name>
|
|
<description>SFT Option Bit The SFTOPT bit is set and
|
|
cleared by software.</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OAR</name>
|
|
<description>Own addresses configuration The OAR bits
|
|
are set by software to select which destination
|
|
logical addresses has to be considered in receive
|
|
mode. Each bit, when set, enables the CEC logical
|
|
address identified by the given bit position. At the
|
|
end of HEADER reception, the received destination
|
|
address is compared with the enabled addresses. In
|
|
case of matching address, the incoming message is
|
|
acknowledged and received. In case of non-matching
|
|
address, the incoming message is received only in
|
|
listen mode (LSTN=1), but without acknowledge sent.
|
|
Broadcast messages are always received. Example: OAR
|
|
= 0b000 0000 0010 0001 means that CEC acknowledges
|
|
addresses 0x0 and 0x5. Consequently, each message
|
|
directed to one of these addresses is
|
|
received.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>15</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LSTN</name>
|
|
<description>Listen mode LSTN bit is set and cleared
|
|
by software.</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXDR</name>
|
|
<displayName>TXDR</displayName>
|
|
<description>CEC Tx data register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>0x20</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TXD</name>
|
|
<description>Tx Data register. TXD is a write-only
|
|
register containing the data byte to be transmitted.
|
|
Note: TXD must be written when
|
|
TXSTART=1</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXDR</name>
|
|
<displayName>RXDR</displayName>
|
|
<description>CEC Rx Data Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RXD</name>
|
|
<description>Rx Data register. RXD is read-only and
|
|
contains the last data byte which has been received
|
|
from the CEC line.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ISR</name>
|
|
<displayName>ISR</displayName>
|
|
<description>CEC Interrupt and Status
|
|
Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RXBR</name>
|
|
<description>Rx-Byte Received The RXBR bit is set by
|
|
hardware to inform application that a new byte has
|
|
been received from the CEC line and stored into the
|
|
RXD buffer. RXBR is cleared by software write at
|
|
1.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXEND</name>
|
|
<description>End Of Reception RXEND is set by
|
|
hardware to inform application that the last byte of
|
|
a CEC message is received from the CEC line and
|
|
stored into the RXD buffer. RXEND is set at the same
|
|
time of RXBR. RXEND is cleared by software write at
|
|
1.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXOVR</name>
|
|
<description>Rx-Overrun RXOVR is set by hardware if
|
|
RXBR is not yet cleared at the time a new byte is
|
|
received on the CEC line and stored into RXD. RXOVR
|
|
assertion stops message reception so that no
|
|
acknowledge is sent. In case of broadcast, a negative
|
|
acknowledge is sent. RXOVR is cleared by software
|
|
write at 1.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BRE</name>
|
|
<description>Rx-Bit Rising Error BRE is set by
|
|
hardware in case a Data-Bit waveform is detected with
|
|
Bit Rising Error. BRE is set either at the time the
|
|
misplaced rising edge occurs, or at the end of the
|
|
maximum BRE tolerance allowed by RXTOL, in case
|
|
rising edge is still longing. BRE stops message
|
|
reception if BRESTP=1. BRE generates an Error-Bit on
|
|
the CEC line if BREGEN=1. BRE is cleared by software
|
|
write at 1.</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SBPE</name>
|
|
<description>Rx-Short Bit Period Error SBPE is set by
|
|
hardware in case a Data-Bit waveform is detected with
|
|
Short Bit Period Error. SBPE is set at the time the
|
|
anticipated falling edge occurs. SBPE generates an
|
|
Error-Bit on the CEC line. SBPE is cleared by
|
|
software write at 1.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LBPE</name>
|
|
<description>Rx-Long Bit Period Error LBPE is set by
|
|
hardware in case a Data-Bit waveform is detected with
|
|
Long Bit Period Error. LBPE is set at the end of the
|
|
maximum bit-extension tolerance allowed by RXTOL, in
|
|
case falling edge is still longing. LBPE always stops
|
|
reception of the CEC message. LBPE generates an
|
|
Error-Bit on the CEC line if LBPEGEN=1. In case of
|
|
broadcast, Error-Bit is generated even in case of
|
|
LBPEGEN=0. LBPE is cleared by software write at
|
|
1.</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXACKE</name>
|
|
<description>Rx-Missing Acknowledge In receive mode,
|
|
RXACKE is set by hardware to inform application that
|
|
no acknowledge was seen on the CEC line. RXACKE
|
|
applies only for broadcast messages and in listen
|
|
mode also for not directly addressed messages
|
|
(destination address not enabled in OAR). RXACKE
|
|
aborts message reception. RXACKE is cleared by
|
|
software write at 1.</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ARBLST</name>
|
|
<description>Arbitration Lost ARBLST is set by
|
|
hardware to inform application that CEC device is
|
|
switching to reception due to arbitration lost event
|
|
following the TXSOM command. ARBLST can be due either
|
|
to a contending CEC device starting earlier or
|
|
starting at the same time but with higher HEADER
|
|
priority. After ARBLST assertion TXSOM bit keeps
|
|
pending for next transmission attempt. ARBLST is
|
|
cleared by software write at 1.</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TXBR</name>
|
|
<description>Tx-Byte Request TXBR is set by hardware
|
|
to inform application that the next transmission data
|
|
has to be written to TXDR. TXBR is set when the 4th
|
|
bit of currently transmitted byte is sent.
|
|
Application must write the next byte to TXDR within 6
|
|
nominal data-bit periods before transmission underrun
|
|
error occurs (TXUDR). TXBR is cleared by software
|
|
write at 1.</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TXEND</name>
|
|
<description>End of Transmission TXEND is set by
|
|
hardware to inform application that the last byte of
|
|
the CEC message has been successfully transmitted.
|
|
TXEND clears the TXSOM and TXEOM control bits. TXEND
|
|
is cleared by software write at 1.</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TXUDR</name>
|
|
<description>Tx-Buffer Underrun In transmission mode,
|
|
TXUDR is set by hardware if application was not in
|
|
time to load TXDR before of next byte transmission.
|
|
TXUDR aborts message transmission and clears TXSOM
|
|
and TXEOM control bits. TXUDR is cleared by software
|
|
write at 1</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TXERR</name>
|
|
<description>Tx-Error In transmission mode, TXERR is
|
|
set by hardware if the CEC initiator detects low
|
|
impedance on the CEC line while it is released. TXERR
|
|
aborts message transmission and clears TXSOM and
|
|
TXEOM controls. TXERR is cleared by software write at
|
|
1.</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TXACKE</name>
|
|
<description>Tx-Missing Acknowledge Error In
|
|
transmission mode, TXACKE is set by hardware to
|
|
inform application that no acknowledge was received.
|
|
In case of broadcast transmission, TXACKE informs
|
|
application that a negative acknowledge was received.
|
|
TXACKE aborts message transmission and clears TXSOM
|
|
and TXEOM controls. TXACKE is cleared by software
|
|
write at 1.</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IER</name>
|
|
<displayName>IER</displayName>
|
|
<description>CEC interrupt enable register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RXBRIE</name>
|
|
<description>Rx-Byte Received Interrupt Enable The
|
|
RXBRIE bit is set and cleared by
|
|
software.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXENDIE</name>
|
|
<description>End Of Reception Interrupt Enable The
|
|
RXENDIE bit is set and cleared by
|
|
software.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXOVRIE</name>
|
|
<description>Rx-Buffer Overrun Interrupt Enable The
|
|
RXOVRIE bit is set and cleared by
|
|
software.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BREIE</name>
|
|
<description>Bit Rising Error Interrupt Enable The
|
|
BREIE bit is set and cleared by
|
|
software.</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SBPEIE</name>
|
|
<description>Short Bit Period Error Interrupt Enable
|
|
The SBPEIE bit is set and cleared by
|
|
software.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LBPEIE</name>
|
|
<description>Long Bit Period Error Interrupt Enable
|
|
The LBPEIE bit is set and cleared by
|
|
software.</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXACKIE</name>
|
|
<description>Rx-Missing Acknowledge Error Interrupt
|
|
Enable The RXACKIE bit is set and cleared by
|
|
software.</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ARBLSTIE</name>
|
|
<description>Arbitration Lost Interrupt Enable The
|
|
ARBLSTIE bit is set and cleared by
|
|
software.</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TXBRIE</name>
|
|
<description>Tx-Byte Request Interrupt Enable The
|
|
TXBRIE bit is set and cleared by
|
|
software.</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TXENDIE</name>
|
|
<description>Tx-End Of Message Interrupt Enable The
|
|
TXENDIE bit is set and cleared by
|
|
software.</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TXUDRIE</name>
|
|
<description>Tx-Underrun Interrupt Enable The TXUDRIE
|
|
bit is set and cleared by software.</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TXERRIE</name>
|
|
<description>Tx-Error Interrupt Enable The TXERRIE
|
|
bit is set and cleared by software.</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TXACKIE</name>
|
|
<description>Tx-Missing Acknowledge Error Interrupt
|
|
Enable The TXACKEIE bit is set and cleared by
|
|
software.</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>HSEM</name>
|
|
<description>HSEM</description>
|
|
<groupName>HSEM</groupName>
|
|
<baseAddress>0x58026400</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>HSEM0</name>
|
|
<description>HSEM global interrupt 1</description>
|
|
<value>125</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>HSEM_R0</name>
|
|
<displayName>HSEM_R0</displayName>
|
|
<description>HSEM register HSEM_R0 HSEM_R31</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PROCID</name>
|
|
<description>Semaphore ProcessID</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MASTERID</name>
|
|
<description>Semaphore MasterID</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>Lock indication</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HSEM_R1</name>
|
|
<displayName>HSEM_R1</displayName>
|
|
<description>HSEM register HSEM_R0 HSEM_R31</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PROCID</name>
|
|
<description>Semaphore ProcessID</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MASTERID</name>
|
|
<description>Semaphore MasterID</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>Lock indication</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HSEM_R2</name>
|
|
<displayName>HSEM_R2</displayName>
|
|
<description>HSEM register HSEM_R0 HSEM_R31</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PROCID</name>
|
|
<description>Semaphore ProcessID</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MASTERID</name>
|
|
<description>Semaphore MasterID</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>Lock indication</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HSEM_R3</name>
|
|
<displayName>HSEM_R3</displayName>
|
|
<description>HSEM register HSEM_R0 HSEM_R31</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PROCID</name>
|
|
<description>Semaphore ProcessID</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MASTERID</name>
|
|
<description>Semaphore MasterID</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>Lock indication</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HSEM_R4</name>
|
|
<displayName>HSEM_R4</displayName>
|
|
<description>HSEM register HSEM_R0 HSEM_R31</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PROCID</name>
|
|
<description>Semaphore ProcessID</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MASTERID</name>
|
|
<description>Semaphore MasterID</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>Lock indication</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HSEM_R5</name>
|
|
<displayName>HSEM_R5</displayName>
|
|
<description>HSEM register HSEM_R0 HSEM_R31</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PROCID</name>
|
|
<description>Semaphore ProcessID</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MASTERID</name>
|
|
<description>Semaphore MasterID</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>Lock indication</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HSEM_R6</name>
|
|
<displayName>HSEM_R6</displayName>
|
|
<description>HSEM register HSEM_R0 HSEM_R31</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PROCID</name>
|
|
<description>Semaphore ProcessID</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MASTERID</name>
|
|
<description>Semaphore MasterID</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>Lock indication</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HSEM_R7</name>
|
|
<displayName>HSEM_R7</displayName>
|
|
<description>HSEM register HSEM_R0 HSEM_R31</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PROCID</name>
|
|
<description>Semaphore ProcessID</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MASTERID</name>
|
|
<description>Semaphore MasterID</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>Lock indication</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HSEM_R8</name>
|
|
<displayName>HSEM_R8</displayName>
|
|
<description>HSEM register HSEM_R0 HSEM_R31</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PROCID</name>
|
|
<description>Semaphore ProcessID</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MASTERID</name>
|
|
<description>Semaphore MasterID</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>Lock indication</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HSEM_R9</name>
|
|
<displayName>HSEM_R9</displayName>
|
|
<description>HSEM register HSEM_R0 HSEM_R31</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PROCID</name>
|
|
<description>Semaphore ProcessID</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MASTERID</name>
|
|
<description>Semaphore MasterID</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>Lock indication</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HSEM_R10</name>
|
|
<displayName>HSEM_R10</displayName>
|
|
<description>HSEM register HSEM_R0 HSEM_R31</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PROCID</name>
|
|
<description>Semaphore ProcessID</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MASTERID</name>
|
|
<description>Semaphore MasterID</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>Lock indication</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HSEM_R11</name>
|
|
<displayName>HSEM_R11</displayName>
|
|
<description>HSEM register HSEM_R0 HSEM_R31</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PROCID</name>
|
|
<description>Semaphore ProcessID</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MASTERID</name>
|
|
<description>Semaphore MasterID</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>Lock indication</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HSEM_R12</name>
|
|
<displayName>HSEM_R12</displayName>
|
|
<description>HSEM register HSEM_R0 HSEM_R31</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PROCID</name>
|
|
<description>Semaphore ProcessID</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MASTERID</name>
|
|
<description>Semaphore MasterID</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>Lock indication</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HSEM_R13</name>
|
|
<displayName>HSEM_R13</displayName>
|
|
<description>HSEM register HSEM_R0 HSEM_R31</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PROCID</name>
|
|
<description>Semaphore ProcessID</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MASTERID</name>
|
|
<description>Semaphore MasterID</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>Lock indication</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HSEM_R14</name>
|
|
<displayName>HSEM_R14</displayName>
|
|
<description>HSEM register HSEM_R0 HSEM_R31</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PROCID</name>
|
|
<description>Semaphore ProcessID</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MASTERID</name>
|
|
<description>Semaphore MasterID</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>Lock indication</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HSEM_R15</name>
|
|
<displayName>HSEM_R15</displayName>
|
|
<description>HSEM register HSEM_R0 HSEM_R31</description>
|
|
<addressOffset>0x3C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PROCID</name>
|
|
<description>Semaphore ProcessID</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MASTERID</name>
|
|
<description>Semaphore MasterID</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>Lock indication</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HSEM_R16</name>
|
|
<displayName>HSEM_R16</displayName>
|
|
<description>HSEM register HSEM_R0 HSEM_R31</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PROCID</name>
|
|
<description>Semaphore ProcessID</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MASTERID</name>
|
|
<description>Semaphore MasterID</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>Lock indication</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HSEM_R17</name>
|
|
<displayName>HSEM_R17</displayName>
|
|
<description>HSEM register HSEM_R0 HSEM_R31</description>
|
|
<addressOffset>0x44</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PROCID</name>
|
|
<description>Semaphore ProcessID</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MASTERID</name>
|
|
<description>Semaphore MasterID</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>Lock indication</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HSEM_R18</name>
|
|
<displayName>HSEM_R18</displayName>
|
|
<description>HSEM register HSEM_R0 HSEM_R31</description>
|
|
<addressOffset>0x48</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PROCID</name>
|
|
<description>Semaphore ProcessID</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MASTERID</name>
|
|
<description>Semaphore MasterID</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>Lock indication</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HSEM_R19</name>
|
|
<displayName>HSEM_R19</displayName>
|
|
<description>HSEM register HSEM_R0 HSEM_R31</description>
|
|
<addressOffset>0x4C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PROCID</name>
|
|
<description>Semaphore ProcessID</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MASTERID</name>
|
|
<description>Semaphore MasterID</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>Lock indication</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HSEM_R20</name>
|
|
<displayName>HSEM_R20</displayName>
|
|
<description>HSEM register HSEM_R0 HSEM_R31</description>
|
|
<addressOffset>0x50</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PROCID</name>
|
|
<description>Semaphore ProcessID</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MASTERID</name>
|
|
<description>Semaphore MasterID</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>Lock indication</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HSEM_R21</name>
|
|
<displayName>HSEM_R21</displayName>
|
|
<description>HSEM register HSEM_R0 HSEM_R31</description>
|
|
<addressOffset>0x54</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PROCID</name>
|
|
<description>Semaphore ProcessID</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MASTERID</name>
|
|
<description>Semaphore MasterID</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>Lock indication</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HSEM_R22</name>
|
|
<displayName>HSEM_R22</displayName>
|
|
<description>HSEM register HSEM_R0 HSEM_R31</description>
|
|
<addressOffset>0x58</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PROCID</name>
|
|
<description>Semaphore ProcessID</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MASTERID</name>
|
|
<description>Semaphore MasterID</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>Lock indication</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HSEM_R23</name>
|
|
<displayName>HSEM_R23</displayName>
|
|
<description>HSEM register HSEM_R0 HSEM_R31</description>
|
|
<addressOffset>0x5C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PROCID</name>
|
|
<description>Semaphore ProcessID</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MASTERID</name>
|
|
<description>Semaphore MasterID</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>Lock indication</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HSEM_R24</name>
|
|
<displayName>HSEM_R24</displayName>
|
|
<description>HSEM register HSEM_R0 HSEM_R31</description>
|
|
<addressOffset>0x60</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PROCID</name>
|
|
<description>Semaphore ProcessID</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MASTERID</name>
|
|
<description>Semaphore MasterID</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>Lock indication</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HSEM_R25</name>
|
|
<displayName>HSEM_R25</displayName>
|
|
<description>HSEM register HSEM_R0 HSEM_R31</description>
|
|
<addressOffset>0x64</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PROCID</name>
|
|
<description>Semaphore ProcessID</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MASTERID</name>
|
|
<description>Semaphore MasterID</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>Lock indication</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HSEM_R26</name>
|
|
<displayName>HSEM_R26</displayName>
|
|
<description>HSEM register HSEM_R0 HSEM_R31</description>
|
|
<addressOffset>0x68</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PROCID</name>
|
|
<description>Semaphore ProcessID</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MASTERID</name>
|
|
<description>Semaphore MasterID</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>Lock indication</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HSEM_R27</name>
|
|
<displayName>HSEM_R27</displayName>
|
|
<description>HSEM register HSEM_R0 HSEM_R31</description>
|
|
<addressOffset>0x6C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PROCID</name>
|
|
<description>Semaphore ProcessID</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MASTERID</name>
|
|
<description>Semaphore MasterID</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>Lock indication</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HSEM_R28</name>
|
|
<displayName>HSEM_R28</displayName>
|
|
<description>HSEM register HSEM_R0 HSEM_R31</description>
|
|
<addressOffset>0x70</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PROCID</name>
|
|
<description>Semaphore ProcessID</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MASTERID</name>
|
|
<description>Semaphore MasterID</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>Lock indication</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HSEM_R29</name>
|
|
<displayName>HSEM_R29</displayName>
|
|
<description>HSEM register HSEM_R0 HSEM_R31</description>
|
|
<addressOffset>0x74</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PROCID</name>
|
|
<description>Semaphore ProcessID</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MASTERID</name>
|
|
<description>Semaphore MasterID</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>Lock indication</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HSEM_R30</name>
|
|
<displayName>HSEM_R30</displayName>
|
|
<description>HSEM register HSEM_R0 HSEM_R31</description>
|
|
<addressOffset>0x78</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PROCID</name>
|
|
<description>Semaphore ProcessID</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MASTERID</name>
|
|
<description>Semaphore MasterID</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>Lock indication</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HSEM_R31</name>
|
|
<displayName>HSEM_R31</displayName>
|
|
<description>HSEM register HSEM_R0 HSEM_R31</description>
|
|
<addressOffset>0x7C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PROCID</name>
|
|
<description>Semaphore ProcessID</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MASTERID</name>
|
|
<description>Semaphore MasterID</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>Lock indication</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HSEM_RLR0</name>
|
|
<displayName>HSEM_RLR0</displayName>
|
|
<description>HSEM Read lock register</description>
|
|
<addressOffset>0x80</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PROCID</name>
|
|
<description>Semaphore ProcessID</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MASTERID</name>
|
|
<description>Semaphore MasterID</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>Lock indication</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HSEM_RLR1</name>
|
|
<displayName>HSEM_RLR1</displayName>
|
|
<description>HSEM Read lock register</description>
|
|
<addressOffset>0x84</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PROCID</name>
|
|
<description>Semaphore ProcessID</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MASTERID</name>
|
|
<description>Semaphore MasterID</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>Lock indication</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HSEM_RLR2</name>
|
|
<displayName>HSEM_RLR2</displayName>
|
|
<description>HSEM Read lock register</description>
|
|
<addressOffset>0x88</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PROCID</name>
|
|
<description>Semaphore ProcessID</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MASTERID</name>
|
|
<description>Semaphore MasterID</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>Lock indication</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HSEM_RLR3</name>
|
|
<displayName>HSEM_RLR3</displayName>
|
|
<description>HSEM Read lock register</description>
|
|
<addressOffset>0x8C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PROCID</name>
|
|
<description>Semaphore ProcessID</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MASTERID</name>
|
|
<description>Semaphore MasterID</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>Lock indication</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HSEM_RLR4</name>
|
|
<displayName>HSEM_RLR4</displayName>
|
|
<description>HSEM Read lock register</description>
|
|
<addressOffset>0x90</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PROCID</name>
|
|
<description>Semaphore ProcessID</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MASTERID</name>
|
|
<description>Semaphore MasterID</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>Lock indication</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HSEM_RLR5</name>
|
|
<displayName>HSEM_RLR5</displayName>
|
|
<description>HSEM Read lock register</description>
|
|
<addressOffset>0x94</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PROCID</name>
|
|
<description>Semaphore ProcessID</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MASTERID</name>
|
|
<description>Semaphore MasterID</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>Lock indication</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HSEM_RLR6</name>
|
|
<displayName>HSEM_RLR6</displayName>
|
|
<description>HSEM Read lock register</description>
|
|
<addressOffset>0x98</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PROCID</name>
|
|
<description>Semaphore ProcessID</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MASTERID</name>
|
|
<description>Semaphore MasterID</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>Lock indication</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HSEM_RLR7</name>
|
|
<displayName>HSEM_RLR7</displayName>
|
|
<description>HSEM Read lock register</description>
|
|
<addressOffset>0x9C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PROCID</name>
|
|
<description>Semaphore ProcessID</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MASTERID</name>
|
|
<description>Semaphore MasterID</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>Lock indication</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HSEM_RLR8</name>
|
|
<displayName>HSEM_RLR8</displayName>
|
|
<description>HSEM Read lock register</description>
|
|
<addressOffset>0xA0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PROCID</name>
|
|
<description>Semaphore ProcessID</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MASTERID</name>
|
|
<description>Semaphore MasterID</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>Lock indication</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HSEM_RLR9</name>
|
|
<displayName>HSEM_RLR9</displayName>
|
|
<description>HSEM Read lock register</description>
|
|
<addressOffset>0xA4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PROCID</name>
|
|
<description>Semaphore ProcessID</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MASTERID</name>
|
|
<description>Semaphore MasterID</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>Lock indication</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HSEM_RLR10</name>
|
|
<displayName>HSEM_RLR10</displayName>
|
|
<description>HSEM Read lock register</description>
|
|
<addressOffset>0xA8</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PROCID</name>
|
|
<description>Semaphore ProcessID</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MASTERID</name>
|
|
<description>Semaphore MasterID</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>Lock indication</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HSEM_RLR11</name>
|
|
<displayName>HSEM_RLR11</displayName>
|
|
<description>HSEM Read lock register</description>
|
|
<addressOffset>0xAC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PROCID</name>
|
|
<description>Semaphore ProcessID</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MASTERID</name>
|
|
<description>Semaphore MasterID</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>Lock indication</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HSEM_RLR12</name>
|
|
<displayName>HSEM_RLR12</displayName>
|
|
<description>HSEM Read lock register</description>
|
|
<addressOffset>0xB0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PROCID</name>
|
|
<description>Semaphore ProcessID</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MASTERID</name>
|
|
<description>Semaphore MasterID</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>Lock indication</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HSEM_RLR13</name>
|
|
<displayName>HSEM_RLR13</displayName>
|
|
<description>HSEM Read lock register</description>
|
|
<addressOffset>0xB4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PROCID</name>
|
|
<description>Semaphore ProcessID</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MASTERID</name>
|
|
<description>Semaphore MasterID</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>Lock indication</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HSEM_RLR14</name>
|
|
<displayName>HSEM_RLR14</displayName>
|
|
<description>HSEM Read lock register</description>
|
|
<addressOffset>0xB8</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PROCID</name>
|
|
<description>Semaphore ProcessID</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MASTERID</name>
|
|
<description>Semaphore MasterID</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>Lock indication</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HSEM_RLR15</name>
|
|
<displayName>HSEM_RLR15</displayName>
|
|
<description>HSEM Read lock register</description>
|
|
<addressOffset>0xBC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PROCID</name>
|
|
<description>Semaphore ProcessID</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MASTERID</name>
|
|
<description>Semaphore MasterID</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>Lock indication</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HSEM_RLR16</name>
|
|
<displayName>HSEM_RLR16</displayName>
|
|
<description>HSEM Read lock register</description>
|
|
<addressOffset>0xC0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PROCID</name>
|
|
<description>Semaphore ProcessID</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MASTERID</name>
|
|
<description>Semaphore MasterID</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>Lock indication</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HSEM_RLR17</name>
|
|
<displayName>HSEM_RLR17</displayName>
|
|
<description>HSEM Read lock register</description>
|
|
<addressOffset>0xC4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PROCID</name>
|
|
<description>Semaphore ProcessID</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MASTERID</name>
|
|
<description>Semaphore MasterID</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>Lock indication</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HSEM_RLR18</name>
|
|
<displayName>HSEM_RLR18</displayName>
|
|
<description>HSEM Read lock register</description>
|
|
<addressOffset>0xC8</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PROCID</name>
|
|
<description>Semaphore ProcessID</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MASTERID</name>
|
|
<description>Semaphore MasterID</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>Lock indication</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HSEM_RLR19</name>
|
|
<displayName>HSEM_RLR19</displayName>
|
|
<description>HSEM Read lock register</description>
|
|
<addressOffset>0xCC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PROCID</name>
|
|
<description>Semaphore ProcessID</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MASTERID</name>
|
|
<description>Semaphore MasterID</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>Lock indication</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HSEM_RLR20</name>
|
|
<displayName>HSEM_RLR20</displayName>
|
|
<description>HSEM Read lock register</description>
|
|
<addressOffset>0xD0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PROCID</name>
|
|
<description>Semaphore ProcessID</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MASTERID</name>
|
|
<description>Semaphore MasterID</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>Lock indication</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HSEM_RLR21</name>
|
|
<displayName>HSEM_RLR21</displayName>
|
|
<description>HSEM Read lock register</description>
|
|
<addressOffset>0xD4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PROCID</name>
|
|
<description>Semaphore ProcessID</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MASTERID</name>
|
|
<description>Semaphore MasterID</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>Lock indication</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HSEM_RLR22</name>
|
|
<displayName>HSEM_RLR22</displayName>
|
|
<description>HSEM Read lock register</description>
|
|
<addressOffset>0xD8</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PROCID</name>
|
|
<description>Semaphore ProcessID</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MASTERID</name>
|
|
<description>Semaphore MasterID</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>Lock indication</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HSEM_RLR23</name>
|
|
<displayName>HSEM_RLR23</displayName>
|
|
<description>HSEM Read lock register</description>
|
|
<addressOffset>0xDC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PROCID</name>
|
|
<description>Semaphore ProcessID</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MASTERID</name>
|
|
<description>Semaphore MasterID</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>Lock indication</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HSEM_RLR24</name>
|
|
<displayName>HSEM_RLR24</displayName>
|
|
<description>HSEM Read lock register</description>
|
|
<addressOffset>0xE0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PROCID</name>
|
|
<description>Semaphore ProcessID</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MASTERID</name>
|
|
<description>Semaphore MasterID</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>Lock indication</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HSEM_RLR25</name>
|
|
<displayName>HSEM_RLR25</displayName>
|
|
<description>HSEM Read lock register</description>
|
|
<addressOffset>0xE4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PROCID</name>
|
|
<description>Semaphore ProcessID</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MASTERID</name>
|
|
<description>Semaphore MasterID</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>Lock indication</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HSEM_RLR26</name>
|
|
<displayName>HSEM_RLR26</displayName>
|
|
<description>HSEM Read lock register</description>
|
|
<addressOffset>0xE8</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PROCID</name>
|
|
<description>Semaphore ProcessID</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MASTERID</name>
|
|
<description>Semaphore MasterID</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>Lock indication</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HSEM_RLR27</name>
|
|
<displayName>HSEM_RLR27</displayName>
|
|
<description>HSEM Read lock register</description>
|
|
<addressOffset>0xEC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PROCID</name>
|
|
<description>Semaphore ProcessID</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MASTERID</name>
|
|
<description>Semaphore MasterID</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>Lock indication</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HSEM_RLR28</name>
|
|
<displayName>HSEM_RLR28</displayName>
|
|
<description>HSEM Read lock register</description>
|
|
<addressOffset>0xF0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PROCID</name>
|
|
<description>Semaphore ProcessID</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MASTERID</name>
|
|
<description>Semaphore MasterID</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>Lock indication</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HSEM_RLR29</name>
|
|
<displayName>HSEM_RLR29</displayName>
|
|
<description>HSEM Read lock register</description>
|
|
<addressOffset>0xF4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PROCID</name>
|
|
<description>Semaphore ProcessID</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MASTERID</name>
|
|
<description>Semaphore MasterID</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>Lock indication</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HSEM_RLR30</name>
|
|
<displayName>HSEM_RLR30</displayName>
|
|
<description>HSEM Read lock register</description>
|
|
<addressOffset>0xF8</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PROCID</name>
|
|
<description>Semaphore ProcessID</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MASTERID</name>
|
|
<description>Semaphore MasterID</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>Lock indication</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HSEM_RLR31</name>
|
|
<displayName>HSEM_RLR31</displayName>
|
|
<description>HSEM Read lock register</description>
|
|
<addressOffset>0xFC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PROCID</name>
|
|
<description>Semaphore ProcessID</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MASTERID</name>
|
|
<description>Semaphore MasterID</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>Lock indication</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HSEM_IER</name>
|
|
<displayName>HSEM_IER</displayName>
|
|
<description>HSEM Interrupt enable register</description>
|
|
<addressOffset>0x100</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ISEM0</name>
|
|
<description>Interrupt semaphore n enable
|
|
bit</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM1</name>
|
|
<description>Interrupt semaphore n enable
|
|
bit</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM2</name>
|
|
<description>Interrupt semaphore n enable
|
|
bit</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM3</name>
|
|
<description>Interrupt semaphore n enable
|
|
bit</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM4</name>
|
|
<description>Interrupt semaphore n enable
|
|
bit</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM5</name>
|
|
<description>Interrupt semaphore n enable
|
|
bit</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM6</name>
|
|
<description>Interrupt semaphore n enable
|
|
bit</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM7</name>
|
|
<description>Interrupt semaphore n enable
|
|
bit</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM8</name>
|
|
<description>Interrupt semaphore n enable
|
|
bit</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM9</name>
|
|
<description>Interrupt semaphore n enable
|
|
bit</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM10</name>
|
|
<description>Interrupt semaphore n enable
|
|
bit</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM11</name>
|
|
<description>Interrupt semaphore n enable
|
|
bit</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM12</name>
|
|
<description>Interrupt semaphore n enable
|
|
bit</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM13</name>
|
|
<description>Interrupt semaphore n enable
|
|
bit</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM14</name>
|
|
<description>Interrupt semaphore n enable
|
|
bit</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM15</name>
|
|
<description>Interrupt semaphore n enable
|
|
bit</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM16</name>
|
|
<description>Interrupt semaphore n enable
|
|
bit</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM17</name>
|
|
<description>Interrupt semaphore n enable
|
|
bit</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM18</name>
|
|
<description>Interrupt semaphore n enable
|
|
bit</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM19</name>
|
|
<description>Interrupt semaphore n enable
|
|
bit</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM20</name>
|
|
<description>Interrupt semaphore n enable
|
|
bit</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM21</name>
|
|
<description>Interrupt semaphore n enable
|
|
bit</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM22</name>
|
|
<description>Interrupt semaphore n enable
|
|
bit</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM23</name>
|
|
<description>Interrupt semaphore n enable
|
|
bit</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM24</name>
|
|
<description>Interrupt semaphore n enable
|
|
bit</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM25</name>
|
|
<description>Interrupt semaphore n enable
|
|
bit</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM26</name>
|
|
<description>Interrupt semaphore n enable
|
|
bit</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM27</name>
|
|
<description>Interrupt semaphore n enable
|
|
bit</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM28</name>
|
|
<description>Interrupt semaphore n enable
|
|
bit</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM29</name>
|
|
<description>Interrupt semaphore n enable
|
|
bit</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM30</name>
|
|
<description>Interrupt semaphore n enable
|
|
bit</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM31</name>
|
|
<description>Interrupt(N) semaphore n enable
|
|
bit.</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HSEM_ICR</name>
|
|
<displayName>HSEM_ICR</displayName>
|
|
<description>HSEM Interrupt clear register</description>
|
|
<addressOffset>0x104</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ISEM0</name>
|
|
<description>Interrupt(N) semaphore n clear
|
|
bit</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM1</name>
|
|
<description>Interrupt(N) semaphore n clear
|
|
bit</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM2</name>
|
|
<description>Interrupt(N) semaphore n clear
|
|
bit</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM3</name>
|
|
<description>Interrupt(N) semaphore n clear
|
|
bit</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM4</name>
|
|
<description>Interrupt(N) semaphore n clear
|
|
bit</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM5</name>
|
|
<description>Interrupt(N) semaphore n clear
|
|
bit</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM6</name>
|
|
<description>Interrupt(N) semaphore n clear
|
|
bit</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM7</name>
|
|
<description>Interrupt(N) semaphore n clear
|
|
bit</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM8</name>
|
|
<description>Interrupt(N) semaphore n clear
|
|
bit</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM9</name>
|
|
<description>Interrupt(N) semaphore n clear
|
|
bit</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM10</name>
|
|
<description>Interrupt(N) semaphore n clear
|
|
bit</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM11</name>
|
|
<description>Interrupt(N) semaphore n clear
|
|
bit</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM12</name>
|
|
<description>Interrupt(N) semaphore n clear
|
|
bit</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM13</name>
|
|
<description>Interrupt(N) semaphore n clear
|
|
bit</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM14</name>
|
|
<description>Interrupt(N) semaphore n clear
|
|
bit</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM15</name>
|
|
<description>Interrupt(N) semaphore n clear
|
|
bit</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM16</name>
|
|
<description>Interrupt(N) semaphore n clear
|
|
bit</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM17</name>
|
|
<description>Interrupt(N) semaphore n clear
|
|
bit</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM18</name>
|
|
<description>Interrupt(N) semaphore n clear
|
|
bit</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM19</name>
|
|
<description>Interrupt(N) semaphore n clear
|
|
bit</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM20</name>
|
|
<description>Interrupt(N) semaphore n clear
|
|
bit</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM21</name>
|
|
<description>Interrupt(N) semaphore n clear
|
|
bit</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM22</name>
|
|
<description>Interrupt(N) semaphore n clear
|
|
bit</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM23</name>
|
|
<description>Interrupt(N) semaphore n clear
|
|
bit</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM24</name>
|
|
<description>Interrupt(N) semaphore n clear
|
|
bit</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM25</name>
|
|
<description>Interrupt(N) semaphore n clear
|
|
bit</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM26</name>
|
|
<description>Interrupt(N) semaphore n clear
|
|
bit</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM27</name>
|
|
<description>Interrupt(N) semaphore n clear
|
|
bit</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM28</name>
|
|
<description>Interrupt(N) semaphore n clear
|
|
bit</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM29</name>
|
|
<description>Interrupt(N) semaphore n clear
|
|
bit</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM30</name>
|
|
<description>Interrupt(N) semaphore n clear
|
|
bit</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM31</name>
|
|
<description>Interrupt(N) semaphore n clear
|
|
bit</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HSEM_ISR</name>
|
|
<displayName>HSEM_ISR</displayName>
|
|
<description>HSEM Interrupt status register</description>
|
|
<addressOffset>0x108</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ISEM0</name>
|
|
<description>Interrupt(N) semaphore n status bit
|
|
before enable (mask)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM1</name>
|
|
<description>Interrupt(N) semaphore n status bit
|
|
before enable (mask)</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM2</name>
|
|
<description>Interrupt(N) semaphore n status bit
|
|
before enable (mask)</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM3</name>
|
|
<description>Interrupt(N) semaphore n status bit
|
|
before enable (mask)</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM4</name>
|
|
<description>Interrupt(N) semaphore n status bit
|
|
before enable (mask)</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM5</name>
|
|
<description>Interrupt(N) semaphore n status bit
|
|
before enable (mask)</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM6</name>
|
|
<description>Interrupt(N) semaphore n status bit
|
|
before enable (mask)</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM7</name>
|
|
<description>Interrupt(N) semaphore n status bit
|
|
before enable (mask)</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM8</name>
|
|
<description>Interrupt(N) semaphore n status bit
|
|
before enable (mask)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM9</name>
|
|
<description>Interrupt(N) semaphore n status bit
|
|
before enable (mask)</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM10</name>
|
|
<description>Interrupt(N) semaphore n status bit
|
|
before enable (mask)</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM11</name>
|
|
<description>Interrupt(N) semaphore n status bit
|
|
before enable (mask)</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM12</name>
|
|
<description>Interrupt(N) semaphore n status bit
|
|
before enable (mask)</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM13</name>
|
|
<description>Interrupt(N) semaphore n status bit
|
|
before enable (mask)</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM14</name>
|
|
<description>Interrupt(N) semaphore n status bit
|
|
before enable (mask)</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM15</name>
|
|
<description>Interrupt(N) semaphore n status bit
|
|
before enable (mask)</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM16</name>
|
|
<description>Interrupt(N) semaphore n status bit
|
|
before enable (mask)</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM17</name>
|
|
<description>Interrupt(N) semaphore n status bit
|
|
before enable (mask)</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM18</name>
|
|
<description>Interrupt(N) semaphore n status bit
|
|
before enable (mask)</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM19</name>
|
|
<description>Interrupt(N) semaphore n status bit
|
|
before enable (mask)</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM20</name>
|
|
<description>Interrupt(N) semaphore n status bit
|
|
before enable (mask)</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM21</name>
|
|
<description>Interrupt(N) semaphore n status bit
|
|
before enable (mask)</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM22</name>
|
|
<description>Interrupt(N) semaphore n status bit
|
|
before enable (mask)</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM23</name>
|
|
<description>Interrupt(N) semaphore n status bit
|
|
before enable (mask)</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM24</name>
|
|
<description>Interrupt(N) semaphore n status bit
|
|
before enable (mask)</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM25</name>
|
|
<description>Interrupt(N) semaphore n status bit
|
|
before enable (mask)</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM26</name>
|
|
<description>Interrupt(N) semaphore n status bit
|
|
before enable (mask)</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM27</name>
|
|
<description>Interrupt(N) semaphore n status bit
|
|
before enable (mask)</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM28</name>
|
|
<description>Interrupt(N) semaphore n status bit
|
|
before enable (mask)</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM29</name>
|
|
<description>Interrupt(N) semaphore n status bit
|
|
before enable (mask)</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM30</name>
|
|
<description>Interrupt(N) semaphore n status bit
|
|
before enable (mask)</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM31</name>
|
|
<description>Interrupt(N) semaphore n status bit
|
|
before enable (mask)</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HSEM_MISR</name>
|
|
<displayName>HSEM_MISR</displayName>
|
|
<description>HSEM Masked interrupt status
|
|
register</description>
|
|
<addressOffset>0x10C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ISEM0</name>
|
|
<description>masked interrupt(N) semaphore n status
|
|
bit after enable (mask)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM1</name>
|
|
<description>masked interrupt(N) semaphore n status
|
|
bit after enable (mask)</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM2</name>
|
|
<description>masked interrupt(N) semaphore n status
|
|
bit after enable (mask)</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM3</name>
|
|
<description>masked interrupt(N) semaphore n status
|
|
bit after enable (mask)</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM4</name>
|
|
<description>masked interrupt(N) semaphore n status
|
|
bit after enable (mask)</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM5</name>
|
|
<description>masked interrupt(N) semaphore n status
|
|
bit after enable (mask)</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM6</name>
|
|
<description>masked interrupt(N) semaphore n status
|
|
bit after enable (mask)</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM7</name>
|
|
<description>masked interrupt(N) semaphore n status
|
|
bit after enable (mask)</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM8</name>
|
|
<description>masked interrupt(N) semaphore n status
|
|
bit after enable (mask)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM9</name>
|
|
<description>masked interrupt(N) semaphore n status
|
|
bit after enable (mask)</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM10</name>
|
|
<description>masked interrupt(N) semaphore n status
|
|
bit after enable (mask)</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM11</name>
|
|
<description>masked interrupt(N) semaphore n status
|
|
bit after enable (mask)</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM12</name>
|
|
<description>masked interrupt(N) semaphore n status
|
|
bit after enable (mask)</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM13</name>
|
|
<description>masked interrupt(N) semaphore n status
|
|
bit after enable (mask)</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM14</name>
|
|
<description>masked interrupt(N) semaphore n status
|
|
bit after enable (mask)</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM15</name>
|
|
<description>masked interrupt(N) semaphore n status
|
|
bit after enable (mask)</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM16</name>
|
|
<description>masked interrupt(N) semaphore n status
|
|
bit after enable (mask)</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM17</name>
|
|
<description>masked interrupt(N) semaphore n status
|
|
bit after enable (mask)</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM18</name>
|
|
<description>masked interrupt(N) semaphore n status
|
|
bit after enable (mask)</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM19</name>
|
|
<description>masked interrupt(N) semaphore n status
|
|
bit after enable (mask)</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM20</name>
|
|
<description>masked interrupt(N) semaphore n status
|
|
bit after enable (mask)</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM21</name>
|
|
<description>masked interrupt(N) semaphore n status
|
|
bit after enable (mask)</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM22</name>
|
|
<description>masked interrupt(N) semaphore n status
|
|
bit after enable (mask)</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM23</name>
|
|
<description>masked interrupt(N) semaphore n status
|
|
bit after enable (mask)</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM24</name>
|
|
<description>masked interrupt(N) semaphore n status
|
|
bit after enable (mask)</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM25</name>
|
|
<description>masked interrupt(N) semaphore n status
|
|
bit after enable (mask)</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM26</name>
|
|
<description>masked interrupt(N) semaphore n status
|
|
bit after enable (mask)</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM27</name>
|
|
<description>masked interrupt(N) semaphore n status
|
|
bit after enable (mask)</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM28</name>
|
|
<description>masked interrupt(N) semaphore n status
|
|
bit after enable (mask)</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM29</name>
|
|
<description>masked interrupt(N) semaphore n status
|
|
bit after enable (mask)</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM30</name>
|
|
<description>masked interrupt(N) semaphore n status
|
|
bit after enable (mask)</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISEM31</name>
|
|
<description>masked interrupt(N) semaphore n status
|
|
bit after enable (mask)</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HSEM_CR</name>
|
|
<displayName>HSEM_CR</displayName>
|
|
<description>HSEM Clear register</description>
|
|
<addressOffset>0x140</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MASTERID</name>
|
|
<description>MasterID of semaphores to be
|
|
cleared</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>KEY</name>
|
|
<description>Semaphore clear Key</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HSEM_KEYR</name>
|
|
<displayName>HSEM_KEYR</displayName>
|
|
<description>HSEM Interrupt clear register</description>
|
|
<addressOffset>0x144</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>KEY</name>
|
|
<description>Semaphore Clear Key</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>I2C1</name>
|
|
<description>I2C</description>
|
|
<groupName>I2C</groupName>
|
|
<baseAddress>0x40005400</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>I2C1_EV</name>
|
|
<description>I2C1 event interrupt</description>
|
|
<value>31</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>I2C1_ER</name>
|
|
<description>I2C1 error interrupt</description>
|
|
<value>32</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CR1</name>
|
|
<displayName>CR1</displayName>
|
|
<description>Access: No wait states, except if a write
|
|
access occurs while a write access to this register is
|
|
ongoing. In this case, wait states are inserted in the
|
|
second write access until the previous one is completed.
|
|
The latency of the second write access can be up to 2 x
|
|
PCLK1 + 6 x I2CCLK.</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Peripheral enable Note: When PE=0, the
|
|
I2C SCL and SDA lines are released. Internal state
|
|
machines and status bits are put back to their reset
|
|
value. When cleared, PE must be kept low for at least
|
|
3 APB clock cycles.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TXIE</name>
|
|
<description>TX Interrupt enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXIE</name>
|
|
<description>RX Interrupt enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADDRIE</name>
|
|
<description>Address match Interrupt enable (slave
|
|
only)</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NACKIE</name>
|
|
<description>Not acknowledge received Interrupt
|
|
enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STOPIE</name>
|
|
<description>STOP detection Interrupt
|
|
enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCIE</name>
|
|
<description>Transfer Complete interrupt enable Note:
|
|
Any of these events will generate an interrupt:
|
|
Transfer Complete (TC) Transfer Complete Reload
|
|
(TCR)</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ERRIE</name>
|
|
<description>Error interrupts enable Note: Any of
|
|
these errors generate an interrupt: Arbitration Loss
|
|
(ARLO) Bus Error detection (BERR) Overrun/Underrun
|
|
(OVR) Timeout detection (TIMEOUT) PEC error detection
|
|
(PECERR) Alert pin event detection
|
|
(ALERT)</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DNF</name>
|
|
<description>Digital noise filter These bits are used
|
|
to configure the digital noise filter on SDA and SCL
|
|
input. The digital filter will filter spikes with a
|
|
length of up to DNF[3:0] * tI2CCLK ... Note: If the
|
|
analog filter is also enabled, the digital filter is
|
|
added to the analog filter. This filter can only be
|
|
programmed when the I2C is disabled (PE =
|
|
0).</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ANFOFF</name>
|
|
<description>Analog noise filter OFF Note: This bit
|
|
can only be programmed when the I2C is disabled (PE =
|
|
0).</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TXDMAEN</name>
|
|
<description>DMA transmission requests
|
|
enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXDMAEN</name>
|
|
<description>DMA reception requests
|
|
enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SBC</name>
|
|
<description>Slave byte control This bit is used to
|
|
enable hardware byte control in slave
|
|
mode.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NOSTRETCH</name>
|
|
<description>Clock stretching disable This bit is
|
|
used to disable clock stretching in slave mode. It
|
|
must be kept cleared in master mode. Note: This bit
|
|
can only be programmed when the I2C is disabled (PE =
|
|
0).</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WUPEN</name>
|
|
<description>Wakeup from Stop mode enable Note: If
|
|
the Wakeup from Stop mode feature is not supported,
|
|
this bit is reserved and forced by hardware to 0.
|
|
Please refer to Section25.3: I2C implementation.
|
|
Note: WUPEN can be set only when DNF =
|
|
0000</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GCEN</name>
|
|
<description>General call enable</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SMBHEN</name>
|
|
<description>SMBus Host address enable Note: If the
|
|
SMBus feature is not supported, this bit is reserved
|
|
and forced by hardware to 0. Please refer to
|
|
Section25.3: I2C implementation.</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SMBDEN</name>
|
|
<description>SMBus Device Default address enable
|
|
Note: If the SMBus feature is not supported, this bit
|
|
is reserved and forced by hardware to 0. Please refer
|
|
to Section25.3: I2C implementation.</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ALERTEN</name>
|
|
<description>SMBus alert enable Device mode
|
|
(SMBHEN=0): Host mode (SMBHEN=1): Note: When
|
|
ALERTEN=0, the SMBA pin can be used as a standard
|
|
GPIO. If the SMBus feature is not supported, this bit
|
|
is reserved and forced by hardware to 0. Please refer
|
|
to Section25.3: I2C implementation.</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PECEN</name>
|
|
<description>PEC enable Note: If the SMBus feature is
|
|
not supported, this bit is reserved and forced by
|
|
hardware to 0. Please refer to Section25.3: I2C
|
|
implementation.</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CR2</name>
|
|
<displayName>CR2</displayName>
|
|
<description>Access: No wait states, except if a write
|
|
access occurs while a write access to this register is
|
|
ongoing. In this case, wait states are inserted in the
|
|
second write access until the previous one is completed.
|
|
The latency of the second write access can be up to 2 x
|
|
PCLK1 + 6 x I2CCLK.</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SADD0</name>
|
|
<description>Slave address bit 0 (master mode) In
|
|
7-bit addressing mode (ADD10 = 0): This bit is dont
|
|
care In 10-bit addressing mode (ADD10 = 1): This bit
|
|
should be written with bit 0 of the slave address to
|
|
be sent Note: Changing these bits when the START bit
|
|
is set is not allowed.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SADD1</name>
|
|
<description>Slave address bit 7:1 (master mode) In
|
|
7-bit addressing mode (ADD10 = 0): These bits should
|
|
be written with the 7-bit slave address to be sent In
|
|
10-bit addressing mode (ADD10 = 1): These bits should
|
|
be written with bits 7:1 of the slave address to be
|
|
sent. Note: Changing these bits when the START bit is
|
|
set is not allowed.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SADD2</name>
|
|
<description>Slave address bit 7:1 (master mode) In
|
|
7-bit addressing mode (ADD10 = 0): These bits should
|
|
be written with the 7-bit slave address to be sent In
|
|
10-bit addressing mode (ADD10 = 1): These bits should
|
|
be written with bits 7:1 of the slave address to be
|
|
sent. Note: Changing these bits when the START bit is
|
|
set is not allowed.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SADD3</name>
|
|
<description>Slave address bit 7:1 (master mode) In
|
|
7-bit addressing mode (ADD10 = 0): These bits should
|
|
be written with the 7-bit slave address to be sent In
|
|
10-bit addressing mode (ADD10 = 1): These bits should
|
|
be written with bits 7:1 of the slave address to be
|
|
sent. Note: Changing these bits when the START bit is
|
|
set is not allowed.</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SADD4</name>
|
|
<description>Slave address bit 7:1 (master mode) In
|
|
7-bit addressing mode (ADD10 = 0): These bits should
|
|
be written with the 7-bit slave address to be sent In
|
|
10-bit addressing mode (ADD10 = 1): These bits should
|
|
be written with bits 7:1 of the slave address to be
|
|
sent. Note: Changing these bits when the START bit is
|
|
set is not allowed.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SADD5</name>
|
|
<description>Slave address bit 7:1 (master mode) In
|
|
7-bit addressing mode (ADD10 = 0): These bits should
|
|
be written with the 7-bit slave address to be sent In
|
|
10-bit addressing mode (ADD10 = 1): These bits should
|
|
be written with bits 7:1 of the slave address to be
|
|
sent. Note: Changing these bits when the START bit is
|
|
set is not allowed.</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SADD6</name>
|
|
<description>Slave address bit 7:1 (master mode) In
|
|
7-bit addressing mode (ADD10 = 0): These bits should
|
|
be written with the 7-bit slave address to be sent In
|
|
10-bit addressing mode (ADD10 = 1): These bits should
|
|
be written with bits 7:1 of the slave address to be
|
|
sent. Note: Changing these bits when the START bit is
|
|
set is not allowed.</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SADD7</name>
|
|
<description>Slave address bit 7:1 (master mode) In
|
|
7-bit addressing mode (ADD10 = 0): These bits should
|
|
be written with the 7-bit slave address to be sent In
|
|
10-bit addressing mode (ADD10 = 1): These bits should
|
|
be written with bits 7:1 of the slave address to be
|
|
sent. Note: Changing these bits when the START bit is
|
|
set is not allowed.</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SADD8</name>
|
|
<description>Slave address bit 9:8 (master mode) In
|
|
7-bit addressing mode (ADD10 = 0): These bits are
|
|
dont care In 10-bit addressing mode (ADD10 = 1):
|
|
These bits should be written with bits 9:8 of the
|
|
slave address to be sent Note: Changing these bits
|
|
when the START bit is set is not
|
|
allowed.</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SADD9</name>
|
|
<description>Slave address bit 9:8 (master mode) In
|
|
7-bit addressing mode (ADD10 = 0): These bits are
|
|
dont care In 10-bit addressing mode (ADD10 = 1):
|
|
These bits should be written with bits 9:8 of the
|
|
slave address to be sent Note: Changing these bits
|
|
when the START bit is set is not
|
|
allowed.</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RD_WRN</name>
|
|
<description>Transfer direction (master mode) Note:
|
|
Changing this bit when the START bit is set is not
|
|
allowed.</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADD10</name>
|
|
<description>10-bit addressing mode (master mode)
|
|
Note: Changing this bit when the START bit is set is
|
|
not allowed.</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HEAD10R</name>
|
|
<description>10-bit address header only read
|
|
direction (master receiver mode) Note: Changing this
|
|
bit when the START bit is set is not
|
|
allowed.</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>START</name>
|
|
<description>Start generation This bit is set by
|
|
software, and cleared by hardware after the Start
|
|
followed by the address sequence is sent, by an
|
|
arbitration loss, by a timeout error detection, or
|
|
when PE = 0. It can also be cleared by software by
|
|
writing 1 to the ADDRCF bit in the I2C_ICR register.
|
|
If the I2C is already in master mode with AUTOEND =
|
|
0, setting this bit generates a Repeated Start
|
|
condition when RELOAD=0, after the end of the NBYTES
|
|
transfer. Otherwise setting this bit will generate a
|
|
START condition once the bus is free. Note: Writing 0
|
|
to this bit has no effect. The START bit can be set
|
|
even if the bus is BUSY or I2C is in slave mode. This
|
|
bit has no effect when RELOAD is set.</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STOP</name>
|
|
<description>Stop generation (master mode) The bit is
|
|
set by software, cleared by hardware when a Stop
|
|
condition is detected, or when PE = 0. In Master
|
|
Mode: Note: Writing 0 to this bit has no
|
|
effect.</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NACK</name>
|
|
<description>NACK generation (slave mode) The bit is
|
|
set by software, cleared by hardware when the NACK is
|
|
sent, or when a STOP condition or an Address matched
|
|
is received, or when PE=0. Note: Writing 0 to this
|
|
bit has no effect. This bit is used in slave mode
|
|
only: in master receiver mode, NACK is automatically
|
|
generated after last byte preceding STOP or RESTART
|
|
condition, whatever the NACK bit value. When an
|
|
overrun occurs in slave receiver NOSTRETCH mode, a
|
|
NACK is automatically generated whatever the NACK bit
|
|
value. When hardware PEC checking is enabled
|
|
(PECBYTE=1), the PEC acknowledge value does not
|
|
depend on the NACK value.</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NBYTES</name>
|
|
<description>Number of bytes The number of bytes to
|
|
be transmitted/received is programmed there. This
|
|
field is dont care in slave mode with SBC=0. Note:
|
|
Changing these bits when the START bit is set is not
|
|
allowed.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RELOAD</name>
|
|
<description>NBYTES reload mode This bit is set and
|
|
cleared by software.</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AUTOEND</name>
|
|
<description>Automatic end mode (master mode) This
|
|
bit is set and cleared by software. Note: This bit
|
|
has no effect in slave mode or when the RELOAD bit is
|
|
set.</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PECBYTE</name>
|
|
<description>Packet error checking byte This bit is
|
|
set by software, and cleared by hardware when the PEC
|
|
is transferred, or when a STOP condition or an
|
|
Address matched is received, also when PE=0. Note:
|
|
Writing 0 to this bit has no effect. This bit has no
|
|
effect when RELOAD is set. This bit has no effect is
|
|
slave mode when SBC=0. If the SMBus feature is not
|
|
supported, this bit is reserved and forced by
|
|
hardware to 0. Please refer to Section25.3: I2C
|
|
implementation.</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OAR1</name>
|
|
<displayName>OAR1</displayName>
|
|
<description>Access: No wait states, except if a write
|
|
access occurs while a write access to this register is
|
|
ongoing. In this case, wait states are inserted in the
|
|
second write access until the previous one is completed.
|
|
The latency of the second write access can be up to 2 x
|
|
PCLK1 + 6 x I2CCLK.</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OA1</name>
|
|
<description>Interface address 7-bit addressing mode:
|
|
dont care 10-bit addressing mode: bits 9:8 of address
|
|
Note: These bits can be written only when OA1EN=0.
|
|
OA1[7:1]: Interface address Bits 7:1 of address Note:
|
|
These bits can be written only when OA1EN=0. OA1[0]:
|
|
Interface address 7-bit addressing mode: dont care
|
|
10-bit addressing mode: bit 0 of address Note: This
|
|
bit can be written only when OA1EN=0.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OA1MODE</name>
|
|
<description>Own Address 1 10-bit mode Note: This bit
|
|
can be written only when OA1EN=0.</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OA1EN</name>
|
|
<description>Own Address 1 enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OAR2</name>
|
|
<displayName>OAR2</displayName>
|
|
<description>Access: No wait states, except if a write
|
|
access occurs while a write access to this register is
|
|
ongoing. In this case, wait states are inserted in the
|
|
second write access until the previous one is completed.
|
|
The latency of the second write access can be up to 2 x
|
|
PCLK1 + 6 x I2CCLK.</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OA2</name>
|
|
<description>Interface address bits 7:1 of address
|
|
Note: These bits can be written only when
|
|
OA2EN=0.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OA2MSK</name>
|
|
<description>Own Address 2 masks Note: These bits can
|
|
be written only when OA2EN=0. As soon as OA2MSK is
|
|
not equal to 0, the reserved I2C addresses (0b0000xxx
|
|
and 0b1111xxx) are not acknowledged even if the
|
|
comparison matches.</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OA2EN</name>
|
|
<description>Own Address 2 enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TIMINGR</name>
|
|
<displayName>TIMINGR</displayName>
|
|
<description>Access: No wait states</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SCLL</name>
|
|
<description>SCL low period (master mode) This field
|
|
is used to generate the SCL low period in master
|
|
mode. tSCLL = (SCLL+1) x tPRESC Note: SCLL is also
|
|
used to generate tBUF and tSU:STA
|
|
timings.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SCLH</name>
|
|
<description>SCL high period (master mode) This field
|
|
is used to generate the SCL high period in master
|
|
mode. tSCLH = (SCLH+1) x tPRESC Note: SCLH is also
|
|
used to generate tSU:STO and tHD:STA
|
|
timing.</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SDADEL</name>
|
|
<description>Data hold time This field is used to
|
|
generate the delay tSDADEL between SCL falling edge
|
|
and SDA edge. In master mode and in slave mode with
|
|
NOSTRETCH = 0, the SCL line is stretched low during
|
|
tSDADEL. tSDADEL= SDADEL x tPRESC Note: SDADEL is
|
|
used to generate tHD:DAT timing.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SCLDEL</name>
|
|
<description>Data setup time This field is used to
|
|
generate a delay tSCLDEL between SDA edge and SCL
|
|
rising edge. In master mode and in slave mode with
|
|
NOSTRETCH = 0, the SCL line is stretched low during
|
|
tSCLDEL. tSCLDEL = (SCLDEL+1) x tPRESC Note: tSCLDEL
|
|
is used to generate tSU:DAT timing.</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PRESC</name>
|
|
<description>Timing prescaler This field is used to
|
|
prescale I2CCLK in order to generate the clock period
|
|
tPRESC used for data setup and hold counters (refer
|
|
to I2C timings on page9) and for SCL high and low
|
|
level counters (refer to I2C master initialization on
|
|
page24). tPRESC = (PRESC+1) x tI2CCLK</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TIMEOUTR</name>
|
|
<displayName>TIMEOUTR</displayName>
|
|
<description>Access: No wait states, except if a write
|
|
access occurs while a write access to this register is
|
|
ongoing. In this case, wait states are inserted in the
|
|
second write access until the previous one is completed.
|
|
The latency of the second write access can be up to 2 x
|
|
PCLK1 + 6 x I2CCLK.</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TIMEOUTA</name>
|
|
<description>Bus Timeout A This field is used to
|
|
configure: The SCL low timeout condition tTIMEOUT
|
|
when TIDLE=0 tTIMEOUT= (TIMEOUTA+1) x 2048 x tI2CCLK
|
|
The bus idle condition (both SCL and SDA high) when
|
|
TIDLE=1 tIDLE= (TIMEOUTA+1) x 4 x tI2CCLK Note: These
|
|
bits can be written only when
|
|
TIMOUTEN=0.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIDLE</name>
|
|
<description>Idle clock timeout detection Note: This
|
|
bit can be written only when
|
|
TIMOUTEN=0.</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMOUTEN</name>
|
|
<description>Clock timeout enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEOUTB</name>
|
|
<description>Bus timeout B This field is used to
|
|
configure the cumulative clock extension timeout: In
|
|
master mode, the master cumulative clock low extend
|
|
time (tLOW:MEXT) is detected In slave mode, the slave
|
|
cumulative clock low extend time (tLOW:SEXT) is
|
|
detected tLOW:EXT= (TIMEOUTB+1) x 2048 x tI2CCLK
|
|
Note: These bits can be written only when
|
|
TEXTEN=0.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TEXTEN</name>
|
|
<description>Extended clock timeout
|
|
enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ISR</name>
|
|
<displayName>ISR</displayName>
|
|
<description>Access: No wait states</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000001</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TXE</name>
|
|
<description>Transmit data register empty
|
|
(transmitters) This bit is set by hardware when the
|
|
I2C_TXDR register is empty. It is cleared when the
|
|
next data to be sent is written in the I2C_TXDR
|
|
register. This bit can be written to 1 by software in
|
|
order to flush the transmit data register I2C_TXDR.
|
|
Note: This bit is set by hardware when
|
|
PE=0.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXIS</name>
|
|
<description>Transmit interrupt status (transmitters)
|
|
This bit is set by hardware when the I2C_TXDR
|
|
register is empty and the data to be transmitted must
|
|
be written in the I2C_TXDR register. It is cleared
|
|
when the next data to be sent is written in the
|
|
I2C_TXDR register. This bit can be written to 1 by
|
|
software when NOSTRETCH=1 only, in order to generate
|
|
a TXIS event (interrupt if TXIE=1 or DMA request if
|
|
TXDMAEN=1). Note: This bit is cleared by hardware
|
|
when PE=0.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXNE</name>
|
|
<description>Receive data register not empty
|
|
(receivers) This bit is set by hardware when the
|
|
received data is copied into the I2C_RXDR register,
|
|
and is ready to be read. It is cleared when I2C_RXDR
|
|
is read. Note: This bit is cleared by hardware when
|
|
PE=0.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ADDR</name>
|
|
<description>Address matched (slave mode) This bit is
|
|
set by hardware as soon as the received slave address
|
|
matched with one of the enabled slave addresses. It
|
|
is cleared by software by setting ADDRCF bit. Note:
|
|
This bit is cleared by hardware when
|
|
PE=0.</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>NACKF</name>
|
|
<description>Not Acknowledge received flag This flag
|
|
is set by hardware when a NACK is received after a
|
|
byte transmission. It is cleared by software by
|
|
setting the NACKCF bit. Note: This bit is cleared by
|
|
hardware when PE=0.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>STOPF</name>
|
|
<description>Stop detection flag This flag is set by
|
|
hardware when a Stop condition is detected on the bus
|
|
and the peripheral is involved in this transfer:
|
|
either as a master, provided that the STOP condition
|
|
is generated by the peripheral. or as a slave,
|
|
provided that the peripheral has been addressed
|
|
previously during this transfer. It is cleared by
|
|
software by setting the STOPCF bit. Note: This bit is
|
|
cleared by hardware when PE=0.</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TC</name>
|
|
<description>Transfer Complete (master mode) This
|
|
flag is set by hardware when RELOAD=0, AUTOEND=0 and
|
|
NBYTES data have been transferred. It is cleared by
|
|
software when START bit or STOP bit is set. Note:
|
|
This bit is cleared by hardware when
|
|
PE=0.</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TCR</name>
|
|
<description>Transfer Complete Reload This flag is
|
|
set by hardware when RELOAD=1 and NBYTES data have
|
|
been transferred. It is cleared by software when
|
|
NBYTES is written to a non-zero value. Note: This bit
|
|
is cleared by hardware when PE=0. This flag is only
|
|
for master mode, or for slave mode when the SBC bit
|
|
is set.</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BERR</name>
|
|
<description>Bus error This flag is set by hardware
|
|
when a misplaced Start or Stop condition is detected
|
|
whereas the peripheral is involved in the transfer.
|
|
The flag is not set during the address phase in slave
|
|
mode. It is cleared by software by setting BERRCF
|
|
bit. Note: This bit is cleared by hardware when
|
|
PE=0.</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ARLO</name>
|
|
<description>Arbitration lost This flag is set by
|
|
hardware in case of arbitration loss. It is cleared
|
|
by software by setting the ARLOCF bit. Note: This bit
|
|
is cleared by hardware when PE=0.</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OVR</name>
|
|
<description>Overrun/Underrun (slave mode) This flag
|
|
is set by hardware in slave mode with NOSTRETCH=1,
|
|
when an overrun/underrun error occurs. It is cleared
|
|
by software by setting the OVRCF bit. Note: This bit
|
|
is cleared by hardware when PE=0.</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PECERR</name>
|
|
<description>PEC Error in reception This flag is set
|
|
by hardware when the received PEC does not match with
|
|
the PEC register content. A NACK is automatically
|
|
sent after the wrong PEC reception. It is cleared by
|
|
software by setting the PECCF bit. Note: This bit is
|
|
cleared by hardware when PE=0. If the SMBus feature
|
|
is not supported, this bit is reserved and forced by
|
|
hardware to 0. Please refer to Section25.3: I2C
|
|
implementation.</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TIMEOUT</name>
|
|
<description>Timeout or tLOW detection flag This flag
|
|
is set by hardware when a timeout or extended clock
|
|
timeout occurred. It is cleared by software by
|
|
setting the TIMEOUTCF bit. Note: This bit is cleared
|
|
by hardware when PE=0. If the SMBus feature is not
|
|
supported, this bit is reserved and forced by
|
|
hardware to 0. Please refer to Section25.3: I2C
|
|
implementation.</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ALERT</name>
|
|
<description>SMBus alert This flag is set by hardware
|
|
when SMBHEN=1 (SMBus host configuration), ALERTEN=1
|
|
and a SMBALERT event (falling edge) is detected on
|
|
SMBA pin. It is cleared by software by setting the
|
|
ALERTCF bit. Note: This bit is cleared by hardware
|
|
when PE=0. If the SMBus feature is not supported,
|
|
this bit is reserved and forced by hardware to 0.
|
|
Please refer to Section25.3: I2C
|
|
implementation.</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BUSY</name>
|
|
<description>Bus busy This flag indicates that a
|
|
communication is in progress on the bus. It is set by
|
|
hardware when a START condition is detected. It is
|
|
cleared by hardware when a Stop condition is
|
|
detected, or when PE=0.</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DIR</name>
|
|
<description>Transfer direction (Slave mode) This
|
|
flag is updated when an address match event occurs
|
|
(ADDR=1).</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ADDCODE</name>
|
|
<description>Address match code (Slave mode) These
|
|
bits are updated with the received address when an
|
|
address match event occurs (ADDR = 1). In the case of
|
|
a 10-bit address, ADDCODE provides the 10-bit header
|
|
followed by the 2 MSBs of the address.</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ICR</name>
|
|
<displayName>ICR</displayName>
|
|
<description>Access: No wait states</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ADDRCF</name>
|
|
<description>Address matched flag clear Writing 1 to
|
|
this bit clears the ADDR flag in the I2C_ISR
|
|
register. Writing 1 to this bit also clears the START
|
|
bit in the I2C_CR2 register.</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NACKCF</name>
|
|
<description>Not Acknowledge flag clear Writing 1 to
|
|
this bit clears the ACKF flag in I2C_ISR
|
|
register.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STOPCF</name>
|
|
<description>Stop detection flag clear Writing 1 to
|
|
this bit clears the STOPF flag in the I2C_ISR
|
|
register.</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BERRCF</name>
|
|
<description>Bus error flag clear Writing 1 to this
|
|
bit clears the BERRF flag in the I2C_ISR
|
|
register.</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ARLOCF</name>
|
|
<description>Arbitration Lost flag clear Writing 1 to
|
|
this bit clears the ARLO flag in the I2C_ISR
|
|
register.</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OVRCF</name>
|
|
<description>Overrun/Underrun flag clear Writing 1 to
|
|
this bit clears the OVR flag in the I2C_ISR
|
|
register.</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PECCF</name>
|
|
<description>PEC Error flag clear Writing 1 to this
|
|
bit clears the PECERR flag in the I2C_ISR register.
|
|
Note: If the SMBus feature is not supported, this bit
|
|
is reserved and forced by hardware to 0. Please refer
|
|
to Section25.3: I2C implementation.</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMOUTCF</name>
|
|
<description>Timeout detection flag clear Writing 1
|
|
to this bit clears the TIMEOUT flag in the I2C_ISR
|
|
register. Note: If the SMBus feature is not
|
|
supported, this bit is reserved and forced by
|
|
hardware to 0. Please refer to Section25.3: I2C
|
|
implementation.</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ALERTCF</name>
|
|
<description>Alert flag clear Writing 1 to this bit
|
|
clears the ALERT flag in the I2C_ISR register. Note:
|
|
If the SMBus feature is not supported, this bit is
|
|
reserved and forced by hardware to 0. Please refer to
|
|
Section25.3: I2C implementation.</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PECR</name>
|
|
<displayName>PECR</displayName>
|
|
<description>Access: No wait states</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PEC</name>
|
|
<description>Packet error checking register This
|
|
field contains the internal PEC when PECEN=1. The PEC
|
|
is cleared by hardware when PE=0.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXDR</name>
|
|
<displayName>RXDR</displayName>
|
|
<description>Access: No wait states</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RXDATA</name>
|
|
<description>8-bit receive data Data byte received
|
|
from the I2C bus.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXDR</name>
|
|
<displayName>TXDR</displayName>
|
|
<description>Access: No wait states</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TXDATA</name>
|
|
<description>8-bit transmit data Data byte to be
|
|
transmitted to the I2C bus. Note: These bits can be
|
|
written only when TXE=1.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral derivedFrom="I2C1">
|
|
<name>I2C2</name>
|
|
<baseAddress>0x40005800</baseAddress>
|
|
<interrupt>
|
|
<name>I2C2_EV</name>
|
|
<description>I2C2 event interrupt</description>
|
|
<value>33</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>I2C2_ER</name>
|
|
<description>I2C2 error interrupt</description>
|
|
<value>34</value>
|
|
</interrupt>
|
|
</peripheral>
|
|
<peripheral derivedFrom="I2C1">
|
|
<name>I2C3</name>
|
|
<baseAddress>0x40005C00</baseAddress>
|
|
<interrupt>
|
|
<name>I2C3_EV</name>
|
|
<description>I2C3 event interrupt</description>
|
|
<value>72</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>I2C3_ER</name>
|
|
<description>I2C3 error interrupt</description>
|
|
<value>73</value>
|
|
</interrupt>
|
|
</peripheral>
|
|
<peripheral derivedFrom="I2C1">
|
|
<name>I2C4</name>
|
|
<baseAddress>0x58001C00</baseAddress>
|
|
<interrupt>
|
|
<name>I2C4_EV</name>
|
|
<description>I2C4 event interrupt</description>
|
|
<value>95</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>I2C4_ER</name>
|
|
<description>I2C4 error interrupt</description>
|
|
<value>96</value>
|
|
</interrupt>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>GPIOA</name>
|
|
<description>GPIO</description>
|
|
<groupName>GPIO</groupName>
|
|
<baseAddress>0x58020000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>MODER</name>
|
|
<displayName>MODER</displayName>
|
|
<description>GPIO port mode register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xABFFFFFF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MODE0</name>
|
|
<description>[1:0]: Port x configuration bits (y =
|
|
0..15) These bits are written by software to
|
|
configure the I/O mode.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODE1</name>
|
|
<description>[1:0]: Port x configuration bits (y =
|
|
0..15) These bits are written by software to
|
|
configure the I/O mode.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODE2</name>
|
|
<description>[1:0]: Port x configuration bits (y =
|
|
0..15) These bits are written by software to
|
|
configure the I/O mode.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODE3</name>
|
|
<description>[1:0]: Port x configuration bits (y =
|
|
0..15) These bits are written by software to
|
|
configure the I/O mode.</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODE4</name>
|
|
<description>[1:0]: Port x configuration bits (y =
|
|
0..15) These bits are written by software to
|
|
configure the I/O mode.</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODE5</name>
|
|
<description>[1:0]: Port x configuration bits (y =
|
|
0..15) These bits are written by software to
|
|
configure the I/O mode.</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODE6</name>
|
|
<description>[1:0]: Port x configuration bits (y =
|
|
0..15) These bits are written by software to
|
|
configure the I/O mode.</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODE7</name>
|
|
<description>[1:0]: Port x configuration bits (y =
|
|
0..15) These bits are written by software to
|
|
configure the I/O mode.</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODE8</name>
|
|
<description>[1:0]: Port x configuration bits (y =
|
|
0..15) These bits are written by software to
|
|
configure the I/O mode.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODE9</name>
|
|
<description>[1:0]: Port x configuration bits (y =
|
|
0..15) These bits are written by software to
|
|
configure the I/O mode.</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODE10</name>
|
|
<description>[1:0]: Port x configuration bits (y =
|
|
0..15) These bits are written by software to
|
|
configure the I/O mode.</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODE11</name>
|
|
<description>[1:0]: Port x configuration bits (y =
|
|
0..15) These bits are written by software to
|
|
configure the I/O mode.</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODE12</name>
|
|
<description>[1:0]: Port x configuration bits (y =
|
|
0..15) These bits are written by software to
|
|
configure the I/O mode.</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODE13</name>
|
|
<description>[1:0]: Port x configuration bits (y =
|
|
0..15) These bits are written by software to
|
|
configure the I/O mode.</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODE14</name>
|
|
<description>[1:0]: Port x configuration bits (y =
|
|
0..15) These bits are written by software to
|
|
configure the I/O mode.</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODE15</name>
|
|
<description>[1:0]: Port x configuration bits (y =
|
|
0..15) These bits are written by software to
|
|
configure the I/O mode.</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OTYPER</name>
|
|
<displayName>OTYPER</displayName>
|
|
<description>GPIO port output type register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OT0</name>
|
|
<description>Port x configuration bits (y = 0..15)
|
|
These bits are written by software to configure the
|
|
I/O output type.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OT1</name>
|
|
<description>Port x configuration bits (y = 0..15)
|
|
These bits are written by software to configure the
|
|
I/O output type.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OT2</name>
|
|
<description>Port x configuration bits (y = 0..15)
|
|
These bits are written by software to configure the
|
|
I/O output type.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OT3</name>
|
|
<description>Port x configuration bits (y = 0..15)
|
|
These bits are written by software to configure the
|
|
I/O output type.</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OT4</name>
|
|
<description>Port x configuration bits (y = 0..15)
|
|
These bits are written by software to configure the
|
|
I/O output type.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OT5</name>
|
|
<description>Port x configuration bits (y = 0..15)
|
|
These bits are written by software to configure the
|
|
I/O output type.</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OT6</name>
|
|
<description>Port x configuration bits (y = 0..15)
|
|
These bits are written by software to configure the
|
|
I/O output type.</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OT7</name>
|
|
<description>Port x configuration bits (y = 0..15)
|
|
These bits are written by software to configure the
|
|
I/O output type.</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OT8</name>
|
|
<description>Port x configuration bits (y = 0..15)
|
|
These bits are written by software to configure the
|
|
I/O output type.</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OT9</name>
|
|
<description>Port x configuration bits (y = 0..15)
|
|
These bits are written by software to configure the
|
|
I/O output type.</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OT10</name>
|
|
<description>Port x configuration bits (y = 0..15)
|
|
These bits are written by software to configure the
|
|
I/O output type.</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OT11</name>
|
|
<description>Port x configuration bits (y = 0..15)
|
|
These bits are written by software to configure the
|
|
I/O output type.</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OT12</name>
|
|
<description>Port x configuration bits (y = 0..15)
|
|
These bits are written by software to configure the
|
|
I/O output type.</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OT13</name>
|
|
<description>Port x configuration bits (y = 0..15)
|
|
These bits are written by software to configure the
|
|
I/O output type.</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OT14</name>
|
|
<description>Port x configuration bits (y = 0..15)
|
|
These bits are written by software to configure the
|
|
I/O output type.</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OT15</name>
|
|
<description>Port x configuration bits (y = 0..15)
|
|
These bits are written by software to configure the
|
|
I/O output type.</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OSPEEDR</name>
|
|
<displayName>OSPEEDR</displayName>
|
|
<description>GPIO port output speed
|
|
register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0C000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OSPEED0</name>
|
|
<description>[1:0]: Port x configuration bits (y =
|
|
0..15) These bits are written by software to
|
|
configure the I/O output speed. Note: Refer to the
|
|
device datasheet for the frequency specifications and
|
|
the power supply and load conditions for each
|
|
speed.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPEED1</name>
|
|
<description>[1:0]: Port x configuration bits (y =
|
|
0..15) These bits are written by software to
|
|
configure the I/O output speed. Note: Refer to the
|
|
device datasheet for the frequency specifications and
|
|
the power supply and load conditions for each
|
|
speed.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPEED2</name>
|
|
<description>[1:0]: Port x configuration bits (y =
|
|
0..15) These bits are written by software to
|
|
configure the I/O output speed. Note: Refer to the
|
|
device datasheet for the frequency specifications and
|
|
the power supply and load conditions for each
|
|
speed.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPEED3</name>
|
|
<description>[1:0]: Port x configuration bits (y =
|
|
0..15) These bits are written by software to
|
|
configure the I/O output speed. Note: Refer to the
|
|
device datasheet for the frequency specifications and
|
|
the power supply and load conditions for each
|
|
speed.</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPEED4</name>
|
|
<description>[1:0]: Port x configuration bits (y =
|
|
0..15) These bits are written by software to
|
|
configure the I/O output speed. Note: Refer to the
|
|
device datasheet for the frequency specifications and
|
|
the power supply and load conditions for each
|
|
speed.</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPEED5</name>
|
|
<description>[1:0]: Port x configuration bits (y =
|
|
0..15) These bits are written by software to
|
|
configure the I/O output speed. Note: Refer to the
|
|
device datasheet for the frequency specifications and
|
|
the power supply and load conditions for each
|
|
speed.</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPEED6</name>
|
|
<description>[1:0]: Port x configuration bits (y =
|
|
0..15) These bits are written by software to
|
|
configure the I/O output speed. Note: Refer to the
|
|
device datasheet for the frequency specifications and
|
|
the power supply and load conditions for each
|
|
speed.</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPEED7</name>
|
|
<description>[1:0]: Port x configuration bits (y =
|
|
0..15) These bits are written by software to
|
|
configure the I/O output speed. Note: Refer to the
|
|
device datasheet for the frequency specifications and
|
|
the power supply and load conditions for each
|
|
speed.</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPEED8</name>
|
|
<description>[1:0]: Port x configuration bits (y =
|
|
0..15) These bits are written by software to
|
|
configure the I/O output speed. Note: Refer to the
|
|
device datasheet for the frequency specifications and
|
|
the power supply and load conditions for each
|
|
speed.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPEED9</name>
|
|
<description>[1:0]: Port x configuration bits (y =
|
|
0..15) These bits are written by software to
|
|
configure the I/O output speed. Note: Refer to the
|
|
device datasheet for the frequency specifications and
|
|
the power supply and load conditions for each
|
|
speed.</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPEED10</name>
|
|
<description>[1:0]: Port x configuration bits (y =
|
|
0..15) These bits are written by software to
|
|
configure the I/O output speed. Note: Refer to the
|
|
device datasheet for the frequency specifications and
|
|
the power supply and load conditions for each
|
|
speed.</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPEED11</name>
|
|
<description>[1:0]: Port x configuration bits (y =
|
|
0..15) These bits are written by software to
|
|
configure the I/O output speed. Note: Refer to the
|
|
device datasheet for the frequency specifications and
|
|
the power supply and load conditions for each
|
|
speed.</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPEED12</name>
|
|
<description>[1:0]: Port x configuration bits (y =
|
|
0..15) These bits are written by software to
|
|
configure the I/O output speed. Note: Refer to the
|
|
device datasheet for the frequency specifications and
|
|
the power supply and load conditions for each
|
|
speed.</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPEED13</name>
|
|
<description>[1:0]: Port x configuration bits (y =
|
|
0..15) These bits are written by software to
|
|
configure the I/O output speed. Note: Refer to the
|
|
device datasheet for the frequency specifications and
|
|
the power supply and load conditions for each
|
|
speed.</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPEED14</name>
|
|
<description>[1:0]: Port x configuration bits (y =
|
|
0..15) These bits are written by software to
|
|
configure the I/O output speed. Note: Refer to the
|
|
device datasheet for the frequency specifications and
|
|
the power supply and load conditions for each
|
|
speed.</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPEED15</name>
|
|
<description>[1:0]: Port x configuration bits (y =
|
|
0..15) These bits are written by software to
|
|
configure the I/O output speed. Note: Refer to the
|
|
device datasheet for the frequency specifications and
|
|
the power supply and load conditions for each
|
|
speed.</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PUPDR</name>
|
|
<displayName>PUPDR</displayName>
|
|
<description>GPIO port pull-up/pull-down
|
|
register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x12100000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PUPD0</name>
|
|
<description>[1:0]: Port x configuration bits (y =
|
|
0..15) These bits are written by software to
|
|
configure the I/O pull-up or pull-down</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUPD1</name>
|
|
<description>[1:0]: Port x configuration bits (y =
|
|
0..15) These bits are written by software to
|
|
configure the I/O pull-up or pull-down</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUPD2</name>
|
|
<description>[1:0]: Port x configuration bits (y =
|
|
0..15) These bits are written by software to
|
|
configure the I/O pull-up or pull-down</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUPD3</name>
|
|
<description>[1:0]: Port x configuration bits (y =
|
|
0..15) These bits are written by software to
|
|
configure the I/O pull-up or pull-down</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUPD4</name>
|
|
<description>[1:0]: Port x configuration bits (y =
|
|
0..15) These bits are written by software to
|
|
configure the I/O pull-up or pull-down</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUPD5</name>
|
|
<description>[1:0]: Port x configuration bits (y =
|
|
0..15) These bits are written by software to
|
|
configure the I/O pull-up or pull-down</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUPD6</name>
|
|
<description>[1:0]: Port x configuration bits (y =
|
|
0..15) These bits are written by software to
|
|
configure the I/O pull-up or pull-down</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUPD7</name>
|
|
<description>[1:0]: Port x configuration bits (y =
|
|
0..15) These bits are written by software to
|
|
configure the I/O pull-up or pull-down</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUPD8</name>
|
|
<description>[1:0]: Port x configuration bits (y =
|
|
0..15) These bits are written by software to
|
|
configure the I/O pull-up or pull-down</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUPD9</name>
|
|
<description>[1:0]: Port x configuration bits (y =
|
|
0..15) These bits are written by software to
|
|
configure the I/O pull-up or pull-down</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUPD10</name>
|
|
<description>[1:0]: Port x configuration bits (y =
|
|
0..15) These bits are written by software to
|
|
configure the I/O pull-up or pull-down</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUPD11</name>
|
|
<description>[1:0]: Port x configuration bits (y =
|
|
0..15) These bits are written by software to
|
|
configure the I/O pull-up or pull-down</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUPD12</name>
|
|
<description>[1:0]: Port x configuration bits (y =
|
|
0..15) These bits are written by software to
|
|
configure the I/O pull-up or pull-down</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUPD13</name>
|
|
<description>[1:0]: Port x configuration bits (y =
|
|
0..15) These bits are written by software to
|
|
configure the I/O pull-up or pull-down</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUPD14</name>
|
|
<description>[1:0]: Port x configuration bits (y =
|
|
0..15) These bits are written by software to
|
|
configure the I/O pull-up or pull-down</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUPD15</name>
|
|
<description>[1:0]: Port x configuration bits (y =
|
|
0..15) These bits are written by software to
|
|
configure the I/O pull-up or pull-down</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IDR</name>
|
|
<displayName>IDR</displayName>
|
|
<description>GPIO port input data register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ID0</name>
|
|
<description>Port input data bit (y = 0..15) These
|
|
bits are read-only. They contain the input value of
|
|
the corresponding I/O port.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ID1</name>
|
|
<description>Port input data bit (y = 0..15) These
|
|
bits are read-only. They contain the input value of
|
|
the corresponding I/O port.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ID2</name>
|
|
<description>Port input data bit (y = 0..15) These
|
|
bits are read-only. They contain the input value of
|
|
the corresponding I/O port.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ID3</name>
|
|
<description>Port input data bit (y = 0..15) These
|
|
bits are read-only. They contain the input value of
|
|
the corresponding I/O port.</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ID4</name>
|
|
<description>Port input data bit (y = 0..15) These
|
|
bits are read-only. They contain the input value of
|
|
the corresponding I/O port.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ID5</name>
|
|
<description>Port input data bit (y = 0..15) These
|
|
bits are read-only. They contain the input value of
|
|
the corresponding I/O port.</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ID6</name>
|
|
<description>Port input data bit (y = 0..15) These
|
|
bits are read-only. They contain the input value of
|
|
the corresponding I/O port.</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ID7</name>
|
|
<description>Port input data bit (y = 0..15) These
|
|
bits are read-only. They contain the input value of
|
|
the corresponding I/O port.</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ID8</name>
|
|
<description>Port input data bit (y = 0..15) These
|
|
bits are read-only. They contain the input value of
|
|
the corresponding I/O port.</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ID9</name>
|
|
<description>Port input data bit (y = 0..15) These
|
|
bits are read-only. They contain the input value of
|
|
the corresponding I/O port.</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ID10</name>
|
|
<description>Port input data bit (y = 0..15) These
|
|
bits are read-only. They contain the input value of
|
|
the corresponding I/O port.</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ID11</name>
|
|
<description>Port input data bit (y = 0..15) These
|
|
bits are read-only. They contain the input value of
|
|
the corresponding I/O port.</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ID12</name>
|
|
<description>Port input data bit (y = 0..15) These
|
|
bits are read-only. They contain the input value of
|
|
the corresponding I/O port.</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ID13</name>
|
|
<description>Port input data bit (y = 0..15) These
|
|
bits are read-only. They contain the input value of
|
|
the corresponding I/O port.</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ID14</name>
|
|
<description>Port input data bit (y = 0..15) These
|
|
bits are read-only. They contain the input value of
|
|
the corresponding I/O port.</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ID15</name>
|
|
<description>Port input data bit (y = 0..15) These
|
|
bits are read-only. They contain the input value of
|
|
the corresponding I/O port.</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ODR</name>
|
|
<displayName>ODR</displayName>
|
|
<description>GPIO port output data register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OD0</name>
|
|
<description>Port output data bit These bits can be
|
|
read and written by software. Note: For atomic bit
|
|
set/reset, the OD bits can be individually set and/or
|
|
reset by writing to the GPIOx_BSRR or GPIOx_BRR
|
|
registers (x = A..F).</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OD1</name>
|
|
<description>Port output data bit These bits can be
|
|
read and written by software. Note: For atomic bit
|
|
set/reset, the OD bits can be individually set and/or
|
|
reset by writing to the GPIOx_BSRR or GPIOx_BRR
|
|
registers (x = A..F).</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OD2</name>
|
|
<description>Port output data bit These bits can be
|
|
read and written by software. Note: For atomic bit
|
|
set/reset, the OD bits can be individually set and/or
|
|
reset by writing to the GPIOx_BSRR or GPIOx_BRR
|
|
registers (x = A..F).</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OD3</name>
|
|
<description>Port output data bit These bits can be
|
|
read and written by software. Note: For atomic bit
|
|
set/reset, the OD bits can be individually set and/or
|
|
reset by writing to the GPIOx_BSRR or GPIOx_BRR
|
|
registers (x = A..F).</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OD4</name>
|
|
<description>Port output data bit These bits can be
|
|
read and written by software. Note: For atomic bit
|
|
set/reset, the OD bits can be individually set and/or
|
|
reset by writing to the GPIOx_BSRR or GPIOx_BRR
|
|
registers (x = A..F).</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OD5</name>
|
|
<description>Port output data bit These bits can be
|
|
read and written by software. Note: For atomic bit
|
|
set/reset, the OD bits can be individually set and/or
|
|
reset by writing to the GPIOx_BSRR or GPIOx_BRR
|
|
registers (x = A..F).</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OD6</name>
|
|
<description>Port output data bit These bits can be
|
|
read and written by software. Note: For atomic bit
|
|
set/reset, the OD bits can be individually set and/or
|
|
reset by writing to the GPIOx_BSRR or GPIOx_BRR
|
|
registers (x = A..F).</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OD7</name>
|
|
<description>Port output data bit These bits can be
|
|
read and written by software. Note: For atomic bit
|
|
set/reset, the OD bits can be individually set and/or
|
|
reset by writing to the GPIOx_BSRR or GPIOx_BRR
|
|
registers (x = A..F).</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OD8</name>
|
|
<description>Port output data bit These bits can be
|
|
read and written by software. Note: For atomic bit
|
|
set/reset, the OD bits can be individually set and/or
|
|
reset by writing to the GPIOx_BSRR or GPIOx_BRR
|
|
registers (x = A..F).</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OD9</name>
|
|
<description>Port output data bit These bits can be
|
|
read and written by software. Note: For atomic bit
|
|
set/reset, the OD bits can be individually set and/or
|
|
reset by writing to the GPIOx_BSRR or GPIOx_BRR
|
|
registers (x = A..F).</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OD10</name>
|
|
<description>Port output data bit These bits can be
|
|
read and written by software. Note: For atomic bit
|
|
set/reset, the OD bits can be individually set and/or
|
|
reset by writing to the GPIOx_BSRR or GPIOx_BRR
|
|
registers (x = A..F).</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OD11</name>
|
|
<description>Port output data bit These bits can be
|
|
read and written by software. Note: For atomic bit
|
|
set/reset, the OD bits can be individually set and/or
|
|
reset by writing to the GPIOx_BSRR or GPIOx_BRR
|
|
registers (x = A..F).</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OD12</name>
|
|
<description>Port output data bit These bits can be
|
|
read and written by software. Note: For atomic bit
|
|
set/reset, the OD bits can be individually set and/or
|
|
reset by writing to the GPIOx_BSRR or GPIOx_BRR
|
|
registers (x = A..F).</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OD13</name>
|
|
<description>Port output data bit These bits can be
|
|
read and written by software. Note: For atomic bit
|
|
set/reset, the OD bits can be individually set and/or
|
|
reset by writing to the GPIOx_BSRR or GPIOx_BRR
|
|
registers (x = A..F).</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OD14</name>
|
|
<description>Port output data bit These bits can be
|
|
read and written by software. Note: For atomic bit
|
|
set/reset, the OD bits can be individually set and/or
|
|
reset by writing to the GPIOx_BSRR or GPIOx_BRR
|
|
registers (x = A..F).</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OD15</name>
|
|
<description>Port output data bit These bits can be
|
|
read and written by software. Note: For atomic bit
|
|
set/reset, the OD bits can be individually set and/or
|
|
reset by writing to the GPIOx_BSRR or GPIOx_BRR
|
|
registers (x = A..F).</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BSRR</name>
|
|
<displayName>BSRR</displayName>
|
|
<description>GPIO port bit set/reset
|
|
register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>0x20</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BS0</name>
|
|
<description>Port x set bit y (y= 0..15) These bits
|
|
are write-only. A read to these bits returns the
|
|
value 0x0000.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BS1</name>
|
|
<description>Port x set bit y (y= 0..15) These bits
|
|
are write-only. A read to these bits returns the
|
|
value 0x0000.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BS2</name>
|
|
<description>Port x set bit y (y= 0..15) These bits
|
|
are write-only. A read to these bits returns the
|
|
value 0x0000.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BS3</name>
|
|
<description>Port x set bit y (y= 0..15) These bits
|
|
are write-only. A read to these bits returns the
|
|
value 0x0000.</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BS4</name>
|
|
<description>Port x set bit y (y= 0..15) These bits
|
|
are write-only. A read to these bits returns the
|
|
value 0x0000.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BS5</name>
|
|
<description>Port x set bit y (y= 0..15) These bits
|
|
are write-only. A read to these bits returns the
|
|
value 0x0000.</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BS6</name>
|
|
<description>Port x set bit y (y= 0..15) These bits
|
|
are write-only. A read to these bits returns the
|
|
value 0x0000.</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BS7</name>
|
|
<description>Port x set bit y (y= 0..15) These bits
|
|
are write-only. A read to these bits returns the
|
|
value 0x0000.</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BS8</name>
|
|
<description>Port x set bit y (y= 0..15) These bits
|
|
are write-only. A read to these bits returns the
|
|
value 0x0000.</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BS9</name>
|
|
<description>Port x set bit y (y= 0..15) These bits
|
|
are write-only. A read to these bits returns the
|
|
value 0x0000.</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BS10</name>
|
|
<description>Port x set bit y (y= 0..15) These bits
|
|
are write-only. A read to these bits returns the
|
|
value 0x0000.</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BS11</name>
|
|
<description>Port x set bit y (y= 0..15) These bits
|
|
are write-only. A read to these bits returns the
|
|
value 0x0000.</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BS12</name>
|
|
<description>Port x set bit y (y= 0..15) These bits
|
|
are write-only. A read to these bits returns the
|
|
value 0x0000.</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BS13</name>
|
|
<description>Port x set bit y (y= 0..15) These bits
|
|
are write-only. A read to these bits returns the
|
|
value 0x0000.</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BS14</name>
|
|
<description>Port x set bit y (y= 0..15) These bits
|
|
are write-only. A read to these bits returns the
|
|
value 0x0000.</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BS15</name>
|
|
<description>Port x set bit y (y= 0..15) These bits
|
|
are write-only. A read to these bits returns the
|
|
value 0x0000.</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR0</name>
|
|
<description>Port x reset bit y (y = 0..15) These
|
|
bits are write-only. A read to these bits returns the
|
|
value 0x0000. Note: If both BSx and BRx are set, BSx
|
|
has priority.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR1</name>
|
|
<description>Port x reset bit y (y = 0..15) These
|
|
bits are write-only. A read to these bits returns the
|
|
value 0x0000. Note: If both BSx and BRx are set, BSx
|
|
has priority.</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR2</name>
|
|
<description>Port x reset bit y (y = 0..15) These
|
|
bits are write-only. A read to these bits returns the
|
|
value 0x0000. Note: If both BSx and BRx are set, BSx
|
|
has priority.</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR3</name>
|
|
<description>Port x reset bit y (y = 0..15) These
|
|
bits are write-only. A read to these bits returns the
|
|
value 0x0000. Note: If both BSx and BRx are set, BSx
|
|
has priority.</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR4</name>
|
|
<description>Port x reset bit y (y = 0..15) These
|
|
bits are write-only. A read to these bits returns the
|
|
value 0x0000. Note: If both BSx and BRx are set, BSx
|
|
has priority.</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR5</name>
|
|
<description>Port x reset bit y (y = 0..15) These
|
|
bits are write-only. A read to these bits returns the
|
|
value 0x0000. Note: If both BSx and BRx are set, BSx
|
|
has priority.</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR6</name>
|
|
<description>Port x reset bit y (y = 0..15) These
|
|
bits are write-only. A read to these bits returns the
|
|
value 0x0000. Note: If both BSx and BRx are set, BSx
|
|
has priority.</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR7</name>
|
|
<description>Port x reset bit y (y = 0..15) These
|
|
bits are write-only. A read to these bits returns the
|
|
value 0x0000. Note: If both BSx and BRx are set, BSx
|
|
has priority.</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR8</name>
|
|
<description>Port x reset bit y (y = 0..15) These
|
|
bits are write-only. A read to these bits returns the
|
|
value 0x0000. Note: If both BSx and BRx are set, BSx
|
|
has priority.</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR9</name>
|
|
<description>Port x reset bit y (y = 0..15) These
|
|
bits are write-only. A read to these bits returns the
|
|
value 0x0000. Note: If both BSx and BRx are set, BSx
|
|
has priority.</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR10</name>
|
|
<description>Port x reset bit y (y = 0..15) These
|
|
bits are write-only. A read to these bits returns the
|
|
value 0x0000. Note: If both BSx and BRx are set, BSx
|
|
has priority.</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR11</name>
|
|
<description>Port x reset bit y (y = 0..15) These
|
|
bits are write-only. A read to these bits returns the
|
|
value 0x0000. Note: If both BSx and BRx are set, BSx
|
|
has priority.</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR12</name>
|
|
<description>Port x reset bit y (y = 0..15) These
|
|
bits are write-only. A read to these bits returns the
|
|
value 0x0000. Note: If both BSx and BRx are set, BSx
|
|
has priority.</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR13</name>
|
|
<description>Port x reset bit y (y = 0..15) These
|
|
bits are write-only. A read to these bits returns the
|
|
value 0x0000. Note: If both BSx and BRx are set, BSx
|
|
has priority.</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR14</name>
|
|
<description>Port x reset bit y (y = 0..15) These
|
|
bits are write-only. A read to these bits returns the
|
|
value 0x0000. Note: If both BSx and BRx are set, BSx
|
|
has priority.</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR15</name>
|
|
<description>Port x reset bit y (y = 0..15) These
|
|
bits are write-only. A read to these bits returns the
|
|
value 0x0000. Note: If both BSx and BRx are set, BSx
|
|
has priority.</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LCKR</name>
|
|
<displayName>LCKR</displayName>
|
|
<description>This register is used to lock the
|
|
configuration of the port bits when a correct write
|
|
sequence is applied to bit 16 (LCKK). The value of bits
|
|
[15:0] is used to lock the configuration of the GPIO.
|
|
During the write sequence, the value of LCKR[15:0] must
|
|
not change. When the LOCK sequence has been applied on a
|
|
port bit, the value of this port bit can no longer be
|
|
modified until the next MCU reset or peripheral reset.A
|
|
specific write sequence is used to write to the
|
|
GPIOx_LCKR register. Only word access (32-bit long) is
|
|
allowed during this locking sequence.Each lock bit
|
|
freezes a specific configuration register (control and
|
|
alternate function registers).</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LCK0</name>
|
|
<description>Port x lock bit y (y= 0..15) These bits
|
|
are read/write but can only be written when the LCKK
|
|
bit is 0.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LCK1</name>
|
|
<description>Port x lock bit y (y= 0..15) These bits
|
|
are read/write but can only be written when the LCKK
|
|
bit is 0.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LCK2</name>
|
|
<description>Port x lock bit y (y= 0..15) These bits
|
|
are read/write but can only be written when the LCKK
|
|
bit is 0.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LCK3</name>
|
|
<description>Port x lock bit y (y= 0..15) These bits
|
|
are read/write but can only be written when the LCKK
|
|
bit is 0.</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LCK4</name>
|
|
<description>Port x lock bit y (y= 0..15) These bits
|
|
are read/write but can only be written when the LCKK
|
|
bit is 0.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LCK5</name>
|
|
<description>Port x lock bit y (y= 0..15) These bits
|
|
are read/write but can only be written when the LCKK
|
|
bit is 0.</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LCK6</name>
|
|
<description>Port x lock bit y (y= 0..15) These bits
|
|
are read/write but can only be written when the LCKK
|
|
bit is 0.</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LCK7</name>
|
|
<description>Port x lock bit y (y= 0..15) These bits
|
|
are read/write but can only be written when the LCKK
|
|
bit is 0.</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LCK8</name>
|
|
<description>Port x lock bit y (y= 0..15) These bits
|
|
are read/write but can only be written when the LCKK
|
|
bit is 0.</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LCK9</name>
|
|
<description>Port x lock bit y (y= 0..15) These bits
|
|
are read/write but can only be written when the LCKK
|
|
bit is 0.</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LCK10</name>
|
|
<description>Port x lock bit y (y= 0..15) These bits
|
|
are read/write but can only be written when the LCKK
|
|
bit is 0.</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LCK11</name>
|
|
<description>Port x lock bit y (y= 0..15) These bits
|
|
are read/write but can only be written when the LCKK
|
|
bit is 0.</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LCK12</name>
|
|
<description>Port x lock bit y (y= 0..15) These bits
|
|
are read/write but can only be written when the LCKK
|
|
bit is 0.</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LCK13</name>
|
|
<description>Port x lock bit y (y= 0..15) These bits
|
|
are read/write but can only be written when the LCKK
|
|
bit is 0.</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LCK14</name>
|
|
<description>Port x lock bit y (y= 0..15) These bits
|
|
are read/write but can only be written when the LCKK
|
|
bit is 0.</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LCK15</name>
|
|
<description>Port x lock bit y (y= 0..15) These bits
|
|
are read/write but can only be written when the LCKK
|
|
bit is 0.</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LCKK</name>
|
|
<description>Lock key This bit can be read any time.
|
|
It can only be modified using the lock key write
|
|
sequence. LOCK key write sequence: WR LCKR[16] = 1 +
|
|
LCKR[15:0] WR LCKR[16] = 0 + LCKR[15:0] WR LCKR[16] =
|
|
1 + LCKR[15:0] RD LCKR RD LCKR[16] = 1 (this read
|
|
operation is optional but it confirms that the lock
|
|
is active) Note: During the LOCK key write sequence,
|
|
the value of LCK[15:0] must not change. Any error in
|
|
the lock sequence aborts the lock. After the first
|
|
lock sequence on any bit of the port, any read access
|
|
on the LCKK bit will return 1 until the next MCU
|
|
reset or peripheral reset.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AFRL</name>
|
|
<displayName>AFRL</displayName>
|
|
<description>GPIO alternate function low
|
|
register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>AFSEL0</name>
|
|
<description>[3:0]: Alternate function selection for
|
|
port x pin y (y = 0..7) These bits are written by
|
|
software to configure alternate function I/Os AFSELy
|
|
selection:</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AFSEL1</name>
|
|
<description>[3:0]: Alternate function selection for
|
|
port x pin y (y = 0..7) These bits are written by
|
|
software to configure alternate function I/Os AFSELy
|
|
selection:</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AFSEL2</name>
|
|
<description>[3:0]: Alternate function selection for
|
|
port x pin y (y = 0..7) These bits are written by
|
|
software to configure alternate function I/Os AFSELy
|
|
selection:</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AFSEL3</name>
|
|
<description>[3:0]: Alternate function selection for
|
|
port x pin y (y = 0..7) These bits are written by
|
|
software to configure alternate function I/Os AFSELy
|
|
selection:</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AFSEL4</name>
|
|
<description>[3:0]: Alternate function selection for
|
|
port x pin y (y = 0..7) These bits are written by
|
|
software to configure alternate function I/Os AFSELy
|
|
selection:</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AFSEL5</name>
|
|
<description>[3:0]: Alternate function selection for
|
|
port x pin y (y = 0..7) These bits are written by
|
|
software to configure alternate function I/Os AFSELy
|
|
selection:</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AFSEL6</name>
|
|
<description>[3:0]: Alternate function selection for
|
|
port x pin y (y = 0..7) These bits are written by
|
|
software to configure alternate function I/Os AFSELy
|
|
selection:</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AFSEL7</name>
|
|
<description>[3:0]: Alternate function selection for
|
|
port x pin y (y = 0..7) These bits are written by
|
|
software to configure alternate function I/Os AFSELy
|
|
selection:</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AFRH</name>
|
|
<displayName>AFRH</displayName>
|
|
<description>GPIO alternate function high
|
|
register</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>AFSEL8</name>
|
|
<description>[3:0]: Alternate function selection for
|
|
port x pin y (y = 8..15) These bits are written by
|
|
software to configure alternate function
|
|
I/Os</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AFSEL9</name>
|
|
<description>[3:0]: Alternate function selection for
|
|
port x pin y (y = 8..15) These bits are written by
|
|
software to configure alternate function
|
|
I/Os</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AFSEL10</name>
|
|
<description>[3:0]: Alternate function selection for
|
|
port x pin y (y = 8..15) These bits are written by
|
|
software to configure alternate function
|
|
I/Os</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AFSEL11</name>
|
|
<description>[3:0]: Alternate function selection for
|
|
port x pin y (y = 8..15) These bits are written by
|
|
software to configure alternate function
|
|
I/Os</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AFSEL12</name>
|
|
<description>[3:0]: Alternate function selection for
|
|
port x pin y (y = 8..15) These bits are written by
|
|
software to configure alternate function
|
|
I/Os</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AFSEL13</name>
|
|
<description>[3:0]: Alternate function selection for
|
|
port x pin y (y = 8..15) These bits are written by
|
|
software to configure alternate function
|
|
I/Os</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AFSEL14</name>
|
|
<description>[3:0]: Alternate function selection for
|
|
port x pin y (y = 8..15) These bits are written by
|
|
software to configure alternate function
|
|
I/Os</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AFSEL15</name>
|
|
<description>[3:0]: Alternate function selection for
|
|
port x pin y (y = 8..15) These bits are written by
|
|
software to configure alternate function
|
|
I/Os</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral derivedFrom="GPIOA">
|
|
<name>GPIOB</name>
|
|
<baseAddress>0x58020400</baseAddress>
|
|
</peripheral>
|
|
<peripheral derivedFrom="GPIOA">
|
|
<name>GPIOC</name>
|
|
<baseAddress>0x58020800</baseAddress>
|
|
</peripheral>
|
|
<peripheral derivedFrom="GPIOA">
|
|
<name>GPIOD</name>
|
|
<baseAddress>0x58020C00</baseAddress>
|
|
</peripheral>
|
|
<peripheral derivedFrom="GPIOA">
|
|
<name>GPIOE</name>
|
|
<baseAddress>0x58021000</baseAddress>
|
|
</peripheral>
|
|
<peripheral derivedFrom="GPIOA">
|
|
<name>GPIOF</name>
|
|
<baseAddress>0x58021400</baseAddress>
|
|
</peripheral>
|
|
<peripheral derivedFrom="GPIOA">
|
|
<name>GPIOG</name>
|
|
<baseAddress>0x58021800</baseAddress>
|
|
</peripheral>
|
|
<peripheral derivedFrom="GPIOA">
|
|
<name>GPIOH</name>
|
|
<baseAddress>0x58021C00</baseAddress>
|
|
</peripheral>
|
|
<peripheral derivedFrom="GPIOA">
|
|
<name>GPIOI</name>
|
|
<baseAddress>0x58022000</baseAddress>
|
|
</peripheral>
|
|
<peripheral derivedFrom="GPIOA">
|
|
<name>GPIOJ</name>
|
|
<baseAddress>0x58022400</baseAddress>
|
|
</peripheral>
|
|
<peripheral derivedFrom="GPIOA">
|
|
<name>GPIOK</name>
|
|
<baseAddress>0x58022800</baseAddress>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>JPEG</name>
|
|
<description>JPEG</description>
|
|
<groupName>JPEG</groupName>
|
|
<baseAddress>0x52003000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>JPEG</name>
|
|
<description>JPEG global interrupt</description>
|
|
<value>121</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CONFR0</name>
|
|
<displayName>CONFR0</displayName>
|
|
<description>JPEG codec control register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>START</name>
|
|
<description>Start This bit start or stop the
|
|
encoding or decoding process. Read this register
|
|
always return 0.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CONFR1</name>
|
|
<displayName>CONFR1</displayName>
|
|
<description>JPEG codec configuration register
|
|
1</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>NF</name>
|
|
<description>Number of color components This field
|
|
defines the number of color components minus
|
|
1.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DE</name>
|
|
<description>Decoding Enable This bit selects the
|
|
coding or decoding process</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>COLORSPACE</name>
|
|
<description>Color Space This filed defines the
|
|
number of quantization tables minus 1 to insert in
|
|
the output stream.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NS</name>
|
|
<description>Number of components for Scan This field
|
|
defines the number of components minus 1 for scan
|
|
header marker segment.</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HDR</name>
|
|
<description>Header Processing This bit enable the
|
|
header processing (generation/parsing).</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>YSIZE</name>
|
|
<description>Y Size This field defines the number of
|
|
lines in source image.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CONFR2</name>
|
|
<displayName>CONFR2</displayName>
|
|
<description>JPEG codec configuration register
|
|
2</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>NMCU</name>
|
|
<description>Number of MCU For encoding: this field
|
|
defines the number of MCU units minus 1 to encode.
|
|
For decoding: this field indicates the number of
|
|
complete MCU units minus 1 to be decoded (this field
|
|
is updated after the JPEG header parsing). If the
|
|
decoded image size has not a X or Y size multiple of
|
|
8 or 16 (depending on the sub-sampling process), the
|
|
resulting incomplete or empty MCU must be added to
|
|
this value to get the total number of MCU
|
|
generated.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>26</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CONFR3</name>
|
|
<displayName>CONFR3</displayName>
|
|
<description>JPEG codec configuration register
|
|
3</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>XSIZE</name>
|
|
<description>X size This field defines the number of
|
|
pixels per line.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CONFRN1</name>
|
|
<displayName>CONFRN1</displayName>
|
|
<description>JPEG codec configuration register
|
|
4-7</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>HD</name>
|
|
<description>Huffman DC Selects the Huffman table for
|
|
encoding the DC coefficients.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HA</name>
|
|
<description>Huffman AC Selects the Huffman table for
|
|
encoding the AC coefficients.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>QT</name>
|
|
<description>Quantization Table Selects quantization
|
|
table associated with a color
|
|
component.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NB</name>
|
|
<description>Number of Block Number of data units
|
|
minus 1 that belong to a particular color in the
|
|
MCU.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>VSF</name>
|
|
<description>Vertical Sampling Factor Vertical
|
|
sampling factor for component i.</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HSF</name>
|
|
<description>Horizontal Sampling Factor Horizontal
|
|
sampling factor for component i.</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CONFRN2</name>
|
|
<displayName>CONFRN2</displayName>
|
|
<description>JPEG codec configuration register
|
|
4-7</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>HD</name>
|
|
<description>Huffman DC Selects the Huffman table for
|
|
encoding the DC coefficients.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HA</name>
|
|
<description>Huffman AC Selects the Huffman table for
|
|
encoding the AC coefficients.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>QT</name>
|
|
<description>Quantization Table Selects quantization
|
|
table associated with a color
|
|
component.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NB</name>
|
|
<description>Number of Block Number of data units
|
|
minus 1 that belong to a particular color in the
|
|
MCU.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>VSF</name>
|
|
<description>Vertical Sampling Factor Vertical
|
|
sampling factor for component i.</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HSF</name>
|
|
<description>Horizontal Sampling Factor Horizontal
|
|
sampling factor for component i.</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CONFRN3</name>
|
|
<displayName>CONFRN3</displayName>
|
|
<description>JPEG codec configuration register
|
|
4-7</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>HD</name>
|
|
<description>Huffman DC Selects the Huffman table for
|
|
encoding the DC coefficients.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HA</name>
|
|
<description>Huffman AC Selects the Huffman table for
|
|
encoding the AC coefficients.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>QT</name>
|
|
<description>Quantization Table Selects quantization
|
|
table associated with a color
|
|
component.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NB</name>
|
|
<description>Number of Block Number of data units
|
|
minus 1 that belong to a particular color in the
|
|
MCU.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>VSF</name>
|
|
<description>Vertical Sampling Factor Vertical
|
|
sampling factor for component i.</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HSF</name>
|
|
<description>Horizontal Sampling Factor Horizontal
|
|
sampling factor for component i.</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CONFRN4</name>
|
|
<displayName>CONFRN4</displayName>
|
|
<description>JPEG codec configuration register
|
|
4-7</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>HD</name>
|
|
<description>Huffman DC Selects the Huffman table for
|
|
encoding the DC coefficients.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HA</name>
|
|
<description>Huffman AC Selects the Huffman table for
|
|
encoding the AC coefficients.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>QT</name>
|
|
<description>Quantization Table Selects quantization
|
|
table associated with a color
|
|
component.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NB</name>
|
|
<description>Number of Block Number of data units
|
|
minus 1 that belong to a particular color in the
|
|
MCU.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>VSF</name>
|
|
<description>Vertical Sampling Factor Vertical
|
|
sampling factor for component i.</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HSF</name>
|
|
<description>Horizontal Sampling Factor Horizontal
|
|
sampling factor for component i.</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CR</name>
|
|
<displayName>CR</displayName>
|
|
<description>JPEG control register</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>JCEN</name>
|
|
<description>JPEG Core Enable Enable the JPEG codec
|
|
Core.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IFTIE</name>
|
|
<description>Input FIFO Threshold Interrupt Enable
|
|
This bit enables the interrupt generation when input
|
|
FIFO reach the threshold.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IFNFIE</name>
|
|
<description>Input FIFO Not Full Interrupt Enable
|
|
This bit enables the interrupt generation when input
|
|
FIFO is not empty.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OFTIE</name>
|
|
<description>Output FIFO Threshold Interrupt Enable
|
|
This bit enables the interrupt generation when output
|
|
FIFO reach the threshold.</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OFNEIE</name>
|
|
<description>Output FIFO Not Empty Interrupt Enable
|
|
This bit enables the interrupt generation when output
|
|
FIFO is not empty.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EOCIE</name>
|
|
<description>End of Conversion Interrupt Enable This
|
|
bit enables the interrupt generation on the end of
|
|
conversion.</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HPDIE</name>
|
|
<description>Header Parsing Done Interrupt Enable
|
|
This bit enables the interrupt generation on the
|
|
Header Parsing Operation.</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IDMAEN</name>
|
|
<description>Input DMA Enable Enable the DMA request
|
|
generation for the input FIFO.</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ODMAEN</name>
|
|
<description>Output DMA Enable Enable the DMA request
|
|
generation for the output FIFO.</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IFF</name>
|
|
<description>Input FIFO Flush This bit flush the
|
|
input FIFO. This bit is always read as
|
|
0.</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OFF</name>
|
|
<description>Output FIFO Flush This bit flush the
|
|
output FIFO. This bit is always read as
|
|
0.</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SR</name>
|
|
<displayName>SR</displayName>
|
|
<description>JPEG status register</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000006</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IFTF</name>
|
|
<description>Input FIFO Threshold Flag This bit is
|
|
set when the input FIFO is not full and is bellow its
|
|
threshold.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IFNFF</name>
|
|
<description>Input FIFO Not Full Flag This bit is set
|
|
when the input FIFO is not full (a data can be
|
|
written).</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OFTF</name>
|
|
<description>Output FIFO Threshold Flag This bit is
|
|
set when the output FIFO is not empty and has reach
|
|
its threshold.</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OFNEF</name>
|
|
<description>Output FIFO Not Empty Flag This bit is
|
|
set when the output FIFO is not empty (a data is
|
|
available).</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EOCF</name>
|
|
<description>End of Conversion Flag This bit is set
|
|
when the JPEG codec core has finished the encoding or
|
|
the decoding process and than last data has been sent
|
|
to the output FIFO.</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HPDF</name>
|
|
<description>Header Parsing Done Flag This bit is set
|
|
in decode mode when the JPEG codec has finished the
|
|
parsing of the headers and the internal registers
|
|
have been updated.</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>COF</name>
|
|
<description>Codec Operation Flag This bit is set
|
|
when when a JPEG codec operation is on going
|
|
(encoding or decoding).</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CFR</name>
|
|
<displayName>CFR</displayName>
|
|
<description>JPEG clear flag register</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CEOCF</name>
|
|
<description>Clear End of Conversion Flag Writing 1
|
|
clears the End of Conversion Flag of the JPEG Status
|
|
Register.</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHPDF</name>
|
|
<description>Clear Header Parsing Done Flag Writing 1
|
|
clears the Header Parsing Done Flag of the JPEG
|
|
Status Register.</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIR</name>
|
|
<displayName>DIR</displayName>
|
|
<description>JPEG data input register</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>0x20</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DATAIN</name>
|
|
<description>Data Input FIFO Input FIFO data
|
|
register.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DOR</name>
|
|
<displayName>DOR</displayName>
|
|
<description>JPEG data output register</description>
|
|
<addressOffset>0x44</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DATAOUT</name>
|
|
<description>Data Output FIFO Output FIFO data
|
|
register.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>MDMA</name>
|
|
<description>MDMA</description>
|
|
<groupName>MDMA</groupName>
|
|
<baseAddress>0x52000000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x1000</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>MDMA</name>
|
|
<description>MDMA</description>
|
|
<value>122</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>MDMA_GISR0</name>
|
|
<displayName>MDMA_GISR0</displayName>
|
|
<description>MDMA Global Interrupt/Status
|
|
Register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>GIF0</name>
|
|
<description>Channel x global interrupt flag (x=...)
|
|
This bit is set and reset by hardware. It is a
|
|
logical OR of all the Channel x interrupt flags
|
|
(CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in
|
|
the interrupt mask register (CTCIEx, BTIEx, BRTIEx,
|
|
TEIEx)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GIF1</name>
|
|
<description>Channel x global interrupt flag (x=...)
|
|
This bit is set and reset by hardware. It is a
|
|
logical OR of all the Channel x interrupt flags
|
|
(CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in
|
|
the interrupt mask register (CTCIEx, BTIEx, BRTIEx,
|
|
TEIEx)</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GIF2</name>
|
|
<description>Channel x global interrupt flag (x=...)
|
|
This bit is set and reset by hardware. It is a
|
|
logical OR of all the Channel x interrupt flags
|
|
(CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in
|
|
the interrupt mask register (CTCIEx, BTIEx, BRTIEx,
|
|
TEIEx)</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GIF3</name>
|
|
<description>Channel x global interrupt flag (x=...)
|
|
This bit is set and reset by hardware. It is a
|
|
logical OR of all the Channel x interrupt flags
|
|
(CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in
|
|
the interrupt mask register (CTCIEx, BTIEx, BRTIEx,
|
|
TEIEx)</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GIF4</name>
|
|
<description>Channel x global interrupt flag (x=...)
|
|
This bit is set and reset by hardware. It is a
|
|
logical OR of all the Channel x interrupt flags
|
|
(CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in
|
|
the interrupt mask register (CTCIEx, BTIEx, BRTIEx,
|
|
TEIEx)</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GIF5</name>
|
|
<description>Channel x global interrupt flag (x=...)
|
|
This bit is set and reset by hardware. It is a
|
|
logical OR of all the Channel x interrupt flags
|
|
(CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in
|
|
the interrupt mask register (CTCIEx, BTIEx, BRTIEx,
|
|
TEIEx)</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GIF6</name>
|
|
<description>Channel x global interrupt flag (x=...)
|
|
This bit is set and reset by hardware. It is a
|
|
logical OR of all the Channel x interrupt flags
|
|
(CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in
|
|
the interrupt mask register (CTCIEx, BTIEx, BRTIEx,
|
|
TEIEx)</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GIF7</name>
|
|
<description>Channel x global interrupt flag (x=...)
|
|
This bit is set and reset by hardware. It is a
|
|
logical OR of all the Channel x interrupt flags
|
|
(CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in
|
|
the interrupt mask register (CTCIEx, BTIEx, BRTIEx,
|
|
TEIEx)</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GIF8</name>
|
|
<description>Channel x global interrupt flag (x=...)
|
|
This bit is set and reset by hardware. It is a
|
|
logical OR of all the Channel x interrupt flags
|
|
(CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in
|
|
the interrupt mask register (CTCIEx, BTIEx, BRTIEx,
|
|
TEIEx)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GIF9</name>
|
|
<description>Channel x global interrupt flag (x=...)
|
|
This bit is set and reset by hardware. It is a
|
|
logical OR of all the Channel x interrupt flags
|
|
(CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in
|
|
the interrupt mask register (CTCIEx, BTIEx, BRTIEx,
|
|
TEIEx)</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GIF10</name>
|
|
<description>Channel x global interrupt flag (x=...)
|
|
This bit is set and reset by hardware. It is a
|
|
logical OR of all the Channel x interrupt flags
|
|
(CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in
|
|
the interrupt mask register (CTCIEx, BTIEx, BRTIEx,
|
|
TEIEx)</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GIF11</name>
|
|
<description>Channel x global interrupt flag (x=...)
|
|
This bit is set and reset by hardware. It is a
|
|
logical OR of all the Channel x interrupt flags
|
|
(CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in
|
|
the interrupt mask register (CTCIEx, BTIEx, BRTIEx,
|
|
TEIEx)</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GIF12</name>
|
|
<description>Channel x global interrupt flag (x=...)
|
|
This bit is set and reset by hardware. It is a
|
|
logical OR of all the Channel x interrupt flags
|
|
(CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in
|
|
the interrupt mask register (CTCIEx, BTIEx, BRTIEx,
|
|
TEIEx)</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GIF13</name>
|
|
<description>Channel x global interrupt flag (x=...)
|
|
This bit is set and reset by hardware. It is a
|
|
logical OR of all the Channel x interrupt flags
|
|
(CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in
|
|
the interrupt mask register (CTCIEx, BTIEx, BRTIEx,
|
|
TEIEx)</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GIF14</name>
|
|
<description>Channel x global interrupt flag (x=...)
|
|
This bit is set and reset by hardware. It is a
|
|
logical OR of all the Channel x interrupt flags
|
|
(CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in
|
|
the interrupt mask register (CTCIEx, BTIEx, BRTIEx,
|
|
TEIEx)</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GIF15</name>
|
|
<description>Channel x global interrupt flag (x=...)
|
|
This bit is set and reset by hardware. It is a
|
|
logical OR of all the Channel x interrupt flags
|
|
(CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in
|
|
the interrupt mask register (CTCIEx, BTIEx, BRTIEx,
|
|
TEIEx)</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MDMA_C0ISR</name>
|
|
<displayName>MDMA_C0ISR</displayName>
|
|
<description>MDMA channel x interrupt/status
|
|
register</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TEIF0</name>
|
|
<description>Channel x transfer error interrupt flag
|
|
This bit is set by hardware. It is cleared by
|
|
software writing 1 to the corresponding bit in the
|
|
DMA_IFCRy register.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTCIF0</name>
|
|
<description>Channel x Channel Transfer Complete
|
|
interrupt flag This bit is set by hardware. It is
|
|
cleared by software writing 1 to the corresponding
|
|
bit in the DMA_IFCRy register. CTC is set when the
|
|
last block was transferred and the channel has been
|
|
automatically disabled. CTC is also set when the
|
|
channel is suspended, as a result of writing EN bit
|
|
to 0.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BRTIF0</name>
|
|
<description>Channel x block repeat transfer complete
|
|
interrupt flag This bit is set by hardware. It is
|
|
cleared by software writing 1 to the corresponding
|
|
bit in the DMA_IFCRy register.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BTIF0</name>
|
|
<description>Channel x block transfer complete
|
|
interrupt flag This bit is set by hardware. It is
|
|
cleared by software writing 1 to the corresponding
|
|
bit in the DMA_IFCRy register.</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCIF0</name>
|
|
<description>channel x buffer transfer
|
|
complete</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CRQA0</name>
|
|
<description>channel x request active
|
|
flag</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MDMA_C0IFCR</name>
|
|
<displayName>MDMA_C0IFCR</displayName>
|
|
<description>MDMA channel x interrupt flag clear
|
|
register</description>
|
|
<addressOffset>0x44</addressOffset>
|
|
<size>0x20</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CTEIF0</name>
|
|
<description>Channel x clear transfer error interrupt
|
|
flag Writing a 1 into this bit clears TEIFx in the
|
|
MDMA_ISRy register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CCTCIF0</name>
|
|
<description>Clear Channel transfer complete
|
|
interrupt flag for channel x Writing a 1 into this
|
|
bit clears CTCIFx in the MDMA_ISRy
|
|
register</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CBRTIF0</name>
|
|
<description>Channel x clear block repeat transfer
|
|
complete interrupt flag Writing a 1 into this bit
|
|
clears BRTIFx in the MDMA_ISRy register</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CBTIF0</name>
|
|
<description>Channel x Clear block transfer complete
|
|
interrupt flag Writing a 1 into this bit clears BTIFx
|
|
in the MDMA_ISRy register</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CLTCIF0</name>
|
|
<description>CLear buffer Transfer Complete Interrupt
|
|
Flag for channel x Writing a 1 into this bit clears
|
|
TCIFx in the MDMA_ISRy register</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MDMA_C0ESR</name>
|
|
<displayName>MDMA_C0ESR</displayName>
|
|
<description>MDMA Channel x error status
|
|
register</description>
|
|
<addressOffset>0x48</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TEA</name>
|
|
<description>Transfer Error Address These bits are
|
|
set and cleared by HW, in case of an MDMA data
|
|
transfer error. It is used in conjunction with TED.
|
|
This field indicates the 7 LSBits of the address
|
|
which generated a transfer/access error. It may be
|
|
used by SW to retrieve the failing address, by adding
|
|
this value (truncated to the buffer transfer length
|
|
size) to the current SAR/DAR value. Note: The SAR/DAR
|
|
current value doesnt reflect this last address due to
|
|
the FIFO management system. The SAR/DAR are only
|
|
updated at the end of a (buffer) transfer (of TLEN+1
|
|
bytes). Note: It is not set in case of a link data
|
|
error.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TED</name>
|
|
<description>Transfer Error Direction These bit is
|
|
set and cleared by HW, in case of an MDMA data
|
|
transfer error.</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TELD</name>
|
|
<description>Transfer Error Link Data These bit is
|
|
set by HW, in case of a transfer error while reading
|
|
the block link data structure. It is cleared by
|
|
software writing 1 to the CTEIFx bit in the DMA_IFCRy
|
|
register.</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TEMD</name>
|
|
<description>Transfer Error Mask Data These bit is
|
|
set by HW, in case of a transfer error while writing
|
|
the Mask Data. It is cleared by software writing 1 to
|
|
the CTEIFx bit in the DMA_IFCRy
|
|
register.</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ASE</name>
|
|
<description>Address/Size Error These bit is set by
|
|
HW, when the programmed address is not aligned with
|
|
the data size. TED will indicate whether the problem
|
|
is on the source or destination. It is cleared by
|
|
software writing 1 to the CTEIFx bit in the DMA_IFCRy
|
|
register.</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BSE</name>
|
|
<description>Block Size Error These bit is set by HW,
|
|
when the block size is not an integer multiple of the
|
|
data size either for source or destination. TED will
|
|
indicate whether the problem is on the source or
|
|
destination. It is cleared by software writing 1 to
|
|
the CTEIFx bit in the DMA_IFCRy
|
|
register.</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MDMA_C0CR</name>
|
|
<displayName>MDMA_C0CR</displayName>
|
|
<description>This register is used to control the
|
|
concerned channel.</description>
|
|
<addressOffset>0x4C</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EN</name>
|
|
<description>channel enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TEIE</name>
|
|
<description>Transfer error interrupt enable This bit
|
|
is set and cleared by software.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CTCIE</name>
|
|
<description>Channel Transfer Complete interrupt
|
|
enable This bit is set and cleared by
|
|
software.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BRTIE</name>
|
|
<description>Block Repeat transfer interrupt enable
|
|
This bit is set and cleared by
|
|
software.</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BTIE</name>
|
|
<description>Block Transfer interrupt enable This bit
|
|
is set and cleared by software.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TCIE</name>
|
|
<description>buffer Transfer Complete interrupt
|
|
enable This bit is set and cleared by
|
|
software.</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PL</name>
|
|
<description>Priority level These bits are set and
|
|
cleared by software. These bits are protected and can
|
|
be written only if EN is 0.</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BEX</name>
|
|
<description>byte Endianness exchange</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HEX</name>
|
|
<description>Half word Endianes
|
|
exchange</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WEX</name>
|
|
<description>Word Endianness exchange</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SWRQ</name>
|
|
<description>SW ReQuest Writing a 1 into this bit
|
|
sets the CRQAx in MDMA_ISRy register, activating the
|
|
request on Channel x Note: Either the whole CxCR
|
|
register or the 8-bit/16-bit register @ Address
|
|
offset: 0x4E + 0x40 chn may be used for SWRQ
|
|
activation. In case of a SW request, acknowledge is
|
|
not generated (neither HW signal, nor CxMAR write
|
|
access).</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MDMA_C0TCR</name>
|
|
<displayName>MDMA_C0TCR</displayName>
|
|
<description>This register is used to configure the
|
|
concerned channel.</description>
|
|
<addressOffset>0x50</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SINC</name>
|
|
<description>Source increment mode These bits are set
|
|
and cleared by software. These bits are protected and
|
|
can be written only if EN is 0 Note: When source is
|
|
AHB (SBUS=1), SINC = 00 is forbidden. In Linked List
|
|
Mode, at the end of a block (single or last block in
|
|
repeated block transfer mode), this register will be
|
|
loaded from memory (from address given by current
|
|
LAR[31:0] + 0x00).</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DINC</name>
|
|
<description>Destination increment mode These bits
|
|
are set and cleared by software. These bits are
|
|
protected and can be written only if EN is 0 Note:
|
|
When destination is AHB (DBUS=1), DINC = 00 is
|
|
forbidden.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SSIZE</name>
|
|
<description>Source data size These bits are set and
|
|
cleared by software. These bits are protected and can
|
|
be written only if EN is 0 Note: If a value of 11 is
|
|
programmed for the TCM access/AHB port, a transfer
|
|
error will occur (TEIF bit set) If SINCOS &lt;
|
|
SSIZE and SINC &#8800; 00, the result will be
|
|
unpredictable. Note: SSIZE = 11 (double-word) is
|
|
forbidden when source is TCM/AHB bus
|
|
(SBUS=1).</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DSIZE</name>
|
|
<description>Destination data size These bits are set
|
|
and cleared by software. These bits are protected and
|
|
can be written only if EN is 0. Note: If a value of
|
|
11 is programmed for the TCM access/AHB port, a
|
|
transfer error will occur (TEIF bit set) If DINCOS
|
|
&lt; DSIZE and DINC &#8800; 00, the result
|
|
will be unpredictable. Note: DSIZE = 11 (double-word)
|
|
is forbidden when destination is TCM/AHB bus
|
|
(DBUS=1).</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SINCOS</name>
|
|
<description>source increment offset
|
|
size</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DINCOS</name>
|
|
<description>Destination increment
|
|
offset</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SBURST</name>
|
|
<description>source burst transfer
|
|
configuration</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DBURST</name>
|
|
<description>Destination burst transfer
|
|
configuration</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TLEN</name>
|
|
<description>buffer transfer lengh</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PKE</name>
|
|
<description>PacK Enable These bit is set and cleared
|
|
by software. If the Source Size is smaller than the
|
|
destination, it will be padded according to the PAM
|
|
value. If the Source data size is larger than the
|
|
destination one, it will be truncated. The alignment
|
|
will be done according to the PAM[0] value. This bit
|
|
is protected and can be written only if EN is
|
|
0</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PAM</name>
|
|
<description>Padding/Alignement Mode These bits are
|
|
set and cleared by software. Case 1: Source data size
|
|
smaller than destination data size - 3 options are
|
|
valid. Case 2: Source data size larger than
|
|
destination data size. The remainder part is
|
|
discarded. When PKE = 1 or DSIZE=SSIZE, these bits
|
|
are ignored. These bits are protected and can be
|
|
written only if EN is 0</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TRGM</name>
|
|
<description>Trigger Mode These bits are set and
|
|
cleared by software. Note: If TRGM is 11 for the
|
|
current block, all the values loaded at the end of
|
|
the current block through the linked list mechanism
|
|
must keep the same value (TRGM=11) and the same SWRM
|
|
value, otherwise the result is undefined. These bits
|
|
are protected and can be written only if EN is
|
|
0.</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWRM</name>
|
|
<description>SW Request Mode This bit is set and
|
|
cleared by software. If a HW or SW request is
|
|
currently active, the bit change will be delayed
|
|
until the current transfer is completed. If the CxMAR
|
|
contains a valid address, the CxMDR value will also
|
|
be written @ CxMAR address. This bit is protected and
|
|
can be written only if EN is 0.</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BWM</name>
|
|
<description>Bufferable Write Mode This bit is set
|
|
and cleared by software. This bit is protected and
|
|
can be written only if EN is 0. Note: All MDMA
|
|
destination accesses are non-cacheable.</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MDMA_C0BNDTR</name>
|
|
<displayName>MDMA_C0BNDTR</displayName>
|
|
<description>MDMA Channel x block number of data
|
|
register</description>
|
|
<addressOffset>0x54</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BNDT</name>
|
|
<description>block number of data to
|
|
transfer</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>17</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BRSUM</name>
|
|
<description>Block Repeat Source address Update Mode
|
|
These bits are protected and can be written only if
|
|
EN is 0.</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BRDUM</name>
|
|
<description>Block Repeat Destination address Update
|
|
Mode These bits are protected and can be written only
|
|
if EN is 0.</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BRC</name>
|
|
<description>Block Repeat Count This field contains
|
|
the number of repetitions of the current block (0 to
|
|
4095). When the channel is enabled, this register is
|
|
read-only, indicating the remaining number of blocks,
|
|
excluding the current one. This register decrements
|
|
after each complete block transfer. Once the last
|
|
block transfer has completed, this register can
|
|
either stay at zero or be reloaded automatically from
|
|
memory (in Linked List mode - i.e. Link Address
|
|
valid). These bits are protected and can be written
|
|
only if EN is 0.</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MDMA_C0SAR</name>
|
|
<displayName>MDMA_C0SAR</displayName>
|
|
<description>MDMA channel x source address
|
|
register</description>
|
|
<addressOffset>0x58</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SAR</name>
|
|
<description>source adr base</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MDMA_C0DAR</name>
|
|
<displayName>MDMA_C0DAR</displayName>
|
|
<description>MDMA channel x destination address
|
|
register</description>
|
|
<addressOffset>0x5C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DAR</name>
|
|
<description>Destination adr base</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MDMA_C0BRUR</name>
|
|
<displayName>MDMA_C0BRUR</displayName>
|
|
<description>MDMA channel x Block Repeat address Update
|
|
register</description>
|
|
<addressOffset>0x60</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SUV</name>
|
|
<description>source adresse update
|
|
value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DUV</name>
|
|
<description>destination address update</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MDMA_C0LAR</name>
|
|
<displayName>MDMA_C0LAR</displayName>
|
|
<description>MDMA channel x Link Address
|
|
register</description>
|
|
<addressOffset>0x64</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LAR</name>
|
|
<description>Link address register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MDMA_C0TBR</name>
|
|
<displayName>MDMA_C0TBR</displayName>
|
|
<description>MDMA channel x Trigger and Bus selection
|
|
Register</description>
|
|
<addressOffset>0x68</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TSEL</name>
|
|
<description>Trigger selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SBUS</name>
|
|
<description>Source BUS select This bit is protected
|
|
and can be written only if EN is 0.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DBUS</name>
|
|
<description>Destination BUS slect This bit is
|
|
protected and can be written only if EN is
|
|
0.</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MDMA_C0MAR</name>
|
|
<displayName>MDMA_C0MAR</displayName>
|
|
<description>MDMA channel x Mask address
|
|
register</description>
|
|
<addressOffset>0x70</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MAR</name>
|
|
<description>Mask address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MDMA_C0MDR</name>
|
|
<displayName>MDMA_C0MDR</displayName>
|
|
<description>MDMA channel x Mask Data
|
|
register</description>
|
|
<addressOffset>0x74</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MDR</name>
|
|
<description>Mask data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MDMA_C1ISR</name>
|
|
<displayName>MDMA_C1ISR</displayName>
|
|
<description>MDMA channel x interrupt/status
|
|
register</description>
|
|
<addressOffset>0x80</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TEIF1</name>
|
|
<description>Channel x transfer error interrupt flag
|
|
This bit is set by hardware. It is cleared by
|
|
software writing 1 to the corresponding bit in the
|
|
DMA_IFCRy register.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTCIF1</name>
|
|
<description>Channel x Channel Transfer Complete
|
|
interrupt flag This bit is set by hardware. It is
|
|
cleared by software writing 1 to the corresponding
|
|
bit in the DMA_IFCRy register. CTC is set when the
|
|
last block was transferred and the channel has been
|
|
automatically disabled. CTC is also set when the
|
|
channel is suspended, as a result of writing EN bit
|
|
to 0.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BRTIF1</name>
|
|
<description>Channel x block repeat transfer complete
|
|
interrupt flag This bit is set by hardware. It is
|
|
cleared by software writing 1 to the corresponding
|
|
bit in the DMA_IFCRy register.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BTIF1</name>
|
|
<description>Channel x block transfer complete
|
|
interrupt flag This bit is set by hardware. It is
|
|
cleared by software writing 1 to the corresponding
|
|
bit in the DMA_IFCRy register.</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCIF1</name>
|
|
<description>channel x buffer transfer
|
|
complete</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CRQA1</name>
|
|
<description>channel x request active
|
|
flag</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MDMA_C1IFCR</name>
|
|
<displayName>MDMA_C1IFCR</displayName>
|
|
<description>MDMA channel x interrupt flag clear
|
|
register</description>
|
|
<addressOffset>0x84</addressOffset>
|
|
<size>0x20</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CTEIF1</name>
|
|
<description>Channel x clear transfer error interrupt
|
|
flag Writing a 1 into this bit clears TEIFx in the
|
|
MDMA_ISRy register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CCTCIF1</name>
|
|
<description>Clear Channel transfer complete
|
|
interrupt flag for channel x Writing a 1 into this
|
|
bit clears CTCIFx in the MDMA_ISRy
|
|
register</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CBRTIF1</name>
|
|
<description>Channel x clear block repeat transfer
|
|
complete interrupt flag Writing a 1 into this bit
|
|
clears BRTIFx in the MDMA_ISRy register</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CBTIF1</name>
|
|
<description>Channel x Clear block transfer complete
|
|
interrupt flag Writing a 1 into this bit clears BTIFx
|
|
in the MDMA_ISRy register</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CLTCIF1</name>
|
|
<description>CLear buffer Transfer Complete Interrupt
|
|
Flag for channel x Writing a 1 into this bit clears
|
|
TCIFx in the MDMA_ISRy register</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MDMA_C1ESR</name>
|
|
<displayName>MDMA_C1ESR</displayName>
|
|
<description>MDMA Channel x error status
|
|
register</description>
|
|
<addressOffset>0x88</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TEA</name>
|
|
<description>Transfer Error Address These bits are
|
|
set and cleared by HW, in case of an MDMA data
|
|
transfer error. It is used in conjunction with TED.
|
|
This field indicates the 7 LSBits of the address
|
|
which generated a transfer/access error. It may be
|
|
used by SW to retrieve the failing address, by adding
|
|
this value (truncated to the buffer transfer length
|
|
size) to the current SAR/DAR value. Note: The SAR/DAR
|
|
current value doesnt reflect this last address due to
|
|
the FIFO management system. The SAR/DAR are only
|
|
updated at the end of a (buffer) transfer (of TLEN+1
|
|
bytes). Note: It is not set in case of a link data
|
|
error.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TED</name>
|
|
<description>Transfer Error Direction These bit is
|
|
set and cleared by HW, in case of an MDMA data
|
|
transfer error.</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TELD</name>
|
|
<description>Transfer Error Link Data These bit is
|
|
set by HW, in case of a transfer error while reading
|
|
the block link data structure. It is cleared by
|
|
software writing 1 to the CTEIFx bit in the DMA_IFCRy
|
|
register.</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TEMD</name>
|
|
<description>Transfer Error Mask Data These bit is
|
|
set by HW, in case of a transfer error while writing
|
|
the Mask Data. It is cleared by software writing 1 to
|
|
the CTEIFx bit in the DMA_IFCRy
|
|
register.</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ASE</name>
|
|
<description>Address/Size Error These bit is set by
|
|
HW, when the programmed address is not aligned with
|
|
the data size. TED will indicate whether the problem
|
|
is on the source or destination. It is cleared by
|
|
software writing 1 to the CTEIFx bit in the DMA_IFCRy
|
|
register.</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BSE</name>
|
|
<description>Block Size Error These bit is set by HW,
|
|
when the block size is not an integer multiple of the
|
|
data size either for source or destination. TED will
|
|
indicate whether the problem is on the source or
|
|
destination. It is cleared by software writing 1 to
|
|
the CTEIFx bit in the DMA_IFCRy
|
|
register.</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MDMA_C1CR</name>
|
|
<displayName>MDMA_C1CR</displayName>
|
|
<description>This register is used to control the
|
|
concerned channel.</description>
|
|
<addressOffset>0x8C</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EN</name>
|
|
<description>channel enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TEIE</name>
|
|
<description>Transfer error interrupt enable This bit
|
|
is set and cleared by software.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CTCIE</name>
|
|
<description>Channel Transfer Complete interrupt
|
|
enable This bit is set and cleared by
|
|
software.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BRTIE</name>
|
|
<description>Block Repeat transfer interrupt enable
|
|
This bit is set and cleared by
|
|
software.</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BTIE</name>
|
|
<description>Block Transfer interrupt enable This bit
|
|
is set and cleared by software.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TCIE</name>
|
|
<description>buffer Transfer Complete interrupt
|
|
enable This bit is set and cleared by
|
|
software.</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PL</name>
|
|
<description>Priority level These bits are set and
|
|
cleared by software. These bits are protected and can
|
|
be written only if EN is 0.</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BEX</name>
|
|
<description>byte Endianness exchange</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HEX</name>
|
|
<description>Half word Endianes
|
|
exchange</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WEX</name>
|
|
<description>Word Endianness exchange</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SWRQ</name>
|
|
<description>SW ReQuest Writing a 1 into this bit
|
|
sets the CRQAx in MDMA_ISRy register, activating the
|
|
request on Channel x Note: Either the whole CxCR
|
|
register or the 8-bit/16-bit register @ Address
|
|
offset: 0x4E + 0x40 chn may be used for SWRQ
|
|
activation. In case of a SW request, acknowledge is
|
|
not generated (neither HW signal, nor CxMAR write
|
|
access).</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MDMA_C1TCR</name>
|
|
<displayName>MDMA_C1TCR</displayName>
|
|
<description>This register is used to configure the
|
|
concerned channel.</description>
|
|
<addressOffset>0x90</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SINC</name>
|
|
<description>Source increment mode These bits are set
|
|
and cleared by software. These bits are protected and
|
|
can be written only if EN is 0 Note: When source is
|
|
AHB (SBUS=1), SINC = 00 is forbidden. In Linked List
|
|
Mode, at the end of a block (single or last block in
|
|
repeated block transfer mode), this register will be
|
|
loaded from memory (from address given by current
|
|
LAR[31:0] + 0x00).</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DINC</name>
|
|
<description>Destination increment mode These bits
|
|
are set and cleared by software. These bits are
|
|
protected and can be written only if EN is 0 Note:
|
|
When destination is AHB (DBUS=1), DINC = 00 is
|
|
forbidden.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SSIZE</name>
|
|
<description>Source data size These bits are set and
|
|
cleared by software. These bits are protected and can
|
|
be written only if EN is 0 Note: If a value of 11 is
|
|
programmed for the TCM access/AHB port, a transfer
|
|
error will occur (TEIF bit set) If SINCOS &lt;
|
|
SSIZE and SINC &#8800; 00, the result will be
|
|
unpredictable. Note: SSIZE = 11 (double-word) is
|
|
forbidden when source is TCM/AHB bus
|
|
(SBUS=1).</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DSIZE</name>
|
|
<description>Destination data size These bits are set
|
|
and cleared by software. These bits are protected and
|
|
can be written only if EN is 0. Note: If a value of
|
|
11 is programmed for the TCM access/AHB port, a
|
|
transfer error will occur (TEIF bit set) If DINCOS
|
|
&lt; DSIZE and DINC &#8800; 00, the result
|
|
will be unpredictable. Note: DSIZE = 11 (double-word)
|
|
is forbidden when destination is TCM/AHB bus
|
|
(DBUS=1).</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SINCOS</name>
|
|
<description>source increment offset
|
|
size</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DINCOS</name>
|
|
<description>Destination increment
|
|
offset</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SBURST</name>
|
|
<description>source burst transfer
|
|
configuration</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DBURST</name>
|
|
<description>Destination burst transfer
|
|
configuration</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TLEN</name>
|
|
<description>buffer transfer lengh</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PKE</name>
|
|
<description>PacK Enable These bit is set and cleared
|
|
by software. If the Source Size is smaller than the
|
|
destination, it will be padded according to the PAM
|
|
value. If the Source data size is larger than the
|
|
destination one, it will be truncated. The alignment
|
|
will be done according to the PAM[0] value. This bit
|
|
is protected and can be written only if EN is
|
|
0</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PAM</name>
|
|
<description>Padding/Alignement Mode These bits are
|
|
set and cleared by software. Case 1: Source data size
|
|
smaller than destination data size - 3 options are
|
|
valid. Case 2: Source data size larger than
|
|
destination data size. The remainder part is
|
|
discarded. When PKE = 1 or DSIZE=SSIZE, these bits
|
|
are ignored. These bits are protected and can be
|
|
written only if EN is 0</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TRGM</name>
|
|
<description>Trigger Mode These bits are set and
|
|
cleared by software. Note: If TRGM is 11 for the
|
|
current block, all the values loaded at the end of
|
|
the current block through the linked list mechanism
|
|
must keep the same value (TRGM=11) and the same SWRM
|
|
value, otherwise the result is undefined. These bits
|
|
are protected and can be written only if EN is
|
|
0.</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWRM</name>
|
|
<description>SW Request Mode This bit is set and
|
|
cleared by software. If a HW or SW request is
|
|
currently active, the bit change will be delayed
|
|
until the current transfer is completed. If the CxMAR
|
|
contains a valid address, the CxMDR value will also
|
|
be written @ CxMAR address. This bit is protected and
|
|
can be written only if EN is 0.</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BWM</name>
|
|
<description>Bufferable Write Mode This bit is set
|
|
and cleared by software. This bit is protected and
|
|
can be written only if EN is 0. Note: All MDMA
|
|
destination accesses are non-cacheable.</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MDMA_C1BNDTR</name>
|
|
<displayName>MDMA_C1BNDTR</displayName>
|
|
<description>MDMA Channel x block number of data
|
|
register</description>
|
|
<addressOffset>0x94</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BNDT</name>
|
|
<description>block number of data to
|
|
transfer</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>17</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BRSUM</name>
|
|
<description>Block Repeat Source address Update Mode
|
|
These bits are protected and can be written only if
|
|
EN is 0.</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BRDUM</name>
|
|
<description>Block Repeat Destination address Update
|
|
Mode These bits are protected and can be written only
|
|
if EN is 0.</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BRC</name>
|
|
<description>Block Repeat Count This field contains
|
|
the number of repetitions of the current block (0 to
|
|
4095). When the channel is enabled, this register is
|
|
read-only, indicating the remaining number of blocks,
|
|
excluding the current one. This register decrements
|
|
after each complete block transfer. Once the last
|
|
block transfer has completed, this register can
|
|
either stay at zero or be reloaded automatically from
|
|
memory (in Linked List mode - i.e. Link Address
|
|
valid). These bits are protected and can be written
|
|
only if EN is 0.</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MDMA_C1SAR</name>
|
|
<displayName>MDMA_C1SAR</displayName>
|
|
<description>MDMA channel x source address
|
|
register</description>
|
|
<addressOffset>0x98</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SAR</name>
|
|
<description>source adr base</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MDMA_C1DAR</name>
|
|
<displayName>MDMA_C1DAR</displayName>
|
|
<description>MDMA channel x destination address
|
|
register</description>
|
|
<addressOffset>0x9C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DAR</name>
|
|
<description>Destination adr base</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MDMA_C1BRUR</name>
|
|
<displayName>MDMA_C1BRUR</displayName>
|
|
<description>MDMA channel x Block Repeat address Update
|
|
register</description>
|
|
<addressOffset>0xA0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SUV</name>
|
|
<description>source adresse update
|
|
value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DUV</name>
|
|
<description>destination address update</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MDMA_C1LAR</name>
|
|
<displayName>MDMA_C1LAR</displayName>
|
|
<description>MDMA channel x Link Address
|
|
register</description>
|
|
<addressOffset>0xA4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LAR</name>
|
|
<description>Link address register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MDMA_C1TBR</name>
|
|
<displayName>MDMA_C1TBR</displayName>
|
|
<description>MDMA channel x Trigger and Bus selection
|
|
Register</description>
|
|
<addressOffset>0xA8</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TSEL</name>
|
|
<description>Trigger selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SBUS</name>
|
|
<description>Source BUS select This bit is protected
|
|
and can be written only if EN is 0.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DBUS</name>
|
|
<description>Destination BUS slect This bit is
|
|
protected and can be written only if EN is
|
|
0.</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MDMA_C1MAR</name>
|
|
<displayName>MDMA_C1MAR</displayName>
|
|
<description>MDMA channel x Mask address
|
|
register</description>
|
|
<addressOffset>0xB0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MAR</name>
|
|
<description>Mask address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MDMA_C1MDR</name>
|
|
<displayName>MDMA_C1MDR</displayName>
|
|
<description>MDMA channel x Mask Data
|
|
register</description>
|
|
<addressOffset>0xB4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MDR</name>
|
|
<description>Mask data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MDMA_C2ISR</name>
|
|
<displayName>MDMA_C2ISR</displayName>
|
|
<description>MDMA channel x interrupt/status
|
|
register</description>
|
|
<addressOffset>0xC0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TEIF2</name>
|
|
<description>Channel x transfer error interrupt flag
|
|
This bit is set by hardware. It is cleared by
|
|
software writing 1 to the corresponding bit in the
|
|
DMA_IFCRy register.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTCIF2</name>
|
|
<description>Channel x Channel Transfer Complete
|
|
interrupt flag This bit is set by hardware. It is
|
|
cleared by software writing 1 to the corresponding
|
|
bit in the DMA_IFCRy register. CTC is set when the
|
|
last block was transferred and the channel has been
|
|
automatically disabled. CTC is also set when the
|
|
channel is suspended, as a result of writing EN bit
|
|
to 0.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BRTIF2</name>
|
|
<description>Channel x block repeat transfer complete
|
|
interrupt flag This bit is set by hardware. It is
|
|
cleared by software writing 1 to the corresponding
|
|
bit in the DMA_IFCRy register.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BTIF2</name>
|
|
<description>Channel x block transfer complete
|
|
interrupt flag This bit is set by hardware. It is
|
|
cleared by software writing 1 to the corresponding
|
|
bit in the DMA_IFCRy register.</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCIF2</name>
|
|
<description>channel x buffer transfer
|
|
complete</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CRQA2</name>
|
|
<description>channel x request active
|
|
flag</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MDMA_C2IFCR</name>
|
|
<displayName>MDMA_C2IFCR</displayName>
|
|
<description>MDMA channel x interrupt flag clear
|
|
register</description>
|
|
<addressOffset>0xC4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CTEIF2</name>
|
|
<description>Channel x clear transfer error interrupt
|
|
flag Writing a 1 into this bit clears TEIFx in the
|
|
MDMA_ISRy register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CCTCIF2</name>
|
|
<description>Clear Channel transfer complete
|
|
interrupt flag for channel x Writing a 1 into this
|
|
bit clears CTCIFx in the MDMA_ISRy
|
|
register</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CBRTIF2</name>
|
|
<description>Channel x clear block repeat transfer
|
|
complete interrupt flag Writing a 1 into this bit
|
|
clears BRTIFx in the MDMA_ISRy register</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CBTIF2</name>
|
|
<description>Channel x Clear block transfer complete
|
|
interrupt flag Writing a 1 into this bit clears BTIFx
|
|
in the MDMA_ISRy register</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CLTCIF2</name>
|
|
<description>CLear buffer Transfer Complete Interrupt
|
|
Flag for channel x Writing a 1 into this bit clears
|
|
TCIFx in the MDMA_ISRy register</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MDMA_C2ESR</name>
|
|
<displayName>MDMA_C2ESR</displayName>
|
|
<description>MDMA Channel x error status
|
|
register</description>
|
|
<addressOffset>0xC8</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TEA</name>
|
|
<description>Transfer Error Address These bits are
|
|
set and cleared by HW, in case of an MDMA data
|
|
transfer error. It is used in conjunction with TED.
|
|
This field indicates the 7 LSBits of the address
|
|
which generated a transfer/access error. It may be
|
|
used by SW to retrieve the failing address, by adding
|
|
this value (truncated to the buffer transfer length
|
|
size) to the current SAR/DAR value. Note: The SAR/DAR
|
|
current value doesnt reflect this last address due to
|
|
the FIFO management system. The SAR/DAR are only
|
|
updated at the end of a (buffer) transfer (of TLEN+1
|
|
bytes). Note: It is not set in case of a link data
|
|
error.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TED</name>
|
|
<description>Transfer Error Direction These bit is
|
|
set and cleared by HW, in case of an MDMA data
|
|
transfer error.</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TELD</name>
|
|
<description>Transfer Error Link Data These bit is
|
|
set by HW, in case of a transfer error while reading
|
|
the block link data structure. It is cleared by
|
|
software writing 1 to the CTEIFx bit in the DMA_IFCRy
|
|
register.</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TEMD</name>
|
|
<description>Transfer Error Mask Data These bit is
|
|
set by HW, in case of a transfer error while writing
|
|
the Mask Data. It is cleared by software writing 1 to
|
|
the CTEIFx bit in the DMA_IFCRy
|
|
register.</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ASE</name>
|
|
<description>Address/Size Error These bit is set by
|
|
HW, when the programmed address is not aligned with
|
|
the data size. TED will indicate whether the problem
|
|
is on the source or destination. It is cleared by
|
|
software writing 1 to the CTEIFx bit in the DMA_IFCRy
|
|
register.</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BSE</name>
|
|
<description>Block Size Error These bit is set by HW,
|
|
when the block size is not an integer multiple of the
|
|
data size either for source or destination. TED will
|
|
indicate whether the problem is on the source or
|
|
destination. It is cleared by software writing 1 to
|
|
the CTEIFx bit in the DMA_IFCRy
|
|
register.</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MDMA_C2CR</name>
|
|
<displayName>MDMA_C2CR</displayName>
|
|
<description>This register is used to control the
|
|
concerned channel.</description>
|
|
<addressOffset>0xCC</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EN</name>
|
|
<description>channel enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TEIE</name>
|
|
<description>Transfer error interrupt enable This bit
|
|
is set and cleared by software.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CTCIE</name>
|
|
<description>Channel Transfer Complete interrupt
|
|
enable This bit is set and cleared by
|
|
software.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BRTIE</name>
|
|
<description>Block Repeat transfer interrupt enable
|
|
This bit is set and cleared by
|
|
software.</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BTIE</name>
|
|
<description>Block Transfer interrupt enable This bit
|
|
is set and cleared by software.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TCIE</name>
|
|
<description>buffer Transfer Complete interrupt
|
|
enable This bit is set and cleared by
|
|
software.</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PL</name>
|
|
<description>Priority level These bits are set and
|
|
cleared by software. These bits are protected and can
|
|
be written only if EN is 0.</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BEX</name>
|
|
<description>byte Endianness exchange</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HEX</name>
|
|
<description>Half word Endianes
|
|
exchange</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WEX</name>
|
|
<description>Word Endianness exchange</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SWRQ</name>
|
|
<description>SW ReQuest Writing a 1 into this bit
|
|
sets the CRQAx in MDMA_ISRy register, activating the
|
|
request on Channel x Note: Either the whole CxCR
|
|
register or the 8-bit/16-bit register @ Address
|
|
offset: 0x4E + 0x40 chn may be used for SWRQ
|
|
activation. In case of a SW request, acknowledge is
|
|
not generated (neither HW signal, nor CxMAR write
|
|
access).</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MDMA_C2TCR</name>
|
|
<displayName>MDMA_C2TCR</displayName>
|
|
<description>This register is used to configure the
|
|
concerned channel.</description>
|
|
<addressOffset>0xD0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SINC</name>
|
|
<description>Source increment mode These bits are set
|
|
and cleared by software. These bits are protected and
|
|
can be written only if EN is 0 Note: When source is
|
|
AHB (SBUS=1), SINC = 00 is forbidden. In Linked List
|
|
Mode, at the end of a block (single or last block in
|
|
repeated block transfer mode), this register will be
|
|
loaded from memory (from address given by current
|
|
LAR[31:0] + 0x00).</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DINC</name>
|
|
<description>Destination increment mode These bits
|
|
are set and cleared by software. These bits are
|
|
protected and can be written only if EN is 0 Note:
|
|
When destination is AHB (DBUS=1), DINC = 00 is
|
|
forbidden.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SSIZE</name>
|
|
<description>Source data size These bits are set and
|
|
cleared by software. These bits are protected and can
|
|
be written only if EN is 0 Note: If a value of 11 is
|
|
programmed for the TCM access/AHB port, a transfer
|
|
error will occur (TEIF bit set) If SINCOS &lt;
|
|
SSIZE and SINC &#8800; 00, the result will be
|
|
unpredictable. Note: SSIZE = 11 (double-word) is
|
|
forbidden when source is TCM/AHB bus
|
|
(SBUS=1).</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DSIZE</name>
|
|
<description>Destination data size These bits are set
|
|
and cleared by software. These bits are protected and
|
|
can be written only if EN is 0. Note: If a value of
|
|
11 is programmed for the TCM access/AHB port, a
|
|
transfer error will occur (TEIF bit set) If DINCOS
|
|
&lt; DSIZE and DINC &#8800; 00, the result
|
|
will be unpredictable. Note: DSIZE = 11 (double-word)
|
|
is forbidden when destination is TCM/AHB bus
|
|
(DBUS=1).</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SINCOS</name>
|
|
<description>source increment offset
|
|
size</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DINCOS</name>
|
|
<description>Destination increment
|
|
offset</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SBURST</name>
|
|
<description>source burst transfer
|
|
configuration</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DBURST</name>
|
|
<description>Destination burst transfer
|
|
configuration</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TLEN</name>
|
|
<description>buffer transfer lengh</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PKE</name>
|
|
<description>PacK Enable These bit is set and cleared
|
|
by software. If the Source Size is smaller than the
|
|
destination, it will be padded according to the PAM
|
|
value. If the Source data size is larger than the
|
|
destination one, it will be truncated. The alignment
|
|
will be done according to the PAM[0] value. This bit
|
|
is protected and can be written only if EN is
|
|
0</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PAM</name>
|
|
<description>Padding/Alignement Mode These bits are
|
|
set and cleared by software. Case 1: Source data size
|
|
smaller than destination data size - 3 options are
|
|
valid. Case 2: Source data size larger than
|
|
destination data size. The remainder part is
|
|
discarded. When PKE = 1 or DSIZE=SSIZE, these bits
|
|
are ignored. These bits are protected and can be
|
|
written only if EN is 0</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TRGM</name>
|
|
<description>Trigger Mode These bits are set and
|
|
cleared by software. Note: If TRGM is 11 for the
|
|
current block, all the values loaded at the end of
|
|
the current block through the linked list mechanism
|
|
must keep the same value (TRGM=11) and the same SWRM
|
|
value, otherwise the result is undefined. These bits
|
|
are protected and can be written only if EN is
|
|
0.</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWRM</name>
|
|
<description>SW Request Mode This bit is set and
|
|
cleared by software. If a HW or SW request is
|
|
currently active, the bit change will be delayed
|
|
until the current transfer is completed. If the CxMAR
|
|
contains a valid address, the CxMDR value will also
|
|
be written @ CxMAR address. This bit is protected and
|
|
can be written only if EN is 0.</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BWM</name>
|
|
<description>Bufferable Write Mode This bit is set
|
|
and cleared by software. This bit is protected and
|
|
can be written only if EN is 0. Note: All MDMA
|
|
destination accesses are non-cacheable.</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MDMA_C2BNDTR</name>
|
|
<displayName>MDMA_C2BNDTR</displayName>
|
|
<description>MDMA Channel x block number of data
|
|
register</description>
|
|
<addressOffset>0xD4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BNDT</name>
|
|
<description>block number of data to
|
|
transfer</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>17</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BRSUM</name>
|
|
<description>Block Repeat Source address Update Mode
|
|
These bits are protected and can be written only if
|
|
EN is 0.</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BRDUM</name>
|
|
<description>Block Repeat Destination address Update
|
|
Mode These bits are protected and can be written only
|
|
if EN is 0.</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BRC</name>
|
|
<description>Block Repeat Count This field contains
|
|
the number of repetitions of the current block (0 to
|
|
4095). When the channel is enabled, this register is
|
|
read-only, indicating the remaining number of blocks,
|
|
excluding the current one. This register decrements
|
|
after each complete block transfer. Once the last
|
|
block transfer has completed, this register can
|
|
either stay at zero or be reloaded automatically from
|
|
memory (in Linked List mode - i.e. Link Address
|
|
valid). These bits are protected and can be written
|
|
only if EN is 0.</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MDMA_C2SAR</name>
|
|
<displayName>MDMA_C2SAR</displayName>
|
|
<description>MDMA channel x source address
|
|
register</description>
|
|
<addressOffset>0xD8</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SAR</name>
|
|
<description>source adr base</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MDMA_C2DAR</name>
|
|
<displayName>MDMA_C2DAR</displayName>
|
|
<description>MDMA channel x destination address
|
|
register</description>
|
|
<addressOffset>0xDC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DAR</name>
|
|
<description>Destination adr base</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MDMA_C2BRUR</name>
|
|
<displayName>MDMA_C2BRUR</displayName>
|
|
<description>MDMA channel x Block Repeat address Update
|
|
register</description>
|
|
<addressOffset>0xE0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SUV</name>
|
|
<description>source adresse update
|
|
value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DUV</name>
|
|
<description>destination address update</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MDMA_C2LAR</name>
|
|
<displayName>MDMA_C2LAR</displayName>
|
|
<description>MDMA channel x Link Address
|
|
register</description>
|
|
<addressOffset>0xE4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LAR</name>
|
|
<description>Link address register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MDMA_C2TBR</name>
|
|
<displayName>MDMA_C2TBR</displayName>
|
|
<description>MDMA channel x Trigger and Bus selection
|
|
Register</description>
|
|
<addressOffset>0xE8</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TSEL</name>
|
|
<description>Trigger selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SBUS</name>
|
|
<description>Source BUS select This bit is protected
|
|
and can be written only if EN is 0.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DBUS</name>
|
|
<description>Destination BUS slect This bit is
|
|
protected and can be written only if EN is
|
|
0.</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MDMA_C2MAR</name>
|
|
<displayName>MDMA_C2MAR</displayName>
|
|
<description>MDMA channel x Mask address
|
|
register</description>
|
|
<addressOffset>0xF0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MAR</name>
|
|
<description>Mask address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MDMA_C2MDR</name>
|
|
<displayName>MDMA_C2MDR</displayName>
|
|
<description>MDMA channel x Mask Data
|
|
register</description>
|
|
<addressOffset>0xF4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MDR</name>
|
|
<description>Mask data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MDMA_C3ISR</name>
|
|
<displayName>MDMA_C3ISR</displayName>
|
|
<description>MDMA channel x interrupt/status
|
|
register</description>
|
|
<addressOffset>0x100</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TEIF3</name>
|
|
<description>Channel x transfer error interrupt flag
|
|
This bit is set by hardware. It is cleared by
|
|
software writing 1 to the corresponding bit in the
|
|
DMA_IFCRy register.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTCIF3</name>
|
|
<description>Channel x Channel Transfer Complete
|
|
interrupt flag This bit is set by hardware. It is
|
|
cleared by software writing 1 to the corresponding
|
|
bit in the DMA_IFCRy register. CTC is set when the
|
|
last block was transferred and the channel has been
|
|
automatically disabled. CTC is also set when the
|
|
channel is suspended, as a result of writing EN bit
|
|
to 0.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BRTIF3</name>
|
|
<description>Channel x block repeat transfer complete
|
|
interrupt flag This bit is set by hardware. It is
|
|
cleared by software writing 1 to the corresponding
|
|
bit in the DMA_IFCRy register.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BTIF3</name>
|
|
<description>Channel x block transfer complete
|
|
interrupt flag This bit is set by hardware. It is
|
|
cleared by software writing 1 to the corresponding
|
|
bit in the DMA_IFCRy register.</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCIF3</name>
|
|
<description>channel x buffer transfer
|
|
complete</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CRQA3</name>
|
|
<description>channel x request active
|
|
flag</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MDMA_C3IFCR</name>
|
|
<displayName>MDMA_C3IFCR</displayName>
|
|
<description>MDMA channel x interrupt flag clear
|
|
register</description>
|
|
<addressOffset>0x104</addressOffset>
|
|
<size>0x20</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CTEIF3</name>
|
|
<description>Channel x clear transfer error interrupt
|
|
flag Writing a 1 into this bit clears TEIFx in the
|
|
MDMA_ISRy register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CCTCIF3</name>
|
|
<description>Clear Channel transfer complete
|
|
interrupt flag for channel x Writing a 1 into this
|
|
bit clears CTCIFx in the MDMA_ISRy
|
|
register</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CBRTIF3</name>
|
|
<description>Channel x clear block repeat transfer
|
|
complete interrupt flag Writing a 1 into this bit
|
|
clears BRTIFx in the MDMA_ISRy register</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CBTIF3</name>
|
|
<description>Channel x Clear block transfer complete
|
|
interrupt flag Writing a 1 into this bit clears BTIFx
|
|
in the MDMA_ISRy register</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CLTCIF3</name>
|
|
<description>CLear buffer Transfer Complete Interrupt
|
|
Flag for channel x Writing a 1 into this bit clears
|
|
TCIFx in the MDMA_ISRy register</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MDMA_C3ESR</name>
|
|
<displayName>MDMA_C3ESR</displayName>
|
|
<description>MDMA Channel x error status
|
|
register</description>
|
|
<addressOffset>0x108</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TEA</name>
|
|
<description>Transfer Error Address These bits are
|
|
set and cleared by HW, in case of an MDMA data
|
|
transfer error. It is used in conjunction with TED.
|
|
This field indicates the 7 LSBits of the address
|
|
which generated a transfer/access error. It may be
|
|
used by SW to retrieve the failing address, by adding
|
|
this value (truncated to the buffer transfer length
|
|
size) to the current SAR/DAR value. Note: The SAR/DAR
|
|
current value doesnt reflect this last address due to
|
|
the FIFO management system. The SAR/DAR are only
|
|
updated at the end of a (buffer) transfer (of TLEN+1
|
|
bytes). Note: It is not set in case of a link data
|
|
error.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TED</name>
|
|
<description>Transfer Error Direction These bit is
|
|
set and cleared by HW, in case of an MDMA data
|
|
transfer error.</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TELD</name>
|
|
<description>Transfer Error Link Data These bit is
|
|
set by HW, in case of a transfer error while reading
|
|
the block link data structure. It is cleared by
|
|
software writing 1 to the CTEIFx bit in the DMA_IFCRy
|
|
register.</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TEMD</name>
|
|
<description>Transfer Error Mask Data These bit is
|
|
set by HW, in case of a transfer error while writing
|
|
the Mask Data. It is cleared by software writing 1 to
|
|
the CTEIFx bit in the DMA_IFCRy
|
|
register.</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ASE</name>
|
|
<description>Address/Size Error These bit is set by
|
|
HW, when the programmed address is not aligned with
|
|
the data size. TED will indicate whether the problem
|
|
is on the source or destination. It is cleared by
|
|
software writing 1 to the CTEIFx bit in the DMA_IFCRy
|
|
register.</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BSE</name>
|
|
<description>Block Size Error These bit is set by HW,
|
|
when the block size is not an integer multiple of the
|
|
data size either for source or destination. TED will
|
|
indicate whether the problem is on the source or
|
|
destination. It is cleared by software writing 1 to
|
|
the CTEIFx bit in the DMA_IFCRy
|
|
register.</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MDMA_C3CR</name>
|
|
<displayName>MDMA_C3CR</displayName>
|
|
<description>This register is used to control the
|
|
concerned channel.</description>
|
|
<addressOffset>0x10C</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EN</name>
|
|
<description>channel enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TEIE</name>
|
|
<description>Transfer error interrupt enable This bit
|
|
is set and cleared by software.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CTCIE</name>
|
|
<description>Channel Transfer Complete interrupt
|
|
enable This bit is set and cleared by
|
|
software.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BRTIE</name>
|
|
<description>Block Repeat transfer interrupt enable
|
|
This bit is set and cleared by
|
|
software.</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BTIE</name>
|
|
<description>Block Transfer interrupt enable This bit
|
|
is set and cleared by software.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TCIE</name>
|
|
<description>buffer Transfer Complete interrupt
|
|
enable This bit is set and cleared by
|
|
software.</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PL</name>
|
|
<description>Priority level These bits are set and
|
|
cleared by software. These bits are protected and can
|
|
be written only if EN is 0.</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BEX</name>
|
|
<description>byte Endianness exchange</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HEX</name>
|
|
<description>Half word Endianes
|
|
exchange</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WEX</name>
|
|
<description>Word Endianness exchange</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SWRQ</name>
|
|
<description>SW ReQuest Writing a 1 into this bit
|
|
sets the CRQAx in MDMA_ISRy register, activating the
|
|
request on Channel x Note: Either the whole CxCR
|
|
register or the 8-bit/16-bit register @ Address
|
|
offset: 0x4E + 0x40 chn may be used for SWRQ
|
|
activation. In case of a SW request, acknowledge is
|
|
not generated (neither HW signal, nor CxMAR write
|
|
access).</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MDMA_C3TCR</name>
|
|
<displayName>MDMA_C3TCR</displayName>
|
|
<description>This register is used to configure the
|
|
concerned channel.</description>
|
|
<addressOffset>0x110</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SINC</name>
|
|
<description>Source increment mode These bits are set
|
|
and cleared by software. These bits are protected and
|
|
can be written only if EN is 0 Note: When source is
|
|
AHB (SBUS=1), SINC = 00 is forbidden. In Linked List
|
|
Mode, at the end of a block (single or last block in
|
|
repeated block transfer mode), this register will be
|
|
loaded from memory (from address given by current
|
|
LAR[31:0] + 0x00).</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DINC</name>
|
|
<description>Destination increment mode These bits
|
|
are set and cleared by software. These bits are
|
|
protected and can be written only if EN is 0 Note:
|
|
When destination is AHB (DBUS=1), DINC = 00 is
|
|
forbidden.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SSIZE</name>
|
|
<description>Source data size These bits are set and
|
|
cleared by software. These bits are protected and can
|
|
be written only if EN is 0 Note: If a value of 11 is
|
|
programmed for the TCM access/AHB port, a transfer
|
|
error will occur (TEIF bit set) If SINCOS &lt;
|
|
SSIZE and SINC &#8800; 00, the result will be
|
|
unpredictable. Note: SSIZE = 11 (double-word) is
|
|
forbidden when source is TCM/AHB bus
|
|
(SBUS=1).</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DSIZE</name>
|
|
<description>Destination data size These bits are set
|
|
and cleared by software. These bits are protected and
|
|
can be written only if EN is 0. Note: If a value of
|
|
11 is programmed for the TCM access/AHB port, a
|
|
transfer error will occur (TEIF bit set) If DINCOS
|
|
&lt; DSIZE and DINC &#8800; 00, the result
|
|
will be unpredictable. Note: DSIZE = 11 (double-word)
|
|
is forbidden when destination is TCM/AHB bus
|
|
(DBUS=1).</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SINCOS</name>
|
|
<description>source increment offset
|
|
size</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DINCOS</name>
|
|
<description>Destination increment
|
|
offset</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SBURST</name>
|
|
<description>source burst transfer
|
|
configuration</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DBURST</name>
|
|
<description>Destination burst transfer
|
|
configuration</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TLEN</name>
|
|
<description>buffer transfer lengh</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PKE</name>
|
|
<description>PacK Enable These bit is set and cleared
|
|
by software. If the Source Size is smaller than the
|
|
destination, it will be padded according to the PAM
|
|
value. If the Source data size is larger than the
|
|
destination one, it will be truncated. The alignment
|
|
will be done according to the PAM[0] value. This bit
|
|
is protected and can be written only if EN is
|
|
0</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PAM</name>
|
|
<description>Padding/Alignement Mode These bits are
|
|
set and cleared by software. Case 1: Source data size
|
|
smaller than destination data size - 3 options are
|
|
valid. Case 2: Source data size larger than
|
|
destination data size. The remainder part is
|
|
discarded. When PKE = 1 or DSIZE=SSIZE, these bits
|
|
are ignored. These bits are protected and can be
|
|
written only if EN is 0</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TRGM</name>
|
|
<description>Trigger Mode These bits are set and
|
|
cleared by software. Note: If TRGM is 11 for the
|
|
current block, all the values loaded at the end of
|
|
the current block through the linked list mechanism
|
|
must keep the same value (TRGM=11) and the same SWRM
|
|
value, otherwise the result is undefined. These bits
|
|
are protected and can be written only if EN is
|
|
0.</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWRM</name>
|
|
<description>SW Request Mode This bit is set and
|
|
cleared by software. If a HW or SW request is
|
|
currently active, the bit change will be delayed
|
|
until the current transfer is completed. If the CxMAR
|
|
contains a valid address, the CxMDR value will also
|
|
be written @ CxMAR address. This bit is protected and
|
|
can be written only if EN is 0.</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BWM</name>
|
|
<description>Bufferable Write Mode This bit is set
|
|
and cleared by software. This bit is protected and
|
|
can be written only if EN is 0. Note: All MDMA
|
|
destination accesses are non-cacheable.</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MDMA_C3BNDTR</name>
|
|
<displayName>MDMA_C3BNDTR</displayName>
|
|
<description>MDMA Channel x block number of data
|
|
register</description>
|
|
<addressOffset>0x114</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BNDT</name>
|
|
<description>block number of data to
|
|
transfer</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>17</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BRSUM</name>
|
|
<description>Block Repeat Source address Update Mode
|
|
These bits are protected and can be written only if
|
|
EN is 0.</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BRDUM</name>
|
|
<description>Block Repeat Destination address Update
|
|
Mode These bits are protected and can be written only
|
|
if EN is 0.</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BRC</name>
|
|
<description>Block Repeat Count This field contains
|
|
the number of repetitions of the current block (0 to
|
|
4095). When the channel is enabled, this register is
|
|
read-only, indicating the remaining number of blocks,
|
|
excluding the current one. This register decrements
|
|
after each complete block transfer. Once the last
|
|
block transfer has completed, this register can
|
|
either stay at zero or be reloaded automatically from
|
|
memory (in Linked List mode - i.e. Link Address
|
|
valid). These bits are protected and can be written
|
|
only if EN is 0.</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MDMA_C3SAR</name>
|
|
<displayName>MDMA_C3SAR</displayName>
|
|
<description>MDMA channel x source address
|
|
register</description>
|
|
<addressOffset>0x118</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SAR</name>
|
|
<description>source adr base</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MDMA_C3DAR</name>
|
|
<displayName>MDMA_C3DAR</displayName>
|
|
<description>MDMA channel x destination address
|
|
register</description>
|
|
<addressOffset>0x11C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DAR</name>
|
|
<description>Destination adr base</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MDMA_C3BRUR</name>
|
|
<displayName>MDMA_C3BRUR</displayName>
|
|
<description>MDMA channel x Block Repeat address Update
|
|
register</description>
|
|
<addressOffset>0x120</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SUV</name>
|
|
<description>source adresse update
|
|
value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DUV</name>
|
|
<description>destination address update</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MDMA_C3LAR</name>
|
|
<displayName>MDMA_C3LAR</displayName>
|
|
<description>MDMA channel x Link Address
|
|
register</description>
|
|
<addressOffset>0x124</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LAR</name>
|
|
<description>Link address register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MDMA_C3TBR</name>
|
|
<displayName>MDMA_C3TBR</displayName>
|
|
<description>MDMA channel x Trigger and Bus selection
|
|
Register</description>
|
|
<addressOffset>0x128</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TSEL</name>
|
|
<description>Trigger selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SBUS</name>
|
|
<description>Source BUS select This bit is protected
|
|
and can be written only if EN is 0.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DBUS</name>
|
|
<description>Destination BUS slect This bit is
|
|
protected and can be written only if EN is
|
|
0.</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MDMA_C3MAR</name>
|
|
<displayName>MDMA_C3MAR</displayName>
|
|
<description>MDMA channel x Mask address
|
|
register</description>
|
|
<addressOffset>0x130</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MAR</name>
|
|
<description>Mask address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MDMA_C3MDR</name>
|
|
<displayName>MDMA_C3MDR</displayName>
|
|
<description>MDMA channel x Mask Data
|
|
register</description>
|
|
<addressOffset>0x134</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MDR</name>
|
|
<description>Mask data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MDMA_C4ISR</name>
|
|
<displayName>MDMA_C4ISR</displayName>
|
|
<description>MDMA channel x interrupt/status
|
|
register</description>
|
|
<addressOffset>0x140</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TEIF4</name>
|
|
<description>Channel x transfer error interrupt flag
|
|
This bit is set by hardware. It is cleared by
|
|
software writing 1 to the corresponding bit in the
|
|
DMA_IFCRy register.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTCIF4</name>
|
|
<description>Channel x Channel Transfer Complete
|
|
interrupt flag This bit is set by hardware. It is
|
|
cleared by software writing 1 to the corresponding
|
|
bit in the DMA_IFCRy register. CTC is set when the
|
|
last block was transferred and the channel has been
|
|
automatically disabled. CTC is also set when the
|
|
channel is suspended, as a result of writing EN bit
|
|
to 0.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BRTIF4</name>
|
|
<description>Channel x block repeat transfer complete
|
|
interrupt flag This bit is set by hardware. It is
|
|
cleared by software writing 1 to the corresponding
|
|
bit in the DMA_IFCRy register.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BTIF4</name>
|
|
<description>Channel x block transfer complete
|
|
interrupt flag This bit is set by hardware. It is
|
|
cleared by software writing 1 to the corresponding
|
|
bit in the DMA_IFCRy register.</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCIF4</name>
|
|
<description>channel x buffer transfer
|
|
complete</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CRQA4</name>
|
|
<description>channel x request active
|
|
flag</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MDMA_C4IFCR</name>
|
|
<displayName>MDMA_C4IFCR</displayName>
|
|
<description>MDMA channel x interrupt flag clear
|
|
register</description>
|
|
<addressOffset>0x144</addressOffset>
|
|
<size>0x20</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CTEIF4</name>
|
|
<description>Channel x clear transfer error interrupt
|
|
flag Writing a 1 into this bit clears TEIFx in the
|
|
MDMA_ISRy register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CCTCIF4</name>
|
|
<description>Clear Channel transfer complete
|
|
interrupt flag for channel x Writing a 1 into this
|
|
bit clears CTCIFx in the MDMA_ISRy
|
|
register</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CBRTIF4</name>
|
|
<description>Channel x clear block repeat transfer
|
|
complete interrupt flag Writing a 1 into this bit
|
|
clears BRTIFx in the MDMA_ISRy register</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CBTIF4</name>
|
|
<description>Channel x Clear block transfer complete
|
|
interrupt flag Writing a 1 into this bit clears BTIFx
|
|
in the MDMA_ISRy register</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CLTCIF4</name>
|
|
<description>CLear buffer Transfer Complete Interrupt
|
|
Flag for channel x Writing a 1 into this bit clears
|
|
TCIFx in the MDMA_ISRy register</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MDMA_C4ESR</name>
|
|
<displayName>MDMA_C4ESR</displayName>
|
|
<description>MDMA Channel x error status
|
|
register</description>
|
|
<addressOffset>0x148</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TEA</name>
|
|
<description>Transfer Error Address These bits are
|
|
set and cleared by HW, in case of an MDMA data
|
|
transfer error. It is used in conjunction with TED.
|
|
This field indicates the 7 LSBits of the address
|
|
which generated a transfer/access error. It may be
|
|
used by SW to retrieve the failing address, by adding
|
|
this value (truncated to the buffer transfer length
|
|
size) to the current SAR/DAR value. Note: The SAR/DAR
|
|
current value doesnt reflect this last address due to
|
|
the FIFO management system. The SAR/DAR are only
|
|
updated at the end of a (buffer) transfer (of TLEN+1
|
|
bytes). Note: It is not set in case of a link data
|
|
error.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TED</name>
|
|
<description>Transfer Error Direction These bit is
|
|
set and cleared by HW, in case of an MDMA data
|
|
transfer error.</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TELD</name>
|
|
<description>Transfer Error Link Data These bit is
|
|
set by HW, in case of a transfer error while reading
|
|
the block link data structure. It is cleared by
|
|
software writing 1 to the CTEIFx bit in the DMA_IFCRy
|
|
register.</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TEMD</name>
|
|
<description>Transfer Error Mask Data These bit is
|
|
set by HW, in case of a transfer error while writing
|
|
the Mask Data. It is cleared by software writing 1 to
|
|
the CTEIFx bit in the DMA_IFCRy
|
|
register.</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ASE</name>
|
|
<description>Address/Size Error These bit is set by
|
|
HW, when the programmed address is not aligned with
|
|
the data size. TED will indicate whether the problem
|
|
is on the source or destination. It is cleared by
|
|
software writing 1 to the CTEIFx bit in the DMA_IFCRy
|
|
register.</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BSE</name>
|
|
<description>Block Size Error These bit is set by HW,
|
|
when the block size is not an integer multiple of the
|
|
data size either for source or destination. TED will
|
|
indicate whether the problem is on the source or
|
|
destination. It is cleared by software writing 1 to
|
|
the CTEIFx bit in the DMA_IFCRy
|
|
register.</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MDMA_C4CR</name>
|
|
<displayName>MDMA_C4CR</displayName>
|
|
<description>This register is used to control the
|
|
concerned channel.</description>
|
|
<addressOffset>0x14C</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EN</name>
|
|
<description>channel enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TEIE</name>
|
|
<description>Transfer error interrupt enable This bit
|
|
is set and cleared by software.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CTCIE</name>
|
|
<description>Channel Transfer Complete interrupt
|
|
enable This bit is set and cleared by
|
|
software.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BRTIE</name>
|
|
<description>Block Repeat transfer interrupt enable
|
|
This bit is set and cleared by
|
|
software.</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BTIE</name>
|
|
<description>Block Transfer interrupt enable This bit
|
|
is set and cleared by software.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TCIE</name>
|
|
<description>buffer Transfer Complete interrupt
|
|
enable This bit is set and cleared by
|
|
software.</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PL</name>
|
|
<description>Priority level These bits are set and
|
|
cleared by software. These bits are protected and can
|
|
be written only if EN is 0.</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BEX</name>
|
|
<description>byte Endianness exchange</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HEX</name>
|
|
<description>Half word Endianes
|
|
exchange</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WEX</name>
|
|
<description>Word Endianness exchange</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SWRQ</name>
|
|
<description>SW ReQuest Writing a 1 into this bit
|
|
sets the CRQAx in MDMA_ISRy register, activating the
|
|
request on Channel x Note: Either the whole CxCR
|
|
register or the 8-bit/16-bit register @ Address
|
|
offset: 0x4E + 0x40 chn may be used for SWRQ
|
|
activation. In case of a SW request, acknowledge is
|
|
not generated (neither HW signal, nor CxMAR write
|
|
access).</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MDMA_C4TCR</name>
|
|
<displayName>MDMA_C4TCR</displayName>
|
|
<description>This register is used to configure the
|
|
concerned channel.</description>
|
|
<addressOffset>0x150</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SINC</name>
|
|
<description>Source increment mode These bits are set
|
|
and cleared by software. These bits are protected and
|
|
can be written only if EN is 0 Note: When source is
|
|
AHB (SBUS=1), SINC = 00 is forbidden. In Linked List
|
|
Mode, at the end of a block (single or last block in
|
|
repeated block transfer mode), this register will be
|
|
loaded from memory (from address given by current
|
|
LAR[31:0] + 0x00).</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DINC</name>
|
|
<description>Destination increment mode These bits
|
|
are set and cleared by software. These bits are
|
|
protected and can be written only if EN is 0 Note:
|
|
When destination is AHB (DBUS=1), DINC = 00 is
|
|
forbidden.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SSIZE</name>
|
|
<description>Source data size These bits are set and
|
|
cleared by software. These bits are protected and can
|
|
be written only if EN is 0 Note: If a value of 11 is
|
|
programmed for the TCM access/AHB port, a transfer
|
|
error will occur (TEIF bit set) If SINCOS &lt;
|
|
SSIZE and SINC &#8800; 00, the result will be
|
|
unpredictable. Note: SSIZE = 11 (double-word) is
|
|
forbidden when source is TCM/AHB bus
|
|
(SBUS=1).</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DSIZE</name>
|
|
<description>Destination data size These bits are set
|
|
and cleared by software. These bits are protected and
|
|
can be written only if EN is 0. Note: If a value of
|
|
11 is programmed for the TCM access/AHB port, a
|
|
transfer error will occur (TEIF bit set) If DINCOS
|
|
&lt; DSIZE and DINC &#8800; 00, the result
|
|
will be unpredictable. Note: DSIZE = 11 (double-word)
|
|
is forbidden when destination is TCM/AHB bus
|
|
(DBUS=1).</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SINCOS</name>
|
|
<description>source increment offset
|
|
size</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DINCOS</name>
|
|
<description>Destination increment
|
|
offset</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SBURST</name>
|
|
<description>source burst transfer
|
|
configuration</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DBURST</name>
|
|
<description>Destination burst transfer
|
|
configuration</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TLEN</name>
|
|
<description>buffer transfer lengh</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PKE</name>
|
|
<description>PacK Enable These bit is set and cleared
|
|
by software. If the Source Size is smaller than the
|
|
destination, it will be padded according to the PAM
|
|
value. If the Source data size is larger than the
|
|
destination one, it will be truncated. The alignment
|
|
will be done according to the PAM[0] value. This bit
|
|
is protected and can be written only if EN is
|
|
0</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PAM</name>
|
|
<description>Padding/Alignement Mode These bits are
|
|
set and cleared by software. Case 1: Source data size
|
|
smaller than destination data size - 3 options are
|
|
valid. Case 2: Source data size larger than
|
|
destination data size. The remainder part is
|
|
discarded. When PKE = 1 or DSIZE=SSIZE, these bits
|
|
are ignored. These bits are protected and can be
|
|
written only if EN is 0</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TRGM</name>
|
|
<description>Trigger Mode These bits are set and
|
|
cleared by software. Note: If TRGM is 11 for the
|
|
current block, all the values loaded at the end of
|
|
the current block through the linked list mechanism
|
|
must keep the same value (TRGM=11) and the same SWRM
|
|
value, otherwise the result is undefined. These bits
|
|
are protected and can be written only if EN is
|
|
0.</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWRM</name>
|
|
<description>SW Request Mode This bit is set and
|
|
cleared by software. If a HW or SW request is
|
|
currently active, the bit change will be delayed
|
|
until the current transfer is completed. If the CxMAR
|
|
contains a valid address, the CxMDR value will also
|
|
be written @ CxMAR address. This bit is protected and
|
|
can be written only if EN is 0.</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BWM</name>
|
|
<description>Bufferable Write Mode This bit is set
|
|
and cleared by software. This bit is protected and
|
|
can be written only if EN is 0. Note: All MDMA
|
|
destination accesses are non-cacheable.</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MDMA_C4BNDTR</name>
|
|
<displayName>MDMA_C4BNDTR</displayName>
|
|
<description>MDMA Channel x block number of data
|
|
register</description>
|
|
<addressOffset>0x154</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BNDT</name>
|
|
<description>block number of data to
|
|
transfer</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>17</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BRSUM</name>
|
|
<description>Block Repeat Source address Update Mode
|
|
These bits are protected and can be written only if
|
|
EN is 0.</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BRDUM</name>
|
|
<description>Block Repeat Destination address Update
|
|
Mode These bits are protected and can be written only
|
|
if EN is 0.</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BRC</name>
|
|
<description>Block Repeat Count This field contains
|
|
the number of repetitions of the current block (0 to
|
|
4095). When the channel is enabled, this register is
|
|
read-only, indicating the remaining number of blocks,
|
|
excluding the current one. This register decrements
|
|
after each complete block transfer. Once the last
|
|
block transfer has completed, this register can
|
|
either stay at zero or be reloaded automatically from
|
|
memory (in Linked List mode - i.e. Link Address
|
|
valid). These bits are protected and can be written
|
|
only if EN is 0.</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MDMA_C4SAR</name>
|
|
<displayName>MDMA_C4SAR</displayName>
|
|
<description>MDMA channel x source address
|
|
register</description>
|
|
<addressOffset>0x158</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SAR</name>
|
|
<description>source adr base</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MDMA_C4DAR</name>
|
|
<displayName>MDMA_C4DAR</displayName>
|
|
<description>MDMA channel x destination address
|
|
register</description>
|
|
<addressOffset>0x15C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DAR</name>
|
|
<description>Destination adr base</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MDMA_C4BRUR</name>
|
|
<displayName>MDMA_C4BRUR</displayName>
|
|
<description>MDMA channel x Block Repeat address Update
|
|
register</description>
|
|
<addressOffset>0x160</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SUV</name>
|
|
<description>source adresse update
|
|
value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DUV</name>
|
|
<description>destination address update</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MDMA_C4LAR</name>
|
|
<displayName>MDMA_C4LAR</displayName>
|
|
<description>MDMA channel x Link Address
|
|
register</description>
|
|
<addressOffset>0x164</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LAR</name>
|
|
<description>Link address register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MDMA_C4TBR</name>
|
|
<displayName>MDMA_C4TBR</displayName>
|
|
<description>MDMA channel x Trigger and Bus selection
|
|
Register</description>
|
|
<addressOffset>0x168</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TSEL</name>
|
|
<description>Trigger selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SBUS</name>
|
|
<description>Source BUS select This bit is protected
|
|
and can be written only if EN is 0.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DBUS</name>
|
|
<description>Destination BUS slect This bit is
|
|
protected and can be written only if EN is
|
|
0.</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MDMA_C4MAR</name>
|
|
<displayName>MDMA_C4MAR</displayName>
|
|
<description>MDMA channel x Mask address
|
|
register</description>
|
|
<addressOffset>0x170</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MAR</name>
|
|
<description>Mask address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MDMA_C4MDR</name>
|
|
<displayName>MDMA_C4MDR</displayName>
|
|
<description>MDMA channel x Mask Data
|
|
register</description>
|
|
<addressOffset>0x174</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MDR</name>
|
|
<description>Mask data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MDMA_C5ISR</name>
|
|
<displayName>MDMA_C5ISR</displayName>
|
|
<description>MDMA channel x interrupt/status
|
|
register</description>
|
|
<addressOffset>0x180</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TEIF5</name>
|
|
<description>Channel x transfer error interrupt flag
|
|
This bit is set by hardware. It is cleared by
|
|
software writing 1 to the corresponding bit in the
|
|
DMA_IFCRy register.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTCIF5</name>
|
|
<description>Channel x Channel Transfer Complete
|
|
interrupt flag This bit is set by hardware. It is
|
|
cleared by software writing 1 to the corresponding
|
|
bit in the DMA_IFCRy register. CTC is set when the
|
|
last block was transferred and the channel has been
|
|
automatically disabled. CTC is also set when the
|
|
channel is suspended, as a result of writing EN bit
|
|
to 0.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BRTIF5</name>
|
|
<description>Channel x block repeat transfer complete
|
|
interrupt flag This bit is set by hardware. It is
|
|
cleared by software writing 1 to the corresponding
|
|
bit in the DMA_IFCRy register.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BTIF5</name>
|
|
<description>Channel x block transfer complete
|
|
interrupt flag This bit is set by hardware. It is
|
|
cleared by software writing 1 to the corresponding
|
|
bit in the DMA_IFCRy register.</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCIF5</name>
|
|
<description>channel x buffer transfer
|
|
complete</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CRQA5</name>
|
|
<description>channel x request active
|
|
flag</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MDMA_C5IFCR</name>
|
|
<displayName>MDMA_C5IFCR</displayName>
|
|
<description>MDMA channel x interrupt flag clear
|
|
register</description>
|
|
<addressOffset>0x184</addressOffset>
|
|
<size>0x20</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CTEIF5</name>
|
|
<description>Channel x clear transfer error interrupt
|
|
flag Writing a 1 into this bit clears TEIFx in the
|
|
MDMA_ISRy register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CCTCIF5</name>
|
|
<description>Clear Channel transfer complete
|
|
interrupt flag for channel x Writing a 1 into this
|
|
bit clears CTCIFx in the MDMA_ISRy
|
|
register</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CBRTIF5</name>
|
|
<description>Channel x clear block repeat transfer
|
|
complete interrupt flag Writing a 1 into this bit
|
|
clears BRTIFx in the MDMA_ISRy register</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CBTIF5</name>
|
|
<description>Channel x Clear block transfer complete
|
|
interrupt flag Writing a 1 into this bit clears BTIFx
|
|
in the MDMA_ISRy register</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CLTCIF5</name>
|
|
<description>CLear buffer Transfer Complete Interrupt
|
|
Flag for channel x Writing a 1 into this bit clears
|
|
TCIFx in the MDMA_ISRy register</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MDMA_C5ESR</name>
|
|
<displayName>MDMA_C5ESR</displayName>
|
|
<description>MDMA Channel x error status
|
|
register</description>
|
|
<addressOffset>0x188</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TEA</name>
|
|
<description>Transfer Error Address These bits are
|
|
set and cleared by HW, in case of an MDMA data
|
|
transfer error. It is used in conjunction with TED.
|
|
This field indicates the 7 LSBits of the address
|
|
which generated a transfer/access error. It may be
|
|
used by SW to retrieve the failing address, by adding
|
|
this value (truncated to the buffer transfer length
|
|
size) to the current SAR/DAR value. Note: The SAR/DAR
|
|
current value doesnt reflect this last address due to
|
|
the FIFO management system. The SAR/DAR are only
|
|
updated at the end of a (buffer) transfer (of TLEN+1
|
|
bytes). Note: It is not set in case of a link data
|
|
error.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TED</name>
|
|
<description>Transfer Error Direction These bit is
|
|
set and cleared by HW, in case of an MDMA data
|
|
transfer error.</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TELD</name>
|
|
<description>Transfer Error Link Data These bit is
|
|
set by HW, in case of a transfer error while reading
|
|
the block link data structure. It is cleared by
|
|
software writing 1 to the CTEIFx bit in the DMA_IFCRy
|
|
register.</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TEMD</name>
|
|
<description>Transfer Error Mask Data These bit is
|
|
set by HW, in case of a transfer error while writing
|
|
the Mask Data. It is cleared by software writing 1 to
|
|
the CTEIFx bit in the DMA_IFCRy
|
|
register.</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ASE</name>
|
|
<description>Address/Size Error These bit is set by
|
|
HW, when the programmed address is not aligned with
|
|
the data size. TED will indicate whether the problem
|
|
is on the source or destination. It is cleared by
|
|
software writing 1 to the CTEIFx bit in the DMA_IFCRy
|
|
register.</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BSE</name>
|
|
<description>Block Size Error These bit is set by HW,
|
|
when the block size is not an integer multiple of the
|
|
data size either for source or destination. TED will
|
|
indicate whether the problem is on the source or
|
|
destination. It is cleared by software writing 1 to
|
|
the CTEIFx bit in the DMA_IFCRy
|
|
register.</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MDMA_C5CR</name>
|
|
<displayName>MDMA_C5CR</displayName>
|
|
<description>This register is used to control the
|
|
concerned channel.</description>
|
|
<addressOffset>0x18C</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EN</name>
|
|
<description>channel enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TEIE</name>
|
|
<description>Transfer error interrupt enable This bit
|
|
is set and cleared by software.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CTCIE</name>
|
|
<description>Channel Transfer Complete interrupt
|
|
enable This bit is set and cleared by
|
|
software.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BRTIE</name>
|
|
<description>Block Repeat transfer interrupt enable
|
|
This bit is set and cleared by
|
|
software.</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BTIE</name>
|
|
<description>Block Transfer interrupt enable This bit
|
|
is set and cleared by software.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TCIE</name>
|
|
<description>buffer Transfer Complete interrupt
|
|
enable This bit is set and cleared by
|
|
software.</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PL</name>
|
|
<description>Priority level These bits are set and
|
|
cleared by software. These bits are protected and can
|
|
be written only if EN is 0.</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BEX</name>
|
|
<description>byte Endianness exchange</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HEX</name>
|
|
<description>Half word Endianes
|
|
exchange</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WEX</name>
|
|
<description>Word Endianness exchange</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SWRQ</name>
|
|
<description>SW ReQuest Writing a 1 into this bit
|
|
sets the CRQAx in MDMA_ISRy register, activating the
|
|
request on Channel x Note: Either the whole CxCR
|
|
register or the 8-bit/16-bit register @ Address
|
|
offset: 0x4E + 0x40 chn may be used for SWRQ
|
|
activation. In case of a SW request, acknowledge is
|
|
not generated (neither HW signal, nor CxMAR write
|
|
access).</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MDMA_C5TCR</name>
|
|
<displayName>MDMA_C5TCR</displayName>
|
|
<description>This register is used to configure the
|
|
concerned channel.</description>
|
|
<addressOffset>0x190</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SINC</name>
|
|
<description>Source increment mode These bits are set
|
|
and cleared by software. These bits are protected and
|
|
can be written only if EN is 0 Note: When source is
|
|
AHB (SBUS=1), SINC = 00 is forbidden. In Linked List
|
|
Mode, at the end of a block (single or last block in
|
|
repeated block transfer mode), this register will be
|
|
loaded from memory (from address given by current
|
|
LAR[31:0] + 0x00).</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DINC</name>
|
|
<description>Destination increment mode These bits
|
|
are set and cleared by software. These bits are
|
|
protected and can be written only if EN is 0 Note:
|
|
When destination is AHB (DBUS=1), DINC = 00 is
|
|
forbidden.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SSIZE</name>
|
|
<description>Source data size These bits are set and
|
|
cleared by software. These bits are protected and can
|
|
be written only if EN is 0 Note: If a value of 11 is
|
|
programmed for the TCM access/AHB port, a transfer
|
|
error will occur (TEIF bit set) If SINCOS &lt;
|
|
SSIZE and SINC &#8800; 00, the result will be
|
|
unpredictable. Note: SSIZE = 11 (double-word) is
|
|
forbidden when source is TCM/AHB bus
|
|
(SBUS=1).</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DSIZE</name>
|
|
<description>Destination data size These bits are set
|
|
and cleared by software. These bits are protected and
|
|
can be written only if EN is 0. Note: If a value of
|
|
11 is programmed for the TCM access/AHB port, a
|
|
transfer error will occur (TEIF bit set) If DINCOS
|
|
&lt; DSIZE and DINC &#8800; 00, the result
|
|
will be unpredictable. Note: DSIZE = 11 (double-word)
|
|
is forbidden when destination is TCM/AHB bus
|
|
(DBUS=1).</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SINCOS</name>
|
|
<description>source increment offset
|
|
size</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DINCOS</name>
|
|
<description>Destination increment
|
|
offset</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SBURST</name>
|
|
<description>source burst transfer
|
|
configuration</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DBURST</name>
|
|
<description>Destination burst transfer
|
|
configuration</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TLEN</name>
|
|
<description>buffer transfer lengh</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PKE</name>
|
|
<description>PacK Enable These bit is set and cleared
|
|
by software. If the Source Size is smaller than the
|
|
destination, it will be padded according to the PAM
|
|
value. If the Source data size is larger than the
|
|
destination one, it will be truncated. The alignment
|
|
will be done according to the PAM[0] value. This bit
|
|
is protected and can be written only if EN is
|
|
0</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PAM</name>
|
|
<description>Padding/Alignement Mode These bits are
|
|
set and cleared by software. Case 1: Source data size
|
|
smaller than destination data size - 3 options are
|
|
valid. Case 2: Source data size larger than
|
|
destination data size. The remainder part is
|
|
discarded. When PKE = 1 or DSIZE=SSIZE, these bits
|
|
are ignored. These bits are protected and can be
|
|
written only if EN is 0</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TRGM</name>
|
|
<description>Trigger Mode These bits are set and
|
|
cleared by software. Note: If TRGM is 11 for the
|
|
current block, all the values loaded at the end of
|
|
the current block through the linked list mechanism
|
|
must keep the same value (TRGM=11) and the same SWRM
|
|
value, otherwise the result is undefined. These bits
|
|
are protected and can be written only if EN is
|
|
0.</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWRM</name>
|
|
<description>SW Request Mode This bit is set and
|
|
cleared by software. If a HW or SW request is
|
|
currently active, the bit change will be delayed
|
|
until the current transfer is completed. If the CxMAR
|
|
contains a valid address, the CxMDR value will also
|
|
be written @ CxMAR address. This bit is protected and
|
|
can be written only if EN is 0.</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BWM</name>
|
|
<description>Bufferable Write Mode This bit is set
|
|
and cleared by software. This bit is protected and
|
|
can be written only if EN is 0. Note: All MDMA
|
|
destination accesses are non-cacheable.</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MDMA_C5BNDTR</name>
|
|
<displayName>MDMA_C5BNDTR</displayName>
|
|
<description>MDMA Channel x block number of data
|
|
register</description>
|
|
<addressOffset>0x194</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BNDT</name>
|
|
<description>block number of data to
|
|
transfer</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>17</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BRSUM</name>
|
|
<description>Block Repeat Source address Update Mode
|
|
These bits are protected and can be written only if
|
|
EN is 0.</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BRDUM</name>
|
|
<description>Block Repeat Destination address Update
|
|
Mode These bits are protected and can be written only
|
|
if EN is 0.</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BRC</name>
|
|
<description>Block Repeat Count This field contains
|
|
the number of repetitions of the current block (0 to
|
|
4095). When the channel is enabled, this register is
|
|
read-only, indicating the remaining number of blocks,
|
|
excluding the current one. This register decrements
|
|
after each complete block transfer. Once the last
|
|
block transfer has completed, this register can
|
|
either stay at zero or be reloaded automatically from
|
|
memory (in Linked List mode - i.e. Link Address
|
|
valid). These bits are protected and can be written
|
|
only if EN is 0.</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MDMA_C5SAR</name>
|
|
<displayName>MDMA_C5SAR</displayName>
|
|
<description>MDMA channel x source address
|
|
register</description>
|
|
<addressOffset>0x198</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SAR</name>
|
|
<description>source adr base</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MDMA_C5DAR</name>
|
|
<displayName>MDMA_C5DAR</displayName>
|
|
<description>MDMA channel x destination address
|
|
register</description>
|
|
<addressOffset>0x19C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DAR</name>
|
|
<description>Destination adr base</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MDMA_C5BRUR</name>
|
|
<displayName>MDMA_C5BRUR</displayName>
|
|
<description>MDMA channel x Block Repeat address Update
|
|
register</description>
|
|
<addressOffset>0x1A0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SUV</name>
|
|
<description>source adresse update
|
|
value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DUV</name>
|
|
<description>destination address update</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MDMA_C5LAR</name>
|
|
<displayName>MDMA_C5LAR</displayName>
|
|
<description>MDMA channel x Link Address
|
|
register</description>
|
|
<addressOffset>0x1A4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LAR</name>
|
|
<description>Link address register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MDMA_C5TBR</name>
|
|
<displayName>MDMA_C5TBR</displayName>
|
|
<description>MDMA channel x Trigger and Bus selection
|
|
Register</description>
|
|
<addressOffset>0x1A8</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TSEL</name>
|
|
<description>Trigger selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SBUS</name>
|
|
<description>Source BUS select This bit is protected
|
|
and can be written only if EN is 0.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DBUS</name>
|
|
<description>Destination BUS slect This bit is
|
|
protected and can be written only if EN is
|
|
0.</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MDMA_C5MAR</name>
|
|
<displayName>MDMA_C5MAR</displayName>
|
|
<description>MDMA channel x Mask address
|
|
register</description>
|
|
<addressOffset>0x1B0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MAR</name>
|
|
<description>Mask address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MDMA_C5MDR</name>
|
|
<displayName>MDMA_C5MDR</displayName>
|
|
<description>MDMA channel x Mask Data
|
|
register</description>
|
|
<addressOffset>0x1B4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MDR</name>
|
|
<description>Mask data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MDMA_C6ISR</name>
|
|
<displayName>MDMA_C6ISR</displayName>
|
|
<description>MDMA channel x interrupt/status
|
|
register</description>
|
|
<addressOffset>0x1C0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TEIF6</name>
|
|
<description>Channel x transfer error interrupt flag
|
|
This bit is set by hardware. It is cleared by
|
|
software writing 1 to the corresponding bit in the
|
|
DMA_IFCRy register.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTCIF6</name>
|
|
<description>Channel x Channel Transfer Complete
|
|
interrupt flag This bit is set by hardware. It is
|
|
cleared by software writing 1 to the corresponding
|
|
bit in the DMA_IFCRy register. CTC is set when the
|
|
last block was transferred and the channel has been
|
|
automatically disabled. CTC is also set when the
|
|
channel is suspended, as a result of writing EN bit
|
|
to 0.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BRTIF6</name>
|
|
<description>Channel x block repeat transfer complete
|
|
interrupt flag This bit is set by hardware. It is
|
|
cleared by software writing 1 to the corresponding
|
|
bit in the DMA_IFCRy register.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BTIF6</name>
|
|
<description>Channel x block transfer complete
|
|
interrupt flag This bit is set by hardware. It is
|
|
cleared by software writing 1 to the corresponding
|
|
bit in the DMA_IFCRy register.</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCIF6</name>
|
|
<description>channel x buffer transfer
|
|
complete</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CRQA6</name>
|
|
<description>channel x request active
|
|
flag</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MDMA_C6IFCR</name>
|
|
<displayName>MDMA_C6IFCR</displayName>
|
|
<description>MDMA channel x interrupt flag clear
|
|
register</description>
|
|
<addressOffset>0x1C4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CTEIF6</name>
|
|
<description>Channel x clear transfer error interrupt
|
|
flag Writing a 1 into this bit clears TEIFx in the
|
|
MDMA_ISRy register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CCTCIF6</name>
|
|
<description>Clear Channel transfer complete
|
|
interrupt flag for channel x Writing a 1 into this
|
|
bit clears CTCIFx in the MDMA_ISRy
|
|
register</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CBRTIF6</name>
|
|
<description>Channel x clear block repeat transfer
|
|
complete interrupt flag Writing a 1 into this bit
|
|
clears BRTIFx in the MDMA_ISRy register</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CBTIF6</name>
|
|
<description>Channel x Clear block transfer complete
|
|
interrupt flag Writing a 1 into this bit clears BTIFx
|
|
in the MDMA_ISRy register</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CLTCIF6</name>
|
|
<description>CLear buffer Transfer Complete Interrupt
|
|
Flag for channel x Writing a 1 into this bit clears
|
|
TCIFx in the MDMA_ISRy register</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MDMA_C6ESR</name>
|
|
<displayName>MDMA_C6ESR</displayName>
|
|
<description>MDMA Channel x error status
|
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register</description>
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<addressOffset>0x1C8</addressOffset>
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<size>0x20</size>
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<access>read-only</access>
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<resetValue>0x00000000</resetValue>
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<fields>
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<field>
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<name>TEA</name>
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<description>Transfer Error Address These bits are
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set and cleared by HW, in case of an MDMA data
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transfer error. It is used in conjunction with TED.
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This field indicates the 7 LSBits of the address
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which generated a transfer/access error. It may be
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used by SW to retrieve the failing address, by adding
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this value (truncated to the buffer transfer length
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size) to the current SAR/DAR value. Note: The SAR/DAR
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current value doesnt reflect this last address due to
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the FIFO management system. The SAR/DAR are only
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updated at the end of a (buffer) transfer (of TLEN+1
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bytes). Note: It is not set in case of a link data
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error.</description>
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<bitOffset>0</bitOffset>
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<bitWidth>7</bitWidth>
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</field>
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<field>
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<name>TED</name>
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<description>Transfer Error Direction These bit is
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set and cleared by HW, in case of an MDMA data
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transfer error.</description>
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<bitOffset>7</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>TELD</name>
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<description>Transfer Error Link Data These bit is
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set by HW, in case of a transfer error while reading
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the block link data structure. It is cleared by
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software writing 1 to the CTEIFx bit in the DMA_IFCRy
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register.</description>
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<bitOffset>8</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>TEMD</name>
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<description>Transfer Error Mask Data These bit is
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set by HW, in case of a transfer error while writing
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the Mask Data. It is cleared by software writing 1 to
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the CTEIFx bit in the DMA_IFCRy
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register.</description>
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<bitOffset>9</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>ASE</name>
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<description>Address/Size Error These bit is set by
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HW, when the programmed address is not aligned with
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the data size. TED will indicate whether the problem
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is on the source or destination. It is cleared by
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software writing 1 to the CTEIFx bit in the DMA_IFCRy
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register.</description>
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<bitOffset>10</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>BSE</name>
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<description>Block Size Error These bit is set by HW,
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when the block size is not an integer multiple of the
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data size either for source or destination. TED will
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indicate whether the problem is on the source or
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destination. It is cleared by software writing 1 to
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the CTEIFx bit in the DMA_IFCRy
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register.</description>
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<bitOffset>11</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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</fields>
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</register>
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<register>
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<name>MDMA_C6CR</name>
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<displayName>MDMA_C6CR</displayName>
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<description>This register is used to control the
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concerned channel.</description>
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<addressOffset>0x1CC</addressOffset>
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<size>0x20</size>
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<resetValue>0x00000000</resetValue>
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<fields>
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<field>
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<name>EN</name>
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<description>channel enable</description>
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<bitOffset>0</bitOffset>
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<bitWidth>1</bitWidth>
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<access>read-write</access>
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</field>
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<field>
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<name>TEIE</name>
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<description>Transfer error interrupt enable This bit
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is set and cleared by software.</description>
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<bitOffset>1</bitOffset>
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<bitWidth>1</bitWidth>
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<access>read-write</access>
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</field>
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<field>
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<name>CTCIE</name>
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<description>Channel Transfer Complete interrupt
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enable This bit is set and cleared by
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software.</description>
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<bitOffset>2</bitOffset>
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<bitWidth>1</bitWidth>
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<access>read-write</access>
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</field>
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<field>
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