fsfw-example-stm32h7-freertos/misc/STM32H743.svd

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3.7 MiB

<?xml version="1.0" encoding="utf-8" standalone="no"?>
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Copyright (c) 2021 STMicroelectronics.
SPDX-License-Identifier: Apache-2.0
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
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Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
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<device schemaVersion="1.1"
xmlns:xs="http://www.w3.org/2001/XMLSchema-instance"
xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
<name>STM32H743</name>
<version>1.4</version>
<description>STM32H743</description>
<cpu>
<name>CM7</name>
<revision>r0p1</revision>
<endian>little</endian>
<mpuPresent>true</mpuPresent>
<fpuPresent>true</fpuPresent>
<nvicPrioBits>4</nvicPrioBits>
<vendorSystickConfig>false</vendorSystickConfig>
</cpu>
<!--Bus Interface Properties-->
<!--Cortex-M3 is byte addressable-->
<addressUnitBits>8</addressUnitBits>
<!--the maximum data bit width accessible within a single transfer-->
<width>32</width>
<!--Register Default Properties-->
<size>0x20</size>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<peripherals>
<peripheral>
<name>COMP1</name>
<description>COMP1</description>
<groupName>COMP1</groupName>
<baseAddress>0x58003800</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>COMP</name>
<description>COMP1 and COMP2</description>
<value>137</value>
</interrupt>
<registers>
<register>
<name>SR</name>
<displayName>SR</displayName>
<description>Comparator status register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>C1VAL</name>
<description>COMP channel 1 output status
bit</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C2VAL</name>
<description>COMP channel 2 output status
bit</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C1IF</name>
<description>COMP channel 1 Interrupt
Flag</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C2IF</name>
<description>COMP channel 2 Interrupt
Flag</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ICFR</name>
<displayName>ICFR</displayName>
<description>Comparator interrupt clear flag
register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CC1IF</name>
<description>Clear COMP channel 1 Interrupt
Flag</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC2IF</name>
<description>Clear COMP channel 2 Interrupt
Flag</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OR</name>
<displayName>OR</displayName>
<description>Comparator option register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AFOP</name>
<description>Selection of source for alternate
function of output ports</description>
<bitOffset>0</bitOffset>
<bitWidth>11</bitWidth>
</field>
<field>
<name>OR</name>
<description>Option Register</description>
<bitOffset>11</bitOffset>
<bitWidth>21</bitWidth>
</field>
</fields>
</register>
<register>
<name>CFGR1</name>
<displayName>CFGR1</displayName>
<description>Comparator configuration register
1</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EN</name>
<description>COMP channel 1 enable bit</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BRGEN</name>
<description>Scaler bridge enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SCALEN</name>
<description>Voltage scaler enable bit</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>POLARITY</name>
<description>COMP channel 1 polarity selection
bit</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ITEN</name>
<description>COMP channel 1 interrupt
enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HYST</name>
<description>COMP channel 1 hysteresis selection
bits</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PWRMODE</name>
<description>Power Mode of the COMP channel
1</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>INMSEL</name>
<description>COMP channel 1 inverting input selection
field</description>
<bitOffset>16</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>INPSEL</name>
<description>COMP channel 1 non-inverting input
selection bit</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BLANKING</name>
<description>COMP channel 1 blanking source selection
bits</description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>LOCK</name>
<description>Lock bit</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CFGR2</name>
<displayName>CFGR2</displayName>
<description>Comparator configuration register
2</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EN</name>
<description>COMP channel 1 enable bit</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BRGEN</name>
<description>Scaler bridge enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SCALEN</name>
<description>Voltage scaler enable bit</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>POLARITY</name>
<description>COMP channel 1 polarity selection
bit</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WINMODE</name>
<description>Window comparator mode selection
bit</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ITEN</name>
<description>COMP channel 1 interrupt
enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HYST</name>
<description>COMP channel 1 hysteresis selection
bits</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PWRMODE</name>
<description>Power Mode of the COMP channel
1</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>INMSEL</name>
<description>COMP channel 1 inverting input selection
field</description>
<bitOffset>16</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>INPSEL</name>
<description>COMP channel 1 non-inverting input
selection bit</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BLANKING</name>
<description>COMP channel 1 blanking source selection
bits</description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>LOCK</name>
<description>Lock bit</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>CRS</name>
<description>CRS</description>
<groupName>CRS</groupName>
<baseAddress>0x40008400</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>CRS</name>
<description>Clock Recovery System globa</description>
<value>144</value>
</interrupt>
<registers>
<register>
<name>CR</name>
<displayName>CR</displayName>
<description>CRS control register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<resetValue>0x00002000</resetValue>
<fields>
<field>
<name>SYNCOKIE</name>
<description>SYNC event OK interrupt
enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SYNCWARNIE</name>
<description>SYNC warning interrupt
enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ERRIE</name>
<description>Synchronization or trimming error
interrupt enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ESYNCIE</name>
<description>Expected SYNC interrupt
enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CEN</name>
<description>Frequency error counter enable This bit
enables the oscillator clock for the frequency error
counter. When this bit is set, the CRS_CFGR register
is write-protected and cannot be
modified.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>AUTOTRIMEN</name>
<description>Automatic trimming enable This bit
enables the automatic hardware adjustment of TRIM
bits according to the measured frequency error
between two SYNC events. If this bit is set, the TRIM
bits are read-only. The TRIM value can be adjusted by
hardware by one or two steps at a time, depending on
the measured frequency error value. Refer to
Section7.3.4: Frequency error evaluation and
automatic trimming for more details.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SWSYNC</name>
<description>Generate software SYNC event This bit is
set by software in order to generate a software SYNC
event. It is automatically cleared by
hardware.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>TRIM</name>
<description>HSI48 oscillator smooth trimming These
bits provide a user-programmable trimming value to
the HSI48 oscillator. They can be programmed to
adjust to variations in voltage and temperature that
influence the frequency of the HSI48. The default
value is 32, which corresponds to the middle of the
trimming interval. The trimming step is around 67 kHz
between two consecutive TRIM steps. A higher TRIM
value corresponds to a higher output frequency. When
the AUTOTRIMEN bit is set, this field is controlled
by hardware and is read-only.</description>
<bitOffset>8</bitOffset>
<bitWidth>6</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CFGR</name>
<displayName>CFGR</displayName>
<description>This register can be written only when the
frequency error counter is disabled (CEN bit is cleared
in CRS_CR). When the counter is enabled, this register is
write-protected.</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x2022BB7F</resetValue>
<fields>
<field>
<name>RELOAD</name>
<description>Counter reload value RELOAD is the value
to be loaded in the frequency error counter with each
SYNC event. Refer to Section7.3.3: Frequency error
measurement for more details about counter
behavior.</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>FELIM</name>
<description>Frequency error limit FELIM contains the
value to be used to evaluate the captured frequency
error value latched in the FECAP[15:0] bits of the
CRS_ISR register. Refer to Section7.3.4: Frequency
error evaluation and automatic trimming for more
details about FECAP evaluation.</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>SYNCDIV</name>
<description>SYNC divider These bits are set and
cleared by software to control the division factor of
the SYNC signal.</description>
<bitOffset>24</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>SYNCSRC</name>
<description>SYNC signal source selection These bits
are set and cleared by software to select the SYNC
signal source. Note: When using USB LPM (Link Power
Management) and the device is in Sleep mode, the
periodic USB SOF will not be generated by the host.
No SYNC signal will therefore be provided to the CRS
to calibrate the HSI48 on the run. To guarantee the
required clock precision after waking up from Sleep
mode, the LSE or reference clock on the GPIOs should
be used as SYNC signal.</description>
<bitOffset>28</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SYNCPOL</name>
<description>SYNC polarity selection This bit is set
and cleared by software to select the input polarity
for the SYNC signal source.</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ISR</name>
<displayName>ISR</displayName>
<description>CRS interrupt and status
register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SYNCOKF</name>
<description>SYNC event OK flag This flag is set by
hardware when the measured frequency error is smaller
than FELIM * 3. This means that either no adjustment
of the TRIM value is needed or that an adjustment by
one trimming step is enough to compensate the
frequency error. An interrupt is generated if the
SYNCOKIE bit is set in the CRS_CR register. It is
cleared by software by setting the SYNCOKC bit in the
CRS_ICR register.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SYNCWARNF</name>
<description>SYNC warning flag This flag is set by
hardware when the measured frequency error is greater
than or equal to FELIM * 3, but smaller than FELIM *
128. This means that to compensate the frequency
error, the TRIM value must be adjusted by two steps
or more. An interrupt is generated if the SYNCWARNIE
bit is set in the CRS_CR register. It is cleared by
software by setting the SYNCWARNC bit in the CRS_ICR
register.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ERRF</name>
<description>Error flag This flag is set by hardware
in case of any synchronization or trimming error. It
is the logical OR of the TRIMOVF, SYNCMISS and
SYNCERR bits. An interrupt is generated if the ERRIE
bit is set in the CRS_CR register. It is cleared by
software in reaction to setting the ERRC bit in the
CRS_ICR register, which clears the TRIMOVF, SYNCMISS
and SYNCERR bits.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ESYNCF</name>
<description>Expected SYNC flag This flag is set by
hardware when the frequency error counter reached a
zero value. An interrupt is generated if the ESYNCIE
bit is set in the CRS_CR register. It is cleared by
software by setting the ESYNCC bit in the CRS_ICR
register.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SYNCERR</name>
<description>SYNC error This flag is set by hardware
when the SYNC pulse arrives before the ESYNC event
and the measured frequency error is greater than or
equal to FELIM * 128. This means that the frequency
error is too big (internal frequency too low) to be
compensated by adjusting the TRIM value, and that
some other action should be taken. An interrupt is
generated if the ERRIE bit is set in the CRS_CR
register. It is cleared by software by setting the
ERRC bit in the CRS_ICR register.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SYNCMISS</name>
<description>SYNC missed This flag is set by hardware
when the frequency error counter reached value FELIM
* 128 and no SYNC was detected, meaning either that a
SYNC pulse was missed or that the frequency error is
too big (internal frequency too high) to be
compensated by adjusting the TRIM value, and that
some other action should be taken. At this point, the
frequency error counter is stopped (waiting for a
next SYNC) and an interrupt is generated if the ERRIE
bit is set in the CRS_CR register. It is cleared by
software by setting the ERRC bit in the CRS_ICR
register.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TRIMOVF</name>
<description>Trimming overflow or underflow This flag
is set by hardware when the automatic trimming tries
to over- or under-flow the TRIM value. An interrupt
is generated if the ERRIE bit is set in the CRS_CR
register. It is cleared by software by setting the
ERRC bit in the CRS_ICR register.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FEDIR</name>
<description>Frequency error direction FEDIR is the
counting direction of the frequency error counter
latched in the time of the last SYNC event. It shows
whether the actual frequency is below or above the
target.</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FECAP</name>
<description>Frequency error capture FECAP is the
frequency error counter value latched in the time of
the last SYNC event. Refer to Section7.3.4: Frequency
error evaluation and automatic trimming for more
details about FECAP usage.</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>ICR</name>
<displayName>ICR</displayName>
<description>CRS interrupt flag clear
register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SYNCOKC</name>
<description>SYNC event OK clear flag Writing 1 to
this bit clears the SYNCOKF flag in the CRS_ISR
register.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SYNCWARNC</name>
<description>SYNC warning clear flag Writing 1 to
this bit clears the SYNCWARNF flag in the CRS_ISR
register.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ERRC</name>
<description>Error clear flag Writing 1 to this bit
clears TRIMOVF, SYNCMISS and SYNCERR bits and
consequently also the ERRF flag in the CRS_ISR
register.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ESYNCC</name>
<description>Expected SYNC clear flag Writing 1 to
this bit clears the ESYNCF flag in the CRS_ISR
register.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>DAC</name>
<description>DAC</description>
<groupName>DAC</groupName>
<baseAddress>0x40007400</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>CR</name>
<displayName>CR</displayName>
<description>DAC control register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EN1</name>
<description>DAC channel1 enable This bit is set and
cleared by software to enable/disable DAC
channel1.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEN1</name>
<description>DAC channel1 trigger
enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TSEL1</name>
<description>DAC channel1 trigger selection These
bits select the external event used to trigger DAC
channel1. Note: Only used if bit TEN1 = 1 (DAC
channel1 trigger enabled).</description>
<bitOffset>2</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>WAVE1</name>
<description>DAC channel1 noise/triangle wave
generation enable These bits are set and cleared by
software. Note: Only used if bit TEN1 = 1 (DAC
channel1 trigger enabled).</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MAMP1</name>
<description>DAC channel1 mask/amplitude selector
These bits are written by software to select mask in
wave generation mode or amplitude in triangle
generation mode. = 1011: Unmask bits[11:0] of LFSR/
triangle amplitude equal to 4095</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>DMAEN1</name>
<description>DAC channel1 DMA enable This bit is set
and cleared by software.</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMAUDRIE1</name>
<description>DAC channel1 DMA Underrun Interrupt
enable This bit is set and cleared by
software.</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CEN1</name>
<description>DAC Channel 1 calibration enable This
bit is set and cleared by software to enable/disable
DAC channel 1 calibration, it can be written only if
bit EN1=0 into DAC_CR (the calibration mode can be
entered/exit only when the DAC channel is disabled)
Otherwise, the write operation is
ignored.</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EN2</name>
<description>DAC channel2 enable This bit is set and
cleared by software to enable/disable DAC
channel2.</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEN2</name>
<description>DAC channel2 trigger
enable</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TSEL2</name>
<description>DAC channel2 trigger selection These
bits select the external event used to trigger DAC
channel2 Note: Only used if bit TEN2 = 1 (DAC
channel2 trigger enabled).</description>
<bitOffset>18</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>WAVE2</name>
<description>DAC channel2 noise/triangle wave
generation enable These bits are set/reset by
software. 1x: Triangle wave generation enabled Note:
Only used if bit TEN2 = 1 (DAC channel2 trigger
enabled)</description>
<bitOffset>22</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MAMP2</name>
<description>DAC channel2 mask/amplitude selector
These bits are written by software to select mask in
wave generation mode or amplitude in triangle
generation mode. = 1011: Unmask bits[11:0] of LFSR/
triangle amplitude equal to 4095</description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>DMAEN2</name>
<description>DAC channel2 DMA enable This bit is set
and cleared by software.</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMAUDRIE2</name>
<description>DAC channel2 DMA underrun interrupt
enable This bit is set and cleared by
software.</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CEN2</name>
<description>DAC Channel 2 calibration enable This
bit is set and cleared by software to enable/disable
DAC channel 2 calibration, it can be written only if
bit EN2=0 into DAC_CR (the calibration mode can be
entered/exit only when the DAC channel is disabled)
Otherwise, the write operation is
ignored.</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SWTRGR</name>
<displayName>SWTRGR</displayName>
<description>DAC software trigger register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SWTRIG1</name>
<description>DAC channel1 software trigger This bit
is set by software to trigger the DAC in software
trigger mode. Note: This bit is cleared by hardware
(one APB1 clock cycle later) once the DAC_DHR1
register value has been loaded into the DAC_DOR1
register.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWTRIG2</name>
<description>DAC channel2 software trigger This bit
is set by software to trigger the DAC in software
trigger mode. Note: This bit is cleared by hardware
(one APB1 clock cycle later) once the DAC_DHR2
register value has been loaded into the DAC_DOR2
register.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>DHR12R1</name>
<displayName>DHR12R1</displayName>
<description>DAC channel1 12-bit right-aligned data
holding register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DACC1DHR</name>
<description>DAC channel1 12-bit right-aligned data
These bits are written by software which specifies
12-bit data for DAC channel1.</description>
<bitOffset>0</bitOffset>
<bitWidth>12</bitWidth>
</field>
</fields>
</register>
<register>
<name>DHR12L1</name>
<displayName>DHR12L1</displayName>
<description>DAC channel1 12-bit left aligned data
holding register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DACC1DHR</name>
<description>DAC channel1 12-bit left-aligned data
These bits are written by software which specifies
12-bit data for DAC channel1.</description>
<bitOffset>4</bitOffset>
<bitWidth>12</bitWidth>
</field>
</fields>
</register>
<register>
<name>DHR8R1</name>
<displayName>DHR8R1</displayName>
<description>DAC channel1 8-bit right aligned data
holding register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DACC1DHR</name>
<description>DAC channel1 8-bit right-aligned data
These bits are written by software which specifies
8-bit data for DAC channel1.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>DHR12R2</name>
<displayName>DHR12R2</displayName>
<description>DAC channel2 12-bit right aligned data
holding register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DACC2DHR</name>
<description>DAC channel2 12-bit right-aligned data
These bits are written by software which specifies
12-bit data for DAC channel2.</description>
<bitOffset>0</bitOffset>
<bitWidth>12</bitWidth>
</field>
</fields>
</register>
<register>
<name>DHR12L2</name>
<displayName>DHR12L2</displayName>
<description>DAC channel2 12-bit left aligned data
holding register</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DACC2DHR</name>
<description>DAC channel2 12-bit left-aligned data
These bits are written by software which specify
12-bit data for DAC channel2.</description>
<bitOffset>4</bitOffset>
<bitWidth>12</bitWidth>
</field>
</fields>
</register>
<register>
<name>DHR8R2</name>
<displayName>DHR8R2</displayName>
<description>DAC channel2 8-bit right-aligned data
holding register</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DACC2DHR</name>
<description>DAC channel2 8-bit right-aligned data
These bits are written by software which specifies
8-bit data for DAC channel2.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>DHR12RD</name>
<displayName>DHR12RD</displayName>
<description>Dual DAC 12-bit right-aligned data holding
register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DACC1DHR</name>
<description>DAC channel1 12-bit right-aligned data
These bits are written by software which specifies
12-bit data for DAC channel1.</description>
<bitOffset>0</bitOffset>
<bitWidth>12</bitWidth>
</field>
<field>
<name>DACC2DHR</name>
<description>DAC channel2 12-bit right-aligned data
These bits are written by software which specifies
12-bit data for DAC channel2.</description>
<bitOffset>16</bitOffset>
<bitWidth>12</bitWidth>
</field>
</fields>
</register>
<register>
<name>DHR12LD</name>
<displayName>DHR12LD</displayName>
<description>DUAL DAC 12-bit left aligned data holding
register</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DACC1DHR</name>
<description>DAC channel1 12-bit left-aligned data
These bits are written by software which specifies
12-bit data for DAC channel1.</description>
<bitOffset>4</bitOffset>
<bitWidth>12</bitWidth>
</field>
<field>
<name>DACC2DHR</name>
<description>DAC channel2 12-bit left-aligned data
These bits are written by software which specifies
12-bit data for DAC channel2.</description>
<bitOffset>20</bitOffset>
<bitWidth>12</bitWidth>
</field>
</fields>
</register>
<register>
<name>DHR8RD</name>
<displayName>DHR8RD</displayName>
<description>DUAL DAC 8-bit right aligned data holding
register</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DACC1DHR</name>
<description>DAC channel1 8-bit right-aligned data
These bits are written by software which specifies
8-bit data for DAC channel1.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>DACC2DHR</name>
<description>DAC channel2 8-bit right-aligned data
These bits are written by software which specifies
8-bit data for DAC channel2.</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>DOR1</name>
<displayName>DOR1</displayName>
<description>DAC channel1 data output
register</description>
<addressOffset>0x2C</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DACC1DOR</name>
<description>DAC channel1 data output These bits are
read-only, they contain data output for DAC
channel1.</description>
<bitOffset>0</bitOffset>
<bitWidth>12</bitWidth>
</field>
</fields>
</register>
<register>
<name>DOR2</name>
<displayName>DOR2</displayName>
<description>DAC channel2 data output
register</description>
<addressOffset>0x30</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DACC2DOR</name>
<description>DAC channel2 data output These bits are
read-only, they contain data output for DAC
channel2.</description>
<bitOffset>0</bitOffset>
<bitWidth>12</bitWidth>
</field>
</fields>
</register>
<register>
<name>SR</name>
<displayName>SR</displayName>
<description>DAC status register</description>
<addressOffset>0x34</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DMAUDR1</name>
<description>DAC channel1 DMA underrun flag This bit
is set by hardware and cleared by software (by
writing it to 1).</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CAL_FLAG1</name>
<description>DAC Channel 1 calibration offset status
This bit is set and cleared by hardware</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>BWST1</name>
<description>DAC Channel 1 busy writing sample time
flag This bit is systematically set just after Sample
&amp; Hold mode enable and is set each time the
software writes the register DAC_SHSR1, It is cleared
by hardware when the write operation of DAC_SHSR1 is
complete. (It takes about 3LSI periods of
synchronization).</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>DMAUDR2</name>
<description>DAC channel2 DMA underrun flag This bit
is set by hardware and cleared by software (by
writing it to 1).</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CAL_FLAG2</name>
<description>DAC Channel 2 calibration offset status
This bit is set and cleared by hardware</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>BWST2</name>
<description>DAC Channel 2 busy writing sample time
flag This bit is systematically set just after Sample
&amp; Hold mode enable and is set each time the
software writes the register DAC_SHSR2, It is cleared
by hardware when the write operation of DAC_SHSR2 is
complete. (It takes about 3 LSI periods of
synchronization).</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>CCR</name>
<displayName>CCR</displayName>
<description>DAC calibration control
register</description>
<addressOffset>0x38</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OTRIM1</name>
<description>DAC Channel 1 offset trimming
value</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>OTRIM2</name>
<description>DAC Channel 2 offset trimming
value</description>
<bitOffset>16</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>MCR</name>
<displayName>MCR</displayName>
<description>DAC mode control register</description>
<addressOffset>0x3C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MODE1</name>
<description>DAC Channel 1 mode These bits can be
written only when the DAC is disabled and not in the
calibration mode (when bit EN1=0 and bit CEN1 =0 in
the DAC_CR register). If EN1=1 or CEN1 =1 the write
operation is ignored. They can be set and cleared by
software to select the DAC Channel 1 mode: DAC
Channel 1 in normal Mode DAC Channel 1 in sample
&amp;amp; hold mode</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>MODE2</name>
<description>DAC Channel 2 mode These bits can be
written only when the DAC is disabled and not in the
calibration mode (when bit EN2=0 and bit CEN2 =0 in
the DAC_CR register). If EN2=1 or CEN2 =1 the write
operation is ignored. They can be set and cleared by
software to select the DAC Channel 2 mode: DAC
Channel 2 in normal Mode DAC Channel 2 in sample
&amp;amp; hold mode</description>
<bitOffset>16</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
<register>
<name>SHSR1</name>
<displayName>SHSR1</displayName>
<description>DAC Sample and Hold sample time register
1</description>
<addressOffset>0x40</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TSAMPLE1</name>
<description>DAC Channel 1 sample Time (only valid in
sample &amp;amp; hold mode) These bits can be written
when the DAC channel1 is disabled or also during
normal operation. in the latter case, the write can
be done only when BWSTx of DAC_SR register is low, If
BWSTx=1, the write operation is
ignored.</description>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
</field>
</fields>
</register>
<register>
<name>SHSR2</name>
<displayName>SHSR2</displayName>
<description>DAC Sample and Hold sample time register
2</description>
<addressOffset>0x44</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TSAMPLE2</name>
<description>DAC Channel 2 sample Time (only valid in
sample &amp;amp; hold mode) These bits can be written
when the DAC channel2 is disabled or also during
normal operation. in the latter case, the write can
be done only when BWSTx of DAC_SR register is low, if
BWSTx=1, the write operation is
ignored.</description>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
</field>
</fields>
</register>
<register>
<name>SHHR</name>
<displayName>SHHR</displayName>
<description>DAC Sample and Hold hold time
register</description>
<addressOffset>0x48</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00010001</resetValue>
<fields>
<field>
<name>THOLD1</name>
<description>DAC Channel 1 hold Time (only valid in
sample &amp;amp; hold mode) Hold time= (THOLD[9:0]) x
T LSI</description>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>THOLD2</name>
<description>DAC Channel 2 hold time (only valid in
sample &amp;amp; hold mode). Hold time= (THOLD[9:0])
x T LSI</description>
<bitOffset>16</bitOffset>
<bitWidth>10</bitWidth>
</field>
</fields>
</register>
<register>
<name>SHRR</name>
<displayName>SHRR</displayName>
<description>DAC Sample and Hold refresh time
register</description>
<addressOffset>0x4C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00010001</resetValue>
<fields>
<field>
<name>TREFRESH1</name>
<description>DAC Channel 1 refresh Time (only valid
in sample &amp;amp; hold mode) Refresh time=
(TREFRESH[7:0]) x T LSI</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>TREFRESH2</name>
<description>DAC Channel 2 refresh Time (only valid
in sample &amp;amp; hold mode) Refresh time=
(TREFRESH[7:0]) x T LSI</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>BDMA</name>
<description>BDMA</description>
<groupName>BDMA</groupName>
<baseAddress>0x58025400</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>BDMA_CH1</name>
<description>BDMA channel 1 interrupt</description>
<value>129</value>
</interrupt>
<interrupt>
<name>BDMA_CH2</name>
<description>BDMA channel 2 interrupt</description>
<value>130</value>
</interrupt>
<interrupt>
<name>BDMA_CH3</name>
<description>BDMA channel 3 interrupt</description>
<value>131</value>
</interrupt>
<interrupt>
<name>BDMA_CH4</name>
<description>BDMA channel 4 interrupt</description>
<value>132</value>
</interrupt>
<interrupt>
<name>BDMA_CH5</name>
<description>BDMA channel 5 interrupt</description>
<value>133</value>
</interrupt>
<interrupt>
<name>BDMA_CH6</name>
<description>BDMA channel 6 interrupt</description>
<value>134</value>
</interrupt>
<interrupt>
<name>BDMA_CH7</name>
<description>BDMA channel 7 interrupt</description>
<value>135</value>
</interrupt>
<interrupt>
<name>BDMA_CH8</name>
<description>BDMA channel 8 interrupt</description>
<value>136</value>
</interrupt>
<registers>
<register>
<name>ISR</name>
<displayName>ISR</displayName>
<description>DMA interrupt status register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>GIF1</name>
<description>Channel x global interrupt flag (x =
1..8) This bit is set by hardware. It is cleared by
software writing 1 to the corresponding bit in the
DMA_IFCR register.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIF1</name>
<description>Channel x transfer complete flag (x =
1..8) This bit is set by hardware. It is cleared by
software writing 1 to the corresponding bit in the
DMA_IFCR register.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HTIF1</name>
<description>Channel x half transfer flag (x = 1..8)
This bit is set by hardware. It is cleared by
software writing 1 to the corresponding bit in the
DMA_IFCR register.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEIF1</name>
<description>Channel x transfer error flag (x = 1..8)
This bit is set by hardware. It is cleared by
software writing 1 to the corresponding bit in the
DMA_IFCR register.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GIF2</name>
<description>Channel x global interrupt flag (x =
1..8) This bit is set by hardware. It is cleared by
software writing 1 to the corresponding bit in the
DMA_IFCR register.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIF2</name>
<description>Channel x transfer complete flag (x =
1..8) This bit is set by hardware. It is cleared by
software writing 1 to the corresponding bit in the
DMA_IFCR register.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HTIF2</name>
<description>Channel x half transfer flag (x = 1..8)
This bit is set by hardware. It is cleared by
software writing 1 to the corresponding bit in the
DMA_IFCR register.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEIF2</name>
<description>Channel x transfer error flag (x = 1..8)
This bit is set by hardware. It is cleared by
software writing 1 to the corresponding bit in the
DMA_IFCR register.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GIF3</name>
<description>Channel x global interrupt flag (x =
1..8) This bit is set by hardware. It is cleared by
software writing 1 to the corresponding bit in the
DMA_IFCR register.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIF3</name>
<description>Channel x transfer complete flag (x =
1..8) This bit is set by hardware. It is cleared by
software writing 1 to the corresponding bit in the
DMA_IFCR register.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HTIF3</name>
<description>Channel x half transfer flag (x = 1..8)
This bit is set by hardware. It is cleared by
software writing 1 to the corresponding bit in the
DMA_IFCR register.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEIF3</name>
<description>Channel x transfer error flag (x = 1..8)
This bit is set by hardware. It is cleared by
software writing 1 to the corresponding bit in the
DMA_IFCR register.</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GIF4</name>
<description>Channel x global interrupt flag (x =
1..8) This bit is set by hardware. It is cleared by
software writing 1 to the corresponding bit in the
DMA_IFCR register.</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIF4</name>
<description>Channel x transfer complete flag (x =
1..8) This bit is set by hardware. It is cleared by
software writing 1 to the corresponding bit in the
DMA_IFCR register.</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HTIF4</name>
<description>Channel x half transfer flag (x = 1..8)
This bit is set by hardware. It is cleared by
software writing 1 to the corresponding bit in the
DMA_IFCR register.</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEIF4</name>
<description>Channel x transfer error flag (x = 1..8)
This bit is set by hardware. It is cleared by
software writing 1 to the corresponding bit in the
DMA_IFCR register.</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GIF5</name>
<description>Channel x global interrupt flag (x =
1..8) This bit is set by hardware. It is cleared by
software writing 1 to the corresponding bit in the
DMA_IFCR register.</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIF5</name>
<description>Channel x transfer complete flag (x =
1..8) This bit is set by hardware. It is cleared by
software writing 1 to the corresponding bit in the
DMA_IFCR register.</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HTIF5</name>
<description>Channel x half transfer flag (x = 1..8)
This bit is set by hardware. It is cleared by
software writing 1 to the corresponding bit in the
DMA_IFCR register.</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEIF5</name>
<description>Channel x transfer error flag (x = 1..8)
This bit is set by hardware. It is cleared by
software writing 1 to the corresponding bit in the
DMA_IFCR register.</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GIF6</name>
<description>Channel x global interrupt flag (x =
1..8) This bit is set by hardware. It is cleared by
software writing 1 to the corresponding bit in the
DMA_IFCR register.</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIF6</name>
<description>Channel x transfer complete flag (x =
1..8) This bit is set by hardware. It is cleared by
software writing 1 to the corresponding bit in the
DMA_IFCR register.</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HTIF6</name>
<description>Channel x half transfer flag (x = 1..8)
This bit is set by hardware. It is cleared by
software writing 1 to the corresponding bit in the
DMA_IFCR register.</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEIF6</name>
<description>Channel x transfer error flag (x = 1..8)
This bit is set by hardware. It is cleared by
software writing 1 to the corresponding bit in the
DMA_IFCR register.</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GIF7</name>
<description>Channel x global interrupt flag (x =
1..8) This bit is set by hardware. It is cleared by
software writing 1 to the corresponding bit in the
DMA_IFCR register.</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIF7</name>
<description>Channel x transfer complete flag (x =
1..8) This bit is set by hardware. It is cleared by
software writing 1 to the corresponding bit in the
DMA_IFCR register.</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HTIF7</name>
<description>Channel x half transfer flag (x = 1..8)
This bit is set by hardware. It is cleared by
software writing 1 to the corresponding bit in the
DMA_IFCR register.</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEIF7</name>
<description>Channel x transfer error flag (x = 1..8)
This bit is set by hardware. It is cleared by
software writing 1 to the corresponding bit in the
DMA_IFCR register.</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GIF8</name>
<description>Channel x global interrupt flag (x =
1..8) This bit is set by hardware. It is cleared by
software writing 1 to the corresponding bit in the
DMA_IFCR register.</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIF8</name>
<description>Channel x transfer complete flag (x =
1..8) This bit is set by hardware. It is cleared by
software writing 1 to the corresponding bit in the
DMA_IFCR register.</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HTIF8</name>
<description>Channel x half transfer flag (x = 1..8)
This bit is set by hardware. It is cleared by
software writing 1 to the corresponding bit in the
DMA_IFCR register.</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEIF8</name>
<description>Channel x transfer error flag (x = 1..8)
This bit is set by hardware. It is cleared by
software writing 1 to the corresponding bit in the
DMA_IFCR register.</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>IFCR</name>
<displayName>IFCR</displayName>
<description>DMA interrupt flag clear
register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CGIF1</name>
<description>Channel x global interrupt clear This
bit is set and cleared by software.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTCIF1</name>
<description>Channel x transfer complete clear This
bit is set and cleared by software.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHTIF1</name>
<description>Channel x half transfer clear This bit
is set and cleared by software.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTEIF1</name>
<description>Channel x transfer error clear This bit
is set and cleared by software.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CGIF2</name>
<description>Channel x global interrupt clear This
bit is set and cleared by software.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTCIF2</name>
<description>Channel x transfer complete clear This
bit is set and cleared by software.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHTIF2</name>
<description>Channel x half transfer clear This bit
is set and cleared by software.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTEIF2</name>
<description>Channel x transfer error clear This bit
is set and cleared by software.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CGIF3</name>
<description>Channel x global interrupt clear This
bit is set and cleared by software.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTCIF3</name>
<description>Channel x transfer complete clear This
bit is set and cleared by software.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHTIF3</name>
<description>Channel x half transfer clear This bit
is set and cleared by software.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTEIF3</name>
<description>Channel x transfer error clear This bit
is set and cleared by software.</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CGIF4</name>
<description>Channel x global interrupt clear This
bit is set and cleared by software.</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTCIF4</name>
<description>Channel x transfer complete clear This
bit is set and cleared by software.</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHTIF4</name>
<description>Channel x half transfer clear This bit
is set and cleared by software.</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTEIF4</name>
<description>Channel x transfer error clear This bit
is set and cleared by software.</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CGIF5</name>
<description>Channel x global interrupt clear This
bit is set and cleared by software.</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTCIF5</name>
<description>Channel x transfer complete clear This
bit is set and cleared by software.</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHTIF5</name>
<description>Channel x half transfer clear This bit
is set and cleared by software.</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTEIF5</name>
<description>Channel x transfer error clear This bit
is set and cleared by software.</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CGIF6</name>
<description>Channel x global interrupt clear This
bit is set and cleared by software.</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTCIF6</name>
<description>Channel x transfer complete clear This
bit is set and cleared by software.</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHTIF6</name>
<description>Channel x half transfer clear This bit
is set and cleared by software.</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTEIF6</name>
<description>Channel x transfer error clear This bit
is set and cleared by software.</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CGIF7</name>
<description>Channel x global interrupt clear This
bit is set and cleared by software.</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTCIF7</name>
<description>Channel x transfer complete clear This
bit is set and cleared by software.</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHTIF7</name>
<description>Channel x half transfer clear This bit
is set and cleared by software.</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTEIF7</name>
<description>Channel x transfer error clear This bit
is set and cleared by software.</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CGIF8</name>
<description>Channel x global interrupt clear This
bit is set and cleared by software.</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTCIF8</name>
<description>Channel x transfer complete clear This
bit is set and cleared by software.</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHTIF8</name>
<description>Channel x half transfer clear This bit
is set and cleared by software.</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTEIF8</name>
<description>Channel x transfer error clear This bit
is set and cleared by software.</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCR1</name>
<displayName>CCR1</displayName>
<description>DMA channel x configuration
register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EN</name>
<description>Channel enable This bit is set and
cleared by software.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIE</name>
<description>Transfer complete interrupt enable This
bit is set and cleared by software.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HTIE</name>
<description>Half transfer interrupt enable This bit
is set and cleared by software.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEIE</name>
<description>Transfer error interrupt enable This bit
is set and cleared by software.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DIR</name>
<description>Data transfer direction This bit is set
and cleared by software.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CIRC</name>
<description>Circular mode This bit is set and
cleared by software.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PINC</name>
<description>Peripheral increment mode This bit is
set and cleared by software.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MINC</name>
<description>Memory increment mode This bit is set
and cleared by software.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PSIZE</name>
<description>Peripheral size These bits are set and
cleared by software.</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MSIZE</name>
<description>Memory size These bits are set and
cleared by software.</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PL</name>
<description>Channel priority level These bits are
set and cleared by software.</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MEM2MEM</name>
<description>Memory to memory mode This bit is set
and cleared by software.</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CNDTR1</name>
<displayName>CNDTR1</displayName>
<description>DMA channel x number of data
register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>NDT</name>
<description>Number of data to transfer Number of
data to be transferred (0 up to 65535). This register
can only be written when the channel is disabled.
Once the channel is enabled, this register is
read-only, indicating the remaining bytes to be
transmitted. This register decrements after each DMA
transfer. Once the transfer is completed, this
register can either stay at zero or be reloaded
automatically by the value previously programmed if
the channel is configured in auto-reload mode. If
this register is zero, no transaction can be served
whether the channel is enabled or not.</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CPAR1</name>
<displayName>CPAR1</displayName>
<description>This register must not be written when the
channel is enabled.</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PA</name>
<description>Peripheral address Base address of the
peripheral data register from/to which the data will
be read/written. When PSIZE is 01 (16-bit), the PA[0]
bit is ignored. Access is automatically aligned to a
half-word address. When PSIZE is 10 (32-bit), PA[1:0]
are ignored. Access is automatically aligned to a
word address.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CMAR1</name>
<displayName>CMAR1</displayName>
<description>This register must not be written when the
channel is enabled.</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MA</name>
<description>Memory address Base address of the
memory area from/to which the data will be
read/written. When MSIZE is 01 (16-bit), the MA[0]
bit is ignored. Access is automatically aligned to a
half-word address. When MSIZE is 10 (32-bit), MA[1:0]
are ignored. Access is automatically aligned to a
word address.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCR2</name>
<displayName>CCR2</displayName>
<description>DMA channel x configuration
register</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EN</name>
<description>Channel enable This bit is set and
cleared by software.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIE</name>
<description>Transfer complete interrupt enable This
bit is set and cleared by software.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HTIE</name>
<description>Half transfer interrupt enable This bit
is set and cleared by software.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEIE</name>
<description>Transfer error interrupt enable This bit
is set and cleared by software.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DIR</name>
<description>Data transfer direction This bit is set
and cleared by software.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CIRC</name>
<description>Circular mode This bit is set and
cleared by software.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PINC</name>
<description>Peripheral increment mode This bit is
set and cleared by software.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MINC</name>
<description>Memory increment mode This bit is set
and cleared by software.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PSIZE</name>
<description>Peripheral size These bits are set and
cleared by software.</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MSIZE</name>
<description>Memory size These bits are set and
cleared by software.</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PL</name>
<description>Channel priority level These bits are
set and cleared by software.</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MEM2MEM</name>
<description>Memory to memory mode This bit is set
and cleared by software.</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CNDTR2</name>
<displayName>CNDTR2</displayName>
<description>DMA channel x number of data
register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>NDT</name>
<description>Number of data to transfer Number of
data to be transferred (0 up to 65535). This register
can only be written when the channel is disabled.
Once the channel is enabled, this register is
read-only, indicating the remaining bytes to be
transmitted. This register decrements after each DMA
transfer. Once the transfer is completed, this
register can either stay at zero or be reloaded
automatically by the value previously programmed if
the channel is configured in auto-reload mode. If
this register is zero, no transaction can be served
whether the channel is enabled or not.</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CPAR2</name>
<displayName>CPAR2</displayName>
<description>This register must not be written when the
channel is enabled.</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PA</name>
<description>Peripheral address Base address of the
peripheral data register from/to which the data will
be read/written. When PSIZE is 01 (16-bit), the PA[0]
bit is ignored. Access is automatically aligned to a
half-word address. When PSIZE is 10 (32-bit), PA[1:0]
are ignored. Access is automatically aligned to a
word address.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CMAR2</name>
<displayName>CMAR2</displayName>
<description>This register must not be written when the
channel is enabled.</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MA</name>
<description>Memory address Base address of the
memory area from/to which the data will be
read/written. When MSIZE is 01 (16-bit), the MA[0]
bit is ignored. Access is automatically aligned to a
half-word address. When MSIZE is 10 (32-bit), MA[1:0]
are ignored. Access is automatically aligned to a
word address.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCR3</name>
<displayName>CCR3</displayName>
<description>DMA channel x configuration
register</description>
<addressOffset>0x30</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EN</name>
<description>Channel enable This bit is set and
cleared by software.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIE</name>
<description>Transfer complete interrupt enable This
bit is set and cleared by software.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HTIE</name>
<description>Half transfer interrupt enable This bit
is set and cleared by software.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEIE</name>
<description>Transfer error interrupt enable This bit
is set and cleared by software.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DIR</name>
<description>Data transfer direction This bit is set
and cleared by software.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CIRC</name>
<description>Circular mode This bit is set and
cleared by software.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PINC</name>
<description>Peripheral increment mode This bit is
set and cleared by software.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MINC</name>
<description>Memory increment mode This bit is set
and cleared by software.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PSIZE</name>
<description>Peripheral size These bits are set and
cleared by software.</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MSIZE</name>
<description>Memory size These bits are set and
cleared by software.</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PL</name>
<description>Channel priority level These bits are
set and cleared by software.</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MEM2MEM</name>
<description>Memory to memory mode This bit is set
and cleared by software.</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CNDTR3</name>
<displayName>CNDTR3</displayName>
<description>DMA channel x number of data
register</description>
<addressOffset>0x34</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>NDT</name>
<description>Number of data to transfer Number of
data to be transferred (0 up to 65535). This register
can only be written when the channel is disabled.
Once the channel is enabled, this register is
read-only, indicating the remaining bytes to be
transmitted. This register decrements after each DMA
transfer. Once the transfer is completed, this
register can either stay at zero or be reloaded
automatically by the value previously programmed if
the channel is configured in auto-reload mode. If
this register is zero, no transaction can be served
whether the channel is enabled or not.</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CPAR3</name>
<displayName>CPAR3</displayName>
<description>This register must not be written when the
channel is enabled.</description>
<addressOffset>0x38</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PA</name>
<description>Peripheral address Base address of the
peripheral data register from/to which the data will
be read/written. When PSIZE is 01 (16-bit), the PA[0]
bit is ignored. Access is automatically aligned to a
half-word address. When PSIZE is 10 (32-bit), PA[1:0]
are ignored. Access is automatically aligned to a
word address.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CMAR3</name>
<displayName>CMAR3</displayName>
<description>This register must not be written when the
channel is enabled.</description>
<addressOffset>0x3C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MA</name>
<description>Memory address Base address of the
memory area from/to which the data will be
read/written. When MSIZE is 01 (16-bit), the MA[0]
bit is ignored. Access is automatically aligned to a
half-word address. When MSIZE is 10 (32-bit), MA[1:0]
are ignored. Access is automatically aligned to a
word address.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCR4</name>
<displayName>CCR4</displayName>
<description>DMA channel x configuration
register</description>
<addressOffset>0x44</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EN</name>
<description>Channel enable This bit is set and
cleared by software.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIE</name>
<description>Transfer complete interrupt enable This
bit is set and cleared by software.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HTIE</name>
<description>Half transfer interrupt enable This bit
is set and cleared by software.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEIE</name>
<description>Transfer error interrupt enable This bit
is set and cleared by software.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DIR</name>
<description>Data transfer direction This bit is set
and cleared by software.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CIRC</name>
<description>Circular mode This bit is set and
cleared by software.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PINC</name>
<description>Peripheral increment mode This bit is
set and cleared by software.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MINC</name>
<description>Memory increment mode This bit is set
and cleared by software.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PSIZE</name>
<description>Peripheral size These bits are set and
cleared by software.</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MSIZE</name>
<description>Memory size These bits are set and
cleared by software.</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PL</name>
<description>Channel priority level These bits are
set and cleared by software.</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MEM2MEM</name>
<description>Memory to memory mode This bit is set
and cleared by software.</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CNDTR4</name>
<displayName>CNDTR4</displayName>
<description>DMA channel x number of data
register</description>
<addressOffset>0x48</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>NDT</name>
<description>Number of data to transfer Number of
data to be transferred (0 up to 65535). This register
can only be written when the channel is disabled.
Once the channel is enabled, this register is
read-only, indicating the remaining bytes to be
transmitted. This register decrements after each DMA
transfer. Once the transfer is completed, this
register can either stay at zero or be reloaded
automatically by the value previously programmed if
the channel is configured in auto-reload mode. If
this register is zero, no transaction can be served
whether the channel is enabled or not.</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CPAR4</name>
<displayName>CPAR4</displayName>
<description>This register must not be written when the
channel is enabled.</description>
<addressOffset>0x4C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PA</name>
<description>Peripheral address Base address of the
peripheral data register from/to which the data will
be read/written. When PSIZE is 01 (16-bit), the PA[0]
bit is ignored. Access is automatically aligned to a
half-word address. When PSIZE is 10 (32-bit), PA[1:0]
are ignored. Access is automatically aligned to a
word address.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CMAR4</name>
<displayName>CMAR4</displayName>
<description>This register must not be written when the
channel is enabled.</description>
<addressOffset>0x50</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MA</name>
<description>Memory address Base address of the
memory area from/to which the data will be
read/written. When MSIZE is 01 (16-bit), the MA[0]
bit is ignored. Access is automatically aligned to a
half-word address. When MSIZE is 10 (32-bit), MA[1:0]
are ignored. Access is automatically aligned to a
word address.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCR5</name>
<displayName>CCR5</displayName>
<description>DMA channel x configuration
register</description>
<addressOffset>0x58</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EN</name>
<description>Channel enable This bit is set and
cleared by software.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIE</name>
<description>Transfer complete interrupt enable This
bit is set and cleared by software.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HTIE</name>
<description>Half transfer interrupt enable This bit
is set and cleared by software.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEIE</name>
<description>Transfer error interrupt enable This bit
is set and cleared by software.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DIR</name>
<description>Data transfer direction This bit is set
and cleared by software.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CIRC</name>
<description>Circular mode This bit is set and
cleared by software.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PINC</name>
<description>Peripheral increment mode This bit is
set and cleared by software.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MINC</name>
<description>Memory increment mode This bit is set
and cleared by software.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PSIZE</name>
<description>Peripheral size These bits are set and
cleared by software.</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MSIZE</name>
<description>Memory size These bits are set and
cleared by software.</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PL</name>
<description>Channel priority level These bits are
set and cleared by software.</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MEM2MEM</name>
<description>Memory to memory mode This bit is set
and cleared by software.</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CNDTR5</name>
<displayName>CNDTR5</displayName>
<description>DMA channel x number of data
register</description>
<addressOffset>0x5C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>NDT</name>
<description>Number of data to transfer Number of
data to be transferred (0 up to 65535). This register
can only be written when the channel is disabled.
Once the channel is enabled, this register is
read-only, indicating the remaining bytes to be
transmitted. This register decrements after each DMA
transfer. Once the transfer is completed, this
register can either stay at zero or be reloaded
automatically by the value previously programmed if
the channel is configured in auto-reload mode. If
this register is zero, no transaction can be served
whether the channel is enabled or not.</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CPAR5</name>
<displayName>CPAR5</displayName>
<description>This register must not be written when the
channel is enabled.</description>
<addressOffset>0x60</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PA</name>
<description>Peripheral address Base address of the
peripheral data register from/to which the data will
be read/written. When PSIZE is 01 (16-bit), the PA[0]
bit is ignored. Access is automatically aligned to a
half-word address. When PSIZE is 10 (32-bit), PA[1:0]
are ignored. Access is automatically aligned to a
word address.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CMAR5</name>
<displayName>CMAR5</displayName>
<description>This register must not be written when the
channel is enabled.</description>
<addressOffset>0x64</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MA</name>
<description>Memory address Base address of the
memory area from/to which the data will be
read/written. When MSIZE is 01 (16-bit), the MA[0]
bit is ignored. Access is automatically aligned to a
half-word address. When MSIZE is 10 (32-bit), MA[1:0]
are ignored. Access is automatically aligned to a
word address.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCR6</name>
<displayName>CCR6</displayName>
<description>DMA channel x configuration
register</description>
<addressOffset>0x6C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EN</name>
<description>Channel enable This bit is set and
cleared by software.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIE</name>
<description>Transfer complete interrupt enable This
bit is set and cleared by software.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HTIE</name>
<description>Half transfer interrupt enable This bit
is set and cleared by software.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEIE</name>
<description>Transfer error interrupt enable This bit
is set and cleared by software.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DIR</name>
<description>Data transfer direction This bit is set
and cleared by software.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CIRC</name>
<description>Circular mode This bit is set and
cleared by software.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PINC</name>
<description>Peripheral increment mode This bit is
set and cleared by software.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MINC</name>
<description>Memory increment mode This bit is set
and cleared by software.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PSIZE</name>
<description>Peripheral size These bits are set and
cleared by software.</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MSIZE</name>
<description>Memory size These bits are set and
cleared by software.</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PL</name>
<description>Channel priority level These bits are
set and cleared by software.</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MEM2MEM</name>
<description>Memory to memory mode This bit is set
and cleared by software.</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CNDTR6</name>
<displayName>CNDTR6</displayName>
<description>DMA channel x number of data
register</description>
<addressOffset>0x70</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>NDT</name>
<description>Number of data to transfer Number of
data to be transferred (0 up to 65535). This register
can only be written when the channel is disabled.
Once the channel is enabled, this register is
read-only, indicating the remaining bytes to be
transmitted. This register decrements after each DMA
transfer. Once the transfer is completed, this
register can either stay at zero or be reloaded
automatically by the value previously programmed if
the channel is configured in auto-reload mode. If
this register is zero, no transaction can be served
whether the channel is enabled or not.</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CPAR6</name>
<displayName>CPAR6</displayName>
<description>This register must not be written when the
channel is enabled.</description>
<addressOffset>0x74</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PA</name>
<description>Peripheral address Base address of the
peripheral data register from/to which the data will
be read/written. When PSIZE is 01 (16-bit), the PA[0]
bit is ignored. Access is automatically aligned to a
half-word address. When PSIZE is 10 (32-bit), PA[1:0]
are ignored. Access is automatically aligned to a
word address.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CMAR6</name>
<displayName>CMAR6</displayName>
<description>This register must not be written when the
channel is enabled.</description>
<addressOffset>0x78</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MA</name>
<description>Memory address Base address of the
memory area from/to which the data will be
read/written. When MSIZE is 01 (16-bit), the MA[0]
bit is ignored. Access is automatically aligned to a
half-word address. When MSIZE is 10 (32-bit), MA[1:0]
are ignored. Access is automatically aligned to a
word address.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCR7</name>
<displayName>CCR7</displayName>
<description>DMA channel x configuration
register</description>
<addressOffset>0x80</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EN</name>
<description>Channel enable This bit is set and
cleared by software.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIE</name>
<description>Transfer complete interrupt enable This
bit is set and cleared by software.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HTIE</name>
<description>Half transfer interrupt enable This bit
is set and cleared by software.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEIE</name>
<description>Transfer error interrupt enable This bit
is set and cleared by software.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DIR</name>
<description>Data transfer direction This bit is set
and cleared by software.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CIRC</name>
<description>Circular mode This bit is set and
cleared by software.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PINC</name>
<description>Peripheral increment mode This bit is
set and cleared by software.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MINC</name>
<description>Memory increment mode This bit is set
and cleared by software.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PSIZE</name>
<description>Peripheral size These bits are set and
cleared by software.</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MSIZE</name>
<description>Memory size These bits are set and
cleared by software.</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PL</name>
<description>Channel priority level These bits are
set and cleared by software.</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MEM2MEM</name>
<description>Memory to memory mode This bit is set
and cleared by software.</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CNDTR7</name>
<displayName>CNDTR7</displayName>
<description>DMA channel x number of data
register</description>
<addressOffset>0x84</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>NDT</name>
<description>Number of data to transfer Number of
data to be transferred (0 up to 65535). This register
can only be written when the channel is disabled.
Once the channel is enabled, this register is
read-only, indicating the remaining bytes to be
transmitted. This register decrements after each DMA
transfer. Once the transfer is completed, this
register can either stay at zero or be reloaded
automatically by the value previously programmed if
the channel is configured in auto-reload mode. If
this register is zero, no transaction can be served
whether the channel is enabled or not.</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CPAR7</name>
<displayName>CPAR7</displayName>
<description>This register must not be written when the
channel is enabled.</description>
<addressOffset>0x88</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PA</name>
<description>Peripheral address Base address of the
peripheral data register from/to which the data will
be read/written. When PSIZE is 01 (16-bit), the PA[0]
bit is ignored. Access is automatically aligned to a
half-word address. When PSIZE is 10 (32-bit), PA[1:0]
are ignored. Access is automatically aligned to a
word address.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CMAR7</name>
<displayName>CMAR7</displayName>
<description>This register must not be written when the
channel is enabled.</description>
<addressOffset>0x8C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MA</name>
<description>Memory address Base address of the
memory area from/to which the data will be
read/written. When MSIZE is 01 (16-bit), the MA[0]
bit is ignored. Access is automatically aligned to a
half-word address. When MSIZE is 10 (32-bit), MA[1:0]
are ignored. Access is automatically aligned to a
word address.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCR8</name>
<displayName>CCR8</displayName>
<description>DMA channel x configuration
register</description>
<addressOffset>0x94</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EN</name>
<description>Channel enable This bit is set and
cleared by software.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIE</name>
<description>Transfer complete interrupt enable This
bit is set and cleared by software.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HTIE</name>
<description>Half transfer interrupt enable This bit
is set and cleared by software.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEIE</name>
<description>Transfer error interrupt enable This bit
is set and cleared by software.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DIR</name>
<description>Data transfer direction This bit is set
and cleared by software.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CIRC</name>
<description>Circular mode This bit is set and
cleared by software.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PINC</name>
<description>Peripheral increment mode This bit is
set and cleared by software.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MINC</name>
<description>Memory increment mode This bit is set
and cleared by software.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PSIZE</name>
<description>Peripheral size These bits are set and
cleared by software.</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MSIZE</name>
<description>Memory size These bits are set and
cleared by software.</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PL</name>
<description>Channel priority level These bits are
set and cleared by software.</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MEM2MEM</name>
<description>Memory to memory mode This bit is set
and cleared by software.</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CNDTR8</name>
<displayName>CNDTR8</displayName>
<description>DMA channel x number of data
register</description>
<addressOffset>0x98</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>NDT</name>
<description>Number of data to transfer Number of
data to be transferred (0 up to 65535). This register
can only be written when the channel is disabled.
Once the channel is enabled, this register is
read-only, indicating the remaining bytes to be
transmitted. This register decrements after each DMA
transfer. Once the transfer is completed, this
register can either stay at zero or be reloaded
automatically by the value previously programmed if
the channel is configured in auto-reload mode. If
this register is zero, no transaction can be served
whether the channel is enabled or not.</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CPAR8</name>
<displayName>CPAR8</displayName>
<description>This register must not be written when the
channel is enabled.</description>
<addressOffset>0x9C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PA</name>
<description>Peripheral address Base address of the
peripheral data register from/to which the data will
be read/written. When PSIZE is 01 (16-bit), the PA[0]
bit is ignored. Access is automatically aligned to a
half-word address. When PSIZE is 10 (32-bit), PA[1:0]
are ignored. Access is automatically aligned to a
word address.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CMAR8</name>
<displayName>CMAR8</displayName>
<description>This register must not be written when the
channel is enabled.</description>
<addressOffset>0xA0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MA</name>
<description>Memory address Base address of the
memory area from/to which the data will be
read/written. When MSIZE is 01 (16-bit), the MA[0]
bit is ignored. Access is automatically aligned to a
half-word address. When MSIZE is 10 (32-bit), MA[1:0]
are ignored. Access is automatically aligned to a
word address.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>DMA2D</name>
<description>DMA2D</description>
<groupName>DMA2D</groupName>
<baseAddress>0x52001000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>DMA2D</name>
<description>DMA2D global interrupt</description>
<value>90</value>
</interrupt>
<registers>
<register>
<name>CR</name>
<displayName>CR</displayName>
<description>DMA2D control register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>START</name>
<description>Start This bit can be used to launch the
DMA2D according to the parameters loaded in the
various configuration registers</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SUSP</name>
<description>Suspend This bit can be used to suspend
the current transfer. This bit is set and reset by
software. It is automatically reset by hardware when
the START bit is reset.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ABORT</name>
<description>Abort This bit can be used to abort the
current transfer. This bit is set by software and is
automatically reset by hardware when the START bit is
reset.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEIE</name>
<description>Transfer error interrupt enable This bit
is set and cleared by software.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIE</name>
<description>Transfer complete interrupt enable This
bit is set and cleared by software.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TWIE</name>
<description>Transfer watermark interrupt enable This
bit is set and cleared by software.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CAEIE</name>
<description>CLUT access error interrupt enable This
bit is set and cleared by software.</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTCIE</name>
<description>CLUT transfer complete interrupt enable
This bit is set and cleared by
software.</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CEIE</name>
<description>Configuration Error Interrupt Enable
This bit is set and cleared by
software.</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MODE</name>
<description>DMA2D mode This bit is set and cleared
by software. It cannot be modified while a transfer
is ongoing.</description>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>ISR</name>
<displayName>ISR</displayName>
<description>DMA2D Interrupt Status
Register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TEIF</name>
<description>Transfer error interrupt flag This bit
is set when an error occurs during a DMA transfer
(data transfer or automatic CLUT
loading).</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIF</name>
<description>Transfer complete interrupt flag This
bit is set when a DMA2D transfer operation is
complete (data transfer only).</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TWIF</name>
<description>Transfer watermark interrupt flag This
bit is set when the last pixel of the watermarked
line has been transferred.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CAEIF</name>
<description>CLUT access error interrupt flag This
bit is set when the CPU accesses the CLUT while the
CLUT is being automatically copied from a system
memory to the internal DMA2D.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTCIF</name>
<description>CLUT transfer complete interrupt flag
This bit is set when the CLUT copy from a system
memory area to the internal DMA2D memory is
complete.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CEIF</name>
<description>Configuration error interrupt flag This
bit is set when the START bit of DMA2D_CR,
DMA2DFGPFCCR or DMA2D_BGPFCCR is set and a wrong
configuration has been programmed.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>IFCR</name>
<displayName>IFCR</displayName>
<description>DMA2D interrupt flag clear
register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CTEIF</name>
<description>Clear Transfer error interrupt flag
Programming this bit to 1 clears the TEIF flag in the
DMA2D_ISR register</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTCIF</name>
<description>Clear transfer complete interrupt flag
Programming this bit to 1 clears the TCIF flag in the
DMA2D_ISR register</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTWIF</name>
<description>Clear transfer watermark interrupt flag
Programming this bit to 1 clears the TWIF flag in the
DMA2D_ISR register</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CAECIF</name>
<description>Clear CLUT access error interrupt flag
Programming this bit to 1 clears the CAEIF flag in
the DMA2D_ISR register</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CCTCIF</name>
<description>Clear CLUT transfer complete interrupt
flag Programming this bit to 1 clears the CTCIF flag
in the DMA2D_ISR register</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CCEIF</name>
<description>Clear configuration error interrupt flag
Programming this bit to 1 clears the CEIF flag in the
DMA2D_ISR register</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FGMAR</name>
<displayName>FGMAR</displayName>
<description>DMA2D foreground memory address
register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MA</name>
<description>Memory address Address of the data used
for the foreground image. This register can only be
written when data transfers are disabled. Once the
data transfer has started, this register is
read-only. The address alignment must match the image
format selected e.g. a 32-bit per pixel format must
be 32-bit aligned, a 16-bit per pixel format must be
16-bit aligned and a 4-bit per pixel format must be
8-bit aligned.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>FGOR</name>
<displayName>FGOR</displayName>
<description>DMA2D foreground offset
register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LO</name>
<description>Line offset Line offset used for the
foreground expressed in pixel. This value is used to
generate the address. It is added at the end of each
line to determine the starting address of the next
line. These bits can only be written when data
transfers are disabled. Once a data transfer has
started, they become read-only. If the image format
is 4-bit per pixel, the line offset must be
even.</description>
<bitOffset>0</bitOffset>
<bitWidth>14</bitWidth>
</field>
</fields>
</register>
<register>
<name>BGMAR</name>
<displayName>BGMAR</displayName>
<description>DMA2D background memory address
register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MA</name>
<description>Memory address Address of the data used
for the background image. This register can only be
written when data transfers are disabled. Once a data
transfer has started, this register is read-only. The
address alignment must match the image format
selected e.g. a 32-bit per pixel format must be
32-bit aligned, a 16-bit per pixel format must be
16-bit aligned and a 4-bit per pixel format must be
8-bit aligned.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>BGOR</name>
<displayName>BGOR</displayName>
<description>DMA2D background offset
register</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LO</name>
<description>Line offset Line offset used for the
background image (expressed in pixel). This value is
used for the address generation. It is added at the
end of each line to determine the starting address of
the next line. These bits can only be written when
data transfers are disabled. Once data transfer has
started, they become read-only. If the image format
is 4-bit per pixel, the line offset must be
even.</description>
<bitOffset>0</bitOffset>
<bitWidth>14</bitWidth>
</field>
</fields>
</register>
<register>
<name>FGPFCCR</name>
<displayName>FGPFCCR</displayName>
<description>DMA2D foreground PFC control
register</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CM</name>
<description>Color mode These bits defines the color
format of the foreground image. They can only be
written when data transfers are disabled. Once the
transfer has started, they are read-only. others:
meaningless</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>CCM</name>
<description>CLUT color mode This bit defines the
color format of the CLUT. It can only be written when
the transfer is disabled. Once the CLUT transfer has
started, this bit is read-only.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>START</name>
<description>Start This bit can be set to start the
automatic loading of the CLUT. It is automatically
reset: ** at the end of the transfer ** when the
transfer is aborted by the user application by
setting the ABORT bit in DMA2D_CR ** when a transfer
error occurs ** when the transfer has not started due
to a configuration error or another transfer
operation already ongoing (data transfer or automatic
background CLUT transfer).</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CS</name>
<description>CLUT size These bits define the size of
the CLUT used for the foreground image. Once the CLUT
transfer has started, this field is read-only. The
number of CLUT entries is equal to CS[7:0] +
1.</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>AM</name>
<description>Alpha mode These bits select the alpha
channel value to be used for the foreground image.
They can only be written data the transfer are
disabled. Once the transfer has started, they become
read-only. other configurations are
meaningless</description>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CSS</name>
<description>Chroma Sub-Sampling These bits define
the chroma sub-sampling mode for YCbCr color mode.
Once the transfer has started, these bits are
read-only. others: meaningless</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>AI</name>
<description>Alpha Inverted This bit inverts the
alpha value. Once the transfer has started, this bit
is read-only.</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RBS</name>
<description>Red Blue Swap This bit allows to swap
the R &amp;amp; B to support BGR or ABGR color
formats. Once the transfer has started, this bit is
read-only.</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ALPHA</name>
<description>Alpha value These bits define a fixed
alpha channel value which can replace the original
alpha value or be multiplied by the original alpha
value according to the alpha mode selected through
the AM[1:0] bits. These bits can only be written when
data transfers are disabled. Once a transfer has
started, they become read-only.</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>