diff --git a/BUILD_WITH_CMAKE.md b/BUILD_WITH_CMAKE.md
new file mode 100644
index 0000000..917bdf5
--- /dev/null
+++ b/BUILD_WITH_CMAKE.md
@@ -0,0 +1,74 @@
+
+## Requirements:
+
+### Known Issues
+Ubuntu 22.04 has some version issues with the compile toolchain, consider using a newer version or other distribution or docker. Or solve the issue and add it here.
+
+### Steps 
+1. `cmake`
+2. `arm-none-eabi-gcc arm-none-eabi-gcc arm-none-eabi-binutils arm-none-eabi-gdb arm-none-eabi-newlib`
+3. `doxygen` 
+4. `graphviz`
+5. `rustup`  || Install using your packet manager or alternatively use the rust install script:  `curl --proto '=https' --tlsv1.2 -sSf https://sh.rustup.rs | sh`
+
+
+
+6. At last: Satisfy Rust requirements 
+
+```sh
+cd ../mission_rust
+cargo update 
+rustup toolchain install nightly
+rustup component add rust-src --toolchain nightly-x86_64-unknown-linux-gnu
+rustup override set nightly
+cargo build -Z build-std
+```
+
+## Build the FSBL
+
+FSBL is the First Stage Boot Loader and prepares the CPU and FPGA configuration for booting up the Second Stage Bootloader and finally the flight software. 
+
+```sh
+cd lib/sw_apps/zynq_fsbl/src
+make BOARD=zed SHELL=/bin/bash
+```
+
+
+If you want, copy the fsbl.elf to the docker/compile_fsbl directory for easier access:
+
+```sh
+cp embeddedsw/lib/sw_apps/zynq_fsbl/src/fsbl.elf .
+```
+
+## Steps
+
+## mission_rust
+
+
+## obsw
+
+##### Clone the submodules (FreeRTOS and lwIP):
+```sh
+git submodule init
+git submodule update
+```
+
+##### To build the obsw, run the following command
+
+Once:
+```sh
+mkdir -p build
+cd build
+```
+
+After adding a new .c file:
+```sh
+cmake -DCMAKE_TOOLCHAIN_FILE=../bsp_z7/cmake/arm-none-eabi.toolchain .. 
+```
+
+Every time
+```sh
+make -j 8"
+```
+
+The romeo-obsw binary can now be found in the `build` directory. The next step to deploy it is here: [DEBUG_ON_ZEDBOARD.md](./DEBUG_ON_ZEDBOARD.md).
\ No newline at end of file
diff --git a/DEBUG_ON_ZEDBOARD.md b/DEBUG_ON_ZEDBOARD.md
new file mode 100644
index 0000000..885a1d3
--- /dev/null
+++ b/DEBUG_ON_ZEDBOARD.md
@@ -0,0 +1,53 @@
+
+# Debugging on `zedboard`
+`zedboard` is the `Xilinx Zynq-7000` development board. 
+## Requirements [TBC]:
+- `OpenOCD`
+- `arm-none-eabi-gdb` 
+
+## Steps
+TODO: discuss this with paul
+1. Set Zedboard `boot mode` to JTAG and connect debugging PC to zedboard JTAG and UART USB port.
+TODO: what is which port, use distinct name/add a graphic
+2. On PC connected to zedboard JTAG USB port:
+```sh
+openocd -f board/digilent_zedboard.cfg
+```
+
+If you have one around, load bitstream at startup (go get a coffee, takes time with onboard JTAG, blue LED lights up when done):
+```sh
+openocd -f board/digilent_zedboard.cfg -c "init" -c "pld load 0 system.bit"
+```
+
+3. To use JTAG Boot for the OBSW, you first need to run the FSBL once.
+
+On build PC (adapt IP if different from debugging PC) in the folder where you build the FSBL as above:
+```sh
+arm-none-eabi-gdb fsbl.elf
+>target extended-remote localhost:3333
+>load
+>cont
+>^C^D^D
+```
+
+### (Optional) Automate this run:
+```sh
+arm-none-eabi-gdb fsbl.elf -iex "target extended-remote localhost:3333" -ex "set pagination off" -ex "load" -ex "break FsblHandoffJtagExit" -ex "cont" -ex="set confirm off" -ex "exit"
+```
+
+It will exit after the Zynq is configured and ready to firmware.
+
+Then load the actual OBSW, in the build (`build_cli` in the example above) folder run:
+```sh
+arm-none-eabi-gdb romeo-obsw
+>target extended-remote localhost:3333
+>load
+>cont
+```
+
+Again, `Command Line Interface (CLI) commands` can be moved to the GNU Debugger (DGB) call. Also, a small function is used as marker to return from GDB if the mission code returns (should not happen in production but might be useful during testing).
+```sh
+arm-none-eabi-gdb romeo-obsw -iex "target extended-remote localhost:3333" -ex "set pagination off" -ex "load" -ex "break done" -ex "cont" -ex="set confirm off" -ex "exit"
+```
+
+UART USB port should output something at `115200baud`, (I use moserial to monitor).
diff --git a/docker/compile_fsbl/.gitignore b/docker/compile_fsbl/.gitignore
new file mode 100644
index 0000000..43c5ba6
--- /dev/null
+++ b/docker/compile_fsbl/.gitignore
@@ -0,0 +1 @@
+embeddedsw
\ No newline at end of file
diff --git a/mission/testIp.c b/mission/testIp.c
index 786918b..250b35e 100644
--- a/mission/testIp.c
+++ b/mission/testIp.c
@@ -160,71 +160,71 @@ static const uint16_t stackSizeWords = 512;
 StaticTask_t xTaskBuffer;
 StackType_t xStack[512];
 
-void testIp() {
+// void testIp() {
 
-  uartIsrQueue =
-      xQueueCreateStatic(QUEUE_LENGTH, 1, ucQueueStorageArea, &xStaticQueue);
+//   uartIsrQueue =
+//       xQueueCreateStatic(QUEUE_LENGTH, 1, ucQueueStorageArea, &xStaticQueue);
 
-  lwip_init();
+//   lwip_init();
 
-  ip4_addr_t slip_addr = {PP_HTONL(LWIP_MAKEU32(10, 0, 0, 32))},
-             slip_mask = {PP_HTONL(LWIP_MAKEU32(255, 255, 255, 0))},
-             slip_gw = {PP_HTONL(LWIP_MAKEU32(10, 0, 0, 1))};
+//   ip4_addr_t slip_addr = {PP_HTONL(LWIP_MAKEU32(10, 0, 0, 32))},
+//              slip_mask = {PP_HTONL(LWIP_MAKEU32(255, 255, 255, 0))},
+//              slip_gw = {PP_HTONL(LWIP_MAKEU32(10, 0, 0, 1))};
 
-  netif_add(&netif, &slip_addr, &slip_mask, &slip_gw, NULL, slipif_init,
-            netif_input);
+//   netif_add(&netif, &slip_addr, &slip_mask, &slip_gw, NULL, slipif_init,
+//             netif_input);
 
-  netif_set_default(&netif);
-  // should be done by driver, which does not do it, so we do it here
-  netif_set_link_up(&netif);
-  netif_set_up(&netif);
+//   netif_set_default(&netif);
+//   // should be done by driver, which does not do it, so we do it here
+//   netif_set_link_up(&netif);
+//   netif_set_up(&netif);
 
-  udpecho_raw_pcb = udp_new_ip_type(IPADDR_TYPE_ANY);
-  if (udpecho_raw_pcb != NULL) {
-    err_t err;
+//   udpecho_raw_pcb = udp_new_ip_type(IPADDR_TYPE_ANY);
+//   if (udpecho_raw_pcb != NULL) {
+//     err_t err;
 
-    err = udp_bind(udpecho_raw_pcb, IP_ANY_TYPE, 7);
-    if (err == ERR_OK) {
-      udp_recv(udpecho_raw_pcb, udpecho_raw_recv, NULL);
-    } else {
-      /* TODO */
-    }
-  } else {
-    /* TODO */
-  }
+//     err = udp_bind(udpecho_raw_pcb, IP_ANY_TYPE, 7);
+//     if (err == ERR_OK) {
+//       udp_recv(udpecho_raw_pcb, udpecho_raw_recv, NULL);
+//     } else {
+//       /* TODO */
+//     }
+//   } else {
+//     /* TODO */
+//   }
 
-  /* Install the UART Interrupt handler. */
-  BaseType_t xStatus =
-      XScuGic_Connect(&xInterruptController, STDIN_INT_NR,
-                      (Xil_ExceptionHandler)handleUARTInt, NULL);
-  configASSERT(xStatus == XST_SUCCESS);
-  (void)xStatus; /* Remove compiler warning if configASSERT() is not defined. */
+//   /* Install the UART Interrupt handler. */
+//   BaseType_t xStatus =
+//       XScuGic_Connect(&xInterruptController, STDIN_INT_NR,
+//                       (Xil_ExceptionHandler)handleUARTInt, NULL);
+//   configASSERT(xStatus == XST_SUCCESS);
+//   (void)xStatus; /* Remove compiler warning if configASSERT() is not defined. */
 
-  // Set trigger level to 62 of 64 bytes, giving interrupt some time to react
-  XUartPs_WriteReg(STDIN_BASEADDRESS, XUARTPS_RXWM_OFFSET, 62);
+//   // Set trigger level to 62 of 64 bytes, giving interrupt some time to react
+//   XUartPs_WriteReg(STDIN_BASEADDRESS, XUARTPS_RXWM_OFFSET, 62);
 
-  // Setting the rx timeout to n*4 -1 bits
-  XUartPs_WriteReg(STDIN_BASEADDRESS, XUARTPS_RXTOUT_OFFSET, 50);
+//   // Setting the rx timeout to n*4 -1 bits
+//   XUartPs_WriteReg(STDIN_BASEADDRESS, XUARTPS_RXTOUT_OFFSET, 50);
 
-  // enable UART Interrupts
-  u32 mask = XUARTPS_IXR_RTRIG | XUARTPS_IXR_RXOVR | XUARTPS_IXR_RXFULL |
-             XUARTPS_IXR_TOUT;
-  /* Write the mask to the IER Register */
-  XUartPs_WriteReg(STDIN_BASEADDRESS, XUARTPS_IER_OFFSET, mask);
-  /* Write the inverse of the Mask to the IDR register */
-  XUartPs_WriteReg(STDIN_BASEADDRESS, XUARTPS_IDR_OFFSET, (~mask));
+//   // enable UART Interrupts
+//   u32 mask = XUARTPS_IXR_RTRIG | XUARTPS_IXR_RXOVR | XUARTPS_IXR_RXFULL |
+//              XUARTPS_IXR_TOUT;
+//   /* Write the mask to the IER Register */
+//   XUartPs_WriteReg(STDIN_BASEADDRESS, XUARTPS_IER_OFFSET, mask);
+//   /* Write the inverse of the Mask to the IDR register */
+//   XUartPs_WriteReg(STDIN_BASEADDRESS, XUARTPS_IDR_OFFSET, (~mask));
 
-  /* Enable the interrupt for the UART1 in the interrupt controller. */
-  XScuGic_Enable(&xInterruptController, STDIN_INT_NR);
+//   /* Enable the interrupt for the UART1 in the interrupt controller. */
+//   XScuGic_Enable(&xInterruptController, STDIN_INT_NR);
 
-  // Start lwip task
-  xTaskCreateStatic(
-      lwip_main,      /* The function that implements the task. */
-      "lwip",         /* The text name assigned to the task - for debug
-                              only as it is not used by the kernel. */
-      stackSizeWords, /* The size of the stack to allocate to the task. */
-      NULL,           /* The parameter passed to the task - not used in this
-                                    simple case. */
-      4,              /* The priority assigned to the task. */
-      xStack, &xTaskBuffer);
-}
\ No newline at end of file
+//   // Start lwip task
+//   xTaskCreateStatic(
+//       lwip_main,      /* The function that implements the task. */
+//       "lwip",         /* The text name assigned to the task - for debug
+//                               only as it is not used by the kernel. */
+//       stackSizeWords, /* The size of the stack to allocate to the task. */
+//       NULL,           /* The parameter passed to the task - not used in this
+//                                     simple case. */
+//       4,              /* The priority assigned to the task. */
+//       xStack, &xTaskBuffer);
+// }
\ No newline at end of file
diff --git a/romeo_design_from_website.bmp b/romeo_design_from_website.bmp
new file mode 100644
index 0000000..b02ad8c
Binary files /dev/null and b/romeo_design_from_website.bmp differ