From 8fa5cddc2369e146647f6736e8047a76bd7c2546 Mon Sep 17 00:00:00 2001
From: Ulrich Mohr <mohr@irs.uni-stuttgart.de>
Date: Mon, 9 Sep 2024 17:37:41 +0200
Subject: [PATCH] cleanup

---
 bsp_z7/hardware/uart.c            |  5 -----
 bsp_z7/lwip/netif/xemacpsif_dma.c |  3 ---
 bsp_z7/main.c                     |  4 ++--
 bsp_z7/newlib/write.c             |  2 +-
 bsp_z7/testEth.c                  |  4 ++--
 mission/mission.c                 | 18 +++++++++++++++---
 6 files changed, 20 insertions(+), 16 deletions(-)

diff --git a/bsp_z7/hardware/uart.c b/bsp_z7/hardware/uart.c
index 49ff7ab..de9107c 100644
--- a/bsp_z7/hardware/uart.c
+++ b/bsp_z7/hardware/uart.c
@@ -54,7 +54,6 @@ void uart0_handle_interrupt(void *) {
 }
 
 void uart1_handle_interrupt(void *) {
-  outbyte('R');
   u32 IsrStatus;
 
   /*
@@ -73,8 +72,6 @@ void uart1_handle_interrupt(void *) {
   
   while (XUartPs_IsReceiveData(XPS_UART1_BASEADDR)) {
     RecievedByte = XUartPs_ReadReg(XPS_UART1_BASEADDR, XUARTPS_FIFO_OFFSET);
-    outbyte(RecievedByte);
-    outbyte(XUartPs_ReadReg(XPS_UART1_BASEADDR, XUARTPS_ISR_OFFSET));
     xQueueSendToBackFromISR(uart1_receive_queue, &RecievedByte,
                             &xHigherPriorityTaskWoken);
   }
@@ -83,8 +80,6 @@ void uart1_handle_interrupt(void *) {
   /* Clear the interrupt status. */
   XUartPs_WriteReg(XPS_UART1_BASEADDR, XUARTPS_ISR_OFFSET, IsrStatus);
 
-  outbyte('X');
-  outbyte('\n');
   /* directly yield if sending to the queue woke something in ourselves */
   portYIELD_FROM_ISR(xHigherPriorityTaskWoken);
 }
diff --git a/bsp_z7/lwip/netif/xemacpsif_dma.c b/bsp_z7/lwip/netif/xemacpsif_dma.c
index adededb..357a001 100644
--- a/bsp_z7/lwip/netif/xemacpsif_dma.c
+++ b/bsp_z7/lwip/netif/xemacpsif_dma.c
@@ -498,8 +498,6 @@ void setup_rx_bds(xemacpsif_s *xemacpsif, XEmacPs_BdRing *rxring)
 
 void emacps_recv_handler(void *arg)
 {
-	outbyte('D');
-
 	struct pbuf *p;
 	XEmacPs_Bd *rxbdset, *curbdptr;
 	struct xemac_s *xemac;
@@ -587,7 +585,6 @@ void emacps_recv_handler(void *arg)
 	sys_sem_signal(&xemac->sem_rx_data_available);
 	xInsideISR--;
 #endif
-	outbyte('M');
 	return;
 }
 
diff --git a/bsp_z7/main.c b/bsp_z7/main.c
index b667c5b..67cc701 100644
--- a/bsp_z7/main.c
+++ b/bsp_z7/main.c
@@ -65,9 +65,9 @@ int main(void) {
 
   // printf("Booting Software\n");
 
-  testEth();
+  // testEth();
 
-  //mission();
+  mission();
 }
 
 static void prvSetupHardware(void) {
diff --git a/bsp_z7/newlib/write.c b/bsp_z7/newlib/write.c
index 7ded118..ef1e502 100644
--- a/bsp_z7/newlib/write.c
+++ b/bsp_z7/newlib/write.c
@@ -22,7 +22,7 @@ int _write(int fd, const char *ptr, int len) {
     return -1; // TODO error
   }
   // we only support a single debug UART, so
-  // stdout and stderr are the same and go to the xiling stdout UART
+  // stdout and stderr are the same and go to the xilinx stdout UART
   // We output directely to avoid loops and allow debugging (not via a write)
   if (fd < 3) {
     int todo;
diff --git a/bsp_z7/testEth.c b/bsp_z7/testEth.c
index 40e8de6..0242d29 100644
--- a/bsp_z7/testEth.c
+++ b/bsp_z7/testEth.c
@@ -94,7 +94,7 @@ void udp_echo_thread(void *_) {
       uint16_t port = ntohs(peer_addr.sin_port);
       switch (port) {
       case 8100:
-        xil_printf("udp rec 8100 len: %i\n", ret);
+        // xil_printf("udp rec 8100 len: %i\n", ret);
         write(uart0_fd, rec_buffer, ret);
         break;
       case 8101:
@@ -119,7 +119,7 @@ void udp_echo_thread(void *_) {
                   sizeof(peer_addr));
     } else if (readable == uart0_receive_queue) {
       ret = read(uart0_fd, rec_buffer, sizeof(rec_buffer));
-      xil_printf("uart got %i\n", ret);
+      // xil_printf("uart got %i\n", ret);
 
       // Do not send empty packets
       if (ret <= 0) {
diff --git a/mission/mission.c b/mission/mission.c
index a4843f2..8c1e065 100644
--- a/mission/mission.c
+++ b/mission/mission.c
@@ -14,13 +14,25 @@ void rust_main();
 
 void test_hardware() {
   int fd0 = hw_device_open("uart0", 5);
-  write(fd0, "uart0\n", 6);
+  write(fd0, "UART0\n", 6);
   int fd1 = hw_device_open("uart1", 5);
   write(fd1, "uart1\n", 6);
 
-  vTaskDelay(1 / portTICK_PERIOD_MS);
+  
+
+  uint8_t buffer[255];
+
+
+  // for (int i = 0; i< sizeof(buffer); i++) {
+  //   buffer[i] = i;
+  // }
+
+  // write(fd0, buffer, sizeof(buffer));
+
+  vTaskDelay(10 / portTICK_PERIOD_MS);
+
+  write(1, "got:\n", 5);
 
-  uint8_t buffer[100];
   int read_bytes = read(fd0, buffer, sizeof(buffer));
   write(1, buffer, read_bytes);
   read_bytes = read(fd1, buffer, sizeof(buffer));