From fb4b12c8f908caf4e67892d57f2322eb1a23417d Mon Sep 17 00:00:00 2001 From: Ulrich Mohr Date: Mon, 14 Oct 2024 13:36:25 +0200 Subject: [PATCH] xilinx ps7_cortexa9 code Version xilinx_v2024.1 --- bsp_z7/ps7_cortexa9_0/README.md | 11 + bsp_z7/ps7_cortexa9_0/include/diskio.h | 60 +- bsp_z7/ps7_cortexa9_0/include/ff.h | 4 +- bsp_z7/ps7_cortexa9_0/include/ffconf.h | 15 +- .../ps7_cortexa9_0/include/pm_api_version.h | 268 ++ bsp_z7/ps7_cortexa9_0/include/print.c | 13 +- bsp_z7/ps7_cortexa9_0/include/sleep.h | 11 +- bsp_z7/ps7_cortexa9_0/include/xadcps.h | 13 +- bsp_z7/ps7_cortexa9_0/include/xadcps_hw.h | 3 +- bsp_z7/ps7_cortexa9_0/include/xcortexa9.h | 18 + .../ps7_cortexa9_0/include/xcortexa9_config.h | 18 + bsp_z7/ps7_cortexa9_0/include/xcpu_cortexa9.h | 3 +- bsp_z7/ps7_cortexa9_0/include/xdebug.h | 6 +- bsp_z7/ps7_cortexa9_0/include/xdevcfg.h | 48 +- bsp_z7/ps7_cortexa9_0/include/xdevcfg_hw.h | 28 +- bsp_z7/ps7_cortexa9_0/include/xdmaps.h | 56 +- bsp_z7/ps7_cortexa9_0/include/xdmaps_hw.h | 9 +- bsp_z7/ps7_cortexa9_0/include/xemacps.h | 101 +- bsp_z7/ps7_cortexa9_0/include/xemacps_bd.h | 10 +- .../ps7_cortexa9_0/include/xemacps_bdring.h | 5 +- bsp_z7/ps7_cortexa9_0/include/xemacps_hw.h | 2 +- bsp_z7/ps7_cortexa9_0/include/xgpiops.h | 33 +- bsp_z7/ps7_cortexa9_0/include/xgpiops_hw.h | 2 +- bsp_z7/ps7_cortexa9_0/include/xil_cache.h | 4 +- .../include/xil_cryptoalginfo.h | 50 + bsp_z7/ps7_cortexa9_0/include/xil_exception.h | 10 +- bsp_z7/ps7_cortexa9_0/include/xil_io.h | 133 +- bsp_z7/ps7_cortexa9_0/include/xil_mem.h | 8 +- .../include/xil_misc_psreset_api.h | 8 +- bsp_z7/ps7_cortexa9_0/include/xil_printf.c | 601 +-- bsp_z7/ps7_cortexa9_0/include/xil_printf.h | 16 +- .../ps7_cortexa9_0/include/xil_sleepcommon.c | 6 + .../ps7_cortexa9_0/include/xil_sleeptimer.h | 11 +- bsp_z7/ps7_cortexa9_0/include/xil_spinlock.h | 13 +- bsp_z7/ps7_cortexa9_0/include/xil_testio.c | 94 +- bsp_z7/ps7_cortexa9_0/include/xil_testmem.c | 224 +- bsp_z7/ps7_cortexa9_0/include/xil_testmem.h | 4 + bsp_z7/ps7_cortexa9_0/include/xil_types.h | 12 +- bsp_z7/ps7_cortexa9_0/include/xil_util.c | 287 +- bsp_z7/ps7_cortexa9_0/include/xil_util.h | 174 +- bsp_z7/ps7_cortexa9_0/include/xilffs.h | 67 + bsp_z7/ps7_cortexa9_0/include/xparameters.h | 25 +- .../ps7_cortexa9_0/include/xplatform_info.c | 121 +- .../ps7_cortexa9_0/include/xplatform_info.h | 41 +- bsp_z7/ps7_cortexa9_0/include/xpm_init.h | 46 + .../ps7_cortexa9_0/include/xpseudo_asm_gcc.h | 188 +- bsp_z7/ps7_cortexa9_0/include/xqspips.h | 59 +- bsp_z7/ps7_cortexa9_0/include/xqspips_hw.h | 25 +- bsp_z7/ps7_cortexa9_0/include/xreg_cortexa9.h | 7 +- bsp_z7/ps7_cortexa9_0/include/xscugic.h | 239 +- bsp_z7/ps7_cortexa9_0/include/xscugic_hw.h | 134 +- bsp_z7/ps7_cortexa9_0/include/xscutimer.h | 62 +- bsp_z7/ps7_cortexa9_0/include/xscutimer_hw.h | 3 +- bsp_z7/ps7_cortexa9_0/include/xscuwdt.h | 49 +- bsp_z7/ps7_cortexa9_0/include/xscuwdt_hw.h | 5 +- bsp_z7/ps7_cortexa9_0/include/xsdps.h | 111 +- bsp_z7/ps7_cortexa9_0/include/xsdps_core.h | 11 +- bsp_z7/ps7_cortexa9_0/include/xsdps_hw.h | 215 +- bsp_z7/ps7_cortexa9_0/include/xstatus.h | 1 + bsp_z7/ps7_cortexa9_0/include/xttcps.h | 20 +- bsp_z7/ps7_cortexa9_0/include/xuartps.h | 21 +- bsp_z7/ps7_cortexa9_0/include/xuartps_hw.h | 37 +- bsp_z7/ps7_cortexa9_0/include/xusbps.h | 223 +- .../ps7_cortexa9_0/include/xusbps_endpoint.h | 95 +- bsp_z7/ps7_cortexa9_0/include/xusbps_hw.h | 91 +- .../libsrc/cpu_cortexa9/src/xcpu_cortexa9.h | 3 +- .../libsrc/devcfg/src/xdevcfg.c | 123 +- .../libsrc/devcfg/src/xdevcfg.h | 48 +- .../libsrc/devcfg/src/xdevcfg_g.c | 5 +- .../libsrc/devcfg/src/xdevcfg_hw.c | 10 +- .../libsrc/devcfg/src/xdevcfg_hw.h | 28 +- .../libsrc/devcfg/src/xdevcfg_intr.c | 32 +- .../libsrc/devcfg/src/xdevcfg_selftest.c | 5 +- .../libsrc/devcfg/src/xdevcfg_sinit.c | 27 +- .../ps7_cortexa9_0/libsrc/dmaps/src/xdmaps.c | 326 +- .../ps7_cortexa9_0/libsrc/dmaps/src/xdmaps.h | 56 +- .../libsrc/dmaps/src/xdmaps_g.c | 5 +- .../libsrc/dmaps/src/xdmaps_hw.c | 36 +- .../libsrc/dmaps/src/xdmaps_hw.h | 9 +- .../libsrc/dmaps/src/xdmaps_selftest.c | 11 +- .../libsrc/dmaps/src/xdmaps_sinit.c | 40 +- .../libsrc/emacps/src/xemacps.c | 14 +- .../libsrc/emacps/src/xemacps.h | 101 +- .../libsrc/emacps/src/xemacps_bd.h | 10 +- .../libsrc/emacps/src/xemacps_bdring.c | 16 +- .../libsrc/emacps/src/xemacps_bdring.h | 5 +- .../libsrc/emacps/src/xemacps_control.c | 5 +- .../libsrc/emacps/src/xemacps_g.c | 5 +- .../libsrc/emacps/src/xemacps_hw.c | 5 +- .../libsrc/emacps/src/xemacps_hw.h | 2 +- .../libsrc/emacps/src/xemacps_intr.c | 7 +- .../libsrc/emacps/src/xemacps_sinit.c | 28 +- .../libsrc/gpiops/src/xgpiops.c | 8 +- .../libsrc/gpiops/src/xgpiops.h | 33 +- .../libsrc/gpiops/src/xgpiops_g.c | 2 +- .../libsrc/gpiops/src/xgpiops_hw.c | 2 +- .../libsrc/gpiops/src/xgpiops_hw.h | 2 +- .../libsrc/gpiops/src/xgpiops_intr.c | 36 +- .../libsrc/gpiops/src/xgpiops_selftest.c | 4 +- .../libsrc/gpiops/src/xgpiops_sinit.c | 22 +- .../libsrc/qspips/src/xqspips.c | 417 +- .../libsrc/qspips/src/xqspips.h | 59 +- .../libsrc/qspips/src/xqspips_g.c | 3 +- .../libsrc/qspips/src/xqspips_hw.c | 37 +- .../libsrc/qspips/src/xqspips_hw.h | 25 +- .../libsrc/qspips/src/xqspips_options.c | 37 +- .../libsrc/qspips/src/xqspips_selftest.c | 9 +- .../libsrc/qspips/src/xqspips_sinit.c | 23 +- .../libsrc/scugic/src/xscugic.c | 726 +-- .../libsrc/scugic/src/xscugic.h | 239 +- .../libsrc/scugic/src/xscugic_g.c | 6 +- .../libsrc/scugic/src/xscugic_hw.c | 547 +-- .../libsrc/scugic/src/xscugic_hw.h | 134 +- .../libsrc/scugic/src/xscugic_intr.c | 25 +- .../libsrc/scugic/src/xscugic_selftest.c | 25 +- .../libsrc/scugic/src/xscugic_sinit.c | 83 +- .../libsrc/scutimer/src/xscutimer.c | 27 +- .../libsrc/scutimer/src/xscutimer.h | 62 +- .../libsrc/scutimer/src/xscutimer_g.c | 3 +- .../libsrc/scutimer/src/xscutimer_hw.h | 3 +- .../libsrc/scutimer/src/xscutimer_selftest.c | 16 +- .../libsrc/scutimer/src/xscutimer_sinit.c | 27 +- .../libsrc/scuwdt/src/xscuwdt.c | 23 +- .../libsrc/scuwdt/src/xscuwdt.h | 49 +- .../libsrc/scuwdt/src/xscuwdt_g.c | 5 +- .../libsrc/scuwdt/src/xscuwdt_hw.h | 5 +- .../libsrc/scuwdt/src/xscuwdt_selftest.c | 8 +- .../libsrc/scuwdt/src/xscuwdt_sinit.c | 28 +- bsp_z7/ps7_cortexa9_0/libsrc/sdps/src/xsdps.c | 128 +- bsp_z7/ps7_cortexa9_0/libsrc/sdps/src/xsdps.h | 111 +- .../libsrc/sdps/src/xsdps_card.c | 521 +-- .../libsrc/sdps/src/xsdps_core.h | 11 +- .../ps7_cortexa9_0/libsrc/sdps/src/xsdps_g.c | 7 +- .../libsrc/sdps/src/xsdps_host.c | 727 +-- .../ps7_cortexa9_0/libsrc/sdps/src/xsdps_hw.h | 215 +- .../libsrc/sdps/src/xsdps_options.c | 95 +- .../libsrc/sdps/src/xsdps_sinit.c | 34 +- .../libsrc/standalone/src/boot.S | 31 +- .../libsrc/standalone/src/outbyte.c | 4 +- .../libsrc/standalone/src/pm_api_version.h | 268 ++ .../libsrc/standalone/src/print.c | 13 +- .../libsrc/standalone/src/putnum.c | 11 +- .../libsrc/standalone/src/read.c | 8 +- .../libsrc/standalone/src/sleep.c | 9 +- .../libsrc/standalone/src/sleep.h | 11 +- .../libsrc/standalone/src/translation_table.S | 11 + .../libsrc/standalone/src/usleep.c | 4 +- .../libsrc/standalone/src/write.c | 8 +- .../libsrc/standalone/src/xcortexa9.h | 18 + .../libsrc/standalone/src/xcortexa9_config.h | 18 + .../libsrc/standalone/src/xdebug.h | 6 +- .../libsrc/standalone/src/xil-crt0.S | 4 +- .../libsrc/standalone/src/xil_cache.c | 100 +- .../libsrc/standalone/src/xil_cache.h | 4 +- .../libsrc/standalone/src/xil_cryptoalginfo.h | 50 + .../libsrc/standalone/src/xil_exception.c | 32 +- .../libsrc/standalone/src/xil_exception.h | 10 +- .../libsrc/standalone/src/xil_io.h | 133 +- .../libsrc/standalone/src/xil_mem.h | 8 +- .../standalone/src/xil_misc_psreset_api.h | 8 +- .../libsrc/standalone/src/xil_mmu.c | 22 +- .../libsrc/standalone/src/xil_printf.c | 601 +-- .../libsrc/standalone/src/xil_printf.h | 16 +- .../libsrc/standalone/src/xil_sleepcommon.c | 6 + .../libsrc/standalone/src/xil_sleeptimer.h | 11 +- .../libsrc/standalone/src/xil_spinlock.h | 13 +- .../libsrc/standalone/src/xil_testio.c | 94 +- .../libsrc/standalone/src/xil_testmem.c | 224 +- .../libsrc/standalone/src/xil_testmem.h | 4 + .../libsrc/standalone/src/xil_types.h | 12 +- .../libsrc/standalone/src/xil_util.c | 287 +- .../libsrc/standalone/src/xil_util.h | 174 +- .../libsrc/standalone/src/xplatform_info.c | 121 +- .../libsrc/standalone/src/xplatform_info.h | 41 +- .../libsrc/standalone/src/xpm_counter.c | 35 +- .../libsrc/standalone/src/xpm_init.c | 224 + .../libsrc/standalone/src/xpm_init.h | 46 + .../libsrc/standalone/src/xpseudo_asm_gcc.h | 188 +- .../libsrc/standalone/src/xreg_cortexa9.h | 7 +- .../libsrc/standalone/src/xstatus.h | 1 + .../ps7_cortexa9_0/libsrc/ttcps/src/xttcps.c | 234 +- .../ps7_cortexa9_0/libsrc/ttcps/src/xttcps.h | 20 +- .../libsrc/ttcps/src/xttcps_options.c | 85 +- .../libsrc/ttcps/src/xttcps_selftest.c | 11 +- .../libsrc/ttcps/src/xttcps_sinit.c | 26 +- .../libsrc/uartps/src/xuartps.c | 7 +- .../libsrc/uartps/src/xuartps.h | 21 +- .../libsrc/uartps/src/xuartps_hw.c | 38 +- .../libsrc/uartps/src/xuartps_hw.h | 37 +- .../libsrc/uartps/src/xuartps_sinit.c | 27 +- .../ps7_cortexa9_0/libsrc/usbps/src/xusbps.c | 52 +- .../ps7_cortexa9_0/libsrc/usbps/src/xusbps.h | 223 +- .../libsrc/usbps/src/xusbps_endpoint.c | 245 +- .../libsrc/usbps/src/xusbps_endpoint.h | 95 +- .../libsrc/usbps/src/xusbps_g.c | 11 +- .../libsrc/usbps/src/xusbps_hw.c | 36 +- .../libsrc/usbps/src/xusbps_hw.h | 91 +- .../libsrc/usbps/src/xusbps_intr.c | 84 +- .../libsrc/usbps/src/xusbps_sinit.c | 23 +- .../ps7_cortexa9_0/libsrc/xadcps/src/Makefile | 3 +- .../ps7_cortexa9_0/libsrc/xadcps/src/xadcps.c | 9 +- .../ps7_cortexa9_0/libsrc/xadcps/src/xadcps.h | 13 +- .../libsrc/xadcps/src/xadcps_g.c | 3 +- .../libsrc/xadcps/src/xadcps_hw.h | 3 +- .../libsrc/xadcps/src/xadcps_intr.c | 3 +- .../libsrc/xadcps/src/xadcps_selftest.c | 3 +- .../libsrc/xadcps/src/xadcps_sinit.c | 26 +- .../libsrc/xilffs/data/xilffs.mld | 6 +- .../libsrc/xilffs/data/xilffs.tcl | 6 +- .../xilffs/examples/xilffs_polled_example.c | 234 - .../ps7_cortexa9_0/libsrc/xilffs/src/diskio.c | 231 +- bsp_z7/ps7_cortexa9_0/libsrc/xilffs/src/ff.c | 4155 +++++++++++------ .../libsrc/xilffs/src/include/diskio.h | 60 +- .../libsrc/xilffs/src/include/ff.h | 4 +- .../libsrc/xilffs/src/include/ffconf.h | 15 +- .../libsrc/xilffs/src/include/xilffs.h | 67 + .../libsrc/xilffs/src/xilffs.cmake | 93 + .../libsrc/xilffs/src/xilffs_config.h.in | 30 + .../libsrc/xilrsa/data/xilrsa.mld | 3 +- 219 files changed, 11733 insertions(+), 7355 deletions(-) create mode 100644 bsp_z7/ps7_cortexa9_0/README.md create mode 100644 bsp_z7/ps7_cortexa9_0/include/pm_api_version.h create mode 100644 bsp_z7/ps7_cortexa9_0/include/xcortexa9.h create mode 100644 bsp_z7/ps7_cortexa9_0/include/xcortexa9_config.h create mode 100644 bsp_z7/ps7_cortexa9_0/include/xil_cryptoalginfo.h create mode 100644 bsp_z7/ps7_cortexa9_0/include/xilffs.h create mode 100644 bsp_z7/ps7_cortexa9_0/include/xpm_init.h create mode 100644 bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/pm_api_version.h create mode 100644 bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xcortexa9.h create mode 100644 bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xcortexa9_config.h create mode 100644 bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xil_cryptoalginfo.h create mode 100644 bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xpm_init.c create mode 100644 bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xpm_init.h delete mode 100644 bsp_z7/ps7_cortexa9_0/libsrc/xilffs/examples/xilffs_polled_example.c create mode 100644 bsp_z7/ps7_cortexa9_0/libsrc/xilffs/src/include/xilffs.h create mode 100644 bsp_z7/ps7_cortexa9_0/libsrc/xilffs/src/xilffs.cmake create mode 100644 bsp_z7/ps7_cortexa9_0/libsrc/xilffs/src/xilffs_config.h.in diff --git a/bsp_z7/ps7_cortexa9_0/README.md b/bsp_z7/ps7_cortexa9_0/README.md new file mode 100644 index 0000000..b5e7492 --- /dev/null +++ b/bsp_z7/ps7_cortexa9_0/README.md @@ -0,0 +1,11 @@ +This is based on the bsp of the zynq_fsbl in https://github.com/Xilinx/embeddedsw/tree/xilinx_v2024.1/lib/sw_apps/zynq_fsbl + +It is generated/collected by xilinx's build system when building the fsbl. + +Currently, version xilinx_v2024.1 is used. + +We use our own CMakeLists.txt located in the subfolders of `libsrc` to select which files to include in our bsp. + +Xilinx exports CMakeLists.txt files for some of their folders as well, which we remove to avoid confusion. + +Additionally, drivers from https://github.com/Xilinx/embeddedsw/tree/xilinx_v2024.1/XilinxProcessorIPLib/drivers are added as needed. \ No newline at end of file diff --git a/bsp_z7/ps7_cortexa9_0/include/diskio.h b/bsp_z7/ps7_cortexa9_0/include/diskio.h index 1c2b4a4..acfa0f0 100644 --- a/bsp_z7/ps7_cortexa9_0/include/diskio.h +++ b/bsp_z7/ps7_cortexa9_0/include/diskio.h @@ -9,8 +9,8 @@ extern "C" { #endif -#define USE_WRITE 1 /* 1: Enable disk_write function */ -#define USE_IOCTL 1 /* 1: Enable disk_ioctl function */ +#define USE_WRITE 1 /**< 1: Enable disk_write function */ +#define USE_IOCTL 1 /**< 1: Enable disk_ioctl function */ #include "ff.h" #include "xil_types.h" @@ -20,11 +20,11 @@ typedef BYTE DSTATUS; /* Results of Disk Functions */ typedef enum { - RES_OK = 0, /* 0: Successful */ - RES_ERROR, /* 1: R/W Error */ - RES_WRPRT, /* 2: Write Protected */ - RES_NOTRDY, /* 3: Not Ready */ - RES_PARERR /* 4: Invalid Parameter */ + RES_OK = 0, /**< 0: Successful */ + RES_ERROR, /**< 1: R/W Error */ + RES_WRPRT, /**< 2: Write Protected */ + RES_NOTRDY, /**< 3: Not Ready */ + RES_PARERR /**< 4: Invalid Parameter */ } DRESULT; @@ -41,40 +41,40 @@ DRESULT disk_ioctl (BYTE pdrv, BYTE cmd, void* buff); /* Disk Status Bits (DSTATUS) */ -#define STA_NOINIT 0x01U /* Drive not initialized */ -#define STA_NODISK 0x02U /* No medium in the drive */ -#define STA_PROTECT 0x04U /* Write protected */ +#define STA_NOINIT 0x01U /**< Drive not initialized */ +#define STA_NODISK 0x02U /**< No medium in the drive */ +#define STA_PROTECT 0x04U /**< Write protected */ /* Command code for disk_ioctrl fucntion */ /* Generic command (Used by FatFs) */ -#define CTRL_SYNC 0U /* Complete pending write process (needed at FF_FS_READONLY == 0) */ -#define GET_SECTOR_COUNT 1U /* Get media size (needed at FF_USE_MKFS == 1) */ -#define GET_SECTOR_SIZE 2U /* Get sector size (needed at FF_MAX_SS != FF_MIN_SS) */ -#define GET_BLOCK_SIZE 3U /* Get erase block size (needed at FF_USE_MKFS == 1) */ -#define CTRL_TRIM 4U /* Inform device that the data on the block of sectors is no longer used (needed at FF_USE_TRIM == 1) */ +#define CTRL_SYNC 0U /**< Complete pending write process (needed at FF_FS_READONLY == 0) */ +#define GET_SECTOR_COUNT 1U /**< Get media size (needed at FF_USE_MKFS == 1) */ +#define GET_SECTOR_SIZE 2U /**< Get sector size (needed at FF_MAX_SS != FF_MIN_SS) */ +#define GET_BLOCK_SIZE 3U /**< Get erase block size (needed at FF_USE_MKFS == 1) */ +#define CTRL_TRIM 4U /**< Inform device that the data on the block of sectors is no longer used (needed at FF_USE_TRIM == 1) */ /* Generic command (Not used by FatFs) */ -#define CTRL_POWER 5U /* Get/Set power status */ -#define CTRL_LOCK 6U /* Lock/Unlock media removal */ -#define CTRL_EJECT 7U /* Eject media */ -#define CTRL_FORMAT 8U /* Create physical format on the media */ +#define CTRL_POWER 5U /**< Get/Set power status */ +#define CTRL_LOCK 6U /**< Lock/Unlock media removal */ +#define CTRL_EJECT 7U /**< Eject media */ +#define CTRL_FORMAT 8U /**< Create physical format on the media */ /* MMC/SDC specific ioctl command */ -#define MMC_GET_TYPE 10U /* Get card type */ -#define MMC_GET_CSD 11U /* Get CSD */ -#define MMC_GET_CID 12U /* Get CID */ -#define MMC_GET_OCR 13U /* Get OCR */ -#define MMC_GET_SDSTAT 14U /* Get SD status */ -#define ISDIO_READ 55 /* Read data form SD iSDIO register */ -#define ISDIO_WRITE 56 /* Write data to SD iSDIO register */ -#define ISDIO_MRITE 57 /* Masked write data to SD iSDIO register */ +#define MMC_GET_TYPE 10U /**< Get card type */ +#define MMC_GET_CSD 11U /**< Get CSD */ +#define MMC_GET_CID 12U /**< Get CID */ +#define MMC_GET_OCR 13U /**< Get OCR */ +#define MMC_GET_SDSTAT 14U /**< Get SD status */ +#define ISDIO_READ 55 /**< Read data form SD iSDIO register */ +#define ISDIO_WRITE 56 /**< Write data to SD iSDIO register */ +#define ISDIO_MRITE 57 /**< Masked write data to SD iSDIO register */ /* ATA/CF specific ioctl command */ -#define ATA_GET_REV 20U /* Get F/W revision */ -#define ATA_GET_MODEL 21U /* Get model name */ -#define ATA_GET_SN 22U /* Get serial number */ +#define ATA_GET_REV 20U /**< Get F/W revision */ +#define ATA_GET_MODEL 21U /**< Get model name */ +#define ATA_GET_SN 22U /**< Get serial number */ #ifdef __cplusplus } diff --git a/bsp_z7/ps7_cortexa9_0/include/ff.h b/bsp_z7/ps7_cortexa9_0/include/ff.h index 6f522f9..0a0e086 100644 --- a/bsp_z7/ps7_cortexa9_0/include/ff.h +++ b/bsp_z7/ps7_cortexa9_0/include/ff.h @@ -26,8 +26,8 @@ extern "C" { #endif -#include "xil_types.h" #include "ffconf.h" /* FatFs configuration options */ +#include "xilffs.h" #if FF_DEFINED != FFCONF_DEF #error Wrong configuration file (ffconf.h). @@ -355,7 +355,7 @@ int f_puts (const TCHAR* str, FIL* cp); /* Put a string to the file */ int f_printf (FIL* fp, const TCHAR* str, ...); /* Put a formatted string to the file */ TCHAR* f_gets (TCHAR* buff, int len, FIL* fp); /* Get a string from the file */ -/* Some API fucntions are implemented as macro */ +/* Some API functions are implemented as macro */ #define f_eof(fp) ((int)((fp)->fptr == (fp)->obj.objsize)) #define f_error(fp) ((fp)->err) diff --git a/bsp_z7/ps7_cortexa9_0/include/ffconf.h b/bsp_z7/ps7_cortexa9_0/include/ffconf.h index 007d807..5a1bbe3 100644 --- a/bsp_z7/ps7_cortexa9_0/include/ffconf.h +++ b/bsp_z7/ps7_cortexa9_0/include/ffconf.h @@ -8,7 +8,11 @@ extern "C" { #endif +#ifdef SDT +#include "xilffs_config.h" +#else #include "xparameters.h" +#endif /*---------------------------------------------------------------------------/ / Function Configurations @@ -34,7 +38,7 @@ extern "C" { / 2: f_opendir(), f_readdir() and f_closedir() are removed in addition to 1. / 3: f_lseek() function is removed in addition to 2. */ - +#ifdef FILE_SYSTEM_USE_STRFUNC #if FILE_SYSTEM_USE_STRFUNC == 0 #define FF_USE_STRFUNC 0 /* 0:Disable */ #elif FILE_SYSTEM_USE_STRFUNC == 1 @@ -42,6 +46,9 @@ extern "C" { #elif FILE_SYSTEM_USE_STRFUNC == 2 #define FF_USE_STRFUNC 2 /* 2:Enable */ #endif +#else +#define FF_USE_STRFUNC 0 /* 0:Disable */ +#endif /* This option switches string functions, f_gets(), f_putc(), f_puts() and f_printf(). / / 0: Disable string functions. @@ -87,7 +94,6 @@ extern "C" { /* This option switches f_forward() function. (0:Disable or 1:Enable) */ -#define FF_USE_STRFUNC 0 #define FF_PRINT_LLI 1 #define FF_PRINT_FLOAT 1 #define FF_STRF_ENCODE 3 @@ -187,7 +193,7 @@ extern "C" { / the file names to read. The maximum possible length of the read file name depends / on character encoding. When LFN is not enabled, these options have no effect. */ - +#ifdef FILE_SYSTEM_SET_FS_RPATH #if FILE_SYSTEM_SET_FS_RPATH == 0 #define FF_FS_RPATH 0U #elif FILE_SYSTEM_SET_FS_RPATH == 1 @@ -195,6 +201,9 @@ extern "C" { #elif FILE_SYSTEM_SET_FS_RPATH == 2 #define FF_FS_RPATH 2U #endif +#else +#define FF_FS_RPATH 0U +#endif /* This option configures support for relative path. / / 0: Disable relative path and remove related functions. diff --git a/bsp_z7/ps7_cortexa9_0/include/pm_api_version.h b/bsp_z7/ps7_cortexa9_0/include/pm_api_version.h new file mode 100644 index 0000000..5498048 --- /dev/null +++ b/bsp_z7/ps7_cortexa9_0/include/pm_api_version.h @@ -0,0 +1,268 @@ +/****************************************************************************** +* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** + * @file pm_api_version.h + * + * @addtogroup xpm_versal_apis XilPM APIs + *****************************************************************************/ + + +#ifndef PM_API_VERSION_H_ +#define PM_API_VERSION_H_ + +/*****************************************************************************/ +/** + * @section EEMI_API_DETAIL XilPM EEMI API Version Detail + * + * This section provides details of EEMI API version and it's history for PM APIs of XilPM library. + * + * | NAME | ID | Platform | Version| Description | + * |----------------------------|-------|---------------|:------:|---------------------------------------------------------------------------| + * | PM_GET_API_VERSION | 0x1 | Both | 1 | The API is used to request the version number of the API | + * | PM_SET_CONFIGURATION | 0x2 | ZynqMP | 1 | The API is used to configure the power management framework | + * | ^ | ^ | ^ | ^ | Note: Deprecated in Versal but supported in ZynqMP | + * | PM_GET_NODE_STATUS | 0x3 | Both | 1 | The API is used to obtain information about current status of a device | + * | PM_GET_OP_CHARACTERISTIC | 0x4 | Both | 2 | V1 - The API is used to get operating characteristics of a device | + * | ^ | ^ | ^ | ^ | V2 - Added support of bitmask functionality, user can check the supported\n "type" first before performing the actual functionality | + * | PM_REGISTER_NOTIFIER | 0x5 | Both | 2 | V1 - The API is used to register a subsystem to be notified about the\n device event | + * | ^ | ^ | ^ | ^ | V2 - Added support of event management functionality | + * | ^ | ^ | ^ | ^ | Note: V2 is supported in Versal but ZynqMP supports only V1 | + * | PM_REQUEST_SUSPEND | 0x6 | Both | 1 | The API is used to send suspend request to another subsystem | + * | PM_SELF_SUSPEND | 0x7 | Both | 3 | V1 - The API is used to suspend a child subsystem | + * | ^ | ^ | ^ | ^ | V2 - Added support of cpu idle functionality during force powerdown | + * | ^ | ^ | ^ | ^ | V3 - Added support of CPU off state | + * | ^ | ^ | ^ | ^ | Note: V3 is supported in Versal and Versal NET but ZynqMP supports only V1| + * | PM_FORCE_POWERDOWN | 0x8 | Both | 2 | V1 - The API is used to Powerdown other processor or node | + * | ^ | ^ | ^ | ^ | V2 - Added support of cpu idle functionality during force powerdown | + * | ^ | ^ | ^ | ^ | Note: V2 is supported in Versal but ZynqMP supports only V1 | + * | PM_ABORT_SUSPEND | 0x9 | Both | 1 | The API is used by a subsystem to abort suspend of a child subsystem | + * | PM_REQUEST_WAKEUP | 0xA | Both | 1 | The API is used to start-up and wake-up a child subsystem | + * | PM_SET_WAKEUP_SOURCE | 0xB | Both | 1 | The API is used to set wakeup source | + * | PM_SYSTEM_SHUTDOWN | 0xC | Both | 1 | The API is used to shutdown or restart the system | + * | PM_REQUEST_NODE | 0xD | Both | 2 | V1 - The API is used to request the usage of a device | + * | ^ | ^ | ^ | ^ | V2 - Added support of security policy handling during request device | + * | ^ | ^ | ^ | ^ | Note: V2 is supported in Versal but ZynqMP supports only V1 | + * | PM_RELEASE_NODE | 0xE | Both | 2 | V1 - The API is used to release the usage of a device | + * | ^ | ^ | ^ | ^ | V2 - Added support of security policy handling during request device | + * | ^ | ^ | ^ | ^ | Note: V2 is supported in Versal but ZynqMP supports only V1 | + * | PM_SET_REQUIREMENT | 0xF | Both | 1 | The API is used to announce a change in requirement for a specific slave\n node which is currently in use | + * | PM_SET_MAX_LATENCY | 0x10 | Both | 1 | The API is used to set maximum allowed latency for the device | + * | PM_RESET_ASSERT | 0x11 | Both | 1 | The API is used to reset or de-reset a device | + * | PM_RESET_GET_STATUS | 0x12 | Both | 1 | The API is used to read the device reset state | + * | PM_MMIO_WRITE | 0x13 | ZynqMP | 1 | The API is used to write a value into a register | + * | ^ | ^ | ^ | ^ | Note: Deprecated in Versal but supported in ZynqMP | + * | PM_MMIO_READ | 0x14 | ZynqMP | 1 | The API is used to read a value from a register | + * | ^ | ^ | ^ | ^ | Note: Deprecated in Versal but supported in ZynqMP | + * | PM_INIT_FINALIZE | 0x15 | Both | 1 | The API is used to initialize subsystem and release unused devices | + * | PM_GET_CHIPID | 0x18 | Both | 1 | The API is used to request the version and ID code of a chip | + * | PM_PINCTRL_REQUEST | 0x1C | Both | 1 | The API is used to request the pin | + * | PM_PINCTRL_RELEASE | 0x1D | Both | 1 | The API is used to release the pin | + * | PM_PINCTRL_GET_FUNCTION | 0x1E | Both | 1 | The API is used to read the pin function | + * | PM_PINCTRL_SET_FUNCTION | 0x1F | Both | 1 | The API is used to set the pin function | + * | PM_PINCTRL_CONFIG_PARAM_GET| 0x20 | Both | 1 | The API is used to read the pin parameter value | + * | PM_PINCTRL_CONFIG_PARAM_SET| 0x21 | Both | 2 | V1 - The API is used to set the pin parameter value | + * | ^ | ^ | ^ | ^ | V2 - Added support of MIO tri-state controlling functionality | + * | ^ | ^ | ^ | ^ | Note: V2 is supported in ZynqMP but Versal supports only V1 | + * | PM_IOCTL | 0x22 | Both | 3 | V1 - The API is used to perform driver-like IOCTL functions on shared\n system devices | + * | ^ | ^ | ^ | ^ | V2 - Added support of bitmask functionality, user can check the supported\n ID first before performing the actual functionality | + * | ^ | ^ | ^ | ^ | V3 - Add support of zeroization of AIE data and program memory separately | + * | ^ | ^ | ^ | ^ | Note: V3 is supported in Versal but ZynqMP supports only V2 | + * | PM_QUERY_DATA | 0x23 | Both | 2 | V1 - The API is used to query information about the platform resources | + * | ^ | ^ | ^ | ^ | V2 - Added support of bitmask functionality, user can check the supported\n ID first before performing the actual functionality | + * | PM_CLOCK_ENABLE | 0x24 | Both | 1 | The API is used to enable the clock | + * | PM_CLOCK_DISABLE | 0x25 | Both | 1 | The API is used to disable the clock | + * | PM_CLOCK_GETSTATE | 0x26 | Both | 1 | The API is used to read the clock state | + * | PM_CLOCK_SETDIVIDER | 0x27 | Both | 1 | The API is used to set the divider value of the clock | + * | PM_CLOCK_GETDIVIDER | 0x28 | Both | 1 | The API is used to read the clock divider | + * | PM_CLOCK_SETPARENT | 0x2B | Both | 1 | The API is used to set the parent of the clock | + * | PM_CLOCK_GETPARENT | 0x2C | Both | 1 | The API is used to read the clock parent | + * | PM_PLL_SET_PARAM | 0x30 | Both | 1 | The API is used to set the parameter of PLL clock | + * | PM_PLL_GET_PARAM | 0x31 | Both | 1 | The API is used to read the parameter of PLL clock | + * | PM_PLL_SET_MODE | 0x32 | Both | 1 | The API is used to set the mode of PLL clock | + * | PM_PLL_GET_MODE | 0x33 | Both | 1 | The API is used to read the mode of PLL clock | + * | PM_REGISTER_ACCESS | 0x34 | ZynqMP | 1 | The API is used for register read/write access data | + * | ^ | ^ | ^ | ^ | Note: Deprecated in Versal but supported in ZynqMP | + * | PM_EFUSE_ACCESS | 0x35 | ZynqMP | 1 | The API is used to provide access to efuse memory | + * | ^ | ^ | ^ | ^ | Note: Deprecated in Versal but supported in ZynqMP | + * | PM_FEATURE_CHECK | 0x3F | Both | 2 | V1 - The API is used to return supported version of the given API | + * | ^ | ^ | ^ | ^ | V2 - Added support of bitmask payload functionality | + * + *****************************************************************************/ + +/*****************************************************************************/ +/** + * @section IOCTL_ID_DETAIL XilPM IOCTL IDs Detail + * + * This section provides the details of the IOCTL IDs which are supported across the different platforms and their brief descriptions. + * + * | Name | ID | Platform | Description | + * |------------------------------------|-------|---------------|---------------------------------------| + * | IOCTL_GET_RPU_OPER_MODE | 0 | Both | Get RPU mode | + * | IOCTL_SET_RPU_OPER_MODE | 1 | Both | Set RPU mode | + * | IOCTL_RPU_BOOT_ADDR_CONFIG | 2 | Both | RPU boot address config | + * | IOCTL_TCM_COMB_CONFIG | 3 | Both | TCM config | + * | IOCTL_SET_TAPDELAY_BYPASS | 4 | Both | TAP delay bypass | + * | IOCTL_SD_DLL_RESET | 6 | Both | SD DLL reset | + * | IOCTL_SET_SD_TAPDELAY | 7 | Both | SD TAP delay | + * | IOCTL_SET_PLL_FRAC_MODE | 8 | Both | Set PLL frac mode | + * | IOCTL_GET_PLL_FRAC_MODE | 9 | Both | Get PLL frac mode | + * | IOCTL_SET_PLL_FRAC_DATA | 10 | Both | Set PLL frac data | + * | IOCTL_GET_PLL_FRAC_DATA | 11 | Both | Get PLL frac data | + * | IOCTL_WRITE_GGS | 12 | Both | Write GGS | + * | IOCTL_READ_GGS | 13 | Both | Read GGS | + * | IOCTL_WRITE_PGGS | 14 | Both | Write PGGS | + * | IOCTL_READ_PGGS | 15 | Both | Read PGGS | + * | IOCTL_ULPI_RESET | 16 | ZynqMP | ULPI reset | + * | IOCTL_SET_BOOT_HEALTH_STATUS | 17 | Both | Set boot status | + * | IOCTL_AFI | 18 | ZynqMP | AFI | + * | IOCTL_OSPI_MUX_SELECT | 21 | Versal | OSPI mux select | + * | IOCTL_USB_SET_STATE | 22 | Versal | USB set state | + * | IOCTL_GET_LAST_RESET_REASON | 23 | Versal | Get last reset reason | + * | IOCTL_AIE_ISR_CLEAR | 24 | Versal | AIE ISR clear | + * | IOCTL_REGISTER_SGI | 25 | None | Register SGI to ATF | + * | IOCTL_SET_FEATURE_CONFIG | 26 | ZynqMP | Set runtime feature config | + * | IOCTL_GET_FEATURE_CONFIG | 27 | ZynqMP | Get runtime feature config | + * | IOCTL_READ_REG | 28 | Versal | Read a 32-bit register | + * | IOCTL_MASK_WRITE_REG | 29 | Versal | RMW a 32-bit register | + * | IOCTL_SET_SD_CONFIG | 30 | ZynqMP | Set SD config register value | + * | IOCTL_SET_GEM_CONFIG | 31 | ZynqMP | Set GEM config register value | + * | IOCTL_SET_USB_CONFIG | 32 | ZynqMP | Set USB config register value | + * | IOCTL_AIE_OPS | 33 | Versal | AIE1/AIEML Run Time Operations | + * | IOCTL_GET_QOS | 34 | Versal | Get Device QoS value | + * | IOCTL_GET_APU_OPER_MODE | 35 | Versal | Get APU operation mode | + * | IOCTL_SET_APU_OPER_MODE | 36 | Versal | Set APU operation mode | + * | IOCTL_PREPARE_DDR_SHUTDOWN | 37 | Versal | Prepare DDR for shut down | + * | IOCTL_GET_SSIT_TEMP | 38 | Versal | Get secondary SLR min/max temperature | + * + *****************************************************************************/ + +/*****************************************************************************/ +/** + * @section QUERY_ID_DETAIL XilPM QUERY IDs Detail + * + * This section provides the details of the QUERY IDs which are supported across the different platforms and their brief descriptions. + * + * | Name | ID | Platform | Description | + * |--------------------------------------------|-------|---------------|---------------------------------------| + * | XPM_QID_INVALID | 0 | Both | Invalid Query ID | + * | XPM_QID_CLOCK_GET_NAME | 1 | Both | Get clock name | + * | XPM_QID_CLOCK_GET_TOPOLOGY | 2 | Both | Get clock topology | + * | XPM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS | 3 | Both | Get clock fixedfactor parameter | + * | XPM_QID_CLOCK_GET_MUXSOURCES | 4 | Both | Get clock mux sources | + * | XPM_QID_CLOCK_GET_ATTRIBUTES | 5 | Both | Get clock attributes | + * | XPM_QID_PINCTRL_GET_NUM_PINS | 6 | Both | Get total pins | + * | XPM_QID_PINCTRL_GET_NUM_FUNCTIONS | 7 | Both | Get total pin functions | + * | XPM_QID_PINCTRL_GET_NUM_FUNCTION_GROUPS | 8 | Both | Get total pin function groups | + * | XPM_QID_PINCTRL_GET_FUNCTION_NAME | 9 | Both | Get pin function name | + * | XPM_QID_PINCTRL_GET_FUNCTION_GROUPS | 10 | Both | Get pin function groups | + * | XPM_QID_PINCTRL_GET_PIN_GROUPS | 11 | Both | Get pin groups | + * | XPM_QID_CLOCK_GET_NUM_CLOCKS | 12 | Both | Get number of clocks | + * | XPM_QID_CLOCK_GET_MAX_DIVISOR | 13 | Both | Get max clock divisor | + * | XPM_QID_PLD_GET_PARENT | 14 | Versal | Get PLD parent | + * | XPM_QID_PINCTRL_GET_ATTRIBUTES | 15 | Versal | Get pin attributes | + * + *****************************************************************************/ + + +/*****************************************************************************/ +/** + * @section GET_OP_CHAR_DETAIL XilPM GET_OP_CHAR IDs Detail + * + * This section provides the details of the GET_OP_CHAR IDs which are supported across the different platforms and their brief descriptions. + * + * | Name | ID | Platform | Description | + * |------------------------------------|-------|---------------|-----------------------------------------------| + * | PM_OPCHAR_TYPE_POWER | 1 | ZynqMP | Operating characteristic ID power | + * | PM_OPCHAR_TYPE_TEMP | 2 | Versal | Operating characteristic ID temperature | + * | PM_OPCHAR_TYPE_LATENCY | 3 | Both | Operating characteristic ID latency | + * + *****************************************************************************/ + + +/** + * PM API IDs + */ +typedef enum { + PM_API_MIN, /**< 0x0 */ + PM_GET_API_VERSION, /**< 0x1 */ + PM_SET_CONFIGURATION, /**< 0x2 */ + PM_GET_NODE_STATUS, /**< 0x3 */ + PM_GET_OP_CHARACTERISTIC, /**< 0x4 */ + PM_REGISTER_NOTIFIER, /**< 0x5 */ + PM_REQUEST_SUSPEND, /**< 0x6 */ + PM_SELF_SUSPEND, /**< 0x7 */ + PM_FORCE_POWERDOWN, /**< 0x8 */ + PM_ABORT_SUSPEND, /**< 0x9 */ + PM_REQUEST_WAKEUP, /**< 0xA */ + PM_SET_WAKEUP_SOURCE, /**< 0xB */ + PM_SYSTEM_SHUTDOWN, /**< 0xC */ + PM_REQUEST_NODE, /**< 0xD */ + PM_RELEASE_NODE, /**< 0xE */ + PM_SET_REQUIREMENT, /**< 0xF */ + PM_SET_MAX_LATENCY, /**< 0x10 */ + PM_RESET_ASSERT, /**< 0x11 */ + PM_RESET_GET_STATUS, /**< 0x12 */ + PM_MMIO_WRITE, /**< 0x13 */ + PM_MMIO_READ, /**< 0x14 */ + PM_INIT_FINALIZE, /**< 0x15 */ + PM_FPGA_LOAD, /**< 0x16 */ + PM_FPGA_GET_STATUS, /**< 0x17 */ + PM_GET_CHIPID, /**< 0x18 */ + PM_SECURE_RSA_AES, /**< 0x19 */ + PM_SECURE_SHA, /**< 0x1A */ + PM_SECURE_RSA, /**< 0x1B */ + PM_PINCTRL_REQUEST, /**< 0x1C */ + PM_PINCTRL_RELEASE, /**< 0x1D */ + PM_PINCTRL_GET_FUNCTION, /**< 0x1E */ + PM_PINCTRL_SET_FUNCTION, /**< 0x1F */ + PM_PINCTRL_CONFIG_PARAM_GET, /**< 0x20 */ + PM_PINCTRL_CONFIG_PARAM_SET, /**< 0x21 */ + PM_IOCTL, /**< 0x22 */ + PM_QUERY_DATA, /**< 0x23 */ + PM_CLOCK_ENABLE, /**< 0x24 */ + PM_CLOCK_DISABLE, /**< 0x25 */ + PM_CLOCK_GETSTATE, /**< 0x26 */ + PM_CLOCK_SETDIVIDER, /**< 0x27 */ + PM_CLOCK_GETDIVIDER, /**< 0x28 */ + PM_CLOCK_SETRATE, /**< 0x29 */ + /* PM_CLOCK_GETRATE API is deprecated */ + PM_RESERVE_ID, /**< 0x2A */ + PM_CLOCK_SETPARENT, /**< 0x2B */ + PM_CLOCK_GETPARENT, /**< 0x2C */ + PM_SECURE_IMAGE, /**< 0x2D */ + PM_FPGA_READ, /**< 0x2E */ + PM_SECURE_AES, /**< 0x2F */ + PM_PLL_SET_PARAMETER, /**< 0x30 */ + PM_PLL_GET_PARAMETER, /**< 0x31 */ + PM_PLL_SET_MODE, /**< 0x32 */ + PM_PLL_GET_MODE, /**< 0x33 */ + PM_REGISTER_ACCESS, /**< 0x34 */ + PM_EFUSE_ACCESS, /**< 0x35 */ + PM_ADD_SUBSYSTEM, /**< 0x36 */ + PM_DESTROY_SUBSYSTEM, /**< 0x37 */ + PM_DESCRIBE_NODES, /**< 0x38 */ + PM_ADD_NODE, /**< 0x39 */ + PM_ADD_NODE_PARENT, /**< 0x3A */ + PM_ADD_NODE_NAME, /**< 0x3B */ + PM_ADD_REQUIREMENT, /**< 0x3C */ + PM_SET_CURRENT_SUBSYSTEM, /**< 0x3D */ + PM_INIT_NODE, /**< 0x3E */ + PM_FEATURE_CHECK, /**< 0x3F */ + PM_ISO_CONTROL, /**< 0x40 */ + PM_ACTIVATE_SUBSYSTEM, /**< 0x41 */ + PM_SET_NODE_ACCESS, /**< 0x42 */ + PM_BISR, /**< 0x43 */ + PM_APPLY_TRIM, /**< 0x44 */ + PM_NOC_CLOCK_ENABLE, /**< 0x45 */ + PM_IF_NOC_CLOCK_ENABLE, /**< 0x46 */ + PM_FORCE_HOUSECLEAN, /**< 0x47 */ + PM_FPGA_GET_VERSION, /**< 0x48 */ + PM_FPGA_GET_FEATURE_LIST, /**< 0x49 */ + PM_API_MAX /**< 0x4A */ +} XPm_ApiId; + +#endif /* PM_API_VERSION_H_ */ diff --git a/bsp_z7/ps7_cortexa9_0/include/print.c b/bsp_z7/ps7_cortexa9_0/include/print.c index e8ac3d4..cb66494 100644 --- a/bsp_z7/ps7_cortexa9_0/include/print.c +++ b/bsp_z7/ps7_cortexa9_0/include/print.c @@ -12,19 +12,22 @@ * the new terms are clearly indicated on the first page of each file where * they apply. * - */ + *****************************************************************************/ +/***************************** Include Files *********************************/ -/* - * print -- do a raw print of a string - */ #include "xil_printf.h" +/*****************************************************************************/ +/** +* print -- do a raw print of a string +* +******************************************************************************/ void print(const char8 *ptr) { #if defined (__aarch64__) && (HYP_GUEST == 1) && (EL1_NONSECURE == 1) && defined (XEN_USE_PV_CONSOLE) XPVXenConsole_Write(ptr); #else -#ifdef STDOUT_BASEADDRESS +#if defined(STDOUT_BASEADDRESS) || defined(SDT) while (*ptr != (char8)0) { outbyte (*ptr); ptr++; diff --git a/bsp_z7/ps7_cortexa9_0/include/sleep.h b/bsp_z7/ps7_cortexa9_0/include/sleep.h index 3c9c788..c41750f 100644 --- a/bsp_z7/ps7_cortexa9_0/include/sleep.h +++ b/bsp_z7/ps7_cortexa9_0/include/sleep.h @@ -1,5 +1,6 @@ /****************************************************************************** -* Copyright (c) 2014 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (C) 2014 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -30,7 +31,8 @@ * 8.0 sk 03/17/22 Modify sleep_MB parameter type from unsigned int to * u32 and usleep_MB parameter type from unsigned long to * ULONG to fix misra_c_2012_rule_4_6 violation. -* +* 9.0 ml 03/03/23 Add description to fix doxygen warnings. +* 9.1 mus 10/24/23 Add support for RISC-V. * * ******************************************************************************/ @@ -87,6 +89,7 @@ extern "C" { (timeout>0) ? 0 : -1; \ } ) +/************************** Function Prototypes ******************************/ void usleep(ULONG useconds); void sleep(u32 seconds); void usleep_R5(ULONG useconds); @@ -97,6 +100,10 @@ int usleep_A53(unsigned long useconds); unsigned sleep_A53(unsigned int seconds); int usleep_A9(unsigned long useconds); unsigned sleep_A9(unsigned int seconds); +void sleep_riscv(u32 seconds); +void usleep_riscv(ULONG useconds); + +/*****************************************************************************/ #ifdef __cplusplus } diff --git a/bsp_z7/ps7_cortexa9_0/include/xadcps.h b/bsp_z7/ps7_cortexa9_0/include/xadcps.h index 980f394..f73ff96 100644 --- a/bsp_z7/ps7_cortexa9_0/include/xadcps.h +++ b/bsp_z7/ps7_cortexa9_0/include/xadcps.h @@ -1,5 +1,6 @@ /****************************************************************************** * Copyright (C) 2011 - 2020 Xilinx, Inc. All rights reserved. +* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -7,7 +8,7 @@ /** * * @file xadcps.h -* @addtogroup xadcps_v2_6 +* @addtogroup Overview * @{ * @details * @@ -157,6 +158,8 @@ * 2.6 aad 11/02/20 Fix MISRAC Mandatory and Advisory errors. * aad 12/17/20 Added missing function declarations and removed * functions with no definitions. +* 2.7 cog 07/24/23 Added support for SDT flow +* * * * @@ -300,7 +303,11 @@ extern "C" { * device. */ typedef struct { +#ifndef SDT u16 DeviceId; /**< Unique ID of device */ +#else + char *Name; +#endif u32 BaseAddress; /**< Device base address */ } XAdcPs_Config; @@ -472,7 +479,11 @@ typedef struct { /** * Functions in xadcps_sinit.c */ +#ifndef SDT XAdcPs_Config *XAdcPs_LookupConfig(u16 DeviceId); +#else +XAdcPs_Config *XAdcPs_LookupConfig(u32 BaseAddress); +#endif /** * Functions in xadcps.c diff --git a/bsp_z7/ps7_cortexa9_0/include/xadcps_hw.h b/bsp_z7/ps7_cortexa9_0/include/xadcps_hw.h index 51cc7c5..1477617 100644 --- a/bsp_z7/ps7_cortexa9_0/include/xadcps_hw.h +++ b/bsp_z7/ps7_cortexa9_0/include/xadcps_hw.h @@ -1,5 +1,6 @@ /****************************************************************************** * Copyright (C) 2011 - 2020 Xilinx, Inc. All rights reserved. +* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -7,7 +8,7 @@ /** * * @file xadcps_hw.h -* @addtogroup xadcps_v2_6 +* @addtogroup Overview * @{ * * This header file contains identifiers and basic driver functions (or diff --git a/bsp_z7/ps7_cortexa9_0/include/xcortexa9.h b/bsp_z7/ps7_cortexa9_0/include/xcortexa9.h new file mode 100644 index 0000000..65a9db0 --- /dev/null +++ b/bsp_z7/ps7_cortexa9_0/include/xcortexa9.h @@ -0,0 +1,18 @@ +/****************************************************************************** +* Copyright (c) 2021-2022 Xilinx, Inc. All rights reserved. +* Copyright (c) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ +#ifndef XIL_XCORTEXA9_H_ /* prevent circular inclusions */ +#define XIL_XCORTEXA9_H_ /* by using protection macros */ + +/***************************** Include Files ********************************/ + +#include "xil_types.h" + +/**************************** Type Definitions ******************************/ +typedef struct { + u32 CpuFreq; +} XCortexa9_Config; + +#endif /* XIL_XCORTEXA9_H_ */ diff --git a/bsp_z7/ps7_cortexa9_0/include/xcortexa9_config.h b/bsp_z7/ps7_cortexa9_0/include/xcortexa9_config.h new file mode 100644 index 0000000..1a774f1 --- /dev/null +++ b/bsp_z7/ps7_cortexa9_0/include/xcortexa9_config.h @@ -0,0 +1,18 @@ +/****************************************************************************** +* Copyright (c) 2021-2022 Xilinx, Inc. All rights reserved. +* Copyright (c) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ +#ifndef XIL_XCORTEXA9_CONFIG_H_ /* prevent circular inclusions */ +#define XIL_XCORTEXA9_CONFIG_H_ /* by using protection macros */ + +/***************************** Include Files ********************************/ + +#include "xcortexa9.h" + +/************************** Variable Definitions ****************************/ +extern XCortexa9_Config XCortexa9_ConfigTable; + +/***************** Macros (Inline Functions) Definitions ********************/ +#define XGet_CpuFreq() XCortexa9_ConfigTable.CpuFreq +#endif /* XIL_XCORTEXA9_CONFIG_H_ */ diff --git a/bsp_z7/ps7_cortexa9_0/include/xcpu_cortexa9.h b/bsp_z7/ps7_cortexa9_0/include/xcpu_cortexa9.h index 3c23a5f..f6b3728 100644 --- a/bsp_z7/ps7_cortexa9_0/include/xcpu_cortexa9.h +++ b/bsp_z7/ps7_cortexa9_0/include/xcpu_cortexa9.h @@ -1,5 +1,6 @@ /****************************************************************************** * Copyright (C) 2011 - 2021 Xilinx, Inc. All rights reserved. +* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -7,7 +8,7 @@ /** * * @file xcpu_cortexa9.h -* @addtogroup cpu_cortexa9_v2_11 +* @addtogroup cpu_cortexa9 Overview * @{ * @details * diff --git a/bsp_z7/ps7_cortexa9_0/include/xdebug.h b/bsp_z7/ps7_cortexa9_0/include/xdebug.h index 8e6b3ef..74bfdb0 100644 --- a/bsp_z7/ps7_cortexa9_0/include/xdebug.h +++ b/bsp_z7/ps7_cortexa9_0/include/xdebug.h @@ -1,6 +1,6 @@ /****************************************************************************** * Copyright (C) 2002 - 2021 Xilinx, Inc. All rights reserved. -* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved. +* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -61,13 +61,13 @@ int printf(const char *format, ...); #else /* defined(DEBUG) && !defined(NDEBUG) */ -#define xdbg_stmnt(x) +#define xdbg_stmnt(x) /**< Debug statement */ /* See VxWorks comments above */ #if defined(XENV_VXWORKS) && defined(_WRS_GNU_VAR_MACROS) #define xdbg_printf(type, args...) #else /* ANSI Syntax */ -#define xdbg_printf(...) +#define xdbg_printf(...) /**< Debug printf */ #endif #endif /* defined(DEBUG) && !defined(NDEBUG) */ diff --git a/bsp_z7/ps7_cortexa9_0/include/xdevcfg.h b/bsp_z7/ps7_cortexa9_0/include/xdevcfg.h index e567699..694e3b3 100644 --- a/bsp_z7/ps7_cortexa9_0/include/xdevcfg.h +++ b/bsp_z7/ps7_cortexa9_0/include/xdevcfg.h @@ -1,5 +1,6 @@ /****************************************************************************** -* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved. +* Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -7,7 +8,7 @@ /** * * @file xdevcfg.h -* @addtogroup devcfg_v3_7 +* @addtogroup devcfg Overview * @{ * @details * @@ -133,6 +134,7 @@ * 3.5 ms 04/18/17 Modified tcl file to add suffix U for all macros * definitions of devcfg in xparameters.h * ms 08/07/17 Fixed compilation warnings in xdevcfg_sinit.c +* 3.8 Nava 06/21/23 Added support for system device-tree flow. * * ******************************************************************************/ @@ -178,8 +180,18 @@ typedef void (*XDcfg_IntrHandler) (void *CallBackRef, u32 Status); * This typedef contains configuration information for the device. */ typedef struct { +#ifndef SDT u16 DeviceId; /**< Unique ID of device */ +#else + char *Name; +#endif u32 BaseAddr; /**< Base address of the device */ +#ifdef SDT + u32 IntrId; /** Bits[11:0] Interrupt-id Bits[15:12] + * trigger type and level flags */ + UINTPTR IntrParent; /** Bit[0] Interrupt parent type Bit[64/32:1] + * Parent base address */ +#endif } XDcfg_Config; /** @@ -210,7 +222,7 @@ typedef struct { *****************************************************************************/ #define XDcfg_Unlock(InstancePtr) \ XDcfg_WriteReg((InstancePtr)->Config.BaseAddr, \ - XDCFG_UNLOCK_OFFSET, XDCFG_UNLOCK_DATA) + XDCFG_UNLOCK_OFFSET, XDCFG_UNLOCK_DATA) @@ -230,8 +242,8 @@ typedef struct { #define XDcfg_GetPsVersion(InstancePtr) \ ((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, \ XDCFG_MCTRL_OFFSET)) & \ - XDCFG_MCTRL_PCAP_PS_VERSION_MASK) >> \ - XDCFG_MCTRL_PCAP_PS_VERSION_SHIFT + XDCFG_MCTRL_PCAP_PS_VERSION_MASK) >> \ + XDCFG_MCTRL_PCAP_PS_VERSION_SHIFT @@ -250,7 +262,7 @@ typedef struct { *****************************************************************************/ #define XDcfg_ReadMultiBootConfig(InstancePtr) \ XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, \ - XDCFG_MULTIBOOT_ADDR_OFFSET) + XDCFG_MULTIBOOT_ADDR_OFFSET) /****************************************************************************/ @@ -269,8 +281,8 @@ typedef struct { *****************************************************************************/ #define XDcfg_SelectIcapInterface(InstancePtr) \ XDcfg_WriteReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET, \ - ((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET)) \ - & ( ~XDCFG_CTRL_PCAP_PR_MASK))) + ((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET)) \ + & ( ~XDCFG_CTRL_PCAP_PR_MASK))) /****************************************************************************/ /** @@ -288,8 +300,8 @@ typedef struct { *****************************************************************************/ #define XDcfg_SelectPcapInterface(InstancePtr) \ XDcfg_WriteReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET, \ - ((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET)) \ - | XDCFG_CTRL_PCAP_PR_MASK)) + ((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET)) \ + | XDCFG_CTRL_PCAP_PR_MASK)) @@ -298,7 +310,11 @@ typedef struct { /* * Lookup configuration in xdevcfg_sinit.c. */ +#ifndef SDT XDcfg_Config *XDcfg_LookupConfig(u16 DeviceId); +#else +XDcfg_Config *XDcfg_LookupConfig(UINTPTR BaseAddress); +#endif /* * Selftest function in xdevcfg_selftest.c @@ -309,7 +325,7 @@ int XDcfg_SelfTest(XDcfg *InstancePtr); * Interface functions in xdevcfg.c */ int XDcfg_CfgInitialize(XDcfg *InstancePtr, - XDcfg_Config *ConfigPtr, u32 EffectiveAddress); + XDcfg_Config *ConfigPtr, u32 EffectiveAddress); void XDcfg_EnablePCAP(XDcfg *InstancePtr); @@ -344,12 +360,12 @@ u32 XDcfg_GetMiscControlRegister(XDcfg *InstancePtr); u32 XDcfg_IsDmaBusy(XDcfg *InstancePtr); void XDcfg_InitiateDma(XDcfg *InstancePtr, u32 SourcePtr, u32 DestPtr, - u32 SrcWordLength, u32 DestWordLength); + u32 SrcWordLength, u32 DestWordLength); u32 XDcfg_Transfer(XDcfg *InstancePtr, - void *SourcePtr, u32 SrcWordLength, - void *DestPtr, u32 DestWordLength, - u32 TransferType); + void *SourcePtr, u32 SrcWordLength, + void *DestPtr, u32 DestWordLength, + u32 TransferType); /* * Interrupt related function prototypes implemented in xdevcfg_intr.c @@ -367,7 +383,7 @@ void XDcfg_IntrClear(XDcfg *InstancePtr, u32 Mask); void XDcfg_InterruptHandler(XDcfg *InstancePtr); void XDcfg_SetHandler(XDcfg *InstancePtr, void *CallBackFunc, - void *CallBackRef); + void *CallBackRef); #ifdef __cplusplus } diff --git a/bsp_z7/ps7_cortexa9_0/include/xdevcfg_hw.h b/bsp_z7/ps7_cortexa9_0/include/xdevcfg_hw.h index 1b7d881..3db7835 100644 --- a/bsp_z7/ps7_cortexa9_0/include/xdevcfg_hw.h +++ b/bsp_z7/ps7_cortexa9_0/include/xdevcfg_hw.h @@ -1,5 +1,6 @@ /****************************************************************************** -* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved. +* Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -7,7 +8,7 @@ /** * * @file xdevcfg_hw.h -* @addtogroup devcfg_v3_7 +* @addtogroup devcfg Overview * @{ * * This file contains the hardware interface to the Device Config Interface. @@ -26,6 +27,7 @@ * version UG585 (v1.4) November 16, 2012. * 2.04a kpc 10/07/13 Added function prototype. * 3.00a kpc 25/02/14 Corrected the XDCFG_BASE_ADDRESS macro value. +* 3.8 Nava 06/21/23 Added support for system device-tree flow. * * ******************************************************************************/ @@ -210,14 +212,14 @@ extern "C" { * of Init Signal */ #define XDCFG_IXR_ERROR_FLAGS_MASK (XDCFG_IXR_AXI_WTO_MASK | \ - XDCFG_IXR_AXI_WERR_MASK | \ - XDCFG_IXR_AXI_RTO_MASK | \ - XDCFG_IXR_AXI_RERR_MASK | \ - XDCFG_IXR_RX_FIFO_OV_MASK | \ - XDCFG_IXR_DMA_CMD_ERR_MASK |\ - XDCFG_IXR_DMA_Q_OV_MASK | \ - XDCFG_IXR_P2D_LEN_ERR_MASK |\ - XDCFG_IXR_PCFG_HMAC_ERR_MASK) + XDCFG_IXR_AXI_WERR_MASK | \ + XDCFG_IXR_AXI_RTO_MASK | \ + XDCFG_IXR_AXI_RERR_MASK | \ + XDCFG_IXR_RX_FIFO_OV_MASK | \ + XDCFG_IXR_DMA_CMD_ERR_MASK |\ + XDCFG_IXR_DMA_Q_OV_MASK | \ + XDCFG_IXR_P2D_LEN_ERR_MASK |\ + XDCFG_IXR_PCFG_HMAC_ERR_MASK) #define XDCFG_IXR_ALL_MASK 0x00F7F8EF @@ -266,9 +268,9 @@ extern "C" { * Status */ #define XDCFG_STATUS_EFUSE_BBRAM_KEY_DISABLE_MASK 0x00000008 - /**< BBRAM key - * disable - */ +/**< BBRAM key + * disable + */ #define XDCFG_STATUS_EFUSE_SEC_EN_MASK 0x00000004 /**< Efuse Security * Enable Status */ diff --git a/bsp_z7/ps7_cortexa9_0/include/xdmaps.h b/bsp_z7/ps7_cortexa9_0/include/xdmaps.h index 179c840..4b98640 100644 --- a/bsp_z7/ps7_cortexa9_0/include/xdmaps.h +++ b/bsp_z7/ps7_cortexa9_0/include/xdmaps.h @@ -1,5 +1,6 @@ /****************************************************************************** -* Copyright (C) 2009 - 2021 Xilinx, Inc. All rights reserved. +* Copyright (C) 2009 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -7,7 +8,7 @@ /** * * @file xdmaps.h -* @addtogroup dmaps_v2_8 +* @addtogroup dmaps Overview * @{ * @details * @@ -60,6 +61,7 @@ * 2.4 adk 13/08/18 Fixed armcc compiler warnings in the driver CR-1008310. * 2.8 sk 05/18/21 Modify all inline functions declarations from extern inline * to static inline to avoid the linkage conflict for IAR compiler. +* 2.9 aj 11/07/23 Added support for system device tree * * *****************************************************************************/ @@ -88,8 +90,19 @@ extern "C" { * This typedef contains configuration information for the device. */ typedef struct { +#ifndef SDT u16 DeviceId; /**< Unique ID of device */ +#else + char *Name; +#endif u32 BaseAddress; /**< Base address of device (IPIF) */ + +#ifdef SDT + u32 IntrId[9]; /** Bits[11:0] Interrupt-id Bits[15:12] + * trigger type and level flags */ + UINTPTR IntrParent; /** Bit[0] Interrupt parent type Bit[64/32:1] + * Parent base address */ +#endif } XDmaPs_Config; @@ -169,15 +182,15 @@ typedef struct { * It's the done handler a user can set for a channel */ typedef void (*XDmaPsDoneHandler) (unsigned int Channel, - XDmaPs_Cmd *DmaCmd, - void *CallbackRef); + XDmaPs_Cmd *DmaCmd, + void *CallbackRef); /** * It's the fault handler a user can set for a channel */ typedef void (*XDmaPsFaultHandler) (unsigned int Channel, - XDmaPs_Cmd *DmaCmd, - void *CallbackRef); + XDmaPs_Cmd *DmaCmd, + void *CallbackRef); #define XDMAPS_MAX_CHAN_BUFS 2 #define XDMAPS_CHAN_BUF_LEN 128 @@ -236,18 +249,18 @@ typedef struct { * Functions implemented in xdmaps.c */ int XDmaPs_CfgInitialize(XDmaPs *InstPtr, - XDmaPs_Config *Config, - u32 EffectiveAddr); + XDmaPs_Config *Config, + u32 EffectiveAddr); int XDmaPs_Start(XDmaPs *InstPtr, unsigned int Channel, - XDmaPs_Cmd *Cmd, - int HoldDmaProg); + XDmaPs_Cmd *Cmd, + int HoldDmaProg); int XDmaPs_IsActive(XDmaPs *InstPtr, unsigned int Channel); int XDmaPs_GenDmaProg(XDmaPs *InstPtr, unsigned int Channel, - XDmaPs_Cmd *Cmd); + XDmaPs_Cmd *Cmd); int XDmaPs_FreeDmaProg(XDmaPs *InstPtr, unsigned int Channel, - XDmaPs_Cmd *Cmd); + XDmaPs_Cmd *Cmd); void XDmaPs_Print_DmaProg(XDmaPs_Cmd *Cmd); @@ -256,13 +269,13 @@ int XDmaPs_ResetChannel(XDmaPs *InstPtr, unsigned int Channel); int XDmaPs_SetDoneHandler(XDmaPs *InstPtr, - unsigned Channel, - XDmaPsDoneHandler DoneHandler, - void *CallbackRef); + unsigned Channel, + XDmaPsDoneHandler DoneHandler, + void *CallbackRef); int XDmaPs_SetFaultHandler(XDmaPs *InstPtr, - XDmaPsFaultHandler FaultHandler, - void *CallbackRef); + XDmaPsFaultHandler FaultHandler, + void *CallbackRef); void XDmaPs_Print_DmaProg(XDmaPs_Cmd *Cmd); int XDmaPs_Instr_DMARMB(char *DmaProg); @@ -276,10 +289,10 @@ int XDmaPs_Instr_DMAWMB(char *DmaProg); static INLINE int XDmaPs_Instr_DMAEND(char *DmaProg); static INLINE void XDmaPs_Memcpy4(char *Dst, char *Src); static INLINE int XDmaPs_Instr_DMAGO(char *DmaProg, unsigned int Cn, - u32 Imm, unsigned int Ns); + u32 Imm, unsigned int Ns); static INLINE int XDmaPs_Instr_DMALD(char *DmaProg); static INLINE int XDmaPs_Instr_DMALP(char *DmaProg, unsigned Lc, - unsigned LoopIterations); + unsigned LoopIterations); static INLINE int XDmaPs_Instr_DMALPEND(char *DmaProg, char *BodyStart, unsigned Lc); static INLINE int XDmaPs_Instr_DMAMOV(char *DmaProg, unsigned Rd, u32 Imm); static INLINE int XDmaPs_Instr_DMANOP(char *DmaProg); @@ -312,7 +325,12 @@ void XDmaPs_FaultISR(XDmaPs *InstPtr); /* * Static loopup function implemented in xdmaps_sinit.c */ +#ifndef SDT XDmaPs_Config *XDmaPs_LookupConfig(u16 DeviceId); +#else +XDmaPs_Config *XDmaPs_LookupConfig(UINTPTR BaseAddress); +u32 XDmaPs_GetDrvIndex(XDmaPs *InstancePtr, UINTPTR BaseAddress); +#endif /* diff --git a/bsp_z7/ps7_cortexa9_0/include/xdmaps_hw.h b/bsp_z7/ps7_cortexa9_0/include/xdmaps_hw.h index d039278..32c2c91 100644 --- a/bsp_z7/ps7_cortexa9_0/include/xdmaps_hw.h +++ b/bsp_z7/ps7_cortexa9_0/include/xdmaps_hw.h @@ -1,5 +1,6 @@ /****************************************************************************** -* Copyright (C) 2009 - 2021 Xilinx, Inc. All rights reserved. +* Copyright (C) 2009 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -7,7 +8,7 @@ /** * * @file xdmaps_hw.h -* @addtogroup dmaps_v2_8 +* @addtogroup dmaps Overview * @{ * * This header file contains the hardware interface of an XDmaPs device. @@ -233,7 +234,7 @@ extern "C" { #define XDMAPS_INTCLR_ALL_MASK 0xFF #define XDmaPs_ReadReg(BaseAddress, RegOffset) \ - Xil_In32((BaseAddress) + (RegOffset)) + Xil_In32((BaseAddress) + (RegOffset)) /***************************************************************************/ /** @@ -251,7 +252,7 @@ extern "C" { * u32 RegisterValue) ******************************************************************************/ #define XDmaPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \ - Xil_Out32((BaseAddress) + (RegOffset), (RegisterValue)) + Xil_Out32((BaseAddress) + (RegOffset), (RegisterValue)) /************************** Variable Definitions *****************************/ /************************** Function Prototypes *****************************/ diff --git a/bsp_z7/ps7_cortexa9_0/include/xemacps.h b/bsp_z7/ps7_cortexa9_0/include/xemacps.h index ac3e7a7..564d926 100644 --- a/bsp_z7/ps7_cortexa9_0/include/xemacps.h +++ b/bsp_z7/ps7_cortexa9_0/include/xemacps.h @@ -1,5 +1,6 @@ /****************************************************************************** -* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved. +* Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (C) 2022 - 2024 Advanced Micro Devices, Inc. All rights reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -7,7 +8,7 @@ /** * * @file xemacps.h -* @addtogroup emacps_v3_16 +* @addtogroup emacps Overview * @{ * @details * @@ -417,15 +418,15 @@ extern "C" { #define XEMACPS_SGMII_ENABLE_OPTION 0x00008000U #define XEMACPS_DEFAULT_OPTIONS \ - ((u32)XEMACPS_FLOW_CONTROL_OPTION | \ - (u32)XEMACPS_FCS_INSERT_OPTION | \ - (u32)XEMACPS_FCS_STRIP_OPTION | \ - (u32)XEMACPS_BROADCAST_OPTION | \ - (u32)XEMACPS_LENTYPE_ERR_OPTION | \ - (u32)XEMACPS_TRANSMITTER_ENABLE_OPTION | \ - (u32)XEMACPS_RECEIVER_ENABLE_OPTION | \ - (u32)XEMACPS_RX_CHKSUM_ENABLE_OPTION | \ - (u32)XEMACPS_TX_CHKSUM_ENABLE_OPTION) + ((u32)XEMACPS_FLOW_CONTROL_OPTION | \ + (u32)XEMACPS_FCS_INSERT_OPTION | \ + (u32)XEMACPS_FCS_STRIP_OPTION | \ + (u32)XEMACPS_BROADCAST_OPTION | \ + (u32)XEMACPS_LENTYPE_ERR_OPTION | \ + (u32)XEMACPS_TRANSMITTER_ENABLE_OPTION | \ + (u32)XEMACPS_RECEIVER_ENABLE_OPTION | \ + (u32)XEMACPS_RX_CHKSUM_ENABLE_OPTION | \ + (u32)XEMACPS_TX_CHKSUM_ENABLE_OPTION) /**< Default options set when device is initialized or reset */ /*@}*/ @@ -456,11 +457,11 @@ extern "C" { #define XEMACPS_HDR_VLAN_SIZE 18U /* size of Ethernet header with VLAN */ #define XEMACPS_TRL_SIZE 4U /* size of Ethernet trailer (FCS) */ #define XEMACPS_MAX_FRAME_SIZE (XEMACPS_MTU + XEMACPS_HDR_SIZE + \ - XEMACPS_TRL_SIZE) + XEMACPS_TRL_SIZE) #define XEMACPS_MAX_VLAN_FRAME_SIZE (XEMACPS_MTU + XEMACPS_HDR_SIZE + \ - XEMACPS_HDR_VLAN_SIZE + XEMACPS_TRL_SIZE) + XEMACPS_HDR_VLAN_SIZE + XEMACPS_TRL_SIZE) #define XEMACPS_MAX_VLAN_FRAME_SIZE_JUMBO (XEMACPS_MTU_JUMBO + XEMACPS_HDR_SIZE + \ - XEMACPS_HDR_VLAN_SIZE + XEMACPS_TRL_SIZE) + XEMACPS_HDR_VLAN_SIZE + XEMACPS_TRL_SIZE) /* DMACR Bust length hash defines */ @@ -500,7 +501,7 @@ typedef void (*XEmacPs_Handler) (void *CallBackRef); * */ typedef void (*XEmacPs_ErrHandler) (void *CallBackRef, u8 Direction, - u32 ErrorWord); + u32 ErrorWord); /*@}*/ @@ -508,12 +509,25 @@ typedef void (*XEmacPs_ErrHandler) (void *CallBackRef, u8 Direction, * This typedef contains configuration information for a device. */ typedef struct { +#ifdef SDT + char *Name; /**< Unique name of the device */ +#else u16 DeviceId; /**< Unique ID of device */ +#endif UINTPTR BaseAddress;/**< Physical base address of IPIF registers */ u8 IsCacheCoherent; /**< Applicable only to A53 in EL1 mode; * describes whether Cache Coherent or not */ -#if defined (XCLOCKING) +#ifdef SDT + u16 IntrId; + UINTPTR IntrParent; +#endif +#if defined (XCLOCKING) || defined (SDT) u32 RefClk; /**< Input clock */ +#endif +#ifdef SDT + char *PhyType; /**< PhyType indicates which type of PHY interface is + * used (MII, GMII, RGMII, etc. + */ #endif u16 S1GDiv0; /**< 1Gbps Clock Divider 0 */ u8 S1GDiv1; /**< 1Gbps Clock Divider 1 */ @@ -606,8 +620,8 @@ typedef struct XEmacPs_Instance { *****************************************************************************/ #define XEmacPs_IntEnable(InstancePtr, Mask) \ XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \ - XEMACPS_IER_OFFSET, \ - ((Mask) & XEMACPS_IXR_ALL_MASK)); + XEMACPS_IER_OFFSET, \ + ((Mask) & XEMACPS_IXR_ALL_MASK)); /****************************************************************************/ /** @@ -627,8 +641,8 @@ typedef struct XEmacPs_Instance { *****************************************************************************/ #define XEmacPs_IntDisable(InstancePtr, Mask) \ XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \ - XEMACPS_IDR_OFFSET, \ - ((Mask) & XEMACPS_IXR_ALL_MASK)); + XEMACPS_IDR_OFFSET, \ + ((Mask) & XEMACPS_IXR_ALL_MASK)); /****************************************************************************/ /** @@ -648,8 +662,8 @@ typedef struct XEmacPs_Instance { *****************************************************************************/ #define XEmacPs_IntQ1Enable(InstancePtr, Mask) \ XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \ - XEMACPS_INTQ1_IER_OFFSET, \ - ((Mask) & XEMACPS_INTQ1_IXR_ALL_MASK)); + XEMACPS_INTQ1_IER_OFFSET, \ + ((Mask) & XEMACPS_INTQ1_IXR_ALL_MASK)); /****************************************************************************/ /** @@ -669,8 +683,8 @@ typedef struct XEmacPs_Instance { *****************************************************************************/ #define XEmacPs_IntQ1Disable(InstancePtr, Mask) \ XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \ - XEMACPS_INTQ1_IDR_OFFSET, \ - ((Mask) & XEMACPS_INTQ1_IXR_ALL_MASK)); + XEMACPS_INTQ1_IDR_OFFSET, \ + ((Mask) & XEMACPS_INTQ1_IXR_ALL_MASK)); /****************************************************************************/ /** @@ -687,10 +701,10 @@ typedef struct XEmacPs_Instance { * *****************************************************************************/ #define XEmacPs_Transmit(InstancePtr) \ - XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \ - XEMACPS_NWCTRL_OFFSET, \ - (XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \ - XEMACPS_NWCTRL_OFFSET) | XEMACPS_NWCTRL_STARTTX_MASK)) + XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \ + XEMACPS_NWCTRL_OFFSET, \ + (XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \ + XEMACPS_NWCTRL_OFFSET) | XEMACPS_NWCTRL_STARTTX_MASK)) /****************************************************************************/ /** @@ -711,9 +725,9 @@ typedef struct XEmacPs_Instance { * *****************************************************************************/ #define XEmacPs_IsRxCsum(InstancePtr) \ - ((XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \ - XEMACPS_NWCFG_OFFSET) & XEMACPS_NWCFG_RXCHKSUMEN_MASK) != 0U \ - ? TRUE : FALSE) + ((XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \ + XEMACPS_NWCFG_OFFSET) & XEMACPS_NWCFG_RXCHKSUMEN_MASK) != 0U \ + ? TRUE : FALSE) /****************************************************************************/ /** @@ -734,9 +748,9 @@ typedef struct XEmacPs_Instance { * *****************************************************************************/ #define XEmacPs_IsTxCsum(InstancePtr) \ - ((XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \ - XEMACPS_DMACR_OFFSET) & XEMACPS_DMACR_TCPCKSUM_MASK) != 0U \ - ? TRUE : FALSE) + ((XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \ + XEMACPS_DMACR_OFFSET) & XEMACPS_DMACR_TCPCKSUM_MASK) != 0U \ + ? TRUE : FALSE) /************************** Function Prototypes *****************************/ @@ -761,10 +775,10 @@ typedef struct XEmacPs_Instance { * *****************************************************************************/ #define XEmacPs_SetRXWatermark(InstancePtr, High, Low) \ - XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \ - XEMACPS_RXWATERMARK_OFFSET, \ - (High & XEMACPS_RXWM_HIGH_MASK) | \ - ((Low << XEMACPS_RXWM_LOW_SHFT_MSK) & XEMACPS_RXWM_LOW_MASK) |) + XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \ + XEMACPS_RXWATERMARK_OFFSET, \ + (High & XEMACPS_RXWM_HIGH_MASK) | \ + ((Low << XEMACPS_RXWM_LOW_SHFT_MSK) & XEMACPS_RXWM_LOW_MASK) |) /****************************************************************************/ /** @@ -781,8 +795,8 @@ typedef struct XEmacPs_Instance { * *****************************************************************************/ #define XEmacPs_GetRXWatermark(InstancePtr) \ - XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \ - XEMACPS_RXWATERMARK_OFFSET) + XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \ + XEMACPS_RXWATERMARK_OFFSET) /* * Initialization functions in xemacps.c */ @@ -797,7 +811,12 @@ void XEmacPs_SetQueuePtr(XEmacPs *InstancePtr, UINTPTR QPtr, u8 QueueNum, /* * Lookup configuration in xemacps_sinit.c */ + +#ifndef SDT XEmacPs_Config *XEmacPs_LookupConfig(u16 DeviceId); +#else +XEmacPs_Config *XEmacPs_LookupConfig(UINTPTR BaseAddress); +#endif /* * Interrupt-related functions in xemacps_intr.c @@ -823,7 +842,7 @@ void XEmacPs_ClearHash(XEmacPs *InstancePtr); void XEmacPs_GetHash(XEmacPs *InstancePtr, void *AddressPtr); void XEmacPs_SetMdioDivisor(XEmacPs *InstancePtr, - XEmacPs_MdcDiv Divisor); + XEmacPs_MdcDiv Divisor); void XEmacPs_SetOperatingSpeed(XEmacPs *InstancePtr, u16 Speed); u16 XEmacPs_GetOperatingSpeed(XEmacPs *InstancePtr); LONG XEmacPs_PhyRead(XEmacPs *InstancePtr, u32 PhyAddress, diff --git a/bsp_z7/ps7_cortexa9_0/include/xemacps_bd.h b/bsp_z7/ps7_cortexa9_0/include/xemacps_bd.h index aff79ff..4641553 100644 --- a/bsp_z7/ps7_cortexa9_0/include/xemacps_bd.h +++ b/bsp_z7/ps7_cortexa9_0/include/xemacps_bd.h @@ -1,5 +1,6 @@ /****************************************************************************** -* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved. +* Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (C) 2022 - 2024 Advanced Micro Devices, Inc. All rights reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -7,7 +8,7 @@ /** * * @file xemacps_bd.h -* @addtogroup emacps_v3_16 +* @addtogroup emacps Overview * @{ * * This header provides operations to manage buffer descriptors in support @@ -45,6 +46,7 @@ * 3.2 hk 11/18/15 Change BD typedef and number of words. * 3.8 hk 08/18/18 Remove duplicate definition of XEmacPs_BdSetLength * 3.8 mus 11/05/18 Support 64 bit DMA addresses for Microblaze-X platform. + * 3.9 aj 22/03/24 Add mask for XEmaPs_BdGetBufAddr * * * @@ -239,11 +241,11 @@ typedef u32 XEmacPs_Bd[XEMACPS_BD_NUM_WORDS]; *****************************************************************************/ #if defined(__aarch64__) || defined(__arch64__) #define XEmacPs_BdGetBufAddr(BdPtr) \ - (XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) | \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & XEMACPS_RXBUF_ADD_MASK) | \ (XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_HI_OFFSET)) << 32U) #else #define XEmacPs_BdGetBufAddr(BdPtr) \ - (XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET)) + (XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & XEMACPS_RXBUF_ADD_MASK) #endif /*****************************************************************************/ diff --git a/bsp_z7/ps7_cortexa9_0/include/xemacps_bdring.h b/bsp_z7/ps7_cortexa9_0/include/xemacps_bdring.h index f5653db..017669d 100644 --- a/bsp_z7/ps7_cortexa9_0/include/xemacps_bdring.h +++ b/bsp_z7/ps7_cortexa9_0/include/xemacps_bdring.h @@ -1,5 +1,6 @@ /****************************************************************************** -* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved. +* Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -7,7 +8,7 @@ /** * * @file xemacps_bdring.h -* @addtogroup emacps_v3_16 +* @addtogroup emacps Overview * @{ * * The Xiline EmacPs Buffer Descriptor ring driver. This is part of EmacPs diff --git a/bsp_z7/ps7_cortexa9_0/include/xemacps_hw.h b/bsp_z7/ps7_cortexa9_0/include/xemacps_hw.h index 59fe1ec..765411d 100644 --- a/bsp_z7/ps7_cortexa9_0/include/xemacps_hw.h +++ b/bsp_z7/ps7_cortexa9_0/include/xemacps_hw.h @@ -8,7 +8,7 @@ /** * * @file xemacps_hw.h -* @addtogroup emacps_v3_16 +* @addtogroup emacps Overview * @{ * * This header file contains identifiers and low-level driver functions (or diff --git a/bsp_z7/ps7_cortexa9_0/include/xgpiops.h b/bsp_z7/ps7_cortexa9_0/include/xgpiops.h index 8b1d89f..cce171a 100644 --- a/bsp_z7/ps7_cortexa9_0/include/xgpiops.h +++ b/bsp_z7/ps7_cortexa9_0/include/xgpiops.h @@ -1,6 +1,6 @@ /****************************************************************************** * Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved. -* Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved. +* Copyright (c) 2022 - 2024 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -124,6 +124,11 @@ * 3.8 sne 09/17/20 Added description for Versal PS and PMC GPIO pins. * 3.9 sne 03/15/21 Fixed MISRA-C violations. * 3.11 sg 02/23/23 Update bank and pin mapping information. +* 3.12 gm 07/11/23 Added SDT support. +* 3.13 gm 03/15/24 Remove const of XGpioPs InstancePtr from function proto +* type of XGpioPs_IntrEnable, XGpioPs_IntrDisable, +* XGpioPs_IntrEnablePin and XGpioPs_IntrDisablePin +* to add multi-core interrupt support. * * * @@ -167,6 +172,7 @@ extern "C" { * Zynq Ultrascale+ MP GPIO device */ #define XGPIOPS_MAX_BANKS 0x04U /**< Max banks in a Zynq GPIO device */ +#define XGPIOPS_MAX_BANKS_CNT 0x06U /**< Max banks number of all platforms */ #define XGPIOPS_DEVICE_MAX_PIN_NUM_ZYNQMP (u32)174 /**< Max pins in the * Zynq Ultrascale+ MP GPIO device @@ -209,8 +215,18 @@ typedef void (*XGpioPs_Handler) (void *CallBackRef, u32 Bank, u32 Status); * This typedef contains configuration information for a device. */ typedef struct { +#ifndef SDT u16 DeviceId; /**< Unique ID of device */ +#else + char *Name; +#endif UINTPTR BaseAddr; /**< Register base address */ +#ifdef SDT + u16 IntrId; /** Bits[11:0] Interrupt-id Bits[15:12] + * trigger type and level flags */ + UINTPTR IntrParent; /** Bit[0] Interrupt parent type Bit[64/32:1] + * Parent base address */ +#endif } XGpioPs_Config; /** @@ -227,6 +243,7 @@ typedef struct { u32 MaxPinNum; /**< Max pins in the GPIO device */ u8 MaxBanks; /**< Max banks in a GPIO device */ u32 PmcGpio; /**< Flag for accessing PS GPIO for versal*/ + u32 CoreIntrMask[XGPIOPS_MAX_BANKS_CNT]; /**< Interrupt mask per core */ } XGpioPs; /************************** Variable Definitions *****************************/ @@ -262,12 +279,12 @@ void XGpioPs_SetOutputEnablePin(const XGpioPs *InstancePtr, u32 Pin, u32 OpEnabl u32 XGpioPs_GetOutputEnablePin(const XGpioPs *InstancePtr, u32 Pin); /* Diagnostic functions in xgpiops_selftest.c */ -s32 XGpioPs_SelfTest(const XGpioPs *InstancePtr); +s32 XGpioPs_SelfTest(XGpioPs *InstancePtr); /* Functions in xgpiops_intr.c */ /* Bank APIs in xgpiops_intr.c */ -void XGpioPs_IntrEnable(const XGpioPs *InstancePtr, u8 Bank, u32 Mask); -void XGpioPs_IntrDisable(const XGpioPs *InstancePtr, u8 Bank, u32 Mask); +void XGpioPs_IntrEnable(XGpioPs *InstancePtr, u8 Bank, u32 Mask); +void XGpioPs_IntrDisable(XGpioPs *InstancePtr, u8 Bank, u32 Mask); u32 XGpioPs_IntrGetEnabled(const XGpioPs *InstancePtr, u8 Bank); u32 XGpioPs_IntrGetStatus(const XGpioPs *InstancePtr, u8 Bank); void XGpioPs_IntrClear(const XGpioPs *InstancePtr, u8 Bank, u32 Mask); @@ -283,14 +300,18 @@ void XGpioPs_IntrHandler(const XGpioPs *InstancePtr); void XGpioPs_SetIntrTypePin(const XGpioPs *InstancePtr, u32 Pin, u8 IrqType); u8 XGpioPs_GetIntrTypePin(const XGpioPs *InstancePtr, u32 Pin); -void XGpioPs_IntrEnablePin(const XGpioPs *InstancePtr, u32 Pin); -void XGpioPs_IntrDisablePin(const XGpioPs *InstancePtr, u32 Pin); +void XGpioPs_IntrEnablePin(XGpioPs *InstancePtr, u32 Pin); +void XGpioPs_IntrDisablePin(XGpioPs *InstancePtr, u32 Pin); u32 XGpioPs_IntrGetEnabledPin(const XGpioPs *InstancePtr, u32 Pin); u32 XGpioPs_IntrGetStatusPin(const XGpioPs *InstancePtr, u32 Pin); void XGpioPs_IntrClearPin(const XGpioPs *InstancePtr, u32 Pin); /* Functions in xgpiops_sinit.c */ +#ifndef SDT XGpioPs_Config *XGpioPs_LookupConfig(u16 DeviceId); +#else +XGpioPs_Config *XGpioPs_LookupConfig(u32 BaseAddress); +#endif #ifdef __cplusplus } #endif diff --git a/bsp_z7/ps7_cortexa9_0/include/xgpiops_hw.h b/bsp_z7/ps7_cortexa9_0/include/xgpiops_hw.h index d291abb..3248dc2 100644 --- a/bsp_z7/ps7_cortexa9_0/include/xgpiops_hw.h +++ b/bsp_z7/ps7_cortexa9_0/include/xgpiops_hw.h @@ -1,6 +1,6 @@ /****************************************************************************** * Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved. -* Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved. +* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ diff --git a/bsp_z7/ps7_cortexa9_0/include/xil_cache.h b/bsp_z7/ps7_cortexa9_0/include/xil_cache.h index 75cd6f6..7c94568 100644 --- a/bsp_z7/ps7_cortexa9_0/include/xil_cache.h +++ b/bsp_z7/ps7_cortexa9_0/include/xil_cache.h @@ -1,5 +1,6 @@ /****************************************************************************** -* Copyright (c) 2010 - 2021 Xilinx, Inc. All rights reserved. +* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved. +* Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -26,6 +27,7 @@ * 3.04a sdm 01/02/12 Remove redundant dsb/dmb instructions in cache maintenance * APIs. * 6.8 aru 09/06/18 Removed compilation warnings for ARMCC toolchain. +* 9.0 ml 03/03/23 Updated function prototypes. * * ******************************************************************************/ diff --git a/bsp_z7/ps7_cortexa9_0/include/xil_cryptoalginfo.h b/bsp_z7/ps7_cortexa9_0/include/xil_cryptoalginfo.h new file mode 100644 index 0000000..df95b88 --- /dev/null +++ b/bsp_z7/ps7_cortexa9_0/include/xil_cryptoalginfo.h @@ -0,0 +1,50 @@ +/******************************************************************************/ +/** +* Copyright (c) 2023 Advanced Micro Devices, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/****************************************************************************/ +/** +* @file xil_cryptoalginfo.h +* @{ +* @details +* +* Crypto algotithm information structure declaration. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 9.0   mmd      07/04/23 First release.
+*
+* +*****************************************************************************/ +#ifndef XIL_CRYPTOALGINFO_H +#define XIL_CRYPTOALGINFO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ +#include "xil_types.h" + +/**************************** Type Definitions *******************************/ +typedef enum _Xil_CryptoAlgNistStatus { + NOT_APPLICABLE = 0x00, + NIST_COMPLIANT = 0x11, + NIST_NON_COMPLIANT = 0xFE, +} Xil_CryptoAlgNistStatus; + +typedef struct _Xil_CryptoAlgInfo { + u32 Version; + Xil_CryptoAlgNistStatus NistStatus; +} Xil_CryptoAlgInfo; + +#ifdef __cplusplus +} +#endif + +#endif /* XIL_CRYPTOALGINFO_H */ diff --git a/bsp_z7/ps7_cortexa9_0/include/xil_exception.h b/bsp_z7/ps7_cortexa9_0/include/xil_exception.h index 3a5bb29..b517983 100644 --- a/bsp_z7/ps7_cortexa9_0/include/xil_exception.h +++ b/bsp_z7/ps7_cortexa9_0/include/xil_exception.h @@ -75,8 +75,10 @@ #include "xil_types.h" #include "xpseudo_asm.h" #include "bspconfig.h" +#ifndef SDT #include "xparameters.h" #include "xdebug.h" +#endif #ifdef __cplusplus extern "C" { @@ -228,7 +230,7 @@ extern "C" { /* * XIL_EXCEPTION_ID_INT is defined for all Xilinx processors. */ -#if (defined (versal) && !defined(ARMR5) && EL3) || defined(ARMR52) +#if (defined (versal) && !defined(ARMR5) && EL3) #define XIL_EXCEPTION_ID_INT XIL_EXCEPTION_ID_FIQ_INT #else #define XIL_EXCEPTION_ID_INT XIL_EXCEPTION_ID_IRQ_INT @@ -267,7 +269,7 @@ extern XExc_VectorTableEntry XExc_VectorTable[]; * C-Style signature: void Xil_ExceptionEnableMask(Mask) * ******************************************************************************/ -#if (defined (versal) && !defined(ARMR5) && EL3) || defined(ARMR52) +#if (defined (versal) && !defined(ARMR5) && EL3) /* * Cortexa72 processor in versal is coupled with GIC-500, and GIC-500 supports * only FIQ at EL3. Hence, tweaking this macro to always enable FIQ @@ -295,7 +297,7 @@ extern XExc_VectorTableEntry XExc_VectorTable[]; * @note None. * ******************************************************************************/ -#if (defined (versal) && !defined(ARMR5) && EL3) || defined(ARMR52) +#if (defined (versal) && !defined(ARMR5) && EL3) #define Xil_ExceptionEnable() \ Xil_ExceptionEnableMask(XIL_EXCEPTION_FIQ) #else @@ -315,7 +317,7 @@ extern XExc_VectorTableEntry XExc_VectorTable[]; * C-Style signature: Xil_ExceptionDisableMask(Mask) * ******************************************************************************/ -#if (defined (versal) && !defined(ARMR5) && EL3) || defined(ARMR52) +#if (defined (versal) && !defined(ARMR5) && EL3) /* * Cortexa72 processor in versal is coupled with GIC-500, and GIC-500 supports * only FIQ at EL3. Hence, tweaking this macro to always disable FIQ diff --git a/bsp_z7/ps7_cortexa9_0/include/xil_io.h b/bsp_z7/ps7_cortexa9_0/include/xil_io.h index 853ef6b..382bc87 100644 --- a/bsp_z7/ps7_cortexa9_0/include/xil_io.h +++ b/bsp_z7/ps7_cortexa9_0/include/xil_io.h @@ -1,5 +1,6 @@ /****************************************************************************** -* Copyright (c) 2014 - 2021 Xilinx, Inc. All rights reserved. +* Copyright (C) 2014 - 2021 Xilinx, Inc. All rights reserved. +* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -32,12 +33,12 @@ * 7.50 dp 02/12/21 Fix compilation error in Xil_EndianSwap32() that occur * when -Werror=conversion compiler flag is enabled * 7.5 mus 05/17/21 Update the functions with comments. It fixes CR#1067739. -* +* 9.0 ml 03/03/23 Add description and remove comments to fix doxygen warnings. * ******************************************************************************/ -#ifndef XIL_IO_H /* prevent circular inclusions */ -#define XIL_IO_H /* by using protection macros */ +#ifndef XIL_IO_H /**< prevent circular inclusions */ +#define XIL_IO_H /**< by using protection macros */ #ifdef __cplusplus extern "C" { @@ -63,25 +64,25 @@ extern u32 XStl_RegUpdate(u32 RegAddr, u32 RegVal); /***************** Macros (Inline Functions) Definitions *********************/ #if defined __GNUC__ #if defined (__MICROBLAZE__) -# define INST_SYNC mbar(0) -# define DATA_SYNC mbar(1) +# define INST_SYNC mbar(0) /**< Instruction Synchronization Barrier */ +# define DATA_SYNC mbar(1) /**< Data Synchronization Barrier */ # else -# define SYNCHRONIZE_IO dmb() -# define INST_SYNC isb() -# define DATA_SYNC dsb() +# define SYNCHRONIZE_IO dmb() /**< Data Memory Barrier */ +# define INST_SYNC isb() /**< Instruction Synchronization Barrier */ +# define DATA_SYNC dsb() /**< Data Synchronization Barrier */ # endif #else -# define SYNCHRONIZE_IO -# define INST_SYNC -# define DATA_SYNC -# define INST_SYNC -# define DATA_SYNC +# define SYNCHRONIZE_IO /**< Data Memory Barrier */ +# define INST_SYNC /**< Instruction Synchronization Barrier */ +# define DATA_SYNC /**< Data Synchronization Barrier */ +# define INST_SYNC /**< Instruction Synchronization Barrier */ +# define DATA_SYNC /**< Data Synchronization Barrier */ #endif #if defined (__GNUC__) || defined (__ICCARM__) || defined (__MICROBLAZE__) -#define INLINE inline +#define INLINE inline /**< static inline keyword */ #else -#define INLINE __inline +#define INLINE __inline /** * *****************************************************************************/ -#ifndef XIL_MEM_H /* prevent circular inclusions */ -#define XIL_MEM_H /* by using protection macros */ +#ifndef XIL_MEM_H /**< prevent circular inclusions */ +#define XIL_MEM_H /**< by using protection macros */ #ifdef __cplusplus extern "C" { diff --git a/bsp_z7/ps7_cortexa9_0/include/xil_misc_psreset_api.h b/bsp_z7/ps7_cortexa9_0/include/xil_misc_psreset_api.h index 878d575..de0ff25 100644 --- a/bsp_z7/ps7_cortexa9_0/include/xil_misc_psreset_api.h +++ b/bsp_z7/ps7_cortexa9_0/include/xil_misc_psreset_api.h @@ -1,5 +1,6 @@ /****************************************************************************** -* Copyright (c) 2013 - 2021 Xilinx, Inc. All rights reserved. +* Copyright (C) 2013 - 2021 Xilinx, Inc. All rights reserved. +* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -15,12 +16,13 @@ * Ver Who Date Changes * ----- ---- -------- ------------------------------------------------------- * 1.00b kpc 03/07/13 First release. +* 9.0 ml 03/03/23 Add description to fix doxygen warnings. * * ******************************************************************************/ -#ifndef XIL_MISC_RESET_H /* prevent circular inclusions */ -#define XIL_MISC_RESET_H /* by using protection macros */ +#ifndef XIL_MISC_RESET_H /**< prevent circular inclusions */ +#define XIL_MISC_RESET_H /**< by using protection macros */ #ifdef __cplusplus extern "C" { diff --git a/bsp_z7/ps7_cortexa9_0/include/xil_printf.c b/bsp_z7/ps7_cortexa9_0/include/xil_printf.c index bf104fd..0f718bf 100644 --- a/bsp_z7/ps7_cortexa9_0/include/xil_printf.c +++ b/bsp_z7/ps7_cortexa9_0/include/xil_printf.c @@ -1,5 +1,6 @@ /****************************************************************************** -* Copyright (c) 1995 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (C) 1995 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (C) 2023 - 2024 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT *******************************************************************************/ /*---------------------------------------------------*/ @@ -12,24 +13,38 @@ #include "xil_printf.h" #include "xil_types.h" #include "xil_assert.h" +#include "bspconfig.h" #include #include #include -static void padding( const s32 l_flag,const struct params_s *par); +/************************** Function Prototypes ******************************/ + +static void padding( const s32 l_flag, const struct params_s *par); static void outs(const charptr lp, struct params_s *par); -static s32 getnum( charptr* linep); +static s32 getnum( charptr *linep); + +/**************************** Type Definitions *******************************/ typedef struct params_s { - s32 len; - s32 num1; - s32 num2; - char8 pad_character; - s32 do_padding; - s32 left_flag; - s32 unsigned_flag; + s32 len; /**< length */ + s32 num1; /**< number 1 */ + s32 num2; /**< number 2 */ + char8 pad_character; /**< pad character */ + s32 do_padding; /**< do padding */ + s32 left_flag; /**< left flag */ + s32 unsigned_flag; /**< unsigned flag */ } params_t; +/***************** Macros (Inline Functions) Definitions *********************/ + +#if (defined(__MICROBLAZE__)) && (!defined(__arch64__)) +#define MICROBLAZE32 +#endif + +#if (!defined(MICROBLAZE32)) && (!defined(ZYNQMP_R5_FSBL_BSP)) && (!defined(DISABLE_64BIT_PRINT)) +#define SUPPORT_64BIT_PRINT +#endif /*---------------------------------------------------*/ /* The purpose of this routine is to output data the */ @@ -40,107 +55,109 @@ typedef struct params_s { /*---------------------------------------------------*/ -/*---------------------------------------------------*/ -/* */ -/* This routine puts pad characters into the output */ -/* buffer. */ -/* */ + +/*****************************************************************************/ +/** +* This routine puts pad characters into the output buffer. +* +******************************************************************************/ static void padding( const s32 l_flag, const struct params_s *par) { - s32 i; + s32 i; - if ((par->do_padding != 0) && (l_flag != 0) && (par->len < par->num1)) { - i=(par->len); - for (; i<(par->num1); i++) { -#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM) - outbyte( par->pad_character); + if ((par->do_padding != 0) && (l_flag != 0) && (par->len < par->num1)) { + i = (par->len); + for (; i < (par->num1); i++) { +#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM) || defined(SDT) + outbyte( par->pad_character); #endif } - } + } } -/*---------------------------------------------------*/ -/* */ -/* This routine moves a string to the output buffer */ -/* as directed by the padding and positioning flags. */ -/* */ +/******************************************************************************/ +/** +* This routine moves a string to the output buffer +* as directed by the padding and positioning flags. +* +*******************************************************************************/ static void outs(const charptr lp, struct params_s *par) { - charptr LocalPtr; + charptr LocalPtr; LocalPtr = lp; - /* pad on left if needed */ - if(LocalPtr != NULL) { + /* pad on left if needed */ + if (LocalPtr != NULL) { par->len = (s32)strlen( LocalPtr); padding( !(par->left_flag), par); /* Move string to the buffer */ while (((*LocalPtr) != (char8)0) && ((par->num2) != 0)) { (par->num2)--; -#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM) +#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM) || defined(SDT) outbyte(*LocalPtr); #endif LocalPtr += 1; } + } + + /* Pad on right if needed */ + /* CR 439175 - elided next stmt. Seemed bogus. */ + padding( par->left_flag, par); } - /* Pad on right if needed */ - /* CR 439175 - elided next stmt. Seemed bogus. */ - padding( par->left_flag, par); -} - -/*---------------------------------------------------*/ -/* */ -/* This routine moves a number to the output buffer */ -/* as directed by the padding and positioning flags. */ -/* */ - +/*****************************************************************************/ +/** +* +* This routine moves a number to the output buffer +* as directed by the padding and positioning flags. +* +******************************************************************************/ static void outnum( const s32 n, const s32 base, struct params_s *par) { - s32 negative; + s32 negative; s32 i; - char8 outbuf[32]; - const char8 digits[] = "0123456789ABCDEF"; - u32 num; - for(i = 0; i<32; i++) { - outbuf[i] = '0'; - } + char8 outbuf[32]; + const char8 digits[] = "0123456789ABCDEF"; + u32 num; + for (i = 0; i < 32; i++) { + outbuf[i] = '0'; + } - /* Check if number is negative */ - if ((par->unsigned_flag == 0) && (base == 10) && (n < 0L)) { - negative = 1; - num =(-(n)); - } - else{ - num = n; - negative = 0; - } + /* Check if number is negative */ + if ((par->unsigned_flag == 0) && (base == 10) && (n < 0L)) { + negative = 1; + num = (-(n)); + } else { + num = n; + negative = 0; + } - /* Build number (backwards) in outbuf */ - i = 0; - do { + /* Build number (backwards) in outbuf */ + i = 0; + do { outbuf[i] = digits[(num % (u32)base)]; i++; num /= base; - } while (num > 0U); + } while (num > 0U); - if (negative != 0) { + if (negative != 0) { outbuf[i] = '-'; i++; } - outbuf[i] = '\0'; - i--; + outbuf[i] = '\0'; + i--; - /* Move the converted number to the buffer and */ - /* add in the padding where needed. */ - par->len = (s32)strlen(outbuf); - padding( !(par->left_flag), par); - while (&outbuf[i] >= outbuf) { -#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM) - outbyte( outbuf[i] ); + /* Move the converted number to the buffer and */ + /* add in the padding where needed. */ + par->len = (s32)strlen(outbuf); + padding( !(par->left_flag), par); + while (&outbuf[i] >= outbuf) { +#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM) || defined(SDT) + outbyte( outbuf[i] ); #endif i--; -} - padding( par->left_flag, par); + } + padding( par->left_flag, par); } /*---------------------------------------------------*/ /* */ @@ -148,96 +165,98 @@ static void outnum( const s32 n, const s32 base, struct params_s *par) /* buffer as directed by the padding and positioning */ /* flags. */ /* */ -#if defined (__aarch64__) || defined (__arch64__) +#if defined (SUPPORT_64BIT_PRINT) static void outnum1( const s64 n, const s32 base, params_t *par) { - s32 negative; + s32 negative; s32 i; - char8 outbuf[64]; - const char8 digits[] = "0123456789ABCDEF"; - u64 num; - for(i = 0; i<64; i++) { - outbuf[i] = '0'; - } + char8 outbuf[64]; + const char8 digits[] = "0123456789ABCDEF"; + u64 num; + for (i = 0; i < 64; i++) { + outbuf[i] = '0'; + } - /* Check if number is negative */ - if ((par->unsigned_flag == 0) && (base == 10) && (n < 0L)) { - negative = 1; - num =(-(n)); - } - else{ - num = (n); - negative = 0; - } + /* Check if number is negative */ + if ((par->unsigned_flag == 0) && (base == 10) && (n < 0L)) { + negative = 1; + num = (-(n)); + } else { + num = (n); + negative = 0; + } - /* Build number (backwards) in outbuf */ - i = 0; - do { + /* Build number (backwards) in outbuf */ + i = 0; + do { outbuf[i] = digits[(num % base)]; i++; num /= base; - } while (num > 0); + } while (num > 0); - if (negative != 0) { + if (negative != 0) { outbuf[i] = '-'; i++; } - outbuf[i] = '\0'; - i--; + outbuf[i] = '\0'; + i--; - /* Move the converted number to the buffer and */ - /* add in the padding where needed. */ - par->len = (s32)strlen(outbuf); - padding( !(par->left_flag), par); - while (&outbuf[i] >= outbuf) { - outbyte( outbuf[i] ); + /* Move the converted number to the buffer and */ + /* add in the padding where needed. */ + par->len = (s32)strlen(outbuf); + padding( !(par->left_flag), par); + while (&outbuf[i] >= outbuf) { + outbyte( outbuf[i] ); i--; -} - padding( par->left_flag, par); + } + padding( par->left_flag, par); } #endif -/*---------------------------------------------------*/ -/* */ -/* This routine gets a number from the format */ -/* string. */ -/* */ -static s32 getnum(charptr* linep) + +/*****************************************************************************/ +/** +* +* This routine gets a number from the format string. +* +******************************************************************************/ +static s32 getnum(charptr *linep) { s32 n = 0; s32 ResultIsDigit = 0; charptr cptr = *linep; while (cptr != NULL) { - ResultIsDigit = isdigit(((u8)*cptr)); + ResultIsDigit = isdigit(((u8) * cptr)); if (ResultIsDigit == 0) { break; } - n = ((n*10) + (((s32)*cptr) - (s32)'0')); + n = ((n * 10) + (((s32) * cptr) - (s32)'0')); cptr += 1; } *linep = ((charptr)(cptr)); - return(n); + return (n); } -/*---------------------------------------------------*/ -/* */ -/* This routine operates just like a printf/sprintf */ -/* routine. It outputs a set of data under the */ -/* control of a formatting string. Not all of the */ -/* standard C format control are supported. The ones */ -/* provided are primarily those needed for embedded */ -/* systems work. Primarily the floating point */ -/* routines are omitted. Other formats could be */ -/* added easily by following the examples shown for */ -/* the supported formats. */ -/* */ - -/* void esp_printf( const func_ptr f_ptr, - const charptr ctrl1, ...) */ +/*****************************************************************************/ +/** +* This routine operates just like a printf/sprintf +* routine. It outputs a set of data under the +* control of a formatting string. Not all of the +* standard C format control are supported. The ones +* provided are primarily those needed for embedded +* systems work. Primarily the floating point +* routines are omitted. Other formats could be +* added easily by following the examples shown for +* the supported formats. +* void esp_printf( const func_ptr f_ptr, +* const charptr ctrl1, ...) +* +*******************************************************************************/ #if defined (__aarch64__) && HYP_GUEST && EL1_NONSECURE && XEN_USE_PV_CONSOLE -void xil_printf( const char8 *ctrl1, ...){ +void xil_printf( const char8 *ctrl1, ...) +{ XPVXenConsole_Printf(ctrl1); } #else @@ -253,195 +272,205 @@ void xil_printf( const char8 *ctrl1, ...) } #endif -/* This routine is equivalent to vprintf routine */ +/*****************************************************************************/ +/** +* This routine is equivalent to vprintf routine +******************************************************************************/ void xil_vprintf(const char8 *ctrl1, va_list argp) { s32 Check; -#if defined (__aarch64__) || defined (__arch64__) - s32 long_flag; +#if defined (SUPPORT_64BIT_PRINT) + s32 long_flag; #endif - s32 dot_flag; + s32 dot_flag; + u32 width, index; + params_t par; - params_t par; + u8 ch; + char8 *ctrl = (char8 *)ctrl1; + const char *string; - u8 ch; - char8 *ctrl = (char8 *)ctrl1; + while ((ctrl != NULL) && (*ctrl != (char8)0)) { - while ((ctrl != NULL) && (*ctrl != (char8)0)) { - - /* move format string chars to buffer until a */ - /* format control is found. */ - if (*ctrl != '%') { -#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM) - outbyte(*ctrl); + /* move format string chars to buffer until a */ + /* format control is found. */ + if (*ctrl != '%') { +#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM) || defined(SDT) + outbyte(*ctrl); #endif ctrl += 1; - continue; - } + continue; + } - /* initialize all the flags for this format. */ - dot_flag = 0; -#if defined (__aarch64__) || defined (__arch64__) + /* initialize all the flags for this format. */ + dot_flag = 0; +#if defined (SUPPORT_64BIT_PRINT) long_flag = 0; #endif - par.unsigned_flag = 0; + par.unsigned_flag = 0; par.left_flag = 0; par.do_padding = 0; - par.pad_character = ' '; - par.num2=32767; - par.num1=0; - par.len=0; + par.pad_character = ' '; + par.num2 = 32767; + par.num1 = 0; + par.len = 0; - try_next: - if(ctrl != NULL) { +try_next: + if (ctrl != NULL) { ctrl += 1; } - if(ctrl != NULL) { - ch = (u8)*ctrl; + if (ctrl != NULL) { + ch = (u8) * ctrl; } else { break; } - if (isdigit(ch) != 0) { - if (dot_flag != 0) { - par.num2 = getnum(&ctrl); - } - else { - if (ch == (u8)'0') { - par.pad_character = '0'; + if (isdigit(ch) != 0) { + if (dot_flag != 0) { + par.num2 = getnum(&ctrl); + } else { + if (ch == (u8)'0') { + par.pad_character = '0'; } - if(ctrl != NULL) { - par.num1 = getnum(&ctrl); + if (ctrl != NULL) { + par.num1 = getnum(&ctrl); } - par.do_padding = 1; - } - if(ctrl != NULL) { - ctrl -= 1; + par.do_padding = 1; } - goto try_next; - } + if (ctrl != NULL) { + ctrl -= 1; + } + goto try_next; + } - switch (tolower(ch)) { - case '%': -#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM) - outbyte( '%'); + switch (tolower(ch)) { + case '%': +#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM) || defined(SDT) + outbyte( '%'); #endif - Check = 1; - break; - - case '-': - par.left_flag = 1; - Check = 0; - break; - - case '.': - dot_flag = 1; - Check = 0; - break; - - case 'l': - #if defined (__aarch64__) || defined (__arch64__) - long_flag = 1; - #endif - Check = 0; - break; - - case 'u': - par.unsigned_flag = 1; - /* fall through */ - case 'i': - case 'd': - #if defined (__aarch64__) || defined (__arch64__) - if (long_flag != 0){ - outnum1((s64)va_arg(argp, s64), 10L, &par); - } - else { - outnum( va_arg(argp, s32), 10L, &par); - } - #else - outnum( va_arg(argp, s32), 10L, &par); - #endif Check = 1; - break; - case 'p': - #if defined (__aarch64__) || defined (__arch64__) - par.unsigned_flag = 1; - outnum1((s64)va_arg(argp, s64), 16L, &par); - Check = 1; - break; - #endif - case 'X': - case 'x': - par.unsigned_flag = 1; - #if defined (__aarch64__) || defined (__arch64__) - if (long_flag != 0) { - outnum1((s64)va_arg(argp, s64), 16L, &par); + break; + + case '-': + par.left_flag = 1; + Check = 0; + break; + + case '.': + if ((*(ctrl + 1) == '*') && (*(ctrl + 2) == 's')) { + width = va_arg(argp, u32); + string = va_arg(argp, const char *); + for (index = 0; index < width && string[index] != '\0' ; index++) { + outbyte(string[index]); + } + ctrl += 2; + } else { + dot_flag = 1; + Check = 0; } - else { - outnum((s32)va_arg(argp, s32), 16L, &par); - } - #else - outnum((s32)va_arg(argp, s32), 16L, &par); - #endif - Check = 1; - break; + break; - case 's': - outs( va_arg( argp, char *), &par); - Check = 1; - break; + case 'l': +#if defined (SUPPORT_64BIT_PRINT) + long_flag = 1; +#endif + Check = 0; + break; - case 'c': -#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM) - outbyte( (char8)va_arg( argp, s32)); + case 'u': + par.unsigned_flag = 1; + /* fall through */ + case 'i': + case 'd': +#if defined (SUPPORT_64BIT_PRINT) + if (long_flag != 0) { + outnum1((s64)va_arg(argp, s64), 10L, &par); + } else { + outnum( va_arg(argp, s32), 10L, &par); + } +#else + outnum( va_arg(argp, s32), 10L, &par); #endif - Check = 1; - break; + Check = 1; + break; + case 'p': +#if defined (__aarch64__) || defined (__arch64__) + par.unsigned_flag = 1; + outnum1((s64)va_arg(argp, s64), 16L, &par); + Check = 1; + break; +#endif + case 'X': + case 'x': + par.unsigned_flag = 1; +#if defined (SUPPORT_64BIT_PRINT) + if (long_flag != 0) { + outnum1((s64)va_arg(argp, s64), 16L, &par); + } else { + outnum((s32)va_arg(argp, s32), 16L, &par); + } +#else + outnum((s32)va_arg(argp, s32), 16L, &par); +#endif + Check = 1; + break; - case '\\': - switch (*ctrl) { - case 'a': -#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM) - outbyte( ((char8)0x07)); -#endif - break; - case 'h': -#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM) - outbyte( ((char8)0x08)); -#endif - break; - case 'r': -#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM) - outbyte( ((char8)0x0D)); -#endif - break; - case 'n': -#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM) - outbyte( ((char8)0x0D)); - outbyte( ((char8)0x0A)); -#endif - break; - default: -#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM) - outbyte( *ctrl); -#endif - break; - } - ctrl += 1; - Check = 0; - break; + case 's': + outs( va_arg( argp, char *), &par); + Check = 1; + break; - default: - Check = 1; - break; - } - if(Check == 1) { - if(ctrl != NULL) { + case 'c': +#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM) || defined(SDT) + outbyte( (char8)va_arg( argp, s32)); +#endif + Check = 1; + break; + + case '\\': + switch (*ctrl) { + case 'a': +#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM) || defined(SDT) + outbyte( ((char8)0x07)); +#endif + break; + case 'h': +#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM) || defined(SDT) + outbyte( ((char8)0x08)); +#endif + break; + case 'r': +#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM) || defined(SDT) + outbyte( ((char8)0x0D)); +#endif + break; + case 'n': +#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM) || defined(SDT) + outbyte( ((char8)0x0D)); + outbyte( ((char8)0x0A)); +#endif + break; + default: +#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM) || defined(SDT) + outbyte( *ctrl); +#endif + break; + } + ctrl += 1; + Check = 0; + break; + + default: + Check = 1; + break; + } + if (Check == 1) { + if (ctrl != NULL) { ctrl += 1; } - continue; - } - goto try_next; - } + continue; + } + goto try_next; + } } /*---------------------------------------------------*/ diff --git a/bsp_z7/ps7_cortexa9_0/include/xil_printf.h b/bsp_z7/ps7_cortexa9_0/include/xil_printf.h index 4906e2a..c69af0f 100644 --- a/bsp_z7/ps7_cortexa9_0/include/xil_printf.h +++ b/bsp_z7/ps7_cortexa9_0/include/xil_printf.h @@ -1,5 +1,6 @@ /****************************************************************************** -* Copyright (c) 1995 - 2021 Xilinx, Inc. All rights reserved. +* Copyright (C) 1995 - 2021 Xilinx, Inc. All rights reserved. +* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT *******************************************************************************/ #ifndef XIL_PRINTF_H @@ -13,8 +14,10 @@ extern "C" { #include #include #include "xil_types.h" -#include "xparameters.h" #include "bspconfig.h" +#ifndef SDT +#include "xparameters.h" +#endif #if defined (__aarch64__) && HYP_GUEST && EL1_NONSECURE && XEN_USE_PV_CONSOLE #include "xen_console.h" #endif @@ -38,13 +41,14 @@ struct params_s; typedef char8* charptr; typedef s32 (*func_ptr)(int c); -/* */ - +/************************** Function Prototypes ******************************/ +/**< prints the statement */ void xil_printf( const char8 *ctrl1, ...); +/**< This routine is equivalent to vprintf routine */ void xil_vprintf(const char8 *ctrl1, va_list argp); void print( const char8 *ptr); -extern void outbyte (uint8_t c); -extern char inbyte(void); +extern void outbyte (char c); /**< To send byte */ +extern char inbyte(void); /**< To receive byte */ #ifdef __cplusplus } diff --git a/bsp_z7/ps7_cortexa9_0/include/xil_sleepcommon.c b/bsp_z7/ps7_cortexa9_0/include/xil_sleepcommon.c index aba3a08..f4322db 100644 --- a/bsp_z7/ps7_cortexa9_0/include/xil_sleepcommon.c +++ b/bsp_z7/ps7_cortexa9_0/include/xil_sleepcommon.c @@ -1,5 +1,6 @@ /****************************************************************************** * Copyright (c) 2017 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -21,6 +22,7 @@ * violation. * 8.0 sk 03/02/22 Update usleep argument type to fix misra_c_2012_ * directive_4_6 violation. +* 9.1 mus 10/24/23 Add support for RISC-V. * ******************************************************************************/ @@ -52,6 +54,8 @@ sleep_A53(seconds); #elif defined (__MICROBLAZE__) sleep_MB(seconds); +#elif defined (__riscv) + sleep_riscv(seconds); #else sleep_A9(seconds); #endif @@ -78,6 +82,8 @@ usleep_A53(useconds); #elif defined (__MICROBLAZE__) usleep_MB(useconds); +#elif defined (__riscv) + usleep_riscv(useconds); #else usleep_A9(useconds); #endif diff --git a/bsp_z7/ps7_cortexa9_0/include/xil_sleeptimer.h b/bsp_z7/ps7_cortexa9_0/include/xil_sleeptimer.h index b133eaf..adcb7e6 100644 --- a/bsp_z7/ps7_cortexa9_0/include/xil_sleeptimer.h +++ b/bsp_z7/ps7_cortexa9_0/include/xil_sleeptimer.h @@ -1,5 +1,6 @@ /****************************************************************************** -* Copyright (c) 2017 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (C) 2017 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -24,7 +25,7 @@ * misra_c_2012_rule_12_1 violation. * 7.7 sk 01/10/22 Add void to XTime_StartTTCTimer function declaration * to fix misra_c_2012_rule_8_2 violation. -* +* 9.0 ml 03/03/23 Add description to fix doxygen warnings. * *****************************************************************************/ @@ -103,8 +104,12 @@ extern "C" { */ /************************** Function Prototypes ******************************/ +/**< This is a helper function used by sleep/usleep APIs to +* have delay in sec/usec */ void Xil_SleepTTCCommon(u32 delay, u64 frequency); -void XTime_StartTTCTimer(void); + +void XTime_StartTTCTimer(void); /**< This API starts the Triple + * Timer Counter */ #endif diff --git a/bsp_z7/ps7_cortexa9_0/include/xil_spinlock.h b/bsp_z7/ps7_cortexa9_0/include/xil_spinlock.h index 0cdf288..b61d7d3 100644 --- a/bsp_z7/ps7_cortexa9_0/include/xil_spinlock.h +++ b/bsp_z7/ps7_cortexa9_0/include/xil_spinlock.h @@ -1,5 +1,6 @@ /****************************************************************************** -* Copyright (c) 2021 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (C) 2021 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -23,12 +24,13 @@ * if condition to fix misrac violations. * 7.7 sk 01/10/22 Update XIL_SPINLOCK_ENABLED from signed to unsigned to * fix misra_c_2012_rule_10_4 violation. +* 9.0 ml 03/03/23 Add description to fix doxygen warnings. * * ******************************************************************************/ -#ifndef XIL_SPINLOCK_H /* prevent circular inclusions */ -#define XIL_SPINLOCK_H /* by using protection macros */ +#ifndef XIL_SPINLOCK_H /**< prevent circular inclusions */ +#define XIL_SPINLOCK_H /**< by using protection macros */ /***************************** Include Files ********************************/ #include "xil_types.h" @@ -61,7 +63,8 @@ u32 Xil_IsSpinLockEnabled(void); if(Xil_IsSpinLockEnabled()!=(u32)0) { \ Xil_SpinLock(); } #else -#define XIL_SPINLOCK() +#define XIL_SPINLOCK() /**< protect multiple applications running at separate + * CPUs to write to the same register */ #endif /* !(__aarch64__) && (__GNUC__) && !(__clang__)*/ #if !defined (__aarch64__) && defined(__GNUC__) && !defined(__clang__) @@ -69,7 +72,7 @@ u32 Xil_IsSpinLockEnabled(void); if(Xil_IsSpinLockEnabled()!=(u32)0) { \ Xil_SpinUnlock(); } #else -#define XIL_SPINUNLOCK() +#define XIL_SPINUNLOCK() /**< Release the lock previously taken */ #endif /* !(__aarch64__) && (__GNUC__) && !(__clang__)*/ diff --git a/bsp_z7/ps7_cortexa9_0/include/xil_testio.c b/bsp_z7/ps7_cortexa9_0/include/xil_testio.c index c05acd9..0fe1204 100644 --- a/bsp_z7/ps7_cortexa9_0/include/xil_testio.c +++ b/bsp_z7/ps7_cortexa9_0/include/xil_testio.c @@ -1,5 +1,6 @@ /****************************************************************************** * Copyright (c) 2009 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -16,6 +17,7 @@ * Ver Who Date Changes * ----- ---- -------- ----------------------------------------------- * 1.00a hbm 08/25/09 First release +* 9.00 ml 04/26/23 Updated code to fix sizeof_mismatch coverity warnings. * * *****************************************************************************/ @@ -90,9 +92,9 @@ s32 Xil_TestIO8(u8 *Addr, s32 Length, u8 Value) s32 Status = 0; for (Index = 0; Index < Length; Index++) { - Xil_Out8((INTPTR)Addr, Value); + Xil_Out8((UINTPTR)Addr, Value); - ValueIn = Xil_In8((INTPTR)Addr); + ValueIn = Xil_In8((UINTPTR)Addr); if ((Value != ValueIn) && (Status == 0)) { Status = -1; @@ -134,23 +136,24 @@ s32 Xil_TestIO16(u16 *Addr, s32 Length, u16 Value, s32 Kind, s32 Swap) u16 *TempAddr16; u16 ValueIn = 0U; s32 Index; + u32 Size_16; TempAddr16 = Addr; Xil_AssertNonvoid(TempAddr16 != NULL); for (Index = 0; Index < Length; Index++) { switch (Kind) { - case XIL_TESTIO_LE: - Xil_Out16LE((INTPTR)TempAddr16, Value); - break; - case XIL_TESTIO_BE: - Xil_Out16BE((INTPTR)TempAddr16, Value); - break; - default: - Xil_Out16((INTPTR)TempAddr16, Value); - break; + case XIL_TESTIO_LE: + Xil_Out16LE((UINTPTR)TempAddr16, Value); + break; + case XIL_TESTIO_BE: + Xil_Out16BE((UINTPTR)TempAddr16, Value); + break; + default: + Xil_Out16((UINTPTR)TempAddr16, Value); + break; } - ValueIn = Xil_In16((INTPTR)TempAddr16); + ValueIn = Xil_In16((UINTPTR)TempAddr16); if ((Kind != 0) && (Swap != 0)) { ValueIn = Swap16(ValueIn); @@ -161,18 +164,18 @@ s32 Xil_TestIO16(u16 *Addr, s32 Length, u16 Value, s32 Kind, s32 Swap) } /* second round */ - Xil_Out16((INTPTR)TempAddr16, Value); + Xil_Out16((UINTPTR)TempAddr16, Value); switch (Kind) { - case XIL_TESTIO_LE: - ValueIn = Xil_In16LE((INTPTR)TempAddr16); - break; - case XIL_TESTIO_BE: - ValueIn = Xil_In16BE((INTPTR)TempAddr16); - break; - default: - ValueIn = Xil_In16((INTPTR)TempAddr16); - break; + case XIL_TESTIO_LE: + ValueIn = Xil_In16LE((UINTPTR)TempAddr16); + break; + case XIL_TESTIO_BE: + ValueIn = Xil_In16BE((UINTPTR)TempAddr16); + break; + default: + ValueIn = Xil_In16((UINTPTR)TempAddr16); + break; } @@ -183,7 +186,8 @@ s32 Xil_TestIO16(u16 *Addr, s32 Length, u16 Value, s32 Kind, s32 Swap) if (Value != ValueIn) { return -1; } - TempAddr16 += sizeof(u16); + Size_16 = sizeof(u16); + TempAddr16 += Size_16; } return 0; } @@ -218,23 +222,24 @@ s32 Xil_TestIO32(u32 *Addr, s32 Length, u32 Value, s32 Kind, s32 Swap) u32 *TempAddr; u32 ValueIn = 0U; s32 Index; + u32 Size_32; TempAddr = Addr; Xil_AssertNonvoid(TempAddr != NULL); for (Index = 0; Index < Length; Index++) { switch (Kind) { - case XIL_TESTIO_LE: - Xil_Out32LE((INTPTR)TempAddr, Value); - break; - case XIL_TESTIO_BE: - Xil_Out32BE((INTPTR)TempAddr, Value); - break; - default: - Xil_Out32((INTPTR)TempAddr, Value); - break; + case XIL_TESTIO_LE: + Xil_Out32LE((UINTPTR)TempAddr, Value); + break; + case XIL_TESTIO_BE: + Xil_Out32BE((UINTPTR)TempAddr, Value); + break; + default: + Xil_Out32((UINTPTR)TempAddr, Value); + break; } - ValueIn = Xil_In32((INTPTR)TempAddr); + ValueIn = Xil_In32((UINTPTR)TempAddr); if ((Kind != 0) && (Swap != 0)) { ValueIn = Swap32(ValueIn); @@ -245,19 +250,19 @@ s32 Xil_TestIO32(u32 *Addr, s32 Length, u32 Value, s32 Kind, s32 Swap) } /* second round */ - Xil_Out32((INTPTR)TempAddr, Value); + Xil_Out32((UINTPTR)TempAddr, Value); switch (Kind) { - case XIL_TESTIO_LE: - ValueIn = Xil_In32LE((INTPTR)TempAddr); - break; - case XIL_TESTIO_BE: - ValueIn = Xil_In32BE((INTPTR)TempAddr); - break; - default: - ValueIn = Xil_In32((INTPTR)TempAddr); - break; + case XIL_TESTIO_LE: + ValueIn = Xil_In32LE((UINTPTR)TempAddr); + break; + case XIL_TESTIO_BE: + ValueIn = Xil_In32BE((UINTPTR)TempAddr); + break; + default: + ValueIn = Xil_In32((UINTPTR)TempAddr); + break; } if ((Kind != 0) && (Swap != 0)) { @@ -267,7 +272,8 @@ s32 Xil_TestIO32(u32 *Addr, s32 Length, u32 Value, s32 Kind, s32 Swap) if (Value != ValueIn) { return -1; } - TempAddr += sizeof(u32); + Size_32 = sizeof(u32); + TempAddr += Size_32; } return 0; } diff --git a/bsp_z7/ps7_cortexa9_0/include/xil_testmem.c b/bsp_z7/ps7_cortexa9_0/include/xil_testmem.c index aaa0617..7c35553 100644 --- a/bsp_z7/ps7_cortexa9_0/include/xil_testmem.c +++ b/bsp_z7/ps7_cortexa9_0/include/xil_testmem.c @@ -1,5 +1,6 @@ /****************************************************************************** * Copyright (c) 2009 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (C) 2022 - 2024 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -34,6 +35,10 @@ * 21_2 violation. * 7.7 sk 01/10/22 Remove arithematic operations on pointer varaible to fix * misra_c_2012_rule_18_4 violation. +* 9.0 ml 08/30/23 Update Memory tests API in BSP, to not to stress test by + default. +* 9.1 ml 02/02/23 Fix compilation warnings report with +* XIL_ENABLE_MEMORY_STRESS_TEST * * *****************************************************************************/ @@ -46,7 +51,9 @@ /************************** Constant Definitions ****************************/ /************************** Function Prototypes *****************************/ +#ifdef XIL_ENABLE_MEMORY_STRESS_TEST static u32 RotateLeft(u32 Input, u8 Width); +#endif /* define ROTATE_RIGHT to give access to this functionality */ #ifdef ROTATE_RIGHT @@ -86,11 +93,15 @@ static u32 RotateRight(u32 Input, u8 Width); s32 Xil_TestMem8(u32 Addrlow, u32 Addrhigh, u32 Words, u8 Pattern, u8 Subtest) { u32 I; - u32 j; u8 Val; u8 WordMem8; s32 Status = 0; u64 Addr = (Addrlow + ((u64)Addrhigh << 32)); +#ifdef XIL_ENABLE_MEMORY_STRESS_TEST + u32 j; +#else + (void)Pattern; +#endif Xil_AssertNonvoid(Words != (u32)0); Xil_AssertNonvoid(Subtest <= XIL_TESTMEM_MAXTEST); @@ -104,14 +115,14 @@ s32 Xil_TestMem8(u32 Addrlow, u32 Addrhigh, u32 Words, u8 Pattern, u8 Subtest) * select the proper Subtest(s) */ - if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) { + if ((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) { /* * Fill the memory with incrementing * values starting from XIL_TESTMEM_INIT_VALUE */ for (I = 0U; I < Words; I++) { /* write memory location */ - sbea(Addr+I, Val); + sbea(Addr + I, Val); Val++; } /* @@ -128,7 +139,7 @@ s32 Xil_TestMem8(u32 Addrlow, u32 Addrhigh, u32 Words, u8 Pattern, u8 Subtest) for (I = 0U; I < Words; I++) { /* read memory location */ - WordMem8 = lbuea(Addr+I); + WordMem8 = lbuea(Addr + I); if (WordMem8 != Val) { Status = -1; goto End_Label; @@ -136,8 +147,8 @@ s32 Xil_TestMem8(u32 Addrlow, u32 Addrhigh, u32 Words, u8 Pattern, u8 Subtest) Val++; } } - - if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) { +#ifdef XIL_ENABLE_MEMORY_STRESS_TEST + if ((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) { /* * set up to cycle through all possible initial * test Patterns for walking ones test @@ -155,7 +166,7 @@ s32 Xil_TestMem8(u32 Addrlow, u32 Addrhigh, u32 Words, u8 Pattern, u8 Subtest) */ for (I = 0U; I < NUM_OF_BITS_IN_BYTE; I++) { /* write memory location */ - sbea(Addr+I, Val); + sbea(Addr + I, Val); Val = (u8)RotateLeft(Val, 8U); } /* @@ -166,7 +177,7 @@ s32 Xil_TestMem8(u32 Addrlow, u32 Addrhigh, u32 Words, u8 Pattern, u8 Subtest) /* Read the values from each location that was written */ for (I = 0U; I < NUM_OF_BITS_IN_BYTE; I++) { /* read memory location */ - WordMem8 = lbuea(Addr+I); + WordMem8 = lbuea(Addr + I); if (WordMem8 != Val) { Status = -1; goto End_Label; @@ -176,7 +187,7 @@ s32 Xil_TestMem8(u32 Addrlow, u32 Addrhigh, u32 Words, u8 Pattern, u8 Subtest) } } - if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) { + if ((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) { /* * set up to cycle through all possible initial test * Patterns for walking zeros test @@ -194,7 +205,7 @@ s32 Xil_TestMem8(u32 Addrlow, u32 Addrhigh, u32 Words, u8 Pattern, u8 Subtest) */ for (I = 0U; I < NUM_OF_BITS_IN_BYTE; I++) { /* write memory location */ - sbea(Addr+I, Val); + sbea(Addr + I, Val); Val = ~((u8)RotateLeft(~Val, NUM_OF_BITS_IN_BYTE)); } /* @@ -205,7 +216,7 @@ s32 Xil_TestMem8(u32 Addrlow, u32 Addrhigh, u32 Words, u8 Pattern, u8 Subtest) /* Read the values from each location that was written */ for (I = 0U; I < NUM_OF_BITS_IN_BYTE; I++) { /* read memory location */ - WordMem8 = lbuea(Addr+I); + WordMem8 = lbuea(Addr + I); if (WordMem8 != Val) { Status = -1; goto End_Label; @@ -216,12 +227,12 @@ s32 Xil_TestMem8(u32 Addrlow, u32 Addrhigh, u32 Words, u8 Pattern, u8 Subtest) } } - if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) { + if ((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) { /* Fill the memory with inverse of address */ for (I = 0U; I < Words; I++) { /* write memory location */ Val = (u8) (~((INTPTR) (Addr + I))); - sbea(Addr+I, Val); + sbea(Addr + I, Val); } /* @@ -231,8 +242,8 @@ s32 Xil_TestMem8(u32 Addrlow, u32 Addrhigh, u32 Words, u8 Pattern, u8 Subtest) for (I = 0U; I < Words; I++) { /* read memory location */ - WordMem8 = lbuea(Addr+I); - Val = (u8) (~((INTPTR) (Addr+I))); + WordMem8 = lbuea(Addr + I); + Val = (u8) (~((INTPTR) (Addr + I))); if ((WordMem8 ^ Val) != 0x00U) { Status = -1; goto End_Label; @@ -240,7 +251,7 @@ s32 Xil_TestMem8(u32 Addrlow, u32 Addrhigh, u32 Words, u8 Pattern, u8 Subtest) } } - if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) { + if ((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) { /* * Generate an initial value for * memory testing @@ -248,8 +259,7 @@ s32 Xil_TestMem8(u32 Addrlow, u32 Addrhigh, u32 Words, u8 Pattern, u8 Subtest) if (Pattern == (u8)0) { Val = 0xA5U; - } - else { + } else { Val = Pattern; } /* @@ -257,7 +267,7 @@ s32 Xil_TestMem8(u32 Addrlow, u32 Addrhigh, u32 Words, u8 Pattern, u8 Subtest) */ for (I = 0U; I < Words; I++) { /* write memory location */ - sbea(Addr+I, Val); + sbea(Addr + I, Val); } /* * Check every word within the words @@ -267,14 +277,14 @@ s32 Xil_TestMem8(u32 Addrlow, u32 Addrhigh, u32 Words, u8 Pattern, u8 Subtest) for (I = 0U; I < Words; I++) { /* read memory location */ - WordMem8 = lbuea(Addr+I); + WordMem8 = lbuea(Addr + I); if (WordMem8 != Val) { Status = -1; goto End_Label; } } } - +#endif End_Label: return Status; } @@ -308,14 +318,18 @@ End_Label: * patterns used not to repeat over the region tested. * *****************************************************************************/ -s32 Xil_TestMem16(u32 Addrlow,u32 Addrhigh, u32 Words, u16 Pattern, u8 Subtest) +s32 Xil_TestMem16(u32 Addrlow, u32 Addrhigh, u32 Words, u16 Pattern, u8 Subtest) { u32 I; - u32 j; u16 Val; u16 WordMem16; s32 Status = 0; u64 Addr = (Addrlow + ((u64)Addrhigh << 32)); +#ifdef XIL_ENABLE_MEMORY_STRESS_TEST + u32 j; +#else + (void)Pattern; +#endif Xil_AssertNonvoid(Words != (u32)0); Xil_AssertNonvoid(Subtest <= XIL_TESTMEM_MAXTEST); @@ -329,14 +343,14 @@ s32 Xil_TestMem16(u32 Addrlow,u32 Addrhigh, u32 Words, u16 Pattern, u8 Subtest) * selectthe proper Subtest(s) */ - if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) { + if ((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) { /* * Fill the memory with incrementing * values starting from 'XIL_TESTMEM_INIT_VALUE' */ for (I = 0U; I < (NUM_OF_BYTES_IN_HW * Words);) { /* write memory location */ - shea(Addr+I, Val); + shea(Addr + I, Val); Val++; I = I + NUM_OF_BYTES_IN_HW; } @@ -355,7 +369,7 @@ s32 Xil_TestMem16(u32 Addrlow,u32 Addrhigh, u32 Words, u16 Pattern, u8 Subtest) for (I = 0U; I < (NUM_OF_BYTES_IN_HW * Words);) { /* read memory location */ - WordMem16 = lhuea(Addr+I); + WordMem16 = lhuea(Addr + I); if (WordMem16 != Val) { Status = -1; goto End_Label; @@ -364,8 +378,8 @@ s32 Xil_TestMem16(u32 Addrlow,u32 Addrhigh, u32 Words, u16 Pattern, u8 Subtest) I = I + NUM_OF_BYTES_IN_HW; } } - - if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) { +#ifdef XIL_ENABLE_MEMORY_STRESS_TEST + if ((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) { /* * set up to cycle through all possible initial test * Patterns for walking ones test @@ -385,7 +399,7 @@ s32 Xil_TestMem16(u32 Addrlow,u32 Addrhigh, u32 Words, u16 Pattern, u8 Subtest) for (I = 0U; I < (NUM_OF_BYTES_IN_HW * NUM_OF_BITS_IN_HW); ) { /* write memory location */ - shea(Addr+I,Val); + shea(Addr + I, Val); Val = (u16)RotateLeft(Val, 16U); I = I + NUM_OF_BYTES_IN_HW; } @@ -397,7 +411,7 @@ s32 Xil_TestMem16(u32 Addrlow,u32 Addrhigh, u32 Words, u16 Pattern, u8 Subtest) /* Read the values from each location that was written */ for (I = 0U; I < (NUM_OF_BYTES_IN_HW * NUM_OF_BITS_IN_HW); ) { /* read memory location */ - WordMem16 = lhuea(Addr+I); + WordMem16 = lhuea(Addr + I); if (WordMem16 != Val) { Status = -1; goto End_Label; @@ -408,7 +422,7 @@ s32 Xil_TestMem16(u32 Addrlow,u32 Addrhigh, u32 Words, u16 Pattern, u8 Subtest) } } - if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) { + if ((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) { /* * set up to cycle through all possible initial * test Patterns for walking zeros test @@ -428,7 +442,7 @@ s32 Xil_TestMem16(u32 Addrlow,u32 Addrhigh, u32 Words, u16 Pattern, u8 Subtest) */ for (I = 0U; I < (NUM_OF_BYTES_IN_HW * NUM_OF_BITS_IN_HW);) { - shea(Addr+I, Val); + shea(Addr + I, Val); Val = ~((u16)RotateLeft(~Val, 16U)); I = I + NUM_OF_BYTES_IN_HW; } @@ -439,7 +453,7 @@ s32 Xil_TestMem16(u32 Addrlow,u32 Addrhigh, u32 Words, u16 Pattern, u8 Subtest) Val = ~(1U << j); /* Read the values from each location that was written */ for (I = 0U; I < (NUM_OF_BYTES_IN_HW * NUM_OF_BITS_IN_HW); ) { - WordMem16= lhuea(Addr+I); + WordMem16 = lhuea(Addr + I); if (WordMem16 != Val) { Status = -1; goto End_Label; @@ -451,12 +465,12 @@ s32 Xil_TestMem16(u32 Addrlow,u32 Addrhigh, u32 Words, u16 Pattern, u8 Subtest) } } - if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) { + if ((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) { /* Fill the memory with inverse of address */ for (I = 0U; I < (NUM_OF_BYTES_IN_HW * Words);) { /* write memory location */ - Val = (u16) (~((INTPTR)((Addr+I)))); - shea(Addr+I, Val); + Val = (u16) (~((INTPTR)((Addr + I)))); + shea(Addr + I, Val); I = I + NUM_OF_BYTES_IN_HW; } /* @@ -464,10 +478,10 @@ s32 Xil_TestMem16(u32 Addrlow,u32 Addrhigh, u32 Words, u16 Pattern, u8 Subtest) * of tested memory */ - for (I = 0U; I < (NUM_OF_BYTES_IN_HW*Words); ) { + for (I = 0U; I < (NUM_OF_BYTES_IN_HW * Words); ) { /* read memory location */ - WordMem16 = lhuea(Addr+I); - Val = (u16) (~((INTPTR) ((Addr+I)))); + WordMem16 = lhuea(Addr + I); + Val = (u16) (~((INTPTR) ((Addr + I)))); if ((WordMem16 ^ Val) != 0x0000U) { Status = -1; goto End_Label; @@ -476,15 +490,14 @@ s32 Xil_TestMem16(u32 Addrlow,u32 Addrhigh, u32 Words, u16 Pattern, u8 Subtest) } } - if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) { + if ((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) { /* * Generate an initial value for * memory testing */ if (Pattern == (u16)0) { Val = 0xDEADU; - } - else { + } else { Val = Pattern; } @@ -492,9 +505,9 @@ s32 Xil_TestMem16(u32 Addrlow,u32 Addrhigh, u32 Words, u16 Pattern, u8 Subtest) * Fill the memory with fixed pattern */ - for (I = 0U; I < (2*Words);) { + for (I = 0U; I < (2 * Words);) { /* write memory location */ - shea(Addr+I, Val); + shea(Addr + I, Val); I = I + NUM_OF_BYTES_IN_HW; } @@ -506,7 +519,7 @@ s32 Xil_TestMem16(u32 Addrlow,u32 Addrhigh, u32 Words, u16 Pattern, u8 Subtest) for (I = 0U; I < (NUM_OF_BYTES_IN_HW * Words);) { /* read memory location */ - WordMem16=lhuea(Addr+I); + WordMem16 = lhuea(Addr + I); if (WordMem16 != Val) { Status = -1; goto End_Label; @@ -514,6 +527,7 @@ s32 Xil_TestMem16(u32 Addrlow,u32 Addrhigh, u32 Words, u16 Pattern, u8 Subtest) I = I + NUM_OF_BYTES_IN_HW; } } +#endif End_Label: return Status; } @@ -549,11 +563,15 @@ End_Label: s32 Xil_TestMem32(u32 Addrlow, u32 Addrhigh, u32 Words, u32 Pattern, u8 Subtest) { u32 I; - u32 j; u32 Val; u32 WordMem32; s32 Status = 0; u64 Addr = (Addrlow + ((u64)Addrhigh << 32)); +#ifdef XIL_ENABLE_MEMORY_STRESS_TEST + u32 j; +#else + (void)Pattern; +#endif Xil_AssertNonvoid(Words != (u32)0); Xil_AssertNonvoid(Subtest <= (u8)XIL_TESTMEM_MAXTEST); @@ -564,13 +582,13 @@ s32 Xil_TestMem32(u32 Addrlow, u32 Addrhigh, u32 Words, u32 Pattern, u8 Subtest) Val = XIL_TESTMEM_INIT_VALUE; - if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) { + if ((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) { /* * Fill the memory with incrementing * values starting from 'XIL_TESTMEM_INIT_VALUE' */ - for (I = 0U; I <(NUM_OF_BYTES_IN_WORD * Words);) { - swea(Addr+I, Val); + for (I = 0U; I < (NUM_OF_BYTES_IN_WORD * Words);) { + swea(Addr + I, Val); Val++; I = I + NUM_OF_BYTES_IN_WORD; } @@ -589,7 +607,7 @@ s32 Xil_TestMem32(u32 Addrlow, u32 Addrhigh, u32 Words, u32 Pattern, u8 Subtest) */ for (I = 0U; I < ( NUM_OF_BYTES_IN_WORD * Words);) { - WordMem32 = lwea(Addr+I); + WordMem32 = lwea(Addr + I); if (WordMem32 != Val) { Status = -1; @@ -600,8 +618,8 @@ s32 Xil_TestMem32(u32 Addrlow, u32 Addrhigh, u32 Words, u32 Pattern, u8 Subtest) I = I + NUM_OF_BYTES_IN_WORD; } } - - if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) { +#ifdef XIL_ENABLE_MEMORY_STRESS_TEST + if ((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) { /* * set up to cycle through all possible initial * test Patterns for walking ones test @@ -622,7 +640,7 @@ s32 Xil_TestMem32(u32 Addrlow, u32 Addrhigh, u32 Words, u32 Pattern, u8 Subtest) for (I = 0U; I < (NUM_OF_BYTES_IN_WORD * NUM_OF_BITS_IN_WORD);) { /* write memory location */ - swea(Addr+I, Val); + swea(Addr + I, Val); Val = (u32) RotateLeft(Val, NUM_OF_BITS_IN_WORD); I = I + NUM_OF_BYTES_IN_WORD; } @@ -638,7 +656,7 @@ s32 Xil_TestMem32(u32 Addrlow, u32 Addrhigh, u32 Words, u32 Pattern, u8 Subtest) for (I = 0U; I < ((u32)32 * NUM_OF_BYTES_IN_WORD);) { /* read memory location */ - WordMem32 = lwea(Addr+I); + WordMem32 = lwea(Addr + I); if (WordMem32 != Val) { Status = -1; @@ -651,7 +669,7 @@ s32 Xil_TestMem32(u32 Addrlow, u32 Addrhigh, u32 Words, u32 Pattern, u8 Subtest) } } - if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) { + if ((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) { /* * set up to cycle through all possible * initial test Patterns for walking zeros test @@ -673,7 +691,7 @@ s32 Xil_TestMem32(u32 Addrlow, u32 Addrhigh, u32 Words, u32 Pattern, u8 Subtest) for (I = 0U; I < (NUM_OF_BITS_IN_WORD * NUM_OF_BYTES_IN_WORD);) { /* write memory location */ - swea(Addr+I, Val); + swea(Addr + I, Val); Val = ~((u32)RotateLeft(~Val, NUM_OF_BITS_IN_WORD)); I = I + NUM_OF_BYTES_IN_WORD; } @@ -689,7 +707,7 @@ s32 Xil_TestMem32(u32 Addrlow, u32 Addrhigh, u32 Words, u32 Pattern, u8 Subtest) * written */ for (I = 0U; I < (NUM_OF_BITS_IN_WORD * NUM_OF_BYTES_IN_WORD);) { /* read memory location */ - WordMem32 = lwea(Addr+I); + WordMem32 = lwea(Addr + I); if (WordMem32 != Val) { Status = -1; goto End_Label; @@ -701,12 +719,12 @@ s32 Xil_TestMem32(u32 Addrlow, u32 Addrhigh, u32 Words, u32 Pattern, u8 Subtest) } } - if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) { + if ((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) { /* Fill the memory with inverse of address */ for (I = 0U; I < (NUM_OF_BYTES_IN_WORD * Words);) { /* write memory location */ - Val = (u32) (~((INTPTR) (Addr+I))); - swea(Addr+I, Val); + Val = (u32) (~((INTPTR) (Addr + I))); + swea(Addr + I, Val); I = I + NUM_OF_BYTES_IN_WORD; } @@ -717,8 +735,8 @@ s32 Xil_TestMem32(u32 Addrlow, u32 Addrhigh, u32 Words, u32 Pattern, u8 Subtest) for (I = 0U; I < (NUM_OF_BYTES_IN_WORD * Words);) { /* Read the location */ - WordMem32 = lwea(Addr+I); - Val = (u32) (~((INTPTR) (Addr+I))); + WordMem32 = lwea(Addr + I); + Val = (u32) (~((INTPTR) (Addr + I))); if ((WordMem32 ^ Val) != 0x00000000U) { Status = -1; @@ -728,7 +746,7 @@ s32 Xil_TestMem32(u32 Addrlow, u32 Addrhigh, u32 Words, u32 Pattern, u8 Subtest) } } - if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) { + if ((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) { /* * Generate an initial value for * memory testing @@ -736,8 +754,7 @@ s32 Xil_TestMem32(u32 Addrlow, u32 Addrhigh, u32 Words, u32 Pattern, u8 Subtest) if (Pattern == (u32)0) { Val = 0xDEADBEEFU; - } - else { + } else { Val = Pattern; } @@ -747,7 +764,7 @@ s32 Xil_TestMem32(u32 Addrlow, u32 Addrhigh, u32 Words, u32 Pattern, u8 Subtest) for (I = 0U; I < (NUM_OF_BYTES_IN_WORD * Words);) { /* write memory location */ - swea(Addr+I, Val); + swea(Addr + I, Val); I = I + NUM_OF_BYTES_IN_WORD; } @@ -761,7 +778,7 @@ s32 Xil_TestMem32(u32 Addrlow, u32 Addrhigh, u32 Words, u32 Pattern, u8 Subtest) /* read memory location */ - WordMem32 = lwea(Addr+I); + WordMem32 = lwea(Addr + I); if (WordMem32 != Val) { Status = -1; goto End_Label; @@ -769,7 +786,7 @@ s32 Xil_TestMem32(u32 Addrlow, u32 Addrhigh, u32 Words, u32 Pattern, u8 Subtest) I = I + NUM_OF_BYTES_IN_WORD; } } - +#endif End_Label: return Status; } @@ -805,11 +822,15 @@ End_Label: s32 Xil_TestMem32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest) { u32 i; - u32 j; u32 Val; u32 FirtVal; u32 WordMem32; s32 Status = 0; +#ifdef XIL_ENABLE_MEMORY_STRESS_TEST + u32 j; +#else + (void)Pattern; +#endif Xil_AssertNonvoid(Words != (u32)0); Xil_AssertNonvoid(Subtest <= (u8)XIL_TESTMEM_MAXTEST); @@ -821,7 +842,7 @@ s32 Xil_TestMem32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest) FirtVal = XIL_TESTMEM_INIT_VALUE; - if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) { + if ((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) { /* * Fill the memory with incrementing * values starting from 'FirtVal' @@ -855,8 +876,8 @@ s32 Xil_TestMem32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest) Val++; } } - - if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) { +#ifdef XIL_ENABLE_MEMORY_STRESS_TEST + if ((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) { /* * set up to cycle through all possible initial * test Patterns for walking ones test @@ -904,7 +925,7 @@ s32 Xil_TestMem32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest) } } - if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) { + if ((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) { /* * set up to cycle through all possible * initial test Patterns for walking zeros test @@ -952,7 +973,7 @@ s32 Xil_TestMem32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest) } } - if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) { + if ((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) { /* Fill the memory with inverse of address */ for (i = 0U; i < Words; i++) { /* write memory location */ @@ -977,7 +998,7 @@ s32 Xil_TestMem32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest) } } - if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) { + if ((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) { /* * Generate an initial value for * memory testing @@ -985,8 +1006,7 @@ s32 Xil_TestMem32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest) if (Pattern == (u32)0) { Val = 0xDEADBEEFU; - } - else { + } else { Val = Pattern; } @@ -1016,7 +1036,7 @@ s32 Xil_TestMem32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest) } } } - +#endif End_Label: return Status; } @@ -1051,11 +1071,15 @@ End_Label: s32 Xil_TestMem16(u16 *Addr, u32 Words, u16 Pattern, u8 Subtest) { u32 i; - u32 j; u16 Val; u16 FirtVal; u16 WordMem16; s32 Status = 0; +#ifdef XIL_ENABLE_MEMORY_STRESS_TEST + u32 j; +#else + (void)Pattern; +#endif Xil_AssertNonvoid(Words != (u32)0); Xil_AssertNonvoid(Subtest <= XIL_TESTMEM_MAXTEST); @@ -1070,7 +1094,7 @@ s32 Xil_TestMem16(u16 *Addr, u32 Words, u16 Pattern, u8 Subtest) * selectthe proper Subtest(s) */ - if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) { + if ((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) { /* * Fill the memory with incrementing * values starting from 'FirtVal' @@ -1102,8 +1126,8 @@ s32 Xil_TestMem16(u16 *Addr, u32 Words, u16 Pattern, u8 Subtest) Val++; } } - - if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) { +#ifdef XIL_ENABLE_MEMORY_STRESS_TEST + if ((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) { /* * set up to cycle through all possible initial test * Patterns for walking ones test @@ -1144,7 +1168,7 @@ s32 Xil_TestMem16(u16 *Addr, u32 Words, u16 Pattern, u8 Subtest) } } - if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) { + if ((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) { /* * set up to cycle through all possible initial * test Patterns for walking zeros test @@ -1187,7 +1211,7 @@ s32 Xil_TestMem16(u16 *Addr, u32 Words, u16 Pattern, u8 Subtest) } } - if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) { + if ((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) { /* Fill the memory with inverse of address */ for (i = 0U; i < Words; i++) { /* write memory location */ @@ -1210,15 +1234,14 @@ s32 Xil_TestMem16(u16 *Addr, u32 Words, u16 Pattern, u8 Subtest) } } - if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) { + if ((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) { /* * Generate an initial value for * memory testing */ if (Pattern == (u16)0) { Val = 0xDEADU; - } - else { + } else { Val = Pattern; } @@ -1246,7 +1269,7 @@ s32 Xil_TestMem16(u16 *Addr, u32 Words, u16 Pattern, u8 Subtest) } } } - +#endif End_Label: return Status; } @@ -1282,11 +1305,15 @@ End_Label: s32 Xil_TestMem8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest) { u32 i; - u32 j; u8 Val; u8 FirtVal; u8 WordMem8; s32 Status = 0; +#ifdef XIL_ENABLE_MEMORY_STRESS_TEST + u32 j; +#else + (void)Pattern; +#endif Xil_AssertNonvoid(Words != (u32)0); Xil_AssertNonvoid(Subtest <= XIL_TESTMEM_MAXTEST); @@ -1301,7 +1328,7 @@ s32 Xil_TestMem8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest) * select the proper Subtest(s) */ - if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) { + if ((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) { /* * Fill the memory with incrementing * values starting from 'FirtVal' @@ -1333,8 +1360,8 @@ s32 Xil_TestMem8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest) Val++; } } - - if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) { +#ifdef XIL_ENABLE_MEMORY_STRESS_TEST + if ((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) { /* * set up to cycle through all possible initial * test Patterns for walking ones test @@ -1373,7 +1400,7 @@ s32 Xil_TestMem8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest) } } - if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) { + if ((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) { /* * set up to cycle through all possible initial test * Patterns for walking zeros test @@ -1413,7 +1440,7 @@ s32 Xil_TestMem8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest) } } - if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) { + if ((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) { /* Fill the memory with inverse of address */ for (i = 0U; i < Words; i++) { /* write memory location */ @@ -1437,7 +1464,7 @@ s32 Xil_TestMem8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest) } } - if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) { + if ((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) { /* * Generate an initial value for * memory testing @@ -1445,8 +1472,7 @@ s32 Xil_TestMem8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest) if (Pattern == (u8)0) { Val = 0xA5U; - } - else { + } else { Val = Pattern; } /* @@ -1471,7 +1497,7 @@ s32 Xil_TestMem8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest) } } } - +#endif End_Label: return Status; } @@ -1489,6 +1515,7 @@ End_Label: * * *****************************************************************************/ +#ifdef XIL_ENABLE_MEMORY_STRESS_TEST static u32 RotateLeft(u32 Input, u8 Width) { u32 Msb; @@ -1524,6 +1551,7 @@ static u32 RotateLeft(u32 Input, u8 Width) return ReturnVal; } +#endif #ifdef ROTATE_RIGHT /*****************************************************************************/ diff --git a/bsp_z7/ps7_cortexa9_0/include/xil_testmem.h b/bsp_z7/ps7_cortexa9_0/include/xil_testmem.h index 7e29233..9fddbc5 100644 --- a/bsp_z7/ps7_cortexa9_0/include/xil_testmem.h +++ b/bsp_z7/ps7_cortexa9_0/include/xil_testmem.h @@ -1,5 +1,6 @@ /****************************************************************************** * Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved. +* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -103,7 +104,10 @@ extern "C" { /***************************** Include Files *********************************/ #include "xil_types.h" +#include "bspconfig.h" +#ifndef SDT #include "xparameters.h" +#endif /************************** Constant Definitions *****************************/ diff --git a/bsp_z7/ps7_cortexa9_0/include/xil_types.h b/bsp_z7/ps7_cortexa9_0/include/xil_types.h index 100bddd..4c37fbc 100644 --- a/bsp_z7/ps7_cortexa9_0/include/xil_types.h +++ b/bsp_z7/ps7_cortexa9_0/include/xil_types.h @@ -1,6 +1,6 @@ /****************************************************************************** * Copyright (c) 2010 - 2021 Xilinx, Inc. All rights reserved. -* Copyright (c) 2022 Advanced Micro Devices, Inc. All Rights Reserved. +* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -27,8 +27,9 @@ * 7.00 mus 01/07/19 Add cpp extern macro * 7.1 aru 08/19/19 Shift the value in UPPER_32_BITS only if it * is 64-bit processor -* 8.1 dp 12/23/22 Updated UINTPTR and INTPTR to point to 64bit data types +* 8.1 dp 12/23/22 Updated UINTPTR and INTPTR to point to 64bit data types * incase of microblaze 32-bit with extended address enabled +* 9.0 ml 14/04/23 Add parenthesis on sub-expression to fix misra-c violation. * * ******************************************************************************/ @@ -45,7 +46,10 @@ extern "C" { #include #include +#include "bspconfig.h" +#ifndef SDT #include "xparameters.h" +#endif /************************** Constant Definitions *****************************/ @@ -163,6 +167,10 @@ typedef void (*XInterruptHandler) (void *InstancePtr); */ typedef void (*XExceptionHandler) (void *InstancePtr); +#if defined (__riscv_xlen) && (__riscv_xlen == 64) +#define __arch64__ +#endif + /** * @brief Returns 32-63 bits of a number. * @param n : Number being accessed. diff --git a/bsp_z7/ps7_cortexa9_0/include/xil_util.c b/bsp_z7/ps7_cortexa9_0/include/xil_util.c index b056c3c..7e9f2b5 100644 --- a/bsp_z7/ps7_cortexa9_0/include/xil_util.c +++ b/bsp_z7/ps7_cortexa9_0/include/xil_util.c @@ -1,7 +1,7 @@ /******************************************************************************/ /** -* Copyright (c) 2019 - 2022 Xilinx, Inc. All rights reserved. -* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved. +* Copyright (C) 2019 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (C) 2022 - 2024 Advanced Micro Devices, Inc. All rights reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -85,6 +85,12 @@ * 8.1 sa 10/20/22 Change the type of first argument passed to Xil_WaitForEvents * API from u32 to UINTPTR for supporting 64 bit addressing. * 8.1 akm 01/02/23 Added Xil_RegisterPlmHandler() & Xil_PlmStubHandler() APIs. +* 9.0 ml 03/03/23 Add description to fix doxygen warnings. +* 9.0 ml 04/26/23 Updated code to fix DC.STRING BUFFER and VARARGS coverity warnings. +* 9.0 ml 09/13/23 Replaced numerical types (int) with proper typedefs(s32) to +* fix MISRA-C violations for Rule 4.6 +* 9.1 kpt 02/21/24 Added Xil_SChangeEndiannessAndCpy function +* * * *****************************************************************************/ @@ -94,7 +100,7 @@ #include "sleep.h" /************************** Constant Definitions ****************************/ -#define MAX_NIBBLES 8U +#define MAX_NIBBLES 8U /**< maximum nibbles */ /************************** Function Prototypes *****************************/ void (*fptr)(void) = NULL; @@ -119,8 +125,7 @@ static size_t strnlen (const char *StartPtr, size_t StrSize) EndPtr = memchr(StartPtr, '\0', StrSize); if (EndPtr == NULL) { StrLen = StrSize; - } - else { + } else { StrLen = (size_t) (EndPtr - StartPtr); } @@ -140,13 +145,13 @@ static size_t strnlen (const char *StartPtr, size_t StrSize) *******************************************************************************/ s32 Xil_Ceil(float Value) { - s32 Result = Value; + s32 Result = Value; if (Value > Result) { - Result = Result + 1; - } + Result = Result + 1; + } - return Result; + return Result; } /****************************************************************************/ @@ -174,16 +179,13 @@ u32 Xil_ConvertCharToNibble(u8 InChar, u8 *Num) if ((InChar >= (u8)'0') && (InChar <= (u8)'9')) { *Num = InChar - (u8)'0'; Status = XST_SUCCESS; - } - else if ((InChar >= (u8)'a') && (InChar <= (u8)'f')) { + } else if ((InChar >= (u8)'a') && (InChar <= (u8)'f')) { *Num = InChar - (u8)'a' + 10U; Status = XST_SUCCESS; - } - else if ((InChar >= (u8)'A') && (InChar <= (u8)'F')) { + } else if ((InChar >= (u8)'A') && (InChar <= (u8)'F')) { *Num = InChar - (u8)'A' + 10U; Status = XST_SUCCESS; - } - else { + } else { Status = XST_FAILURE; } @@ -218,8 +220,8 @@ u32 Xil_ConvertStringToHex(const char *Str, u32 *buf, u8 Len) while (ConvertedLen < Len) { for (i = 0U; i < MAX_NIBBLES; i++) { Status = Xil_ConvertCharToNibble((u8)Str[ConvertedLen], - &Nibble[i]); - ConvertedLen = ConvertedLen +1U; + &Nibble[i]); + ConvertedLen = ConvertedLen + 1U; if (Status != XST_SUCCESS) { /* Error converting char to nibble */ goto END; @@ -227,9 +229,9 @@ u32 Xil_ConvertStringToHex(const char *Str, u32 *buf, u8 Len) } buf[index] = (((u32)Nibble[0] << (u8)28U) | ((u32)Nibble[1] << (u8)24U) | - ((u32)Nibble[2] << (u8)20U) | ((u32)Nibble[3] << (u8)16U) | - ((u32)Nibble[4] << (u8)12U) | ((u32)Nibble[5] << (u8)8U) | - ((u32)Nibble[6] << (u8)4U) | (u32)Nibble[7]); + ((u32)Nibble[2] << (u8)20U) | ((u32)Nibble[3] << (u8)16U) | + ((u32)Nibble[4] << (u8)12U) | ((u32)Nibble[5] << (u8)8U) | + ((u32)Nibble[6] << (u8)4U) | (u32)Nibble[7]); index++; } END: @@ -246,7 +248,8 @@ END: * @return None. * *****************************************************************************/ -void Xil_RegisterPlmHandler(void (*PlmAlive) (void)) { +void Xil_RegisterPlmHandler(void (*PlmAlive) (void)) +{ fptr = PlmAlive; } @@ -259,7 +262,8 @@ void Xil_RegisterPlmHandler(void (*PlmAlive) (void)) { * @return None. * *****************************************************************************/ -void Xil_PlmStubHandler(void) { +void Xil_PlmStubHandler(void) +{ if (fptr != NULL) { fptr(); } @@ -288,7 +292,7 @@ u32 Xil_WaitForEvent(UINTPTR RegAddr, u32 EventMask, u32 Event, u32 Timeout) u32 PollCount = Timeout; u32 Status = XST_FAILURE; - while(PollCount > 0U) { + while (PollCount > 0U) { EventStatus = Xil_In32(RegAddr) & EventMask; if (EventStatus == Event) { Status = XST_SUCCESS; @@ -323,7 +327,7 @@ u32 Xil_WaitForEvent(UINTPTR RegAddr, u32 EventMask, u32 Event, u32 Timeout) * ******************************************************************************/ u32 Xil_WaitForEvents(UINTPTR EventsRegAddr, u32 EventsMask, u32 WaitEvents, - u32 Timeout, u32* Events) + u32 Timeout, u32 *Events) { u32 EventStatus; u32 PollCount = Timeout; @@ -333,7 +337,7 @@ u32 Xil_WaitForEvents(UINTPTR EventsRegAddr, u32 EventsMask, u32 WaitEvents, do { EventStatus = Xil_In32(EventsRegAddr); EventStatus &= EventsMask; - if((EventStatus & WaitEvents) != 0U) { + if ((EventStatus & WaitEvents) != 0U) { Status = XST_SUCCESS; *Events = EventStatus; break; @@ -343,8 +347,7 @@ u32 Xil_WaitForEvents(UINTPTR EventsRegAddr, u32 EventsMask, u32 WaitEvents, Xil_PlmStubHandler(); #endif usleep(1U); - } - while(PollCount > 0U); + } while (PollCount > 0U); return Status; } @@ -366,12 +369,12 @@ u32 Xil_IsValidHexChar(const char *Ch) { u32 Status = XST_FAILURE; - if(NULL == Ch) { + if (NULL == Ch) { goto END; } - if (((*Ch >= '0') && (*Ch <='9'))|| - ((*Ch >= 'a') && (*Ch <='f'))|| - ((*Ch >= 'A') && (*Ch <='F'))) { + if (((*Ch >= '0') && (*Ch <= '9')) || + ((*Ch >= 'a') && (*Ch <= 'f')) || + ((*Ch >= 'A') && (*Ch <= 'F'))) { Status = XST_SUCCESS; } @@ -399,7 +402,7 @@ u32 Xil_ValidateHexStr(const char *HexStr) u32 Len; u32 Status = XST_INVALID_PARAM; - if(NULL == HexStr) { + if (NULL == HexStr) { goto END; } @@ -466,21 +469,20 @@ u32 Xil_ConvertStringToHexBE(const char *Str, u8 *Buf, u32 Len) goto END; } - if(Len != (strlen(Str) * XIL_SIZE_OF_NIBBLE_IN_BITS)) { + if (Len != (strlen(Str) * XIL_SIZE_OF_NIBBLE_IN_BITS)) { Status = (u32)XST_INVALID_PARAM; goto END; } ConvertedLen = 0U; while (ConvertedLen < (Len / XIL_SIZE_OF_NIBBLE_IN_BITS)) { - if ((Xil_ConvertCharToNibble(((u8)Str[ConvertedLen]),&UpperNibble) - == (u32)XST_SUCCESS) && (Xil_ConvertCharToNibble(((u8)Str[ConvertedLen+1U]), - &LowerNibble) == (u32)XST_SUCCESS)) { - Buf[ConvertedLen/2U] = + if ((Xil_ConvertCharToNibble(((u8)Str[ConvertedLen]), &UpperNibble) + == (u32)XST_SUCCESS) && (Xil_ConvertCharToNibble(((u8)Str[ConvertedLen + 1U]), + &LowerNibble) == (u32)XST_SUCCESS)) { + Buf[ConvertedLen / 2U] = (UpperNibble << XIL_SIZE_OF_NIBBLE_IN_BITS) | - LowerNibble; - } - else { + LowerNibble; + } else { Status = (u32)XST_INVALID_PARAM; goto END; } @@ -528,7 +530,7 @@ u32 Xil_ConvertStringToHexLE(const char *Str, u8 *Buf, u32 Len) goto END; } - if(Len != (strlen(Str) * XIL_SIZE_OF_NIBBLE_IN_BITS)) { + if (Len != (strlen(Str) * XIL_SIZE_OF_NIBBLE_IN_BITS)) { Status = XST_INVALID_PARAM; goto END; } @@ -537,15 +539,14 @@ u32 Xil_ConvertStringToHexLE(const char *Str, u8 *Buf, u32 Len) ConvertedLen = 0U; while (ConvertedLen < (Len / XIL_SIZE_OF_NIBBLE_IN_BITS)) { if ((Xil_ConvertCharToNibble(((u8)Str[ConvertedLen]), - &UpperNibble) == XST_SUCCESS) && - (Xil_ConvertCharToNibble(((u8)Str[ConvertedLen + 1U]), - &LowerNibble) == XST_SUCCESS)) { - Buf[StrIndex] = - (UpperNibble << XIL_SIZE_OF_NIBBLE_IN_BITS) | - LowerNibble; - StrIndex = StrIndex - 1U; - } - else { + &UpperNibble) == XST_SUCCESS) && + (Xil_ConvertCharToNibble(((u8)Str[ConvertedLen + 1U]), + &LowerNibble) == XST_SUCCESS)) { + Buf[StrIndex] = + (UpperNibble << XIL_SIZE_OF_NIBBLE_IN_BITS) | + LowerNibble; + StrIndex = StrIndex - 1U; + } else { Status = XST_INVALID_PARAM; goto END; } @@ -580,7 +581,7 @@ u32 Xil_Strnlen(const char *Str, u32 MaxLen) goto END; } - while(StrLen < MaxLen) { + while (StrLen < MaxLen) { if ('\0' == *InStr) { break; } @@ -625,7 +626,7 @@ void Xil_UtilRMW32(u32 Addr, u32 Mask, u32 Value) * @return XST_SUCCESS on success and error code on failure * ******************************************************************************/ -int Xil_Strcpy(char *DestPtr, const char *SrcPtr, const u32 Size) +s32 Xil_Strcpy(char *DestPtr, const char *SrcPtr, const u32 Size) { int Status = XST_FAILURE; u32 Count; @@ -665,8 +666,8 @@ END: * @note None * ****************************************************************************/ -int Xil_StrCpyRange(const u8 *Src, u8 *Dest, u32 From, u32 To, u32 MaxSrcLen, - u32 MaxDstLen) +s32 Xil_StrCpyRange(const u8 *Src, u8 *Dest, u32 From, u32 To, u32 MaxSrcLen, + u32 MaxDstLen) { int Status = XST_FAILURE; u32 SrcLength; @@ -693,7 +694,7 @@ int Xil_StrCpyRange(const u8 *Src, u8 *Dest, u32 From, u32 To, u32 MaxSrcLen, goto END; } - for (Index = From; (Index <= To) && (Src[Index]!= (u8)'\0'); Index++) { + for (Index = From; (Index <= To) && (Src[Index] != (u8)'\0'); Index++) { Dest[Index - From] = Src[Index]; } @@ -716,7 +717,7 @@ END: * @return XST_SUCCESS on success and error code on failure * ******************************************************************************/ -int Xil_Strcat(char* Str1Ptr, const char* Str2Ptr, const u32 Size) +s32 Xil_Strcat(char *Str1Ptr, const char *Str2Ptr, const u32 Size) { int Status = XST_FAILURE; u32 Count = 0U; @@ -761,7 +762,7 @@ END: * @return XST_SUCCESS on success and error code on failure * ******************************************************************************/ -int Xil_SecureMemCpy(void * DestPtr, u32 DestPtrLen, const void * SrcPtr, u32 Len) +s32 Xil_SecureMemCpy(void *DestPtr, u32 DestPtrLen, const void *SrcPtr, u32 Len) { int Status = XST_FAILURE; u8 *Dest = (u8 *)DestPtr; @@ -807,7 +808,7 @@ END: * 1 if first non-matching character is greater value in Buf1Ptr * ******************************************************************************/ -int Xil_MemCmp(const void * Buf1Ptr, const void * Buf2Ptr, u32 Len) +s32 Xil_MemCmp(const void *Buf1Ptr, const void *Buf2Ptr, u32 Len) { volatile int RetVal = 1; const u8 *Buf1 = Buf1Ptr; @@ -854,7 +855,7 @@ END: * - XST_SUCCESS: If Zeroization is successful. * - XST_FAILURE: If Zeroization is not successful. ********************************************************************************/ -int Xil_SecureZeroize(u8 *DataPtr, const u32 Length) +s32 Xil_SecureZeroize(u8 *DataPtr, const u32 Length) { u32 Index; int Status = XST_FAILURE; @@ -863,7 +864,7 @@ int Xil_SecureZeroize(u8 *DataPtr, const u32 Length) (void)memset(DataPtr, 0, Length); /* Read it back to verify */ - for (Index = 0U; Index < Length; Index++) { + for (Index = 0U; Index < Length; Index++) { if (DataPtr[Index] != 0x00U) { goto END; } @@ -895,18 +896,16 @@ END: * XST_INVALID_PARAM - Invalid inputs * *****************************************************************************/ -int Xil_SMemCmp(const void *Src1, const u32 Src1Size, - const void *Src2, const u32 Src2Size, const u32 CmpLen) +s32 Xil_SMemCmp(const void *Src1, const u32 Src1Size, + const void *Src2, const u32 Src2Size, const u32 CmpLen) { int Status = XST_FAILURE; if ((Src1 == NULL) || (Src2 == NULL)) { Status = XST_INVALID_PARAM; - } - else if ((CmpLen == 0U) || (Src1Size < CmpLen) || (Src2Size < CmpLen)) { + } else if ((CmpLen == 0U) || (Src1Size < CmpLen) || (Src2Size < CmpLen)) { Status = XST_INVALID_PARAM; - } - else { + } else { Status = memcmp (Src1, Src2, CmpLen); if (Status != 0) { Status = XST_FAILURE; @@ -937,8 +936,8 @@ int Xil_SMemCmp(const void *Src1, const u32 Src1Size, * XST_INVALID_PARAM - Invalid inputs * *****************************************************************************/ -int Xil_SMemCmp_CT(const void *Src1, const u32 Src1Size, - const void *Src2, const u32 Src2Size, const u32 CmpLen) +s32 Xil_SMemCmp_CT(const void *Src1, const u32 Src1Size, + const void *Src2, const u32 Src2Size, const u32 CmpLen) { volatile int Status = XST_FAILURE; volatile int StatusRedundant = XST_FAILURE; @@ -951,13 +950,11 @@ int Xil_SMemCmp_CT(const void *Src1, const u32 Src1Size, if ((Src1 == NULL) || (Src2 == NULL)) { Status = XST_INVALID_PARAM; - } - else if ((CmpLen == 0U) || (Src1Size < CmpLen) || (Src2Size < CmpLen)) { + } else if ((CmpLen == 0U) || (Src1Size < CmpLen) || (Src2Size < CmpLen)) { Status = XST_INVALID_PARAM; - } - else { + } else { while (Cnt >= sizeof(u32)) { - Data |= (*(const u32 *)Src_1 ^ *(const u32 *)Src_2); + Data |= (*(const u32 *)Src_1 ^ * (const u32 *)Src_2); DataRedundant &= ~Data; Src_1 += sizeof(u32); Src_2 += sizeof(u32); @@ -998,29 +995,26 @@ int Xil_SMemCmp_CT(const void *Src1, const u32 Src1Size, * XST_INVALID_PARAM - Invalid inputs * *****************************************************************************/ -int Xil_SMemCpy(void *Dest, const u32 DestSize, - const void *Src, const u32 SrcSize, const u32 CopyLen) +s32 Xil_SMemCpy(void *Dest, const u32 DestSize, + const void *Src, const u32 SrcSize, const u32 CopyLen) { int Status = XST_FAILURE; const u8 *Src8 = (const u8 *) Src; const u8 *Dst8 = (u8 *) Dest; - void * volatile DestTemp = Dest; - const void * volatile SrcTemp = Src; + void *volatile DestTemp = Dest; + const void *volatile SrcTemp = Src; if ((Dest == NULL) || (Src == NULL)) { Status = XST_INVALID_PARAM; - } - else if ((CopyLen == 0U) || (DestSize < CopyLen) || (SrcSize < CopyLen)) { + } else if ((CopyLen == 0U) || (DestSize < CopyLen) || (SrcSize < CopyLen)) { Status = XST_INVALID_PARAM; } /* Return error for overlap string */ else if ((Src8 < Dst8) && (&Src8[CopyLen - 1U] >= Dst8)) { Status = XST_INVALID_PARAM; - } - else if ((Dst8 < Src8) && (&Dst8[CopyLen - 1U] >= Src8)) { + } else if ((Dst8 < Src8) && (&Dst8[CopyLen - 1U] >= Src8)) { Status = XST_INVALID_PARAM; - } - else { + } else { (void)memcpy(DestTemp, SrcTemp, CopyLen); Status = XST_SUCCESS; } @@ -1045,15 +1039,14 @@ int Xil_SMemCpy(void *Dest, const u32 DestSize, * XST_INVALID_PARAM - Invalid inputs * *****************************************************************************/ -int Xil_SMemSet(void *Dest, const u32 DestSize, - const u8 Data, const u32 Len) +s32 Xil_SMemSet(void *Dest, const u32 DestSize, + const u8 Data, const u32 Len) { int Status = XST_FAILURE; if ((Dest == NULL) || (DestSize < Len) || (Len == 0U)) { Status = XST_INVALID_PARAM; - } - else { + } else { (void)memset(Dest, (s32)Data, Len); Status = XST_SUCCESS; } @@ -1077,29 +1070,29 @@ int Xil_SMemSet(void *Dest, const u32 DestSize, * XST_INVALID_PARAM - Invalid inputs * *****************************************************************************/ -int Xil_SStrCat (u8 *DestStr, const u32 DestSize, - const u8 *SrcStr, const u32 SrcSize) +s32 Xil_SStrCat (u8 *DestStr, const u32 DestSize, + const u8 *SrcStr, const u32 SrcSize) { int Status = XST_FAILURE; u32 SrcLen; u32 DstLen; + u32 Length; if ((DestStr == NULL) || (SrcStr == NULL)) { Status = XST_INVALID_PARAM; goto END; } - SrcLen = strnlen((const char*)SrcStr, SrcSize); - DstLen = strnlen((const char*)DestStr, DestSize); + SrcLen = strnlen((const char *)SrcStr, SrcSize); + DstLen = strnlen((const char *)DestStr, DestSize); + Length = SrcLen + DstLen; if ((DestSize <= DstLen) || (SrcSize <= SrcLen)) { Status = XST_INVALID_PARAM; - } - else if (DestSize <= (SrcLen + DstLen)) { + } else if (DestSize <= Length) { Status = XST_INVALID_PARAM; - } - else { - (void)strcat((char*)DestStr, (const char*)SrcStr); + } else { + (void)strncat((char *)DestStr, (const char *)SrcStr, Length); Status = XST_SUCCESS; } @@ -1124,8 +1117,8 @@ END: * XST_INVALID_PARAM - Invalid inputs * *****************************************************************************/ -int Xil_SStrCmp(const u8 *Str1, const u32 Str1Size, - const u8 *Str2, const u32 Str2Size) +s32 Xil_SStrCmp(const u8 *Str1, const u32 Str1Size, + const u8 *Str2, const u32 Str2Size) { int Status = XST_FAILURE; u32 Str1Len = 0U; @@ -1136,16 +1129,14 @@ int Xil_SStrCmp(const u8 *Str1, const u32 Str1Size, goto END; } - Str1Len = strnlen((const char*)Str1, Str1Size); - Str2Len = strnlen((const char*)Str2, Str2Size); + Str1Len = strnlen((const char *)Str1, Str1Size); + Str2Len = strnlen((const char *)Str2, Str2Size); if ((Str1Size <= Str1Len) || (Str2Size <= Str2Len)) { Status = XST_INVALID_PARAM; - } - else if ((Str1Len < Str2Len) || (Str1Len > Str2Len)) { + } else if ((Str1Len < Str2Len) || (Str1Len > Str2Len)) { Status = XST_FAILURE; - } - else { + } else { Status = memcmp(Str1, Str2, Str1Len); if (Status != 0) { Status = XST_FAILURE; @@ -1177,8 +1168,8 @@ END: * XST_INVALID_PARAM - Invalid inputs * *****************************************************************************/ -int Xil_SStrCmp_CT (const u8 *Str1, const u32 Str1Size, - const u8 *Str2, const u32 Str2Size) +s32 Xil_SStrCmp_CT (const u8 *Str1, const u32 Str1Size, + const u8 *Str2, const u32 Str2Size) { int Status = XST_FAILURE; u32 Str1Len = 0U; @@ -1189,16 +1180,14 @@ int Xil_SStrCmp_CT (const u8 *Str1, const u32 Str1Size, goto END; } - Str1Len = strnlen((const char*)Str1, Str1Size); - Str2Len = strnlen((const char*)Str2, Str2Size); + Str1Len = strnlen((const char *)Str1, Str1Size); + Str2Len = strnlen((const char *)Str2, Str2Size); if ((Str1Size <= Str1Len) || (Str2Size <= Str2Len)) { Status = XST_INVALID_PARAM; - } - else if (Str1Len != Str2Len) { + } else if (Str1Len != Str2Len) { Status = XST_FAILURE; - } - else { + } else { Status = Xil_SMemCmp_CT (Str1, Str1Size, Str2, Str2Size, Str1Len); } @@ -1222,8 +1211,8 @@ END: * XST_INVALID_PARAM - Invalid inputs * *****************************************************************************/ -int Xil_SStrCpy(u8 *DestStr, const u32 DestSize, - const u8 *SrcStr, const u32 SrcSize) +s32 Xil_SStrCpy(u8 *DestStr, const u32 DestSize, + const u8 *SrcStr, const u32 SrcSize) { int Status = XST_FAILURE; u32 SrcLen = 0U; @@ -1233,12 +1222,11 @@ int Xil_SStrCpy(u8 *DestStr, const u32 DestSize, goto END; } - SrcLen = strnlen((const char*)SrcStr, SrcSize); + SrcLen = strnlen((const char *)SrcStr, SrcSize); if ((DestSize <= SrcLen) || (SrcSize <= SrcLen)) { Status = XST_INVALID_PARAM; - } - else { + } else { (void)memcpy(DestStr, SrcStr, SrcLen + 1U); Status = XST_SUCCESS; } @@ -1263,19 +1251,17 @@ END: * XST_INVALID_PARAM - Invalid inputs * *****************************************************************************/ -int Xil_SMemMove(void *Dest, const u32 DestSize, - const void *Src, const u32 SrcSize, const u32 CopyLen) +s32 Xil_SMemMove(void *Dest, const u32 DestSize, + const void *Src, const u32 SrcSize, const u32 CopyLen) { volatile int Status = XST_FAILURE; const void *Output = NULL; if ((Dest == NULL) || (Src == NULL)) { Status = XST_INVALID_PARAM; - } - else if ((CopyLen == 0U) || (DestSize < CopyLen) || (SrcSize < CopyLen)) { + } else if ((CopyLen == 0U) || (DestSize < CopyLen) || (SrcSize < CopyLen)) { Status = XST_INVALID_PARAM; - } - else { + } else { Output = memmove(Dest, Src, CopyLen); if (Output != NULL) { Status = XST_SUCCESS; @@ -1313,7 +1299,7 @@ u32 Xil_WaitForEventSet(u32 Timeout, u32 NumOfEvents, volatile u32 *EventAddr, . va_start(Event, EventAddr); /* wait for all events to complete */ for (i = 0; i < NumOfEvents; i++) { - while(PollCount > 0U) { + while (PollCount > 0U) { if (Xil_In32((UINTPTR)EventAddr)) { LoopCnt++; break; @@ -1330,13 +1316,13 @@ u32 Xil_WaitForEventSet(u32 Timeout, u32 NumOfEvents, volatile u32 *EventAddr, . EventAddr = va_arg(Event, volatile u32 *); PollCount = Timeout; } - va_end(Event); END: if (LoopCnt == NumOfEvents) { Status = XST_SUCCESS; } + va_end(Event); return Status; } @@ -1369,9 +1355,58 @@ s32 Xil_SecureRMW32(UINTPTR Addr, u32 Mask, u32 Value) /* verify value written to specified address */ ReadReg = Xil_In32(Addr) & Mask; - if(ReadReg == (Mask & Value)) { + if (ReadReg == (Mask & Value)) { Status = XST_SUCCESS; } return Status; } + +/*****************************************************************************/ +/** + * @brief This function changes the endianness of source data and copies it + * into destination buffer. + * + * @param Dest - Pointer to destination memory + * @param DestSize - Memory available at destination + * @param Src - Pointer to source memory + * @param SrcSize - Maximum data that can be copied from source + * @param CopyLen - Number of bytes to be copied + * + * @return + * XST_SUCCESS - Copy is successful + * XST_INVALID_PARAM - Invalid inputs + * XST_FAILURE - On failure + * + *****************************************************************************/ +s32 Xil_SChangeEndiannessAndCpy(void *Dest, const u32 DestSize, + const void *Src, const u32 SrcSize, const u32 CopyLen) +{ + s32 Status = XST_FAILURE; + volatile u32 Index; + const u8 *Src8 = (const u8 *) Src; + const u8 *Dst8 = (u8 *) Dest; + u8 *DestTemp = Dest; + const u8 *SrcTemp = Src; + + if ((Dest == NULL) || (Src == NULL)) { + Status = XST_INVALID_PARAM; + } else if ((CopyLen == 0U) || (DestSize < CopyLen) || (SrcSize < CopyLen)) { + Status = XST_INVALID_PARAM; + } + /* Return error for overlap string */ + else if ((Src8 < Dst8) && (&Src8[CopyLen - 1U] >= Dst8)) { + Status = XST_INVALID_PARAM; + } else if ((Dst8 < Src8) && (&Dst8[CopyLen - 1U] >= Src8)) { + Status = XST_INVALID_PARAM; + } else { + for (Index = 0U; Index < CopyLen; Index++) { + DestTemp[Index] = SrcTemp[CopyLen - Index - 1U]; + } + if (Index == CopyLen) { + Status = XST_SUCCESS; + } + } + + return Status; +} diff --git a/bsp_z7/ps7_cortexa9_0/include/xil_util.h b/bsp_z7/ps7_cortexa9_0/include/xil_util.h index d65854c..981c7ee 100644 --- a/bsp_z7/ps7_cortexa9_0/include/xil_util.h +++ b/bsp_z7/ps7_cortexa9_0/include/xil_util.h @@ -1,7 +1,7 @@ /******************************************************************************/ /** -* Copyright (c) 2019 - 2022 Xilinx, Inc. All rights reserved. -* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved. +* Copyright (C) 2019 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (C) 2022 - 2024 Advanced Micro Devices, Inc. All rights reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -61,6 +61,12 @@ * 8.1 akm 01/02/23 Added Xil_RegisterPlmHandler() & Xil_PlmStubHandler() APIs. * bm 03/14/23 Added XSECURE_REDUNDANT_CALL and XSECURE_REDUNDANT_IMPL macros * sk 03/14/23 Added Status Check Glitch detect Macro +* 9.0 ml 03/03/23 Add description to fix doxygen warnings. +* mmd 07/09/23 Added macro to build version +* ml 09/13/23 Replaced numerical types (int) with proper typedefs(s32) to +* fix MISRA-C violations for Rule 4.6 +* 9.1 kpt 02/21/24 Added Xil_SChangeEndiannessAndCpy function +* * * *****************************************************************************/ @@ -72,19 +78,33 @@ extern "C" { #endif +/******************************* Include Files ********************************/ #include "xil_types.h" #include "xil_io.h" #include "xstatus.h" /*************************** Constant Definitions *****************************/ -#define XIL_SIZE_OF_NIBBLE_IN_BITS 4U -#define XIL_SIZE_OF_BYTE_IN_BITS 8U - -/* Maximum string length handled by Xil_ValidateHexStr function */ -#define XIL_MAX_HEX_STR_LEN 512U +#define XIL_SIZE_OF_NIBBLE_IN_BITS 4U /**< size of nibble in bits */ +#define XIL_SIZE_OF_BYTE_IN_BITS 8U /**< size of byte in bits */ +#define XIL_MAX_HEX_STR_LEN 512U /**< Maximum string length handled by + Xil_ValidateHexStr function */ /****************** Macros (Inline Functions) Definitions *********************/ + +/******************************************************************************/ +/** + * + * Builds version number by concatenates 16-bit Major version and Minor version. + * + * @param Major is the 16-bit major version number + * @param Minor is the 16-bit minor version number + * + * @return 32-bit version number + * + ******************************************************************************/ +#define XIL_BUILD_VERSION(Major, Minor) ((((u32)Major) << 16U) | (Minor)) + #ifdef __GNUC__ /******************************************************************************/ /** @@ -103,12 +123,12 @@ extern "C" { * ******************************************************************************/ #define XSECURE_TEMPORAL_IMPL(Var, VarTmp, Function, ...) \ - { \ - Var = XST_FAILURE; \ - VarTmp = XST_FAILURE; \ - Var = Function(__VA_ARGS__); \ - VarTmp = Var; \ - } + { \ + Var = XST_FAILURE; \ + VarTmp = XST_FAILURE; \ + Var = Function(__VA_ARGS__); \ + VarTmp = Var; \ + } /******************************************************************************/ /** @@ -133,14 +153,14 @@ extern "C" { volatile int StatusTmp; \ XSECURE_TEMPORAL_IMPL(Status, StatusTmp, Function, __VA_ARGS__); \ if ((Status != XST_SUCCESS) || \ - (StatusTmp != XST_SUCCESS)) { \ + (StatusTmp != XST_SUCCESS)) { \ if (((Status) != (StatusTmp)) || \ - (Status == XST_SUCCESS)) { \ + (Status == XST_SUCCESS)) { \ Status = XST_GLITCH_ERROR; \ }\ goto Label; \ } \ - } + } /******************************************************************************/ /** @@ -163,7 +183,7 @@ extern "C" { { \ Status = Function(__VA_ARGS__); \ StatusTmp = Function(__VA_ARGS__); \ - } + } /******************************************************************************/ /** @@ -182,7 +202,7 @@ extern "C" { { \ Function(__VA_ARGS__); \ Function(__VA_ARGS__); \ - } + } /******************************************************************************/ /** @@ -204,110 +224,114 @@ extern "C" { #endif /*************************** Function Prototypes ******************************/ -/* Ceils the provided float value */ +/**< Ceils the provided float value */ s32 Xil_Ceil(float Value); -/* Converts input character to nibble */ +/**< Converts input character to nibble */ u32 Xil_ConvertCharToNibble(u8 InChar, u8 *Num); -/* Convert input hex string to array of 32-bits integers */ +/**< Convert input hex string to array of 32-bits integers */ u32 Xil_ConvertStringToHex(const char *Str, u32 *buf, u8 Len); #ifdef VERSAL_PLM -/* Register PLM handler */ +/**< Register PLM handler */ void Xil_RegisterPlmHandler(void (*PlmAlive) (void)); -/* Call PLM handler */ +/**< Call PLM handler */ void Xil_PlmStubHandler(void); #endif -/* Waits for specified event */ +/**< Waits for specified event */ u32 Xil_WaitForEvent(UINTPTR RegAddr, u32 EventMask, u32 Event, u32 Timeout); -/* Waits for specified events */ +/**< Waits for specified events */ u32 Xil_WaitForEvents(UINTPTR EventsRegAddr, u32 EventsMask, u32 WaitEvents, - u32 Timeout, u32* Events); + u32 Timeout, u32 *Events); -/* Validate input hex character */ +/**< Validate input hex character */ u32 Xil_IsValidHexChar(const char *Ch); -/* Validate the input string contains only hexadecimal characters */ +/**< Validate the input string contains only hexadecimal characters */ u32 Xil_ValidateHexStr(const char *HexStr); -/* Convert string to hex numbers in little enidian format */ +/**< Convert string to hex numbers in little enidian format */ u32 Xil_ConvertStringToHexLE(const char *Str, u8 *Buf, u32 Len); -/* Returns length of the input string */ +/**< Returns length of the input string */ u32 Xil_Strnlen(const char *Str, u32 MaxLen); -/* Convert string to hex numbers in big endian format */ -u32 Xil_ConvertStringToHexBE(const char * Str, u8 * Buf, u32 Len); +/**< Convert string to hex numbers in big endian format */ +u32 Xil_ConvertStringToHexBE(const char *Str, u8 *Buf, u32 Len); -/*Read, Modify and Write to an address*/ +/**< Read, Modify and Write to an address*/ void Xil_UtilRMW32(u32 Addr, u32 Mask, u32 Value); -/* Copies source string to destination string */ -int Xil_Strcpy(char *DestPtr, const char *SrcPtr, const u32 Size); +/**< Copies source string to destination string */ +s32 Xil_Strcpy(char *DestPtr, const char *SrcPtr, const u32 Size); -/* Copies specified range from source string to destination string */ -int Xil_StrCpyRange(const u8 *Src, u8 *Dest, u32 From, u32 To, u32 MaxSrcLen, - u32 MaxDstLen); +/**< Copies specified range from source string to destination string */ +s32 Xil_StrCpyRange(const u8 *Src, u8 *Dest, u32 From, u32 To, u32 MaxSrcLen, + u32 MaxDstLen); -/* Appends string2 to string1 */ -int Xil_Strcat(char* Str1Ptr, const char* Str2Ptr, const u32 Size); +/**< Appends string2 to string1 */ +s32 Xil_Strcat(char *Str1Ptr, const char *Str2Ptr, const u32 Size); -/* Copies Len bytes from source memory to destination memory */ -int Xil_SecureMemCpy(void * DestPtr, u32 DestPtrLen, const void * SrcPtr, u32 Len); +/**< Copies Len bytes from source memory to destination memory */ +s32 Xil_SecureMemCpy(void *DestPtr, u32 DestPtrLen, const void *SrcPtr, u32 Len); -/* Compares Len bytes from memory1 and memory2 */ -int Xil_MemCmp(const void * Buf1Ptr, const void * Buf2Ptr, u32 Len); +/**< Compares Len bytes from memory1 and memory2 */ +s32 Xil_MemCmp(const void *Buf1Ptr, const void *Buf2Ptr, u32 Len); -/* Zeroizes the memory of given length */ -int Xil_SecureZeroize(u8 *DataPtr, const u32 Length); +/**< Zeroizes the memory of given length */ +s32 Xil_SecureZeroize(u8 *DataPtr, const u32 Length); -/* Copies Len bytes from source memory to destination memory */ -int Xil_SMemCpy (void *Dest, const u32 DestSize, - const void *Src, const u32 SrcSize, const u32 CopyLen); +/**< Copies Len bytes from source memory to destination memory */ +s32 Xil_SMemCpy (void *Dest, const u32 DestSize, + const void *Src, const u32 SrcSize, const u32 CopyLen); -/* Copies Len bytes from source memory to destination memory, allows +/**< Copies Len bytes from source memory to destination memory, allows overlapped memory between source and destination */ -int Xil_SMemMove(void *Dest, const u32 DestSize, - const void *Src, const u32 SrcSize, const u32 CopyLen); +s32 Xil_SMemMove(void *Dest, const u32 DestSize, + const void *Src, const u32 SrcSize, const u32 CopyLen); -/* Compares Len bytes between source and destination memory */ -int Xil_SMemCmp (const void *Src1, const u32 Src1Size, - const void *Src2, const u32 Src2Size, const u32 CmpLen); +/**< Compares Len bytes between source and destination memory */ +s32 Xil_SMemCmp (const void *Src1, const u32 Src1Size, + const void *Src2, const u32 Src2Size, const u32 CmpLen); -/* Compares Len bytes between source and destination memory with constant time */ -int Xil_SMemCmp_CT (const void *Src1, const u32 Src1Size, - const void *Src2, const u32 Src2Size, const u32 CmpLen); +/**< Compares Len bytes between source and destination memory with constant time */ +s32 Xil_SMemCmp_CT (const void *Src1, const u32 Src1Size, + const void *Src2, const u32 Src2Size, const u32 CmpLen); -/* Sets the destination memory of given length with given data */ -int Xil_SMemSet (void *Dest, const u32 DestSize, - const u8 Data, const u32 Len); +/**< Sets the destination memory of given length with given data */ +s32 Xil_SMemSet (void *Dest, const u32 DestSize, + const u8 Data, const u32 Len); -/* Copies source string to destination string */ -int Xil_SStrCpy (u8 *DestStr, const u32 DestSize, - const u8 *SrcStr, const u32 SrcSize); +/**< Copies source string to destination string */ +s32 Xil_SStrCpy (u8 *DestStr, const u32 DestSize, + const u8 *SrcStr, const u32 SrcSize); -/* Compares source string with destination string */ -int Xil_SStrCmp (const u8 *Str1, const u32 Str1Size, - const u8 *Str2, const u32 Str2Size); +/**< Compares source string with destination string */ +s32 Xil_SStrCmp (const u8 *Str1, const u32 Str1Size, + const u8 *Str2, const u32 Str2Size); -/* Compares source string with destination string with constant time */ -int Xil_SStrCmp_CT (const u8 *Str1, const u32 Str1Size, - const u8 *Str2, const u32 Str2Size); +/**< Compares source string with destination string with constant time */ +s32 Xil_SStrCmp_CT (const u8 *Str1, const u32 Str1Size, + const u8 *Str2, const u32 Str2Size); -/* Concatenates source string to destination string */ -int Xil_SStrCat (u8 *DestStr, const u32 DestSize, - const u8 *SrcStr, const u32 SrcSize); +/**< Concatenates source string to destination string */ +s32 Xil_SStrCat (u8 *DestStr, const u32 DestSize, + const u8 *SrcStr, const u32 SrcSize); -/* Waits for event timeout */ +/**< Waits for event timeout */ u32 Xil_WaitForEventSet(u32 Timeout, u32 NumOfEvents, volatile u32 *EventAddr, ...); -/* Implements Read Modify Writes securely */ +/**< Implements Read Modify Writes securely */ s32 Xil_SecureRMW32(UINTPTR Addr, u32 Mask, u32 Value); +/**< Changes byte endianness of source buffer and copies it into destination */ +s32 Xil_SChangeEndiannessAndCpy(void *Dest, const u32 DestSize, + const void *Src, const u32 SrcSize, const u32 CopyLen); + #ifdef __cplusplus } #endif diff --git a/bsp_z7/ps7_cortexa9_0/include/xilffs.h b/bsp_z7/ps7_cortexa9_0/include/xilffs.h new file mode 100644 index 0000000..dd51f5b --- /dev/null +++ b/bsp_z7/ps7_cortexa9_0/include/xilffs.h @@ -0,0 +1,67 @@ +/****************************************************************************** +* Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** + * + * @file xilffs.h + * @addtogroup xilffs Overview + * @{ + * @details + * + * This file contains declarations specific to AMD's unique requirements and + * functionalities for xilffs. + * + * 
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date        Changes
+ * ----- ---- -------- -------------------------------------------------------
+ * 5.2   ht   10/10/23    Added code for versioning of library.
+ *
+ *
+ * + *@note + *****************************************************************************/ +#ifndef XILFFS_H +#define XILFFS_H + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ +#include "xil_util.h" +#include "xil_io.h" +#include "xil_types.h" + +/************************** Constant Definitions *****************************/ +/* Library version info */ +#define XILFFS_MAJOR_VERSION 5U +#define XILFFS_MINOR_VERSION 2U + +/****************** Macros (Inline Functions) Definitions *********************/ + +/*****************************************************************************/ +/** + * + * @brief This function returns the version number of xilffs library. + * + * @return 32-bit version number + * +******************************************************************************/ +static __attribute__((always_inline)) INLINE +u32 Xilffs_GetLibVersion(void) +{ + return (XIL_BUILD_VERSION(XILFFS_MAJOR_VERSION, XILFFS_MINOR_VERSION)); +} + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* XILFFS_H */ diff --git a/bsp_z7/ps7_cortexa9_0/include/xparameters.h b/bsp_z7/ps7_cortexa9_0/include/xparameters.h index f032659..511b0f2 100644 --- a/bsp_z7/ps7_cortexa9_0/include/xparameters.h +++ b/bsp_z7/ps7_cortexa9_0/include/xparameters.h @@ -1,5 +1,6 @@ /****************************************************************************** * Copyright (c) 2021 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (C) 2024 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ #ifndef XPARAMETERS_H /* prevent circular inclusions */ @@ -7,7 +8,6 @@ /* Definition for CPU ID */ #define XPAR_CPU_ID 0U -//#define USE_AMP 0U TODO having this to 0 breaks xil_cache /* Definitions for peripheral PS7_CORTEXA9_0 */ #define XPAR_PS7_CORTEXA9_0_CPU_CLK_FREQ_HZ 666666687 @@ -23,17 +23,8 @@ #include "xparameters_ps.h" -// Default is for Zedboard -#ifndef ZYNQ_USE_UART0 -#define STDIN_BASEADDRESS XPS_UART1_BASEADDR -#define STDIN_INT_NR XPAR_XUARTPS_1_INTR -#define STDOUT_BASEADDRESS XPS_UART1_BASEADDR -#else -#define STDIN_BASEADDRESS XPS_UART0_BASEADDR -#define STDIN_INT_NR XPAR_XUARTPS_0_INTR -#define STDOUT_BASEADDRESS XPS_UART0_BASEADDR -#endif - +#define STDIN_BASEADDRESS 0xE0001000 +#define STDOUT_BASEADDRESS 0xE0001000 /******************************************************************/ @@ -357,6 +348,7 @@ #define XPAR_PS7_SD_0_CLK_50_DDR_OTAP_DLY 0 #define XPAR_PS7_SD_0_CLK_100_SDR_OTAP_DLY 0 #define XPAR_PS7_SD_0_CLK_200_SDR_OTAP_DLY 0 +#define XPAR_PS7_SD_0_CLK_200_DDR_OTAP_DLY 0 /******************************************************************/ @@ -380,6 +372,7 @@ #define XPAR_XSDPS_0_CLK_50_DDR_OTAP_DLY 0 #define XPAR_XSDPS_0_CLK_100_SDR_OTAP_DLY 0 #define XPAR_XSDPS_0_CLK_200_SDR_OTAP_DLY 0 +#define XPAR_XSDPS_0_CLK_200_DDR_OTAP_DLY 0 /******************************************************************/ @@ -428,8 +421,8 @@ /* Definitions for peripheral PS7_UART_1 */ #define XPAR_PS7_UART_1_DEVICE_ID 0 -#define XPAR_PS7_UART_1_BASEADDR 0xE0001000 -#define XPAR_PS7_UART_1_HIGHADDR 0xE0001FFF +#define XPAR_PS7_UART_1_BASEADDR 0xE0000000 +#define XPAR_PS7_UART_1_HIGHADDR 0xE0000FFF #define XPAR_PS7_UART_1_UART_CLK_FREQ_HZ 50000000 #define XPAR_PS7_UART_1_HAS_MODEM 0 @@ -438,8 +431,8 @@ /* Canonical definitions for peripheral PS7_UART_1 */ #define XPAR_XUARTPS_0_DEVICE_ID XPAR_PS7_UART_1_DEVICE_ID -#define XPAR_XUARTPS_0_BASEADDR 0xE0001000 -#define XPAR_XUARTPS_0_HIGHADDR 0xE0001FFF +#define XPAR_XUARTPS_0_BASEADDR 0xE0000000 +#define XPAR_XUARTPS_0_HIGHADDR 0xE0000FFF #define XPAR_XUARTPS_0_UART_CLK_FREQ_HZ 50000000 #define XPAR_XUARTPS_0_HAS_MODEM 0 diff --git a/bsp_z7/ps7_cortexa9_0/include/xplatform_info.c b/bsp_z7/ps7_cortexa9_0/include/xplatform_info.c index 83692d8..bdb7c6a 100644 --- a/bsp_z7/ps7_cortexa9_0/include/xplatform_info.c +++ b/bsp_z7/ps7_cortexa9_0/include/xplatform_info.c @@ -43,6 +43,9 @@ * reported with "-Wundef" flag CR#1111453 * 8.1 mus 02/13/23 Added new API's XGetCoreId and XGetClusterId. As of now * they are supported only for VERSAL_NET APU and RPU. +* 9.0 mus 03/28/23 Added new API XGetBootStatus for VERSAL_NET. It can be +* used to identify type of boot (cold/warm). +* 9.0 mus 07/27/23 Updated XGetCoreId API to support A9, R5 and A53 processor. * * ******************************************************************************/ @@ -102,17 +105,17 @@ u32 XGet_Zynq_UltraMp_Platform_info(void) { #if defined (__aarch64__) && (EL1_NONSECURE == 1) XSmc_OutVar reg; - /* + /* * This SMC call will return, - * idcode - upper 32 bits of reg.Arg0 - * version - lower 32 bits of reg.Arg1 + * idcode - upper 32 bits of reg.Arg0 + * version - lower 32 bits of reg.Arg1 */ - reg = Xil_Smc(GET_CHIPID_SMC_FID,0,0, 0, 0, 0, 0, 0); + reg = Xil_Smc(GET_CHIPID_SMC_FID, 0, 0, 0, 0, 0, 0, 0); return (u32)((reg.Arg1 >> XPLAT_INFO_SHIFT) & XPLAT_INFO_MASK); #else u32 reg; reg = ((Xil_In32(XPLAT_PS_VERSION_ADDRESS) >> XPLAT_INFO_SHIFT ) - & XPLAT_INFO_MASK); + & XPLAT_INFO_MASK); return reg; #endif } @@ -130,24 +133,71 @@ u32 XGet_Zynq_UltraMp_Platform_info(void) u32 XGetPSVersion_Info(void) { #if defined (__aarch64__) && (EL1_NONSECURE == 1) - /* - * This SMC call will return, - * idcode - upper 32 bits of reg.Arg0 - * version - lower 32 bits of reg.Arg1 - */ - XSmc_OutVar reg; - reg = Xil_Smc(GET_CHIPID_SMC_FID,0,0, 0, 0, 0, 0, 0); - return (u32)((reg.Arg1 & XPS_VERSION_INFO_MASK) >> - XPS_VERSION_INFO_SHIFT); + /* + * This SMC call will return, + * idcode - upper 32 bits of reg.Arg0 + * version - lower 32 bits of reg.Arg1 + */ + XSmc_OutVar reg; + reg = Xil_Smc(GET_CHIPID_SMC_FID, 0, 0, 0, 0, 0, 0, 0); + return (u32)((reg.Arg1 & XPS_VERSION_INFO_MASK) >> + XPS_VERSION_INFO_SHIFT); #else u32 reg; reg = (Xil_In32(XPLAT_PS_VERSION_ADDRESS) - & XPS_VERSION_INFO_MASK); + & XPS_VERSION_INFO_MASK); return (reg >> XPS_VERSION_INFO_SHIFT); #endif } #endif +#if ! defined(__microblaze__) && ! defined(__riscv) +/*****************************************************************************/ +/** +* +* @brief This API is used to provide infomation about core id of the +* CPU core from which it is executed. +* +* @return Core id of the core on which API is executed. +* +******************************************************************************/ +u8 XGetCoreId(void) +{ + UINTPTR CoreId; + +#if (defined (__aarch64__) && ! defined (VERSAL_NET)) + /* CortexA53 and CortexA72 */ + CoreId = (mfcp(MPIDR_EL1) & XREG_MPIDR_MASK); + CoreId = ((CoreId & XREG_MPIDR_AFFINITY0_MASK) >> \ + XREG_MPIDR_AFFINITY0_SHIFT); +#elif (defined (__aarch64__) && defined (VERSAL_NET)) + /* CortexA78 */ + CoreId = (mfcp(MPIDR_EL1) & XREG_MPIDR_MASK); + CoreId = ((CoreId & XREG_MPIDR_AFFINITY0_MASK) >> \ + XREG_MPIDR_AFFINITY0_SHIFT); +#else + /* CortexA9, CortexR5 and CortexR52 */ +#ifdef __GNUC__ + CoreId = (mfcp(XREG_CP15_MULTI_PROC_AFFINITY) & XREG_MPIDR_MASK); +#elif defined (__ICCARM__) + mfcp(XREG_CP15_MULTI_PROC_AFFINITY, CoreId); + CoreId &= XREG_MPIDR_MASK; +#else + { + register u32 C15Reg __asm(XREG_CP15_MULTI_PROC_AFFINITY); + CoreId = C15Reg; + } + CoreId &= XREG_MPIDR_MASK; +#endif + + CoreId = ((CoreId & XREG_MPIDR_AFFINITY0_MASK) >> \ + XREG_MPIDR_AFFINITY0_SHIFT); +#endif + + return (u8)CoreId; +} +#endif + #if (defined (__aarch64__) && defined (VERSAL_NET)) || defined (ARMR52) /*****************************************************************************/ /** @@ -165,11 +215,11 @@ u8 XGetClusterId(void) #if defined (ARMR52) ClusterId = (mfcp(XREG_CP15_MULTI_PROC_AFFINITY) & XREG_MPIDR_MASK); ClusterId = ((ClusterId & XREG_MPIDR_AFFINITY1_MASK) >> \ - XREG_MPIDR_AFFINITY1_SHIFT); + XREG_MPIDR_AFFINITY1_SHIFT); #else ClusterId = (mfcp(MPIDR_EL1) & XREG_MPIDR_MASK); ClusterId = ((ClusterId & XREG_MPIDR_AFFINITY2_MASK) >> \ - XREG_MPIDR_AFFINITY2_SHIFT); + XREG_MPIDR_AFFINITY2_SHIFT); #endif return (u8)ClusterId; @@ -178,27 +228,38 @@ u8 XGetClusterId(void) /*****************************************************************************/ /** * -* @brief This API is used to provide infomation about core id of the -* CPU core from which it is executed. +* @brief This API returns boot status of core from which it is executed. +* 0th bit of CORE_X_PWRDWN/RPU_PCIL_X_PWRDWN register indicates boot type. * -* @return Core id of the core on which API is executed. +* @return - 0 for cold boot +* - 1 for warm boot * ******************************************************************************/ -u8 XGetCoreId(void) +u8 XGetBootStatus(void) { - u64 CoreId; + u32 Status; + UINTPTR Addr; -#if defined (ARMR52) - CoreId = (mfcp(XREG_CP15_MULTI_PROC_AFFINITY) & XREG_MPIDR_MASK); - CoreId = ((CoreId & XREG_MPIDR_AFFINITY0_MASK) >> \ - XREG_MPIDR_AFFINITY0_SHIFT); +#if (__aarch64__) + u8 CpuNum; + + CpuNum = XGetClusterId(); + CpuNum *= XPS_NUM_OF_CORES_PER_CLUSTER; + CpuNum += XGetCoreId(); + + Addr = XPS_CORE_X_PWRDWN_BASEADDR + (CpuNum * XPS_CORE_X_PWRDWN_OFFSET); + Status = Xil_In32(Addr); + + return (Status & XPS_CORE_X_PWRDWN_EN_MASK); #else - CoreId = (mfcp(MPIDR_EL1) & XREG_MPIDR_MASK); - CoreId = ((CoreId & XREG_MPIDR_AFFINITY1_MASK) >> \ - XREG_MPIDR_AFFINITY1_SHIFT); + Addr = (XPS_RPU_PCIL_CLUSTER_OFFSET * XGetClusterId()) + XPS_RPU_PCIL_A0_PWRDWN; + Addr += (XGetCoreId() * XPS_RPU_PCIL_CORE_OFFSET); + + Status = Xil_In32(Addr); + + return (Status & XPS_RPU_PCIL_X_PWRDWN_EN_MASK); #endif - return (u8)CoreId; } #endif diff --git a/bsp_z7/ps7_cortexa9_0/include/xplatform_info.h b/bsp_z7/ps7_cortexa9_0/include/xplatform_info.h index 3e5df15..251a697 100644 --- a/bsp_z7/ps7_cortexa9_0/include/xplatform_info.h +++ b/bsp_z7/ps7_cortexa9_0/include/xplatform_info.h @@ -36,6 +36,11 @@ * misra_c_2012_rule_10_4 violation. * 8.1 mus 02/13/23 Added new API's XGetCoreId and XGetClusterId. As of now * they are supported only for VERSAL_NET APU and RPU. +* 9.0 mus 03/28/23 Added new API XGetBootStatus for VERSAL_NET. It can be +* used to identify type of boot (cold/warm). +* 9.0 mus 07/27/23 Updated XGetCoreId API to support A9, R5 and A53 processor +* 9.0 ml 09/14/23 Added U to numerical to fix MISRA-C violation for Rule +* 10.1 and 10.4 * * ******************************************************************************/ @@ -60,12 +65,12 @@ extern "C" { #define XPAR_PMC_TAP_BASEADDR 0xF11A0000U #define XPAR_PMC_TAP_VERSION_OFFSET 0x00000004U #define XPLAT_PS_VERSION_ADDRESS (XPAR_PMC_TAP_BASEADDR + \ - XPAR_PMC_TAP_VERSION_OFFSET) + XPAR_PMC_TAP_VERSION_OFFSET) #else #define XPAR_CSU_BASEADDR 0xFFCA0000U #define XPAR_CSU_VER_OFFSET 0x00000044U #define XPLAT_PS_VERSION_ADDRESS (XPAR_CSU_BASEADDR + \ - XPAR_CSU_VER_OFFSET) + XPAR_CSU_VER_OFFSET) #endif #define XPLAT_ZYNQ_ULTRA_MP_SILICON 0x0 #define XPLAT_ZYNQ_ULTRA_MP 0x1 @@ -84,11 +89,37 @@ extern "C" { #define XPS_VERSION_INFO_SHIFT 0x8U #define XPLAT_INFO_SHIFT 0x18U #else -#define XPS_VERSION_INFO_MASK (0xF) +#define XPS_VERSION_INFO_MASK 0xFU #define XPS_VERSION_INFO_SHIFT 0x0U #define XPLAT_INFO_SHIFT 0xCU #endif +#if defined (VERSAL_NET) +#if defined (ARMR52) +#define XPS_NUM_OF_CORES_PER_CLUSTER 2U +#define XPS_RPU_PCIL_A0_PWRDWN 0xEB4200C0U +/* + * Offset between RPU_PCIL_X_PWRDWN registers of consecutive + * CPU cores in given cluster + */ +#define XPS_RPU_PCIL_CORE_OFFSET 0x100U + +/* + * Offset between RPU_PCIL_A0_PWRDWN registers of 2 clusters + */ +#define XPS_RPU_PCIL_CLUSTER_OFFSET 0x1000U +#define XPS_RPU_PCIL_X_PWRDWN_EN_MASK 1U +#else +#define XPS_NUM_OF_CORES_PER_CLUSTER 4U +#define XPS_CORE_X_PWRDWN_BASEADDR 0xECB10000U +/* + * Offset between CORE_X_PWRDWN registers of consecutive + * CPU cores + */ +#define XPS_CORE_X_PWRDWN_OFFSET 48U +#define XPS_CORE_X_PWRDWN_EN_MASK 1U +#endif +#endif /**************************** Type Definitions *******************************/ /** *@endcond @@ -97,6 +128,9 @@ extern "C" { u32 XGetPlatform_Info(void); +#if ! defined(__microblaze__) && ! defined(__riscv) +u8 XGetCoreId(void); +#endif #if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32) || defined (PSU_PMU) || defined (versal) u32 XGetPSVersion_Info(void); @@ -109,6 +143,7 @@ u32 XGet_Zynq_UltraMp_Platform_info(void); #if (defined (__aarch64__) && defined (VERSAL_NET)) || defined (ARMR52) u8 XGetClusterId(void); u8 XGetCoreId(void); +u8 XGetBootStatus(void); #endif /************************** Function Prototypes ******************************/ diff --git a/bsp_z7/ps7_cortexa9_0/include/xpm_init.h b/bsp_z7/ps7_cortexa9_0/include/xpm_init.h new file mode 100644 index 0000000..f2856be --- /dev/null +++ b/bsp_z7/ps7_cortexa9_0/include/xpm_init.h @@ -0,0 +1,46 @@ +/****************************************************************************** +*Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved. +*SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xpm_init.h +* @addtogroup xpm_init xpm_init APIs +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+*  1.0  gm      14/06/23 Initial release.
+*
+******************************************************************************/ + +#ifndef XPM_INIT_H +#define XPM_INIT_H + +/************************** Constant Definitions *****************************/ + +#if defined (XPM_SUPPORT) +#ifdef VERSAL_NET +#define MAX_NODE_COUNT 38 +#elif defined(versal) +#define MAX_NODE_COUNT 33 +#endif + +/**************************** Type Definitions *******************************/ + +typedef struct { + UINTPTR BaseAddress; + UINTPTR NodeId; + UINTPTR ResetId; +} XpmNodeInfo; + +/************************** Function Prototypes ******************************/ + +UINTPTR XpmGetNodeId(UINTPTR BaseAddress); +UINTPTR XpmGetResetId(UINTPTR BaseAddress); + +#endif +#endif diff --git a/bsp_z7/ps7_cortexa9_0/include/xpseudo_asm_gcc.h b/bsp_z7/ps7_cortexa9_0/include/xpseudo_asm_gcc.h index b8517d3..5721b4c 100644 --- a/bsp_z7/ps7_cortexa9_0/include/xpseudo_asm_gcc.h +++ b/bsp_z7/ps7_cortexa9_0/include/xpseudo_asm_gcc.h @@ -1,6 +1,6 @@ /****************************************************************************** * Copyright (c) 2014 - 2022 Xilinx, Inc. All rights reserved. -* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved. +* Copyright (c) 2022 - 2024 Advanced Micro Devices, Inc. All rights reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -23,6 +23,7 @@ * 7.2 dp 04/30/20 Added clobber "cc" to mtcpsr for aarch32 processors * 8.0 mus 02/24/22 Added macro mfcpnotoken and mtcpnotoken. * 8.1 asa 02/13/23 Create macros to read ESR, FAR and ELR registers. +* 9.1 ml 11/15/23 Fix compilation errors reported with -std=c2x compiler flag * * ******************************************************************************/ @@ -56,9 +57,9 @@ extern "C" { #if defined (__aarch64__) /* pseudo assembler instructions */ #define mfcpsr() ({u32 rval = 0U; \ - asm volatile("mrs %0, DAIF" : "=r" (rval));\ - rval;\ - }) + __asm volatile("mrs %0, DAIF" : "=r" (rval));\ + rval;\ + }) #define mtcpsr(v) __asm__ __volatile__ ("msr DAIF, %0" : : "r" (v)) @@ -68,12 +69,10 @@ extern "C" { #define cpsief() //__asm__ __volatile__("cpsie f\n") #define cpsidf() //__asm__ __volatile__("cpsid f\n") - - #define mtgpr(rn, v) /*__asm__ __volatile__(\ "mov r" stringify(rn) ", %0 \n"\ : : "r" (v)\ - )*/ +)*/ #define mfgpr(rn) /*({u32 rval; \ __asm__ __volatile__(\ @@ -81,7 +80,7 @@ extern "C" { : "=r" (rval)\ );\ rval;\ - })*/ +})*/ /* memory synchronization operations */ @@ -94,47 +93,45 @@ extern "C" { /* Data Memory Barrier */ #define dmb() __asm__ __volatile__("dmb sy") - /* Memory Operations */ #define ldr(adr) ({u64 rval; \ - __asm__ __volatile__(\ - "ldr %0,[%1]"\ - : "=r" (rval) : "r" (adr)\ - );\ - rval;\ - }) + __asm__ __volatile__(\ + "ldr %0,[%1]"\ + : "=r" (rval) : "r" (adr)\ + );\ + rval;\ + }) #if (EL3 == 1) #define mfelrel3() ({u64 rval = 0U; \ - asm volatile("mrs %0, ELR_EL3" : "=r" (rval));\ - rval;\ - }) + __asm volatile("mrs %0, ELR_EL3" : "=r" (rval));\ + rval;\ + }) #define mfesrel3() ({u64 rval = 0U; \ - asm volatile("mrs %0, ESR_EL3" : "=r" (rval));\ - rval;\ - }) + __asm volatile("mrs %0, ESR_EL3" : "=r" (rval));\ + rval;\ + }) #define mffarel3() ({u64 rval = 0U; \ - asm volatile("mrs %0, FAR_EL3" : "=r" (rval));\ - rval;\ - }) + __asm volatile("mrs %0, FAR_EL3" : "=r" (rval));\ + rval;\ + }) #else #define mfelrel1() ({u64 rval = 0U; \ - asm volatile("mrs %0, ELR_EL1" : "=r" (rval));\ - rval;\ - }) + __asm volatile("mrs %0, ELR_EL1" : "=r" (rval));\ + rval;\ + }) #define mfesrel1() ({u64 rval = 0U; \ - asm volatile("mrs %0, ESR_EL1" : "=r" (rval));\ - rval;\ - }) + __asm volatile("mrs %0, ESR_EL1" : "=r" (rval));\ + rval;\ + }) #define mffarel1() ({u64 rval = 0U; \ - asm volatile("mrs %0, FAR_EL1" : "=r" (rval));\ - rval;\ - }) - + __asm volatile("mrs %0, FAR_EL1" : "=r" (rval));\ + rval;\ + }) #endif @@ -144,17 +141,17 @@ extern "C" { /* pseudo assembler instructions */ #define mfcpsr() ({u32 rval = 0U; \ - __asm__ __volatile__(\ - "mrs %0, cpsr\n"\ - : "=r" (rval)\ - );\ - rval;\ - }) + __asm__ __volatile__(\ + "mrs %0, cpsr\n"\ + : "=r" (rval)\ + );\ + rval;\ + }) #define mtcpsr(v) __asm__ __volatile__(\ - "msr cpsr,%0\n"\ - : : "r" (v) : "cc" \ - ) + "msr cpsr,%0\n"\ + : : "r" (v) : "cc" \ + ) #define cpsiei() __asm__ __volatile__("cpsie i\n") #define cpsidi() __asm__ __volatile__("cpsid i\n") @@ -162,20 +159,18 @@ extern "C" { #define cpsief() __asm__ __volatile__("cpsie f\n") #define cpsidf() __asm__ __volatile__("cpsid f\n") - - #define mtgpr(rn, v) __asm__ __volatile__(\ - "mov r" stringify(rn) ", %0 \n"\ - : : "r" (v)\ - ) + "mov r" stringify(rn) ", %0 \n"\ + : : "r" (v)\ + ) #define mfgpr(rn) ({u32 rval; \ - __asm__ __volatile__(\ - "mov %0,r" stringify(rn) "\n"\ - : "=r" (rval)\ - );\ - rval;\ - }) + __asm__ __volatile__(\ + "mov %0,r" stringify(rn) "\n"\ + : "=r" (rval)\ + );\ + rval;\ + }) /* memory synchronization operations */ @@ -188,44 +183,43 @@ extern "C" { /* Data Memory Barrier */ #define dmb() __asm__ __volatile__ ("dmb" : : : "memory") - /* Memory Operations */ #define ldr(adr) ({u32 rval; \ - __asm__ __volatile__(\ - "ldr %0,[%1]"\ - : "=r" (rval) : "r" (adr)\ - );\ - rval;\ - }) + __asm__ __volatile__(\ + "ldr %0,[%1]"\ + : "=r" (rval) : "r" (adr)\ + );\ + rval;\ + }) #endif #define ldrb(adr) ({u8 rval; \ - __asm__ __volatile__(\ - "ldrb %0,[%1]"\ - : "=r" (rval) : "r" (adr)\ - );\ - rval;\ - }) + __asm__ __volatile__(\ + "ldrb %0,[%1]"\ + : "=r" (rval) : "r" (adr)\ + );\ + rval;\ + }) #define strw(adr, val) __asm__ __volatile__(\ - "str %0,[%1]\n"\ - : : "r" (val), "r" (adr)\ - ) + "str %0,[%1]\n"\ + : : "r" (val), "r" (adr)\ + ) #define strb(adr, val) __asm__ __volatile__(\ - "strb %0,[%1]\n"\ - : : "r" (val), "r" (adr)\ - ) + "strb %0,[%1]\n"\ + : : "r" (val), "r" (adr)\ + ) /* Count leading zeroes (clz) */ #define clz(arg) ({u8 rval; \ - __asm__ __volatile__(\ - "clz %0,%1"\ - : "=r" (rval) : "r" (arg)\ - );\ - rval;\ - }) + __asm__ __volatile__(\ + "clz %0,%1"\ + : "=r" (rval) : "r" (arg)\ + );\ + rval;\ + }) #if defined (__aarch64__) #define mtcpdc(reg,val) __asm__ __volatile__("dc " #reg ",%0" : : "r" (val)) @@ -236,14 +230,14 @@ extern "C" { #define mtcpat(reg,val) __asm__ __volatile__("at " #reg ",%0" : : "r" (val)) /* CP15 operations */ #define mfcp(reg) ({u64 rval = 0U;\ - __asm__ __volatile__("mrs %0, " #reg : "=r" (rval));\ - rval;\ - }) + __asm__ __volatile__("mrs %0, " #reg : "=r" (rval));\ + rval;\ + }) #define mfcpnotoken(reg) ({u64 rval = 0U;\ - __asm__ __volatile__("mrs %0, " reg : "=r" (rval));\ - rval;\ - }) + __asm__ __volatile__("mrs %0, " reg : "=r" (rval));\ + rval;\ + }) #define mtcp(reg,val) __asm__ __volatile__("msr " #reg ",%0" : : "r" (val)) #define mtcpnotoken(reg,val) __asm__ __volatile__("msr " reg ",%0" : : "r" (val)) @@ -251,22 +245,22 @@ extern "C" { #else /* CP15 operations */ #define mtcp(rn, v) __asm__ __volatile__(\ - "mcr " rn "\n"\ - : : "r" (v)\ - ); + "mcr " rn "\n"\ + : : "r" (v)\ + ); #define mfcp(rn) ({u32 rval = 0U; \ - __asm__ __volatile__(\ - "mrc " rn "\n"\ - : "=r" (rval)\ - );\ - rval;\ - }) + __asm__ __volatile__(\ + "mrc " rn "\n"\ + : "=r" (rval)\ + );\ + rval;\ + }) #define mtcp2(rn, v) __asm__ __volatile__(\ - "mcrr " rn "\n"\ - : : "r" (v), "r" (0)\ - ); + "mcrr " rn "\n"\ + : : "r" (v), "r" (0)\ + ); #endif diff --git a/bsp_z7/ps7_cortexa9_0/include/xqspips.h b/bsp_z7/ps7_cortexa9_0/include/xqspips.h index d7bae80..11540d1 100644 --- a/bsp_z7/ps7_cortexa9_0/include/xqspips.h +++ b/bsp_z7/ps7_cortexa9_0/include/xqspips.h @@ -1,5 +1,6 @@ /****************************************************************************** * Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (C) 2023 - 2024 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -7,7 +8,7 @@ /** * * @file xqspips.h -* @addtogroup qspips_v3_10 +* @addtogroup qspips Overview * @{ * @details * @@ -270,6 +271,8 @@ * XQspiPs_InterruptHandler() APIs to fill TX FIFO with valid * data when RX buffer is not NULL. * 3.8 akm 09/02/20 Updated the Makefile to support parallel make execution. +* 3.11 akm 07/10/23 Update the driver to support for system device-tree flow. +* 3.12 sb 02/20/24 Add missing parenthesis for macro expansions. * * * @@ -478,16 +481,26 @@ extern "C" { * requested if the status event indicates an error. */ typedef void (*XQspiPs_StatusHandler) (void *CallBackRef, u32 StatusEvent, - unsigned ByteCount); + unsigned ByteCount); /** * This typedef contains configuration information for the device. */ typedef struct { +#ifndef SDT u16 DeviceId; /**< Unique ID of device */ +#else + char *Name; +#endif u32 BaseAddress; /**< Base address of the device */ u32 InputClockHz; /**< Input clock frequency */ u8 ConnectionMode; /**< Single, Stacked and Parallel mode */ +#ifdef SDT + u32 IntrId; /**< Bits[11:0] Interrupt-id Bits[15:12] + * trigger type and level flags */ + UINTPTR IntrParent; /**< Bit[0] Interrupt parent type Bit[64/32:1] + * Parent base address */ +#endif } XQspiPs_Config; /** @@ -571,7 +584,7 @@ typedef struct { *****************************************************************************/ #define XQspiPs_SetSlaveIdle(InstancePtr, RegisterValue) \ XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + \ - XQSPIPS_SICR_OFFSET, (RegisterValue)) + XQSPIPS_SICR_OFFSET, (RegisterValue)) /****************************************************************************/ /** @@ -589,7 +602,7 @@ typedef struct { *****************************************************************************/ #define XQspiPs_GetSlaveIdle(InstancePtr) \ XQspiPs_In32(((InstancePtr)->Config.BaseAddress) + \ - XQSPIPS_SICR_OFFSET) + XQSPIPS_SICR_OFFSET) /****************************************************************************/ /** @@ -608,7 +621,7 @@ typedef struct { *****************************************************************************/ #define XQspiPs_SetTXWatermark(InstancePtr, RegisterValue) \ XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + \ - XQSPIPS_TXWR_OFFSET, (RegisterValue)) + XQSPIPS_TXWR_OFFSET, (RegisterValue)) /****************************************************************************/ /** @@ -625,7 +638,7 @@ typedef struct { * *****************************************************************************/ #define XQspiPs_GetTXWatermark(InstancePtr) \ - XQspiPs_In32((InstancePtr->Config.BaseAddress) + XQSPIPS_TXWR_OFFSET) + XQspiPs_In32(((InstancePtr)->Config.BaseAddress) + XQSPIPS_TXWR_OFFSET) /****************************************************************************/ /** @@ -644,7 +657,7 @@ typedef struct { *****************************************************************************/ #define XQspiPs_SetRXWatermark(InstancePtr, RegisterValue) \ XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + \ - XQSPIPS_RXWR_OFFSET, (RegisterValue)) + XQSPIPS_RXWR_OFFSET, (RegisterValue)) /****************************************************************************/ /** @@ -661,7 +674,7 @@ typedef struct { * *****************************************************************************/ #define XQspiPs_GetRXWatermark(InstancePtr) \ - XQspiPs_In32((InstancePtr->Config.BaseAddress) + XQSPIPS_RXWR_OFFSET) + XQspiPs_In32(((InstancePtr)->Config.BaseAddress) + XQSPIPS_RXWR_OFFSET) /****************************************************************************/ /** @@ -677,8 +690,8 @@ typedef struct { * *****************************************************************************/ #define XQspiPs_Enable(InstancePtr) \ - XQspiPs_Out32((InstancePtr->Config.BaseAddress) + XQSPIPS_ER_OFFSET, \ - XQSPIPS_ER_ENABLE_MASK) + XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + XQSPIPS_ER_OFFSET, \ + XQSPIPS_ER_ENABLE_MASK) /****************************************************************************/ /** @@ -694,7 +707,7 @@ typedef struct { * *****************************************************************************/ #define XQspiPs_Disable(InstancePtr) \ - XQspiPs_Out32((InstancePtr->Config.BaseAddress) + XQSPIPS_ER_OFFSET, 0) + XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + XQSPIPS_ER_OFFSET, 0) /****************************************************************************/ /** @@ -714,7 +727,7 @@ typedef struct { *****************************************************************************/ #define XQspiPs_SetLqspiConfigReg(InstancePtr, RegisterValue) \ XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + \ - XQSPIPS_LQSPI_CR_OFFSET, (RegisterValue)) + XQSPIPS_LQSPI_CR_OFFSET, (RegisterValue)) /****************************************************************************/ /** @@ -731,35 +744,39 @@ typedef struct { * *****************************************************************************/ #define XQspiPs_GetLqspiConfigReg(InstancePtr) \ - XQspiPs_In32((InstancePtr->Config.BaseAddress) + \ - XQSPIPS_LQSPI_CR_OFFSET) + XQspiPs_In32(((InstancePtr)->Config.BaseAddress) + \ + XQSPIPS_LQSPI_CR_OFFSET) /************************** Function Prototypes ******************************/ /* * Initialization function, implemented in xqspips_sinit.c */ +#ifndef SDT XQspiPs_Config *XQspiPs_LookupConfig(u16 DeviceId); +#else +XQspiPs_Config *XQspiPs_LookupConfig(UINTPTR BaseAddress); +#endif /* * Functions implemented in xqspips.c */ int XQspiPs_CfgInitialize(XQspiPs *InstancePtr, XQspiPs_Config *Config, - u32 EffectiveAddr); + u32 EffectiveAddr); void XQspiPs_Reset(XQspiPs *InstancePtr); void XQspiPs_Abort(XQspiPs *InstancePtr); s32 XQspiPs_Transfer(XQspiPs *InstancePtr, u8 *SendBufPtr, u8 *RecvBufPtr, - u32 ByteCount); + u32 ByteCount); s32 XQspiPs_PolledTransfer(XQspiPs *InstancePtr, u8 *SendBufPtr, - u8 *RecvBufPtr, u32 ByteCount); + u8 *RecvBufPtr, u32 ByteCount); int XQspiPs_LqspiRead(XQspiPs *InstancePtr, u8 *RecvBufPtr, - u32 Address, unsigned ByteCount); + u32 Address, unsigned ByteCount); int XQspiPs_SetSlaveSelect(XQspiPs *InstancePtr); void XQspiPs_SetStatusHandler(XQspiPs *InstancePtr, void *CallBackRef, - XQspiPs_StatusHandler FuncPtr); + XQspiPs_StatusHandler FuncPtr); void XQspiPs_InterruptHandler(void *InstancePtr); /* @@ -777,9 +794,9 @@ s32 XQspiPs_SetClkPrescaler(XQspiPs *InstancePtr, u8 Prescaler); u8 XQspiPs_GetClkPrescaler(XQspiPs *InstancePtr); int XQspiPs_SetDelays(XQspiPs *InstancePtr, u8 DelayNss, u8 DelayBtwn, - u8 DelayAfter, u8 DelayInit); + u8 DelayAfter, u8 DelayInit); void XQspiPs_GetDelays(XQspiPs *InstancePtr, u8 *DelayNss, u8 *DelayBtwn, - u8 *DelayAfter, u8 *DelayInit); + u8 *DelayAfter, u8 *DelayInit); #ifdef __cplusplus } #endif diff --git a/bsp_z7/ps7_cortexa9_0/include/xqspips_hw.h b/bsp_z7/ps7_cortexa9_0/include/xqspips_hw.h index ab50675..a136a2f 100644 --- a/bsp_z7/ps7_cortexa9_0/include/xqspips_hw.h +++ b/bsp_z7/ps7_cortexa9_0/include/xqspips_hw.h @@ -1,5 +1,6 @@ /****************************************************************************** * Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -7,7 +8,7 @@ /** * * @file xqspips_hw.h -* @addtogroup qspips_v3_10 +* @addtogroup qspips Overview * @{ * * This header file contains the identifiers and basic HW access driver @@ -117,18 +118,18 @@ extern "C" { /* Deselect the Slave select line and set the transfer size to 32 at reset */ #define XQSPIPS_CR_RESET_MASK_SET XQSPIPS_CR_IFMODE_MASK | \ - XQSPIPS_CR_SSCTRL_MASK | \ - XQSPIPS_CR_DATA_SZ_MASK | \ - XQSPIPS_CR_MSTREN_MASK | \ - XQSPIPS_CR_SSFORCE_MASK | \ - XQSPIPS_CR_HOLD_B_MASK + XQSPIPS_CR_SSCTRL_MASK | \ + XQSPIPS_CR_DATA_SZ_MASK | \ + XQSPIPS_CR_MSTREN_MASK | \ + XQSPIPS_CR_SSFORCE_MASK | \ + XQSPIPS_CR_HOLD_B_MASK #define XQSPIPS_CR_RESET_MASK_CLR XQSPIPS_CR_CPOL_MASK | \ - XQSPIPS_CR_CPHA_MASK | \ - XQSPIPS_CR_PRESC_MASK | \ - XQSPIPS_CR_MANSTRTEN_MASK | \ - XQSPIPS_CR_MANSTRT_MASK | \ - XQSPIPS_CR_ENDIAN_MASK | \ - XQSPIPS_CR_REF_CLK_MASK + XQSPIPS_CR_CPHA_MASK | \ + XQSPIPS_CR_PRESC_MASK | \ + XQSPIPS_CR_MANSTRTEN_MASK | \ + XQSPIPS_CR_MANSTRT_MASK | \ + XQSPIPS_CR_ENDIAN_MASK | \ + XQSPIPS_CR_REF_CLK_MASK /* @} */ diff --git a/bsp_z7/ps7_cortexa9_0/include/xreg_cortexa9.h b/bsp_z7/ps7_cortexa9_0/include/xreg_cortexa9.h index 2a4fff2..0d2c7b1 100644 --- a/bsp_z7/ps7_cortexa9_0/include/xreg_cortexa9.h +++ b/bsp_z7/ps7_cortexa9_0/include/xreg_cortexa9.h @@ -1,5 +1,6 @@ /****************************************************************************** * Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved. +* Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -20,6 +21,7 @@ * Ver Who Date Changes * ----- -------- -------- ----------------------------------------------- * 1.00a ecm/sdm 10/20/09 First release +* 9.0 mus 07/29/23 Added definitions for processor affinity register. * * ******************************************************************************/ @@ -489,7 +491,10 @@ extern "C" { #define XREG_CP15_MAIN_TLB_ATTR "cp15:5:c15:c7:2" #endif - +/* Affinity register bits */ +#define XREG_MPIDR_MASK 0xFFFFFFFFU +#define XREG_MPIDR_AFFINITY0_MASK 0x3U +#define XREG_MPIDR_AFFINITY0_SHIFT 0x0U /* MPE register definitions */ #define XREG_FPSID c0 #define XREG_FPSCR c1 diff --git a/bsp_z7/ps7_cortexa9_0/include/xscugic.h b/bsp_z7/ps7_cortexa9_0/include/xscugic.h index 0ee7342..3eb2f65 100644 --- a/bsp_z7/ps7_cortexa9_0/include/xscugic.h +++ b/bsp_z7/ps7_cortexa9_0/include/xscugic.h @@ -1,6 +1,6 @@ /****************************************************************************** * Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved. -* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved. +* Copyright (C) 2022 - 2024 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -8,56 +8,10 @@ /** * * @file xscugic.h -* @addtogroup scugic Overview +* @addtogroup scugic_api SCUGIC APIs * @{ * @details * -* The generic interrupt controller driver component. -* -* The interrupt controller driver uses the idea of priority for the various -* handlers. Priority is an integer within the range of 1 and 31 inclusive with -* default of 1 being the highest priority interrupt source. The priorities -* of the various sources can be dynamically altered as needed through -* hardware configuration. -* -* The generic interrupt controller supports the following -* features: -* -* - specific individual interrupt enabling/disabling -* - specific individual interrupt acknowledging -* - attaching specific callback function to handle interrupt source -* - assigning desired priority to interrupt source if default is not -* acceptable. -* -* Details about connecting the interrupt handler of the driver are contained -* in the source file specific to interrupt processing, xscugic_intr.c. -* -* This driver is intended to be RTOS and processor independent. It works with -* physical addresses only. Any needs for dynamic memory management, threads -* or thread mutual exclusion, virtual memory, or cache control must be -* satisfied by the layer above this driver. -* -* Interrupt Vector Tables -* -* The device ID of the interrupt controller device is used by the driver as a -* direct index into the configuration data table. The user should populate the -* vector table with handlers and callbacks at run-time using the -* XScuGic_Connect() and XScuGic_Disconnect() functions. -* -* Each vector table entry corresponds to a device that can generate an -* interrupt. Each entry contains an interrupt handler function and an -* argument to be passed to the handler when an interrupt occurs. The -* user must use XScuGic_Connect() when the interrupt handler takes an -* argument other than the base address. -* -* Nested Interrupts Processing -* -* Nested interrupts are not supported by this driver. -* -* NOTE: -* The generic interrupt controller is not a part of the snoop control unit -* as indicated by the prefix "scu" in the name of the driver. -* It is an independent module in APU. * * 
 * MODIFICATION HISTORY:
@@ -190,12 +144,14 @@
 *                     executed, redistributor address will be stored in newly
 *                     added member of XScuGic data structure "RedistBaseAddr".
 *                     It fixes CR#1150432.
+* 5.2   ml   03/02/23 Add description to fix Doxygen warnings.
+* 5.2   adk  04/14/23 Added support for system device-tree flow.
 *
* ******************************************************************************/ -#ifndef XSCUGIC_H /* prevent circular inclusions */ -#define XSCUGIC_H /* by using protection macros */ +#ifndef XSCUGIC_H /**< prevent circular inclusions */ +#define XSCUGIC_H /**< by using protection macros */ #ifdef __cplusplus extern "C" { @@ -212,13 +168,23 @@ extern "C" { /************************** Constant Definitions *****************************/ +/** + * @name EFUSE status Register information + * EFUSE Status Register + * @{ + */ #define EFUSE_STATUS_OFFSET 0x10 #define EFUSE_STATUS_CPU_MASK 0x80 #if !defined (ARMR5) && !defined (__aarch64__) && !defined (ARMA53_32) -#define ARMA9 +#define ARMA9 /**< ARMA9 macro to identify cortexA9 */ #endif +/** + * @name GICD_CTLR Register information + * GICD_CTLR Status Register + * @{ + */ #define XSCUGIC500_DCTLR_ARE_NS_ENABLE 0x20 #define XSCUGIC500_DCTLR_ARE_S_ENABLE 0x10 @@ -245,8 +211,12 @@ extern "C" { */ typedef struct { - Xil_InterruptHandler Handler; - void *CallBackRef; + Xil_InterruptHandler Handler; /**< Interrupt Handler */ + void *CallBackRef; /**< CallBackRef is the callback reference passed in + by the upper layer when setting the Interrupt + handler for specific interrupt ID, and it will + passed back to Interrupt handler when it is + invoked. */ } XScuGic_VectorTableEntry; /** @@ -254,9 +224,15 @@ typedef struct */ typedef struct { +#ifndef SDT u16 DeviceId; /**< Unique ID of device */ u32 CpuBaseAddress; /**< CPU Interface Register base address */ u32 DistBaseAddress; /**< Distributor Register base address */ +#else + char *Name; /**< Compatible string */ + u32 DistBaseAddress; /**< Distributor Register base address */ + u32 CpuBaseAddress; /**< CPU Interface Register base address */ +#endif XScuGic_VectorTableEntry HandlerTable[XSCUGIC_MAX_NUM_INTR_INPUTS];/**< Vector table of interrupt handlers */ } XScuGic_Config; @@ -285,17 +261,16 @@ extern XScuGic_Config XScuGic_ConfigTable[]; /**< Config table */ /****************************************************************************/ /** * -* Write the given CPU Interface register +* Writes the given CPU Interface register. * -* @param InstancePtr is a pointer to the instance to be worked on. -* @param RegOffset is the register offset to be written -* @param Data is the 32-bit value to write to the register +* @param InstancePtr Pointer to the instance to be worked on. +* @param RegOffset Register offset to be written. +* @param Data 32-bit value to write to the register. * * @return None. * -* @note -* C-style signature: -* void XScuGic_CPUWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data) +* @note C-style signature: +* void XScuGic_CPUWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data) * *****************************************************************************/ #define XScuGic_CPUWriteReg(InstancePtr, RegOffset, Data) \ @@ -305,16 +280,15 @@ extern XScuGic_Config XScuGic_ConfigTable[]; /**< Config table */ /****************************************************************************/ /** * -* Read the given CPU Interface register +* Reads the given CPU Interface register. * -* @param InstancePtr is a pointer to the instance to be worked on. -* @param RegOffset is the register offset to be read +* @param InstancePtr Pointer to the instance to be worked on. +* @param RegOffset Rregister offset to be read. * -* @return The 32-bit value of the register +* @return 32-bit value of the register * -* @note -* C-style signature: -* u32 XScuGic_CPUReadReg(XScuGic *InstancePtr, u32 RegOffset) +* @note C-style signature: +* u32 XScuGic_CPUReadReg(XScuGic *InstancePtr, u32 RegOffset) * *****************************************************************************/ #define XScuGic_CPUReadReg(InstancePtr, RegOffset) \ @@ -323,17 +297,16 @@ extern XScuGic_Config XScuGic_ConfigTable[]; /**< Config table */ /****************************************************************************/ /** * -* Write the given Distributor Interface register +* Writes the given Distributor Interface register. * -* @param InstancePtr is a pointer to the instance to be worked on. -* @param RegOffset is the register offset to be written -* @param Data is the 32-bit value to write to the register +* @param InstancePtr Pointer to the instance to be worked on. +* @param RegOffset Register offset to be written. +* @param Data 32-bit value to write to the register. * * @return None. * -* @note -* C-style signature: -* void XScuGic_DistWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data) +* @note C-style signature: +* void XScuGic_DistWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data) * *****************************************************************************/ #define XScuGic_DistWriteReg(InstancePtr, RegOffset, Data) \ @@ -343,16 +316,15 @@ extern XScuGic_Config XScuGic_ConfigTable[]; /**< Config table */ /****************************************************************************/ /** * -* Read the given Distributor Interface register +* Reads the given Distributor Interface register * -* @param InstancePtr is a pointer to the instance to be worked on. -* @param RegOffset is the register offset to be read +* @param InstancePtr Pointer to the instance to be worked on. +* @param RegOffset Register offset to be read. * -* @return The 32-bit value of the register +* @return The 32-bit value of the register. * -* @note -* C-style signature: -* u32 XScuGic_DistReadReg(XScuGic *InstancePtr, u32 RegOffset) +* @note C-style signature: +* u32 XScuGic_DistReadReg(XScuGic *InstancePtr, u32 RegOffset) * *****************************************************************************/ #define XScuGic_DistReadReg(InstancePtr, RegOffset) \ @@ -362,17 +334,16 @@ extern XScuGic_Config XScuGic_ConfigTable[]; /**< Config table */ /****************************************************************************/ /** * -* Write the given ReDistributor Interface register +* Writes the given ReDistributor Interface register. * -* @param InstancePtr is a pointer to the instance to be worked on. -* @param RegOffset is the register offset to be written -* @param Data is the 32-bit value to write to the register +* @param InstancePtr Pointer to the instance to be worked on. +* @param RegOffset Register offset to be written. +* @param Data 32-bit value to write to the register. * * @return None. * -* @note -* C-style signature: -* void XScuGic_DistWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data) +* @note C-style signature: +* void XScuGic_DistWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data) * *****************************************************************************/ #define XScuGic_ReDistWriteReg(InstancePtr, RegOffset, Data) \ @@ -381,16 +352,15 @@ extern XScuGic_Config XScuGic_ConfigTable[]; /**< Config table */ /****************************************************************************/ /** * -* Read the given ReDistributor Interface register +* Reads the given ReDistributor Interface register. * -* @param InstancePtr is a pointer to the instance to be worked on. -* @param RegOffset is the register offset to be read +* @param InstancePtr Pointer to the instance to be worked on. +* @param RegOffset Register offset to be read. * -* @return The 32-bit value of the register +* @return 32-bit value of the register. * -* @note -* C-style signature: -* u32 XScuGic_DistReadReg(XScuGic *InstancePtr, u32 RegOffset) +* @note C-style signature: +* u32 XScuGic_DistReadReg(XScuGic *InstancePtr, u32 RegOffset) * *****************************************************************************/ #define XScuGic_ReDistReadReg(InstancePtr, RegOffset) \ @@ -399,17 +369,16 @@ extern XScuGic_Config XScuGic_ConfigTable[]; /**< Config table */ /****************************************************************************/ /** * -* Write the given ReDistributor SGI PPI Interface register +* Writes the given ReDistributor SGI PPI Interface register. * -* @param InstancePtr is a pointer to the instance to be worked on. -* @param RegOffset is the register offset to be written -* @param Data is the 32-bit value to write to the register +* @param InstancePtr Pointer to the instance to be worked on. +* @param RegOffset Register offset to be written. +* @param Data 32-bit value to write to the register. * * @return None. * -* @note -* C-style signature: -* void XScuGic_DistWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data) +* @note C-style signature: +* void XScuGic_DistWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data) * *****************************************************************************/ #define XScuGic_ReDistSGIPPIWriteReg(InstancePtr, RegOffset, Data) \ @@ -419,16 +388,15 @@ extern XScuGic_Config XScuGic_ConfigTable[]; /**< Config table */ /****************************************************************************/ /** * -* Read the given ReDistributor SGI PPI Interface register +* Reads the given ReDistributor SGI PPI Interface register * -* @param InstancePtr is a pointer to the instance to be worked on. -* @param RegOffset is the register offset to be read +* @param InstancePtr Pointer to the instance to be worked on. +* @param RegOffset Register offset to be read. * * @return The 32-bit value of the register * -* @note -* C-style signature: -* u32 XScuGic_DistReadReg(XScuGic *InstancePtr, u32 RegOffset) +* @note C-style signature: +* u32 XScuGic_DistReadReg(XScuGic *InstancePtr, u32 RegOffset) * *****************************************************************************/ #define XScuGic_ReDistSGIPPIReadReg(InstancePtr, RegOffset) \ @@ -443,9 +411,12 @@ extern XScuGic_Config XScuGic_ConfigTable[]; /**< Config table */ #define XREG_ICC_SGI1R_EL1 "p15, 0, %0, %1, c12" #define XREG_ICC_PMR_EL1 "p15, 0, %0, c4, c6, 0" #define XREG_ICC_IAR0_EL1 "p15, 0, %0, c12, c8, 0" +#define XREG_ICC_IAR1_EL1 "p15, 0, %0, c12, c12, 0" #define XREG_ICC_EOIR0_EL1 "p15, 0, %0, c12, c8, 1" +#define XREG_ICC_EOIR1_EL1 "p15, 0, %0, c12, c12, 1" #define XREG_IMP_CBAR "p15, 1, %0, c15, c3, 0" #define XREG_ICC_BPR0_EL1 "p15, 0, %0, c12, c8, 3" +#define XREG_ICC_BPR1_EL1 "p15, 0, %0, c12, c12, 3" #define XREG_ICC_RPR_EL1 "p15, 0, %0, c12, c11, 3" #else #define XREG_ICC_SRE_EL1 "S3_0_C12_C12_5" @@ -463,13 +434,12 @@ extern XScuGic_Config XScuGic_ConfigTable[]; /**< Config table */ #endif /****************************************************************************/ /** -* This function enables system register interface for GIC CPU Interface +* Enables system register interface for GIC CPU Interface. * -* @param value to be written +* @param value Value to be written. * * @return None. * -* @note None. * *****************************************************************************/ #if defined (__aarch64__) @@ -480,13 +450,12 @@ extern XScuGic_Config XScuGic_ConfigTable[]; /**< Config table */ #endif /****************************************************************************/ /** -* This function enables Grou0 interrupts +* Enable Grou0 interrupts. * * @param None. * * @return None. * -* @note None. * *****************************************************************************/ #if defined(ARMR52) @@ -502,7 +471,6 @@ extern XScuGic_Config XScuGic_ConfigTable[]; /**< Config table */ * * @return None. * -* @note None. * *****************************************************************************/ #if defined (ARMR52) @@ -518,13 +486,12 @@ extern XScuGic_Config XScuGic_ConfigTable[]; /**< Config table */ #endif /****************************************************************************/ /** -* This function writes to ICC_SGI0R_EL1 +* Writes to ICC_SGI0R_EL1. * -* @param value to be written +* @param value Value to be written. * * @return None. * -* @note None. * *****************************************************************************/ #if defined(ARMR52) @@ -535,13 +502,12 @@ extern XScuGic_Config XScuGic_ConfigTable[]; /**< Config table */ /****************************************************************************/ /** -* This function writes to ICC_SGI1R_EL1 +* Writes to ICC_SGI1R_EL1. * -* @param value to be written +* @param value Value to be written. * * @return None. * -* @note None. * *****************************************************************************/ #if defined(ARMR52) @@ -552,13 +518,12 @@ extern XScuGic_Config XScuGic_ConfigTable[]; /**< Config table */ /****************************************************************************/ /** -* This function reads ICC_SGI1R_EL1 register +* Reads ICC_SGI1R_EL1 register. * * @param None * * @return Value of ICC_SGI1R_EL1 register * -* @note None. * *****************************************************************************/ #if defined (ARMR52) @@ -568,13 +533,12 @@ extern XScuGic_Config XScuGic_ConfigTable[]; /**< Config table */ #endif /****************************************************************************/ /** -* This function sets interrupt priority filter +* Sets interrupt priority filter. * * @param None. * * @return None. * -* @note None. * *****************************************************************************/ #if defined (ARMR52) @@ -584,17 +548,16 @@ extern XScuGic_Config XScuGic_ConfigTable[]; /**< Config table */ #endif /****************************************************************************/ /** -* This function returns interrupt id of highest priority pending interrupt +* Returns interrupt ID of highest priority pending interrupt. * * @param None. * * @return None. * -* @note None. * *****************************************************************************/ #if defined(ARMR52) -#define XScuGic_get_IntID() mfcp(XREG_ICC_IAR0_EL1) +#define XScuGic_get_IntID() mfcp(XREG_ICC_IAR1_EL1) #elif EL3 #define XScuGic_get_IntID() mfcpnotoken(XREG_ICC_IAR0_EL1) #else @@ -602,17 +565,16 @@ extern XScuGic_Config XScuGic_ConfigTable[]; /**< Config table */ #endif /****************************************************************************/ /** -* This function acks the interrupt +* Acknowledges the interrupt. * * @param None. * * @return None. * -* @note None. * *****************************************************************************/ #if defined(ARMR52) -#define XScuGic_ack_Int(val) mtcp(XREG_ICC_EOIR0_EL1,val) +#define XScuGic_ack_Int(val) mtcp(XREG_ICC_EOIR1_EL1,val) #elif EL3 #define XScuGic_ack_Int(val) mtcpnotoken(XREG_ICC_EOIR0_EL1,val) #else @@ -627,7 +589,6 @@ extern XScuGic_Config XScuGic_ConfigTable[]; /**< Config table */ * * @return None. * -* @note None. * *****************************************************************************/ #define XScuGic_Get_Rdist_Int_Trigger_Index(IntrId) ((Int_Id%16) * 2U) @@ -660,12 +621,23 @@ void XScuGic_UnmapAllInterruptsFromCpu(XScuGic *InstancePtr, u8 Cpu_Identifier); void XScuGic_Stop(XScuGic *InstancePtr); void XScuGic_SetCpuID(u32 CpuCoreId); u32 XScuGic_GetCpuID(void); +#ifndef SDT u8 XScuGic_IsInitialized(u32 DeviceId); +#else +u8 XScuGic_IsInitialized(u32 BaseAddress); +#endif +#ifndef SDT /* - * Initialization functions in xscugic_sinit.c + * Lookup configuration by using DeviceId */ XScuGic_Config *XScuGic_LookupConfig(u16 DeviceId); +/* + * Lookup configuration by using BaseAddress + */ XScuGic_Config *XScuGic_LookupConfigBaseAddr(UINTPTR BaseAddress); +#else +XScuGic_Config *XScuGic_LookupConfig(UINTPTR BaseAddr); +#endif /* * Interrupt functions in xscugic_intr.c @@ -685,5 +657,6 @@ void XScuGic_MarkCoreAwake(XScuGic *InstancePtr); } #endif -#endif /* end of protection macro */ +#endif +/* end of protection macro */ /** @} */ diff --git a/bsp_z7/ps7_cortexa9_0/include/xscugic_hw.h b/bsp_z7/ps7_cortexa9_0/include/xscugic_hw.h index 0bbd0c4..90637a2 100644 --- a/bsp_z7/ps7_cortexa9_0/include/xscugic_hw.h +++ b/bsp_z7/ps7_cortexa9_0/include/xscugic_hw.h @@ -1,6 +1,6 @@ /****************************************************************************** * Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved. -* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved. +* Copyright (C) 2022 - 2024 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -8,11 +8,11 @@ /** * * @file xscugic_hw.h -* @addtogroup scugic Overview +* @addtogroup scugic_api SCUGIC APIs * @{ * -* This header file contains identifiers and HW access functions (or -* macros) that can be used to access the device. The user should refer to the +* The xscugic_hw.h header file contains identifiers and hardware access functions (or +* macros) that can be used to access the device. The user should refer to the * hardware device specification for more details of the device operation. * The driver functions/APIs are defined in xscugic.h. * @@ -69,13 +69,14 @@ * based address for specific CPU core. Also, added new macro * XScuGic_ReadReg64 to read 64 bit value from specific address. * 5.1 mus 02/15/23 Added support for VERSAL_NET APU and RPU GIC. -* +* 5.2 ml 03/02/23 Add description to fix Doxygen warnings. +* 5.2 mus 03/26/23 Fixed calculation for XSCUGIC_RDIST_INT_PRIORITY_OFFSET_CALC. * * ******************************************************************************/ -#ifndef XSCUGIC_HW_H /* prevent circular inclusions */ -#define XSCUGIC_HW_H /* by using protection macros */ +#ifndef XSCUGIC_HW_H /**< prevent circular inclusions */ +#define XSCUGIC_HW_H /**< by using protection macros */ #ifdef __cplusplus extern "C" { @@ -110,24 +111,31 @@ extern "C" { * The maximum number of interrupts supported by the hardware. */ #ifdef PLATFORM_ZYNQ -#define XSCUGIC_MAX_NUM_INTR_INPUTS 95U /* Maximum number of interrupt defined by Zynq */ +#define XSCUGIC_MAX_NUM_INTR_INPUTS 95U /**< Maximum number of + interrupt defined by + Zynq */ #elif defined (VERSAL_NET) -#define XSCUGIC_MAX_NUM_INTR_INPUTS 256U /* Maximum number of interrupt sources in VERSAL NET */ +#define XSCUGIC_MAX_NUM_INTR_INPUTS 256U /**< Maximum number of + interrupt sources in + VERSAL NET */ #elif defined (versal) -#define XSCUGIC_MAX_NUM_INTR_INPUTS 192U +#define XSCUGIC_MAX_NUM_INTR_INPUTS 192U /**< Maximum number of + interrupt sources in + VERSAL */ #else -#define XSCUGIC_MAX_NUM_INTR_INPUTS 195U /* Maximum number of interrupt defined by Zynq Ultrascale Mp */ +#define XSCUGIC_MAX_NUM_INTR_INPUTS 195U /**< Maximum number of + interrupt defined by + Zynq Ultrascale Mp */ #endif -/* - * First Interrupt Id for SPI interrupts. - */ -#define XSCUGIC_SPI_INT_ID_START 0x20U -/* - * The maximum priority value that can be used in the GIC. - */ -#define XSCUGIC_MAX_INTR_PRIO_VAL 248U -#define XSCUGIC_INTR_PRIO_MASK 0x000000F8U +#define XSCUGIC_SPI_INT_ID_START 0x20U /**< First Interrupt Id for + SPI interrupts. */ + +#define XSCUGIC_MAX_INTR_PRIO_VAL 248U /**< The maximum priority value + that can be used in + the GIC. */ +#define XSCUGIC_INTR_PRIO_MASK 0x000000F8U /**< The Interrupt + priority mask value */ /** @name Distributor Interface Register Map * @@ -338,7 +346,7 @@ extern "C" { * There are up to 255 of these registers staring at location 0xC08. * @{ */ -#define XSCUGIC_INT_CFG_MASK 0x00000003U /**< */ +#define XSCUGIC_INT_CFG_MASK 0x00000003U /**< Interrupt configuration Mask */ /* @} */ /** @name PPI Status Register @@ -523,6 +531,7 @@ extern "C" { #define XSCUGIC_RDIST_ISENABLE_OFFSET 0x100U #define XSCUGIC_RDIST_IPRIORITYR_OFFSET 0x400U #define XSCUGIC_RDIST_IGROUPR_OFFSET 0x80U + #define XSCUGIC_RDIST_GRPMODR_OFFSET 0xD00U #define XSCUGIC_RDIST_INT_CONFIG_OFFSET 0xC00U #define XSCUGIC_RDIST_TYPER_OFFSET 0x8U @@ -535,7 +544,7 @@ extern "C" { /* * GICR_IGROUPR register definitions */ -#if (defined(ARMR52) || EL3) +#if EL3 #define XSCUGIC_DEFAULT_SECURITY 0x0U #else #define XSCUGIC_DEFAULT_SECURITY 0xFFFFFFFFU @@ -551,13 +560,12 @@ extern "C" { /****************************************************************************/ /** * -* Read the Interrupt Configuration Register offset for an interrupt id. +* Reads the Interrupt Configuration Register offset for an interrupt ID. * -* @param InterruptID is the interrupt number. +* @param InterruptID Interrupt number. * * @return The 32-bit value of the offset * -* @note * *****************************************************************************/ #define XSCUGIC_INT_CFG_OFFSET_CALC(InterruptID) \ @@ -566,13 +574,12 @@ extern "C" { /****************************************************************************/ /** * -* Read the Interrupt Priority Register offset for an interrupt id. +* Reads the Interrupt Priority Register offset for an interrupt ID. * -* @param InterruptID is the interrupt number. +* @param InterruptID Interrupt number. * * @return The 32-bit value of the offset * -* @note * *****************************************************************************/ #define XSCUGIC_PRIORITY_OFFSET_CALC(InterruptID) \ @@ -581,13 +588,12 @@ extern "C" { /****************************************************************************/ /** * -* Read the Interrupt Routing Register offset for an interrupt id. +* Reads the Interrupt Routing Register offset for an interrupt ID. * -* @param InterruptID is the interrupt number. +* @param InterruptID Interrupt number. * * @return The 32-bit value of the offset * -* @note * *****************************************************************************/ #define XSCUGIC_IROUTER_OFFSET_CALC(InterruptID) \ @@ -596,13 +602,12 @@ extern "C" { /****************************************************************************/ /** * -* Read the SPI Target Register offset for an interrupt id. +* Reads the SPI Target Register offset for an interrupt ID. * -* @param InterruptID is the interrupt number. +* @param InterruptID Interrupt number. * -* @return The 32-bit value of the offset +* @return The 32-bit value of the offset. * -* @note * *****************************************************************************/ #define XSCUGIC_SPI_TARGET_OFFSET_CALC(InterruptID) \ @@ -610,13 +615,12 @@ extern "C" { /****************************************************************************/ /** * -* Read the SPI Target Register offset for an interrupt id. +* Reads the SPI Target Register offset for an interrupt ID. * -* @param InterruptID is the interrupt number. +* @param InterruptID Interrupt number. * * @return The 32-bit value of the offset * -* @note * *****************************************************************************/ #define XSCUGIC_SECURITY_TARGET_OFFSET_CALC(InterruptID) \ @@ -625,13 +629,12 @@ extern "C" { /****************************************************************************/ /** * -* Read the Re-distributor Interrupt configuration register offset +* Reads the Re-distributor Interrupt configuration register offset. * -* @param InterruptID is the interrupt number. +* @param InterruptID Interrupt number. * * @return The 32-bit value of the offset * -* @note * *****************************************************************************/ #define XSCUGIC_RDIST_INT_CONFIG_OFFSET_CALC(InterruptID) \ @@ -640,28 +643,26 @@ extern "C" { /****************************************************************************/ /** * -* Read the Re-distributor Interrupt Priority register offset +* Reads the Re-distributor Interrupt Priority register offset. * -* @param InterruptID is the interrupt number. +* @param InterruptID Interrupt number. * * @return The 32-bit value of the offset * -* @note * *****************************************************************************/ #define XSCUGIC_RDIST_INT_PRIORITY_OFFSET_CALC(InterruptID) \ - ((u32)XSCUGIC_RDIST_IPRIORITYR_OFFSET + (InterruptID * 4)) + ((u32)XSCUGIC_RDIST_IPRIORITYR_OFFSET + ((InterruptID/4) * 4)) /****************************************************************************/ /** * -* Read the Interrupt Clear-Enable Register offset for an interrupt ID +* Reads the Interrupt Clear-Enable Register offset for an interrupt ID. * -* @param Register is the register offset for the clear/enable bank. -* @param InterruptID is the interrupt number. +* @param Register Register offset for the clear/enable bank. +* @param InterruptID Interrupt number. * * @return The 32-bit value of the offset * -* @note * *****************************************************************************/ #define XSCUGIC_EN_DIS_OFFSET_CALC(Register, InterruptID) \ @@ -670,16 +671,15 @@ extern "C" { /****************************************************************************/ /** * -* Read the given Intc register. +* Reads the given Intc register. * -* @param BaseAddress is the base address of the device. -* @param RegOffset is the register offset to be read +* @param BaseAddress Base address of the device. +* @param RegOffset Register offset to be read. * * @return The 32-bit value of the register * -* @note -* C-style signature: -* u32 XScuGic_ReadReg(u32 BaseAddress, u32 RegOffset) +* @note C-style signature: +* u32 XScuGic_ReadReg(u32 BaseAddress, u32 RegOffset) * *****************************************************************************/ #define XScuGic_ReadReg(BaseAddress, RegOffset) \ @@ -688,16 +688,15 @@ extern "C" { /****************************************************************************/ /** * -* Read the given Intc register. +* Reads the given Intc register. * -* @param BaseAddress is the base address of the device. -* @param RegOffset is the register offset to be read +* @param BaseAddress Base address of the device. +* @param RegOffset Register offset to be read. * * @return The 64-bit value of the register * -* @note -* C-style signature: -* u32 XScuGic_ReadReg64(UINTPTR BaseAddress, u32 RegOffset) +* @note C-style signature: +* u32 XScuGic_ReadReg64(UINTPTR BaseAddress, u32 RegOffset) * *****************************************************************************/ #define XScuGic_ReadReg64(BaseAddress, RegOffset) \ @@ -706,17 +705,16 @@ extern "C" { /****************************************************************************/ /** * -* Write the given Intc register. +* Writes the given Intc register. * -* @param BaseAddress is the base address of the device. -* @param RegOffset is the register offset to be written -* @param Data is the 32-bit value to write to the register +* @param BaseAddress Base address of the device. +* @param RegOffset Register offset to be written +* @param Data 32-bit value to write to the register * * @return None. * -* @note -* C-style signature: -* void XScuGic_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data) +* @note C-style signature: +* void XScuGic_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data) * *****************************************************************************/ #define XScuGic_WriteReg(BaseAddress, RegOffset, Data) \ diff --git a/bsp_z7/ps7_cortexa9_0/include/xscutimer.h b/bsp_z7/ps7_cortexa9_0/include/xscutimer.h index bdce1c6..008b900 100644 --- a/bsp_z7/ps7_cortexa9_0/include/xscutimer.h +++ b/bsp_z7/ps7_cortexa9_0/include/xscutimer.h @@ -1,5 +1,6 @@ /****************************************************************************** * Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved. +* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -7,7 +8,7 @@ /** * * @file xscutimer.h -* @addtogroup scutimer_v2_4 +* @addtogroup scutimer Overview * @{ * @details * @@ -82,6 +83,7 @@ * 2.3 mus 08/31/20 Updated makefile to support parallel make and * incremental builds, it would help to reduce compilation * time. +* 2.5 dp 07/11/23 Add support for system device tree flow * * ******************************************************************************/ @@ -106,7 +108,11 @@ extern "C" { * This typedef contains configuration information for the device. */ typedef struct { +#ifndef SDT u16 DeviceId; /**< Unique ID of device */ +#else + char *Name; +#endif u32 BaseAddr; /**< Base address of the device */ #ifdef XIL_INTERRUPT u32 IntrId; @@ -145,9 +151,9 @@ typedef struct { ******************************************************************************/ #define XScuTimer_IsExpired(InstancePtr) \ ((XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \ - XSCUTIMER_ISR_OFFSET) & \ - XSCUTIMER_ISR_EVENT_FLAG_MASK) == \ - XSCUTIMER_ISR_EVENT_FLAG_MASK) + XSCUTIMER_ISR_OFFSET) & \ + XSCUTIMER_ISR_EVENT_FLAG_MASK) == \ + XSCUTIMER_ISR_EVENT_FLAG_MASK) /****************************************************************************/ /** @@ -165,8 +171,8 @@ typedef struct { ******************************************************************************/ #define XScuTimer_RestartTimer(InstancePtr) \ XScuTimer_LoadTimer((InstancePtr), \ - XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \ - XSCUTIMER_LOAD_OFFSET)) + XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \ + XSCUTIMER_LOAD_OFFSET)) /****************************************************************************/ /** @@ -186,7 +192,7 @@ typedef struct { ******************************************************************************/ #define XScuTimer_LoadTimer(InstancePtr, Value) \ XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \ - XSCUTIMER_LOAD_OFFSET, (Value)) + XSCUTIMER_LOAD_OFFSET, (Value)) /****************************************************************************/ /** @@ -204,7 +210,7 @@ typedef struct { ******************************************************************************/ #define XScuTimer_GetCounterValue(InstancePtr) \ XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \ - XSCUTIMER_COUNTER_OFFSET) + XSCUTIMER_COUNTER_OFFSET) /****************************************************************************/ /** @@ -221,10 +227,10 @@ typedef struct { ******************************************************************************/ #define XScuTimer_EnableAutoReload(InstancePtr) \ XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \ - XSCUTIMER_CONTROL_OFFSET, \ - (XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \ - XSCUTIMER_CONTROL_OFFSET) | \ - XSCUTIMER_CONTROL_AUTO_RELOAD_MASK)) + XSCUTIMER_CONTROL_OFFSET, \ + (XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \ + XSCUTIMER_CONTROL_OFFSET) | \ + XSCUTIMER_CONTROL_AUTO_RELOAD_MASK)) /****************************************************************************/ /** @@ -241,10 +247,10 @@ typedef struct { ******************************************************************************/ #define XScuTimer_DisableAutoReload(InstancePtr) \ XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \ - XSCUTIMER_CONTROL_OFFSET, \ - (XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \ - XSCUTIMER_CONTROL_OFFSET) & \ - ~(XSCUTIMER_CONTROL_AUTO_RELOAD_MASK))) + XSCUTIMER_CONTROL_OFFSET, \ + (XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \ + XSCUTIMER_CONTROL_OFFSET) & \ + ~(XSCUTIMER_CONTROL_AUTO_RELOAD_MASK))) /****************************************************************************/ /** @@ -261,10 +267,10 @@ typedef struct { ******************************************************************************/ #define XScuTimer_EnableInterrupt(InstancePtr) \ XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \ - XSCUTIMER_CONTROL_OFFSET, \ - (XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \ - XSCUTIMER_CONTROL_OFFSET) | \ - XSCUTIMER_CONTROL_IRQ_ENABLE_MASK)) + XSCUTIMER_CONTROL_OFFSET, \ + (XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \ + XSCUTIMER_CONTROL_OFFSET) | \ + XSCUTIMER_CONTROL_IRQ_ENABLE_MASK)) /****************************************************************************/ /** @@ -281,10 +287,10 @@ typedef struct { ******************************************************************************/ #define XScuTimer_DisableInterrupt(InstancePtr) \ XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \ - XSCUTIMER_CONTROL_OFFSET, \ - (XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \ - XSCUTIMER_CONTROL_OFFSET) & \ - ~(XSCUTIMER_CONTROL_IRQ_ENABLE_MASK))) + XSCUTIMER_CONTROL_OFFSET, \ + (XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \ + XSCUTIMER_CONTROL_OFFSET) & \ + ~(XSCUTIMER_CONTROL_IRQ_ENABLE_MASK))) /*****************************************************************************/ /** @@ -301,7 +307,7 @@ typedef struct { ******************************************************************************/ #define XScuTimer_GetInterruptStatus(InstancePtr) \ XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \ - XSCUTIMER_ISR_OFFSET) + XSCUTIMER_ISR_OFFSET) /*****************************************************************************/ /** @@ -318,14 +324,18 @@ typedef struct { ******************************************************************************/ #define XScuTimer_ClearInterruptStatus(InstancePtr) \ XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \ - XSCUTIMER_ISR_OFFSET, XSCUTIMER_ISR_EVENT_FLAG_MASK) + XSCUTIMER_ISR_OFFSET, XSCUTIMER_ISR_EVENT_FLAG_MASK) /************************** Function Prototypes ******************************/ /* * Lookup configuration in xscutimer_sinit.c */ +#ifndef SDT XScuTimer_Config *XScuTimer_LookupConfig(u16 DeviceId); +#else +XScuTimer_Config *XScuTimer_LookupConfig(UINTPTR BaseAddr); +#endif /* * Selftest function in xscutimer_selftest.c diff --git a/bsp_z7/ps7_cortexa9_0/include/xscutimer_hw.h b/bsp_z7/ps7_cortexa9_0/include/xscutimer_hw.h index c34acd1..8eb1875 100644 --- a/bsp_z7/ps7_cortexa9_0/include/xscutimer_hw.h +++ b/bsp_z7/ps7_cortexa9_0/include/xscutimer_hw.h @@ -1,5 +1,6 @@ /****************************************************************************** * Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved. +* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -7,7 +8,7 @@ /** * * @file xscutimer_hw.h -* @addtogroup scutimer_v2_4 +* @addtogroup scutimer Overview * @{ * * This file contains the hardware interface to the Timer. diff --git a/bsp_z7/ps7_cortexa9_0/include/xscuwdt.h b/bsp_z7/ps7_cortexa9_0/include/xscuwdt.h index 8d11ff8..9130e4d 100644 --- a/bsp_z7/ps7_cortexa9_0/include/xscuwdt.h +++ b/bsp_z7/ps7_cortexa9_0/include/xscuwdt.h @@ -1,5 +1,6 @@ /****************************************************************************** -* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved. +* Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -7,7 +8,7 @@ /** * * @file xscuwdt.h -* @addtogroup scuwdt_v2_4 +* @addtogroup Overview * @{ * @details * @@ -106,6 +107,8 @@ * time. * 2.3 sne 09/16/20 Fixed MISRA-C violations. * 2.4 sne 02/04/21 Fixed Doxygen warnings. +* 2.5 asa 07/18/23 Added support for system device tree based workflow +* decoupling flow. * * ******************************************************************************/ @@ -129,8 +132,18 @@ extern "C" { * This typedef contains configuration information for the device. */ typedef struct { +#ifndef SDT u16 DeviceId; /**< Unique ID of device */ - u32 BaseAddr; /**< Base address of the device */ +#else + char *Name; /**< Unique name of the device */ +#endif + UINTPTR BaseAddr; /**< Register base address */ +#ifdef SDT + u32 IntrId; /** Bits[11:0] Interrupt-id Bits[15:12] + * trigger type and level flags */ + UINTPTR IntrParent; /** Bit[0] Interrupt parent type Bit[64/32:1] + * Parent base address */ +#endif } XScuWdt_Config; /** @@ -168,7 +181,7 @@ extern XScuWdt_Config XScuWdt_ConfigTable[]; #define XScuWdt_IsWdtExpired(InstancePtr) \ ((XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \ XSCUWDT_RST_STS_OFFSET) & \ - XSCUWDT_RST_STS_RESET_FLAG_MASK) == XSCUWDT_RST_STS_RESET_FLAG_MASK) + XSCUWDT_RST_STS_RESET_FLAG_MASK) == XSCUWDT_RST_STS_RESET_FLAG_MASK) /****************************************************************************/ /** @@ -189,7 +202,7 @@ extern XScuWdt_Config XScuWdt_ConfigTable[]; #define XScuWdt_IsTimerExpired(InstancePtr) \ ((XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \ XSCUWDT_ISR_OFFSET) & \ - XSCUWDT_ISR_EVENT_FLAG_MASK) == XSCUWDT_ISR_EVENT_FLAG_MASK) + XSCUWDT_ISR_EVENT_FLAG_MASK) == XSCUWDT_ISR_EVENT_FLAG_MASK) /****************************************************************************/ /** @@ -230,7 +243,7 @@ extern XScuWdt_Config XScuWdt_ConfigTable[]; ******************************************************************************/ #define XScuWdt_LoadWdt(InstancePtr, Value) \ XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \ - XSCUWDT_LOAD_OFFSET, (Value)) + XSCUWDT_LOAD_OFFSET, (Value)) /****************************************************************************/ /** @@ -250,7 +263,7 @@ extern XScuWdt_Config XScuWdt_ConfigTable[]; XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \ XSCUWDT_CONTROL_OFFSET, \ (XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \ - XSCUWDT_CONTROL_OFFSET) | \ + XSCUWDT_CONTROL_OFFSET) | \ (XSCUWDT_CONTROL_WD_MODE_MASK))) /****************************************************************************/ @@ -271,14 +284,14 @@ extern XScuWdt_Config XScuWdt_ConfigTable[]; * ******************************************************************************/ #define XScuWdt_SetTimerMode(InstancePtr) \ -{ \ - XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \ - XSCUWDT_DISABLE_OFFSET, \ - XSCUWDT_DISABLE_VALUE1); \ - XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \ - XSCUWDT_DISABLE_OFFSET, \ - XSCUWDT_DISABLE_VALUE2); \ -} + { \ + XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \ + XSCUWDT_DISABLE_OFFSET, \ + XSCUWDT_DISABLE_VALUE1); \ + XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \ + XSCUWDT_DISABLE_OFFSET, \ + XSCUWDT_DISABLE_VALUE2); \ + } /****************************************************************************/ /** @@ -332,14 +345,18 @@ extern XScuWdt_Config XScuWdt_ConfigTable[]; #define XScuWdt_EnableAutoReload(InstancePtr) \ XScuWdt_SetControlReg((InstancePtr), \ (XScuWdt_GetControlReg(InstancePtr) | \ - XSCUWDT_CONTROL_AUTO_RELOAD_MASK)) + XSCUWDT_CONTROL_AUTO_RELOAD_MASK)) /************************** Function Prototypes ******************************/ /* * Lookup configuration in xscuwdt_sinit.c. */ +#ifndef SDT XScuWdt_Config *XScuWdt_LookupConfig(u16 DeviceId); +#else +XScuWdt_Config *XScuWdt_LookupConfig(UINTPTR BaseAddress); +#endif /* * Selftest function in xscuwdt_selftest.c diff --git a/bsp_z7/ps7_cortexa9_0/include/xscuwdt_hw.h b/bsp_z7/ps7_cortexa9_0/include/xscuwdt_hw.h index 0cdfc1e..3c401ec 100644 --- a/bsp_z7/ps7_cortexa9_0/include/xscuwdt_hw.h +++ b/bsp_z7/ps7_cortexa9_0/include/xscuwdt_hw.h @@ -1,5 +1,6 @@ /****************************************************************************** -* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved. +* Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -7,7 +8,7 @@ /** * * @file xscuwdt_hw.h -* @addtogroup scuwdt_v2_4 +* @addtogroup Overview * @{ * * This file contains the hardware interface to the Xilinx SCU private Watch Dog diff --git a/bsp_z7/ps7_cortexa9_0/include/xsdps.h b/bsp_z7/ps7_cortexa9_0/include/xsdps.h index 77aa9c6..3bdc4f6 100644 --- a/bsp_z7/ps7_cortexa9_0/include/xsdps.h +++ b/bsp_z7/ps7_cortexa9_0/include/xsdps.h @@ -1,6 +1,6 @@ /****************************************************************************** * Copyright (C) 2013 - 2022 Xilinx, Inc. All rights reserved. -* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved. +* Copyright (c) 2022 - 2024 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -8,75 +8,10 @@ /** * * @file xsdps.h -* @addtogroup sdps Overview +* @addtogroup sdps_api SDPS APIs * @{ * @details * -* This section explains the implementation of the XSdPs driver. -* See xsdps.h for a detailed description of the device and driver. -* -* This driver is used initialize read from and write to the SD card. -* Features such as switching bus width to 4-bit and switching to high speed, -* changing clock frequency, block size etc. are supported. -* SD 2.0 uses 1/4 bus width and speeds of 25/50KHz. Initialization, however -* is done using 1-bit bus width and 400KHz clock frequency. -* SD commands are classified as broadcast and addressed. Commands can be -* those with response only (using only command line) or -* response + data (using command and data lines). -* Only one command can be sent at a time. During a data transfer however, -* when dsta lines are in use, certain commands (which use only the command -* line) can be sent, most often to obtain status. -* This driver does not support multi card slots at present. -* -* Initialization & Configuration -* -* This includes initialization on the host controller side to select -* clock frequency, bus power and default transfer related parameters. -* The default voltage is 3.3V. -* On the SD card side, the initialization and identification state diagram is -* implemented. This resets the card, gives it a unique address/ID and -* identifies key card related specifications. -* -* Data transfer -* -* The SD card is put in transfer state to read from or write to it. -* The default block size is 512 bytes and if supported, -* default bus width is 4-bit and bus speed is High speed. -* The read and write functions are implemented in polled mode using ADMA2. -* -* At any point, when key parameters such as block size or -* clock/speed or bus width are modified, this driver takes care of -* maintaining the same selection on host and card. -* All error bits in host controller are monitored by the driver and in the -* event one of them is set, driver will clear the interrupt status and -* communicate failure to the upper layer. -* -* File system use -* -* This driver can be used with xilffs library to read and write files to SD. -* (Please refer to procedure in diskio.c). The file system read/write example -* in polled mode can used for reference. -* -* There is no example for using SD driver without file system at present. -* However, the driver can be used without the file system. The glue layer -* in filesystem can be used as reference for the same. The block count -* passed to the read/write function in one call is limited by the ADMA2 -* descriptor table and hence care will have to be taken to call read/write -* API's in a loop for large file sizes. -* -* Interrupt mode is not supported because it offers no improvement when used -* with file system. -* -* eMMC support -* -* SD driver supports SD and eMMC based on the "enable MMC" parameter in SDK. -* The features of eMMC supported by the driver will depend on those supported -* by the host controller. The current driver supports read/write on eMMC card -* using 4-bit and high speed mode currently. -* -* Features not supported include - card write protect, password setting, -* lock/unlock, interrupts, SDMA mode, programmed I/O mode and -* 64-bit addressed ADMA2, erase/pre-erase commands. * * 
 * MODIFICATION HISTORY:
@@ -161,6 +96,11 @@
 * 4.1   sa     01/03/23 Report error if Transfer size is greater than 2MB.
 * 4.1	sa     12/19/22 Enable eMMC HS400 mode for Versal Net.
 * 	sa     01/25/23	Use instance structure to store DMA descriptor tables.
+* 4.2   ro     06/12/23 Added support for system device-tree flow.
+* 4.2   ap     08/09/23 Reordered XSdPs_FrameCmd XSdPs_Identify_UhsMode functions
+* 4.3   ap     10/11/23 Resolved compilation errors with Microblaze RISC-V
+* 4.3   ap     11/29/23 Add support for Sanitize feature.
+* 4.3   ap     12/22/23 Add support to read custom HS400 tap delay value from design for eMMC.
 *
 *
* @@ -243,8 +183,12 @@ extern "C" { * This typedef contains configuration information for the device. */ typedef struct { +#ifndef SDT u16 DeviceId; /**< Unique ID of device */ - u32 BaseAddress; /**< Base address of the device */ +#else + char *Name; +#endif + UINTPTR BaseAddress; /**< Base address of the device */ u32 InputClockHz; /**< Input clock frequency */ u32 CardDetect; /**< Card Detect */ u32 WriteProtect; /**< Write Protect */ @@ -253,7 +197,7 @@ typedef struct { u32 HasEMIO; /**< If SD is connected to EMIO */ u8 SlotType; /**< Slot type */ u8 IsCacheCoherent; /**< If SD is Cache Coherent or not */ -#if defined (XCLOCKING) +#if defined (XCLOCKING) || defined (SDT) u32 RefClk; /**< Input clocks */ #endif u32 ITapDly_SDR_Clk50; /**< Input Tap delay for HSD/SDR25 modes */ @@ -262,6 +206,7 @@ typedef struct { u32 OTapDly_DDR_Clk50; /**< Output Tap delay for DDR50 modes */ u32 OTapDly_SDR_Clk100; /**< Input Tap delay for SDR50 modes */ u32 OTapDly_SDR_Clk200; /**< Input Tap delay for SDR104/HS200 modes */ + u32 OTapDly_DDR_Clk200; /**< Input Tap delay for HS400 modes */ } XSdPs_Config; /** @@ -275,7 +220,8 @@ typedef struct { #pragma data_alignment = 32 } XSdPs_Adma2Descriptor32; #else -} __attribute__((__packed__))XSdPs_Adma2Descriptor32; +} +__attribute__((__packed__))XSdPs_Adma2Descriptor32; #endif /** @@ -325,11 +271,11 @@ typedef struct { u8 IsTuningDone; /**< Flag to indicate HS200 tuning complete */ #ifdef __ICCARM__ #pragma data_alignment = 32 - XSdPs_Adma2Descriptor32 Adma2_DescrTbl32[32]; - XSdPs_Adma2Descriptor64 Adma2_DescrTbl64[32]; + XSdPs_Adma2Descriptor32 Adma2_DescrTbl32[32]; /**< ADMA descriptor table 32 Bit */ + XSdPs_Adma2Descriptor64 Adma2_DescrTbl64[32]; /**< ADMA descriptor table 64 Bit */ #else - XSdPs_Adma2Descriptor32 Adma2_DescrTbl32[32] __attribute__ ((aligned(32))); - XSdPs_Adma2Descriptor64 Adma2_DescrTbl64[32] __attribute__ ((aligned(32))); + XSdPs_Adma2Descriptor32 Adma2_DescrTbl32[32] __attribute__ ((aligned(32))); /**< ADMA descriptor table 32 Bit */ + XSdPs_Adma2Descriptor64 Adma2_DescrTbl64[32] __attribute__ ((aligned(32))); /**< ADMA descriptor table 64 Bit */ #endif } XSdPs; @@ -355,10 +301,24 @@ typedef struct { */ #define ENABLE_HS400_MODE +/************************** Variable Definitions *****************************/ +/** + * XSdPs Configuration Table + */ +#ifndef SDT +extern XSdPs_Config XSdPs_ConfigTable[XPAR_XSDPS_NUM_INSTANCES]; +#else +extern XSdPs_Config XSdPs_ConfigTable[]; +#endif + /************************** Function Prototypes ******************************/ +#ifndef SDT XSdPs_Config *XSdPs_LookupConfig(u16 DeviceId); +#else +XSdPs_Config *XSdPs_LookupConfig(u32 BaseAddress); +#endif s32 XSdPs_CfgInitialize(XSdPs *InstancePtr, XSdPs_Config *ConfigPtr, - u32 EffectiveAddr); + UINTPTR EffectiveAddr); s32 XSdPs_CardInitialize(XSdPs *InstancePtr); s32 XSdPs_ReadPolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, u8 *Buff); s32 XSdPs_WritePolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, const u8 *Buff); @@ -380,6 +340,7 @@ s32 XSdPs_CheckReadTransfer(XSdPs *InstancePtr); s32 XSdPs_StartWriteTransfer(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, u8 *Buff); s32 XSdPs_CheckWriteTransfer(XSdPs *InstancePtr); s32 XSdPs_Erase(XSdPs *InstancePtr, u32 StartAddr, u32 EndAddr); +s32 XSdPs_Sanitize(XSdPs *InstancePtr); #ifdef __cplusplus } diff --git a/bsp_z7/ps7_cortexa9_0/include/xsdps_core.h b/bsp_z7/ps7_cortexa9_0/include/xsdps_core.h index 239c2f1..9a5a289 100644 --- a/bsp_z7/ps7_cortexa9_0/include/xsdps_core.h +++ b/bsp_z7/ps7_cortexa9_0/include/xsdps_core.h @@ -1,6 +1,6 @@ /****************************************************************************** * Copyright (C) 2013 - 2022 Xilinx, Inc. All rights reserved. -* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved. +* Copyright (c) 2022 - 2024 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -8,10 +8,10 @@ /** * * @file xsdps_core.h -* @addtogroup sdps Overview +* @addtogroup sdps_api SDPS APIs * @{ * -* The xsdps_core.h header file contains the identifiers and basic HW access driver +* The xsdps_core.h header file contains the identifiers and basic hardware access driver * functions (or macros) that can be used to access the device. Other driver * functions are defined in xsdps.h. * @@ -27,6 +27,7 @@ * mn 11/28/21 Fix MISRA-C violations. * 4.0 sk 02/25/22 Add support for eMMC5.1. * 4.1 sa 01/06/23 Include xil_util.h in this file. +* 4.2 ap 08/09/23 Add XSdPs_SetTapDelay APIs. * * ******************************************************************************/ @@ -110,6 +111,10 @@ void XSdPs_ConfigInterrupt(XSdPs *InstancePtr); s32 XSdPs_SendErase(XSdPs *InstancePtr); s32 XSdPs_SetEndAddr(XSdPs *InstancePtr, u32 EndAddr); s32 XSdPs_SetStartAddr(XSdPs *InstancePtr, u32 StartAddr); +void XSdPs_SetTapDelay_SDR104(XSdPs *InstancePtr); +void XSdPs_SetTapDelay_SDR50(XSdPs *InstancePtr); +void XSdPs_SetTapDelay_DDR50(XSdPs *InstancePtr); +void XSdPs_SetTapDelay_SDR25(XSdPs *InstancePtr); #ifdef VERSAL_NET u32 XSdPs_Select_HS400(XSdPs *InstancePtr); #endif diff --git a/bsp_z7/ps7_cortexa9_0/include/xsdps_hw.h b/bsp_z7/ps7_cortexa9_0/include/xsdps_hw.h index 7ee7774..9257158 100644 --- a/bsp_z7/ps7_cortexa9_0/include/xsdps_hw.h +++ b/bsp_z7/ps7_cortexa9_0/include/xsdps_hw.h @@ -1,6 +1,6 @@ /****************************************************************************** * Copyright (C) 2013 - 2022 Xilinx, Inc. All rights reserved. -* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved. +* Copyright (c) 2022 - 2024 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -8,7 +8,7 @@ /** * * @file xsdps_hw.h -* @addtogroup sdps Overview +* @addtogroup sdps_api SDPS APIs * @{{ * * The xsdps_hw.h header file contains the identifiers and basic HW access driver @@ -45,6 +45,9 @@ * 4.0 sk 02/25/22 Add support for eMMC5.1. * sk 04/07/22 Fix typo in 'XSDPS_MMC_1_BIT_BUS_ARG' macro definition. * 4.1 sk 11/10/22 Add SD/eMMC Tap delay support for Versal Net. +* 4.2 ro 06/12/23 Added support for system device-tree flow. +* 4.3 ap 11/29/23 Add support for Sanitize feature. +* 4.3 ap 12/22/23 Add support to read custom HS400 tap delay value from design for eMMC. * * * @@ -63,8 +66,8 @@ extern "C" { #include "xil_types.h" #include "xil_assert.h" #include "xil_io.h" +#include "bspconfig.h" #include "xparameters.h" - /************************** Constant Definitions *****************************/ /** @name Register Map @@ -76,8 +79,8 @@ extern "C" { #define XSDPS_SDMA_SYS_ADDR_OFFSET 0x00U /**< SDMA System Address Register */ #define XSDPS_SDMA_SYS_ADDR_LO_OFFSET XSDPS_SDMA_SYS_ADDR_OFFSET - /**< SDMA System Address - Low Register */ +/**< SDMA System Address + Low Register */ #define XSDPS_ARGMT2_LO_OFFSET 0x00U /**< Argument2 Low Register */ #define XSDPS_SDMA_SYS_ADDR_HI_OFFSET 0x02U /**< SDMA System Address High Register */ @@ -87,7 +90,7 @@ extern "C" { #define XSDPS_BLK_CNT_OFFSET 0x06U /**< Block Count Register */ #define XSDPS_ARGMT_OFFSET 0x08U /**< Argument Register */ #define XSDPS_ARGMT1_LO_OFFSET XSDPS_ARGMT_OFFSET - /**< Argument1 Register */ +/**< Argument1 Register */ #define XSDPS_ARGMT1_HI_OFFSET 0x0AU /**< Argument1 Register */ #define XSDPS_XFER_MODE_OFFSET 0x0CU /**< Transfer Mode Register */ @@ -714,16 +717,16 @@ extern "C" { #define RESP_NONE (u32)XSDPS_CMD_RESP_NONE_MASK #define RESP_R1 (u32)XSDPS_CMD_RESP_L48_MASK | (u32)XSDPS_CMD_CRC_CHK_EN_MASK | \ - (u32)XSDPS_CMD_INX_CHK_EN_MASK + (u32)XSDPS_CMD_INX_CHK_EN_MASK #define RESP_R1B (u32)XSDPS_CMD_RESP_L48_BSY_CHK_MASK | \ - (u32)XSDPS_CMD_CRC_CHK_EN_MASK | (u32)XSDPS_CMD_INX_CHK_EN_MASK + (u32)XSDPS_CMD_CRC_CHK_EN_MASK | (u32)XSDPS_CMD_INX_CHK_EN_MASK #define RESP_R2 (u32)XSDPS_CMD_RESP_L136_MASK | (u32)XSDPS_CMD_CRC_CHK_EN_MASK #define RESP_R3 (u32)XSDPS_CMD_RESP_L48_MASK #define RESP_R6 (u32)XSDPS_CMD_RESP_L48_BSY_CHK_MASK | \ - (u32)XSDPS_CMD_CRC_CHK_EN_MASK | (u32)XSDPS_CMD_INX_CHK_EN_MASK + (u32)XSDPS_CMD_CRC_CHK_EN_MASK | (u32)XSDPS_CMD_INX_CHK_EN_MASK /** @} */ @@ -929,18 +932,24 @@ extern "C" { #define EXT_CSD_PART_CONFIG_ACC_BOOT1 (0x2U) #define EXT_CSD_PART_CONFIG_ACC_RPMB (0x3U) #define EXT_CSD_PART_CONFIG_ACC_GP0 (0x4U) +#define EXT_CSD_SANITIZE_START (0x1U) #define EXT_CSD_PART_CONFIG_BYTE (179U) +#define EXT_CSD_SANIT_CONFIG_BYTE (165U) #define XSDPS_MMC_PART_CFG_0_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24U) \ - | ((u32)EXT_CSD_PART_CONFIG_BYTE << 16U) \ - | ((u32)(0U) << 8U)) + | ((u32)EXT_CSD_PART_CONFIG_BYTE << 16U) \ + | ((u32)(0U) << 8U)) #define XSDPS_MMC_PART_CFG_1_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24U) \ - | ((u32)EXT_CSD_PART_CONFIG_BYTE << 16U) \ - | ((u32)EXT_CSD_PART_CONFIG_ACC_BOOT0 << 8U)) + | ((u32)EXT_CSD_PART_CONFIG_BYTE << 16U) \ + | ((u32)EXT_CSD_PART_CONFIG_ACC_BOOT0 << 8U)) #define XSDPS_MMC_PART_CFG_2_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24U) \ - | ((u32)EXT_CSD_PART_CONFIG_BYTE << 16U) \ - | ((u32)EXT_CSD_PART_CONFIG_ACC_BOOT1 << 8U)) + | ((u32)EXT_CSD_PART_CONFIG_BYTE << 16U) \ + | ((u32)EXT_CSD_PART_CONFIG_ACC_BOOT1 << 8U)) + +#define XSDPS_MMC_START_SANITIZE_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24U) \ + | ((u32)EXT_CSD_SANIT_CONFIG_BYTE << 16U) \ + | ((u32)EXT_CSD_SANITIZE_START << 8U)) #define EXT_CSD_PART_SUPPORT_PART_EN (0x1U) @@ -952,14 +961,14 @@ extern "C" { #define EXT_CSD_CARD_TYPE_52 (1U<<1) /* Card can run at 52MHz */ #define EXT_CSD_CARD_TYPE_MASK 0x3FU /* Mask out reserved bits */ #define EXT_CSD_CARD_TYPE_DDR_1_8V (1U<<2) /* Card can run at 52MHz */ - /* DDR mode @1.8V or 3V I/O */ +/* DDR mode @1.8V or 3V I/O */ #define EXT_CSD_CARD_TYPE_DDR_1_2V (1U<<3) /* Card can run at 52MHz */ - /* DDR mode @1.2V I/O */ +/* DDR mode @1.2V I/O */ #define EXT_CSD_CARD_TYPE_DDR_52 (EXT_CSD_CARD_TYPE_DDR_1_8V \ - | EXT_CSD_CARD_TYPE_DDR_1_2V) + | EXT_CSD_CARD_TYPE_DDR_1_2V) #define EXT_CSD_CARD_TYPE_SDR_1_8V (1U<<4) /* Card can run at 200MHz */ #define EXT_CSD_CARD_TYPE_SDR_1_2V (1U<<5) /* Card can run at 200MHz */ - /* SDR mode @1.2V I/O */ +/* SDR mode @1.2V I/O */ #define EXT_CSD_BUS_WIDTH_BYTE 183U #define EXT_CSD_BUS_WIDTH_1_BIT 0U /* Card is in 1 bit mode */ #define EXT_CSD_BUS_WIDTH_4_BIT 1U /* Card is in 4 bit mode */ @@ -992,44 +1001,44 @@ extern "C" { * SD/MMC Arguments for Bus Speed and Bus Width. */ #define XSDPS_MMC_DEF_SPEED_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \ - | ((u32)EXT_CSD_HS_TIMING_BYTE << 16) \ - | ((u32)EXT_CSD_HS_TIMING_DEF << 8)) + | ((u32)EXT_CSD_HS_TIMING_BYTE << 16) \ + | ((u32)EXT_CSD_HS_TIMING_DEF << 8)) #define XSDPS_MMC_HIGH_SPEED_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \ - | ((u32)EXT_CSD_HS_TIMING_BYTE << 16) \ - | ((u32)EXT_CSD_HS_TIMING_HIGH << 8)) + | ((u32)EXT_CSD_HS_TIMING_BYTE << 16) \ + | ((u32)EXT_CSD_HS_TIMING_HIGH << 8)) #define XSDPS_MMC_HS200_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \ - | ((u32)EXT_CSD_HS_TIMING_BYTE << 16) \ - | ((u32)EXT_CSD_HS_TIMING_HS200 << 8)) + | ((u32)EXT_CSD_HS_TIMING_BYTE << 16) \ + | ((u32)EXT_CSD_HS_TIMING_HS200 << 8)) #define XSDPS_MMC_HS400_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \ - | ((u32)EXT_CSD_HS_TIMING_BYTE << 16) \ - | ((u32)EXT_CSD_HS_TIMING_HS400 << 8)) + | ((u32)EXT_CSD_HS_TIMING_BYTE << 16) \ + | ((u32)EXT_CSD_HS_TIMING_HS400 << 8)) #define XSDPS_MMC_1_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \ - | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \ - | ((u32)EXT_CSD_BUS_WIDTH_1_BIT << 8)) + | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \ + | ((u32)EXT_CSD_BUS_WIDTH_1_BIT << 8)) #define XSDPS_MMC_4_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \ - | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \ - | ((u32)EXT_CSD_BUS_WIDTH_4_BIT << 8)) + | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \ + | ((u32)EXT_CSD_BUS_WIDTH_4_BIT << 8)) #define XSDPS_MMC_8_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \ - | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \ - | ((u32)EXT_CSD_BUS_WIDTH_8_BIT << 8)) + | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \ + | ((u32)EXT_CSD_BUS_WIDTH_8_BIT << 8)) #define XSDPS_MMC_DDR_4_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \ - | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \ - | ((u32)EXT_CSD_BUS_WIDTH_DDR_4_BIT << 8)) + | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \ + | ((u32)EXT_CSD_BUS_WIDTH_DDR_4_BIT << 8)) #define XSDPS_MMC_DDR_8_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \ - | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \ - | ((u32)EXT_CSD_BUS_WIDTH_DDR_8_BIT << 8)) + | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \ + | ((u32)EXT_CSD_BUS_WIDTH_DDR_8_BIT << 8)) #define XSDPS_MMC_RST_FUN_EN_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \ - | ((u32)EXT_CSD_RST_N_FUN_BYTE << 16) \ - | ((u32)EXT_CSD_RST_N_FUN_PERM_EN << 8)) + | ((u32)EXT_CSD_RST_N_FUN_BYTE << 16) \ + | ((u32)EXT_CSD_RST_N_FUN_PERM_EN << 8)) #define XSDPS_MMC_DELAY_FOR_SWITCH 1000U @@ -1196,6 +1205,8 @@ extern "C" { #define SD_ITAPCHGWIN 0x00000200U #define SD_ITAPDLYENA 0x00000100U #define SD_OTAPDLYENA 0x00000040U +#define SD_OTAPDLYSEL_SD104_B0 0x00000002U +#define SD_OTAPDLYSEL_SD104_B2 0x00000002U #define SD_OTAPDLYSEL_HS200_B0 0x00000007U #define SD_OTAPDLYSEL_HS200_B2 0x00000007U #define SD_OTAPDLYSEL_HS400 0x00000004U @@ -1224,6 +1235,8 @@ extern "C" { #define SD_ITAPCHGWIN 0x00000200U #define SD_ITAPDLYENA 0x00000100U #define SD_OTAPDLYENA 0x00000040U +#define SD_OTAPDLYSEL_SD104_B0 0x00000002U +#define SD_OTAPDLYSEL_SD104_B2 0x00000002U #define SD_OTAPDLYSEL_HS200_B0 0x00000002U #define SD_OTAPDLYSEL_HS200_B2 0x00000002U #define SD_ITAPDLYSEL_SD50 0x0000000EU @@ -1255,6 +1268,8 @@ extern "C" { #define SD1_ITAPCHGWIN 0x02000000U #define SD1_ITAPDLYENA 0x01000000U #define SD1_OTAPDLYENA 0x00400000U +#define SD_OTAPDLYSEL_SD104_B0 0x00000003U +#define SD_OTAPDLYSEL_SD104_B2 0x00000002U #define SD_OTAPDLYSEL_HS200_B0 0x00000003U #define SD_OTAPDLYSEL_HS200_B2 0x00000002U #define SD_ITAPDLYSEL_SD50 0x00000014U @@ -1273,7 +1288,7 @@ extern "C" { #endif /** @} */ -#ifdef __MICROBLAZE__ +#if defined (__MICROBLAZE__) || defined (__riscv) #define XPS_SYS_CTRL_BASEADDR 0xFF180000U /**< System controller Baseaddress */ #endif @@ -1294,16 +1309,16 @@ extern "C" { /****************************************************************************/ /** -* Read a register. +* Reads a register. * -* @param InstancePtr is the pointer to the sdps instance. -* @param RegOffset contains the offset from the 1st register of the +* @param InstancePtr Pointer to the sdps instance. +* @param RegOffset Contains the offset from the 1st register of the * device to the target register. * * @return The value read from the register. * * @note C-Style signature: -* u32 XSdPs_ReadReg(XSdPs *InstancePtr. s32 RegOffset) +* u32 XSdPs_ReadReg(XSdPs *InstancePtr. s32 RegOffset) * ******************************************************************************/ #define XSdPs_ReadReg64(InstancePtr, RegOffset) \ @@ -1311,36 +1326,36 @@ extern "C" { /***************************************************************************/ /** -* Write to a register. +* Writes to a register. * -* @param InstancePtr is the pointer to the sdps instance. -* @param RegOffset contains the offset from the 1st register of the +* @param InstancePtr Pointer to the sdps instance. +* @param RegOffset Contains the offset from the 1st register of the * device to target register. -* @param RegisterValue is the value to be written to the register. +* @param RegisterValue Value to be written to the register. * * @return None. * * @note C-Style signature: -* void XSdPs_WriteReg(XSdPs *InstancePtr, s32 RegOffset, -* u64 RegisterValue) +* void XSdPs_WriteReg(XSdPs *InstancePtr, s32 RegOffset, +* u64 RegisterValue) * ******************************************************************************/ #define XSdPs_WriteReg64(InstancePtr, RegOffset, RegisterValue) \ XSdPs_Out64((InstancePtr->Config.BaseAddress) + (RegOffset), \ - (RegisterValue)) + (RegisterValue)) /****************************************************************************/ /** -* Read a register. +* Reads a register. * -* @param BaseAddress contains the base address of the device. -* @param RegOffset contains the offset from the 1st register of the +* @param BaseAddress Contains the base address of the device. +* @param RegOffset Contains the offset from the 1st register of the * device to the target register. * * @return The value read from the register. * * @note C-Style signature: -* u32 XSdPs_ReadReg(u32 BaseAddress. int RegOffset) +* u32 XSdPs_ReadReg(UINTPTR BaseAddress. int RegOffset) * ******************************************************************************/ #define XSdPs_ReadReg(BaseAddress, RegOffset) \ @@ -1348,18 +1363,18 @@ extern "C" { /***************************************************************************/ /** -* Write to a register. +* Writes to a register. * -* @param BaseAddress contains the base address of the device. -* @param RegOffset contains the offset from the 1st register of the +* @param BaseAddress Contains the base address of the device. +* @param RegOffset Contains the offset from the 1st register of the * device to target register. -* @param RegisterValue is the value to be written to the register. +* @param RegisterValue Value to be written to the register. * * @return None. * * @note C-Style signature: -* void XSdPs_WriteReg(u32 BaseAddress, int RegOffset, -* u32 RegisterValue) +* void XSdPs_WriteReg(UINTPTR BaseAddress, int RegOffset, +* u32 RegisterValue) * ******************************************************************************/ #define XSdPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \ @@ -1367,25 +1382,25 @@ extern "C" { /****************************************************************************/ /** -* Read a register. +* Reads a register. * -* @param BaseAddress contains the base address of the device. -* @param RegOffset contains the offset from the 1st register of the +* @param BaseAddress Contains the base address of the device. +* @param RegOffset Contains the offset from the 1st register of the * device to the target register. * * @return The value read from the register. * * @note C-Style signature: -* u16 XSdPs_ReadReg(u32 BaseAddress. int RegOffset) +* u16 XSdPs_ReadReg(UINTPTR BaseAddress. int RegOffset) * ******************************************************************************/ -static INLINE u16 XSdPs_ReadReg16(u32 BaseAddress, u8 RegOffset) +static INLINE u16 XSdPs_ReadReg16(UINTPTR BaseAddress, u8 RegOffset) { -#if defined (__MICROBLAZE__) +#if defined (__MICROBLAZE__) || defined (__riscv) u32 Reg; BaseAddress += RegOffset & 0xFC; Reg = XSdPs_In32(BaseAddress); - Reg >>= ((RegOffset & 0x3)*8); + Reg >>= ((RegOffset & 0x3) * 8); return (u16)Reg; #else return XSdPs_In16((UINTPTR)(BaseAddress) + (UINTPTR)(RegOffset)); @@ -1394,29 +1409,29 @@ static INLINE u16 XSdPs_ReadReg16(u32 BaseAddress, u8 RegOffset) /***************************************************************************/ /** -* Write to a register. +* Writes to a register. * -* @param BaseAddress contains the base address of the device. -* @param RegOffset contains the offset from the 1st register of the +* @param BaseAddress Contains the base address of the device. +* @param RegOffset Contains the offset from the 1st register of the * device to target register. -* @param RegisterValue is the value to be written to the register. +* @param RegisterValue Value to be written to the register. * * @return None. * * @note C-Style signature: -* void XSdPs_WriteReg(u32 BaseAddress, int RegOffset, -* u16 RegisterValue) +* void XSdPs_WriteReg(UINTPTR BaseAddress, int RegOffset, +* u16 RegisterValue) * ******************************************************************************/ -static INLINE void XSdPs_WriteReg16(u32 BaseAddress, u8 RegOffset, u16 RegisterValue) +static INLINE void XSdPs_WriteReg16(UINTPTR BaseAddress, u8 RegOffset, u16 RegisterValue) { -#if defined (__MICROBLAZE__) +#if defined (__MICROBLAZE__) || defined (__riscv) u32 Reg; BaseAddress += RegOffset & 0xFC; Reg = XSdPs_In32(BaseAddress); - Reg &= ~(0xFFFFU<<((RegOffset & 0x3)*8)); - Reg |= RegisterValue <<((RegOffset & 0x3)*8); + Reg &= ~(0xFFFFU << ((RegOffset & 0x3) * 8)); + Reg |= RegisterValue << ((RegOffset & 0x3) * 8); XSdPs_Out32(BaseAddress, Reg); #else XSdPs_Out16((UINTPTR)(BaseAddress) + (UINTPTR)(RegOffset), (RegisterValue)); @@ -1425,25 +1440,25 @@ static INLINE void XSdPs_WriteReg16(u32 BaseAddress, u8 RegOffset, u16 RegisterV /****************************************************************************/ /** -* Read a register. +* Reads a register. * -* @param BaseAddress contains the base address of the device. -* @param RegOffset contains the offset from the 1st register of the +* @param BaseAddress Contains the base address of the device. +* @param RegOffset Contains the offset from the 1st register of the * device to the target register. * * @return The value read from the register. * * @note C-Style signature: -* u8 XSdPs_ReadReg(u32 BaseAddress. int RegOffset) +* u8 XSdPs_ReadReg(UINTPTR BaseAddress. int RegOffset) * ******************************************************************************/ -static INLINE u8 XSdPs_ReadReg8(u32 BaseAddress, u8 RegOffset) +static INLINE u8 XSdPs_ReadReg8(UINTPTR BaseAddress, u8 RegOffset) { -#if defined (__MICROBLAZE__) +#if defined (__MICROBLAZE__) || defined (__riscv) u32 Reg; BaseAddress += RegOffset & 0xFC; Reg = XSdPs_In32(BaseAddress); - Reg >>= ((RegOffset & 0x3)*8); + Reg >>= ((RegOffset & 0x3) * 8); return (u8)Reg; #else return XSdPs_In8((UINTPTR)(BaseAddress) + (UINTPTR)(RegOffset)); @@ -1451,28 +1466,28 @@ static INLINE u8 XSdPs_ReadReg8(u32 BaseAddress, u8 RegOffset) } /***************************************************************************/ /** -* Write to a register. +* Writes to a register. * -* @param BaseAddress contains the base address of the device. -* @param RegOffset contains the offset from the 1st register of the +* @param BaseAddress Contains the base address of the device. +* @param RegOffset Contains the offset from the 1st register of the * device to target register. -* @param RegisterValue is the value to be written to the register. +* @param RegisterValue Value to be written to the register. * * @return None. * * @note C-Style signature: -* void XSdPs_WriteReg(u32 BaseAddress, int RegOffset, -* u8 RegisterValue) +* void XSdPs_WriteReg(UINTPTR BaseAddress, int RegOffset, +* u8 RegisterValue) * ******************************************************************************/ -static INLINE void XSdPs_WriteReg8(u32 BaseAddress, u8 RegOffset, u8 RegisterValue) +static INLINE void XSdPs_WriteReg8(UINTPTR BaseAddress, u8 RegOffset, u8 RegisterValue) { -#if defined (__MICROBLAZE__) +#if defined (__MICROBLAZE__) || defined (__riscv) u32 Reg; BaseAddress += RegOffset & 0xFC; Reg = XSdPs_In32(BaseAddress); - Reg &= ~(0xFFU<<((RegOffset & 0x3)*8)); - Reg |= RegisterValue <<((RegOffset & 0x3)*8); + Reg &= ~(0xFFU << ((RegOffset & 0x3) * 8)); + Reg |= RegisterValue << ((RegOffset & 0x3) * 8); XSdPs_Out32(BaseAddress, Reg); #else XSdPs_Out8((UINTPTR)(BaseAddress) + (UINTPTR)(RegOffset), (RegisterValue)); @@ -1480,19 +1495,19 @@ static INLINE void XSdPs_WriteReg8(u32 BaseAddress, u8 RegOffset, u8 RegisterVal } /***************************************************************************/ /** -* Macro to get present status register +* Macro to get present status register. * -* @param BaseAddress contains the base address of the device. +* @param BaseAddress Contains the base address of the device. * * @return None. * * @note C-Style signature: -* void XSdPs_WriteReg(u32 BaseAddress, int RegOffset, -* u8 RegisterValue) +* void XSdPs_WriteReg(UINTPTR BaseAddress, int RegOffset, +* u8 RegisterValue) * ******************************************************************************/ #define XSdPs_GetPresentStatusReg(BaseAddress) \ - XSdPs_In32((BaseAddress) + (XSDPS_PRES_STATE_OFFSET)) + XSdPs_In32((BaseAddress) + (XSDPS_PRES_STATE_OFFSET)) /************************** Function Prototypes ******************************/ diff --git a/bsp_z7/ps7_cortexa9_0/include/xstatus.h b/bsp_z7/ps7_cortexa9_0/include/xstatus.h index 85d1e73..f534bdf 100644 --- a/bsp_z7/ps7_cortexa9_0/include/xstatus.h +++ b/bsp_z7/ps7_cortexa9_0/include/xstatus.h @@ -32,6 +32,7 @@ extern "C" { #include "xil_types.h" #include "xil_assert.h" +#include "bspconfig.h" /************************** Constant Definitions *****************************/ diff --git a/bsp_z7/ps7_cortexa9_0/include/xttcps.h b/bsp_z7/ps7_cortexa9_0/include/xttcps.h index 643e73e..e62fc6f 100644 --- a/bsp_z7/ps7_cortexa9_0/include/xttcps.h +++ b/bsp_z7/ps7_cortexa9_0/include/xttcps.h @@ -1,6 +1,6 @@ /****************************************************************************** * Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved. -* Copyright (c) 2022 Advanced Micro Devices, Inc. All Rights Reserved. +* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -149,6 +149,7 @@ * It fixes CR#1084697. * 3.16 adk 04/19/22 Fix infinite loop in the examples by adding polled * timeout loop. +* 3.18 adk 04/14/23 Added support for system device-tree flow. * * ******************************************************************************/ @@ -181,6 +182,7 @@ typedef void (*XTtcPs_StatusHandler) (const void *CallBackRef, u32 StatusEvent); #define XTTCPS_MAX_INTERVAL_COUNT 0xFFFFFFFFU #endif +#define XTTCPS_NUM_COUNTERS 3U /** @name Configuration options * * Options for the device. Each of the options is bit field, so more than one @@ -203,11 +205,18 @@ typedef void (*XTtcPs_StatusHandler) (const void *CallBackRef, u32 StatusEvent); * This typedef contains configuration information for the device. */ typedef struct { +#ifndef SDT u16 DeviceId; /**< Unique ID for device */ +#else + char *Name; +#endif u32 BaseAddress; /**< Base address for device */ u32 InputClockHz; /**< Input clock frequency */ -#ifdef XIL_INTERRUPT - u16 IntrId; +#if !defined(SDT) && defined(XIL_INTERRUPT) + u32 IntrId; + UINTPTR IntrParent; /** Bit[0] Interrupt parent type Bit[64/32:1] Parent base address */ +#elif defined(SDT) + u32 IntrId[XTTCPS_NUM_COUNTERS]; /** Bits[11:0] Interrupt-id Bits[15:12] trigger type and level flags */ UINTPTR IntrParent; /** Bit[0] Interrupt parent type Bit[64/32:1] Parent base address */ #endif } XTtcPs_Config; @@ -487,7 +496,11 @@ typedef u32 XMatchRegValue; /* * Initialization functions in xttcps_sinit.c */ +#ifndef SDT XTtcPs_Config *XTtcPs_LookupConfig(u16 DeviceId); +#else +XTtcPs_Config *XTtcPs_LookupConfig(u32 BaseAddress); +#endif /* * Required functions, in xttcps.c @@ -495,6 +508,7 @@ XTtcPs_Config *XTtcPs_LookupConfig(u16 DeviceId); s32 XTtcPs_CfgInitialize(XTtcPs *InstancePtr, XTtcPs_Config * ConfigPtr, u32 EffectiveAddr); +u32 XTtcPs_Release(XTtcPs *InstancePtr); void XTtcPs_SetMatchValue(XTtcPs *InstancePtr, u8 MatchIndex, XMatchRegValue Value); XMatchRegValue XTtcPs_GetMatchValue(XTtcPs *InstancePtr, u8 MatchIndex); diff --git a/bsp_z7/ps7_cortexa9_0/include/xuartps.h b/bsp_z7/ps7_cortexa9_0/include/xuartps.h index 20dd99f..89ed5fd 100644 --- a/bsp_z7/ps7_cortexa9_0/include/xuartps.h +++ b/bsp_z7/ps7_cortexa9_0/include/xuartps.h @@ -1,6 +1,6 @@ /****************************************************************************** * Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved. -* Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. +* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -149,6 +149,7 @@ * 3.9 rna 12/03/19 Modified the XUARTPS_MAX_RATE macro. * 3.9 sd 02/06/20 Added clock support * 3.12 gm 11/04/22 Added timeout support using Xil_WaitForEvent +* 3.13 adk 14/04/23 Added support for system device-tree flow. * * * @@ -272,13 +273,23 @@ extern "C" { * This typedef contains configuration information for the device. */ typedef struct { +#ifndef SDT u16 DeviceId; /**< Unique ID of device */ +#else + char *Name; +#endif u32 BaseAddress; /**< Base address of device (IPIF) */ u32 InputClockHz;/**< Input clock frequency */ s32 ModemPinsConnected; /** Specifies whether modem pins are connected * to MIO or FMIO */ -#if defined (XCLOCKING) - u32 RefClk; /**< Input clock frequency */ +#if defined (XCLOCKING) || defined(SDT) + u32 RefClk; /**< Input clock frequency */ +#endif +#if defined(SDT) + u32 IntrId; /** Bits[11:0] Interrupt-id Bits[15:12] + * trigger type and level flags */ + UINTPTR IntrParent; /** Bit[0] Interrupt parent type Bit[64/32:1] + * Parent base address */ #endif } XUartPs_Config; @@ -444,7 +455,11 @@ typedef struct { /************************** Function Prototypes *****************************/ /* Static lookup function implemented in xuartps_sinit.c */ +#ifndef SDT XUartPs_Config *XUartPs_LookupConfig(u16 DeviceId); +#else +XUartPs_Config *XUartPs_LookupConfig(u32 BaseAddress); +#endif /* Interface functions implemented in xuartps.c */ s32 XUartPs_CfgInitialize(XUartPs *InstancePtr, diff --git a/bsp_z7/ps7_cortexa9_0/include/xuartps_hw.h b/bsp_z7/ps7_cortexa9_0/include/xuartps_hw.h index 59d4ccf..f45d5c8 100644 --- a/bsp_z7/ps7_cortexa9_0/include/xuartps_hw.h +++ b/bsp_z7/ps7_cortexa9_0/include/xuartps_hw.h @@ -1,6 +1,6 @@ /****************************************************************************** * Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved. -* Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. +* Copyright (C) 2022 - 2024 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -32,6 +32,8 @@ * 3.1 kvn 04/10/15 Modified code for latest RTL changes. * 3.6 ms 02/16/18 Updates flow control mode offset value in * modem control register. +* 4.0 sd 02/02/24 Added macros for transmission FIFO empty check +* and transmission active state check * * * @@ -48,6 +50,7 @@ extern "C" { #include "xil_types.h" #include "xil_assert.h" #include "xil_io.h" +#include "xstatus.h" /************************** Constant Definitions *****************************/ @@ -408,6 +411,36 @@ extern "C" { ((Xil_In32((BaseAddress) + XUARTPS_SR_OFFSET) & \ (u32)XUARTPS_SR_TXFULL) == (u32)XUARTPS_SR_TXFULL) +/****************************************************************************/ +/** +* Check if transmission FIFO is empty +* +* @return TRUE if the TX FIFO is empty, FALSE if Tx FIFO is not empty +* +* @note C-Style signature: +* u32 XUartPs_IsTransmitEmpty(u32 BaseAddress) +* +******************************************************************************/ +#define XUartPs_IsTransmitEmpty(BaseAddress) \ + ((Xil_In32((BaseAddress) + XUARTPS_SR_OFFSET) & \ + (u32)XUARTPS_SR_TXEMPTY) == (u32)XUARTPS_SR_TXEMPTY) + +/****************************************************************************/ +/** +* Check if transmission state machine is active +* +* @return TRUE if the TX state machine is active, FALSE if Tx state machine +* is In-active +* +* @note C-Style signature: +* u32 XUartPs_IsTransmitActive(u32 BaseAddress) +* +******************************************************************************/ +#define XUartPs_IsTransmitActive(BaseAddress) \ + ((Xil_In32((BaseAddress) + XUARTPS_SR_OFFSET) & \ + (u32)XUARTPS_SR_TACTIVE) == (u32)XUARTPS_SR_TACTIVE) + + /************************** Function Prototypes ******************************/ void XUartPs_SendByte(u32 BaseAddress, u8 Data); @@ -416,6 +449,8 @@ u8 XUartPs_RecvByte(u32 BaseAddress); void XUartPs_ResetHw(u32 BaseAddress); +void XUartPs_WaitTransmitDone(u32 BaseAddress); + /************************** Variable Definitions *****************************/ #ifdef __cplusplus diff --git a/bsp_z7/ps7_cortexa9_0/include/xusbps.h b/bsp_z7/ps7_cortexa9_0/include/xusbps.h index 5c01051..d215b77 100644 --- a/bsp_z7/ps7_cortexa9_0/include/xusbps.h +++ b/bsp_z7/ps7_cortexa9_0/include/xusbps.h @@ -1,5 +1,6 @@ /****************************************************************************** * Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved. +* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -7,7 +8,7 @@ /** * * @file xusbps.h -* @addtogroup usbps_v2_7 +* @addtogroup usbps Overview * @{ * @details * @@ -163,6 +164,7 @@ * examples. * 2.5 pm 02/20/20 Added ISO support for usb 2.0 and ch9 common framework * calls. + * 2.8 pm 07/07/23 Added support for system device-tree flow. * * ******************************************************************************/ @@ -256,13 +258,13 @@ extern "C" { #define XUSBPS_EP_STS_CONTROLLER_STATE 2 /**< Current controller state. */ /* @} */ - /* - * Device Speeds - */ - #define XUSBPS_SPEED_UNKNOWN 0U - #define XUSBPS_SPEED_LOW 1U - #define XUSBPS_SPEED_FULL 2U - #define XUSBPS_SPEED_HIGH 3U +/* + * Device Speeds + */ +#define XUSBPS_SPEED_UNKNOWN 0U +#define XUSBPS_SPEED_LOW 1U +#define XUSBPS_SPEED_FULL 2U +#define XUSBPS_SPEED_HIGH 3U /** * @name USB Default alternate setting @@ -272,15 +274,15 @@ extern "C" { #define XUSBPS_DEFAULT_ALT_SETTING 0 /**< The default alternate setting is 0 */ /* @} */ - /* - * Device States - */ - #define XUSBPS_STATE_ATTACHED 0U - #define XUSBPS_STATE_POWERED 1U - #define XUSBPS_STATE_DEFAULT 2U - #define XUSBPS_STATE_ADDRESS 3U - #define XUSBPS_STATE_CONFIGURED 4U - #define XUSBPS_STATE_SUSPENDED 5U +/* + * Device States + */ +#define XUSBPS_STATE_ATTACHED 0U +#define XUSBPS_STATE_POWERED 1U +#define XUSBPS_STATE_DEFAULT 2U +#define XUSBPS_STATE_ADDRESS 3U +#define XUSBPS_STATE_CONFIGURED 4U +#define XUSBPS_STATE_SUSPENDED 5U /** * @name Endpoint event types @@ -290,11 +292,11 @@ extern "C" { * @{ */ #define XUSBPS_EP_EVENT_SETUP_DATA_RECEIVED 0x01 - /**< Setup data has been received on the endpoint. */ +/**< Setup data has been received on the endpoint. */ #define XUSBPS_EP_EVENT_DATA_RX 0x02 - /**< Data frame has been received on the endpoint. */ +/**< Data frame has been received on the endpoint. */ #define XUSBPS_EP_EVENT_DATA_TX 0x03 - /**< Data frame has been sent on the endpoint. */ +/**< Data frame has been sent on the endpoint. */ /* @} */ @@ -303,7 +305,7 @@ extern "C" { * @{ */ #define XUSBPS_MAX_PACKET_SIZE 1024 - /**< Maximum value can be put into the queue head */ +/**< Maximum value can be put into the queue head */ /* @} */ /**************************** Type Definitions *******************************/ @@ -320,7 +322,7 @@ extern "C" { * was registered. */ typedef void (*XUsbPs_EpHandlerFunc)(void *CallBackRef, - u8 EpNum, u8 EventType, void *Data); + u8 EpNum, u8 EventType, void *Data); /****************************************************************************** * This data type defines the callback function to be used for Endpoint @@ -369,24 +371,24 @@ typedef u8 XUsbPs_dTD[XUSBPS_dTD_ALIGN]; */ typedef struct { XUsbPs_dQH *dQH; - /**< Pointer to the Queue Head structure of the endpoint. */ + /**< Pointer to the Queue Head structure of the endpoint. */ XUsbPs_dTD *dTDs; - /**< Pointer to the first dTD of the dTD list for this - * endpoint. */ + /**< Pointer to the first dTD of the dTD list for this + * endpoint. */ XUsbPs_dTD *dTDCurr; - /**< Buffer to the currently processed descriptor. */ + /**< Buffer to the currently processed descriptor. */ u8 *dTDBufs; - /**< Pointer to the first buffer of the buffer list for this - * endpoint. */ + /**< Pointer to the first buffer of the buffer list for this + * endpoint. */ XUsbPs_EpHandlerFunc HandlerFunc; XUsbPs_EpIsoHandlerFunc HandlerIsoFunc; - /**< Handler function for this endpoint. */ + /**< Handler function for this endpoint. */ void *HandlerRef; - /**< User data reference for the handler. */ + /**< User data reference for the handler. */ u32 RequestedBytes; /**< RequestedBytes for transfer */ u32 BytesTxed; /**< Actual Bytes transferred */ u8 *BufferPtr; /**< Buffer location */ @@ -400,23 +402,23 @@ typedef struct { */ typedef struct { XUsbPs_dQH *dQH; - /**< Pointer to the Queue Head structure of the endpoint. */ + /**< Pointer to the Queue Head structure of the endpoint. */ XUsbPs_dTD *dTDs; - /**< List of pointers to the Transfer Descriptors of the - * endpoint. */ + /**< List of pointers to the Transfer Descriptors of the + * endpoint. */ XUsbPs_dTD *dTDHead; - /**< Buffer to the next available descriptor in the list. */ + /**< Buffer to the next available descriptor in the list. */ XUsbPs_dTD *dTDTail; - /**< Buffer to the last unsent descriptor in the list*/ + /**< Buffer to the last unsent descriptor in the list*/ XUsbPs_EpHandlerFunc HandlerFunc; XUsbPs_EpIsoHandlerFunc HandlerIsoFunc; - /**< Handler function for this endpoint. */ + /**< Handler function for this endpoint. */ void *HandlerRef; - /**< User data reference for the handler. */ + /**< User data reference for the handler. */ u32 RequestedBytes; /**< RequestedBytes for transfer */ u32 BytesTxed; /**< Actual Bytes transferred */ u8 *BufferPtr; /**< Buffer location */ @@ -462,21 +464,21 @@ XUsbPs_SetupData; */ typedef struct { u32 Type; - /**< Endpoint type: - - XUSBPS_EP_TYPE_CONTROL - - XUSBPS_EP_TYPE_ISOCHRONOUS - - XUSBPS_EP_TYPE_BULK - - XUSBPS_EP_TYPE_INTERRUPT */ + /**< Endpoint type: + - XUSBPS_EP_TYPE_CONTROL + - XUSBPS_EP_TYPE_ISOCHRONOUS + - XUSBPS_EP_TYPE_BULK + - XUSBPS_EP_TYPE_INTERRUPT */ u32 NumBufs; - /**< Number of buffers to be handled by this endpoint. */ + /**< Number of buffers to be handled by this endpoint. */ u32 BufSize; - /**< Buffer size. Only relevant for OUT (receive) Endpoints. */ + /**< Buffer size. Only relevant for OUT (receive) Endpoints. */ u16 MaxPacketSize; - /**< Maximum packet size for this endpoint. This number will - * define the maximum number of bytes sent on the wire per - * transaction. Range: 0..1024 */ + /**< Maximum packet size for this endpoint. This number will + * define the maximum number of bytes sent on the wire per + * transaction. Range: 0..1024 */ } XUsbPs_EpSetup; @@ -502,7 +504,7 @@ typedef struct { in the core. */ XUsbPs_EpConfig EpCfg[XUSBPS_MAX_ENDPOINTS]; - /**< List of endpoint configurations. */ + /**< List of endpoint configurations. */ u32 DMAMemPhys; /**< Physical base address of DMAable memory @@ -518,7 +520,7 @@ typedef struct { * structure which is allocated by the caller. */ XUsbPs_Endpoint Ep[XUSBPS_MAX_ENDPOINTS]; - /**< List of endpoint metadata structures. */ + /**< List of endpoint metadata structures. */ u32 PhysAligned; /**< 64 byte aligned base address of the DMA memory block. Will be computed and set by @@ -536,8 +538,17 @@ typedef struct { * XUsbPs_ConfigureDevice() function call */ typedef struct { +#ifndef SDT u16 DeviceID; /**< Unique ID of controller. */ +#else + char *Name; /**< Unique Name of controller */ +#endif u32 BaseAddress; /**< Core register base address. */ +#ifdef SDT + u16 IntrId; /** Bits[11:0] Interrupt-id Bits[15:12] trigger type */ + /** level flags */ + UINTPTR IntrParent; /** Bit[0] Interrupt parent type Bit[64/32:1] */ +#endif } XUsbPs_Config; typedef XUsbPs_Config Usb_Config; @@ -556,7 +567,7 @@ struct Usb_DevData { */ typedef struct { XUsbPs_SetupData SetupData; - /**< Setup Packet buffer */ + /**< Setup Packet buffer */ XUsbPs_Config Config; /**< Configuration structure */ int CurrentAltSetting; /**< Current alternative setting of interface */ @@ -573,15 +584,15 @@ typedef struct { * XUsbPs_ConfigureDevice() function call. */ XUsbPs_DeviceConfig DeviceConfig; - /**< Configuration for the DEVICE mode. */ + /**< Configuration for the DEVICE mode. */ XUsbPs_IntrHandlerFunc HandlerFunc; - /**< Handler function for the controller. */ + /**< Handler function for the controller. */ void *HandlerRef; - /**< User data reference for the handler. */ + /**< User data reference for the handler. */ u32 HandlerMask; - /**< User interrupt mask. Defines which interrupts will cause - * the callback to be called. */ + /**< User interrupt mask. Defines which interrupts will cause + * the callback to be called. */ struct Usb_DevData *AppData; u8 IsConfigDone; void *data_ptr; /* pointer for storing applications data */ @@ -655,7 +666,7 @@ typedef struct { ******************************************************************************/ #define XUsbPs_ForceFS(InstancePtr) \ XUsbPs_SetBits(InstancePtr, XUSBPS_PORTSCR1_OFFSET, \ - XUSBPS_PORTSCR_PFSC_MASK) + XUSBPS_PORTSCR_PFSC_MASK) /*****************************************************************************/ @@ -671,14 +682,14 @@ typedef struct { * ******************************************************************************/ #define XUsbPs_StartTimer0(InstancePtr, Interval) \ -{ \ - XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress, \ - XUSBPS_TIMER0_LD_OFFSET, (Interval)); \ - XUsbPs_SetBits(InstancePtr, XUSBPS_TIMER0_CTL_OFFSET, \ - XUSBPS_TIMER_RUN_MASK | \ - XUSBPS_TIMER_RESET_MASK | \ - XUSBPS_TIMER_REPEAT_MASK); \ -} \ + { \ + XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress, \ + XUSBPS_TIMER0_LD_OFFSET, (Interval)); \ + XUsbPs_SetBits(InstancePtr, XUSBPS_TIMER0_CTL_OFFSET, \ + XUSBPS_TIMER_RUN_MASK | \ + XUSBPS_TIMER_RESET_MASK | \ + XUSBPS_TIMER_REPEAT_MASK); \ + } \ /*****************************************************************************/ @@ -693,7 +704,7 @@ typedef struct { ******************************************************************************/ #define XUsbPs_StopTimer0(InstancePtr) \ XUsbPs_ClrBits(InstancePtr, XUSBPS_TIMER0_CTL_OFFSET, \ - XUSBPS_TIMER_RUN_MASK) + XUSBPS_TIMER_RUN_MASK) /*****************************************************************************/ @@ -708,8 +719,8 @@ typedef struct { ******************************************************************************/ #define XUsbPs_ReadTimer0(InstancePtr) \ XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress, \ - XUSBPS_TIMER0_CTL_OFFSET) & \ - XUSBPS_TIMER_COUNTER_MASK + XUSBPS_TIMER0_CTL_OFFSET) & \ + XUSBPS_TIMER_COUNTER_MASK /*****************************************************************************/ @@ -724,7 +735,7 @@ typedef struct { ******************************************************************************/ #define XUsbPs_RemoteWakeup(InstancePtr) \ XUsbPs_SetBits(InstancePtr, XUSBPS_PORTSCR1_OFFSET, \ - XUSBPS_PORTSCR_FPR_MASK) + XUSBPS_PORTSCR_FPR_MASK) /****************************************************************************** @@ -749,8 +760,8 @@ typedef struct { ******************************************************************************/ #define XUsbPs_EpEnable(InstancePtr, EpNum, Dir) \ XUsbPs_SetBits(InstancePtr, XUSBPS_EPCRn_OFFSET(EpNum), \ - ((Dir) & XUSBPS_EP_DIRECTION_OUT ? XUSBPS_EPCR_RXE_MASK : 0) | \ - ((Dir) & XUSBPS_EP_DIRECTION_IN ? XUSBPS_EPCR_TXE_MASK : 0)) + ((Dir) & XUSBPS_EP_DIRECTION_OUT ? XUSBPS_EPCR_RXE_MASK : 0) | \ + ((Dir) & XUSBPS_EP_DIRECTION_IN ? XUSBPS_EPCR_TXE_MASK : 0)) /*****************************************************************************/ @@ -770,8 +781,8 @@ typedef struct { ******************************************************************************/ #define XUsbPs_EpDisable(InstancePtr, EpNum, Dir) \ XUsbPs_ClrBits(InstancePtr, XUSBPS_EPCRn_OFFSET(EpNum), \ - ((Dir) & XUSBPS_EP_DIRECTION_OUT ? XUSBPS_EPCR_RXE_MASK : 0) | \ - ((Dir) & XUSBPS_EP_DIRECTION_IN ? XUSBPS_EPCR_TXE_MASK : 0)) + ((Dir) & XUSBPS_EP_DIRECTION_OUT ? XUSBPS_EPCR_RXE_MASK : 0) | \ + ((Dir) & XUSBPS_EP_DIRECTION_IN ? XUSBPS_EPCR_TXE_MASK : 0)) /*****************************************************************************/ @@ -792,8 +803,8 @@ typedef struct { ******************************************************************************/ #define XUsbPs_EpStall(InstancePtr, EpNum, Dir) \ XUsbPs_SetBits(InstancePtr, XUSBPS_EPCRn_OFFSET(EpNum), \ - ((Dir) & XUSBPS_EP_DIRECTION_OUT ? XUSBPS_EPCR_RXS_MASK : 0) | \ - ((Dir) & XUSBPS_EP_DIRECTION_IN ? XUSBPS_EPCR_TXS_MASK : 0)) + ((Dir) & XUSBPS_EP_DIRECTION_OUT ? XUSBPS_EPCR_RXS_MASK : 0) | \ + ((Dir) & XUSBPS_EP_DIRECTION_IN ? XUSBPS_EPCR_TXS_MASK : 0)) /*****************************************************************************/ @@ -813,8 +824,8 @@ typedef struct { ******************************************************************************/ #define XUsbPs_EpUnStall(InstancePtr, EpNum, Dir) \ XUsbPs_ClrBits(InstancePtr, XUSBPS_EPCRn_OFFSET(EpNum), \ - ((Dir) & XUSBPS_EP_DIRECTION_OUT ? XUSBPS_EPCR_RXS_MASK : 0) | \ - ((Dir) & XUSBPS_EP_DIRECTION_IN ? XUSBPS_EPCR_TXS_MASK : 0)) + ((Dir) & XUSBPS_EP_DIRECTION_OUT ? XUSBPS_EPCR_RXS_MASK : 0) | \ + ((Dir) & XUSBPS_EP_DIRECTION_IN ? XUSBPS_EPCR_TXS_MASK : 0)) /*****************************************************************************/ @@ -834,8 +845,8 @@ typedef struct { ******************************************************************************/ #define XUsbPs_EpFlush(InstancePtr, EpNum, Dir) \ XUsbPs_SetBits(InstancePtr, XUSBPS_EPFLUSH_OFFSET, \ - 1 << (EpNum + ((Dir) & XUSBPS_EP_DIRECTION_OUT ? \ - XUSBPS_EPFLUSH_RX_SHIFT:XUSBPS_EPFLUSH_TX_SHIFT))) \ + 1 << (EpNum + ((Dir) & XUSBPS_EP_DIRECTION_OUT ? \ + XUSBPS_EPFLUSH_RX_SHIFT:XUSBPS_EPFLUSH_TX_SHIFT))) \ /*****************************************************************************/ /** @@ -849,7 +860,7 @@ typedef struct { * ******************************************************************************/ #define XUsbPs_IntrEnable(InstancePtr, IntrMask) \ - XUsbPs_SetBits(InstancePtr, XUSBPS_IER_OFFSET, IntrMask) + XUsbPs_SetBits(InstancePtr, XUSBPS_IER_OFFSET, IntrMask) /*****************************************************************************/ @@ -865,7 +876,7 @@ typedef struct { * ******************************************************************************/ #define XUsbPs_IntrDisable(InstancePtr, IntrMask) \ - XUsbPs_ClrBits(InstancePtr, XUSBPS_IER_OFFSET, IntrMask) + XUsbPs_ClrBits(InstancePtr, XUSBPS_IER_OFFSET, IntrMask) /*****************************************************************************/ @@ -914,7 +925,7 @@ typedef struct { ******************************************************************************/ #define XUsbPs_NakIntrClear(InstancePtr, NakIntrMask) \ XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress, \ - XUSBPS_EPNAKISR_OFFSET, NakIntrMask) + XUSBPS_EPNAKISR_OFFSET, NakIntrMask) @@ -940,8 +951,8 @@ typedef struct { * ******************************************************************************/ #define XUsbPs_SetIntrThreshold(InstancePtr, Threshold) \ - XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress, \ - XUSBPS_CMD_OFFSET, (Threshold))\ + XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress, \ + XUSBPS_CMD_OFFSET, (Threshold))\ /*****************************************************************************/ @@ -955,8 +966,8 @@ typedef struct { * ******************************************************************************/ #define XUsbPs_SetSetupTripwire(InstancePtr) \ - XUsbPs_SetBits(InstancePtr, XUSBPS_CMD_OFFSET, \ - XUSBPS_CMD_SUTW_MASK) + XUsbPs_SetBits(InstancePtr, XUSBPS_CMD_OFFSET, \ + XUSBPS_CMD_SUTW_MASK) /*****************************************************************************/ @@ -970,8 +981,8 @@ typedef struct { * ******************************************************************************/ #define XUsbPs_ClrSetupTripwire(InstancePtr) \ - XUsbPs_ClrBits(InstancePtr, XUSBPS_CMD_OFFSET, \ - XUSBPS_CMD_SUTW_MASK) + XUsbPs_ClrBits(InstancePtr, XUSBPS_CMD_OFFSET, \ + XUSBPS_CMD_SUTW_MASK) /*****************************************************************************/ @@ -989,9 +1000,9 @@ typedef struct { * ******************************************************************************/ #define XUsbPs_SetupTripwireIsSet(InstancePtr) \ - (XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress, \ - XUSBPS_CMD_OFFSET) & \ - XUSBPS_CMD_SUTW_MASK ? TRUE : FALSE) + (XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress, \ + XUSBPS_CMD_OFFSET) & \ + XUSBPS_CMD_SUTW_MASK ? TRUE : FALSE) /****************************************************************************** @@ -1015,8 +1026,8 @@ typedef struct { *****************************************************************************/ #define XUsbPs_SetBits(InstancePtr, RegOffset, Bits) \ XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress, RegOffset, \ - XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress, \ - RegOffset) | (Bits)); + XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress, \ + RegOffset) | (Bits)); /****************************************************************************/ @@ -1037,8 +1048,8 @@ typedef struct { *****************************************************************************/ #define XUsbPs_ClrBits(InstancePtr, RegOffset, Bits) \ XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress, RegOffset, \ - XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress, \ - RegOffset) & ~(Bits)); + XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress, \ + RegOffset) & ~(Bits)); /************************** Function Prototypes ******************************/ @@ -1049,10 +1060,10 @@ typedef struct { * Implemented in file xusbps.c */ int XUsbPs_CfgInitialize(XUsbPs *InstancePtr, - const XUsbPs_Config *ConfigPtr, u32 BaseAddress); + const XUsbPs_Config *ConfigPtr, u32 BaseAddress); int XUsbPs_ConfigureDevice(XUsbPs *InstancePtr, - const XUsbPs_DeviceConfig *CfgPtr); + const XUsbPs_DeviceConfig *CfgPtr); /** * Common functions used for DEVICE/HOST mode. @@ -1086,23 +1097,23 @@ int XUsbPs_RequestHostResume(const XUsbPs *InstancePtr); int XUsbPs_EpBufferSend(XUsbPs *InstancePtr, u8 EpNum, const u8 *BufferPtr, u32 BufferLen); int XUsbPs_EpBufferSendWithZLT(XUsbPs *InstancePtr, u8 EpNum, - const u8 *BufferPtr, u32 BufferLen); + const u8 *BufferPtr, u32 BufferLen); int XUsbPs_EpBufferReceive(XUsbPs *InstancePtr, u8 EpNum, - u8 **BufferPtr, u32 *BufferLenPtr, u32 *Handle); + u8 **BufferPtr, u32 *BufferLenPtr, u32 *Handle); void XUsbPs_EpBufferRelease(u32 Handle); int XUsbPs_EpSetHandler(XUsbPs *InstancePtr, u8 EpNum, u8 Direction, XUsbPs_EpHandlerFunc CallBackFunc, void *CallBackRef); s32 XUsbPs_EpSetIsoHandler(XUsbPs *InstancePtr, u8 EpNum, u8 Direction, - XUsbPs_EpIsoHandlerFunc CallBackFunc); + XUsbPs_EpIsoHandlerFunc CallBackFunc); int XUsbPs_EpGetSetupData(XUsbPs *InstancePtr, int EpNum, - XUsbPs_SetupData *SetupDataPtr); + XUsbPs_SetupData *SetupDataPtr); int XUsbPs_EpPrime(XUsbPs *InstancePtr, u8 EpNum, u8 Direction); int XUsbPs_ReconfigureEp(XUsbPs *InstancePtr, XUsbPs_DeviceConfig *CfgPtr, - int EpNum, unsigned short NewDirection, int DirectionChanged); + int EpNum, unsigned short NewDirection, int DirectionChanged); /* * Interrupt handling functions @@ -1112,17 +1123,21 @@ int XUsbPs_ReconfigureEp(XUsbPs *InstancePtr, XUsbPs_DeviceConfig *CfgPtr, void XUsbPs_IntrHandler(void *InstancePtr); int XUsbPs_IntrSetHandler(XUsbPs *InstancePtr, - XUsbPs_IntrHandlerFunc CallBackFunc, - void *CallBackRef, u32 Mask); + XUsbPs_IntrHandlerFunc CallBackFunc, + void *CallBackRef, u32 Mask); void XUsbPs_EpGetData(XUsbPs *InstancePtr, u8 EpNum, u32 BufferLen); s32 XUsbPs_EpDataBufferReceive(XUsbPs *InstancePtr, u8 EpNum, - u8 *BufferPtr, u32 BufferLen); + u8 *BufferPtr, u32 BufferLen); /* * Helper functions for static configuration. * Implemented in xusbps_sinit.c */ +#ifndef SDT XUsbPs_Config *XUsbPs_LookupConfig(u16 DeviceId); +#else +XUsbPs_Config *XUsbPs_LookupConfig(u32 BaseAddress); +#endif #ifdef __cplusplus } diff --git a/bsp_z7/ps7_cortexa9_0/include/xusbps_endpoint.h b/bsp_z7/ps7_cortexa9_0/include/xusbps_endpoint.h index b924726..2869929 100644 --- a/bsp_z7/ps7_cortexa9_0/include/xusbps_endpoint.h +++ b/bsp_z7/ps7_cortexa9_0/include/xusbps_endpoint.h @@ -1,5 +1,6 @@ /****************************************************************************** * Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved. +* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -7,7 +8,7 @@ /** * * @file xusbps_endpoint.h -* @addtogroup usbps_v2_7 +* @addtogroup usbps Overview * @{ * * This is an internal file containung the definitions for endpoints. It is @@ -67,9 +68,9 @@ extern "C" { * @{ */ #define XUSBPS_dTDNLP_T_MASK 0x00000001 - /**< USB dTD Next Link Pointer Terminate Bit */ +/**< USB dTD Next Link Pointer Terminate Bit */ #define XUSBPS_dTDNLP_ADDR_MASK 0xFFFFFFE0 - /**< USB dTD Next Link Pointer Address [31:5] */ +/**< USB dTD Next Link Pointer Address [31:5] */ /* @} */ @@ -108,16 +109,16 @@ extern "C" { * ******************************************************************************/ #define XUsbPs_dTDInvalidateCache(dTDPtr) \ - Xil_DCacheInvalidateRange((unsigned int)dTDPtr, sizeof(XUsbPs_dTD)) + Xil_DCacheInvalidateRange((unsigned int)dTDPtr, sizeof(XUsbPs_dTD)) #define XUsbPs_dTDFlushCache(dTDPtr) \ - Xil_DCacheFlushRange((unsigned int)dTDPtr, sizeof(XUsbPs_dTD)) + Xil_DCacheFlushRange((unsigned int)dTDPtr, sizeof(XUsbPs_dTD)) #define XUsbPs_dQHInvalidateCache(dQHPtr) \ - Xil_DCacheInvalidateRange((unsigned int)dQHPtr, sizeof(XUsbPs_dQH)) + Xil_DCacheInvalidateRange((unsigned int)dQHPtr, sizeof(XUsbPs_dQH)) #define XUsbPs_dQHFlushCache(dQHPtr) \ - Xil_DCacheFlushRange((unsigned int)dQHPtr, sizeof(XUsbPs_dQH)) + Xil_DCacheFlushRange((unsigned int)dQHPtr, sizeof(XUsbPs_dQH)) /*****************************************************************************/ /** @@ -132,9 +133,9 @@ extern "C" { * ******************************************************************************/ #define XUsbPs_dTDSetTransferLen(dTDPtr, Len) \ - XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDTOKEN, \ + XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDTOKEN, \ (XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) & \ - ~XUSBPS_dTDTOKEN_LEN_MASK) | ((Len) << 16)) + ~XUSBPS_dTDTOKEN_LEN_MASK) | ((Len) << 16)) /*****************************************************************************/ @@ -151,8 +152,8 @@ extern "C" { * ******************************************************************************/ #define XUsbPs_dTDGetNLP(dTDPtr) \ - (XUsbPs_dTD *) ((XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDNLP)\ - & XUSBPS_dTDNLP_ADDR_MASK)) + (XUsbPs_dTD *) ((XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDNLP)\ + & XUSBPS_dTDNLP_ADDR_MASK)) /*****************************************************************************/ @@ -168,10 +169,10 @@ extern "C" { * ******************************************************************************/ #define XUsbPs_dTDSetNLP(dTDPtr, NLP) \ - XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDNLP, \ + XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDNLP, \ (XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDNLP) & \ - ~XUSBPS_dTDNLP_ADDR_MASK) | \ - ((NLP) & XUSBPS_dTDNLP_ADDR_MASK)) + ~XUSBPS_dTDNLP_ADDR_MASK) | \ + ((NLP) & XUSBPS_dTDNLP_ADDR_MASK)) /*****************************************************************************/ @@ -188,8 +189,8 @@ extern "C" { * ******************************************************************************/ #define XUsbPs_dTDGetTransferLen(dTDPtr) \ - (u32) ((XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) \ - & XUSBPS_dTDTOKEN_LEN_MASK) >> 16) + (u32) ((XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) \ + & XUSBPS_dTDTOKEN_LEN_MASK) >> 16) /*****************************************************************************/ @@ -205,9 +206,9 @@ extern "C" { * ******************************************************************************/ #define XUsbPs_dTDSetIOC(dTDPtr) \ - XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDTOKEN, \ + XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDTOKEN, \ XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) | \ - XUSBPS_dTDTOKEN_IOC_MASK) + XUSBPS_dTDTOKEN_IOC_MASK) /*****************************************************************************/ @@ -222,9 +223,9 @@ extern "C" { * ******************************************************************************/ #define XUsbPs_dTDSetTerminate(dTDPtr) \ - XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDNLP, \ + XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDNLP, \ XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDNLP) | \ - XUSBPS_dTDNLP_T_MASK) + XUSBPS_dTDNLP_T_MASK) /*****************************************************************************/ @@ -239,9 +240,9 @@ extern "C" { * ******************************************************************************/ #define XUsbPs_dTDClrTerminate(dTDPtr) \ - XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDNLP, \ + XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDNLP, \ XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDNLP) & \ - ~XUSBPS_dTDNLP_T_MASK) + ~XUSBPS_dTDNLP_T_MASK) /*****************************************************************************/ @@ -260,8 +261,8 @@ extern "C" { * ******************************************************************************/ #define XUsbPs_dTDIsActive(dTDPtr) \ - ((XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) & \ - XUSBPS_dTDTOKEN_ACTIVE_MASK) ? TRUE : FALSE) + ((XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) & \ + XUSBPS_dTDTOKEN_ACTIVE_MASK) ? TRUE : FALSE) /*****************************************************************************/ @@ -276,9 +277,9 @@ extern "C" { * ******************************************************************************/ #define XUsbPs_dTDSetActive(dTDPtr) \ - XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDTOKEN, \ + XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDTOKEN, \ XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) | \ - XUSBPS_dTDTOKEN_ACTIVE_MASK) + XUSBPS_dTDTOKEN_ACTIVE_MASK) /*****************************************************************************/ /** @@ -293,9 +294,9 @@ extern "C" { * ******************************************************************************/ #define XUsbPs_dTDSetMultO(dTDPtr, val) \ - XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDTOKEN, \ + XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDTOKEN, \ (XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) & \ - (~XUSBPS_dTDTOKEN_MULTO_MASK)) | val) + (~XUSBPS_dTDTOKEN_MULTO_MASK)) | val) /*****************************************************************************/ @@ -326,7 +327,7 @@ extern "C" { * ******************************************************************************/ #define XUsbPs_WritedTD(dTDPtr, Id, Val) \ - (*(u32 *) ((u32)(dTDPtr) + (u32)(Id)) = (u32)(Val)) + (*(u32 *) ((u32)(dTDPtr) + (u32)(Id)) = (u32)(Val)) /******************************************************************************/ @@ -368,17 +369,17 @@ extern "C" { * @{ */ #define XUSBPS_dQHCFG_IOS_MASK 0x00008000 - /**< USB dQH Interrupt on Setup Bit */ +/**< USB dQH Interrupt on Setup Bit */ #define XUSBPS_dQHCFG_MPL_MASK 0x07FF0000 - /**< USB dQH Maximum Packet Length - * Field [10:0] */ +/**< USB dQH Maximum Packet Length + * Field [10:0] */ #define XUSBPS_dQHCFG_MPL_SHIFT 16 #define XUSBPS_dQHCFG_ZLT_MASK 0x20000000 - /**< USB dQH Zero Length Termination - * Select Bit */ +/**< USB dQH Zero Length Termination + * Select Bit */ #define XUSBPS_dQHCFG_MULT_MASK 0xC0000000 - /* USB dQH Number of Transactions Field - * [1:0] */ +/* USB dQH Number of Transactions Field + * [1:0] */ #define XUSBPS_dQHCFG_MULT_SHIFT 30 /* @} */ @@ -396,9 +397,9 @@ extern "C" { * ******************************************************************************/ #define XUsbPs_dQHSetMaxPacketLen(dQHPtr, Len) \ - XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, \ + XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, \ (XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) & \ - ~XUSBPS_dQHCFG_MPL_MASK) | ((Len) << 16)) + ~XUSBPS_dQHCFG_MPL_MASK) | ((Len) << 16)) /*****************************************************************************/ /** @@ -412,9 +413,9 @@ extern "C" { * ******************************************************************************/ #define XUsbPs_dQHSetIOS(dQHPtr) \ - XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, \ + XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, \ XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) | \ - XUSBPS_dQHCFG_IOS_MASK) + XUSBPS_dQHCFG_IOS_MASK) /*****************************************************************************/ /** @@ -428,9 +429,9 @@ extern "C" { * ******************************************************************************/ #define XUsbPs_dQHClrIOS(dQHPtr) \ - XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, \ + XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, \ XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) & \ - ~XUSBPS_dQHCFG_IOS_MASK) + ~XUSBPS_dQHCFG_IOS_MASK) /*****************************************************************************/ /** @@ -445,9 +446,9 @@ extern "C" { * ******************************************************************************/ #define XUsbPs_dQHEnableZLT(dQHPtr) \ - XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, \ + XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, \ XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) & \ - ~XUSBPS_dQHCFG_ZLT_MASK) + ~XUSBPS_dQHCFG_ZLT_MASK) /*****************************************************************************/ @@ -463,9 +464,9 @@ extern "C" { * ******************************************************************************/ #define XUsbPs_dQHDisableZLT(dQHPtr) \ - XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, \ + XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, \ XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) | \ - XUSBPS_dQHCFG_ZLT_MASK) + XUSBPS_dQHCFG_ZLT_MASK) /*****************************************************************************/ /** @@ -495,7 +496,7 @@ extern "C" { * ******************************************************************************/ #define XUsbPs_WritedQH(dQHPtr, Id, Val) \ - (*(u32 *) ((u32)(dQHPtr) + (u32)(Id)) = (u32)(Val)) + (*(u32 *) ((u32)(dQHPtr) + (u32)(Id)) = (u32)(Val)) diff --git a/bsp_z7/ps7_cortexa9_0/include/xusbps_hw.h b/bsp_z7/ps7_cortexa9_0/include/xusbps_hw.h index 4f985dc..2f057a6 100644 --- a/bsp_z7/ps7_cortexa9_0/include/xusbps_hw.h +++ b/bsp_z7/ps7_cortexa9_0/include/xusbps_hw.h @@ -1,5 +1,6 @@ /****************************************************************************** * Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved. +* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -7,7 +8,7 @@ /** * * @file xusbps_hw.h -* @addtogroup usbps_v2_7 +* @addtogroup usbps Overview * @{ * * This header file contains identifiers and low-level driver functions (or @@ -22,7 +23,7 @@ * 1.00a wgr 10/10/10 First release * 1.04a nm 10/23/12 Fixed CR# 679106. * 1.05a kpc 07/03/13 Added XUsbPs_ResetHw function prototype - * 2.00a kpc 04/03/14 Fixed CR#777764. Corrected max endpoint vale and masks + * 2.00a kpc 04/03/14 Fixed CR#777764. Corrected max endpoint vale and masks * 2.5 pm 02/20/20 Added Endpoint Control Register bit positions for Rx & Tx * * @@ -110,7 +111,7 @@ extern "C" { /* NOTE: The Port Control / Status Register index is 1-based. */ #define XUSBPS_PORTSCRn_OFFSET(n) \ - (XUSBPS_PORTSCR1_OFFSET + (((n)-1) * XUSBPS_REG_SPACING)) + (XUSBPS_PORTSCR1_OFFSET + (((n)-1) * XUSBPS_REG_SPACING)) #define XUSBPS_OTGCSR_OFFSET 0x000001A4 /**< OTG Status and Control */ @@ -133,7 +134,7 @@ extern "C" { #define XUSBPS_EP_ALL_MASK 0x0FFF0FFF /**< Mask used for endpoint control * registers */ #define XUSBPS_EPCRn_OFFSET(n) \ - (XUSBPS_EPCR0_OFFSET + ((n) * XUSBPS_REG_SPACING)) + (XUSBPS_EPCR0_OFFSET + ((n) * XUSBPS_REG_SPACING)) #define XUSBPS_EPFLUSH_RX_SHIFT 0 #define XUSBPS_EPFLUSH_TX_SHIFT 16 @@ -251,24 +252,24 @@ extern "C" { #define XUSBPS_IXR_TI1_MASK 0x02000000 /**< Timer 1 Interrupt */ #define XUSBPS_IXR_ALL (XUSBPS_IXR_UI_MASK | \ - XUSBPS_IXR_UE_MASK | \ - XUSBPS_IXR_PC_MASK | \ - XUSBPS_IXR_FRE_MASK | \ - XUSBPS_IXR_AA_MASK | \ - XUSBPS_IXR_UR_MASK | \ - XUSBPS_IXR_SR_MASK | \ - XUSBPS_IXR_SLE_MASK | \ - XUSBPS_IXR_ULPI_MASK | \ - XUSBPS_IXR_HCH_MASK | \ - XUSBPS_IXR_RCL_MASK | \ - XUSBPS_IXR_PS_MASK | \ - XUSBPS_IXR_AS_MASK | \ - XUSBPS_IXR_NAK_MASK | \ - XUSBPS_IXR_UA_MASK | \ - XUSBPS_IXR_UP_MASK | \ - XUSBPS_IXR_TI0_MASK | \ - XUSBPS_IXR_TI1_MASK) - /**< Mask for ALL IRQ types */ + XUSBPS_IXR_UE_MASK | \ + XUSBPS_IXR_PC_MASK | \ + XUSBPS_IXR_FRE_MASK | \ + XUSBPS_IXR_AA_MASK | \ + XUSBPS_IXR_UR_MASK | \ + XUSBPS_IXR_SR_MASK | \ + XUSBPS_IXR_SLE_MASK | \ + XUSBPS_IXR_ULPI_MASK | \ + XUSBPS_IXR_HCH_MASK | \ + XUSBPS_IXR_RCL_MASK | \ + XUSBPS_IXR_PS_MASK | \ + XUSBPS_IXR_AS_MASK | \ + XUSBPS_IXR_NAK_MASK | \ + XUSBPS_IXR_UA_MASK | \ + XUSBPS_IXR_UP_MASK | \ + XUSBPS_IXR_TI0_MASK | \ + XUSBPS_IXR_TI1_MASK) +/**< Mask for ALL IRQ types */ /* @} */ @@ -291,13 +292,13 @@ extern "C" { * @{ */ #define XUSBPS_DEVICEADDR_DEVICEAADV_MASK 0x01000000 - /**< Device Addr Auto Advance */ +/**< Device Addr Auto Advance */ #define XUSBPS_DEVICEADDR_ADDR_MASK 0xFE000000 - /**< Device Address */ +/**< Device Address */ #define XUSBPS_DEVICEADDR_ADDR_SHIFT 25 - /**< Address shift */ +/**< Address shift */ #define XUSBPS_DEVICEADDR_MAX 127 - /**< Biggest allowed address */ +/**< Biggest allowed address */ /* @} */ /** @name USB TT Control Register (TTCTRL) bit positions. @@ -319,11 +320,11 @@ extern "C" { * @{ */ #define XUSBPS_TXFILL_OVERHEAD_MASK 0x000000FF - /**< Scheduler Overhead */ +/**< Scheduler Overhead */ #define XUSBPS_TXFILL_HEALTH_MASK 0x00001F00 - /**< Scheduler Health Cntr */ +/**< Scheduler Health Cntr */ #define XUSBPS_TXFILL_BURST_MASK 0x003F0000 - /**< FIFO Burst Threshold */ +/**< FIFO Burst Threshold */ /* @} */ @@ -411,22 +412,22 @@ extern "C" { * Enable Bit */ #define XUSBPS_OTG_ISB_ALL (XUSBPS_OTGSC_IDIS_MASK |\ - XUSBPS_OTGSC_AVVIS_MASK | \ - XUSBPS_OTGSC_ASVIS_MASK | \ - XUSBPS_OTGSC_BSVIS_MASK | \ - XUSBPS_OTGSC_BSEIS_MASK | \ - XUSBPS_OTGSC_1MSS_MASK | \ - XUSBPS_OTGSC_DPIS_MASK) - /** Mask for All IRQ status masks */ + XUSBPS_OTGSC_AVVIS_MASK | \ + XUSBPS_OTGSC_ASVIS_MASK | \ + XUSBPS_OTGSC_BSVIS_MASK | \ + XUSBPS_OTGSC_BSEIS_MASK | \ + XUSBPS_OTGSC_1MSS_MASK | \ + XUSBPS_OTGSC_DPIS_MASK) +/** Mask for All IRQ status masks */ #define XUSBPS_OTG_IEB_ALL (XUSBPS_OTGSC_IDIE_MASK |\ - XUSBPS_OTGSC_AVVIE_MASK | \ - XUSBPS_OTGSC_ASVIE_MASK | \ - XUSBPS_OTGSC_BSVIE_MASK | \ - XUSBPS_OTGSC_BSEE_IEB_MASK | \ - XUSBPS_OTGSC_1MSE_MASK | \ - XUSBPS_OTGSC_DPIE_MASK) - /** Mask for All IRQ Enable masks */ + XUSBPS_OTGSC_AVVIE_MASK | \ + XUSBPS_OTGSC_ASVIE_MASK | \ + XUSBPS_OTGSC_BSVIE_MASK | \ + XUSBPS_OTGSC_BSEE_IEB_MASK | \ + XUSBPS_OTGSC_1MSE_MASK | \ + XUSBPS_OTGSC_DPIE_MASK) +/** Mask for All IRQ Enable masks */ /* @} */ @@ -468,7 +469,7 @@ extern "C" { * *****************************************************************************/ #define XUsbPs_ReadReg(BaseAddress, RegOffset) \ - Xil_In32(BaseAddress + (RegOffset)) + Xil_In32(BaseAddress + (RegOffset)) /****************************************************************************/ @@ -487,7 +488,7 @@ extern "C" { * *****************************************************************************/ #define XUsbPs_WriteReg(BaseAddress, RegOffset, Data) \ - Xil_Out32(BaseAddress + (RegOffset), (Data)) + Xil_Out32(BaseAddress + (RegOffset), (Data)) /************************** Function Prototypes ******************************/ diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/cpu_cortexa9/src/xcpu_cortexa9.h b/bsp_z7/ps7_cortexa9_0/libsrc/cpu_cortexa9/src/xcpu_cortexa9.h index 3c23a5f..f6b3728 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/cpu_cortexa9/src/xcpu_cortexa9.h +++ b/bsp_z7/ps7_cortexa9_0/libsrc/cpu_cortexa9/src/xcpu_cortexa9.h @@ -1,5 +1,6 @@ /****************************************************************************** * Copyright (C) 2011 - 2021 Xilinx, Inc. All rights reserved. +* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -7,7 +8,7 @@ /** * * @file xcpu_cortexa9.h -* @addtogroup cpu_cortexa9_v2_11 +* @addtogroup cpu_cortexa9 Overview * @{ * @details * diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/devcfg/src/xdevcfg.c b/bsp_z7/ps7_cortexa9_0/libsrc/devcfg/src/xdevcfg.c index 5bac22a..6730ca1 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/devcfg/src/xdevcfg.c +++ b/bsp_z7/ps7_cortexa9_0/libsrc/devcfg/src/xdevcfg.c @@ -1,5 +1,6 @@ /****************************************************************************** -* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved. +* Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -7,7 +8,7 @@ /** * * @file xdevcfg.c -* @addtogroup devcfg_v3_7 +* @addtogroup devcfg Overview * @{ * * This file contains the implementation of the interface functions for XDcfg @@ -55,7 +56,7 @@ * XDCFG_INT_STS_OFFSET) & * XDCFG_IXR_D_P_DONE_MASK) != * XDCFG_IXR_D_P_DONE_MASK); -* +* 3.8 Nava 06/21/23 Added support for system device-tree flow. * * * @@ -106,7 +107,7 @@ * ******************************************************************************/ int XDcfg_CfgInitialize(XDcfg *InstancePtr, - XDcfg_Config *ConfigPtr, u32 EffectiveAddress) + XDcfg_Config *ConfigPtr, u32 EffectiveAddress) { Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(ConfigPtr != NULL); @@ -124,7 +125,9 @@ int XDcfg_CfgInitialize(XDcfg *InstancePtr, /* * Copy configuration into instance. */ +#ifndef SDT InstancePtr->Config.DeviceId = ConfigPtr->DeviceId; +#endif /* * Save the base address pointer such that the registers of the block @@ -172,10 +175,10 @@ void XDcfg_EnablePCAP(XDcfg *InstancePtr) CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr, - XDCFG_CTRL_OFFSET); + XDCFG_CTRL_OFFSET); XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_CTRL_OFFSET, - (CtrlReg | XDCFG_CTRL_PCAP_MODE_MASK)); + (CtrlReg | XDCFG_CTRL_PCAP_MODE_MASK)); } @@ -203,10 +206,10 @@ void XDcfg_DisablePCAP(XDcfg *InstancePtr) CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr, - XDCFG_CTRL_OFFSET); + XDCFG_CTRL_OFFSET); XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_CTRL_OFFSET, - (CtrlReg & ( ~XDCFG_CTRL_PCAP_MODE_MASK))); + (CtrlReg & ( ~XDCFG_CTRL_PCAP_MODE_MASK))); } @@ -235,10 +238,10 @@ void XDcfg_SetControlRegister(XDcfg *InstancePtr, u32 Mask) CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr, - XDCFG_CTRL_OFFSET); + XDCFG_CTRL_OFFSET); XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_CTRL_OFFSET, - (CtrlReg | Mask)); + (CtrlReg | Mask)); } @@ -266,10 +269,10 @@ void XDcfg_ClearControlRegister(XDcfg *InstancePtr, u32 Mask) CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr, - XDCFG_CTRL_OFFSET); + XDCFG_CTRL_OFFSET); XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_CTRL_OFFSET, - (CtrlReg & ~Mask)); + (CtrlReg & ~Mask)); } @@ -488,7 +491,7 @@ void XDcfg_SetRomShadowRegister(XDcfg *InstancePtr, u32 Data) Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_ROM_SHADOW_OFFSET, - Data); + Data); } @@ -545,10 +548,10 @@ void XDcfg_SetMiscControlRegister(XDcfg *InstancePtr, u32 Mask) RegData = XDcfg_ReadReg(InstancePtr->Config.BaseAddr, - XDCFG_MCTRL_OFFSET); + XDCFG_MCTRL_OFFSET); XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_MCTRL_OFFSET, - (RegData | Mask)); + (RegData | Mask)); } /****************************************************************************/ @@ -601,10 +604,10 @@ u32 XDcfg_IsDmaBusy(XDcfg *InstancePtr) /* Read the PCAP status register for DMA status */ RegData = XDcfg_ReadReg(InstancePtr->Config.BaseAddr, - XDCFG_STATUS_OFFSET); + XDCFG_STATUS_OFFSET); if ((RegData & XDCFG_STATUS_DMA_CMD_Q_F_MASK) == - XDCFG_STATUS_DMA_CMD_Q_F_MASK){ + XDCFG_STATUS_DMA_CMD_Q_F_MASK) { return XST_SUCCESS; } @@ -637,24 +640,24 @@ u32 XDcfg_IsDmaBusy(XDcfg *InstancePtr) * ****************************************************************************/ void XDcfg_InitiateDma(XDcfg *InstancePtr, u32 SourcePtr, u32 DestPtr, - u32 SrcWordLength, u32 DestWordLength) + u32 SrcWordLength, u32 DestWordLength) { XDcfg_WriteReg(InstancePtr->Config.BaseAddr, - XDCFG_DMA_SRC_ADDR_OFFSET, - SourcePtr); + XDCFG_DMA_SRC_ADDR_OFFSET, + SourcePtr); XDcfg_WriteReg(InstancePtr->Config.BaseAddr, - XDCFG_DMA_DEST_ADDR_OFFSET, - DestPtr); + XDCFG_DMA_DEST_ADDR_OFFSET, + DestPtr); XDcfg_WriteReg(InstancePtr->Config.BaseAddr, - XDCFG_DMA_SRC_LEN_OFFSET, - SrcWordLength); + XDCFG_DMA_SRC_LEN_OFFSET, + SrcWordLength); XDcfg_WriteReg(InstancePtr->Config.BaseAddr, - XDCFG_DMA_DEST_LEN_OFFSET, - DestWordLength); + XDCFG_DMA_DEST_LEN_OFFSET, + DestWordLength); } /******************************************************************************/ @@ -680,8 +683,8 @@ void XDcfg_InitiateDma(XDcfg *InstancePtr, u32 SourcePtr, u32 DestPtr, * ****************************************************************************/ static u32 XDcfg_PcapReadback(XDcfg *InstancePtr, u32 SourcePtr, - u32 SrcWordLength, u32 DestPtr, - u32 DestWordLength) + u32 SrcWordLength, u32 DestPtr, + u32 DestWordLength) { u32 IntrReg; @@ -689,7 +692,7 @@ static u32 XDcfg_PcapReadback(XDcfg *InstancePtr, u32 SourcePtr, * Send READ Frame command to FPGA */ XDcfg_InitiateDma(InstancePtr, SourcePtr, XDCFG_DMA_INVALID_ADDRESS, - SrcWordLength, 0); + SrcWordLength, 0); /* * Store the enabled interrupts to enable before the actual read @@ -701,10 +704,10 @@ static u32 XDcfg_PcapReadback(XDcfg *InstancePtr, u32 SourcePtr, /* * Wait till you get the DMA done for the read command sent */ - while ((XDcfg_ReadReg(InstancePtr->Config.BaseAddr, - XDCFG_INT_STS_OFFSET) & - XDCFG_IXR_D_P_DONE_MASK) != - XDCFG_IXR_D_P_DONE_MASK); + while ((XDcfg_ReadReg(InstancePtr->Config.BaseAddr, + XDCFG_INT_STS_OFFSET) & + XDCFG_IXR_D_P_DONE_MASK) != + XDCFG_IXR_D_P_DONE_MASK); /* * Enable the previously stored Interrupts . */ @@ -714,7 +717,7 @@ static u32 XDcfg_PcapReadback(XDcfg *InstancePtr, u32 SourcePtr, * Initiate the DMA write command. */ XDcfg_InitiateDma(InstancePtr, XDCFG_DMA_INVALID_ADDRESS, (u32)DestPtr, - 0, DestWordLength); + 0, DestWordLength); return XST_SUCCESS; } @@ -762,9 +765,9 @@ static u32 XDcfg_PcapReadback(XDcfg *InstancePtr, u32 SourcePtr, * *****************************************************************************/ u32 XDcfg_Transfer(XDcfg *InstancePtr, - void *SourcePtr, u32 SrcWordLength, - void *DestPtr, u32 DestWordLength, - u32 TransferType) + void *SourcePtr, u32 SrcWordLength, + void *DestPtr, u32 DestWordLength, + u32 TransferType) { u32 CtrlReg; @@ -781,7 +784,7 @@ u32 XDcfg_Transfer(XDcfg *InstancePtr, * Check whether the fabric is in initialized state */ if ((XDcfg_ReadReg(InstancePtr->Config.BaseAddr, XDCFG_STATUS_OFFSET) - & XDCFG_STATUS_PCFG_INIT_MASK) == 0) { + & XDCFG_STATUS_PCFG_INIT_MASK) == 0) { /* * We don't need to check PCFG_INIT to be high for * non-encrypted loopback transfers. @@ -792,7 +795,7 @@ u32 XDcfg_Transfer(XDcfg *InstancePtr, } if ((TransferType == XDCFG_SECURE_PCAP_WRITE) || - (TransferType == XDCFG_NON_SECURE_PCAP_WRITE)) { + (TransferType == XDCFG_NON_SECURE_PCAP_WRITE)) { /* Check for valid source pointer and length */ if ((!SourcePtr) || (SrcWordLength == 0)) { @@ -803,8 +806,8 @@ u32 XDcfg_Transfer(XDcfg *InstancePtr, CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr, XDCFG_MCTRL_OFFSET); XDcfg_WriteReg(InstancePtr->Config.BaseAddr, - XDCFG_MCTRL_OFFSET, (CtrlReg & - ~(XDCFG_MCTRL_PCAP_LPBK_MASK))); + XDCFG_MCTRL_OFFSET, (CtrlReg & + ~(XDCFG_MCTRL_PCAP_LPBK_MASK))); if (TransferType == XDCFG_NON_SECURE_PCAP_WRITE) { /* @@ -815,8 +818,8 @@ u32 XDcfg_Transfer(XDcfg *InstancePtr, XDCFG_CTRL_OFFSET); XDcfg_WriteReg(InstancePtr->Config.BaseAddr, - XDCFG_CTRL_OFFSET, (CtrlReg & - ~XDCFG_CTRL_PCAP_RATE_EN_MASK)); + XDCFG_CTRL_OFFSET, (CtrlReg & + ~XDCFG_CTRL_PCAP_RATE_EN_MASK)); } if (TransferType == XDCFG_SECURE_PCAP_WRITE) { @@ -828,11 +831,11 @@ u32 XDcfg_Transfer(XDcfg *InstancePtr, * operation. */ XDcfg_SetControlRegister(InstancePtr, - XDCFG_CTRL_PCAP_RATE_EN_MASK); + XDCFG_CTRL_PCAP_RATE_EN_MASK); } XDcfg_InitiateDma(InstancePtr, (u32)SourcePtr, - (u32)DestPtr, SrcWordLength, DestWordLength); + (u32)DestPtr, SrcWordLength, DestWordLength); } @@ -847,8 +850,8 @@ u32 XDcfg_Transfer(XDcfg *InstancePtr, CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr, XDCFG_MCTRL_OFFSET); XDcfg_WriteReg(InstancePtr->Config.BaseAddr, - XDCFG_MCTRL_OFFSET, (CtrlReg & - ~(XDCFG_MCTRL_PCAP_LPBK_MASK))); + XDCFG_MCTRL_OFFSET, (CtrlReg & + ~(XDCFG_MCTRL_PCAP_LPBK_MASK))); /* * For PCAP readback of FPGA configuration register or memory, @@ -860,26 +863,26 @@ u32 XDcfg_Transfer(XDcfg *InstancePtr, * transfer to support this mode of operation. */ return XDcfg_PcapReadback(InstancePtr, - (u32)SourcePtr, SrcWordLength, - (u32)DestPtr, DestWordLength); + (u32)SourcePtr, SrcWordLength, + (u32)DestPtr, DestWordLength); } if ((TransferType == XDCFG_CONCURRENT_SECURE_READ_WRITE) || - (TransferType == XDCFG_CONCURRENT_NONSEC_READ_WRITE)) { + (TransferType == XDCFG_CONCURRENT_NONSEC_READ_WRITE)) { if ((!SourcePtr) || (SrcWordLength == 0) || - (!DestPtr) || (DestWordLength == 0)) { + (!DestPtr) || (DestWordLength == 0)) { return XST_INVALID_PARAM; } if (TransferType == XDCFG_CONCURRENT_NONSEC_READ_WRITE) { /* Enable internal PCAP loopback */ CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr, - XDCFG_MCTRL_OFFSET); + XDCFG_MCTRL_OFFSET); XDcfg_WriteReg(InstancePtr->Config.BaseAddr, - XDCFG_MCTRL_OFFSET, (CtrlReg | - XDCFG_MCTRL_PCAP_LPBK_MASK)); + XDCFG_MCTRL_OFFSET, (CtrlReg | + XDCFG_MCTRL_PCAP_LPBK_MASK)); /* * Clear QUARTER_PCAP_RATE_EN bit @@ -889,8 +892,8 @@ u32 XDcfg_Transfer(XDcfg *InstancePtr, XDCFG_CTRL_OFFSET); XDcfg_WriteReg(InstancePtr->Config.BaseAddr, - XDCFG_CTRL_OFFSET, (CtrlReg & - ~XDCFG_CTRL_PCAP_RATE_EN_MASK)); + XDCFG_CTRL_OFFSET, (CtrlReg & + ~XDCFG_CTRL_PCAP_RATE_EN_MASK)); } if (TransferType == XDCFG_CONCURRENT_SECURE_READ_WRITE) { @@ -898,8 +901,8 @@ u32 XDcfg_Transfer(XDcfg *InstancePtr, CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr, XDCFG_MCTRL_OFFSET); XDcfg_WriteReg(InstancePtr->Config.BaseAddr, - XDCFG_MCTRL_OFFSET, (CtrlReg & - ~(XDCFG_MCTRL_PCAP_LPBK_MASK))); + XDCFG_MCTRL_OFFSET, (CtrlReg & + ~(XDCFG_MCTRL_PCAP_LPBK_MASK))); /* * Set the QUARTER_PCAP_RATE_EN bit @@ -907,11 +910,11 @@ u32 XDcfg_Transfer(XDcfg *InstancePtr, * cycles, this is required for encrypted data. */ XDcfg_SetControlRegister(InstancePtr, - XDCFG_CTRL_PCAP_RATE_EN_MASK); + XDCFG_CTRL_PCAP_RATE_EN_MASK); } XDcfg_InitiateDma(InstancePtr, (u32)SourcePtr, - (u32)DestPtr, SrcWordLength, DestWordLength); + (u32)DestPtr, SrcWordLength, DestWordLength); } return XST_SUCCESS; diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/devcfg/src/xdevcfg.h b/bsp_z7/ps7_cortexa9_0/libsrc/devcfg/src/xdevcfg.h index e567699..694e3b3 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/devcfg/src/xdevcfg.h +++ b/bsp_z7/ps7_cortexa9_0/libsrc/devcfg/src/xdevcfg.h @@ -1,5 +1,6 @@ /****************************************************************************** -* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved. +* Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -7,7 +8,7 @@ /** * * @file xdevcfg.h -* @addtogroup devcfg_v3_7 +* @addtogroup devcfg Overview * @{ * @details * @@ -133,6 +134,7 @@ * 3.5 ms 04/18/17 Modified tcl file to add suffix U for all macros * definitions of devcfg in xparameters.h * ms 08/07/17 Fixed compilation warnings in xdevcfg_sinit.c +* 3.8 Nava 06/21/23 Added support for system device-tree flow. * * ******************************************************************************/ @@ -178,8 +180,18 @@ typedef void (*XDcfg_IntrHandler) (void *CallBackRef, u32 Status); * This typedef contains configuration information for the device. */ typedef struct { +#ifndef SDT u16 DeviceId; /**< Unique ID of device */ +#else + char *Name; +#endif u32 BaseAddr; /**< Base address of the device */ +#ifdef SDT + u32 IntrId; /** Bits[11:0] Interrupt-id Bits[15:12] + * trigger type and level flags */ + UINTPTR IntrParent; /** Bit[0] Interrupt parent type Bit[64/32:1] + * Parent base address */ +#endif } XDcfg_Config; /** @@ -210,7 +222,7 @@ typedef struct { *****************************************************************************/ #define XDcfg_Unlock(InstancePtr) \ XDcfg_WriteReg((InstancePtr)->Config.BaseAddr, \ - XDCFG_UNLOCK_OFFSET, XDCFG_UNLOCK_DATA) + XDCFG_UNLOCK_OFFSET, XDCFG_UNLOCK_DATA) @@ -230,8 +242,8 @@ typedef struct { #define XDcfg_GetPsVersion(InstancePtr) \ ((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, \ XDCFG_MCTRL_OFFSET)) & \ - XDCFG_MCTRL_PCAP_PS_VERSION_MASK) >> \ - XDCFG_MCTRL_PCAP_PS_VERSION_SHIFT + XDCFG_MCTRL_PCAP_PS_VERSION_MASK) >> \ + XDCFG_MCTRL_PCAP_PS_VERSION_SHIFT @@ -250,7 +262,7 @@ typedef struct { *****************************************************************************/ #define XDcfg_ReadMultiBootConfig(InstancePtr) \ XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, \ - XDCFG_MULTIBOOT_ADDR_OFFSET) + XDCFG_MULTIBOOT_ADDR_OFFSET) /****************************************************************************/ @@ -269,8 +281,8 @@ typedef struct { *****************************************************************************/ #define XDcfg_SelectIcapInterface(InstancePtr) \ XDcfg_WriteReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET, \ - ((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET)) \ - & ( ~XDCFG_CTRL_PCAP_PR_MASK))) + ((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET)) \ + & ( ~XDCFG_CTRL_PCAP_PR_MASK))) /****************************************************************************/ /** @@ -288,8 +300,8 @@ typedef struct { *****************************************************************************/ #define XDcfg_SelectPcapInterface(InstancePtr) \ XDcfg_WriteReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET, \ - ((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET)) \ - | XDCFG_CTRL_PCAP_PR_MASK)) + ((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET)) \ + | XDCFG_CTRL_PCAP_PR_MASK)) @@ -298,7 +310,11 @@ typedef struct { /* * Lookup configuration in xdevcfg_sinit.c. */ +#ifndef SDT XDcfg_Config *XDcfg_LookupConfig(u16 DeviceId); +#else +XDcfg_Config *XDcfg_LookupConfig(UINTPTR BaseAddress); +#endif /* * Selftest function in xdevcfg_selftest.c @@ -309,7 +325,7 @@ int XDcfg_SelfTest(XDcfg *InstancePtr); * Interface functions in xdevcfg.c */ int XDcfg_CfgInitialize(XDcfg *InstancePtr, - XDcfg_Config *ConfigPtr, u32 EffectiveAddress); + XDcfg_Config *ConfigPtr, u32 EffectiveAddress); void XDcfg_EnablePCAP(XDcfg *InstancePtr); @@ -344,12 +360,12 @@ u32 XDcfg_GetMiscControlRegister(XDcfg *InstancePtr); u32 XDcfg_IsDmaBusy(XDcfg *InstancePtr); void XDcfg_InitiateDma(XDcfg *InstancePtr, u32 SourcePtr, u32 DestPtr, - u32 SrcWordLength, u32 DestWordLength); + u32 SrcWordLength, u32 DestWordLength); u32 XDcfg_Transfer(XDcfg *InstancePtr, - void *SourcePtr, u32 SrcWordLength, - void *DestPtr, u32 DestWordLength, - u32 TransferType); + void *SourcePtr, u32 SrcWordLength, + void *DestPtr, u32 DestWordLength, + u32 TransferType); /* * Interrupt related function prototypes implemented in xdevcfg_intr.c @@ -367,7 +383,7 @@ void XDcfg_IntrClear(XDcfg *InstancePtr, u32 Mask); void XDcfg_InterruptHandler(XDcfg *InstancePtr); void XDcfg_SetHandler(XDcfg *InstancePtr, void *CallBackFunc, - void *CallBackRef); + void *CallBackRef); #ifdef __cplusplus } diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/devcfg/src/xdevcfg_g.c b/bsp_z7/ps7_cortexa9_0/libsrc/devcfg/src/xdevcfg_g.c index 28d1efd..b779f05 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/devcfg/src/xdevcfg_g.c +++ b/bsp_z7/ps7_cortexa9_0/libsrc/devcfg/src/xdevcfg_g.c @@ -1,5 +1,6 @@ /****************************************************************************** -* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved. +* Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -7,7 +8,7 @@ /** * * @file xdevcfg_g.c -* @addtogroup devcfg_v3_7 +* @addtogroup devcfg Overview * @{ * * This file contains a table that specifies the configuration of the Device diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/devcfg/src/xdevcfg_hw.c b/bsp_z7/ps7_cortexa9_0/libsrc/devcfg/src/xdevcfg_hw.c index 1feacd9..a5efdec 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/devcfg/src/xdevcfg_hw.c +++ b/bsp_z7/ps7_cortexa9_0/libsrc/devcfg/src/xdevcfg_hw.c @@ -1,5 +1,6 @@ /****************************************************************************** -* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved. +* Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -7,7 +8,7 @@ /** * * @file xdevcfg_hw.c -* @addtogroup devcfg_v3_7 +* @addtogroup devcfg Overview * @{ * * This file contains the implementation of the interface reset functionality @@ -17,6 +18,7 @@ * Ver Who Date Changes * ----- --- -------- --------------------------------------------- * 2.04a kpc 10/07/13 First release +* 3.8 Nava 06/21/23 Added support for system device-tree flow. * * ******************************************************************************/ @@ -59,7 +61,7 @@ void XDcfg_ResetHw(u32 BaseAddr) /* Mask the interrupts */ XDcfg_WriteReg(BaseAddr, XDCFG_INT_MASK_OFFSET, - XDCFG_IXR_ALL_MASK); + XDCFG_IXR_ALL_MASK); /* Clear the interuupt status */ Regval = XDcfg_ReadReg(BaseAddr, XDCFG_INT_STS_OFFSET); XDcfg_WriteReg(BaseAddr, XDCFG_INT_STS_OFFSET, Regval); @@ -77,7 +79,7 @@ void XDcfg_ResetHw(u32 BaseAddr) XDcfg_WriteReg(BaseAddr, XDCFG_MCTRL_OFFSET, Regval); /*Reset the configuration register to reset value */ XDcfg_WriteReg(BaseAddr, XDCFG_CFG_OFFSET, - XDCFG_CONFIG_RESET_VALUE); + XDCFG_CONFIG_RESET_VALUE); /*Disable the PCAP rate enable bit */ Regval = XDcfg_ReadReg(BaseAddr, XDCFG_CTRL_OFFSET); Regval = Regval & ~XDCFG_CTRL_PCAP_RATE_EN_MASK; diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/devcfg/src/xdevcfg_hw.h b/bsp_z7/ps7_cortexa9_0/libsrc/devcfg/src/xdevcfg_hw.h index 1b7d881..3db7835 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/devcfg/src/xdevcfg_hw.h +++ b/bsp_z7/ps7_cortexa9_0/libsrc/devcfg/src/xdevcfg_hw.h @@ -1,5 +1,6 @@ /****************************************************************************** -* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved. +* Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -7,7 +8,7 @@ /** * * @file xdevcfg_hw.h -* @addtogroup devcfg_v3_7 +* @addtogroup devcfg Overview * @{ * * This file contains the hardware interface to the Device Config Interface. @@ -26,6 +27,7 @@ * version UG585 (v1.4) November 16, 2012. * 2.04a kpc 10/07/13 Added function prototype. * 3.00a kpc 25/02/14 Corrected the XDCFG_BASE_ADDRESS macro value. +* 3.8 Nava 06/21/23 Added support for system device-tree flow. * * ******************************************************************************/ @@ -210,14 +212,14 @@ extern "C" { * of Init Signal */ #define XDCFG_IXR_ERROR_FLAGS_MASK (XDCFG_IXR_AXI_WTO_MASK | \ - XDCFG_IXR_AXI_WERR_MASK | \ - XDCFG_IXR_AXI_RTO_MASK | \ - XDCFG_IXR_AXI_RERR_MASK | \ - XDCFG_IXR_RX_FIFO_OV_MASK | \ - XDCFG_IXR_DMA_CMD_ERR_MASK |\ - XDCFG_IXR_DMA_Q_OV_MASK | \ - XDCFG_IXR_P2D_LEN_ERR_MASK |\ - XDCFG_IXR_PCFG_HMAC_ERR_MASK) + XDCFG_IXR_AXI_WERR_MASK | \ + XDCFG_IXR_AXI_RTO_MASK | \ + XDCFG_IXR_AXI_RERR_MASK | \ + XDCFG_IXR_RX_FIFO_OV_MASK | \ + XDCFG_IXR_DMA_CMD_ERR_MASK |\ + XDCFG_IXR_DMA_Q_OV_MASK | \ + XDCFG_IXR_P2D_LEN_ERR_MASK |\ + XDCFG_IXR_PCFG_HMAC_ERR_MASK) #define XDCFG_IXR_ALL_MASK 0x00F7F8EF @@ -266,9 +268,9 @@ extern "C" { * Status */ #define XDCFG_STATUS_EFUSE_BBRAM_KEY_DISABLE_MASK 0x00000008 - /**< BBRAM key - * disable - */ +/**< BBRAM key + * disable + */ #define XDCFG_STATUS_EFUSE_SEC_EN_MASK 0x00000004 /**< Efuse Security * Enable Status */ diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/devcfg/src/xdevcfg_intr.c b/bsp_z7/ps7_cortexa9_0/libsrc/devcfg/src/xdevcfg_intr.c index 9e7a741..77dd267 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/devcfg/src/xdevcfg_intr.c +++ b/bsp_z7/ps7_cortexa9_0/libsrc/devcfg/src/xdevcfg_intr.c @@ -1,5 +1,6 @@ /****************************************************************************** -* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved. +* Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -7,7 +8,7 @@ /** * * @file xdevcfg_intr.c -* @addtogroup devcfg_v3_7 +* @addtogroup devcfg Overview * @{ * * Contains the implementation of interrupt related functions of the XDcfg @@ -22,6 +23,7 @@ * 2.01a nm 07/07/12 Updated the XDcfg_IntrClear function to directly * set the mask instead of oring it with the * value read from the interrupt status register +* 3.8 Nava 06/21/23 Added support for system device-tree flow. * * ******************************************************************************/ @@ -70,11 +72,11 @@ void XDcfg_IntrEnable(XDcfg *InstancePtr, u32 Mask) * Enable the specified interrupts in the Interrupt Mask Register. */ RegValue = XDcfg_ReadReg(InstancePtr->Config.BaseAddr, - XDCFG_INT_MASK_OFFSET); + XDCFG_INT_MASK_OFFSET); RegValue &= ~(Mask & XDCFG_IXR_ALL_MASK); XDcfg_WriteReg(InstancePtr->Config.BaseAddr, - XDCFG_INT_MASK_OFFSET, - RegValue); + XDCFG_INT_MASK_OFFSET, + RegValue); } @@ -108,11 +110,11 @@ void XDcfg_IntrDisable(XDcfg *InstancePtr, u32 Mask) * Disable the specified interrupts in the Interrupt Mask Register. */ RegValue = XDcfg_ReadReg(InstancePtr->Config.BaseAddr, - XDCFG_INT_MASK_OFFSET); + XDCFG_INT_MASK_OFFSET); RegValue |= (Mask & XDCFG_IXR_ALL_MASK); XDcfg_WriteReg(InstancePtr->Config.BaseAddr, - XDCFG_INT_MASK_OFFSET, - RegValue); + XDCFG_INT_MASK_OFFSET, + RegValue); } /****************************************************************************/ /** @@ -170,7 +172,7 @@ u32 XDcfg_IntrGetStatus(XDcfg *InstancePtr) * Return the value read from the Interrupt Status register. */ return XDcfg_ReadReg(InstancePtr->Config.BaseAddr, - XDCFG_INT_STS_OFFSET); + XDCFG_INT_STS_OFFSET); } /****************************************************************************/ @@ -199,8 +201,8 @@ void XDcfg_IntrClear(XDcfg *InstancePtr, u32 Mask) Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); XDcfg_WriteReg(InstancePtr->Config.BaseAddr, - XDCFG_INT_STS_OFFSET, - Mask); + XDCFG_INT_STS_OFFSET, + Mask); } @@ -232,7 +234,7 @@ void XDcfg_InterruptHandler(XDcfg *InstancePtr) * Read the Interrupt status register. */ IntrStatusReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr, - XDCFG_INT_STS_OFFSET); + XDCFG_INT_STS_OFFSET); /* * Write the status back to clear the interrupts so that no @@ -240,13 +242,13 @@ void XDcfg_InterruptHandler(XDcfg *InstancePtr) * This also does the DMA acknowledgment automatically. */ XDcfg_WriteReg(InstancePtr->Config.BaseAddr, - XDCFG_INT_STS_OFFSET, IntrStatusReg); + XDCFG_INT_STS_OFFSET, IntrStatusReg); /* * Signal application that there are events to handle. */ InstancePtr->StatusHandler(InstancePtr->CallBackRef, - IntrStatusReg); + IntrStatusReg); } @@ -268,7 +270,7 @@ void XDcfg_InterruptHandler(XDcfg *InstancePtr) * *****************************************************************************/ void XDcfg_SetHandler(XDcfg *InstancePtr, void *CallBackFunc, - void *CallBackRef) + void *CallBackRef) { /* * Asserts validate the input arguments diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/devcfg/src/xdevcfg_selftest.c b/bsp_z7/ps7_cortexa9_0/libsrc/devcfg/src/xdevcfg_selftest.c index f1fa391..6392cef 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/devcfg/src/xdevcfg_selftest.c +++ b/bsp_z7/ps7_cortexa9_0/libsrc/devcfg/src/xdevcfg_selftest.c @@ -1,5 +1,6 @@ /****************************************************************************** -* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved. +* Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -7,7 +8,7 @@ /** * * @file xdevcfg_selftest.c -* @addtogroup devcfg_v3_7 +* @addtogroup devcfg Overview * @{ * * Contains diagnostic self-test functions for the XDcfg driver. diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/devcfg/src/xdevcfg_sinit.c b/bsp_z7/ps7_cortexa9_0/libsrc/devcfg/src/xdevcfg_sinit.c index b42d32b..4bd6def 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/devcfg/src/xdevcfg_sinit.c +++ b/bsp_z7/ps7_cortexa9_0/libsrc/devcfg/src/xdevcfg_sinit.c @@ -1,5 +1,6 @@ /****************************************************************************** -* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved. +* Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -7,7 +8,7 @@ /** * * @file xdevcfg_sinit.c -* @addtogroup devcfg_v3_7 +* @addtogroup devcfg Overview * @{ * * This file contains method for static initialization (compile-time) of the @@ -20,6 +21,7 @@ * ----- --- -------- --------------------------------------------- * 1.00a hvm 02/07/11 First release * 3.5 ms 08/07/17 Fixed compilation warnings. +* 3.8 Nava 06/21/23 Added support for system device-tree flow. * * ******************************************************************************/ @@ -27,7 +29,9 @@ /***************************** Include Files *********************************/ #include "xdevcfg.h" +#ifndef SDT #include "xparameters.h" +#endif /************************** Constant Definitions *****************************/ @@ -50,6 +54,7 @@ * @note None. * ******************************************************************************/ +#ifndef SDT XDcfg_Config *XDcfg_LookupConfig(u16 DeviceId) { extern XDcfg_Config XDcfg_ConfigTable[]; @@ -65,4 +70,22 @@ XDcfg_Config *XDcfg_LookupConfig(u16 DeviceId) return (CfgPtr); } +#else +XDcfg_Config *XDcfg_LookupConfig(UINTPTR BaseAddress) +{ + extern XDcfg_Config XDcfg_ConfigTable[]; + XDcfg_Config *CfgPtr = NULL; + u32 Index; + + for (Index = (u32)0x0; XDcfg_ConfigTable[Index].Name != NULL; Index++) { + if ((XDcfg_ConfigTable[Index].BaseAddr == BaseAddress) || + !BaseAddress) { + CfgPtr = &XDcfg_ConfigTable[Index]; + break; + } + } + + return (CfgPtr); +} +#endif /** @} */ diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/dmaps/src/xdmaps.c b/bsp_z7/ps7_cortexa9_0/libsrc/dmaps/src/xdmaps.c index 27dffb9..33e4fa3 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/dmaps/src/xdmaps.c +++ b/bsp_z7/ps7_cortexa9_0/libsrc/dmaps/src/xdmaps.c @@ -1,5 +1,6 @@ /****************************************************************************** -* Copyright (C) 2009 - 2021 Xilinx, Inc. All rights reserved. +* Copyright (C) 2009 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -7,7 +8,7 @@ /** * * @file xdmaps.c -* @addtogroup dmaps_v2_8 +* @addtogroup dmaps Overview * @{ * * This file contains the implementation of the interface functions for XDmaPs @@ -46,6 +47,7 @@ * 2.3 kpc 14/10/16 Fixed the compiler error when optimization O0 is used. * 2.5 hk 08/16/19 Add a memory barrier before DMASEV as per specification. * 2.6 hk 02/14/20 Correct boundary check for Channel. +* 2.7 aj 12/07/23 Fixed changes to support system device tree flow * * * @@ -78,8 +80,8 @@ /************************** Function Prototypes *****************************/ static int XDmaPs_Exec_DMAKILL(u32 BaseAddr, - unsigned int Channel, - unsigned int Thread); + unsigned int Channel, + unsigned int Thread); static void XDmaPs_BufPool_Free(XDmaPs_ProgBuf *Pool, void *Buf); @@ -88,7 +90,7 @@ static int XDmaPs_Exec_DMAGO(u32 BaseAddr, unsigned int Channel, u32 DmaProg); static void XDmaPs_DoneISR_n(XDmaPs *InstPtr, unsigned Channel); static void *XDmaPs_BufPool_Allocate(XDmaPs_ProgBuf *Pool); static int XDmaPs_BuildDmaProg(unsigned Channel, XDmaPs_Cmd *Cmd, - unsigned CacheLength); + unsigned CacheLength); static void XDmaPs_Print_DmaProgBuf(char *Buf, int Length); @@ -125,8 +127,8 @@ static void XDmaPs_Print_DmaProgBuf(char *Buf, int Length); * *****************************************************************************/ int XDmaPs_CfgInitialize(XDmaPs *InstPtr, - XDmaPs_Config *Config, - u32 EffectiveAddr) + XDmaPs_Config *Config, + u32 EffectiveAddr) { int Status = XST_SUCCESS; unsigned int CacheLength = 0; @@ -143,15 +145,26 @@ int XDmaPs_CfgInitialize(XDmaPs *InstPtr, /* * Setup the driver instance using passed in parameters */ +#ifndef SDT InstPtr->Config.DeviceId = Config->DeviceId; +#endif InstPtr->Config.BaseAddress = EffectiveAddr; +#ifdef SDT + InstPtr->Config.IntrParent = Config->IntrParent; + /* Added one fault Inerrupt and eight per-channel Interrupt */ + for (Channel = 0; Channel < (XDMAPS_CHANNELS_PER_DEV + 1); Channel++) { + InstPtr->Config.IntrId[Channel] = Config->IntrId[Channel]; + } +#endif + CfgReg = XDmaPs_ReadReg(EffectiveAddr, XDMAPS_CR1_OFFSET); CacheLength = CfgReg & XDMAPS_CR1_I_CACHE_LEN_MASK; - if (CacheLength < 2 || CacheLength > 5) + if (CacheLength < 2 || CacheLength > 5) { CacheLength = 0; - else + } else { CacheLength = 1 << CacheLength; + } InstPtr->CacheLength = CacheLength; @@ -161,7 +174,11 @@ int XDmaPs_CfgInitialize(XDmaPs *InstPtr, for (Channel = 0; Channel < XDMAPS_CHANNELS_PER_DEV; Channel++) { ChanData = InstPtr->Chans + Channel; ChanData->ChanId = Channel; +#ifndef SDT ChanData->DevId = Config->DeviceId; +#else + ChanData->DevId = XDmaPs_GetDrvIndex(InstPtr, EffectiveAddr); +#endif } InstPtr->IsReady = 1; @@ -185,7 +202,7 @@ int XDmaPs_ResetManager(XDmaPs *InstPtr) { int Status; Status = XDmaPs_Exec_DMAKILL(InstPtr->Config.BaseAddress, - 0, 0); + 0, 0); return Status; } @@ -207,7 +224,7 @@ int XDmaPs_ResetChannel(XDmaPs *InstPtr, unsigned int Channel) { int Status; Status = XDmaPs_Exec_DMAKILL(InstPtr->Config.BaseAddress, - Channel, 1); + Channel, 1); return Status; @@ -247,8 +264,11 @@ void XDmaPs_FaultISR(XDmaPs *InstPtr) Fsm = XDmaPs_ReadReg(BaseAddr, XDMAPS_FSM_OFFSET) & 0x01; Fsc = XDmaPs_ReadReg(BaseAddr, XDMAPS_FSC_OFFSET) & 0xFF; - +#ifndef SDT DevId = InstPtr->Config.DeviceId; +#else + DevId = XDmaPs_GetDrvIndex(InstPtr, BaseAddr); +#endif if (Fsm) { /* @@ -275,9 +295,9 @@ void XDmaPs_FaultISR(XDmaPs *InstPtr) if (Fsc & (0x01 << Chan)) { FaultType = XDmaPs_ReadReg(BaseAddr, - XDmaPs_FTCn_OFFSET(Chan)); + XDmaPs_FTCn_OFFSET(Chan)); Pc = XDmaPs_ReadReg(BaseAddr, - XDmaPs_CPCn_OFFSET(Chan)); + XDmaPs_CPCn_OFFSET(Chan)); /* kill the channel thread */ /* Should we disable interrupt? */ @@ -302,7 +322,7 @@ void XDmaPs_FaultISR(XDmaPs *InstPtr) DmaProgBuf = (void *)DmaCmd->GeneratedDmaProg; if (DmaProgBuf) XDmaPs_BufPool_Free(ChanData->ProgBufPool, - DmaProgBuf); + DmaProgBuf); DmaCmd->GeneratedDmaProg = NULL; } @@ -332,16 +352,17 @@ void XDmaPs_FaultISR(XDmaPs *InstPtr) * ******************************************************************************/ int XDmaPs_SetDoneHandler(XDmaPs *InstPtr, - unsigned Channel, - XDmaPsDoneHandler DoneHandler, - void *CallbackRef) + unsigned Channel, + XDmaPsDoneHandler DoneHandler, + void *CallbackRef) { XDmaPs_ChannelData *ChanData; Xil_AssertNonvoid(InstPtr != NULL); - if (Channel >= XDMAPS_CHANNELS_PER_DEV) + if (Channel >= XDMAPS_CHANNELS_PER_DEV) { return XST_FAILURE; + } ChanData = InstPtr->Chans + Channel; @@ -367,8 +388,8 @@ int XDmaPs_SetDoneHandler(XDmaPs *InstPtr, * ******************************************************************************/ int XDmaPs_SetFaultHandler(XDmaPs *InstPtr, - XDmaPsFaultHandler FaultHandler, - void *CallbackRef) + XDmaPsFaultHandler FaultHandler, + void *CallbackRef) { Xil_AssertNonvoid(InstPtr != NULL); @@ -437,7 +458,7 @@ static INLINE void XDmaPs_Memcpy4(char *Dst, char *Src) * *****************************************************************************/ static INLINE int XDmaPs_Instr_DMAGO(char *DmaProg, unsigned int Cn, - u32 Imm, unsigned int Ns) + u32 Imm, unsigned int Ns) { /* * DMAGO encoding: @@ -504,7 +525,7 @@ static INLINE int XDmaPs_Instr_DMALD(char *DmaProg) * *****************************************************************************/ static INLINE int XDmaPs_Instr_DMALP(char *DmaProg, unsigned Lc, - unsigned LoopIterations) + unsigned LoopIterations) { /* * DMALP encoding @@ -742,19 +763,19 @@ int XDmaPs_Instr_DMAWMB(char *DmaProg) static INLINE unsigned XDmaPs_ToEndianSwapSizeBits(unsigned int EndianSwapSize) { switch (EndianSwapSize) { - case 0: - case 8: - return 0; - case 16: - return 1; - case 32: - return 2; - case 64: - return 3; - case 128: - return 4; - default: - return 0; + case 0: + case 8: + return 0; + case 16: + return 1; + case 32: + return 2; + case 64: + return 3; + case 128: + return 4; + default: + return 0; } } @@ -775,24 +796,24 @@ static INLINE unsigned XDmaPs_ToEndianSwapSizeBits(unsigned int EndianSwapSize) static INLINE unsigned XDmaPs_ToBurstSizeBits(unsigned BurstSize) { switch (BurstSize) { - case 1: - return 0; - case 2: - return 1; - case 4: - return 2; - case 8: - return 3; - case 16: - return 4; - case 32: - return 5; - case 64: - return 6; - case 128: - return 7; - default: - return 0; + case 1: + return 0; + case 2: + return 1; + case 4: + return 2; + case 8: + return 3; + case 16: + return 4; + case 32: + return 5; + case 64: + return 6; + case 128: + return 7; + default: + return 0; } } @@ -835,7 +856,7 @@ u32 XDmaPs_ToCCRValue(XDmaPs_ChanCtrl *ChanCtrl) XDmaPs_ToBurstSizeBits(ChanCtrl->DstBurstSize); unsigned dst_burst_len = (ChanCtrl->DstBurstLen - 1) & 0x0F; unsigned dst_cache_ctrl = (ChanCtrl->DstCacheCtrl & 0x03) - | ((ChanCtrl->DstCacheCtrl & 0x08) >> 1); + | ((ChanCtrl->DstCacheCtrl & 0x08) >> 1); unsigned dst_prot_ctrl = ChanCtrl->DstProtCtrl & 0x07; unsigned dst_inc_bit = ChanCtrl->DstInc & 1; @@ -843,21 +864,21 @@ u32 XDmaPs_ToCCRValue(XDmaPs_ChanCtrl *ChanCtrl) XDmaPs_ToBurstSizeBits(ChanCtrl->SrcBurstSize); unsigned src_burst_len = (ChanCtrl->SrcBurstLen - 1) & 0x0F; unsigned src_cache_ctrl = (ChanCtrl->SrcCacheCtrl & 0x03) - | ((ChanCtrl->SrcCacheCtrl & 0x08) >> 1); + | ((ChanCtrl->SrcCacheCtrl & 0x08) >> 1); unsigned src_prot_ctrl = ChanCtrl->SrcProtCtrl & 0x07; unsigned src_inc_bit = ChanCtrl->SrcInc & 1; u32 ccr_value = (es << 28) - | (dst_cache_ctrl << 25) - | (dst_prot_ctrl << 22) - | (dst_burst_len << 18) - | (dst_burst_size << 15) - | (dst_inc_bit << 14) - | (src_cache_ctrl << 11) - | (src_prot_ctrl << 8) - | (src_burst_len << 4) - | (src_burst_size << 1) - | (src_inc_bit); + | (dst_cache_ctrl << 25) + | (dst_prot_ctrl << 22) + | (dst_burst_len << 18) + | (dst_burst_size << 15) + | (dst_inc_bit << 14) + | (src_cache_ctrl << 11) + | (src_prot_ctrl << 8) + | (src_burst_len << 4) + | (src_burst_size << 1) + | (src_inc_bit); return ccr_value; } @@ -883,9 +904,9 @@ u32 XDmaPs_ToCCRValue(XDmaPs_ChanCtrl *ChanCtrl) * *****************************************************************************/ int XDmaPs_ConstructSingleLoop(char *DmaProgStart, - int CacheLength, - char *DmaProgLoopStart, - int LoopCount) + int CacheLength, + char *DmaProgLoopStart, + int LoopCount) { int CacheStartOffset; int CacheEndOffset; @@ -909,7 +930,7 @@ int XDmaPs_ConstructSingleLoop(char *DmaProgStart, != CacheEndOffset / CacheLength) { /* insert the nops */ NumNops = CacheLength - - CacheStartOffset % CacheLength; + - CacheStartOffset % CacheLength; while (NumNops--) { DmaProgBuf += XDmaPs_Instr_DMANOP(DmaProgBuf); @@ -920,7 +941,7 @@ int XDmaPs_ConstructSingleLoop(char *DmaProgStart, DmaProgBuf += XDmaPs_Instr_DMALD(DmaProgBuf); DmaProgBuf += XDmaPs_Instr_DMAST(DmaProgBuf); DmaProgBuf += XDmaPs_Instr_DMALPEND(DmaProgBuf, - DmaProgBuf - 2, 0); + DmaProgBuf - 2, 0); return DmaProgBuf - DmaProgLoopStart; } @@ -948,10 +969,10 @@ int XDmaPs_ConstructSingleLoop(char *DmaProgStart, * *****************************************************************************/ int XDmaPs_ConstructNestedLoop(char *DmaProgStart, - int CacheLength, - char *DmaProgLoopStart, - unsigned int LoopCountOuter, - unsigned int LoopCountInner) + int CacheLength, + char *DmaProgLoopStart, + unsigned int LoopCountOuter, + unsigned int LoopCountInner) { int CacheStartOffset; int CacheEndOffset; @@ -974,14 +995,14 @@ int XDmaPs_ConstructNestedLoop(char *DmaProgStart, */ DmaProgBuf += XDmaPs_ConstructSingleLoop(DmaProgStart, - CacheLength, - DmaProgBuf, - LoopCountInner); + CacheLength, + DmaProgBuf, + LoopCountInner); /* outer loop end */ DmaProgBuf += XDmaPs_Instr_DMALPEND(DmaProgBuf, - InnerLoopStart, - 1); + InnerLoopStart, + 1); /* * the nested loop is constructed for @@ -1004,7 +1025,7 @@ int XDmaPs_ConstructNestedLoop(char *DmaProgStart, != CacheEndOffset / CacheLength) { /* insert the nops */ NumNops = CacheLength - - CacheStartOffset % CacheLength; + - CacheStartOffset % CacheLength; while (NumNops--) { DmaProgBuf += XDmaPs_Instr_DMANOP(DmaProgBuf); @@ -1021,10 +1042,10 @@ int XDmaPs_ConstructNestedLoop(char *DmaProgStart, /* inner DMALPEND */ DmaProgBuf += XDmaPs_Instr_DMALPEND(DmaProgBuf, - DmaProgBuf - 2, 0); + DmaProgBuf - 2, 0); /* outer DMALPEND */ DmaProgBuf += XDmaPs_Instr_DMALPEND(DmaProgBuf, - InnerLoopStart, 1); + InnerLoopStart, 1); /* return the number of bytes */ return DmaProgBuf - DmaProgLoopStart; @@ -1066,7 +1087,7 @@ int XDmaPs_ConstructNestedLoop(char *DmaProgStart, * *****************************************************************************/ static int XDmaPs_BuildDmaProg(unsigned Channel, XDmaPs_Cmd *Cmd, - unsigned CacheLength) + unsigned CacheLength) { /* * unpack arguments @@ -1118,18 +1139,20 @@ static int XDmaPs_BuildDmaProg(unsigned Channel, XDmaPs_Cmd *Cmd, /* insert DMAMOV for SAR and DAR */ DmaProgBuf += XDmaPs_Instr_DMAMOV(DmaProgBuf, - XDMAPS_MOV_SAR, - SrcAddr); + XDMAPS_MOV_SAR, + SrcAddr); DmaProgBuf += XDmaPs_Instr_DMAMOV(DmaProgBuf, - XDMAPS_MOV_DAR, - DstAddr); + XDMAPS_MOV_DAR, + DstAddr); - if (ChanCtrl->SrcInc) + if (ChanCtrl->SrcInc) { SrcUnaligned = SrcAddr % ChanCtrl->SrcBurstSize; + } - if (ChanCtrl->DstInc) + if (ChanCtrl->DstInc) { DstUnaligned = DstAddr % ChanCtrl->DstBurstSize; + } if ((SrcUnaligned && DstInc) || (DstUnaligned && SrcInc)) { ChanCtrl = &Mem2MemByteCC; @@ -1151,12 +1174,12 @@ static int XDmaPs_BuildDmaProg(unsigned Channel, XDmaPs_Cmd *Cmd, /* if head is unaligned, transfer head in bytes */ UnalignedCount = MemBurstSize - Unaligned; CCRValue = XDMAPS_CCR_SINGLE_BYTE - | (SrcInc & 1) - | ((DstInc & 1) << 14); + | (SrcInc & 1) + | ((DstInc & 1) << 14); DmaProgBuf += XDmaPs_Instr_DMAMOV(DmaProgBuf, - XDMAPS_MOV_CCR, - CCRValue); + XDMAPS_MOV_CCR, + CCRValue); for (Index = 0; Index < UnalignedCount; Index++) { DmaProgBuf += XDmaPs_Instr_DMALD(DmaProgBuf); @@ -1169,8 +1192,8 @@ static int XDmaPs_BuildDmaProg(unsigned Channel, XDmaPs_Cmd *Cmd, /* now the burst transfer part */ CCRValue = XDmaPs_ToCCRValue(ChanCtrl); DmaProgBuf += XDmaPs_Instr_DMAMOV(DmaProgBuf, - XDMAPS_MOV_CCR, - CCRValue); + XDMAPS_MOV_CCR, + CCRValue); BurstBytes = ChanCtrl->SrcBurstSize * ChanCtrl->SrcBurstLen; @@ -1196,16 +1219,16 @@ static int XDmaPs_BuildDmaProg(unsigned Channel, XDmaPs_Cmd *Cmd, if (LoopCount1 > 1) DmaProgBuf += XDmaPs_ConstructNestedLoop(DmaProgStart, - CacheLength, - DmaProgBuf, - LoopCount1, - 256); + CacheLength, + DmaProgBuf, + LoopCount1, + 256); else DmaProgBuf += XDmaPs_ConstructSingleLoop(DmaProgStart, - CacheLength, - DmaProgBuf, - 256); + CacheLength, + DmaProgBuf, + 256); /* there will be some that cannot be covered by * nested loops @@ -1215,9 +1238,9 @@ static int XDmaPs_BuildDmaProg(unsigned Channel, XDmaPs_Cmd *Cmd, if (LoopCount > 0) { DmaProgBuf += XDmaPs_ConstructSingleLoop(DmaProgStart, - CacheLength, - DmaProgBuf, - LoopCount); + CacheLength, + DmaProgBuf, + LoopCount); } if (TailBytes) { @@ -1244,13 +1267,13 @@ static int XDmaPs_BuildDmaProg(unsigned Channel, XDmaPs_Cmd *Cmd, DmaProgBuf += XDmaPs_Instr_DMAMOV(DmaProgBuf, - XDMAPS_MOV_CCR, - CCRValue); + XDMAPS_MOV_CCR, + CCRValue); DmaProgBuf += XDmaPs_ConstructSingleLoop(DmaProgStart, - CacheLength, - DmaProgBuf, - TailWords); + CacheLength, + DmaProgBuf, + TailWords); } @@ -1264,19 +1287,19 @@ static int XDmaPs_BuildDmaProg(unsigned Channel, XDmaPs_Cmd *Cmd, * to perform a burst. */ CCRValue = XDMAPS_CCR_SINGLE_BYTE - | (SrcInc & 1) - | ((DstInc & 1) << 14); + | (SrcInc & 1) + | ((DstInc & 1) << 14); DmaProgBuf += XDmaPs_Instr_DMAMOV(DmaProgBuf, - XDMAPS_MOV_CCR, - CCRValue); + XDMAPS_MOV_CCR, + CCRValue); DmaProgBuf += XDmaPs_ConstructSingleLoop(DmaProgStart, - CacheLength, - DmaProgBuf, - TailBytes); + CacheLength, + DmaProgBuf, + TailBytes); } } @@ -1322,8 +1345,9 @@ int XDmaPs_GenDmaProg(XDmaPs *InstPtr, unsigned int Channel, XDmaPs_Cmd *Cmd) Xil_AssertNonvoid(Cmd != NULL); - if (Channel > XDMAPS_CHANNELS_PER_DEV) + if (Channel > XDMAPS_CHANNELS_PER_DEV) { return XST_FAILURE; + } ChanData = InstPtr->Chans + Channel; ChanCtrl = &Cmd->ChanCtrl; @@ -1352,7 +1376,7 @@ int XDmaPs_GenDmaProg(XDmaPs *InstPtr, unsigned int Channel, XDmaPs_Cmd *Cmd) Cmd->GeneratedDmaProg = Buf; ProgLen = XDmaPs_BuildDmaProg(Channel, Cmd, - InstPtr->CacheLength); + InstPtr->CacheLength); Cmd->GeneratedDmaProgLength = ProgLen; @@ -1396,8 +1420,9 @@ int XDmaPs_FreeDmaProg(XDmaPs *InstPtr, unsigned int Channel, XDmaPs_Cmd *Cmd) Xil_AssertNonvoid(InstPtr != NULL); Xil_AssertNonvoid(Cmd != NULL); - if (Channel > XDMAPS_CHANNELS_PER_DEV) + if (Channel > XDMAPS_CHANNELS_PER_DEV) { return XST_FAILURE; + } Buf = (void *)Cmd->GeneratedDmaProg; ChanData = InstPtr->Chans + Channel; @@ -1437,8 +1462,8 @@ int XDmaPs_FreeDmaProg(XDmaPs *InstPtr, unsigned int Channel, XDmaPs_Cmd *Cmd) * ****************************************************************************/ int XDmaPs_Start(XDmaPs *InstPtr, unsigned int Channel, - XDmaPs_Cmd *Cmd, - int HoldDmaProg) + XDmaPs_Cmd *Cmd, + int HoldDmaProg) { int Status; u32 DmaProg = 0; @@ -1450,32 +1475,35 @@ int XDmaPs_Start(XDmaPs *InstPtr, unsigned int Channel, Cmd->DmaStatus = XST_FAILURE; - if (XDmaPs_IsActive(InstPtr, Channel)) + if (XDmaPs_IsActive(InstPtr, Channel)) { return XST_DEVICE_BUSY; + } if (!Cmd->UserDmaProg && !Cmd->GeneratedDmaProg) { Status = XDmaPs_GenDmaProg(InstPtr, Channel, Cmd); - if (Status) + if (Status) { return XST_FAILURE; + } } InstPtr->Chans[Channel].HoldDmaProg = HoldDmaProg; - if (Cmd->UserDmaProg) + if (Cmd->UserDmaProg) { DmaProg = (u32)Cmd->UserDmaProg; - else if (Cmd->GeneratedDmaProg) + } else if (Cmd->GeneratedDmaProg) { DmaProg = (u32)Cmd->GeneratedDmaProg; + } if (DmaProg) { /* enable the interrupt */ Inten = XDmaPs_ReadReg(InstPtr->Config.BaseAddress, - XDMAPS_INTEN_OFFSET); + XDMAPS_INTEN_OFFSET); Inten |= 0x01 << Channel; /* set the correpsonding bit */ XDmaPs_WriteReg(InstPtr->Config.BaseAddress, - XDMAPS_INTEN_OFFSET, - Inten); + XDMAPS_INTEN_OFFSET, + Inten); Inten = XDmaPs_ReadReg(InstPtr->Config.BaseAddress, - XDMAPS_INTEN_OFFSET); + XDMAPS_INTEN_OFFSET); InstPtr->Chans[Channel].DmaCmdToHw = Cmd; @@ -1484,13 +1512,12 @@ int XDmaPs_Start(XDmaPs *InstPtr, unsigned int Channel, } if (Cmd->ChanCtrl.DstInc) { Xil_DCacheInvalidateRange(Cmd->BD.DstAddr, - Cmd->BD.Length); + Cmd->BD.Length); } Status = XDmaPs_Exec_DMAGO(InstPtr->Config.BaseAddress, - Channel, DmaProg); - } - else { + Channel, DmaProg); + } else { InstPtr->Chans[Channel].DmaCmdToHw = NULL; Status = XST_FAILURE; } @@ -1517,8 +1544,9 @@ int XDmaPs_IsActive(XDmaPs *InstPtr, unsigned int Channel) Xil_AssertNonvoid(InstPtr != NULL); /* Need to assert Channel is in range */ - if (Channel >= XDMAPS_CHANNELS_PER_DEV) + if (Channel >= XDMAPS_CHANNELS_PER_DEV) { return XST_FAILURE; + } return InstPtr->Chans[Channel].DmaCmdToHw != NULL; } @@ -1725,8 +1753,8 @@ void XDmaPs_DoneISR_7(XDmaPs *InstPtr) * *****************************************************************************/ static int XDmaPs_Exec_DMAKILL(u32 BaseAddr, - unsigned int Channel, - unsigned int Thread) + unsigned int Channel, + unsigned int Thread) { u32 DbgInst0; int WaitCount; @@ -1736,14 +1764,15 @@ static int XDmaPs_Exec_DMAKILL(u32 BaseAddr, /* wait while debug status is busy */ WaitCount = 0; while ((XDmaPs_ReadReg(BaseAddr, XDMAPS_DBGSTATUS_OFFSET) - & XDMAPS_DBGSTATUS_BUSY) - && (WaitCount < XDMAPS_MAX_WAIT)) + & XDMAPS_DBGSTATUS_BUSY) + && (WaitCount < XDMAPS_MAX_WAIT)) { WaitCount++; + } if (WaitCount >= XDMAPS_MAX_WAIT) { /* wait time out */ xil_printf("PL330 device at %x debug status busy time out\n", - BaseAddr); + BaseAddr); return -1; } @@ -1816,7 +1845,7 @@ static int XDmaPs_Exec_DMAGO(u32 BaseAddr, unsigned int Channel, u32 DmaProg) /* wait while debug status is busy */ WaitCount = 0; while ((XDmaPs_ReadReg(BaseAddr, XDMAPS_DBGSTATUS_OFFSET) - & XDMAPS_DBGSTATUS_BUSY) + & XDMAPS_DBGSTATUS_BUSY) && (WaitCount < XDMAPS_MAX_WAIT)) { WaitCount++; @@ -1837,7 +1866,7 @@ static int XDmaPs_Exec_DMAGO(u32 BaseAddr, unsigned int Channel, u32 DmaProg) /* wait while the DMA Manager is busy */ WaitCount = 0; while ((XDmaPs_ReadReg(BaseAddr, - XDMAPS_DS_OFFSET) & XDMAPS_DS_DMA_STATUS) + XDMAPS_DS_OFFSET) & XDMAPS_DS_DMA_STATUS) != XDMAPS_DS_DMA_STATUS_STOPPED && WaitCount <= XDMAPS_MAX_WAIT) { WaitCount++; @@ -1896,7 +1925,7 @@ static void XDmaPs_DoneISR_n(XDmaPs *InstPtr, unsigned Channel) DmaProgBuf = (void *)DmaCmd->GeneratedDmaProg; if (DmaProgBuf) XDmaPs_BufPool_Free(ChanData->ProgBufPool, - DmaProgBuf); + DmaProgBuf); DmaCmd->GeneratedDmaProg = NULL; } @@ -1925,8 +1954,9 @@ static void XDmaPs_DoneISR_n(XDmaPs *InstPtr, unsigned Channel) static void XDmaPs_Print_DmaProgBuf(char *Buf, int Length) { int Index; - for (Index = 0; Index < Length; Index++) + for (Index = 0; Index < Length; Index++) { xil_printf("[%x] %x\r\n", Index, Buf[Index]); + } } /****************************************************************************/ @@ -1940,20 +1970,20 @@ static void XDmaPs_Print_DmaProgBuf(char *Buf, int Length) * @note None. * *****************************************************************************/ - void XDmaPs_Print_DmaProg(XDmaPs_Cmd *Cmd) +void XDmaPs_Print_DmaProg(XDmaPs_Cmd *Cmd) { if (Cmd->GeneratedDmaProg && Cmd->GeneratedDmaProgLength) { xil_printf("Generated DMA program (%d):\r\n", Cmd->GeneratedDmaProgLength); XDmaPs_Print_DmaProgBuf((char *)Cmd->GeneratedDmaProg, - Cmd->GeneratedDmaProgLength); + Cmd->GeneratedDmaProgLength); } if (Cmd->UserDmaProg && Cmd->UserDmaProgLength) { xil_printf("User defined DMA program (%d):\r\n", Cmd->UserDmaProgLength); XDmaPs_Print_DmaProgBuf((char *)Cmd->UserDmaProg, - Cmd->UserDmaProgLength); + Cmd->UserDmaProgLength); } } diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/dmaps/src/xdmaps.h b/bsp_z7/ps7_cortexa9_0/libsrc/dmaps/src/xdmaps.h index 179c840..4b98640 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/dmaps/src/xdmaps.h +++ b/bsp_z7/ps7_cortexa9_0/libsrc/dmaps/src/xdmaps.h @@ -1,5 +1,6 @@ /****************************************************************************** -* Copyright (C) 2009 - 2021 Xilinx, Inc. All rights reserved. +* Copyright (C) 2009 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -7,7 +8,7 @@ /** * * @file xdmaps.h -* @addtogroup dmaps_v2_8 +* @addtogroup dmaps Overview * @{ * @details * @@ -60,6 +61,7 @@ * 2.4 adk 13/08/18 Fixed armcc compiler warnings in the driver CR-1008310. * 2.8 sk 05/18/21 Modify all inline functions declarations from extern inline * to static inline to avoid the linkage conflict for IAR compiler. +* 2.9 aj 11/07/23 Added support for system device tree * * *****************************************************************************/ @@ -88,8 +90,19 @@ extern "C" { * This typedef contains configuration information for the device. */ typedef struct { +#ifndef SDT u16 DeviceId; /**< Unique ID of device */ +#else + char *Name; +#endif u32 BaseAddress; /**< Base address of device (IPIF) */ + +#ifdef SDT + u32 IntrId[9]; /** Bits[11:0] Interrupt-id Bits[15:12] + * trigger type and level flags */ + UINTPTR IntrParent; /** Bit[0] Interrupt parent type Bit[64/32:1] + * Parent base address */ +#endif } XDmaPs_Config; @@ -169,15 +182,15 @@ typedef struct { * It's the done handler a user can set for a channel */ typedef void (*XDmaPsDoneHandler) (unsigned int Channel, - XDmaPs_Cmd *DmaCmd, - void *CallbackRef); + XDmaPs_Cmd *DmaCmd, + void *CallbackRef); /** * It's the fault handler a user can set for a channel */ typedef void (*XDmaPsFaultHandler) (unsigned int Channel, - XDmaPs_Cmd *DmaCmd, - void *CallbackRef); + XDmaPs_Cmd *DmaCmd, + void *CallbackRef); #define XDMAPS_MAX_CHAN_BUFS 2 #define XDMAPS_CHAN_BUF_LEN 128 @@ -236,18 +249,18 @@ typedef struct { * Functions implemented in xdmaps.c */ int XDmaPs_CfgInitialize(XDmaPs *InstPtr, - XDmaPs_Config *Config, - u32 EffectiveAddr); + XDmaPs_Config *Config, + u32 EffectiveAddr); int XDmaPs_Start(XDmaPs *InstPtr, unsigned int Channel, - XDmaPs_Cmd *Cmd, - int HoldDmaProg); + XDmaPs_Cmd *Cmd, + int HoldDmaProg); int XDmaPs_IsActive(XDmaPs *InstPtr, unsigned int Channel); int XDmaPs_GenDmaProg(XDmaPs *InstPtr, unsigned int Channel, - XDmaPs_Cmd *Cmd); + XDmaPs_Cmd *Cmd); int XDmaPs_FreeDmaProg(XDmaPs *InstPtr, unsigned int Channel, - XDmaPs_Cmd *Cmd); + XDmaPs_Cmd *Cmd); void XDmaPs_Print_DmaProg(XDmaPs_Cmd *Cmd); @@ -256,13 +269,13 @@ int XDmaPs_ResetChannel(XDmaPs *InstPtr, unsigned int Channel); int XDmaPs_SetDoneHandler(XDmaPs *InstPtr, - unsigned Channel, - XDmaPsDoneHandler DoneHandler, - void *CallbackRef); + unsigned Channel, + XDmaPsDoneHandler DoneHandler, + void *CallbackRef); int XDmaPs_SetFaultHandler(XDmaPs *InstPtr, - XDmaPsFaultHandler FaultHandler, - void *CallbackRef); + XDmaPsFaultHandler FaultHandler, + void *CallbackRef); void XDmaPs_Print_DmaProg(XDmaPs_Cmd *Cmd); int XDmaPs_Instr_DMARMB(char *DmaProg); @@ -276,10 +289,10 @@ int XDmaPs_Instr_DMAWMB(char *DmaProg); static INLINE int XDmaPs_Instr_DMAEND(char *DmaProg); static INLINE void XDmaPs_Memcpy4(char *Dst, char *Src); static INLINE int XDmaPs_Instr_DMAGO(char *DmaProg, unsigned int Cn, - u32 Imm, unsigned int Ns); + u32 Imm, unsigned int Ns); static INLINE int XDmaPs_Instr_DMALD(char *DmaProg); static INLINE int XDmaPs_Instr_DMALP(char *DmaProg, unsigned Lc, - unsigned LoopIterations); + unsigned LoopIterations); static INLINE int XDmaPs_Instr_DMALPEND(char *DmaProg, char *BodyStart, unsigned Lc); static INLINE int XDmaPs_Instr_DMAMOV(char *DmaProg, unsigned Rd, u32 Imm); static INLINE int XDmaPs_Instr_DMANOP(char *DmaProg); @@ -312,7 +325,12 @@ void XDmaPs_FaultISR(XDmaPs *InstPtr); /* * Static loopup function implemented in xdmaps_sinit.c */ +#ifndef SDT XDmaPs_Config *XDmaPs_LookupConfig(u16 DeviceId); +#else +XDmaPs_Config *XDmaPs_LookupConfig(UINTPTR BaseAddress); +u32 XDmaPs_GetDrvIndex(XDmaPs *InstancePtr, UINTPTR BaseAddress); +#endif /* diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/dmaps/src/xdmaps_g.c b/bsp_z7/ps7_cortexa9_0/libsrc/dmaps/src/xdmaps_g.c index 30facf1..2a8cdeb 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/dmaps/src/xdmaps_g.c +++ b/bsp_z7/ps7_cortexa9_0/libsrc/dmaps/src/xdmaps_g.c @@ -1,5 +1,6 @@ /****************************************************************************** -* Copyright (C) 2009 - 2021 Xilinx, Inc. All rights reserved. +* Copyright (C) 2009 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -7,7 +8,7 @@ /** * * @file xdmaps_g.c -* @addtogroup dmaps_v2_8 +* @addtogroup dmaps Overview * @{ * * This file contains a configuration table where each entry is a configuration diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/dmaps/src/xdmaps_hw.c b/bsp_z7/ps7_cortexa9_0/libsrc/dmaps/src/xdmaps_hw.c index cb45d29..9a2d632 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/dmaps/src/xdmaps_hw.c +++ b/bsp_z7/ps7_cortexa9_0/libsrc/dmaps/src/xdmaps_hw.c @@ -1,5 +1,6 @@ /****************************************************************************** -* Copyright (C) 2009 - 2021 Xilinx, Inc. All rights reserved. +* Copyright (C) 2009 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -7,10 +8,10 @@ /** * * @file xdmaps_hw.c -* @addtogroup dmaps_v2_8 +* @addtogroup dmaps Overview * @{ * -* This file contains the implementation of the interface reset functionality +* This file contains the implementation of the interface reset functionality * for XDmaPs driver. * * 
@@ -40,10 +41,10 @@
 
 /*****************************************************************************/
 /**
-* This function perform the reset sequence to the given dmaps interface by 
+* This function perform the reset sequence to the given dmaps interface by
 * configuring the appropriate control bits in the dmaps specifc registers
 * the dmaps reset squence involves the following steps
-*	Disable all the interuupts 
+*	Disable all the interuupts
 *	Clear the pending interrupts
 *	Kill all the active channel threads
 *	Kill the manager thread
@@ -52,8 +53,8 @@
 *
 * @return N/A
 *
-* @note 
-* This function will not modify the slcr registers that are relavant for 
+* @note
+* This function will not modify the slcr registers that are relavant for
 * dmaps controller
 ******************************************************************************/
 void XDmaPs_ResetHw(u32 BaseAddress)
@@ -67,22 +68,23 @@ void XDmaPs_ResetHw(u32 BaseAddress)
 	/* Clear the interrupts */
 	XDmaPs_WriteReg(BaseAddress, XDMAPS_INTCLR_OFFSET, XDMAPS_INTCLR_ALL_MASK);
 	/* Kill the dma channel threads */
-	for (ChanIndex=0; ChanIndex < XDMAPS_CHANNELS_PER_DEV; ChanIndex++) {
+	for (ChanIndex = 0; ChanIndex < XDMAPS_CHANNELS_PER_DEV; ChanIndex++) {
 		while ((XDmaPs_ReadReg(BaseAddress, XDMAPS_DBGSTATUS_OFFSET)
-				& XDMAPS_DBGSTATUS_BUSY)
-				&& (WaitCount < XDMAPS_MAX_WAIT))
-				WaitCount++;
+			& XDMAPS_DBGSTATUS_BUSY)
+		       && (WaitCount < XDMAPS_MAX_WAIT)) {
+			WaitCount++;
+		}
 
-		DbgInst = XDmaPs_DBGINST0(0, 0x01, ChanIndex, 1);	
+		DbgInst = XDmaPs_DBGINST0(0, 0x01, ChanIndex, 1);
 		XDmaPs_WriteReg(BaseAddress, XDMAPS_DBGINST0_OFFSET, DbgInst);
-		XDmaPs_WriteReg(BaseAddress, XDMAPS_DBGINST1_OFFSET, 0x0);	
+		XDmaPs_WriteReg(BaseAddress, XDMAPS_DBGINST1_OFFSET, 0x0);
 		XDmaPs_WriteReg(BaseAddress, XDMAPS_DBGCMD_OFFSET, 0x0);
-	}	
+	}
 	/* Kill the manager thread	*/
-	DbgInst = XDmaPs_DBGINST0(0, 0x01, 0, 0);	
+	DbgInst = XDmaPs_DBGINST0(0, 0x01, 0, 0);
 	XDmaPs_WriteReg(BaseAddress, XDMAPS_DBGINST0_OFFSET, DbgInst);
-	XDmaPs_WriteReg(BaseAddress, XDMAPS_DBGINST1_OFFSET, 0x0);	
-	XDmaPs_WriteReg(BaseAddress, XDMAPS_DBGCMD_OFFSET, 0x0);	
+	XDmaPs_WriteReg(BaseAddress, XDMAPS_DBGINST1_OFFSET, 0x0);
+	XDmaPs_WriteReg(BaseAddress, XDMAPS_DBGCMD_OFFSET, 0x0);
 }
 
 
diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/dmaps/src/xdmaps_hw.h b/bsp_z7/ps7_cortexa9_0/libsrc/dmaps/src/xdmaps_hw.h
index d039278..32c2c91 100644
--- a/bsp_z7/ps7_cortexa9_0/libsrc/dmaps/src/xdmaps_hw.h
+++ b/bsp_z7/ps7_cortexa9_0/libsrc/dmaps/src/xdmaps_hw.h
@@ -1,5 +1,6 @@
 /******************************************************************************
-* Copyright (C) 2009 - 2021 Xilinx, Inc.  All rights reserved.
+* Copyright (C) 2009 - 2022 Xilinx, Inc.  All rights reserved.
+* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc.  All rights reserved.
 * SPDX-License-Identifier: MIT
 ******************************************************************************/
 
@@ -7,7 +8,7 @@
 /**
 *
 * @file xdmaps_hw.h
-* @addtogroup dmaps_v2_8
+* @addtogroup dmaps Overview
 * @{
 *
 * This header file contains the hardware interface of an XDmaPs device.
@@ -233,7 +234,7 @@ extern "C" {
 #define XDMAPS_INTCLR_ALL_MASK		0xFF
 
 #define XDmaPs_ReadReg(BaseAddress, RegOffset) \
-    Xil_In32((BaseAddress) + (RegOffset))
+	Xil_In32((BaseAddress) + (RegOffset))
 
 /***************************************************************************/
 /**
@@ -251,7 +252,7 @@ extern "C" {
 *                          u32 RegisterValue)
 ******************************************************************************/
 #define XDmaPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
-    Xil_Out32((BaseAddress) + (RegOffset), (RegisterValue))
+	Xil_Out32((BaseAddress) + (RegOffset), (RegisterValue))
 /************************** Variable Definitions *****************************/
 
 /************************** Function Prototypes *****************************/
diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/dmaps/src/xdmaps_selftest.c b/bsp_z7/ps7_cortexa9_0/libsrc/dmaps/src/xdmaps_selftest.c
index dd2d4d3..e0e9d92 100644
--- a/bsp_z7/ps7_cortexa9_0/libsrc/dmaps/src/xdmaps_selftest.c
+++ b/bsp_z7/ps7_cortexa9_0/libsrc/dmaps/src/xdmaps_selftest.c
@@ -1,5 +1,6 @@
 /******************************************************************************
-* Copyright (C) 2009 - 2021 Xilinx, Inc.  All rights reserved.
+* Copyright (C) 2009 - 2022 Xilinx, Inc.  All rights reserved.
+* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc.  All rights reserved.
 * SPDX-License-Identifier: MIT
 ******************************************************************************/
 
@@ -7,7 +8,7 @@
 /**
 *
 * @file xdmaps_selftest.c
-* @addtogroup dmaps_v2_8
+* @addtogroup dmaps Overview
 * @{
 *
 * This file contains the self-test functions for the XDmaPs driver.
@@ -71,13 +72,15 @@ int XDmaPs_SelfTest(XDmaPs *InstPtr)
 	int i;
 
 	if (XDmaPs_ReadReg(BaseAddr, XDMAPS_DBGSTATUS_OFFSET)
-	    & XDMAPS_DBGSTATUS_BUSY)
+	    & XDMAPS_DBGSTATUS_BUSY) {
 		return XST_FAILURE;
+	}
 
 	for (i = 0; i < XDMAPS_CHANNELS_PER_DEV; i++) {
 		if (XDmaPs_ReadReg(BaseAddr,
-				    XDmaPs_CSn_OFFSET(i)))
+				   XDmaPs_CSn_OFFSET(i))) {
 			return XST_FAILURE;
+		}
 	}
 	return XST_SUCCESS;
 }
diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/dmaps/src/xdmaps_sinit.c b/bsp_z7/ps7_cortexa9_0/libsrc/dmaps/src/xdmaps_sinit.c
index 751df21..d36215c 100644
--- a/bsp_z7/ps7_cortexa9_0/libsrc/dmaps/src/xdmaps_sinit.c
+++ b/bsp_z7/ps7_cortexa9_0/libsrc/dmaps/src/xdmaps_sinit.c
@@ -1,5 +1,6 @@
 /******************************************************************************
-* Copyright (C) 2009 - 2021 Xilinx, Inc.  All rights reserved.
+* Copyright (C) 2009 - 2022 Xilinx, Inc.  All rights reserved.
+* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc.  All rights reserved.
 * SPDX-License-Identifier: MIT
 ******************************************************************************/
 
@@ -7,10 +8,10 @@
 /**
 *
 * @file xdmaps_sinit.c
-* @addtogroup dmaps_v2_8
+* @addtogroup dmaps Overview
 * @{
 *
-* The implementation of the XDmaPs driver's static initialzation
+* The implementation of the XDmaPs driver's static initialization
 * functionality.
 *
 * 
@@ -26,7 +27,9 @@
 /***************************** Include Files ********************************/
 
 #include "xstatus.h"
+#ifndef SDT
 #include "xparameters.h"
+#endif
 #include "xdmaps.h"
 
 /************************** Constant Definitions ****************************/
@@ -60,6 +63,7 @@ extern XDmaPs_Config XDmaPs_ConfigTable[];
 * None.
 *
 ******************************************************************************/
+#ifndef SDT
 XDmaPs_Config *XDmaPs_LookupConfig(u16 DeviceId)
 {
 	XDmaPs_Config *CfgPtr = NULL;
@@ -75,4 +79,34 @@ XDmaPs_Config *XDmaPs_LookupConfig(u16 DeviceId)
 
 	return CfgPtr;
 }
+#else
+XDmaPs_Config *XDmaPs_LookupConfig(UINTPTR BaseAddress)
+{
+	XDmaPs_Config *CfgPtr = NULL;
+	int i;
+
+	for (i = (u32)0x0; XDmaPs_ConfigTable[i].Name != NULL; i++) {
+		if ((XDmaPs_ConfigTable[i].BaseAddress == BaseAddress) ||
+		    !BaseAddress) {
+			CfgPtr = &XDmaPs_ConfigTable[i];
+			break;
+		}
+	}
+
+	return CfgPtr;
+}
+
+u32 XDmaPs_GetDrvIndex(XDmaPs *InstancePtr, UINTPTR BaseAddress)
+{
+	u32 Index = 0;
+
+	for (Index = (u32)0x0; XDmaPs_ConfigTable[Index].Name != NULL; Index++) {
+		if ((XDmaPs_ConfigTable[Index].BaseAddress == BaseAddress)) {
+			break;
+		}
+	}
+
+	return Index;
+}
+#endif
 /** @} */
diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/emacps/src/xemacps.c b/bsp_z7/ps7_cortexa9_0/libsrc/emacps/src/xemacps.c
index 88a35cb..82ffae9 100644
--- a/bsp_z7/ps7_cortexa9_0/libsrc/emacps/src/xemacps.c
+++ b/bsp_z7/ps7_cortexa9_0/libsrc/emacps/src/xemacps.c
@@ -1,5 +1,6 @@
 /******************************************************************************
-* Copyright (C) 2010 - 2020 Xilinx, Inc.  All rights reserved.
+* Copyright (C) 2010 - 2022 Xilinx, Inc.  All rights reserved.
+* Copyright (C) 2022 - 2024 Advanced Micro Devices, Inc. All rights reserved.
 * SPDX-License-Identifier: MIT
 ******************************************************************************/
 
@@ -7,7 +8,7 @@
 /**
 *
 * @file xemacps.c
-* @addtogroup emacps_v3_16
+* @addtogroup emacps Overview
 * @{
 *
 * The XEmacPs driver. Functions in this file are the minimum required functions
@@ -85,12 +86,21 @@ LONG XEmacPs_CfgInitialize(XEmacPs *InstancePtr, XEmacPs_Config * CfgPtr,
 	Xil_AssertNonvoid(CfgPtr != NULL);
 
 	/* Set device base address and ID */
+#ifndef SDT
 	InstancePtr->Config.DeviceId = CfgPtr->DeviceId;
+#endif
 	InstancePtr->Config.BaseAddress = EffectiveAddress;
 	InstancePtr->Config.IsCacheCoherent = CfgPtr->IsCacheCoherent;
+#ifdef SDT
+	InstancePtr->Config.IntrId = CfgPtr->IntrId;
+	InstancePtr->Config.IntrParent = CfgPtr->IntrParent;
+#endif
 #if defined  (XCLOCKING)
 	InstancePtr->Config.RefClk = CfgPtr->RefClk;
 #endif
+#ifdef SDT
+	InstancePtr->Config.PhyType = CfgPtr->PhyType;
+#endif
 
 	InstancePtr->Config.S1GDiv0 = CfgPtr->S1GDiv0;
 	InstancePtr->Config.S1GDiv1 = CfgPtr->S1GDiv1;
diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/emacps/src/xemacps.h b/bsp_z7/ps7_cortexa9_0/libsrc/emacps/src/xemacps.h
index ac3e7a7..564d926 100644
--- a/bsp_z7/ps7_cortexa9_0/libsrc/emacps/src/xemacps.h
+++ b/bsp_z7/ps7_cortexa9_0/libsrc/emacps/src/xemacps.h
@@ -1,5 +1,6 @@
 /******************************************************************************
-* Copyright (C) 2010 - 2020 Xilinx, Inc.  All rights reserved.
+* Copyright (C) 2010 - 2022 Xilinx, Inc.  All rights reserved.
+* Copyright (C) 2022 - 2024 Advanced Micro Devices, Inc. All rights reserved.
 * SPDX-License-Identifier: MIT
 ******************************************************************************/
 
@@ -7,7 +8,7 @@
 /**
  *
  * @file xemacps.h
-* @addtogroup emacps_v3_16
+* @addtogroup emacps Overview
 * @{
 * @details
  *
@@ -417,15 +418,15 @@ extern "C" {
 #define XEMACPS_SGMII_ENABLE_OPTION	0x00008000U
 
 #define XEMACPS_DEFAULT_OPTIONS                     \
-    ((u32)XEMACPS_FLOW_CONTROL_OPTION |                  \
-     (u32)XEMACPS_FCS_INSERT_OPTION |                    \
-     (u32)XEMACPS_FCS_STRIP_OPTION |                     \
-     (u32)XEMACPS_BROADCAST_OPTION |                     \
-     (u32)XEMACPS_LENTYPE_ERR_OPTION |                   \
-     (u32)XEMACPS_TRANSMITTER_ENABLE_OPTION |            \
-     (u32)XEMACPS_RECEIVER_ENABLE_OPTION |               \
-     (u32)XEMACPS_RX_CHKSUM_ENABLE_OPTION |              \
-     (u32)XEMACPS_TX_CHKSUM_ENABLE_OPTION)
+	((u32)XEMACPS_FLOW_CONTROL_OPTION |                  \
+	 (u32)XEMACPS_FCS_INSERT_OPTION |                    \
+	 (u32)XEMACPS_FCS_STRIP_OPTION |                     \
+	 (u32)XEMACPS_BROADCAST_OPTION |                     \
+	 (u32)XEMACPS_LENTYPE_ERR_OPTION |                   \
+	 (u32)XEMACPS_TRANSMITTER_ENABLE_OPTION |            \
+	 (u32)XEMACPS_RECEIVER_ENABLE_OPTION |               \
+	 (u32)XEMACPS_RX_CHKSUM_ENABLE_OPTION |              \
+	 (u32)XEMACPS_TX_CHKSUM_ENABLE_OPTION)
 
 /**< Default options set when device is initialized or reset */
 /*@}*/
@@ -456,11 +457,11 @@ extern "C" {
 #define XEMACPS_HDR_VLAN_SIZE   18U	/* size of Ethernet header with VLAN */
 #define XEMACPS_TRL_SIZE        4U	/* size of Ethernet trailer (FCS) */
 #define XEMACPS_MAX_FRAME_SIZE       (XEMACPS_MTU + XEMACPS_HDR_SIZE + \
-        XEMACPS_TRL_SIZE)
+				      XEMACPS_TRL_SIZE)
 #define XEMACPS_MAX_VLAN_FRAME_SIZE  (XEMACPS_MTU + XEMACPS_HDR_SIZE + \
-        XEMACPS_HDR_VLAN_SIZE + XEMACPS_TRL_SIZE)
+				      XEMACPS_HDR_VLAN_SIZE + XEMACPS_TRL_SIZE)
 #define XEMACPS_MAX_VLAN_FRAME_SIZE_JUMBO  (XEMACPS_MTU_JUMBO + XEMACPS_HDR_SIZE + \
-        XEMACPS_HDR_VLAN_SIZE + XEMACPS_TRL_SIZE)
+		XEMACPS_HDR_VLAN_SIZE + XEMACPS_TRL_SIZE)
 
 /* DMACR Bust length hash defines */
 
@@ -500,7 +501,7 @@ typedef void (*XEmacPs_Handler) (void *CallBackRef);
  *
  */
 typedef void (*XEmacPs_ErrHandler) (void *CallBackRef, u8 Direction,
-				     u32 ErrorWord);
+				    u32 ErrorWord);
 
 /*@}*/
 
@@ -508,12 +509,25 @@ typedef void (*XEmacPs_ErrHandler) (void *CallBackRef, u8 Direction,
  * This typedef contains configuration information for a device.
  */
 typedef struct {
+#ifdef SDT
+	char *Name;     /**< Unique name of the device */
+#else
 	u16 DeviceId;	/**< Unique ID  of device */
+#endif
 	UINTPTR BaseAddress;/**< Physical base address of IPIF registers */
 	u8 IsCacheCoherent; /**< Applicable only to A53 in EL1 mode;
 				* describes whether Cache Coherent or not */
-#if defined  (XCLOCKING)
+#ifdef SDT
+	u16 IntrId;
+	UINTPTR IntrParent;
+#endif
+#if defined  (XCLOCKING) || defined (SDT)
 	u32 RefClk;	/**< Input clock */
+#endif
+#ifdef SDT
+	char *PhyType;     /**< PhyType indicates which type of PHY interface is
+			     *  used (MII, GMII, RGMII, etc.
+			     */
 #endif
 	u16 S1GDiv0;	/**< 1Gbps Clock Divider 0 */
 	u8 S1GDiv1;	/**< 1Gbps Clock Divider 1 */
@@ -606,8 +620,8 @@ typedef struct XEmacPs_Instance {
 *****************************************************************************/
 #define XEmacPs_IntEnable(InstancePtr, Mask)                            \
 	XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress,             \
-		XEMACPS_IER_OFFSET,                                     \
-		((Mask) & XEMACPS_IXR_ALL_MASK));
+			 XEMACPS_IER_OFFSET,                                     \
+			 ((Mask) & XEMACPS_IXR_ALL_MASK));
 
 /****************************************************************************/
 /**
@@ -627,8 +641,8 @@ typedef struct XEmacPs_Instance {
 *****************************************************************************/
 #define XEmacPs_IntDisable(InstancePtr, Mask)                           \
 	XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress,             \
-		XEMACPS_IDR_OFFSET,                                     \
-		((Mask) & XEMACPS_IXR_ALL_MASK));
+			 XEMACPS_IDR_OFFSET,                                     \
+			 ((Mask) & XEMACPS_IXR_ALL_MASK));
 
 /****************************************************************************/
 /**
@@ -648,8 +662,8 @@ typedef struct XEmacPs_Instance {
 *****************************************************************************/
 #define XEmacPs_IntQ1Enable(InstancePtr, Mask)                            \
 	XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress,             \
-		XEMACPS_INTQ1_IER_OFFSET,                                \
-		((Mask) & XEMACPS_INTQ1_IXR_ALL_MASK));
+			 XEMACPS_INTQ1_IER_OFFSET,                                \
+			 ((Mask) & XEMACPS_INTQ1_IXR_ALL_MASK));
 
 /****************************************************************************/
 /**
@@ -669,8 +683,8 @@ typedef struct XEmacPs_Instance {
 *****************************************************************************/
 #define XEmacPs_IntQ1Disable(InstancePtr, Mask)                           \
 	XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress,             \
-		XEMACPS_INTQ1_IDR_OFFSET,                               \
-		((Mask) & XEMACPS_INTQ1_IXR_ALL_MASK));
+			 XEMACPS_INTQ1_IDR_OFFSET,                               \
+			 ((Mask) & XEMACPS_INTQ1_IXR_ALL_MASK));
 
 /****************************************************************************/
 /**
@@ -687,10 +701,10 @@ typedef struct XEmacPs_Instance {
 *
 *****************************************************************************/
 #define XEmacPs_Transmit(InstancePtr)                              \
-        XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress,          \
-        XEMACPS_NWCTRL_OFFSET,                                     \
-        (XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress,          \
-        XEMACPS_NWCTRL_OFFSET) | XEMACPS_NWCTRL_STARTTX_MASK))
+	XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress,          \
+			 XEMACPS_NWCTRL_OFFSET,                                     \
+			 (XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress,          \
+					  XEMACPS_NWCTRL_OFFSET) | XEMACPS_NWCTRL_STARTTX_MASK))
 
 /****************************************************************************/
 /**
@@ -711,9 +725,9 @@ typedef struct XEmacPs_Instance {
 *
 *****************************************************************************/
 #define XEmacPs_IsRxCsum(InstancePtr)                                     \
-        ((XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress,             \
-          XEMACPS_NWCFG_OFFSET) & XEMACPS_NWCFG_RXCHKSUMEN_MASK) != 0U     \
-          ? TRUE : FALSE)
+	((XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress,             \
+			  XEMACPS_NWCFG_OFFSET) & XEMACPS_NWCFG_RXCHKSUMEN_MASK) != 0U     \
+	 ? TRUE : FALSE)
 
 /****************************************************************************/
 /**
@@ -734,9 +748,9 @@ typedef struct XEmacPs_Instance {
 *
 *****************************************************************************/
 #define XEmacPs_IsTxCsum(InstancePtr)                                     \
-        ((XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress,              \
-          XEMACPS_DMACR_OFFSET) & XEMACPS_DMACR_TCPCKSUM_MASK) != 0U       \
-          ? TRUE : FALSE)
+	((XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress,              \
+			  XEMACPS_DMACR_OFFSET) & XEMACPS_DMACR_TCPCKSUM_MASK) != 0U       \
+	 ? TRUE : FALSE)
 
 /************************** Function Prototypes *****************************/
 
@@ -761,10 +775,10 @@ typedef struct XEmacPs_Instance {
 *
 *****************************************************************************/
 #define XEmacPs_SetRXWatermark(InstancePtr, High, Low)                     \
-        XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress,                \
-        XEMACPS_RXWATERMARK_OFFSET,                                        \
-        (High & XEMACPS_RXWM_HIGH_MASK) |  \
-        ((Low << XEMACPS_RXWM_LOW_SHFT_MSK) & XEMACPS_RXWM_LOW_MASK) |)
+	XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress,                \
+			 XEMACPS_RXWATERMARK_OFFSET,                                        \
+			 (High & XEMACPS_RXWM_HIGH_MASK) |  \
+			 ((Low << XEMACPS_RXWM_LOW_SHFT_MSK) & XEMACPS_RXWM_LOW_MASK) |)
 
 /****************************************************************************/
 /**
@@ -781,8 +795,8 @@ typedef struct XEmacPs_Instance {
 *
 *****************************************************************************/
 #define XEmacPs_GetRXWatermark(InstancePtr)                     \
-        XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress,                \
-        XEMACPS_RXWATERMARK_OFFSET)
+	XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress,                \
+			XEMACPS_RXWATERMARK_OFFSET)
 /*
  * Initialization functions in xemacps.c
  */
@@ -797,7 +811,12 @@ void XEmacPs_SetQueuePtr(XEmacPs *InstancePtr, UINTPTR QPtr, u8 QueueNum,
 /*
  * Lookup configuration in xemacps_sinit.c
  */
+
+#ifndef SDT
 XEmacPs_Config *XEmacPs_LookupConfig(u16 DeviceId);
+#else
+XEmacPs_Config *XEmacPs_LookupConfig(UINTPTR BaseAddress);
+#endif
 
 /*
  * Interrupt-related functions in xemacps_intr.c
@@ -823,7 +842,7 @@ void XEmacPs_ClearHash(XEmacPs *InstancePtr);
 void XEmacPs_GetHash(XEmacPs *InstancePtr, void *AddressPtr);
 
 void XEmacPs_SetMdioDivisor(XEmacPs *InstancePtr,
-				XEmacPs_MdcDiv Divisor);
+			    XEmacPs_MdcDiv Divisor);
 void XEmacPs_SetOperatingSpeed(XEmacPs *InstancePtr, u16 Speed);
 u16 XEmacPs_GetOperatingSpeed(XEmacPs *InstancePtr);
 LONG XEmacPs_PhyRead(XEmacPs *InstancePtr, u32 PhyAddress,
diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/emacps/src/xemacps_bd.h b/bsp_z7/ps7_cortexa9_0/libsrc/emacps/src/xemacps_bd.h
index aff79ff..4641553 100644
--- a/bsp_z7/ps7_cortexa9_0/libsrc/emacps/src/xemacps_bd.h
+++ b/bsp_z7/ps7_cortexa9_0/libsrc/emacps/src/xemacps_bd.h
@@ -1,5 +1,6 @@
 /******************************************************************************
-* Copyright (C) 2010 - 2020 Xilinx, Inc.  All rights reserved.
+* Copyright (C) 2010 - 2022 Xilinx, Inc.  All rights reserved.
+* Copyright (C) 2022 - 2024 Advanced Micro Devices, Inc. All rights reserved.
 * SPDX-License-Identifier: MIT
 ******************************************************************************/
 
@@ -7,7 +8,7 @@
 /**
  *
  * @file xemacps_bd.h
-* @addtogroup emacps_v3_16
+* @addtogroup emacps Overview
 * @{
  *
  * This header provides operations to manage buffer descriptors in support
@@ -45,6 +46,7 @@
  * 3.2   hk   11/18/15 Change BD typedef and number of words.
  * 3.8   hk   08/18/18 Remove duplicate definition of XEmacPs_BdSetLength
  * 3.8   mus  11/05/18 Support 64 bit DMA addresses for Microblaze-X platform.
+ * 3.9   aj   22/03/24 Add mask for XEmaPs_BdGetBufAddr
  *
  * 

  *
@@ -239,11 +241,11 @@ typedef u32 XEmacPs_Bd[XEMACPS_BD_NUM_WORDS];
  *****************************************************************************/
 #if defined(__aarch64__) || defined(__arch64__)
 #define XEmacPs_BdGetBufAddr(BdPtr)                               \
-    (XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) |		  \
+    ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & XEMACPS_RXBUF_ADD_MASK) |		  \
 	(XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_HI_OFFSET)) << 32U)
 #else
 #define XEmacPs_BdGetBufAddr(BdPtr)                               \
-    (XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET))
+    (XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & XEMACPS_RXBUF_ADD_MASK)
 #endif
 
 /*****************************************************************************/
diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/emacps/src/xemacps_bdring.c b/bsp_z7/ps7_cortexa9_0/libsrc/emacps/src/xemacps_bdring.c
index 5a355ff..a2d7c33 100644
--- a/bsp_z7/ps7_cortexa9_0/libsrc/emacps/src/xemacps_bdring.c
+++ b/bsp_z7/ps7_cortexa9_0/libsrc/emacps/src/xemacps_bdring.c
@@ -1,5 +1,6 @@
 /******************************************************************************
-* Copyright (C) 2010 - 2020 Xilinx, Inc.  All rights reserved.
+* Copyright (C) 2010 - 2022 Xilinx, Inc.  All rights reserved.
+* Copyright (C) 2022 - 2024 Advanced Micro Devices, Inc. All rights reserved.
 * SPDX-License-Identifier: MIT
 ******************************************************************************/
 
@@ -7,7 +8,7 @@
 /**
 *
 * @file xemacps_bdring.c
-* @addtogroup emacps_v3_16
+* @addtogroup emacps Overview
 * @{
 *
 * This file implements buffer descriptor ring related functions.
@@ -676,12 +677,13 @@ u32 XEmacPs_BdRingFromHwTx(XEmacPs_BdRing * RingPtr, u32 BdLimit,
 				BdPartialCount = 0U;
 			}
 
+			/* Move on to next BD in work group */
+			CurBdPtr = XEmacPs_BdRingNext(RingPtr, CurBdPtr);
+
 			/* Reached the end of the work group */
 			if (CurBdPtr == RingPtr->HwTail) {
 				break;
 			}
-			/* Move on to next BD in work group */
-			CurBdPtr = XEmacPs_BdRingNext(RingPtr, CurBdPtr);
 		}
 
 		/* Subtract off any partial packet BDs found */
@@ -822,13 +824,13 @@ u32 XEmacPs_BdRingFromHwRx(XEmacPs_BdRing * RingPtr, u32 BdLimit,
 				BdPartialCount++;
 			}
 
+			/* Move on to next BD in work group */
+			CurBdPtr = XEmacPs_BdRingNext(RingPtr, CurBdPtr);
+
 			/* Reached the end of the work group */
 			if (CurBdPtr == RingPtr->HwTail) {
 				break;
 			}
-
-			/* Move on to next BD in work group */
-			CurBdPtr = XEmacPs_BdRingNext(RingPtr, CurBdPtr);
 		}
 
 		/* Subtract off any partial packet BDs found */
diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/emacps/src/xemacps_bdring.h b/bsp_z7/ps7_cortexa9_0/libsrc/emacps/src/xemacps_bdring.h
index f5653db..017669d 100644
--- a/bsp_z7/ps7_cortexa9_0/libsrc/emacps/src/xemacps_bdring.h
+++ b/bsp_z7/ps7_cortexa9_0/libsrc/emacps/src/xemacps_bdring.h
@@ -1,5 +1,6 @@
 /******************************************************************************
-* Copyright (C) 2010 - 2020 Xilinx, Inc.  All rights reserved.
+* Copyright (C) 2010 - 2022 Xilinx, Inc.  All rights reserved.
+* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved.
 * SPDX-License-Identifier: MIT
 ******************************************************************************/
 
@@ -7,7 +8,7 @@
 /**
 *
 * @file xemacps_bdring.h
-* @addtogroup emacps_v3_16
+* @addtogroup emacps Overview
 * @{
 *
 * The Xiline EmacPs Buffer Descriptor ring driver. This is part of EmacPs
diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/emacps/src/xemacps_control.c b/bsp_z7/ps7_cortexa9_0/libsrc/emacps/src/xemacps_control.c
index 4c72f20..719ba78 100644
--- a/bsp_z7/ps7_cortexa9_0/libsrc/emacps/src/xemacps_control.c
+++ b/bsp_z7/ps7_cortexa9_0/libsrc/emacps/src/xemacps_control.c
@@ -1,5 +1,6 @@
 /******************************************************************************
-* Copyright (C) 2009 - 2020 Xilinx, Inc.  All rights reserved.
+* Copyright (C) 2009 - 2022 Xilinx, Inc.  All rights reserved.
+* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved.
 * SPDX-License-Identifier: MIT
 ******************************************************************************/
 
@@ -7,7 +8,7 @@
 /**
  *
  * @file xemacps_control.c
-* @addtogroup emacps_v3_16
+* @addtogroup emacps Overview
 * @{
  *
  * Functions in this file implement general purpose command and control related
diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/emacps/src/xemacps_g.c b/bsp_z7/ps7_cortexa9_0/libsrc/emacps/src/xemacps_g.c
index 020c6f7..7bb25a4 100644
--- a/bsp_z7/ps7_cortexa9_0/libsrc/emacps/src/xemacps_g.c
+++ b/bsp_z7/ps7_cortexa9_0/libsrc/emacps/src/xemacps_g.c
@@ -1,5 +1,6 @@
 /******************************************************************************
-* Copyright (C) 2010 - 2020 Xilinx, Inc.  All rights reserved.
+* Copyright (C) 2010 - 2022 Xilinx, Inc.  All rights reserved.
+* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved.
 * SPDX-License-Identifier: MIT
 ******************************************************************************/
 
@@ -7,7 +8,7 @@
 /**
 *
 * @file xemacps_g.c
-* @addtogroup emacps_v3_16
+* @addtogroup emacps Overview
 * @{
 *
 * This file contains a configuration table that specifies the configuration of
diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/emacps/src/xemacps_hw.c b/bsp_z7/ps7_cortexa9_0/libsrc/emacps/src/xemacps_hw.c
index fdf9bab..06df263 100644
--- a/bsp_z7/ps7_cortexa9_0/libsrc/emacps/src/xemacps_hw.c
+++ b/bsp_z7/ps7_cortexa9_0/libsrc/emacps/src/xemacps_hw.c
@@ -1,5 +1,6 @@
 /******************************************************************************
-* Copyright (C) 2010 - 2020 Xilinx, Inc.  All rights reserved.
+* Copyright (C) 2010 - 2022 Xilinx, Inc.  All rights reserved.
+* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved.
 * SPDX-License-Identifier: MIT
 ******************************************************************************/
 
@@ -7,7 +8,7 @@
 /**
 *
 * @file xemacps_hw.c
-* @addtogroup emacps_v3_16
+* @addtogroup emacps Overview
 * @{
 *
 * This file contains the implementation of the ethernet interface reset sequence
diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/emacps/src/xemacps_hw.h b/bsp_z7/ps7_cortexa9_0/libsrc/emacps/src/xemacps_hw.h
index 59fe1ec..765411d 100644
--- a/bsp_z7/ps7_cortexa9_0/libsrc/emacps/src/xemacps_hw.h
+++ b/bsp_z7/ps7_cortexa9_0/libsrc/emacps/src/xemacps_hw.h
@@ -8,7 +8,7 @@
 /**
 *
 * @file xemacps_hw.h
-* @addtogroup emacps_v3_16
+* @addtogroup emacps Overview
 * @{
 *
 * This header file contains identifiers and low-level driver functions (or
diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/emacps/src/xemacps_intr.c b/bsp_z7/ps7_cortexa9_0/libsrc/emacps/src/xemacps_intr.c
index 2dbdb0b..c25e773 100644
--- a/bsp_z7/ps7_cortexa9_0/libsrc/emacps/src/xemacps_intr.c
+++ b/bsp_z7/ps7_cortexa9_0/libsrc/emacps/src/xemacps_intr.c
@@ -1,5 +1,6 @@
 /******************************************************************************
-* Copyright (C) 2010 - 2020 Xilinx, Inc.  All rights reserved.
+* Copyright (C) 2010 - 2022 Xilinx, Inc.  All rights reserved.
+* Copyright (C) 2022 - 2024 Advanced Micro Devices, Inc. All rights reserved.
 * SPDX-License-Identifier: MIT
 ******************************************************************************/
 
@@ -7,7 +8,7 @@
 /**
 *
 * @file xemacps_intr.c
-* @addtogroup emacps_v3_16
+* @addtogroup emacps Overview
 * @{
 *
 * Functions in this file implement general purpose interrupt processing related
@@ -228,7 +229,7 @@ void XEmacPs_IntrHandler(void *XEmacPsPtr)
 
 	/* Transmit error conditions interrupt */
         if (((RegISR & XEMACPS_IXR_TX_ERR_MASK) != 0x00000000U) &&
-            (!(RegISR & XEMACPS_IXR_TXCOMPL_MASK) != 0x00000000U)) {
+            ((!(RegISR & XEMACPS_IXR_TXCOMPL_MASK)) != 0x00000000U)) {
 		/* Clear TX status register */
 		RegSR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
 					  XEMACPS_TXSR_OFFSET);
diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/emacps/src/xemacps_sinit.c b/bsp_z7/ps7_cortexa9_0/libsrc/emacps/src/xemacps_sinit.c
index 8214a7d..89d3210 100644
--- a/bsp_z7/ps7_cortexa9_0/libsrc/emacps/src/xemacps_sinit.c
+++ b/bsp_z7/ps7_cortexa9_0/libsrc/emacps/src/xemacps_sinit.c
@@ -1,5 +1,6 @@
 /******************************************************************************
-* Copyright (C) 2010 - 2020 Xilinx, Inc.  All rights reserved.
+* Copyright (C) 2010 - 2022 Xilinx, Inc.  All rights reserved.
+* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved.
 * SPDX-License-Identifier: MIT
 ******************************************************************************/
 
@@ -7,7 +8,7 @@
 /**
 *
 * @file xemacps_sinit.c
-* @addtogroup emacps_v3_16
+* @addtogroup emacps Overview
 * @{
 *
 * This file contains lookup method by device ID when success, it returns
@@ -27,7 +28,9 @@
 /***************************** Include Files *********************************/
 
 #include "xemacps.h"
+#ifndef SDT
 #include "xparameters.h"
+#endif
 
 /************************** Constant Definitions *****************************/
 
@@ -35,7 +38,11 @@
 /**************************** Type Definitions *******************************/
 
 /*************************** Variable Definitions *****************************/
+#ifdef SDT
+extern XEmacPs_Config XEmacPs_ConfigTable[];
+#else
 extern XEmacPs_Config XEmacPs_ConfigTable[XPAR_XEMACPS_NUM_INSTANCES];
+#endif
 
 /***************** Macros (Inline Functions) Definitions *********************/
 
@@ -54,6 +61,22 @@ extern XEmacPs_Config XEmacPs_ConfigTable[XPAR_XEMACPS_NUM_INSTANCES];
 * device ID, or NULL if no match is found.
 *
 ******************************************************************************/
+#ifdef SDT
+XEmacPs_Config *XEmacPs_LookupConfig(UINTPTR BaseAddress)
+{
+	XEmacPs_Config *CfgPtr = NULL;
+	u32 Index;
+	/* Checks all the instances */
+	for (Index = (u32)0x0; XEmacPs_ConfigTable[Index].Name != NULL; Index++) {
+		if ((XEmacPs_ConfigTable[Index].BaseAddress == BaseAddress) ||
+		    !BaseAddress) {
+			CfgPtr = &XEmacPs_ConfigTable[Index];
+			break;
+		}
+	}
+	return (XEmacPs_Config *)(CfgPtr);
+}
+#else
 XEmacPs_Config *XEmacPs_LookupConfig(u16 DeviceId)
 {
 	XEmacPs_Config *CfgPtr = NULL;
@@ -68,4 +91,5 @@ XEmacPs_Config *XEmacPs_LookupConfig(u16 DeviceId)
 
 	return (XEmacPs_Config *)(CfgPtr);
 }
+#endif
 /** @} */
diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/gpiops/src/xgpiops.c b/bsp_z7/ps7_cortexa9_0/libsrc/gpiops/src/xgpiops.c
index 460bb2b..41ffbba 100644
--- a/bsp_z7/ps7_cortexa9_0/libsrc/gpiops/src/xgpiops.c
+++ b/bsp_z7/ps7_cortexa9_0/libsrc/gpiops/src/xgpiops.c
@@ -1,6 +1,6 @@
 /******************************************************************************
 * Copyright (C) 2010 - 2021 Xilinx, Inc.  All rights reserved.
-* Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
+* Copyright (c) 2022 - 2024 Advanced Micro Devices, Inc. All Rights Reserved.
 * SPDX-License-Identifier: MIT
 ******************************************************************************/
 
@@ -35,6 +35,9 @@
 *                     as Pointer to const,Casting operation to a pointer,
 *                     Literal value requires a U suffix.
 * 3.5   sne  03/13/19 Added Versal support.
+* 3.12  gm   07/11/23 Added SDT support.
+* 3.13  gm   03/15/24 Added multi-core interrupt support.
+*
 *
* ******************************************************************************/ @@ -89,7 +92,9 @@ s32 XGpioPs_CfgInitialize(XGpioPs *InstancePtr, const XGpioPs_Config *ConfigPtr, */ InstancePtr->IsReady = 0U; InstancePtr->GpioConfig.BaseAddr = EffectiveAddr; +#ifndef SDT InstancePtr->GpioConfig.DeviceId = ConfigPtr->DeviceId; +#endif InstancePtr->Handler = (XGpioPs_Handler)StubHandler; InstancePtr->Platform = XGetPlatform_Info(); @@ -176,6 +181,7 @@ s32 XGpioPs_CfgInitialize(XGpioPs *InstancePtr, const XGpioPs_Config *ConfigPtr, ((u32)(i) * XGPIOPS_REG_MASK_OFFSET) + XGPIOPS_INTDIS_OFFSET, 0xFFFFFFFFU); } + InstancePtr->CoreIntrMask[i] = 0; } /* Indicate the component is now ready to use. */ diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/gpiops/src/xgpiops.h b/bsp_z7/ps7_cortexa9_0/libsrc/gpiops/src/xgpiops.h index 8b1d89f..cce171a 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/gpiops/src/xgpiops.h +++ b/bsp_z7/ps7_cortexa9_0/libsrc/gpiops/src/xgpiops.h @@ -1,6 +1,6 @@ /****************************************************************************** * Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved. -* Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved. +* Copyright (c) 2022 - 2024 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -124,6 +124,11 @@ * 3.8 sne 09/17/20 Added description for Versal PS and PMC GPIO pins. * 3.9 sne 03/15/21 Fixed MISRA-C violations. * 3.11 sg 02/23/23 Update bank and pin mapping information. +* 3.12 gm 07/11/23 Added SDT support. +* 3.13 gm 03/15/24 Remove const of XGpioPs InstancePtr from function proto +* type of XGpioPs_IntrEnable, XGpioPs_IntrDisable, +* XGpioPs_IntrEnablePin and XGpioPs_IntrDisablePin +* to add multi-core interrupt support. * * * @@ -167,6 +172,7 @@ extern "C" { * Zynq Ultrascale+ MP GPIO device */ #define XGPIOPS_MAX_BANKS 0x04U /**< Max banks in a Zynq GPIO device */ +#define XGPIOPS_MAX_BANKS_CNT 0x06U /**< Max banks number of all platforms */ #define XGPIOPS_DEVICE_MAX_PIN_NUM_ZYNQMP (u32)174 /**< Max pins in the * Zynq Ultrascale+ MP GPIO device @@ -209,8 +215,18 @@ typedef void (*XGpioPs_Handler) (void *CallBackRef, u32 Bank, u32 Status); * This typedef contains configuration information for a device. */ typedef struct { +#ifndef SDT u16 DeviceId; /**< Unique ID of device */ +#else + char *Name; +#endif UINTPTR BaseAddr; /**< Register base address */ +#ifdef SDT + u16 IntrId; /** Bits[11:0] Interrupt-id Bits[15:12] + * trigger type and level flags */ + UINTPTR IntrParent; /** Bit[0] Interrupt parent type Bit[64/32:1] + * Parent base address */ +#endif } XGpioPs_Config; /** @@ -227,6 +243,7 @@ typedef struct { u32 MaxPinNum; /**< Max pins in the GPIO device */ u8 MaxBanks; /**< Max banks in a GPIO device */ u32 PmcGpio; /**< Flag for accessing PS GPIO for versal*/ + u32 CoreIntrMask[XGPIOPS_MAX_BANKS_CNT]; /**< Interrupt mask per core */ } XGpioPs; /************************** Variable Definitions *****************************/ @@ -262,12 +279,12 @@ void XGpioPs_SetOutputEnablePin(const XGpioPs *InstancePtr, u32 Pin, u32 OpEnabl u32 XGpioPs_GetOutputEnablePin(const XGpioPs *InstancePtr, u32 Pin); /* Diagnostic functions in xgpiops_selftest.c */ -s32 XGpioPs_SelfTest(const XGpioPs *InstancePtr); +s32 XGpioPs_SelfTest(XGpioPs *InstancePtr); /* Functions in xgpiops_intr.c */ /* Bank APIs in xgpiops_intr.c */ -void XGpioPs_IntrEnable(const XGpioPs *InstancePtr, u8 Bank, u32 Mask); -void XGpioPs_IntrDisable(const XGpioPs *InstancePtr, u8 Bank, u32 Mask); +void XGpioPs_IntrEnable(XGpioPs *InstancePtr, u8 Bank, u32 Mask); +void XGpioPs_IntrDisable(XGpioPs *InstancePtr, u8 Bank, u32 Mask); u32 XGpioPs_IntrGetEnabled(const XGpioPs *InstancePtr, u8 Bank); u32 XGpioPs_IntrGetStatus(const XGpioPs *InstancePtr, u8 Bank); void XGpioPs_IntrClear(const XGpioPs *InstancePtr, u8 Bank, u32 Mask); @@ -283,14 +300,18 @@ void XGpioPs_IntrHandler(const XGpioPs *InstancePtr); void XGpioPs_SetIntrTypePin(const XGpioPs *InstancePtr, u32 Pin, u8 IrqType); u8 XGpioPs_GetIntrTypePin(const XGpioPs *InstancePtr, u32 Pin); -void XGpioPs_IntrEnablePin(const XGpioPs *InstancePtr, u32 Pin); -void XGpioPs_IntrDisablePin(const XGpioPs *InstancePtr, u32 Pin); +void XGpioPs_IntrEnablePin(XGpioPs *InstancePtr, u32 Pin); +void XGpioPs_IntrDisablePin(XGpioPs *InstancePtr, u32 Pin); u32 XGpioPs_IntrGetEnabledPin(const XGpioPs *InstancePtr, u32 Pin); u32 XGpioPs_IntrGetStatusPin(const XGpioPs *InstancePtr, u32 Pin); void XGpioPs_IntrClearPin(const XGpioPs *InstancePtr, u32 Pin); /* Functions in xgpiops_sinit.c */ +#ifndef SDT XGpioPs_Config *XGpioPs_LookupConfig(u16 DeviceId); +#else +XGpioPs_Config *XGpioPs_LookupConfig(u32 BaseAddress); +#endif #ifdef __cplusplus } #endif diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/gpiops/src/xgpiops_g.c b/bsp_z7/ps7_cortexa9_0/libsrc/gpiops/src/xgpiops_g.c index 8d55f88..d8e1186 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/gpiops/src/xgpiops_g.c +++ b/bsp_z7/ps7_cortexa9_0/libsrc/gpiops/src/xgpiops_g.c @@ -1,6 +1,6 @@ /****************************************************************************** * Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved. -* Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved. +* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/gpiops/src/xgpiops_hw.c b/bsp_z7/ps7_cortexa9_0/libsrc/gpiops/src/xgpiops_hw.c index 7734ba8..57e684a 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/gpiops/src/xgpiops_hw.c +++ b/bsp_z7/ps7_cortexa9_0/libsrc/gpiops/src/xgpiops_hw.c @@ -1,6 +1,6 @@ /****************************************************************************** * Copyright (C) 2013 - 2021 Xilinx, Inc. All rights reserved. -* Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved. +* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/gpiops/src/xgpiops_hw.h b/bsp_z7/ps7_cortexa9_0/libsrc/gpiops/src/xgpiops_hw.h index d291abb..3248dc2 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/gpiops/src/xgpiops_hw.h +++ b/bsp_z7/ps7_cortexa9_0/libsrc/gpiops/src/xgpiops_hw.h @@ -1,6 +1,6 @@ /****************************************************************************** * Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved. -* Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved. +* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/gpiops/src/xgpiops_intr.c b/bsp_z7/ps7_cortexa9_0/libsrc/gpiops/src/xgpiops_intr.c index 0f3e26b..504df04 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/gpiops/src/xgpiops_intr.c +++ b/bsp_z7/ps7_cortexa9_0/libsrc/gpiops/src/xgpiops_intr.c @@ -1,6 +1,6 @@ /****************************************************************************** * Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved. -* Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved. +* Copyright (c) 2022 - 2024 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -35,6 +35,7 @@ * 3.5 sne 03/20/19 Fixed multiple interrupts problem CR#1024556. * 3.6 sne 06/12/19 Fixed IAR compiler warning. * 3.6 sne 08/14/19 Added interrupt handler support on versal. +* 3.13 gm 03/15/24 Added multi-core interrupt support. * * * @@ -71,7 +72,7 @@ * @note None. * *****************************************************************************/ -void XGpioPs_IntrEnable(const XGpioPs *InstancePtr, u8 Bank, u32 Mask) +void XGpioPs_IntrEnable(XGpioPs *InstancePtr, u8 Bank, u32 Mask) { Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); @@ -87,6 +88,9 @@ void XGpioPs_IntrEnable(const XGpioPs *InstancePtr, u8 Bank, u32 Mask) XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr, ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) + XGPIOPS_INTEN_OFFSET, Mask); + + /* Setup mask for CPU */ + InstancePtr->CoreIntrMask[Bank] |= Mask; } /****************************************************************************/ @@ -102,7 +106,7 @@ void XGpioPs_IntrEnable(const XGpioPs *InstancePtr, u8 Bank, u32 Mask) * @note None. * *****************************************************************************/ -void XGpioPs_IntrEnablePin(const XGpioPs *InstancePtr, u32 Pin) +void XGpioPs_IntrEnablePin(XGpioPs *InstancePtr, u32 Pin) { u8 Bank; u8 PinNumber; @@ -123,6 +127,9 @@ void XGpioPs_IntrEnablePin(const XGpioPs *InstancePtr, u32 Pin) XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr, ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) + XGPIOPS_INTEN_OFFSET, IntrReg); + + /* Setup mask for CPU */ + InstancePtr->CoreIntrMask[Bank] |= IntrReg; } /****************************************************************************/ @@ -142,7 +149,7 @@ void XGpioPs_IntrEnablePin(const XGpioPs *InstancePtr, u32 Pin) * @note None. * *****************************************************************************/ -void XGpioPs_IntrDisable(const XGpioPs *InstancePtr, u8 Bank, u32 Mask) +void XGpioPs_IntrDisable(XGpioPs *InstancePtr, u8 Bank, u32 Mask) { Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); @@ -158,6 +165,9 @@ void XGpioPs_IntrDisable(const XGpioPs *InstancePtr, u8 Bank, u32 Mask) XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr, ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) + XGPIOPS_INTDIS_OFFSET, Mask); + + /* Setup mask for CPU */ + InstancePtr->CoreIntrMask[Bank] &= ~Mask; } /****************************************************************************/ @@ -173,7 +183,7 @@ void XGpioPs_IntrDisable(const XGpioPs *InstancePtr, u8 Bank, u32 Mask) * @note None. * *****************************************************************************/ -void XGpioPs_IntrDisablePin(const XGpioPs *InstancePtr, u32 Pin) +void XGpioPs_IntrDisablePin(XGpioPs *InstancePtr, u32 Pin) { u8 Bank; u8 PinNumber; @@ -194,6 +204,9 @@ void XGpioPs_IntrDisablePin(const XGpioPs *InstancePtr, u32 Pin) XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr, ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) + XGPIOPS_INTDIS_OFFSET, IntrReg); + + /* Setup mask for CPU */ + InstancePtr->CoreIntrMask[Bank] &= ~IntrReg; } /****************************************************************************/ @@ -735,6 +748,7 @@ void XGpioPs_SetCallbackHandler(XGpioPs *InstancePtr, void *CallBackRef, void XGpioPs_IntrHandler(const XGpioPs *InstancePtr) { u8 Bank; + u32 Mask; u32 IntrStatus; u32 IntrEnabled; @@ -755,12 +769,12 @@ void XGpioPs_IntrHandler(const XGpioPs *InstancePtr) #endif IntrStatus = XGpioPs_IntrGetStatus(InstancePtr, Bank); IntrEnabled = XGpioPs_IntrGetEnabled(InstancePtr,Bank); - if ((IntrStatus & IntrEnabled) != (u32)0) { - XGpioPs_IntrClear(InstancePtr, Bank, - (IntrStatus & IntrEnabled)); - InstancePtr->Handler(InstancePtr-> - CallBackRef, Bank, - (IntrStatus & IntrEnabled)); + Mask = IntrStatus & IntrEnabled & InstancePtr->CoreIntrMask[Bank]; + + if (Mask != (u32)0) + { + XGpioPs_IntrClear(InstancePtr, Bank, Mask); + InstancePtr->Handler(InstancePtr->CallBackRef, Bank, Mask); } } } diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/gpiops/src/xgpiops_selftest.c b/bsp_z7/ps7_cortexa9_0/libsrc/gpiops/src/xgpiops_selftest.c index b666f7d..db8eb0b 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/gpiops/src/xgpiops_selftest.c +++ b/bsp_z7/ps7_cortexa9_0/libsrc/gpiops/src/xgpiops_selftest.c @@ -1,6 +1,6 @@ /****************************************************************************** * Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved. -* Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved. +* Copyright (c) 2022 - 2024 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -61,7 +61,7 @@ * * ******************************************************************************/ -s32 XGpioPs_SelfTest(const XGpioPs *InstancePtr) +s32 XGpioPs_SelfTest(XGpioPs *InstancePtr) { s32 Status = (s32)0; u32 IntrEnabled; diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/gpiops/src/xgpiops_sinit.c b/bsp_z7/ps7_cortexa9_0/libsrc/gpiops/src/xgpiops_sinit.c index 72a2ad8..3b59fe3 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/gpiops/src/xgpiops_sinit.c +++ b/bsp_z7/ps7_cortexa9_0/libsrc/gpiops/src/xgpiops_sinit.c @@ -1,6 +1,6 @@ /****************************************************************************** * Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved. -* Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved. +* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -24,6 +24,8 @@ * ----- ---- -------- ----------------------------------------------- * 1.00a sv 01/15/10 First Release * 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance. +* 3.12 gm 07/11/23 Added SDT support. +* * * ******************************************************************************/ @@ -57,6 +59,7 @@ * @note None. * ******************************************************************************/ +#ifndef SDT XGpioPs_Config *XGpioPs_LookupConfig(u16 DeviceId) { XGpioPs_Config *CfgPtr = NULL; @@ -71,4 +74,21 @@ XGpioPs_Config *XGpioPs_LookupConfig(u16 DeviceId) return (XGpioPs_Config *)CfgPtr; } +#else +XGpioPs_Config *XGpioPs_LookupConfig(u32 BaseAddress) +{ + XGpioPs_Config *CfgPtr = NULL; + u32 Index; + + for (Index = (u32)0x0; XGpioPs_ConfigTable[Index].Name != NULL; Index++) { + if ((XGpioPs_ConfigTable[Index].BaseAddr == BaseAddress) || + !BaseAddress) { + CfgPtr = &XGpioPs_ConfigTable[Index]; + break; + } + } + + return (XGpioPs_Config *)CfgPtr; +} +#endif /** @} */ diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/qspips/src/xqspips.c b/bsp_z7/ps7_cortexa9_0/libsrc/qspips/src/xqspips.c index 68f1d3f..0974aed 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/qspips/src/xqspips.c +++ b/bsp_z7/ps7_cortexa9_0/libsrc/qspips/src/xqspips.c @@ -1,5 +1,6 @@ /****************************************************************************** * Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -7,7 +8,7 @@ /** * * @file xqspips.c -* @addtogroup qspips_v3_10 +* @addtogroup qspips Overview * @{ * * Contains implements the interface functions of the XQspiPs driver. @@ -117,7 +118,7 @@ typedef struct { /************************** Function Prototypes ******************************/ static void XQspiPs_GetReadData(XQspiPs *InstancePtr, u32 Data, u8 Size); static void StubStatusHandler(void *CallBackRef, u32 StatusEvent, - unsigned ByteCount); + unsigned ByteCount); /************************** Variable Definitions *****************************/ @@ -191,7 +192,7 @@ static XQspiPsInstFormat FlashInst[] = { * ******************************************************************************/ int XQspiPs_CfgInitialize(XQspiPs *InstancePtr, XQspiPs_Config *ConfigPtr, - u32 EffectiveAddr) + u32 EffectiveAddr) { Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(ConfigPtr != NULL); @@ -265,11 +266,11 @@ void XQspiPs_Reset(XQspiPs *InstancePtr) * Do not modify reserved bits. */ ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress, - XQSPIPS_CR_OFFSET); + XQSPIPS_CR_OFFSET); ConfigReg |= XQSPIPS_CR_RESET_MASK_SET; ConfigReg &= ~XQSPIPS_CR_RESET_MASK_CLR; XQspiPs_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPS_CR_OFFSET, - ConfigReg); + ConfigReg); } /*****************************************************************************/ @@ -299,7 +300,7 @@ void XQspiPs_Abort(XQspiPs *InstancePtr) * De-assert slave select lines. */ ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress, - XQSPIPS_CR_OFFSET); + XQSPIPS_CR_OFFSET); ConfigReg |= (XQSPIPS_CR_SSCTRL_MASK | XQSPIPS_CR_SSFORCE_MASK); XQspiPs_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPS_CR_OFFSET, ConfigReg); @@ -310,24 +311,24 @@ void XQspiPs_Abort(XQspiPs *InstancePtr) IsLock = XQspiPs_ReadReg(XPAR_XSLCR_0_BASEADDR, SLCR_LOCKSTA); if (IsLock) { XQspiPs_WriteReg(XPAR_XSLCR_0_BASEADDR, SLCR_UNLOCK, - SLCR_UNLOCK_MASK); + SLCR_UNLOCK_MASK); } XQspiPs_WriteReg(XPAR_XSLCR_0_BASEADDR, LQSPI_RST_CTRL, - LQSPI_RST_CTRL_MASK); + LQSPI_RST_CTRL_MASK); XQspiPs_WriteReg(XPAR_XSLCR_0_BASEADDR, LQSPI_RST_CTRL, 0x0); if (IsLock) { XQspiPs_WriteReg(XPAR_XSLCR_0_BASEADDR, SLCR_LOCK, - SLCR_LOCK_MASK); + SLCR_LOCK_MASK); } /* * Set the RX and TX FIFO threshold to reset value (one) */ XQspiPs_WriteReg(InstancePtr->Config.BaseAddress, - XQSPIPS_RXWR_OFFSET, XQSPIPS_RXWR_RESET_VALUE); + XQSPIPS_RXWR_OFFSET, XQSPIPS_RXWR_RESET_VALUE); XQspiPs_WriteReg(InstancePtr->Config.BaseAddress, - XQSPIPS_TXWR_OFFSET, XQSPIPS_TXWR_RESET_VALUE); + XQSPIPS_TXWR_OFFSET, XQSPIPS_TXWR_RESET_VALUE); InstancePtr->RemainingBytes = 0; InstancePtr->RequestedBytes = 0; @@ -400,7 +401,7 @@ void XQspiPs_Abort(XQspiPs *InstancePtr) * ******************************************************************************/ s32 XQspiPs_Transfer(XQspiPs *InstancePtr, u8 *SendBufPtr, u8 *RecvBufPtr, - u32 ByteCount) + u32 ByteCount) { u32 StatusReg; u32 ConfigReg; @@ -460,7 +461,7 @@ s32 XQspiPs_Transfer(XQspiPs *InstancePtr, u8 *SendBufPtr, u8 *RecvBufPtr, * Set the RX FIFO threshold */ XQspiPs_WriteReg(InstancePtr->Config.BaseAddress, - XQSPIPS_RXWR_OFFSET, XQSPIPS_RXFIFO_THRESHOLD_OPT); + XQSPIPS_RXWR_OFFSET, XQSPIPS_RXFIFO_THRESHOLD_OPT); /* * If the slave select is "Forced" or under manual control, @@ -468,11 +469,11 @@ s32 XQspiPs_Transfer(XQspiPs *InstancePtr, u8 *SendBufPtr, u8 *RecvBufPtr, */ if (XQspiPs_IsManualChipSelect(InstancePtr)) { ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress, - XQSPIPS_CR_OFFSET); + XQSPIPS_CR_OFFSET); ConfigReg &= ~XQSPIPS_CR_SSCTRL_MASK; XQspiPs_WriteReg(InstancePtr->Config.BaseAddress, - XQSPIPS_CR_OFFSET, - ConfigReg); + XQSPIPS_CR_OFFSET, + ConfigReg); } /* @@ -484,7 +485,7 @@ s32 XQspiPs_Transfer(XQspiPs *InstancePtr, u8 *SendBufPtr, u8 *RecvBufPtr, * Clear all the interrupts. */ XQspiPs_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPS_SR_OFFSET, - XQSPIPS_IXR_WR_TO_CLR_MASK); + XQSPIPS_IXR_WR_TO_CLR_MASK); if (Index < ARRAY_SIZE(FlashInst)) { CurrInst = &FlashInst[Index]; @@ -493,7 +494,7 @@ s32 XQspiPs_Transfer(XQspiPs *InstancePtr, u8 *SendBufPtr, u8 *RecvBufPtr, * Spansion (3 bytes) and Micron (2 bytes) */ if ((CurrInst->OpCode == XQSPIPS_FLASH_OPCODE_WRSR) && - (ByteCount == 3)) { + (ByteCount == 3)) { CurrInst->InstSize = 3; CurrInst->TxOffset = XQSPIPS_TXD_11_OFFSET; } @@ -511,36 +512,36 @@ s32 XQspiPs_Transfer(XQspiPs *InstancePtr, u8 *SendBufPtr, u8 *RecvBufPtr, * The remaining bytes of the instruction will be transmitted * through TXD0 below. */ - switch (ByteCount%4) { - case XQSPIPS_SIZE_ONE: - CurrInst->OpCode = Instruction; - CurrInst->InstSize = XQSPIPS_SIZE_ONE; - CurrInst->TxOffset = XQSPIPS_TXD_01_OFFSET; - if (ByteCount > 4) { - SwitchFlag = 1; - } - break; - case XQSPIPS_SIZE_TWO: - CurrInst->OpCode = Instruction; - CurrInst->InstSize = XQSPIPS_SIZE_TWO; - CurrInst->TxOffset = XQSPIPS_TXD_10_OFFSET; - if (ByteCount > 4) { - SwitchFlag = 1; - } - break; - case XQSPIPS_SIZE_THREE: - CurrInst->OpCode = Instruction; - CurrInst->InstSize = XQSPIPS_SIZE_THREE; - CurrInst->TxOffset = XQSPIPS_TXD_11_OFFSET; - if (ByteCount > 4) { - SwitchFlag = 1; - } - break; - default: - CurrInst->OpCode = Instruction; - CurrInst->InstSize = XQSPIPS_SIZE_FOUR; - CurrInst->TxOffset = XQSPIPS_TXD_00_OFFSET; - break; + switch (ByteCount % 4) { + case XQSPIPS_SIZE_ONE: + CurrInst->OpCode = Instruction; + CurrInst->InstSize = XQSPIPS_SIZE_ONE; + CurrInst->TxOffset = XQSPIPS_TXD_01_OFFSET; + if (ByteCount > 4) { + SwitchFlag = 1; + } + break; + case XQSPIPS_SIZE_TWO: + CurrInst->OpCode = Instruction; + CurrInst->InstSize = XQSPIPS_SIZE_TWO; + CurrInst->TxOffset = XQSPIPS_TXD_10_OFFSET; + if (ByteCount > 4) { + SwitchFlag = 1; + } + break; + case XQSPIPS_SIZE_THREE: + CurrInst->OpCode = Instruction; + CurrInst->InstSize = XQSPIPS_SIZE_THREE; + CurrInst->TxOffset = XQSPIPS_TXD_11_OFFSET; + if (ByteCount > 4) { + SwitchFlag = 1; + } + break; + default: + CurrInst->OpCode = Instruction; + CurrInst->InstSize = XQSPIPS_SIZE_FOUR; + CurrInst->TxOffset = XQSPIPS_TXD_00_OFFSET; + break; } } @@ -577,8 +578,8 @@ s32 XQspiPs_Transfer(XQspiPs *InstancePtr, u8 *SendBufPtr, u8 *RecvBufPtr, */ if (XQspiPs_IsManualStart(InstancePtr)) { ConfigReg = XQspiPs_ReadReg( - InstancePtr->Config.BaseAddress, - XQSPIPS_CR_OFFSET); + InstancePtr->Config.BaseAddress, + XQSPIPS_CR_OFFSET); ConfigReg |= XQSPIPS_CR_MANSTRT_MASK; XQspiPs_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPS_CR_OFFSET, ConfigReg); @@ -588,8 +589,8 @@ s32 XQspiPs_Transfer(XQspiPs *InstancePtr, u8 *SendBufPtr, u8 *RecvBufPtr, */ do { StatusReg = XQspiPs_ReadReg( - InstancePtr->Config.BaseAddress, - XQSPIPS_SR_OFFSET); + InstancePtr->Config.BaseAddress, + XQSPIPS_SR_OFFSET); } while ((StatusReg & XQSPIPS_IXR_TXOW_MASK) == 0); } @@ -599,15 +600,15 @@ s32 XQspiPs_Transfer(XQspiPs *InstancePtr, u8 *SendBufPtr, u8 *RecvBufPtr, * we have to send). */ while ((InstancePtr->RemainingBytes > 0) && - (TransCount < XQSPIPS_FIFO_DEPTH)) { + (TransCount < XQSPIPS_FIFO_DEPTH)) { /* * In case of Write fill the Tx FIFO with data to be transmitted. * In case of Read fill the TX FIFO with first 4bytes(1Byte Command + 3Byte Address) * of data from TX Buffer and the remaining bytes(i.e., RequestedBytes - 4) * with DUMMY. */ - if(InstancePtr->RecvBufferPtr && - ((InstancePtr->RequestedBytes - InstancePtr->RemainingBytes) > 4)) { + if (InstancePtr->RecvBufferPtr && + ((InstancePtr->RequestedBytes - InstancePtr->RemainingBytes) > 4)) { XQspiPs_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPS_TXD_00_OFFSET, XQSPIPS_DUMMY_TX_DATA); } else { @@ -629,19 +630,19 @@ s32 XQspiPs_Transfer(XQspiPs *InstancePtr, u8 *SendBufPtr, u8 *RecvBufPtr, * enabling interrupts should have been done by the caller). */ XQspiPs_WriteReg(InstancePtr->Config.BaseAddress, - XQSPIPS_IER_OFFSET, XQSPIPS_IXR_RXNEMPTY_MASK | - XQSPIPS_IXR_TXOW_MASK | XQSPIPS_IXR_RXOVR_MASK | - XQSPIPS_IXR_TXUF_MASK); + XQSPIPS_IER_OFFSET, XQSPIPS_IXR_RXNEMPTY_MASK | + XQSPIPS_IXR_TXOW_MASK | XQSPIPS_IXR_RXOVR_MASK | + XQSPIPS_IXR_TXUF_MASK); /* * If, in Manual Start mode, Start the transfer. */ if (XQspiPs_IsManualStart(InstancePtr)) { ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress, - XQSPIPS_CR_OFFSET); + XQSPIPS_CR_OFFSET); ConfigReg |= XQSPIPS_CR_MANSTRT_MASK; XQspiPs_WriteReg(InstancePtr->Config.BaseAddress, - XQSPIPS_CR_OFFSET, ConfigReg); + XQSPIPS_CR_OFFSET, ConfigReg); } return XST_SUCCESS; @@ -701,7 +702,7 @@ s32 XQspiPs_Transfer(XQspiPs *InstancePtr, u8 *SendBufPtr, u8 *RecvBufPtr, * ******************************************************************************/ s32 XQspiPs_PolledTransfer(XQspiPs *InstancePtr, u8 *SendBufPtr, - u8 *RecvBufPtr, u32 ByteCount) + u8 *RecvBufPtr, u32 ByteCount) { u32 StatusReg; u32 ConfigReg; @@ -762,7 +763,7 @@ s32 XQspiPs_PolledTransfer(XQspiPs *InstancePtr, u8 *SendBufPtr, * Set the RX FIFO threshold */ XQspiPs_WriteReg(InstancePtr->Config.BaseAddress, - XQSPIPS_RXWR_OFFSET, XQSPIPS_RXFIFO_THRESHOLD_OPT); + XQSPIPS_RXWR_OFFSET, XQSPIPS_RXFIFO_THRESHOLD_OPT); /* * If the slave select is "Forced" or under manual control, @@ -770,11 +771,11 @@ s32 XQspiPs_PolledTransfer(XQspiPs *InstancePtr, u8 *SendBufPtr, */ if (XQspiPs_IsManualChipSelect(InstancePtr)) { ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress, - XQSPIPS_CR_OFFSET); + XQSPIPS_CR_OFFSET); ConfigReg &= ~XQSPIPS_CR_SSCTRL_MASK; XQspiPs_WriteReg(InstancePtr->Config.BaseAddress, - XQSPIPS_CR_OFFSET, - ConfigReg); + XQSPIPS_CR_OFFSET, + ConfigReg); } /* @@ -790,7 +791,7 @@ s32 XQspiPs_PolledTransfer(XQspiPs *InstancePtr, u8 *SendBufPtr, * Spansion (3 bytes) and Micron (2 bytes) */ if ((CurrInst->OpCode == XQSPIPS_FLASH_OPCODE_WRSR) && - (ByteCount == 3)) { + (ByteCount == 3)) { CurrInst->InstSize = 3; CurrInst->TxOffset = XQSPIPS_TXD_11_OFFSET; } @@ -808,35 +809,35 @@ s32 XQspiPs_PolledTransfer(XQspiPs *InstancePtr, u8 *SendBufPtr, * through TXD0 below. */ switch (ByteCount % 4) { - case XQSPIPS_SIZE_ONE: - CurrInst->OpCode = Instruction; - CurrInst->InstSize = XQSPIPS_SIZE_ONE; - CurrInst->TxOffset = XQSPIPS_TXD_01_OFFSET; - if (ByteCount > 4) { - SwitchFlag = 1; - } - break; - case XQSPIPS_SIZE_TWO: - CurrInst->OpCode = Instruction; - CurrInst->InstSize = XQSPIPS_SIZE_TWO; - CurrInst->TxOffset = XQSPIPS_TXD_10_OFFSET; - if (ByteCount > 4) { - SwitchFlag = 1; - } - break; - case XQSPIPS_SIZE_THREE: - CurrInst->OpCode = Instruction; - CurrInst->InstSize = XQSPIPS_SIZE_THREE; - CurrInst->TxOffset = XQSPIPS_TXD_11_OFFSET; - if (ByteCount > 4) { - SwitchFlag = 1; - } - break; - default: - CurrInst->OpCode = Instruction; - CurrInst->InstSize = XQSPIPS_SIZE_FOUR; - CurrInst->TxOffset = XQSPIPS_TXD_00_OFFSET; - break; + case XQSPIPS_SIZE_ONE: + CurrInst->OpCode = Instruction; + CurrInst->InstSize = XQSPIPS_SIZE_ONE; + CurrInst->TxOffset = XQSPIPS_TXD_01_OFFSET; + if (ByteCount > 4) { + SwitchFlag = 1; + } + break; + case XQSPIPS_SIZE_TWO: + CurrInst->OpCode = Instruction; + CurrInst->InstSize = XQSPIPS_SIZE_TWO; + CurrInst->TxOffset = XQSPIPS_TXD_10_OFFSET; + if (ByteCount > 4) { + SwitchFlag = 1; + } + break; + case XQSPIPS_SIZE_THREE: + CurrInst->OpCode = Instruction; + CurrInst->InstSize = XQSPIPS_SIZE_THREE; + CurrInst->TxOffset = XQSPIPS_TXD_11_OFFSET; + if (ByteCount > 4) { + SwitchFlag = 1; + } + break; + default: + CurrInst->OpCode = Instruction; + CurrInst->InstSize = XQSPIPS_SIZE_FOUR; + CurrInst->TxOffset = XQSPIPS_TXD_00_OFFSET; + break; } } @@ -860,7 +861,7 @@ s32 XQspiPs_PolledTransfer(XQspiPs *InstancePtr, u8 *SendBufPtr, /* Write the command to the FIFO */ XQspiPs_WriteReg(InstancePtr->Config.BaseAddress, - CurrInst->TxOffset, Data); + CurrInst->TxOffset, Data); ++TransCount; /* @@ -873,8 +874,8 @@ s32 XQspiPs_PolledTransfer(XQspiPs *InstancePtr, u8 *SendBufPtr, */ if (XQspiPs_IsManualStart(InstancePtr)) { ConfigReg = XQspiPs_ReadReg( - InstancePtr->Config.BaseAddress, - XQSPIPS_CR_OFFSET); + InstancePtr->Config.BaseAddress, + XQSPIPS_CR_OFFSET); ConfigReg |= XQSPIPS_CR_MANSTRT_MASK; XQspiPs_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPS_CR_OFFSET, ConfigReg); @@ -884,8 +885,8 @@ s32 XQspiPs_PolledTransfer(XQspiPs *InstancePtr, u8 *SendBufPtr, */ do { StatusReg = XQspiPs_ReadReg( - InstancePtr->Config.BaseAddress, - XQSPIPS_SR_OFFSET); + InstancePtr->Config.BaseAddress, + XQSPIPS_SR_OFFSET); } while ((StatusReg & XQSPIPS_IXR_TXOW_MASK) == 0); } @@ -901,15 +902,15 @@ s32 XQspiPs_PolledTransfer(XQspiPs *InstancePtr, u8 *SendBufPtr, * many as we have to send). */ while ((InstancePtr->RemainingBytes > 0) && - (TransCount < XQSPIPS_FIFO_DEPTH)) { + (TransCount < XQSPIPS_FIFO_DEPTH)) { /* * In case of Write fill the Tx FIFO with data to be transmitted. * In case of Read fill the TX FIFO with first 4bytes(1Byte Command + 3Byte Address) * of data from TX Buffer and the remaining bytes(i.e., RequestedBytes - 4) * with DUMMY. */ - if(InstancePtr->RecvBufferPtr && - ((InstancePtr->RequestedBytes - InstancePtr->RemainingBytes) > 4)) { + if (InstancePtr->RecvBufferPtr && + ((InstancePtr->RequestedBytes - InstancePtr->RemainingBytes) > 4)) { XQspiPs_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPS_TXD_00_OFFSET, XQSPIPS_DUMMY_TX_DATA); } else { @@ -927,22 +928,22 @@ s32 XQspiPs_PolledTransfer(XQspiPs *InstancePtr, u8 *SendBufPtr, } while ((InstancePtr->RemainingBytes > 0) || - (InstancePtr->RequestedBytes > 0)) { + (InstancePtr->RequestedBytes > 0)) { /* * Fill the TX FIFO with RX threshold no. of entries (or as * many as we have to send, in case that's less). */ while ((InstancePtr->RemainingBytes > 0) && - (TransCount < XQSPIPS_RXFIFO_THRESHOLD_OPT)) { + (TransCount < XQSPIPS_RXFIFO_THRESHOLD_OPT)) { /* * In case of Write fill the Tx FIFO with data to be transmitted. * In case of Read fill the TX FIFO with first 4bytes(1Byte Command + 3Byte Address) * of data from TX Buffer and the remaining bytes(i.e., RequestedBytes - 4) * with DUMMY. */ - if(InstancePtr->RecvBufferPtr && - ((InstancePtr->RequestedBytes - InstancePtr->RemainingBytes) > 4)) { + if (InstancePtr->RecvBufferPtr && + ((InstancePtr->RequestedBytes - InstancePtr->RemainingBytes) > 4)) { XQspiPs_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPS_TXD_00_OFFSET, XQSPIPS_DUMMY_TX_DATA); } else { @@ -964,8 +965,8 @@ s32 XQspiPs_PolledTransfer(XQspiPs *InstancePtr, u8 *SendBufPtr, */ if (IsManualStart == TRUE) { ConfigReg = XQspiPs_ReadReg( - InstancePtr->Config.BaseAddress, - XQSPIPS_CR_OFFSET); + InstancePtr->Config.BaseAddress, + XQSPIPS_CR_OFFSET); ConfigReg |= XQSPIPS_CR_MANSTRT_MASK; XQspiPs_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPS_CR_OFFSET, ConfigReg); @@ -988,10 +989,10 @@ s32 XQspiPs_PolledTransfer(XQspiPs *InstancePtr, u8 *SendBufPtr, do { StatusReg = XQspiPs_ReadReg( - InstancePtr->Config.BaseAddress, - XQSPIPS_SR_OFFSET); + InstancePtr->Config.BaseAddress, + XQSPIPS_SR_OFFSET); } while (((StatusReg & XQSPIPS_IXR_TXOW_MASK) == 0) && - ((StatusReg & XQSPIPS_IXR_RXNEMPTY_MASK) == 0)); + ((StatusReg & XQSPIPS_IXR_RXNEMPTY_MASK) == 0)); /* * A transmit has just completed. Process received data @@ -1004,7 +1005,7 @@ s32 XQspiPs_PolledTransfer(XQspiPs *InstancePtr, u8 *SendBufPtr, * software may not care to receive data). */ while ((InstancePtr->RequestedBytes > 0) && - (RxCount < XQSPIPS_RXFIFO_THRESHOLD_OPT)) { + (RxCount < XQSPIPS_RXFIFO_THRESHOLD_OPT)) { u32 Data; RxCount++; @@ -1012,13 +1013,13 @@ s32 XQspiPs_PolledTransfer(XQspiPs *InstancePtr, u8 *SendBufPtr, if (InstancePtr->RecvBufferPtr != NULL) { if (InstancePtr->RequestedBytes < 4) { Data = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress, - XQSPIPS_RXD_OFFSET); + XQSPIPS_RXD_OFFSET); XQspiPs_GetReadData(InstancePtr, Data, - InstancePtr->RequestedBytes); + InstancePtr->RequestedBytes); } else { (*(u32 *)InstancePtr->RecvBufferPtr) = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress, - XQSPIPS_RXD_OFFSET); + XQSPIPS_RXD_OFFSET); InstancePtr->RecvBufferPtr += 4; InstancePtr->RequestedBytes -= 4; if (InstancePtr->RequestedBytes < 0) { @@ -1027,7 +1028,7 @@ s32 XQspiPs_PolledTransfer(XQspiPs *InstancePtr, u8 *SendBufPtr, } } else { Data = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress, - XQSPIPS_RXD_OFFSET); + XQSPIPS_RXD_OFFSET); InstancePtr->RequestedBytes -= 4; } } @@ -1040,10 +1041,10 @@ s32 XQspiPs_PolledTransfer(XQspiPs *InstancePtr, u8 *SendBufPtr, */ if (XQspiPs_IsManualChipSelect(InstancePtr)) { ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress, - XQSPIPS_CR_OFFSET); + XQSPIPS_CR_OFFSET); ConfigReg |= XQSPIPS_CR_SSCTRL_MASK; XQspiPs_WriteReg(InstancePtr->Config.BaseAddress, - XQSPIPS_CR_OFFSET, ConfigReg); + XQSPIPS_CR_OFFSET, ConfigReg); } /* @@ -1060,7 +1061,7 @@ s32 XQspiPs_PolledTransfer(XQspiPs *InstancePtr, u8 *SendBufPtr, * Reset the RX FIFO threshold to one */ XQspiPs_WriteReg(InstancePtr->Config.BaseAddress, - XQSPIPS_RXWR_OFFSET, XQSPIPS_RXWR_RESET_VALUE); + XQSPIPS_RXWR_OFFSET, XQSPIPS_RXWR_RESET_VALUE); return XST_SUCCESS; } @@ -1085,7 +1086,7 @@ s32 XQspiPs_PolledTransfer(XQspiPs *InstancePtr, u8 *SendBufPtr, * ******************************************************************************/ int XQspiPs_LqspiRead(XQspiPs *InstancePtr, u8 *RecvBufPtr, - u32 Address, unsigned ByteCount) + u32 Address, unsigned ByteCount) { int Status = (int)XST_SUCCESS; Xil_AssertNonvoid(InstancePtr != NULL); @@ -1102,11 +1103,11 @@ int XQspiPs_LqspiRead(XQspiPs *InstancePtr, u8 *RecvBufPtr, XQspiPs_Enable(InstancePtr); if (XQspiPs_GetLqspiConfigReg(InstancePtr) & - XQSPIPS_LQSPI_CR_LINEAR_MASK) { + XQSPIPS_LQSPI_CR_LINEAR_MASK) { memcpy((void *)RecvBufPtr, - (const void *)(XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR + - Address), - (size_t)ByteCount); + (const void *)(XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR + + Address), + (size_t)ByteCount); Status = (int)XST_SUCCESS; } else { Status = (int)XST_FAILURE; @@ -1160,10 +1161,10 @@ int XQspiPs_SetSlaveSelect(XQspiPs *InstancePtr) * Select the slave */ ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress, - XQSPIPS_CR_OFFSET); + XQSPIPS_CR_OFFSET); ConfigReg &= ~XQSPIPS_CR_SSCTRL_MASK; XQspiPs_WriteReg(InstancePtr->Config.BaseAddress, - XQSPIPS_CR_OFFSET, ConfigReg); + XQSPIPS_CR_OFFSET, ConfigReg); return XST_SUCCESS; } @@ -1206,7 +1207,7 @@ int XQspiPs_SetSlaveSelect(XQspiPs *InstancePtr) * ******************************************************************************/ void XQspiPs_SetStatusHandler(XQspiPs *InstancePtr, void *CallBackRef, - XQspiPs_StatusHandler FuncPtr) + XQspiPs_StatusHandler FuncPtr) { Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid(FuncPtr != NULL); @@ -1233,7 +1234,7 @@ void XQspiPs_SetStatusHandler(XQspiPs *InstancePtr, void *CallBackRef, * ******************************************************************************/ static void StubStatusHandler(void *CallBackRef, u32 StatusEvent, - unsigned ByteCount) + unsigned ByteCount) { (void) CallBackRef; (void) StatusEvent; @@ -1298,15 +1299,15 @@ void XQspiPs_InterruptHandler(void *InstancePtr) * TX_EMPTY interrupt. */ IntrStatus = XQspiPs_ReadReg(QspiPtr->Config.BaseAddress, - XQSPIPS_SR_OFFSET); + XQSPIPS_SR_OFFSET); XQspiPs_WriteReg(QspiPtr->Config.BaseAddress, XQSPIPS_SR_OFFSET, - (IntrStatus & XQSPIPS_IXR_WR_TO_CLR_MASK)); + (IntrStatus & XQSPIPS_IXR_WR_TO_CLR_MASK)); XQspiPs_WriteReg(QspiPtr->Config.BaseAddress, XQSPIPS_IDR_OFFSET, - XQSPIPS_IXR_TXOW_MASK | XQSPIPS_IXR_RXNEMPTY_MASK | - XQSPIPS_IXR_RXOVR_MASK | XQSPIPS_IXR_TXUF_MASK); + XQSPIPS_IXR_TXOW_MASK | XQSPIPS_IXR_RXNEMPTY_MASK | + XQSPIPS_IXR_RXOVR_MASK | XQSPIPS_IXR_TXUF_MASK); if ((IntrStatus & XQSPIPS_IXR_TXOW_MASK) || - (IntrStatus & XQSPIPS_IXR_RXNEMPTY_MASK)) { + (IntrStatus & XQSPIPS_IXR_RXNEMPTY_MASK)) { /* * Rx FIFO has just reached threshold no. of entries. @@ -1320,24 +1321,24 @@ void XQspiPs_InterruptHandler(void *InstancePtr) */ TransCount = QspiPtr->RequestedBytes - QspiPtr->RemainingBytes; if (TransCount % 4) { - TransCount = TransCount/4 + 1; + TransCount = TransCount / 4 + 1; } else { - TransCount = TransCount/4; + TransCount = TransCount / 4; } while ((Count < TransCount) && - (Count < XQSPIPS_RXFIFO_THRESHOLD_OPT)) { + (Count < XQSPIPS_RXFIFO_THRESHOLD_OPT)) { if (QspiPtr->RecvBufferPtr != NULL) { if (QspiPtr->RequestedBytes < 4) { Data = XQspiPs_ReadReg(QspiPtr->Config.BaseAddress, - XQSPIPS_RXD_OFFSET); + XQSPIPS_RXD_OFFSET); XQspiPs_GetReadData(QspiPtr, Data, - QspiPtr->RequestedBytes); + QspiPtr->RequestedBytes); } else { (*(u32 *)QspiPtr->RecvBufferPtr) = XQspiPs_ReadReg(QspiPtr->Config.BaseAddress, - XQSPIPS_RXD_OFFSET); + XQSPIPS_RXD_OFFSET); QspiPtr->RecvBufferPtr += 4; QspiPtr->RequestedBytes -= 4; if (QspiPtr->RequestedBytes < 0) { @@ -1363,7 +1364,7 @@ void XQspiPs_InterruptHandler(void *InstancePtr) * remaining entries (in case that is less than threshold) */ while ((QspiPtr->RemainingBytes > 0) && - (Count < XQSPIPS_RXFIFO_THRESHOLD_OPT)) { + (Count < XQSPIPS_RXFIFO_THRESHOLD_OPT)) { /* * Send more data. * In case of Write fill the Tx FIFO with data to be transmitted. @@ -1371,8 +1372,8 @@ void XQspiPs_InterruptHandler(void *InstancePtr) * of data from TX Buffer and the remaining bytes(i.e., RequestedBytes - 4) * with DUMMY. */ - if(QspiPtr->RecvBufferPtr && - ((QspiPtr->RequestedBytes - QspiPtr->RemainingBytes) > 4)) { + if (QspiPtr->RecvBufferPtr && + ((QspiPtr->RequestedBytes - QspiPtr->RemainingBytes) > 4)) { XQspiPs_WriteReg(QspiPtr->Config.BaseAddress, XQSPIPS_TXD_00_OFFSET, XQSPIPS_DUMMY_TX_DATA); } else { @@ -1391,7 +1392,7 @@ void XQspiPs_InterruptHandler(void *InstancePtr) } if ((QspiPtr->RemainingBytes == 0) && - (QspiPtr->RequestedBytes == 0)) { + (QspiPtr->RequestedBytes == 0)) { /* * No more data to send. Disable the interrupt * and inform the upper layer software that the @@ -1399,11 +1400,11 @@ void XQspiPs_InterruptHandler(void *InstancePtr) * when another transfer is initiated. */ XQspiPs_WriteReg(QspiPtr->Config.BaseAddress, - XQSPIPS_IDR_OFFSET, - XQSPIPS_IXR_RXNEMPTY_MASK | - XQSPIPS_IXR_TXOW_MASK | - XQSPIPS_IXR_RXOVR_MASK | - XQSPIPS_IXR_TXUF_MASK); + XQSPIPS_IDR_OFFSET, + XQSPIPS_IXR_RXNEMPTY_MASK | + XQSPIPS_IXR_TXOW_MASK | + XQSPIPS_IXR_RXOVR_MASK | + XQSPIPS_IXR_TXUF_MASK); /* * If the Slave select is being manually controlled, @@ -1411,12 +1412,12 @@ void XQspiPs_InterruptHandler(void *InstancePtr) */ if (XQspiPs_IsManualChipSelect(InstancePtr)) { ConfigReg = XQspiPs_ReadReg( - QspiPtr->Config.BaseAddress, - XQSPIPS_CR_OFFSET); + QspiPtr->Config.BaseAddress, + XQSPIPS_CR_OFFSET); ConfigReg |= XQSPIPS_CR_SSCTRL_MASK; XQspiPs_WriteReg(QspiPtr->Config.BaseAddress, - XQSPIPS_CR_OFFSET, - ConfigReg); + XQSPIPS_CR_OFFSET, + ConfigReg); } /* @@ -1433,11 +1434,11 @@ void XQspiPs_InterruptHandler(void *InstancePtr) * Reset the RX FIFO threshold to one */ XQspiPs_WriteReg(QspiPtr->Config.BaseAddress, - XQSPIPS_RXWR_OFFSET, XQSPIPS_RXWR_RESET_VALUE); + XQSPIPS_RXWR_OFFSET, XQSPIPS_RXWR_RESET_VALUE); QspiPtr->StatusHandler(QspiPtr->StatusRef, - XST_SPI_TRANSFER_DONE, - QspiPtr->RequestedBytes); + XST_SPI_TRANSFER_DONE, + QspiPtr->RequestedBytes); } else { /* * Enable the TXOW interrupt. @@ -1453,12 +1454,12 @@ void XQspiPs_InterruptHandler(void *InstancePtr) */ if (XQspiPs_IsManualStart(QspiPtr)) { ConfigReg = XQspiPs_ReadReg( - QspiPtr->Config.BaseAddress, - XQSPIPS_CR_OFFSET); + QspiPtr->Config.BaseAddress, + XQSPIPS_CR_OFFSET); ConfigReg |= XQSPIPS_CR_MANSTRT_MASK; XQspiPs_WriteReg( QspiPtr->Config.BaseAddress, - XQSPIPS_CR_OFFSET, ConfigReg); + XQSPIPS_CR_OFFSET, ConfigReg); } } } @@ -1476,11 +1477,11 @@ void XQspiPs_InterruptHandler(void *InstancePtr) */ if (XQspiPs_IsManualChipSelect(InstancePtr)) { ConfigReg = XQspiPs_ReadReg( - QspiPtr->Config.BaseAddress, - XQSPIPS_CR_OFFSET); + QspiPtr->Config.BaseAddress, + XQSPIPS_CR_OFFSET); ConfigReg |= XQSPIPS_CR_SSCTRL_MASK; XQspiPs_WriteReg(QspiPtr->Config.BaseAddress, - XQSPIPS_CR_OFFSET, ConfigReg); + XQSPIPS_CR_OFFSET, ConfigReg); } /* @@ -1492,10 +1493,10 @@ void XQspiPs_InterruptHandler(void *InstancePtr) * Reset the RX FIFO threshold to one */ XQspiPs_WriteReg(QspiPtr->Config.BaseAddress, - XQSPIPS_RXWR_OFFSET, XQSPIPS_RXWR_RESET_VALUE); + XQSPIPS_RXWR_OFFSET, XQSPIPS_RXWR_RESET_VALUE); QspiPtr->StatusHandler(QspiPtr->StatusRef, - XST_SPI_RECEIVE_OVERRUN, BytesDone); + XST_SPI_RECEIVE_OVERRUN, BytesDone); } if (IntrStatus & XQSPIPS_IXR_TXUF_MASK) { @@ -1508,11 +1509,11 @@ void XQspiPs_InterruptHandler(void *InstancePtr) */ if (XQspiPs_IsManualChipSelect(InstancePtr)) { ConfigReg = XQspiPs_ReadReg( - QspiPtr->Config.BaseAddress, - XQSPIPS_CR_OFFSET); + QspiPtr->Config.BaseAddress, + XQSPIPS_CR_OFFSET); ConfigReg |= XQSPIPS_CR_SSCTRL_MASK; XQspiPs_WriteReg(QspiPtr->Config.BaseAddress, - XQSPIPS_CR_OFFSET, ConfigReg); + XQSPIPS_CR_OFFSET, ConfigReg); } /* @@ -1524,10 +1525,10 @@ void XQspiPs_InterruptHandler(void *InstancePtr) * Reset the RX FIFO threshold to one */ XQspiPs_WriteReg(QspiPtr->Config.BaseAddress, - XQSPIPS_RXWR_OFFSET, XQSPIPS_RXWR_RESET_VALUE); + XQSPIPS_RXWR_OFFSET, XQSPIPS_RXWR_RESET_VALUE); QspiPtr->StatusHandler(QspiPtr->StatusRef, - XST_SPI_TRANSMIT_UNDERRUN, BytesDone); + XST_SPI_TRANSMIT_UNDERRUN, BytesDone); } } @@ -1552,46 +1553,46 @@ static void XQspiPs_GetReadData(XQspiPs *InstancePtr, u32 Data, u8 Size) if (InstancePtr->RecvBufferPtr) { switch (Size) { - case 1: - if (InstancePtr->ShiftReadData == 1) { - *((u8 *)InstancePtr->RecvBufferPtr) = - ((Data & 0xFF000000) >> 24); - } else { - *((u8 *)InstancePtr->RecvBufferPtr) = - (Data & 0xFF); - } - InstancePtr->RecvBufferPtr += 1; - break; - case 2: - if (InstancePtr->ShiftReadData == 1) { - *((u16 *)InstancePtr->RecvBufferPtr) = - ((Data >> 16) & 0xFF00) | - ((Data >> 8) & 0xFF); - } else { - *((u16 *)InstancePtr->RecvBufferPtr) = - (Data & 0xFFFF); - } - InstancePtr->RecvBufferPtr += 2; - break; - case 3: - if (InstancePtr->ShiftReadData == 1) { - *((u16 *)InstancePtr->RecvBufferPtr) = - ((Data & 0x00FFFF00) >> 8); + case 1: + if (InstancePtr->ShiftReadData == 1) { + *((u8 *)InstancePtr->RecvBufferPtr) = + ((Data & 0xFF000000) >> 24); + } else { + *((u8 *)InstancePtr->RecvBufferPtr) = + (Data & 0xFF); + } + InstancePtr->RecvBufferPtr += 1; + break; + case 2: + if (InstancePtr->ShiftReadData == 1) { + *((u16 *)InstancePtr->RecvBufferPtr) = + ((Data >> 16) & 0xFF00) | + ((Data >> 8) & 0xFF); + } else { + *((u16 *)InstancePtr->RecvBufferPtr) = + (Data & 0xFFFF); + } InstancePtr->RecvBufferPtr += 2; - DataByte3 = ((Data & 0xFF000000) >> 24); - *((u8 *)InstancePtr->RecvBufferPtr) = DataByte3; - } else { - *((u16 *)InstancePtr->RecvBufferPtr) = - (Data & 0xFFFF); - InstancePtr->RecvBufferPtr += 2; - DataByte3 = ((Data & 0x00FF0000) >> 16); - *((u8 *)InstancePtr->RecvBufferPtr) = DataByte3; - } - InstancePtr->RecvBufferPtr += 1; - break; - default: - /* This will never execute */ - break; + break; + case 3: + if (InstancePtr->ShiftReadData == 1) { + *((u16 *)InstancePtr->RecvBufferPtr) = + ((Data & 0x00FFFF00) >> 8); + InstancePtr->RecvBufferPtr += 2; + DataByte3 = ((Data & 0xFF000000) >> 24); + *((u8 *)InstancePtr->RecvBufferPtr) = DataByte3; + } else { + *((u16 *)InstancePtr->RecvBufferPtr) = + (Data & 0xFFFF); + InstancePtr->RecvBufferPtr += 2; + DataByte3 = ((Data & 0x00FF0000) >> 16); + *((u8 *)InstancePtr->RecvBufferPtr) = DataByte3; + } + InstancePtr->RecvBufferPtr += 1; + break; + default: + /* This will never execute */ + break; } } InstancePtr->ShiftReadData = 0; diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/qspips/src/xqspips.h b/bsp_z7/ps7_cortexa9_0/libsrc/qspips/src/xqspips.h index d7bae80..11540d1 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/qspips/src/xqspips.h +++ b/bsp_z7/ps7_cortexa9_0/libsrc/qspips/src/xqspips.h @@ -1,5 +1,6 @@ /****************************************************************************** * Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (C) 2023 - 2024 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -7,7 +8,7 @@ /** * * @file xqspips.h -* @addtogroup qspips_v3_10 +* @addtogroup qspips Overview * @{ * @details * @@ -270,6 +271,8 @@ * XQspiPs_InterruptHandler() APIs to fill TX FIFO with valid * data when RX buffer is not NULL. * 3.8 akm 09/02/20 Updated the Makefile to support parallel make execution. +* 3.11 akm 07/10/23 Update the driver to support for system device-tree flow. +* 3.12 sb 02/20/24 Add missing parenthesis for macro expansions. * * * @@ -478,16 +481,26 @@ extern "C" { * requested if the status event indicates an error. */ typedef void (*XQspiPs_StatusHandler) (void *CallBackRef, u32 StatusEvent, - unsigned ByteCount); + unsigned ByteCount); /** * This typedef contains configuration information for the device. */ typedef struct { +#ifndef SDT u16 DeviceId; /**< Unique ID of device */ +#else + char *Name; +#endif u32 BaseAddress; /**< Base address of the device */ u32 InputClockHz; /**< Input clock frequency */ u8 ConnectionMode; /**< Single, Stacked and Parallel mode */ +#ifdef SDT + u32 IntrId; /**< Bits[11:0] Interrupt-id Bits[15:12] + * trigger type and level flags */ + UINTPTR IntrParent; /**< Bit[0] Interrupt parent type Bit[64/32:1] + * Parent base address */ +#endif } XQspiPs_Config; /** @@ -571,7 +584,7 @@ typedef struct { *****************************************************************************/ #define XQspiPs_SetSlaveIdle(InstancePtr, RegisterValue) \ XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + \ - XQSPIPS_SICR_OFFSET, (RegisterValue)) + XQSPIPS_SICR_OFFSET, (RegisterValue)) /****************************************************************************/ /** @@ -589,7 +602,7 @@ typedef struct { *****************************************************************************/ #define XQspiPs_GetSlaveIdle(InstancePtr) \ XQspiPs_In32(((InstancePtr)->Config.BaseAddress) + \ - XQSPIPS_SICR_OFFSET) + XQSPIPS_SICR_OFFSET) /****************************************************************************/ /** @@ -608,7 +621,7 @@ typedef struct { *****************************************************************************/ #define XQspiPs_SetTXWatermark(InstancePtr, RegisterValue) \ XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + \ - XQSPIPS_TXWR_OFFSET, (RegisterValue)) + XQSPIPS_TXWR_OFFSET, (RegisterValue)) /****************************************************************************/ /** @@ -625,7 +638,7 @@ typedef struct { * *****************************************************************************/ #define XQspiPs_GetTXWatermark(InstancePtr) \ - XQspiPs_In32((InstancePtr->Config.BaseAddress) + XQSPIPS_TXWR_OFFSET) + XQspiPs_In32(((InstancePtr)->Config.BaseAddress) + XQSPIPS_TXWR_OFFSET) /****************************************************************************/ /** @@ -644,7 +657,7 @@ typedef struct { *****************************************************************************/ #define XQspiPs_SetRXWatermark(InstancePtr, RegisterValue) \ XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + \ - XQSPIPS_RXWR_OFFSET, (RegisterValue)) + XQSPIPS_RXWR_OFFSET, (RegisterValue)) /****************************************************************************/ /** @@ -661,7 +674,7 @@ typedef struct { * *****************************************************************************/ #define XQspiPs_GetRXWatermark(InstancePtr) \ - XQspiPs_In32((InstancePtr->Config.BaseAddress) + XQSPIPS_RXWR_OFFSET) + XQspiPs_In32(((InstancePtr)->Config.BaseAddress) + XQSPIPS_RXWR_OFFSET) /****************************************************************************/ /** @@ -677,8 +690,8 @@ typedef struct { * *****************************************************************************/ #define XQspiPs_Enable(InstancePtr) \ - XQspiPs_Out32((InstancePtr->Config.BaseAddress) + XQSPIPS_ER_OFFSET, \ - XQSPIPS_ER_ENABLE_MASK) + XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + XQSPIPS_ER_OFFSET, \ + XQSPIPS_ER_ENABLE_MASK) /****************************************************************************/ /** @@ -694,7 +707,7 @@ typedef struct { * *****************************************************************************/ #define XQspiPs_Disable(InstancePtr) \ - XQspiPs_Out32((InstancePtr->Config.BaseAddress) + XQSPIPS_ER_OFFSET, 0) + XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + XQSPIPS_ER_OFFSET, 0) /****************************************************************************/ /** @@ -714,7 +727,7 @@ typedef struct { *****************************************************************************/ #define XQspiPs_SetLqspiConfigReg(InstancePtr, RegisterValue) \ XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + \ - XQSPIPS_LQSPI_CR_OFFSET, (RegisterValue)) + XQSPIPS_LQSPI_CR_OFFSET, (RegisterValue)) /****************************************************************************/ /** @@ -731,35 +744,39 @@ typedef struct { * *****************************************************************************/ #define XQspiPs_GetLqspiConfigReg(InstancePtr) \ - XQspiPs_In32((InstancePtr->Config.BaseAddress) + \ - XQSPIPS_LQSPI_CR_OFFSET) + XQspiPs_In32(((InstancePtr)->Config.BaseAddress) + \ + XQSPIPS_LQSPI_CR_OFFSET) /************************** Function Prototypes ******************************/ /* * Initialization function, implemented in xqspips_sinit.c */ +#ifndef SDT XQspiPs_Config *XQspiPs_LookupConfig(u16 DeviceId); +#else +XQspiPs_Config *XQspiPs_LookupConfig(UINTPTR BaseAddress); +#endif /* * Functions implemented in xqspips.c */ int XQspiPs_CfgInitialize(XQspiPs *InstancePtr, XQspiPs_Config *Config, - u32 EffectiveAddr); + u32 EffectiveAddr); void XQspiPs_Reset(XQspiPs *InstancePtr); void XQspiPs_Abort(XQspiPs *InstancePtr); s32 XQspiPs_Transfer(XQspiPs *InstancePtr, u8 *SendBufPtr, u8 *RecvBufPtr, - u32 ByteCount); + u32 ByteCount); s32 XQspiPs_PolledTransfer(XQspiPs *InstancePtr, u8 *SendBufPtr, - u8 *RecvBufPtr, u32 ByteCount); + u8 *RecvBufPtr, u32 ByteCount); int XQspiPs_LqspiRead(XQspiPs *InstancePtr, u8 *RecvBufPtr, - u32 Address, unsigned ByteCount); + u32 Address, unsigned ByteCount); int XQspiPs_SetSlaveSelect(XQspiPs *InstancePtr); void XQspiPs_SetStatusHandler(XQspiPs *InstancePtr, void *CallBackRef, - XQspiPs_StatusHandler FuncPtr); + XQspiPs_StatusHandler FuncPtr); void XQspiPs_InterruptHandler(void *InstancePtr); /* @@ -777,9 +794,9 @@ s32 XQspiPs_SetClkPrescaler(XQspiPs *InstancePtr, u8 Prescaler); u8 XQspiPs_GetClkPrescaler(XQspiPs *InstancePtr); int XQspiPs_SetDelays(XQspiPs *InstancePtr, u8 DelayNss, u8 DelayBtwn, - u8 DelayAfter, u8 DelayInit); + u8 DelayAfter, u8 DelayInit); void XQspiPs_GetDelays(XQspiPs *InstancePtr, u8 *DelayNss, u8 *DelayBtwn, - u8 *DelayAfter, u8 *DelayInit); + u8 *DelayAfter, u8 *DelayInit); #ifdef __cplusplus } #endif diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/qspips/src/xqspips_g.c b/bsp_z7/ps7_cortexa9_0/libsrc/qspips/src/xqspips_g.c index 31c0507..30da604 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/qspips/src/xqspips_g.c +++ b/bsp_z7/ps7_cortexa9_0/libsrc/qspips/src/xqspips_g.c @@ -1,5 +1,6 @@ /****************************************************************************** * Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -7,7 +8,7 @@ /** * * @file xqspips_g.c -* @addtogroup qspips_v3_10 +* @addtogroup qspips Overview * @{ * * This file contains a configuration table that specifies the configuration of diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/qspips/src/xqspips_hw.c b/bsp_z7/ps7_cortexa9_0/libsrc/qspips/src/xqspips_hw.c index 77af96c..ce2691f 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/qspips/src/xqspips_hw.c +++ b/bsp_z7/ps7_cortexa9_0/libsrc/qspips/src/xqspips_hw.c @@ -1,5 +1,6 @@ /****************************************************************************** * Copyright (C) 2013 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -7,7 +8,7 @@ /** * * @file xqspips_hw.c -* @addtogroup qspips_v3_10 +* @addtogroup qspips Overview * @{ * * Contains low level functions, primarily reset related. @@ -71,13 +72,13 @@ void XQspiPs_ResetHw(u32 BaseAddress) * Disable interrupts */ XQspiPs_WriteReg(BaseAddress, XQSPIPS_IDR_OFFSET, - XQSPIPS_IXR_DISABLE_ALL); + XQSPIPS_IXR_DISABLE_ALL); /* * Disable device */ XQspiPs_WriteReg(BaseAddress, XQSPIPS_ER_OFFSET, - 0); + 0); /* * De-assert slave select lines. @@ -92,14 +93,14 @@ void XQspiPs_ResetHw(u32 BaseAddress) * status bit is used next to clear the RXFIFO */ XQspiPs_WriteReg(BaseAddress, XQSPIPS_TXWR_OFFSET, - (XQSPIPS_TXWR_RESET_VALUE & XQSPIPS_TXWR_MASK)); + (XQSPIPS_TXWR_RESET_VALUE & XQSPIPS_TXWR_MASK)); XQspiPs_WriteReg(BaseAddress, XQSPIPS_RXWR_OFFSET, - (XQSPIPS_RXWR_RESET_VALUE & XQSPIPS_RXWR_MASK)); + (XQSPIPS_RXWR_RESET_VALUE & XQSPIPS_RXWR_MASK)); /* * Clear RXFIFO */ - while ((XQspiPs_ReadReg(BaseAddress,XQSPIPS_SR_OFFSET) & + while ((XQspiPs_ReadReg(BaseAddress, XQSPIPS_SR_OFFSET) & XQSPIPS_IXR_RXNEMPTY_MASK) != 0) { XQspiPs_ReadReg(BaseAddress, XQSPIPS_RXD_OFFSET); } @@ -110,7 +111,7 @@ void XQspiPs_ResetHw(u32 BaseAddress) */ XQspiPs_ReadReg(BaseAddress, XQSPIPS_SR_OFFSET); XQspiPs_WriteReg(BaseAddress, XQSPIPS_SR_OFFSET, - XQSPIPS_IXR_WR_TO_CLR_MASK); + XQSPIPS_IXR_WR_TO_CLR_MASK); /* * Write default value to configuration register @@ -124,7 +125,7 @@ void XQspiPs_ResetHw(u32 BaseAddress) * De-select linear mode */ XQspiPs_WriteReg(BaseAddress, XQSPIPS_LQSPI_CR_OFFSET, - 0x0); + 0x0); } @@ -166,33 +167,33 @@ void XQspiPs_LinearInit(u32 BaseAddress) * enable linear mode and use fast read. */ - if(XPAR_XQSPIPS_0_QSPI_MODE == XQSPIPS_CONNECTION_MODE_SINGLE){ + if (XPAR_XQSPIPS_0_QSPI_MODE == XQSPIPS_CONNECTION_MODE_SINGLE) { LinearCfg = XQSPIPS_LQSPI_CR_RST_STATE; - }else if(XPAR_XQSPIPS_0_QSPI_MODE == - XQSPIPS_CONNECTION_MODE_STACKED){ + } else if (XPAR_XQSPIPS_0_QSPI_MODE == + XQSPIPS_CONNECTION_MODE_STACKED) { LinearCfg = XQSPIPS_LQSPI_CR_RST_STATE | - XQSPIPS_LQSPI_CR_TWO_MEM_MASK; + XQSPIPS_LQSPI_CR_TWO_MEM_MASK; - }else if(XPAR_XQSPIPS_0_QSPI_MODE == - XQSPIPS_CONNECTION_MODE_PARALLEL){ + } else if (XPAR_XQSPIPS_0_QSPI_MODE == + XQSPIPS_CONNECTION_MODE_PARALLEL) { LinearCfg = XQSPIPS_LQSPI_CR_RST_STATE | - XQSPIPS_LQSPI_CR_TWO_MEM_MASK | - XQSPIPS_LQSPI_CR_SEP_BUS_MASK; + XQSPIPS_LQSPI_CR_TWO_MEM_MASK | + XQSPIPS_LQSPI_CR_SEP_BUS_MASK; } XQspiPs_WriteReg(BaseAddress, XQSPIPS_LQSPI_CR_OFFSET, - LinearCfg); + LinearCfg); /* * Enable device */ XQspiPs_WriteReg(BaseAddress, XQSPIPS_ER_OFFSET, - XQSPIPS_ER_ENABLE_MASK); + XQSPIPS_ER_ENABLE_MASK); } /** @} */ diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/qspips/src/xqspips_hw.h b/bsp_z7/ps7_cortexa9_0/libsrc/qspips/src/xqspips_hw.h index ab50675..a136a2f 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/qspips/src/xqspips_hw.h +++ b/bsp_z7/ps7_cortexa9_0/libsrc/qspips/src/xqspips_hw.h @@ -1,5 +1,6 @@ /****************************************************************************** * Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -7,7 +8,7 @@ /** * * @file xqspips_hw.h -* @addtogroup qspips_v3_10 +* @addtogroup qspips Overview * @{ * * This header file contains the identifiers and basic HW access driver @@ -117,18 +118,18 @@ extern "C" { /* Deselect the Slave select line and set the transfer size to 32 at reset */ #define XQSPIPS_CR_RESET_MASK_SET XQSPIPS_CR_IFMODE_MASK | \ - XQSPIPS_CR_SSCTRL_MASK | \ - XQSPIPS_CR_DATA_SZ_MASK | \ - XQSPIPS_CR_MSTREN_MASK | \ - XQSPIPS_CR_SSFORCE_MASK | \ - XQSPIPS_CR_HOLD_B_MASK + XQSPIPS_CR_SSCTRL_MASK | \ + XQSPIPS_CR_DATA_SZ_MASK | \ + XQSPIPS_CR_MSTREN_MASK | \ + XQSPIPS_CR_SSFORCE_MASK | \ + XQSPIPS_CR_HOLD_B_MASK #define XQSPIPS_CR_RESET_MASK_CLR XQSPIPS_CR_CPOL_MASK | \ - XQSPIPS_CR_CPHA_MASK | \ - XQSPIPS_CR_PRESC_MASK | \ - XQSPIPS_CR_MANSTRTEN_MASK | \ - XQSPIPS_CR_MANSTRT_MASK | \ - XQSPIPS_CR_ENDIAN_MASK | \ - XQSPIPS_CR_REF_CLK_MASK + XQSPIPS_CR_CPHA_MASK | \ + XQSPIPS_CR_PRESC_MASK | \ + XQSPIPS_CR_MANSTRTEN_MASK | \ + XQSPIPS_CR_MANSTRT_MASK | \ + XQSPIPS_CR_ENDIAN_MASK | \ + XQSPIPS_CR_REF_CLK_MASK /* @} */ diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/qspips/src/xqspips_options.c b/bsp_z7/ps7_cortexa9_0/libsrc/qspips/src/xqspips_options.c index 54d455d..70c4479 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/qspips/src/xqspips_options.c +++ b/bsp_z7/ps7_cortexa9_0/libsrc/qspips/src/xqspips_options.c @@ -1,5 +1,6 @@ /****************************************************************************** * Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -7,7 +8,7 @@ /** * * @file xqspips_options.c -* @addtogroup qspips_v3_10 +* @addtogroup qspips Overview * @{ * * Contains functions for the configuration of the XQspiPs driver component. @@ -116,7 +117,7 @@ s32 XQspiPs_SetOptions(XQspiPs *InstancePtr, u32 Options) Options &= ~XQSPIPS_LQSPI_MODE_OPTION; ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress, - XQSPIPS_CR_OFFSET); + XQSPIPS_CR_OFFSET); /* * Loop through the options table, turning the option on or off @@ -143,18 +144,18 @@ s32 XQspiPs_SetOptions(XQspiPs *InstancePtr, u32 Options) * Check for the LQSPI configuration options. */ ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress, - XQSPIPS_LQSPI_CR_OFFSET); + XQSPIPS_LQSPI_CR_OFFSET); if (QspiOptions & XQSPIPS_LQSPI_MODE_OPTION) { XQspiPs_WriteReg(InstancePtr->Config.BaseAddress, - XQSPIPS_LQSPI_CR_OFFSET, - XQSPIPS_LQSPI_CR_RST_STATE); + XQSPIPS_LQSPI_CR_OFFSET, + XQSPIPS_LQSPI_CR_RST_STATE); XQspiPs_SetSlaveSelect(InstancePtr); } else { ConfigReg &= ~XQSPIPS_LQSPI_CR_LINEAR_MASK; XQspiPs_WriteReg(InstancePtr->Config.BaseAddress, - XQSPIPS_LQSPI_CR_OFFSET, ConfigReg); + XQSPIPS_LQSPI_CR_OFFSET, ConfigReg); } return XST_SUCCESS; @@ -190,7 +191,7 @@ u32 XQspiPs_GetOptions(XQspiPs *InstancePtr) * Get the current options from QSPI configuration register. */ ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress, - XQSPIPS_CR_OFFSET); + XQSPIPS_CR_OFFSET); /* * Loop through the options table to grab options @@ -205,7 +206,7 @@ u32 XQspiPs_GetOptions(XQspiPs *InstancePtr) * Check for the LQSPI configuration options. */ ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress, - XQSPIPS_LQSPI_CR_OFFSET); + XQSPIPS_LQSPI_CR_OFFSET); if ((ConfigReg & XQSPIPS_LQSPI_CR_LINEAR_MASK) != 0) { OptionsFlag |= XQSPIPS_LQSPI_MODE_OPTION; @@ -257,15 +258,15 @@ s32 XQspiPs_SetClkPrescaler(XQspiPs *InstancePtr, u8 Prescaler) * results back to the configuration register. */ ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress, - XQSPIPS_CR_OFFSET); + XQSPIPS_CR_OFFSET); ConfigReg &= ~XQSPIPS_CR_PRESC_MASK; ConfigReg |= (u32) (Prescaler & XQSPIPS_CR_PRESC_MAXIMUM) << - XQSPIPS_CR_PRESC_SHIFT; + XQSPIPS_CR_PRESC_SHIFT; XQspiPs_WriteReg(InstancePtr->Config.BaseAddress, - XQSPIPS_CR_OFFSET, - ConfigReg); + XQSPIPS_CR_OFFSET, + ConfigReg); return XST_SUCCESS; } @@ -291,7 +292,7 @@ u8 XQspiPs_GetClkPrescaler(XQspiPs *InstancePtr) Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress, - XQSPIPS_CR_OFFSET); + XQSPIPS_CR_OFFSET); ConfigReg &= XQSPIPS_CR_PRESC_MASK; @@ -330,7 +331,7 @@ u8 XQspiPs_GetClkPrescaler(XQspiPs *InstancePtr) * ******************************************************************************/ int XQspiPs_SetDelays(XQspiPs *InstancePtr, u8 DelayNss, u8 DelayBtwn, - u8 DelayAfter, u8 DelayInit) + u8 DelayAfter, u8 DelayInit) { u32 DelayRegister; @@ -352,7 +353,7 @@ int XQspiPs_SetDelays(XQspiPs *InstancePtr, u8 DelayNss, u8 DelayBtwn, DelayRegister |= (u32) DelayInit; XQspiPs_WriteReg(InstancePtr->Config.BaseAddress, - XQSPIPS_DR_OFFSET, DelayRegister); + XQSPIPS_DR_OFFSET, DelayRegister); return XST_SUCCESS; } @@ -380,7 +381,7 @@ int XQspiPs_SetDelays(XQspiPs *InstancePtr, u8 DelayNss, u8 DelayBtwn, * ******************************************************************************/ void XQspiPs_GetDelays(XQspiPs *InstancePtr, u8 *DelayNss, u8 *DelayBtwn, - u8 *DelayAfter, u8 *DelayInit) + u8 *DelayAfter, u8 *DelayInit) { u32 DelayRegister; @@ -388,7 +389,7 @@ void XQspiPs_GetDelays(XQspiPs *InstancePtr, u8 *DelayNss, u8 *DelayBtwn, Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); DelayRegister = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress, - XQSPIPS_DR_OFFSET); + XQSPIPS_DR_OFFSET); *DelayInit = (u8)(DelayRegister & XQSPIPS_DR_INIT_MASK); @@ -399,6 +400,6 @@ void XQspiPs_GetDelays(XQspiPs *InstancePtr, u8 *DelayNss, u8 *DelayBtwn, XQSPIPS_DR_BTWN_SHIFT); *DelayNss = (u8)((DelayRegister & XQSPIPS_DR_NSS_MASK) >> - XQSPIPS_DR_NSS_SHIFT); + XQSPIPS_DR_NSS_SHIFT); } /** @} */ diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/qspips/src/xqspips_selftest.c b/bsp_z7/ps7_cortexa9_0/libsrc/qspips/src/xqspips_selftest.c index a35158d..c899856 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/qspips/src/xqspips_selftest.c +++ b/bsp_z7/ps7_cortexa9_0/libsrc/qspips/src/xqspips_selftest.c @@ -1,5 +1,6 @@ /****************************************************************************** * Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -7,7 +8,7 @@ /** * * @file xqspips_selftest.c -* @addtogroup qspips_v3_10 +* @addtogroup qspips Overview * @{ * * This file contains the implementation of selftest function for the QSPI @@ -86,15 +87,15 @@ int XQspiPs_SelfTest(XQspiPs *InstancePtr) * hardware out there. */ Status = XQspiPs_SetDelays(InstancePtr, DelayTestNss, DelayTestBtwn, - DelayTestAfter, DelayTestInit); + DelayTestAfter, DelayTestInit); if (Status != XST_SUCCESS) { return Status; } XQspiPs_GetDelays(InstancePtr, &DelayTestNss, &DelayTestBtwn, - &DelayTestAfter, &DelayTestInit); + &DelayTestAfter, &DelayTestInit); if ((0x5A != DelayTestNss) || (0xA5 != DelayTestBtwn) || - (0xAA != DelayTestAfter) || (0x55 != DelayTestInit)) { + (0xAA != DelayTestAfter) || (0x55 != DelayTestInit)) { return XST_REGISTER_ERROR; } diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/qspips/src/xqspips_sinit.c b/bsp_z7/ps7_cortexa9_0/libsrc/qspips/src/xqspips_sinit.c index f47fb67..3d1f32e 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/qspips/src/xqspips_sinit.c +++ b/bsp_z7/ps7_cortexa9_0/libsrc/qspips/src/xqspips_sinit.c @@ -1,5 +1,6 @@ /****************************************************************************** * Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -7,7 +8,7 @@ /** * * @file xqspips_sinit.c -* @addtogroup qspips_v3_10 +* @addtogroup qspips Overview * @{ * * The implementation of the XQspiPs component's static initialization @@ -19,6 +20,7 @@ * Ver Who Date Changes * ----- --- -------- ----------------------------------------------- * 1.00 sdm 11/25/10 First release +* 3.11 akm 07/10/23 Update the driver to support for system device-tree flow. * * ******************************************************************************/ @@ -27,7 +29,9 @@ #include "xstatus.h" #include "xqspips.h" +#ifndef SDT #include "xparameters.h" +#endif /************************** Constant Definitions *****************************/ @@ -58,6 +62,7 @@ extern XQspiPs_Config XQspiPs_ConfigTable[]; * @note None. * ******************************************************************************/ +#ifndef SDT XQspiPs_Config *XQspiPs_LookupConfig(u16 DeviceId) { XQspiPs_Config *CfgPtr = NULL; @@ -71,4 +76,20 @@ XQspiPs_Config *XQspiPs_LookupConfig(u16 DeviceId) } return CfgPtr; } +#else +XQspiPs_Config *XQspiPs_LookupConfig(UINTPTR BaseAddress) +{ + XQspiPs_Config *CfgPtr = NULL; + int Index; + + for (Index = 0U; XQspiPs_ConfigTable[Index].Name != NULL; Index++) { + if ((XQspiPs_ConfigTable[Index].BaseAddress == BaseAddress) || + !BaseAddress) { + CfgPtr = &XQspiPs_ConfigTable[Index]; + break; + } + } + return CfgPtr; +} +#endif /** @} */ diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/scugic/src/xscugic.c b/bsp_z7/ps7_cortexa9_0/libsrc/scugic/src/xscugic.c index bb74614..8016296 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/scugic/src/xscugic.c +++ b/bsp_z7/ps7_cortexa9_0/libsrc/scugic/src/xscugic.c @@ -1,6 +1,6 @@ /****************************************************************************** * Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved. -* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved. +* Copyright (C) 2022 - 2024 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -8,11 +8,11 @@ /** * * @file xscugic.c -* @addtogroup scugic Overview +* @addtogroup scugic_api SCUGIC APIs * @{ * -* Contains required functions for the XScuGic driver for the Interrupt -* Controller. See xscugic.h for a detailed description of the driver. +* The xscugic.c file contains required functions for the XScuGic driver for the Interrupt +* Controller. * * 
 * MODIFICATION HISTORY:
@@ -164,7 +164,16 @@
 *                     detecting targeted cores for specific interrupt id.
 *                     Also, DoDistributorInit has been modified to move CPU
 *                     interface specific register writes to XScuGic_CfgInitialize.
-*
+* 5.2   ml   03/02/23 Add description to fix Doxygen warnings.
+* 5.2   mus  04/26/23 Update DoDistributorInit to initialize priority of SGI and
+*                     PPI interrupts. It was missing for GICv3 based controllers.
+* 5.2   mus  07/27/23 Removed dependency on XPAR_CPU_ID by changic logic to get
+*                     CPU ID, it will be read from affinity register of processor
+*                     who is caling SCUGIC driver API's.
+* 5.2   ml   09/07/23 Typecasting with u32 to fix MISRA-C_RULE_10.3 violation.
+* 5.2   ml   09/07/23 Compared with zero to fix MISRA-C_RULE_14.4 violation.
+* 5.2   ml   09/07/23 Added comments to fix HIS COMF violations.
+* 5.2   ml   09/07/23 Include xplatform_info.h  for all processors.
 *
* ******************************************************************************/ @@ -173,11 +182,13 @@ #include "xil_types.h" #include "xil_assert.h" #include "xscugic.h" -#if defined (VERSAL_NET) + #include "xplatform_info.h" -#endif + /************************** Constant Definitions *****************************/ +#define DEFAULT_PRIORITY 0xa0a0a0a0U /**< Default value for priority_level + register */ /**************************** Type Definitions *******************************/ @@ -185,7 +196,7 @@ /***************** Macros (Inline Functions) Definitions *********************/ /************************** Variable Definitions *****************************/ -static u32 CpuId = XPAR_CPU_ID; /**< CPU Core identifier */ +static u32 CpuId; /**< CPU Core identifier */ /************************** Function Prototypes ******************************/ @@ -201,16 +212,15 @@ static void StubHandler(void *CallBackRef); * - All interrupt sources are disabled * - Enable the distributor * -* @param InstancePtr is a pointer to the XScuGic instance. +* @param InstancePtr Pointer to the XScuGic instance. * * @return None * -* @note None. * ******************************************************************************/ static void DoDistributorInit(const XScuGic *InstancePtr) { - u32 Int_Id; + u32 Int_Id, Offset = 0; #if defined (GICv3) u32 Temp; @@ -239,20 +249,22 @@ static void DoDistributorInit(const XScuGic *InstancePtr) * Only write to the SPI interrupts, so start at 32 */ for (Int_Id = 32U; Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS; - Int_Id = Int_Id+16U) { + Int_Id = Int_Id + 16U) { /* * Each INT_ID uses two bits, or 16 INT_ID per register * Set them all to be level sensitive, active HIGH. */ XScuGic_DistWriteReg(InstancePtr, - XSCUGIC_INT_CFG_OFFSET_CALC(Int_Id), - 0U); + XSCUGIC_INT_CFG_OFFSET_CALC(Int_Id), + 0U); } +#if defined (GICv3) + Offset = 32U; +#endif -#define DEFAULT_PRIORITY 0xa0a0a0a0U - for (Int_Id = 0U; Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS; - Int_Id = Int_Id+4U) { + for (Int_Id = Offset; Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS; + Int_Id = Int_Id + 4U) { /* * 2. The priority using int the priority_level register * The priority_level and spi_target registers use one byte per @@ -260,32 +272,45 @@ static void DoDistributorInit(const XScuGic *InstancePtr) * Write a default value that can be changed elsewhere. */ XScuGic_DistWriteReg(InstancePtr, - XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id), - DEFAULT_PRIORITY); + XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id), + DEFAULT_PRIORITY); } #if defined (GICv3) - for (Int_Id = 0U; Int_IdIsReady != XIL_COMPONENT_IS_READY) { + if (InstancePtr->IsReady != XIL_COMPONENT_IS_READY) { InstancePtr->IsReady = 0U; InstancePtr->Config = ConfigPtr; - #if defined(ARMR52) +#if defined(ARMR52) /* Read Distributor base address through IMP_CBAR register */ ConfigPtr->DistBaseAddress = mfcp(XREG_IMP_CBAR); - #endif +#endif for (Int_Id = 0U; Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS; - Int_Id++) { + Int_Id++) { /* * Initialize the handler to point to a stub to handle an * interrupt which has not been connected to a handler @@ -449,41 +477,41 @@ s32 XScuGic_CfgInitialize(XScuGic *InstancePtr, * unhandled interrupts can be tracked. */ if ((InstancePtr->Config->HandlerTable[Int_Id].Handler - == (Xil_InterruptHandler)NULL)) { + == (Xil_InterruptHandler)NULL)) { InstancePtr->Config->HandlerTable[Int_Id].Handler - = (Xil_InterruptHandler)StubHandler; + = (Xil_InterruptHandler)StubHandler; } InstancePtr->Config->HandlerTable[Int_Id].CallBackRef = - InstancePtr; + InstancePtr; } #if defined (GICv3) - u32 Waker_State; + u32 Waker_State; - InstancePtr->RedistBaseAddr = XScuGic_GetRedistBaseAddr(); + InstancePtr->RedistBaseAddr = XScuGic_GetRedistBaseAddr(); - #if defined (GIC600) - XScuGic_ReDistWriteReg(InstancePtr,XSCUGIC_RDIST_PWRR_OFFSET, - (XScuGic_ReDistReadReg(InstancePtr, XSCUGIC_RDIST_PWRR_OFFSET) & - (~XSCUGIC_RDIST_PWRR_RDPD_MASK))); - #endif +#if defined (GIC600) + XScuGic_ReDistWriteReg(InstancePtr, XSCUGIC_RDIST_PWRR_OFFSET, + (XScuGic_ReDistReadReg(InstancePtr, XSCUGIC_RDIST_PWRR_OFFSET) & + (~XSCUGIC_RDIST_PWRR_RDPD_MASK))); +#endif - Waker_State = XScuGic_ReDistReadReg(InstancePtr,XSCUGIC_RDIST_WAKER_OFFSET); - XScuGic_ReDistWriteReg(InstancePtr,XSCUGIC_RDIST_WAKER_OFFSET, - Waker_State & (~ XSCUGIC_RDIST_WAKER_LOW_POWER_STATE_MASK)); + Waker_State = XScuGic_ReDistReadReg(InstancePtr, XSCUGIC_RDIST_WAKER_OFFSET); + XScuGic_ReDistWriteReg(InstancePtr, XSCUGIC_RDIST_WAKER_OFFSET, + Waker_State & (~ XSCUGIC_RDIST_WAKER_LOW_POWER_STATE_MASK)); /* Enable system reg interface through ICC_SRE_EL1 */ - #if EL3 - XScuGic_Enable_SystemReg_CPU_Interface_EL3(); - #endif - XScuGic_Enable_SystemReg_CPU_Interface_EL1(); +#if EL3 + XScuGic_Enable_SystemReg_CPU_Interface_EL3(); +#endif + XScuGic_Enable_SystemReg_CPU_Interface_EL1(); isb(); #endif XScuGic_Stop(InstancePtr); DistributorInit(InstancePtr); #if defined (GICv3) XScuGic_Enable_Group1_Interrupts(); - #if defined (ARMR52) || (defined (__aarch64__) && (EL1_NONSECURE == 0)) +#if defined (ARMR52) || (defined (__aarch64__) && (EL1_NONSECURE == 0)) XScuGic_Enable_Group0_Interrupts(); - #endif +#endif XScuGic_set_priority_filter(0xff); #else CPUInitialize(InstancePtr); @@ -502,28 +530,26 @@ s32 XScuGic_CfgInitialize(XScuGic *InstancePtr, * argument provided in this call as the Callbackref is used as the argument * for the handler when it is called. * -* @param InstancePtr is a pointer to the XScuGic instance. +* @param InstancePtr Pointer to the XScuGic instance. * @param Int_Id contains the ID of the interrupt source and should be * in the range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1 -* @param Handler to the handler for that interrupt. -* @param CallBackRef is the callback reference, usually the instance -* pointer of the connecting driver. +* @param Handler Handler for interrupt. +* @param CallBackRef Instance pointer of the connecting driver. * * @return * * - XST_SUCCESS if the handler was connected correctly. * -* @note * * WARNING: The handler provided as an argument will overwrite any handler * that was previously connected. * ****************************************************************************/ s32 XScuGic_Connect(XScuGic *InstancePtr, u32 Int_Id, - Xil_InterruptHandler Handler, void *CallBackRef) + Xil_InterruptHandler Handler, void *CallBackRef) { /* - * Assert the arguments + * Validate the input arguments */ Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS); @@ -535,8 +561,14 @@ s32 XScuGic_Connect(XScuGic *InstancePtr, u32 Int_Id, * handler */ InstancePtr->Config->HandlerTable[Int_Id].Handler = (Xil_InterruptHandler)Handler; + + /* + * The Int_Id is used as an index into the table to select the proper + * CallBackRef + */ InstancePtr->Config->HandlerTable[Int_Id].CallBackRef = CallBackRef; + /* Return statement */ return XST_SUCCESS; } @@ -547,13 +579,12 @@ s32 XScuGic_Connect(XScuGic *InstancePtr, u32 Int_Id, * location pointed at by the Int_Id. This effectively disconnects that interrupt * source from any handler. The interrupt is disabled also. * -* @param InstancePtr is a pointer to the XScuGic instance to be worked on. -* @param Int_Id contains the ID of the interrupt source and should +* @param InstancePtr Pointer to the XScuGic instance to be worked on. +* @param Int_Id Contains the ID of the interrupt source and should * be in the range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1 * * @return None. * -* @note None. * ****************************************************************************/ void XScuGic_Disconnect(XScuGic *InstancePtr, u32 Int_Id) @@ -587,7 +618,7 @@ void XScuGic_Disconnect(XScuGic *InstancePtr, u32 Int_Id) * modifying the other interrupt ids */ XScuGic_DistWriteReg(InstancePtr, (u32)XSCUGIC_DISABLE_OFFSET + - ((Int_Id / 32U) * 4U), Mask); + ((Int_Id / 32U) * 4U), Mask); /* * Release the lock previously taken. This macro ensures that the lock @@ -611,13 +642,12 @@ void XScuGic_Disconnect(XScuGic *InstancePtr, u32 Int_Id) * called. * This API also maps the interrupt to the requesting CPU. * -* @param InstancePtr is a pointer to the XScuGic instance. -* @param Int_Id contains the ID of the interrupt source and should be +* @param InstancePtr Pointer to the XScuGic instance. +* @param Int_Id Contains the ID of the interrupt source and should be * in the range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1 * * @return None. * -* @note None. * ****************************************************************************/ void XScuGic_Enable(XScuGic *InstancePtr, u32 Int_Id) @@ -641,20 +671,20 @@ void XScuGic_Enable(XScuGic *InstancePtr, u32 Int_Id) Int_Id &= 0x1f; Int_Id = 1 << Int_Id; - Temp = XScuGic_ReDistSGIPPIReadReg(InstancePtr,XSCUGIC_RDIST_ISENABLE_OFFSET); + Temp = XScuGic_ReDistSGIPPIReadReg(InstancePtr, XSCUGIC_RDIST_ISENABLE_OFFSET); Temp |= Int_Id; - XScuGic_ReDistSGIPPIWriteReg(InstancePtr,XSCUGIC_RDIST_ISENABLE_OFFSET,Temp); + XScuGic_ReDistSGIPPIWriteReg(InstancePtr, XSCUGIC_RDIST_ISENABLE_OFFSET, Temp); return; } #endif - #if defined (VERSAL_NET) - #if defined (ARMR52) - Cpu_Identifier = XGetCoreId(); - #else - Cpu_Identifier = XGetCoreId(); - Cpu_Identifier |= (XGetClusterId() << XSCUGIC_CLUSTERID_SHIFT); - #endif - #endif +#if defined (VERSAL_NET) +#if defined (ARMR52) + Cpu_Identifier = XGetCoreId(); +#else + Cpu_Identifier = XGetCoreId(); + Cpu_Identifier |= (XGetClusterId() << XSCUGIC_CLUSTERID_SHIFT); +#endif +#endif XScuGic_InterruptMaptoCpu(InstancePtr, Cpu_Identifier, Int_Id); /* * Call spinlock to protect multiple applications running at separate @@ -673,7 +703,7 @@ void XScuGic_Enable(XScuGic *InstancePtr, u32 Int_Id) * corresponding bit in the Enable Set register. */ XScuGic_DistWriteReg(InstancePtr, (u32)XSCUGIC_ENABLE_SET_OFFSET + - ((Int_Id / 32U) * 4U), Mask); + ((Int_Id / 32U) * 4U), Mask); /* * Release the lock previously taken. This macro ensures that the lock @@ -691,13 +721,12 @@ void XScuGic_Enable(XScuGic *InstancePtr, u32 Int_Id) * Int_Id, but will not cause an interrupt. * This API also unmaps the interrupt for the requesting CPU. * -* @param InstancePtr is a pointer to the XScuGic instance. -* @param Int_Id contains the ID of the interrupt source and should be +* @param InstancePtr Pointer to the XScuGic instance. +* @param Int_Id Contains the ID of the interrupt source and should be * in the range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1 * * @return None. * -* @note None. * ****************************************************************************/ void XScuGic_Disable(XScuGic *InstancePtr, u32 Int_Id) @@ -721,20 +750,20 @@ void XScuGic_Disable(XScuGic *InstancePtr, u32 Int_Id) Int_Id &= 0x1f; Int_Id = 1 << Int_Id; - Temp = XScuGic_ReDistSGIPPIReadReg(InstancePtr,XSCUGIC_RDIST_ISENABLE_OFFSET); + Temp = XScuGic_ReDistSGIPPIReadReg(InstancePtr, XSCUGIC_RDIST_ISENABLE_OFFSET); Temp &= ~Int_Id; - XScuGic_ReDistSGIPPIWriteReg(InstancePtr,XSCUGIC_RDIST_ISENABLE_OFFSET,Temp); + XScuGic_ReDistSGIPPIWriteReg(InstancePtr, XSCUGIC_RDIST_ISENABLE_OFFSET, Temp); return; } #endif - #if defined (VERSAL_NET) - #if defined (ARMR52) - Cpu_Identifier = XGetCoreId(); - #else - Cpu_Identifier = XGetCoreId(); - Cpu_Identifier |= (XGetClusterId() << XSCUGIC_CLUSTERID_SHIFT); - #endif - #endif +#if defined (VERSAL_NET) +#if defined (ARMR52) + Cpu_Identifier = XGetCoreId(); +#else + Cpu_Identifier = XGetCoreId(); + Cpu_Identifier |= (XGetClusterId() << XSCUGIC_CLUSTERID_SHIFT); +#endif +#endif XScuGic_InterruptUnmapFromCpu(InstancePtr, Cpu_Identifier, Int_Id); @@ -756,7 +785,7 @@ void XScuGic_Disable(XScuGic *InstancePtr, u32 Int_Id) * corresponding bit in the IDR. */ XScuGic_DistWriteReg(InstancePtr, (u32)XSCUGIC_DISABLE_OFFSET + - ((Int_Id / 32U) * 4U), Mask); + ((Int_Id / 32U) * 4U), Mask); /* * Release the lock previously taken. This macro ensures that the lock @@ -768,16 +797,16 @@ void XScuGic_Disable(XScuGic *InstancePtr, u32 Int_Id) /*****************************************************************************/ /** * -* Allows software to simulate an interrupt in the interrupt controller. This +* Allows software to simulate an interrupt in the interrupt controller. This * function will only be successful when the interrupt controller has been -* started in simulation mode. A simulated interrupt allows the interrupt +* started in simulation mode. A simulated interrupt allows the interrupt * controller to be tested without any device to drive an interrupt input * signal into it. * -* @param InstancePtr is a pointer to the XScuGic instance. -* @param Int_Id is the software interrupt ID to simulate an interrupt. -* @param Cpu_Identifier is the list of CPUs to send the interrupt. -* For VERSAL_NET bits 0-7 specifies core id to send the interrupt. +* @param InstancePtr Pointer to the XScuGic instance. +* @param Int_Id Software interrupt ID to simulate an interrupt. +* @param Cpu_Identifier List of CPUs to send the interrupt. +* For VERSAL_NET bits 0-7 specifies core ID to send the interrupt. * bits 8-15 specifies the cluster id. * * @return @@ -785,7 +814,6 @@ void XScuGic_Disable(XScuGic *InstancePtr, u32 Int_Id) * XST_SUCCESS if successful, or XST_FAILURE if the interrupt could not be * simulated * -* @note None. * ******************************************************************************/ s32 XScuGic_SoftwareIntr(XScuGic *InstancePtr, u32 Int_Id, u32 Cpu_Identifier) @@ -807,23 +835,23 @@ s32 XScuGic_SoftwareIntr(XScuGic *InstancePtr, u32 Int_Id, u32 Cpu_Identifier) #endif #if defined (GICv3) - #if defined (VERSAL_NET) - #if defined (ARMR52) +#if defined (VERSAL_NET) +#if defined (ARMR52) Mask = ((Cpu_Identifier & XSCUGIC_CLUSTERID_MASK) >> XSCUGIC_CLUSTERID_SHIFT); Mask = ( Mask << XSCUGIC_SGI1R_AFFINITY1_SHIFT); Mask |= (Cpu_Identifier & XSCUGIC_COREID_MASK); - #else +#else Mask = ((Cpu_Identifier & XSCUGIC_CLUSTERID_MASK) >> XSCUGIC_CLUSTERID_SHIFT); Mask = ( Mask << XSCUGIC_SGI1R_AFFINITY2_SHIFT); Mask |= ((Cpu_Identifier & XSCUGIC_COREID_MASK) << XSCUGIC_SGI1R_AFFINITY1_SHIFT); Mask |= 0x1; - #endif +#endif Mask |= (Int_Id << XSCUGIC_SGIR_EL1_INITID_SHIFT); - #else +#else Mask = (Cpu_Identifier | (Int_Id << XSCUGIC_SGIR_EL1_INITID_SHIFT)); - #endif +#endif #if EL3 XScuGic_WriteICC_SGI0R_EL1(Mask); #else @@ -845,7 +873,7 @@ s32 XScuGic_SoftwareIntr(XScuGic *InstancePtr, u32 Int_Id, u32 Cpu_Identifier) * Use the target list for the Cpu ID. */ Mask = ((Cpu_Identifier << 16U) | Int_Id) & - (XSCUGIC_SFI_TRIG_CPU_MASK | XSCUGIC_SFI_TRIG_INTID_MASK); + (XSCUGIC_SFI_TRIG_CPU_MASK | XSCUGIC_SFI_TRIG_INTID_MASK); /* * Write to the Software interrupt trigger register. Use the appropriate @@ -870,11 +898,10 @@ s32 XScuGic_SoftwareIntr(XScuGic *InstancePtr, u32 Int_Id, u32 Cpu_Identifier) * A stub for the asynchronous callback. The stub is here in case the upper * layers forget to set the handler. * -* @param CallBackRef is a pointer to the upper layer callback reference +* @param CallBackRef Pointer to the upper layer callback reference. * * @return None. * -* @note None. * ******************************************************************************/ static void StubHandler(void *CallBackRef) @@ -894,13 +921,13 @@ static void StubHandler(void *CallBackRef) /** * Sets the interrupt priority and trigger type for the specificd IRQ source. * -* @param InstancePtr is a pointer to the instance to be worked on. -* @param Int_Id is the IRQ source number to modify -* @param Priority is the new priority for the IRQ source. 0 is highest +* @param InstancePtr Pointer to the instance to be worked on. +* @param Int_Id IRQ source number to modify. +* @param Priority New priority for the IRQ source. 0 is highest * priority, 0xF8(248) is lowest. There are 32 priority levels * supported with a step of 8. Hence the supported priorities are * 0, 8, 16, 32, 40 ..., 248. -* @param Trigger is the new trigger type for the IRQ source. +* @param Trigger New trigger type for the IRQ source. * Each bit pair describes the configuration for an INT_ID. * SFI Read Only b10 always * PPI Read Only depending on how the PPIs are configured. @@ -912,11 +939,10 @@ static void StubHandler(void *CallBackRef) * * @return None. * -* @note None. * *****************************************************************************/ void XScuGic_SetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id, - u8 Priority, u8 Trigger) + u8 Priority, u8 Trigger) { u32 RegValue; #if defined (GICv3) @@ -932,13 +958,12 @@ void XScuGic_SetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id, Xil_AssertVoid(Trigger <= (u8)XSCUGIC_INT_CFG_MASK); Xil_AssertVoid(LocalPriority <= (u8)XSCUGIC_MAX_INTR_PRIO_VAL); #if defined (GICv3) - if (Int_Id < XSCUGIC_SPI_INT_ID_START ) - { - XScuGic_ReDistSGIPPIWriteReg(InstancePtr,XSCUGIC_RDIST_INT_PRIORITY_OFFSET_CALC(Int_Id),Priority); - Temp = XScuGic_ReDistSGIPPIReadReg(InstancePtr,XSCUGIC_RDIST_INT_CONFIG_OFFSET_CALC(Int_Id)); + if (Int_Id < XSCUGIC_SPI_INT_ID_START ) { + XScuGic_ReDistSGIPPIWriteReg(InstancePtr, XSCUGIC_RDIST_INT_PRIORITY_OFFSET_CALC(Int_Id), Priority); + Temp = XScuGic_ReDistSGIPPIReadReg(InstancePtr, XSCUGIC_RDIST_INT_CONFIG_OFFSET_CALC(Int_Id)); Index = XScuGic_Get_Rdist_Int_Trigger_Index(Int_Id); Temp |= (Trigger << Index); - XScuGic_ReDistSGIPPIWriteReg(InstancePtr,XSCUGIC_RDIST_INT_CONFIG_OFFSET_CALC(Int_Id),Temp); + XScuGic_ReDistSGIPPIWriteReg(InstancePtr, XSCUGIC_RDIST_INT_CONFIG_OFFSET_CALC(Int_Id), Temp); return; } #endif @@ -954,7 +979,7 @@ void XScuGic_SetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id, * Determine the register to write to using the Int_Id. */ RegValue = XScuGic_DistReadReg(InstancePtr, - XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id)); + XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id)); /* * The priority bits are Bits 7 to 3 in GIC Priority Register. This @@ -967,37 +992,37 @@ void XScuGic_SetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id, * Shift and Mask the correct bits for the priority and trigger in the * register */ - RegValue &= ~((u32)XSCUGIC_PRIORITY_MASK << ((Int_Id%4U)*8U)); - RegValue |= (u32)LocalPriority << ((Int_Id%4U)*8U); + RegValue &= ~((u32)XSCUGIC_PRIORITY_MASK << ((Int_Id % 4U) * 8U)); + RegValue |= (u32)LocalPriority << ((Int_Id % 4U) * 8U); /* * Write the value back to the register. */ XScuGic_DistWriteReg(InstancePtr, XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id), - RegValue); + RegValue); /* * Determine the register to write to using the Int_Id. */ RegValue = XScuGic_DistReadReg(InstancePtr, - XSCUGIC_INT_CFG_OFFSET_CALC(Int_Id)); + XSCUGIC_INT_CFG_OFFSET_CALC(Int_Id)); /* * Shift and Mask the correct bits for the priority and trigger in the * register */ - RegValue &= ~((u32)XSCUGIC_INT_CFG_MASK << ((Int_Id%16U)*2U)); - RegValue |= (u32)Trigger << ((Int_Id%16U)*2U); + RegValue &= ~((u32)XSCUGIC_INT_CFG_MASK << ((Int_Id % 16U) * 2U)); + RegValue |= (u32)Trigger << ((Int_Id % 16U) * 2U); /* * Write the value back to the register. */ XScuGic_DistWriteReg(InstancePtr, XSCUGIC_INT_CFG_OFFSET_CALC(Int_Id), - RegValue); - /* - * Release the lock previously taken. This macro ensures that the lock - * is given only if spinlock mechanism is enabled by the user. - */ + RegValue); + /* + * Release the lock previously taken. This macro ensures that the lock + * is given only if spinlock mechanism is enabled by the user. + */ XIL_SPINUNLOCK(); } @@ -1005,23 +1030,25 @@ void XScuGic_SetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id, /** * Gets the interrupt priority and trigger type for the specificd IRQ source. * -* @param InstancePtr is a pointer to the instance to be worked on. -* @param Int_Id is the IRQ source number to modify -* @param Priority is a pointer to the value of the priority of the IRQ -* source. This is a return value. -* @param Trigger is pointer to the value of the trigger of the IRQ +* @param InstancePtr Pointer to the instance to be worked on. +* @param Int_Id IRQ source number to modify. +* @param Priority Pointer to the value of the priority of the IRQ * source. This is a return value. +* @param Trigger Pointer to the value of the trigger of the IRQ +* source. * -* @return None. +* @return Pointer to the value of the trigger of the IRQ +* source. * -* @note None * *****************************************************************************/ void XScuGic_GetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id, - u8 *Priority, u8 *Trigger) + u8 *Priority, u8 *Trigger) { u32 RegValue; - + /* + * Validate the input arguments + */ Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS); @@ -1029,11 +1056,10 @@ void XScuGic_GetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id, Xil_AssertVoid(Trigger != NULL); #if defined (GICv3) - if (Int_Id < XSCUGIC_SPI_INT_ID_START ) - { - *Priority = XScuGic_ReDistSGIPPIReadReg(InstancePtr,XSCUGIC_RDIST_INT_PRIORITY_OFFSET_CALC(Int_Id)); - RegValue = XScuGic_ReDistSGIPPIReadReg(InstancePtr,XSCUGIC_RDIST_INT_CONFIG_OFFSET_CALC(Int_Id)); - RegValue = RegValue >> ((Int_Id%16U)*2U); + if (Int_Id < XSCUGIC_SPI_INT_ID_START ) { + *Priority = XScuGic_ReDistSGIPPIReadReg(InstancePtr, XSCUGIC_RDIST_INT_PRIORITY_OFFSET_CALC(Int_Id)); + RegValue = XScuGic_ReDistSGIPPIReadReg(InstancePtr, XSCUGIC_RDIST_INT_CONFIG_OFFSET_CALC(Int_Id)); + RegValue = RegValue >> ((Int_Id % 16U) * 2U); *Trigger = (u8)(RegValue & XSCUGIC_INT_CFG_MASK); return; } @@ -1042,113 +1068,124 @@ void XScuGic_GetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id, * Determine the register to read to using the Int_Id. */ RegValue = XScuGic_DistReadReg(InstancePtr, - XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id)); + XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id)); /* * Shift and Mask the correct bits for the priority and trigger in the * register */ - RegValue = RegValue >> ((Int_Id%4U)*8U); + RegValue = RegValue >> ((Int_Id % 4U) * 8U); + /* + * Priority is expected to hold a value where only + * the bits set in both RegValue and XSCUGIC_PRIORITY_MASK + * are preserved. + */ *Priority = (u8)(RegValue & XSCUGIC_PRIORITY_MASK); /* * Determine the register to read to using the Int_Id. */ RegValue = XScuGic_DistReadReg(InstancePtr, - XSCUGIC_INT_CFG_OFFSET_CALC(Int_Id)); + XSCUGIC_INT_CFG_OFFSET_CALC(Int_Id)); /* * Shift and Mask the correct bits for the priority and trigger in the * register */ - RegValue = RegValue >> ((Int_Id%16U)*2U); + RegValue = RegValue >> ((Int_Id % 16U) * 2U); + /* + * Trigger is expected to hold a value where only + * the bits set in both RegValue and XSCUGIC_INT_CFG_MASK + * are preserved. + */ *Trigger = (u8)(RegValue & XSCUGIC_INT_CFG_MASK); } /****************************************************************************/ /** -* Sets the target CPU for the interrupt of a peripheral +* Sets the target CPU for the interrupt of a peripheral. * -* @param InstancePtr is a pointer to the instance to be worked on. -* @param Cpu_Identifier is a CPU number for which the interrupt has to be targeted +* @param InstancePtr Pointer to the instance to be worked on. +* @param Cpu_Identifier CPU number for which the interrupt has to be targeted * For VERSAL_NET APU: 0 t0 3 bits sepcifies core id and 4 to 7 bits specifies * cluster id of the targeted core. -* @param Int_Id is the IRQ source number to modify +* @param Int_Id IRQ source number to modify. * * @return None. * -* @note None * *****************************************************************************/ void XScuGic_InterruptMaptoCpu(XScuGic *InstancePtr, u8 Cpu_Identifier, u32 Int_Id) { u32 RegValue; -if (Int_Id >= XSCUGIC_SPI_INT_ID_START) { + if (Int_Id >= XSCUGIC_SPI_INT_ID_START) { #if defined (GICv3) - Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr != NULL); - #if defined (VERSAL_NET) - #if defined (ARMR52) - RegValue = (Cpu_Identifier & XSCUGIC_COREID_MASK); - #else - RegValue = ((Cpu_Identifier & XSCUGIC_CLUSTERID_MASK) >> XSCUGIC_CLUSTERID_SHIFT); - RegValue = (RegValue << XSCUGIC_IROUTER_AFFINITY2_SHIFT); - RegValue |= ((Cpu_Identifier & XSCUGIC_COREID_MASK) << XSCUGIC_IROUTER_AFFINITY1_SHIFT); - #endif - #else - RegValue = XScuGic_DistReadReg(InstancePtr, - XSCUGIC_IROUTER_OFFSET_CALC(Int_Id)); - RegValue |= Cpu_Identifier; - #endif - - XScuGic_DistWriteReg(InstancePtr, XSCUGIC_IROUTER_OFFSET_CALC(Int_Id), - RegValue); +#if defined (VERSAL_NET) +#if defined (ARMR52) + RegValue = (Cpu_Identifier & XSCUGIC_COREID_MASK); #else - u8 Cpu_CoreId; - u32 Offset; - Xil_AssertVoid(InstancePtr != NULL); - - /* - * Call spinlock to protect multiple applications running at separate - * CPUs to write to the same register. This macro also ensures that - * the spinlock mechanism is used only if spinlock is enabled by - * user. - */ - XIL_SPINLOCK(); - - RegValue = XScuGic_DistReadReg(InstancePtr, - XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id)); - - Offset = (Int_Id & 0x3U); - Cpu_CoreId = (0x1U << Cpu_Identifier); - - RegValue |= (u32)(Cpu_CoreId) << (Offset*8U); - XScuGic_DistWriteReg(InstancePtr, - XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id), - RegValue); - /* - * Release the lock previously taken. This macro ensures that the lock - * is given only if spinlock mechanism is enabled by the user. - */ - XIL_SPINUNLOCK(); + RegValue = ((Cpu_Identifier & XSCUGIC_CLUSTERID_MASK) >> XSCUGIC_CLUSTERID_SHIFT); + RegValue = (RegValue << XSCUGIC_IROUTER_AFFINITY2_SHIFT); + RegValue |= ((Cpu_Identifier & XSCUGIC_COREID_MASK) << XSCUGIC_IROUTER_AFFINITY1_SHIFT); #endif -} +#else + RegValue = XScuGic_DistReadReg(InstancePtr, + XSCUGIC_IROUTER_OFFSET_CALC(Int_Id)); + RegValue |= Cpu_Identifier; +#endif + + XScuGic_DistWriteReg(InstancePtr, XSCUGIC_IROUTER_OFFSET_CALC(Int_Id), + RegValue); +#else + u8 Cpu_CoreId; + u32 Offset; + Xil_AssertVoid(InstancePtr != NULL); + + /* + * Call spinlock to protect multiple applications running at separate + * CPUs to write to the same register. This macro also ensures that + * the spinlock mechanism is used only if spinlock is enabled by + * user. + */ + XIL_SPINLOCK(); + + /* + * Determine the register to read to using the Int_Id. + */ + RegValue = XScuGic_DistReadReg(InstancePtr, + XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id)); + + Offset = (Int_Id & 0x3U); + Cpu_CoreId = (0x1U << Cpu_Identifier); + + RegValue |= (u32)(Cpu_CoreId) << (Offset * 8U); + XScuGic_DistWriteReg(InstancePtr, + XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id), + RegValue); + /* + * Release the lock previously taken. This macro ensures that the lock + * is given only if spinlock mechanism is enabled by the user. + */ + XIL_SPINUNLOCK(); +#endif + } } /****************************************************************************/ /** -* Unmaps specific SPI interrupt from the target CPU +* Unmaps specific SPI interrupt from the target CPU. * -* @param InstancePtr is a pointer to the instance to be worked on. -* @param Cpu_Identifier is a CPU number from which the interrupt has to be -* unmapped +* @param InstancePtr Pointer to the instance to be worked on. +* @param Cpu_Identifier CPU number from which the interrupt has to be +* unmapped. * For VERSAL_NET APU: 0 t0 3 bits sepcifies core id and 4 to 7 * bits specifies cluster id of the targeted core. -* @param Int_Id is the IRQ source number to modify +* @param Int_Id IRQ source number to modify * * @return None. * -* @note None * *****************************************************************************/ void XScuGic_InterruptUnmapFromCpu(XScuGic *InstancePtr, u8 Cpu_Identifier, u32 Int_Id) @@ -1158,71 +1195,77 @@ void XScuGic_InterruptUnmapFromCpu(XScuGic *InstancePtr, u8 Cpu_Identifier, u32 u32 Temp; #endif -if (Int_Id >= XSCUGIC_SPI_INT_ID_START) { + if (Int_Id >= XSCUGIC_SPI_INT_ID_START) { #if defined (GICv3) - Xil_AssertVoid(InstancePtr != NULL); + /* + * Validate the input arguments + */ + Xil_AssertVoid(InstancePtr != NULL); - RegValue = XScuGic_DistReadReg(InstancePtr, - XSCUGIC_IROUTER_OFFSET_CALC(Int_Id)); + RegValue = XScuGic_DistReadReg(InstancePtr, + XSCUGIC_IROUTER_OFFSET_CALC(Int_Id)); - #if defined (VERSAL_NET) - #if defined (ARMR52) - Temp = (Cpu_Identifier & XSCUGIC_COREID_MASK); - #else - Temp = ((Cpu_Identifier & XSCUGIC_CLUSTERID_MASK) >> XSCUGIC_CLUSTERID_SHIFT); - Temp = (Temp << XSCUGIC_IROUTER_AFFINITY2_SHIFT); - Temp |= ((Cpu_Identifier & XSCUGIC_COREID_MASK) << XSCUGIC_IROUTER_AFFINITY1_SHIFT); - #endif - RegValue &= ~Temp; - #else - RegValue &= ~Cpu_Identifier; - #endif - - XScuGic_DistWriteReg(InstancePtr, XSCUGIC_IROUTER_OFFSET_CALC(Int_Id), - RegValue); +#if defined (VERSAL_NET) +#if defined (ARMR52) + Temp = (Cpu_Identifier & XSCUGIC_COREID_MASK); #else - u32 Cpu_CoreId; - u32 Offset; - Xil_AssertVoid(InstancePtr != NULL); - - /* - * Call spinlock to protect multiple applications running at separate - * CPUs to write to the same register. This macro also ensures that - * the spinlock mechanism is used only if spinlock is enabled by - * user. - */ - XIL_SPINLOCK(); - - RegValue = XScuGic_DistReadReg(InstancePtr, - XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id)); - - Offset = (Int_Id & 0x3U); - Cpu_CoreId = ((u32)0x1U << Cpu_Identifier); - - RegValue &= ~(Cpu_CoreId << (Offset*8U)); - XScuGic_DistWriteReg(InstancePtr, - XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id), - RegValue); - - /* - * Release the lock previously taken. This macro ensures that the lock - * is given only if spinlock mechanism is enabled by the user. - */ - XIL_SPINUNLOCK(); + Temp = ((Cpu_Identifier & XSCUGIC_CLUSTERID_MASK) >> XSCUGIC_CLUSTERID_SHIFT); + Temp = (Temp << XSCUGIC_IROUTER_AFFINITY2_SHIFT); + Temp |= ((Cpu_Identifier & XSCUGIC_COREID_MASK) << XSCUGIC_IROUTER_AFFINITY1_SHIFT); #endif -} + RegValue &= ~Temp; +#else + RegValue &= ~Cpu_Identifier; +#endif + + XScuGic_DistWriteReg(InstancePtr, XSCUGIC_IROUTER_OFFSET_CALC(Int_Id), + RegValue); +#else + u32 Cpu_CoreId; + u32 Offset; + + /* + * Validate the input arguments + */ + Xil_AssertVoid(InstancePtr != NULL); + + /* + * Call spinlock to protect multiple applications running at separate + * CPUs to write to the same register. This macro also ensures that + * the spinlock mechanism is used only if spinlock is enabled by + * user. + */ + XIL_SPINLOCK(); + + RegValue = XScuGic_DistReadReg(InstancePtr, + XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id)); + + Offset = (Int_Id & 0x3U); + Cpu_CoreId = ((u32)0x1U << Cpu_Identifier); + + RegValue &= ~(Cpu_CoreId << (Offset * 8U)); + XScuGic_DistWriteReg(InstancePtr, + XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id), + RegValue); + + /* + * Release the lock previously taken. This macro ensures that the lock + * is given only if spinlock mechanism is enabled by the user. + */ + XIL_SPINUNLOCK(); +#endif + } } /****************************************************************************/ /** -* Unmaps all SPI interrupts from the target CPU +* Unmaps all SPI interrupts from the target CPU. * -* @param InstancePtr is a pointer to the instance to be worked on. -* @param Cpu_Identifier is a CPU number from which the interrupts has to be -* unmapped +* @param InstancePtr Pointer to the instance to be worked on. +* @param Cpu_Identifier CPU number from which the interrupts has to be +* unmapped. * * @return None. * -* @note None * *****************************************************************************/ void XScuGic_UnmapAllInterruptsFromCpu(XScuGic *InstancePtr, u8 Cpu_Identifier) @@ -1233,7 +1276,7 @@ void XScuGic_UnmapAllInterruptsFromCpu(XScuGic *InstancePtr, u8 Cpu_Identifier) Xil_AssertVoid(InstancePtr != NULL); - /* + /* * Call spinlock to protect multiple applications running at separate * CPUs to write to the same register. This macro also ensures that * the spinlock mechanism is used only if spinlock is enabled by @@ -1245,14 +1288,14 @@ void XScuGic_UnmapAllInterruptsFromCpu(XScuGic *InstancePtr, u8 Cpu_Identifier) LocalCpuID |= LocalCpuID << 16U; for (Int_Id = 32U; Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS; - Int_Id = Int_Id+4U) { + Int_Id = Int_Id + 4U) { Target_Cpu = XScuGic_DistReadReg(InstancePtr, - XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id)); + XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id)); /* Remove LocalCpuID from interrupt target register */ Target_Cpu &= (~LocalCpuID); XScuGic_DistWriteReg(InstancePtr, - XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id), Target_Cpu); + XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id), Target_Cpu); } @@ -1264,17 +1307,16 @@ void XScuGic_UnmapAllInterruptsFromCpu(XScuGic *InstancePtr, u8 Cpu_Identifier) } /****************************************************************************/ /** -* It checks if the interrupt target register contains all interrupts to be +* Checks if the interrupt target register contains all interrupts to be * targeted for current CPU. If they are programmed to be forwarded to current * cpu, this API disable all interrupts and disable GIC distributor. * This API also removes current CPU from interrupt target registers for all * interrupt. * -* @param InstancePtr is a pointer to the instance to be worked on. +* @param InstancePtr Pointer to the instance to be worked on. * * @return None. * -* @note None * *****************************************************************************/ void XScuGic_Stop(XScuGic *InstancePtr) @@ -1282,11 +1324,11 @@ void XScuGic_Stop(XScuGic *InstancePtr) u32 Int_Id; u32 RegValue; u32 Target_Cpu; - #if (defined (USE_AMP) && (USE_AMP==1)) +#if (defined (USE_AMP) && (USE_AMP==1)) u32 DistDisable = 0; /* Do not disable distributor */ - #else +#else u32 DistDisable = 1; /* Track distributor status*/ - #endif +#endif u32 LocalCpuID = ((u32)0x1 << CpuId); Xil_AssertVoid(InstancePtr != NULL); @@ -1306,44 +1348,44 @@ void XScuGic_Stop(XScuGic *InstancePtr) */ XIL_SPINLOCK(); #if defined (GICv3) - #if defined (VERSAL_NET) - #if defined (ARMR52) +#if defined (VERSAL_NET) +#if defined (ARMR52) LocalCpuID = XGetCoreId(); - #else +#else /* VERSAL_NET CortexA78 case */ LocalCpuID = XGetClusterId(); LocalCpuID = (LocalCpuID << XSCUGIC_IROUTER_AFFINITY2_SHIFT); LocalCpuID |= ((u32)XGetCoreId() << XSCUGIC_IROUTER_AFFINITY1_SHIFT); - #endif /*#if defined (ARMR52)*/ - #else +#endif /*#if defined (ARMR52)*/ +#else /* Versal CortexA72 case */ LocalCpuID = CpuId; - #endif /*#if defined (VERSAL_NET)*/ +#endif /*#if defined (VERSAL_NET)*/ /* - * Check if the interrupt are targeted to current cpu only or not. - * Also remove current cpu from interrupt target register for all - * interrupts. - */ - for (Int_Id = 32U; Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS; - Int_Id++) { + * Check if the interrupt are targeted to current cpu only or not. + * Also remove current cpu from interrupt target register for all + * interrupts. + */ + for (Int_Id = 32U; Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS; + Int_Id++) { - Target_Cpu = XScuGic_DistReadReg(InstancePtr, - XSCUGIC_IROUTER_OFFSET_CALC(Int_Id)); - if ((Target_Cpu != LocalCpuID)) { - /* - * If any other CPU is also programmed for interrupts - * GIC distributor can not be disabled. - */ - DistDisable = 0; - } + Target_Cpu = XScuGic_DistReadReg(InstancePtr, + XSCUGIC_IROUTER_OFFSET_CALC(Int_Id)); + if ((Target_Cpu != LocalCpuID)) { + /* + * If any other CPU is also programmed for interrupts + * GIC distributor can not be disabled. + */ + DistDisable = 0; + } - /* Remove current CPU from interrupt target register */ - Target_Cpu &= (~LocalCpuID); - XScuGic_DistWriteReg(InstancePtr, - XSCUGIC_IROUTER_OFFSET_CALC(Int_Id), Target_Cpu); + /* Remove current CPU from interrupt target register */ + Target_Cpu &= (~LocalCpuID); + XScuGic_DistWriteReg(InstancePtr, + XSCUGIC_IROUTER_OFFSET_CALC(Int_Id), Target_Cpu); - } + } #else LocalCpuID |= LocalCpuID << 8U; @@ -1355,10 +1397,10 @@ void XScuGic_Stop(XScuGic *InstancePtr) * interrupts. */ for (Int_Id = 32U; Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS; - Int_Id = Int_Id+4U) { + Int_Id = Int_Id + 4U) { Target_Cpu = XScuGic_DistReadReg(InstancePtr, - XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id)); + XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id)); if ((Target_Cpu != LocalCpuID) && (Target_Cpu != (u32)0)) { /* * If any other CPU is also programmed to target @@ -1370,7 +1412,7 @@ void XScuGic_Stop(XScuGic *InstancePtr) /* Remove current CPU from interrupt target register */ Target_Cpu &= (~LocalCpuID); XScuGic_DistWriteReg(InstancePtr, - XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id), Target_Cpu); + XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id), Target_Cpu); } #endif @@ -1380,14 +1422,14 @@ void XScuGic_Stop(XScuGic *InstancePtr) */ if (DistDisable == (u32)1) { for (Int_Id = 0U; Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS; - Int_Id = Int_Id+32U) { + Int_Id = Int_Id + 32U) { /* * Disable all the interrupts */ XScuGic_DistWriteReg(InstancePtr, - XSCUGIC_EN_DIS_OFFSET_CALC(XSCUGIC_DISABLE_OFFSET, - Int_Id), - 0xFFFFFFFFU); + XSCUGIC_EN_DIS_OFFSET_CALC(XSCUGIC_DISABLE_OFFSET, + Int_Id), + 0xFFFFFFFFU); } XScuGic_DistWriteReg(InstancePtr, XSCUGIC_DIST_EN_OFFSET, 0U); } @@ -1400,17 +1442,19 @@ void XScuGic_Stop(XScuGic *InstancePtr) /****************************************************************************/ /** -* This updates the CpuId global variable. +* Updates the CpuId global variable. * -* @param CpuCoreId is the CPU core number. +* @param CpuCoreId CPU core number. * * @return None. * -* @note None * *****************************************************************************/ void XScuGic_SetCpuID(u32 CpuCoreId) { + /* + * Validate the input arguments + */ Xil_AssertVoid(CpuCoreId <= 1U); CpuId = CpuCoreId; @@ -1418,11 +1462,10 @@ void XScuGic_SetCpuID(u32 CpuCoreId) /****************************************************************************/ /** -* This function returns the CpuId variable. +* Returns the CpuId variable. * * @return The CPU core number. * -* @note None. * *****************************************************************************/ u32 XScuGic_GetCpuID(void) @@ -1432,42 +1475,56 @@ u32 XScuGic_GetCpuID(void) /****************************************************************************/ /** -* It checks whether the XScGic is initialized or not given the device id. +* Checks whether the XScGic is initialized or not given the device ID. * -* @param DeviceId the XScuGic device. +* @param DeviceId ID of the XScuGic device. * * @return Returns 1 if initialized otherwise 0. * -* @note None * *****************************************************************************/ +#ifndef SDT u8 XScuGic_IsInitialized(u32 DeviceId) +#else +u8 XScuGic_IsInitialized(u32 BaseAddress) +#endif { u8 Device_Initilaized = 0U; XScuGic_Config *CfgPtr; u32 RegVal; - +#ifndef SDT + /* + * Looks up the device configuration based + * on the unique device ID. + */ CfgPtr = XScuGic_LookupConfig(DeviceId); +#else + /* + * Looks up the device configuration based on the CPU interface + * base address of the device. + */ + CfgPtr = XScuGic_LookupConfig(BaseAddress); +#endif if (CfgPtr != NULL) { RegVal = XScuGic_ReadReg(CfgPtr->DistBaseAddress, XSCUGIC_DIST_EN_OFFSET); - if (RegVal & XSCUGIC_EN_INT_MASK) { + if ((RegVal & XSCUGIC_EN_INT_MASK) != 0U) { Device_Initilaized = 1U; } } - + /* Return statement */ return Device_Initilaized; } #if defined (GICv3) /****************************************************************************/ /** -* It marks processor core which calls this API as asleep +* Marks processor core which calls this API as asleep. * * @return None. * * @note It should be called before suspending processor core. Once this * API is invoked, pending interrupts for processor core asserts * WakeRequest, to indicate that the PE is to have its power -* restored In case of Versal SoC, WakeRequest will be consumed by +* restored. In case of Versal SoC, WakeRequest will be consumed by * psv_psm processor and psmfw will wake up APU processor core. * *****************************************************************************/ @@ -1475,19 +1532,18 @@ void XScuGic_MarkCoreAsleep(XScuGic *InstancePtr) { u32 Waker_State; - Waker_State = XScuGic_ReDistReadReg(InstancePtr,XSCUGIC_RDIST_WAKER_OFFSET); - XScuGic_ReDistWriteReg(InstancePtr,XSCUGIC_RDIST_WAKER_OFFSET, - Waker_State | - XSCUGIC_RDIST_WAKER_LOW_POWER_STATE_MASK); + Waker_State = XScuGic_ReDistReadReg(InstancePtr, XSCUGIC_RDIST_WAKER_OFFSET); + XScuGic_ReDistWriteReg(InstancePtr, XSCUGIC_RDIST_WAKER_OFFSET, + Waker_State | + XSCUGIC_RDIST_WAKER_LOW_POWER_STATE_MASK); } /****************************************************************************/ /** -* It marks processor core which calls this API as awake +* Marks processor core which calls this API as awake. * * @return None. * -* @note None * *****************************************************************************/ void XScuGic_MarkCoreAwake(XScuGic *InstancePtr) @@ -1495,10 +1551,10 @@ void XScuGic_MarkCoreAwake(XScuGic *InstancePtr) u32 Waker_State; Waker_State = XScuGic_ReDistReadReg(InstancePtr, - XSCUGIC_RDIST_WAKER_OFFSET); - XScuGic_ReDistWriteReg(InstancePtr,XSCUGIC_RDIST_WAKER_OFFSET, - Waker_State & - (~ XSCUGIC_RDIST_WAKER_LOW_POWER_STATE_MASK)); + XSCUGIC_RDIST_WAKER_OFFSET); + XScuGic_ReDistWriteReg(InstancePtr, XSCUGIC_RDIST_WAKER_OFFSET, + Waker_State & + (~ XSCUGIC_RDIST_WAKER_LOW_POWER_STATE_MASK)); } #endif /** @} */ diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/scugic/src/xscugic.h b/bsp_z7/ps7_cortexa9_0/libsrc/scugic/src/xscugic.h index 0ee7342..3eb2f65 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/scugic/src/xscugic.h +++ b/bsp_z7/ps7_cortexa9_0/libsrc/scugic/src/xscugic.h @@ -1,6 +1,6 @@ /****************************************************************************** * Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved. -* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved. +* Copyright (C) 2022 - 2024 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -8,56 +8,10 @@ /** * * @file xscugic.h -* @addtogroup scugic Overview +* @addtogroup scugic_api SCUGIC APIs * @{ * @details * -* The generic interrupt controller driver component. -* -* The interrupt controller driver uses the idea of priority for the various -* handlers. Priority is an integer within the range of 1 and 31 inclusive with -* default of 1 being the highest priority interrupt source. The priorities -* of the various sources can be dynamically altered as needed through -* hardware configuration. -* -* The generic interrupt controller supports the following -* features: -* -* - specific individual interrupt enabling/disabling -* - specific individual interrupt acknowledging -* - attaching specific callback function to handle interrupt source -* - assigning desired priority to interrupt source if default is not -* acceptable. -* -* Details about connecting the interrupt handler of the driver are contained -* in the source file specific to interrupt processing, xscugic_intr.c. -* -* This driver is intended to be RTOS and processor independent. It works with -* physical addresses only. Any needs for dynamic memory management, threads -* or thread mutual exclusion, virtual memory, or cache control must be -* satisfied by the layer above this driver. -* -* Interrupt Vector Tables -* -* The device ID of the interrupt controller device is used by the driver as a -* direct index into the configuration data table. The user should populate the -* vector table with handlers and callbacks at run-time using the -* XScuGic_Connect() and XScuGic_Disconnect() functions. -* -* Each vector table entry corresponds to a device that can generate an -* interrupt. Each entry contains an interrupt handler function and an -* argument to be passed to the handler when an interrupt occurs. The -* user must use XScuGic_Connect() when the interrupt handler takes an -* argument other than the base address. -* -* Nested Interrupts Processing -* -* Nested interrupts are not supported by this driver. -* -* NOTE: -* The generic interrupt controller is not a part of the snoop control unit -* as indicated by the prefix "scu" in the name of the driver. -* It is an independent module in APU. * * 
 * MODIFICATION HISTORY:
@@ -190,12 +144,14 @@
 *                     executed, redistributor address will be stored in newly
 *                     added member of XScuGic data structure "RedistBaseAddr".
 *                     It fixes CR#1150432.
+* 5.2   ml   03/02/23 Add description to fix Doxygen warnings.
+* 5.2   adk  04/14/23 Added support for system device-tree flow.
 *
* ******************************************************************************/ -#ifndef XSCUGIC_H /* prevent circular inclusions */ -#define XSCUGIC_H /* by using protection macros */ +#ifndef XSCUGIC_H /**< prevent circular inclusions */ +#define XSCUGIC_H /**< by using protection macros */ #ifdef __cplusplus extern "C" { @@ -212,13 +168,23 @@ extern "C" { /************************** Constant Definitions *****************************/ +/** + * @name EFUSE status Register information + * EFUSE Status Register + * @{ + */ #define EFUSE_STATUS_OFFSET 0x10 #define EFUSE_STATUS_CPU_MASK 0x80 #if !defined (ARMR5) && !defined (__aarch64__) && !defined (ARMA53_32) -#define ARMA9 +#define ARMA9 /**< ARMA9 macro to identify cortexA9 */ #endif +/** + * @name GICD_CTLR Register information + * GICD_CTLR Status Register + * @{ + */ #define XSCUGIC500_DCTLR_ARE_NS_ENABLE 0x20 #define XSCUGIC500_DCTLR_ARE_S_ENABLE 0x10 @@ -245,8 +211,12 @@ extern "C" { */ typedef struct { - Xil_InterruptHandler Handler; - void *CallBackRef; + Xil_InterruptHandler Handler; /**< Interrupt Handler */ + void *CallBackRef; /**< CallBackRef is the callback reference passed in + by the upper layer when setting the Interrupt + handler for specific interrupt ID, and it will + passed back to Interrupt handler when it is + invoked. */ } XScuGic_VectorTableEntry; /** @@ -254,9 +224,15 @@ typedef struct */ typedef struct { +#ifndef SDT u16 DeviceId; /**< Unique ID of device */ u32 CpuBaseAddress; /**< CPU Interface Register base address */ u32 DistBaseAddress; /**< Distributor Register base address */ +#else + char *Name; /**< Compatible string */ + u32 DistBaseAddress; /**< Distributor Register base address */ + u32 CpuBaseAddress; /**< CPU Interface Register base address */ +#endif XScuGic_VectorTableEntry HandlerTable[XSCUGIC_MAX_NUM_INTR_INPUTS];/**< Vector table of interrupt handlers */ } XScuGic_Config; @@ -285,17 +261,16 @@ extern XScuGic_Config XScuGic_ConfigTable[]; /**< Config table */ /****************************************************************************/ /** * -* Write the given CPU Interface register +* Writes the given CPU Interface register. * -* @param InstancePtr is a pointer to the instance to be worked on. -* @param RegOffset is the register offset to be written -* @param Data is the 32-bit value to write to the register +* @param InstancePtr Pointer to the instance to be worked on. +* @param RegOffset Register offset to be written. +* @param Data 32-bit value to write to the register. * * @return None. * -* @note -* C-style signature: -* void XScuGic_CPUWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data) +* @note C-style signature: +* void XScuGic_CPUWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data) * *****************************************************************************/ #define XScuGic_CPUWriteReg(InstancePtr, RegOffset, Data) \ @@ -305,16 +280,15 @@ extern XScuGic_Config XScuGic_ConfigTable[]; /**< Config table */ /****************************************************************************/ /** * -* Read the given CPU Interface register +* Reads the given CPU Interface register. * -* @param InstancePtr is a pointer to the instance to be worked on. -* @param RegOffset is the register offset to be read +* @param InstancePtr Pointer to the instance to be worked on. +* @param RegOffset Rregister offset to be read. * -* @return The 32-bit value of the register +* @return 32-bit value of the register * -* @note -* C-style signature: -* u32 XScuGic_CPUReadReg(XScuGic *InstancePtr, u32 RegOffset) +* @note C-style signature: +* u32 XScuGic_CPUReadReg(XScuGic *InstancePtr, u32 RegOffset) * *****************************************************************************/ #define XScuGic_CPUReadReg(InstancePtr, RegOffset) \ @@ -323,17 +297,16 @@ extern XScuGic_Config XScuGic_ConfigTable[]; /**< Config table */ /****************************************************************************/ /** * -* Write the given Distributor Interface register +* Writes the given Distributor Interface register. * -* @param InstancePtr is a pointer to the instance to be worked on. -* @param RegOffset is the register offset to be written -* @param Data is the 32-bit value to write to the register +* @param InstancePtr Pointer to the instance to be worked on. +* @param RegOffset Register offset to be written. +* @param Data 32-bit value to write to the register. * * @return None. * -* @note -* C-style signature: -* void XScuGic_DistWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data) +* @note C-style signature: +* void XScuGic_DistWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data) * *****************************************************************************/ #define XScuGic_DistWriteReg(InstancePtr, RegOffset, Data) \ @@ -343,16 +316,15 @@ extern XScuGic_Config XScuGic_ConfigTable[]; /**< Config table */ /****************************************************************************/ /** * -* Read the given Distributor Interface register +* Reads the given Distributor Interface register * -* @param InstancePtr is a pointer to the instance to be worked on. -* @param RegOffset is the register offset to be read +* @param InstancePtr Pointer to the instance to be worked on. +* @param RegOffset Register offset to be read. * -* @return The 32-bit value of the register +* @return The 32-bit value of the register. * -* @note -* C-style signature: -* u32 XScuGic_DistReadReg(XScuGic *InstancePtr, u32 RegOffset) +* @note C-style signature: +* u32 XScuGic_DistReadReg(XScuGic *InstancePtr, u32 RegOffset) * *****************************************************************************/ #define XScuGic_DistReadReg(InstancePtr, RegOffset) \ @@ -362,17 +334,16 @@ extern XScuGic_Config XScuGic_ConfigTable[]; /**< Config table */ /****************************************************************************/ /** * -* Write the given ReDistributor Interface register +* Writes the given ReDistributor Interface register. * -* @param InstancePtr is a pointer to the instance to be worked on. -* @param RegOffset is the register offset to be written -* @param Data is the 32-bit value to write to the register +* @param InstancePtr Pointer to the instance to be worked on. +* @param RegOffset Register offset to be written. +* @param Data 32-bit value to write to the register. * * @return None. * -* @note -* C-style signature: -* void XScuGic_DistWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data) +* @note C-style signature: +* void XScuGic_DistWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data) * *****************************************************************************/ #define XScuGic_ReDistWriteReg(InstancePtr, RegOffset, Data) \ @@ -381,16 +352,15 @@ extern XScuGic_Config XScuGic_ConfigTable[]; /**< Config table */ /****************************************************************************/ /** * -* Read the given ReDistributor Interface register +* Reads the given ReDistributor Interface register. * -* @param InstancePtr is a pointer to the instance to be worked on. -* @param RegOffset is the register offset to be read +* @param InstancePtr Pointer to the instance to be worked on. +* @param RegOffset Register offset to be read. * -* @return The 32-bit value of the register +* @return 32-bit value of the register. * -* @note -* C-style signature: -* u32 XScuGic_DistReadReg(XScuGic *InstancePtr, u32 RegOffset) +* @note C-style signature: +* u32 XScuGic_DistReadReg(XScuGic *InstancePtr, u32 RegOffset) * *****************************************************************************/ #define XScuGic_ReDistReadReg(InstancePtr, RegOffset) \ @@ -399,17 +369,16 @@ extern XScuGic_Config XScuGic_ConfigTable[]; /**< Config table */ /****************************************************************************/ /** * -* Write the given ReDistributor SGI PPI Interface register +* Writes the given ReDistributor SGI PPI Interface register. * -* @param InstancePtr is a pointer to the instance to be worked on. -* @param RegOffset is the register offset to be written -* @param Data is the 32-bit value to write to the register +* @param InstancePtr Pointer to the instance to be worked on. +* @param RegOffset Register offset to be written. +* @param Data 32-bit value to write to the register. * * @return None. * -* @note -* C-style signature: -* void XScuGic_DistWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data) +* @note C-style signature: +* void XScuGic_DistWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data) * *****************************************************************************/ #define XScuGic_ReDistSGIPPIWriteReg(InstancePtr, RegOffset, Data) \ @@ -419,16 +388,15 @@ extern XScuGic_Config XScuGic_ConfigTable[]; /**< Config table */ /****************************************************************************/ /** * -* Read the given ReDistributor SGI PPI Interface register +* Reads the given ReDistributor SGI PPI Interface register * -* @param InstancePtr is a pointer to the instance to be worked on. -* @param RegOffset is the register offset to be read +* @param InstancePtr Pointer to the instance to be worked on. +* @param RegOffset Register offset to be read. * * @return The 32-bit value of the register * -* @note -* C-style signature: -* u32 XScuGic_DistReadReg(XScuGic *InstancePtr, u32 RegOffset) +* @note C-style signature: +* u32 XScuGic_DistReadReg(XScuGic *InstancePtr, u32 RegOffset) * *****************************************************************************/ #define XScuGic_ReDistSGIPPIReadReg(InstancePtr, RegOffset) \ @@ -443,9 +411,12 @@ extern XScuGic_Config XScuGic_ConfigTable[]; /**< Config table */ #define XREG_ICC_SGI1R_EL1 "p15, 0, %0, %1, c12" #define XREG_ICC_PMR_EL1 "p15, 0, %0, c4, c6, 0" #define XREG_ICC_IAR0_EL1 "p15, 0, %0, c12, c8, 0" +#define XREG_ICC_IAR1_EL1 "p15, 0, %0, c12, c12, 0" #define XREG_ICC_EOIR0_EL1 "p15, 0, %0, c12, c8, 1" +#define XREG_ICC_EOIR1_EL1 "p15, 0, %0, c12, c12, 1" #define XREG_IMP_CBAR "p15, 1, %0, c15, c3, 0" #define XREG_ICC_BPR0_EL1 "p15, 0, %0, c12, c8, 3" +#define XREG_ICC_BPR1_EL1 "p15, 0, %0, c12, c12, 3" #define XREG_ICC_RPR_EL1 "p15, 0, %0, c12, c11, 3" #else #define XREG_ICC_SRE_EL1 "S3_0_C12_C12_5" @@ -463,13 +434,12 @@ extern XScuGic_Config XScuGic_ConfigTable[]; /**< Config table */ #endif /****************************************************************************/ /** -* This function enables system register interface for GIC CPU Interface +* Enables system register interface for GIC CPU Interface. * -* @param value to be written +* @param value Value to be written. * * @return None. * -* @note None. * *****************************************************************************/ #if defined (__aarch64__) @@ -480,13 +450,12 @@ extern XScuGic_Config XScuGic_ConfigTable[]; /**< Config table */ #endif /****************************************************************************/ /** -* This function enables Grou0 interrupts +* Enable Grou0 interrupts. * * @param None. * * @return None. * -* @note None. * *****************************************************************************/ #if defined(ARMR52) @@ -502,7 +471,6 @@ extern XScuGic_Config XScuGic_ConfigTable[]; /**< Config table */ * * @return None. * -* @note None. * *****************************************************************************/ #if defined (ARMR52) @@ -518,13 +486,12 @@ extern XScuGic_Config XScuGic_ConfigTable[]; /**< Config table */ #endif /****************************************************************************/ /** -* This function writes to ICC_SGI0R_EL1 +* Writes to ICC_SGI0R_EL1. * -* @param value to be written +* @param value Value to be written. * * @return None. * -* @note None. * *****************************************************************************/ #if defined(ARMR52) @@ -535,13 +502,12 @@ extern XScuGic_Config XScuGic_ConfigTable[]; /**< Config table */ /****************************************************************************/ /** -* This function writes to ICC_SGI1R_EL1 +* Writes to ICC_SGI1R_EL1. * -* @param value to be written +* @param value Value to be written. * * @return None. * -* @note None. * *****************************************************************************/ #if defined(ARMR52) @@ -552,13 +518,12 @@ extern XScuGic_Config XScuGic_ConfigTable[]; /**< Config table */ /****************************************************************************/ /** -* This function reads ICC_SGI1R_EL1 register +* Reads ICC_SGI1R_EL1 register. * * @param None * * @return Value of ICC_SGI1R_EL1 register * -* @note None. * *****************************************************************************/ #if defined (ARMR52) @@ -568,13 +533,12 @@ extern XScuGic_Config XScuGic_ConfigTable[]; /**< Config table */ #endif /****************************************************************************/ /** -* This function sets interrupt priority filter +* Sets interrupt priority filter. * * @param None. * * @return None. * -* @note None. * *****************************************************************************/ #if defined (ARMR52) @@ -584,17 +548,16 @@ extern XScuGic_Config XScuGic_ConfigTable[]; /**< Config table */ #endif /****************************************************************************/ /** -* This function returns interrupt id of highest priority pending interrupt +* Returns interrupt ID of highest priority pending interrupt. * * @param None. * * @return None. * -* @note None. * *****************************************************************************/ #if defined(ARMR52) -#define XScuGic_get_IntID() mfcp(XREG_ICC_IAR0_EL1) +#define XScuGic_get_IntID() mfcp(XREG_ICC_IAR1_EL1) #elif EL3 #define XScuGic_get_IntID() mfcpnotoken(XREG_ICC_IAR0_EL1) #else @@ -602,17 +565,16 @@ extern XScuGic_Config XScuGic_ConfigTable[]; /**< Config table */ #endif /****************************************************************************/ /** -* This function acks the interrupt +* Acknowledges the interrupt. * * @param None. * * @return None. * -* @note None. * *****************************************************************************/ #if defined(ARMR52) -#define XScuGic_ack_Int(val) mtcp(XREG_ICC_EOIR0_EL1,val) +#define XScuGic_ack_Int(val) mtcp(XREG_ICC_EOIR1_EL1,val) #elif EL3 #define XScuGic_ack_Int(val) mtcpnotoken(XREG_ICC_EOIR0_EL1,val) #else @@ -627,7 +589,6 @@ extern XScuGic_Config XScuGic_ConfigTable[]; /**< Config table */ * * @return None. * -* @note None. * *****************************************************************************/ #define XScuGic_Get_Rdist_Int_Trigger_Index(IntrId) ((Int_Id%16) * 2U) @@ -660,12 +621,23 @@ void XScuGic_UnmapAllInterruptsFromCpu(XScuGic *InstancePtr, u8 Cpu_Identifier); void XScuGic_Stop(XScuGic *InstancePtr); void XScuGic_SetCpuID(u32 CpuCoreId); u32 XScuGic_GetCpuID(void); +#ifndef SDT u8 XScuGic_IsInitialized(u32 DeviceId); +#else +u8 XScuGic_IsInitialized(u32 BaseAddress); +#endif +#ifndef SDT /* - * Initialization functions in xscugic_sinit.c + * Lookup configuration by using DeviceId */ XScuGic_Config *XScuGic_LookupConfig(u16 DeviceId); +/* + * Lookup configuration by using BaseAddress + */ XScuGic_Config *XScuGic_LookupConfigBaseAddr(UINTPTR BaseAddress); +#else +XScuGic_Config *XScuGic_LookupConfig(UINTPTR BaseAddr); +#endif /* * Interrupt functions in xscugic_intr.c @@ -685,5 +657,6 @@ void XScuGic_MarkCoreAwake(XScuGic *InstancePtr); } #endif -#endif /* end of protection macro */ +#endif +/* end of protection macro */ /** @} */ diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/scugic/src/xscugic_g.c b/bsp_z7/ps7_cortexa9_0/libsrc/scugic/src/xscugic_g.c index 7b5f3ae..d5be5c9 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/scugic/src/xscugic_g.c +++ b/bsp_z7/ps7_cortexa9_0/libsrc/scugic/src/xscugic_g.c @@ -1,6 +1,6 @@ /****************************************************************************** * Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved. -* Copyright (c) 2022 Advanced Micro Devices, Inc. All Rights Reserved. +* Copyright (c) 2022 - 2024 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -8,10 +8,10 @@ /** * * @file xscugic_g.c -* @addtogroup scugic Overview +* @addtogroup scugic_api SCUGIC APIs * @{ * -* This file contains a configuration table that specifies the configuration of +* The xscugic_g.c file contains a configuration table that specifies the configuration of * interrupt controller devices in the system. * * 
diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/scugic/src/xscugic_hw.c b/bsp_z7/ps7_cortexa9_0/libsrc/scugic/src/xscugic_hw.c
index 88c38c7..45aebfc 100644
--- a/bsp_z7/ps7_cortexa9_0/libsrc/scugic/src/xscugic_hw.c
+++ b/bsp_z7/ps7_cortexa9_0/libsrc/scugic/src/xscugic_hw.c
@@ -1,6 +1,6 @@
 /******************************************************************************
 * Copyright (C) 2010 - 2022 Xilinx, Inc.  All rights reserved.
-* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved.
+* Copyright (C) 2022 - 2024 Advanced Micro Devices, Inc. All Rights Reserved.
 * SPDX-License-Identifier: MIT
 ******************************************************************************/
 
@@ -8,14 +8,14 @@
 /**
 *
 * @file xscugic_hw.c
-* @addtogroup scugic Overview
+* @addtogroup scugic_api SCUGIC APIs
 * @{
 *
-* This file contains low-level driver functions that can be used to access the
-* device.  The user should refer to the hardware device specification for more
+* The xscugic_hw.c file contains low-level driver functions that can be used to access the
+* device. The user should refer to the hardware device specification for more
 * details of the device operation.
 * These routines are used when the user does not want to create an instance of
-* XScuGic structure but still wants to use the ScuGic device. Hence the
+* XScuGic structure but still wants to use the ScuGic device. Hence, the
 * routines provided here take device id or scugic base address as arguments.
 * Separate static versions of DistInit and CPUInit are provided to implement
 * the low level driver routines.
@@ -93,6 +93,10 @@
 * 5.1   mus  03/07/23 Fix XScuGic_InterruptMapFromCpuByDistAddr and
 *                     XScuGic_InterruptUnmapFromCpuByDistAddr for GICv3.
 *
+* 5.2   ml   03/02/23 Remove few comments to fix doxygen warnings.
+* 5.2   mus  07/19/23 Updated XScuGic_DeviceInterruptHandler to support SDT
+*                     flow.
+* 5.2   ml   09/07/23 Added comments to fix HIS COMF violations.
 *
* ******************************************************************************/ @@ -103,12 +107,17 @@ #include "xil_types.h" #include "xil_assert.h" #include "xscugic.h" +#ifndef SDT #include "xparameters.h" #if defined (VERSAL_NET) #include "xplatform_info.h" #endif +#endif + /************************** Constant Definitions *****************************/ +#define DEFAULT_PRIORITY 0xa0a0a0a0U /**< Default value for priority_level + register */ /**************************** Type Definitions *******************************/ /***************** Macros (Inline Functions) Definitions *********************/ @@ -134,12 +143,9 @@ static XScuGic_Config *LookupConfigByBaseAddress(u32 CpuBaseAddress); * - All interrupt sources are disabled * - Enable the distributor * -* @param InstancePtr is a pointer to the XScuGic instance. -* @param CpuID is the Cpu ID to be initialized. * * @return None * -* @note None. * ******************************************************************************/ static void DistInit(const XScuGic_Config *Config) @@ -147,7 +153,7 @@ static void DistInit(const XScuGic_Config *Config) u32 Int_Id; #if (defined (USE_AMP) && (USE_AMP==1)) - #warning "Building GIC for AMP" +#warning "Building GIC for AMP" /* * The distributor should not be initialized by FreeRTOS in the case of @@ -163,14 +169,14 @@ static void DistInit(const XScuGic_Config *Config) UINTPTR RedistBaseAddr; RedistBaseAddr = XScuGic_GetRedistBaseAddr(); - #if defined (GIC600) - XScuGic_WriteReg(RedistBaseAddr,XSCUGIC_RDIST_PWRR_OFFSET, - (XScuGic_ReadReg(RedistBaseAddr, XSCUGIC_RDIST_PWRR_OFFSET) & - (~XSCUGIC_RDIST_PWRR_RDPD_MASK))); - #endif - Waker_State = XScuGic_ReadReg(RedistBaseAddr,XSCUGIC_RDIST_WAKER_OFFSET); - XScuGic_WriteReg(RedistBaseAddr,XSCUGIC_RDIST_WAKER_OFFSET, - Waker_State & (~ XSCUGIC_RDIST_WAKER_LOW_POWER_STATE_MASK)); +#if defined (GIC600) + XScuGic_WriteReg(RedistBaseAddr, XSCUGIC_RDIST_PWRR_OFFSET, + (XScuGic_ReadReg(RedistBaseAddr, XSCUGIC_RDIST_PWRR_OFFSET) & + (~XSCUGIC_RDIST_PWRR_RDPD_MASK))); +#endif + Waker_State = XScuGic_ReadReg(RedistBaseAddr, XSCUGIC_RDIST_WAKER_OFFSET); + XScuGic_WriteReg(RedistBaseAddr, XSCUGIC_RDIST_WAKER_OFFSET, + Waker_State & (~ XSCUGIC_RDIST_WAKER_LOW_POWER_STATE_MASK)); /* Enable system reg interface through ICC_SRE_EL1 */ #if EL3 XScuGic_Enable_SystemReg_CPU_Interface_EL3(); @@ -202,19 +208,17 @@ static void DistInit(const XScuGic_Config *Config) * Only write to the SPI interrupts, so start at 32 */ for (Int_Id = 32U; Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS; - Int_Id = Int_Id+16U) { + Int_Id = Int_Id + 16U) { /* * Each INT_ID uses two bits, or 16 INT_ID per register * Set them all to be level sensitive, active HIGH. */ XScuGic_WriteReg(Config->DistBaseAddress, - XSCUGIC_INT_CFG_OFFSET_CALC(Int_Id), 0U); + XSCUGIC_INT_CFG_OFFSET_CALC(Int_Id), 0U); } - -#define DEFAULT_PRIORITY 0xa0a0a0a0U for (Int_Id = 0U; Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS; - Int_Id = Int_Id+4U) { + Int_Id = Int_Id + 4U) { /* * 2. The priority using int the priority_level register * The priority_level and spi_target registers use one byte per @@ -222,34 +226,34 @@ static void DistInit(const XScuGic_Config *Config) * Write a default value that can be changed elsewhere. */ XScuGic_WriteReg(Config->DistBaseAddress, - XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id), - DEFAULT_PRIORITY); + XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id), + DEFAULT_PRIORITY); } #if defined (GICv3) - for (Int_Id = 0U; Int_IdDistBaseAddress, - XSCUGIC_SECURITY_TARGET_OFFSET_CALC(Int_Id), - XSCUGIC_DEFAULT_SECURITY); + XSCUGIC_SECURITY_TARGET_OFFSET_CALC(Int_Id), + XSCUGIC_DEFAULT_SECURITY); } /* * Set security for SGI/PPI * */ XScuGic_WriteReg( RedistBaseAddr + XSCUGIC_RDIST_SGI_PPI_OFFSET, - XSCUGIC_RDIST_IGROUPR_OFFSET, XSCUGIC_DEFAULT_SECURITY); + XSCUGIC_RDIST_IGROUPR_OFFSET, XSCUGIC_DEFAULT_SECURITY); #endif for (Int_Id = 0U; Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS; - Int_Id = Int_Id+32U) { + Int_Id = Int_Id + 32U) { /* * 4. Enable the SPI using the enable_set register. * Leave all disabled for now. */ XScuGic_WriteReg(Config->DistBaseAddress, - XSCUGIC_EN_DIS_OFFSET_CALC(XSCUGIC_DISABLE_OFFSET, - Int_Id), - 0xFFFFFFFFU); + XSCUGIC_EN_DIS_OFFSET_CALC(XSCUGIC_DISABLE_OFFSET, + Int_Id), + 0xFFFFFFFFU); } @@ -258,14 +262,14 @@ static void DistInit(const XScuGic_Config *Config) Temp |= XSCUGIC_EN_INT_MASK; XScuGic_WriteReg(Config->DistBaseAddress, XSCUGIC_DIST_EN_OFFSET, Temp); XScuGic_Enable_Group1_Interrupts(); - #if defined (ARMR52) || (defined (__aarch64__) && (EL1_NONSECURE == 0)) +#if defined (ARMR52) || (defined (__aarch64__) && (EL1_NONSECURE == 0)) XScuGic_Enable_Group0_Interrupts(); - #endif +#endif XScuGic_set_priority_filter(0xff); #else XScuGic_WriteReg(Config->DistBaseAddress, XSCUGIC_DIST_EN_OFFSET, - XSCUGIC_EN_INT_MASK); + XSCUGIC_EN_INT_MASK); #endif } @@ -279,12 +283,9 @@ static void DistInit(const XScuGic_Config *Config) * - Set the priority of the CPU. * - Enable the CPU interface * -* @param ConfigPtr is a pointer to a config table for the particular -* device this driver is associated with. * * @return None * -* @note None. * ******************************************************************************/ static void CPUInit(const XScuGic_Config *Config) @@ -294,7 +295,7 @@ static void CPUInit(const XScuGic_Config *Config) * register */ XScuGic_WriteReg(Config->CpuBaseAddress, XSCUGIC_CPU_PRIOR_OFFSET, - 0xF0U); + 0xF0U); /* * If the CPU operates in both security domains, set parameters in the @@ -322,54 +323,72 @@ static void CPUInit(const XScuGic_Config *Config) /*****************************************************************************/ /** * -* Initialize the GIC based on the device id. The -* initialization entails: +* Initializes the GIC based on the device ID. The initialization entails: * * - Initialize distributor interface * - Initialize cpu interface * -* @param DeviceId is device id to be worked on. +* @param DeviceId Device id to be worked on. * * @return * * - XST_SUCCESS if initialization was successful * -* @note -* -* None. * ******************************************************************************/ +#ifndef SDT s32 XScuGic_DeviceInitialize(u32 DeviceId) { XScuGic_Config *Config; - + /* + * assigning configTable element by using device Id + */ Config = &XScuGic_ConfigTable[(u32)DeviceId]; DistInit(Config); #if !defined (GICv3) CPUInit(Config); #endif - + /* Return statement */ return XST_SUCCESS; } +#else +s32 XScuGic_DeviceInitialize(u32 DistBaseAddr) +{ + XScuGic_Config *Config; + /* + * Looks up the device configuration based on the Distributor + * interface base address of the device. + */ + Config = XScuGic_LookupConfig(DistBaseAddr); + if ( Config == NULL ) { + return XST_FAILURE; + } + DistInit(Config); +#if !defined (GICv3) + CPUInit(Config); +#endif + /* Return statement */ + return XST_SUCCESS; +} +#endif /*****************************************************************************/ /** -* This function is the primary interrupt handler for the driver. It must be +* This function is the primary interrupt handler for the driver. It must be * connected to the interrupt source such that it is called when an interrupt of * the interrupt controller is active. It will resolve which interrupts are * active and enabled and call the appropriate interrupt handler. It uses * the Interrupt Type information to determine when to acknowledge the -* interrupt.Highest priority interrupts are serviced first. +* interrupt. Highest priority interrupts are serviced first. * * This function assumes that an interrupt vector table has been previously * initialized. It does not verify that entries in the table are valid before * calling an interrupt handler. * -* @param DeviceId is the unique identifier for the ScuGic device. +* @param DeviceId Unique identifier for the ScuGic device. * * @return None. * -* @note None. * ******************************************************************************/ void XScuGic_DeviceInterruptHandler(void *DeviceId) @@ -382,7 +401,11 @@ void XScuGic_DeviceInterruptHandler(void *DeviceId) XScuGic_VectorTableEntry *TablePtr; XScuGic_Config *CfgPtr; +#ifndef SDT CfgPtr = &XScuGic_ConfigTable[(INTPTR)DeviceId]; +#else + CfgPtr = LookupConfigByBaseAddress((u32)DeviceId); +#endif #if defined (GICv3) InterruptID = XScuGic_get_IntID(); @@ -393,7 +416,7 @@ void XScuGic_DeviceInterruptHandler(void *DeviceId) * clear the interrupt in the GIC. */ IntIDFull = XScuGic_ReadReg(CfgPtr->CpuBaseAddress, - XSCUGIC_INT_ACK_OFFSET); + XSCUGIC_INT_ACK_OFFSET); InterruptID = IntIDFull & XSCUGIC_ACK_INTID_MASK; #endif @@ -444,38 +467,43 @@ IntrExit: /*****************************************************************************/ /** * -* Register a handler function for a specific interrupt ID. The vector table +* Register a handler function for a specific interrupt ID. The vector table * of the interrupt controller is updated, overwriting any previous handler. * The handler function will be called when an interrupt occurs for the given * interrupt ID. * -* @param BaseAddress is the CPU Interface Register base address of the +* @param BaseAddress CPU Interface Register base address of the * interrupt controller whose vector table will be modified. -* @param InterruptID is the interrupt ID to be associated with the input +* @param InterruptID Interrupt ID to be associated with the input * handler. -* @param IntrHandler is the function pointer that will be added to +* @param IntrHandler Function pointer that will be added to * the vector table for the given interrupt ID. -* @param CallBackRef is the argument that will be passed to the new +* @param CallBackRef Argument that will be passed to the new * handler function when it is called. This is user-specific. * * @return None. * -* @note -* -* Note that this function has no effect if the input base address is invalid. +* @note This function has no effect if the input base address is invalid. * ******************************************************************************/ void XScuGic_RegisterHandler(u32 BaseAddress, s32 InterruptID, - Xil_InterruptHandler IntrHandler, void *CallBackRef) + Xil_InterruptHandler IntrHandler, void *CallBackRef) { XScuGic_Config *CfgPtr; + + /* + * Looks up the device configuration based on the CPU interface + * base address of the device. + */ CfgPtr = LookupConfigByBaseAddress(BaseAddress); + /* checks whether cfgptr is NULL or not */ if (CfgPtr != NULL) { if (IntrHandler != NULL) { CfgPtr->HandlerTable[InterruptID].Handler = - (Xil_InterruptHandler)IntrHandler; + (Xil_InterruptHandler)IntrHandler; } + /* checks whether callBackRef is NULL or not */ if (CallBackRef != NULL) { CfgPtr->HandlerTable[InterruptID].CallBackRef = CallBackRef; @@ -490,27 +518,33 @@ void XScuGic_RegisterHandler(u32 BaseAddress, s32 InterruptID, * the device. A table contains the configuration info for each device in the * system. * -* @param CpuBaseAddress is the CPU Interface Register base address. +* @param CpuBaseAddress CPU Interface Register base address. * * @return A pointer to the configuration structure for the specified * device, or NULL if the device was not found. * -* @note None. * ******************************************************************************/ static XScuGic_Config *LookupConfigByBaseAddress(u32 CpuBaseAddress) { XScuGic_Config *CfgPtr = NULL; u32 Index; - +#ifndef SDT for (Index = 0U; Index < XPAR_SCUGIC_NUM_INSTANCES; Index++) { +#else + for (Index = 0U; XScuGic_ConfigTable[Index].Name != NULL; Index++) { +#endif + /* + * checks the CpuBaseAddress in configuration table + * whether it matches or not + */ if (XScuGic_ConfigTable[Index].CpuBaseAddress == - CpuBaseAddress) { + CpuBaseAddress) { CfgPtr = &XScuGic_ConfigTable[Index]; break; } } - + /* Return statement */ return (XScuGic_Config *)CfgPtr; } @@ -518,21 +552,21 @@ static XScuGic_Config *LookupConfigByBaseAddress(u32 CpuBaseAddress) /** * Sets the interrupt priority and trigger type for the specificd IRQ source. * -* @param DistBaseAddress is the distributor base address -* @param Int_Id is the IRQ source number to modify -* @param Priority is the new priority for the IRQ source. 0 is highest +* @param DistBaseAddress Distributor base address +* @param Int_Id IRQ source number to modify +* @param Priority New priority for the IRQ source. 0 is highest * priority, 0xF8(248) is lowest. There are 32 priority * levels supported with a step of 8. Hence the supported * priorities are 0, 8, 16, 32, 40 ..., 248. -* @param Trigger is the new trigger type for the IRQ source. +* @param Trigger New trigger type for the IRQ source. * Each bit pair describes the configuration for an INT_ID. * SFI Read Only b10 always * PPI Read Only depending on how the PPIs are configured. * b01 Active HIGH level sensitive -* b11 Rising edge sensitive -* SPI LSB is read only. +* b11 Rising edge sensitive +* SPI LSB is read only. * b01 Active HIGH level sensitive -* b11 Rising edge sensitive/ +* b11 Rising edge sensitive/ * * @return None. * @@ -541,7 +575,7 @@ static XScuGic_Config *LookupConfigByBaseAddress(u32 CpuBaseAddress) * *****************************************************************************/ void XScuGic_SetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id, - u8 Priority, u8 Trigger) + u8 Priority, u8 Trigger) { u32 RegValue; #if defined (GICv3) @@ -555,17 +589,16 @@ void XScuGic_SetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id, Xil_AssertVoid(Trigger <= XSCUGIC_INT_CFG_MASK); Xil_AssertVoid(LocalPriority <= XSCUGIC_MAX_INTR_PRIO_VAL); #if defined (GICv3) - if (Int_Id < XSCUGIC_SPI_INT_ID_START ) - { + if (Int_Id < XSCUGIC_SPI_INT_ID_START ) { RedistBaseAddr = XScuGic_GetRedistBaseAddr(); XScuGic_WriteReg(RedistBaseAddr + XSCUGIC_RDIST_SGI_PPI_OFFSET, - XSCUGIC_RDIST_INT_PRIORITY_OFFSET_CALC(Int_Id),Priority); + XSCUGIC_RDIST_INT_PRIORITY_OFFSET_CALC(Int_Id), Priority); Temp = XScuGic_ReadReg(RedistBaseAddr + XSCUGIC_RDIST_SGI_PPI_OFFSET, - XSCUGIC_RDIST_INT_CONFIG_OFFSET_CALC(Int_Id)); + XSCUGIC_RDIST_INT_CONFIG_OFFSET_CALC(Int_Id)); Index = XScuGic_Get_Rdist_Int_Trigger_Index(Int_Id); Temp |= (Trigger << Index); XScuGic_WriteReg(RedistBaseAddr + XSCUGIC_RDIST_SGI_PPI_OFFSET, - XSCUGIC_RDIST_INT_CONFIG_OFFSET_CALC(Int_Id),Temp); + XSCUGIC_RDIST_INT_CONFIG_OFFSET_CALC(Int_Id), Temp); return; } #endif @@ -582,7 +615,7 @@ void XScuGic_SetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id, * Determine the register to write to using the Int_Id. */ RegValue = XScuGic_ReadReg(DistBaseAddress, - XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id)); + XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id)); /* * The priority bits are Bits 7 to 3 in GIC Priority Register. This @@ -595,32 +628,32 @@ void XScuGic_SetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id, * Shift and Mask the correct bits for the priority and trigger in the * register */ - RegValue &= ~((u32)XSCUGIC_PRIORITY_MASK << ((Int_Id%4U)*8U)); - RegValue |= (u32)LocalPriority << ((Int_Id%4U)*8U); + RegValue &= ~((u32)XSCUGIC_PRIORITY_MASK << ((Int_Id % 4U) * 8U)); + RegValue |= (u32)LocalPriority << ((Int_Id % 4U) * 8U); /* * Write the value back to the register. */ XScuGic_WriteReg(DistBaseAddress, XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id), - RegValue); + RegValue); /* * Determine the register to write to using the Int_Id. */ RegValue = XScuGic_ReadReg(DistBaseAddress, - XSCUGIC_INT_CFG_OFFSET_CALC(Int_Id)); + XSCUGIC_INT_CFG_OFFSET_CALC(Int_Id)); /* * Shift and Mask the correct bits for the priority and trigger in the * register */ - RegValue &= ~((u32)XSCUGIC_INT_CFG_MASK << ((Int_Id%16U)*2U)); - RegValue |= (u32)Trigger << ((Int_Id%16U)*2U); + RegValue &= ~((u32)XSCUGIC_INT_CFG_MASK << ((Int_Id % 16U) * 2U)); + RegValue |= (u32)Trigger << ((Int_Id % 16U) * 2U); /* * Write the value back to the register. */ XScuGic_WriteReg(DistBaseAddress, XSCUGIC_INT_CFG_OFFSET_CALC(Int_Id), - RegValue); + RegValue); /* * Release the lock previously taken. This macro ensures that the lock @@ -633,11 +666,11 @@ void XScuGic_SetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id, /** * Gets the interrupt priority and trigger type for the specificd IRQ source. * -* @param DistBaseAddress is the distributor base address -* @param Int_Id is the IRQ source number to modify -* @param Priority is a pointer to the value of the priority of the IRQ +* @param DistBaseAddress Distributor base address +* @param Int_Id IRQ source number to modify +* @param Priority Pointer to the value of the priority of the IRQ * source. This is a return value. -* @param Trigger is pointer to the value of the trigger of the IRQ +* @param Trigger Pointer to the value of the trigger of the IRQ * source. This is a return value. * * @return None. @@ -647,7 +680,7 @@ void XScuGic_SetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id, * *****************************************************************************/ void XScuGic_GetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id, - u8 *Priority, u8 *Trigger) + u8 *Priority, u8 *Trigger) { u32 RegValue; #if defined (GICv3) @@ -658,14 +691,13 @@ void XScuGic_GetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id, Xil_AssertVoid(Priority != NULL); Xil_AssertVoid(Trigger != NULL); #if defined (GICv3) - if (Int_Id < XSCUGIC_SPI_INT_ID_START ) - { + if (Int_Id < XSCUGIC_SPI_INT_ID_START ) { RedistBaseAddr = XScuGic_GetRedistBaseAddr(); *Priority = XScuGic_ReadReg(RedistBaseAddr + XSCUGIC_RDIST_SGI_PPI_OFFSET, XSCUGIC_RDIST_INT_PRIORITY_OFFSET_CALC(Int_Id)); RegValue = XScuGic_ReadReg(RedistBaseAddr + XSCUGIC_RDIST_SGI_PPI_OFFSET, XSCUGIC_RDIST_INT_CONFIG_OFFSET_CALC(Int_Id)); - RegValue = RegValue >> ((Int_Id%16U)*2U); + RegValue = RegValue >> ((Int_Id % 16U) * 2U); *Trigger = (u8)(RegValue & XSCUGIC_INT_CFG_MASK); return; } @@ -674,42 +706,41 @@ void XScuGic_GetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id, * Determine the register to read to using the Int_Id. */ RegValue = XScuGic_ReadReg(DistBaseAddress, - XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id)); + XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id)); /* * Shift and Mask the correct bits for the priority and trigger in the * register */ - RegValue = RegValue >> ((Int_Id%4U)*8U); + RegValue = RegValue >> ((Int_Id % 4U) * 8U); *Priority = (u8)(RegValue & XSCUGIC_PRIORITY_MASK); /* * Determine the register to read to using the Int_Id. */ RegValue = XScuGic_ReadReg(DistBaseAddress, - XSCUGIC_INT_CFG_OFFSET_CALC(Int_Id)); + XSCUGIC_INT_CFG_OFFSET_CALC(Int_Id)); /* * Shift and Mask the correct bits for the priority and trigger in the * register */ - RegValue = RegValue >> ((Int_Id%16U)*2U); + RegValue = RegValue >> ((Int_Id % 16U) * 2U); *Trigger = (u8)(RegValue & XSCUGIC_INT_CFG_MASK); } /****************************************************************************/ /** -* Sets the target CPU for the interrupt of a peripheral +* Sets the target CPU for the interrupt of a peripheral. * -* @param DistBaseAddress is the device base address -* @param Cpu_Id is a CPU number from which the interrupt has to be +* @param DistBaseAddress Device base address +* @param Cpu_Id CPU number from which the interrupt has to be * unmapped -* @param Int_Id is the IRQ source number to modify +* @param Int_Id IRQ source number to modify * * @return None. * -* @note None * *****************************************************************************/ void XScuGic_InterruptMapFromCpuByDistAddr(u32 DistBaseAddress, @@ -720,147 +751,145 @@ void XScuGic_InterruptMapFromCpuByDistAddr(u32 DistBaseAddress, u32 Offset; u8 Cpu_CoreId; #endif - + /* Validate the input arguments */ Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS); -if (Int_Id >= XSCUGIC_SPI_INT_ID_START) { + if (Int_Id >= XSCUGIC_SPI_INT_ID_START) { #if defined (GICv3) - u32 Temp; - Temp = Int_Id; + u32 Temp; + Temp = Int_Id; - #if defined (VERSAL_NET) - #if defined (ARMR52) - RegValue = (Cpu_Id & XSCUGIC_COREID_MASK); - #else - RegValue = ((Cpu_Id & XSCUGIC_CLUSTERID_MASK) >> XSCUGIC_CLUSTERID_SHIFT); - RegValue = (RegValue << XSCUGIC_IROUTER_AFFINITY2_SHIFT); - RegValue |= ((Cpu_Id & XSCUGIC_COREID_MASK) << XSCUGIC_IROUTER_AFFINITY1_SHIFT); - #endif - #else - RegValue = XScuGic_ReadReg(DistBaseAddress, - XSCUGIC_IROUTER_OFFSET_CALC(Temp)); - RegValue |= (Cpu_Id); - #endif - - XScuGic_WriteReg(DistBaseAddress, XSCUGIC_IROUTER_OFFSET_CALC(Temp), - RegValue); +#if defined (VERSAL_NET) +#if defined (ARMR52) + RegValue = (Cpu_Id & XSCUGIC_COREID_MASK); #else - /* - * Call spinlock to protect multiple applications running at separate - * CPUs to write to the same register. This macro also ensures that - * the spinlock mechanism is used only if spinlock is enabled by - * user. - */ - XIL_SPINLOCK(); - RegValue = XScuGic_ReadReg(DistBaseAddress, - XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id)); - - Offset = (Int_Id & 0x3U); - Cpu_CoreId = (0x1U << Cpu_Id); - - RegValue |= (u32)(Cpu_CoreId) << (Offset*8U); - - XScuGic_WriteReg(DistBaseAddress, - XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id), - RegValue); - /* - * Release the lock previously taken. This macro ensures that the lock - * is given only if spinlock mechanism is enabled by the user. - */ - XIL_SPINUNLOCK(); + RegValue = ((Cpu_Id & XSCUGIC_CLUSTERID_MASK) >> XSCUGIC_CLUSTERID_SHIFT); + RegValue = (RegValue << XSCUGIC_IROUTER_AFFINITY2_SHIFT); + RegValue |= ((Cpu_Id & XSCUGIC_COREID_MASK) << XSCUGIC_IROUTER_AFFINITY1_SHIFT); #endif -} +#else + RegValue = XScuGic_ReadReg(DistBaseAddress, + XSCUGIC_IROUTER_OFFSET_CALC(Temp)); + RegValue |= (Cpu_Id); +#endif + + XScuGic_WriteReg(DistBaseAddress, XSCUGIC_IROUTER_OFFSET_CALC(Temp), + RegValue); +#else + /* + * Call spinlock to protect multiple applications running at separate + * CPUs to write to the same register. This macro also ensures that + * the spinlock mechanism is used only if spinlock is enabled by + * user. + */ + XIL_SPINLOCK(); + RegValue = XScuGic_ReadReg(DistBaseAddress, + XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id)); + + Offset = (Int_Id & 0x3U); + Cpu_CoreId = (0x1U << Cpu_Id); + + RegValue |= (u32)(Cpu_CoreId) << (Offset * 8U); + + XScuGic_WriteReg(DistBaseAddress, + XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id), + RegValue); + /* + * Release the lock previously taken. This macro ensures that the lock + * is given only if spinlock mechanism is enabled by the user. + */ + XIL_SPINUNLOCK(); +#endif + } } /****************************************************************************/ /** -* Unmaps specific SPI interrupt from the target CPU +* Unmaps specific SPI interrupt from the target CPU. * -* @param DistBaseAddress is the device base address -* @param Cpu_Id is a CPU number from which the interrupt has to be +* @param DistBaseAddress Device base address +* @param Cpu_Id CPU number from which the interrupt has to be * unmapped -* @param Int_Id is the IRQ source number to modify +* @param Int_Id IRQ source number to modify * -* @return None. +* @return None * -* @note None * *****************************************************************************/ void XScuGic_InterruptUnmapFromCpuByDistAddr(u32 DistBaseAddress, - u8 Cpu_Id, u32 Int_Id) + u8 Cpu_Id, u32 Int_Id) { u32 RegValue; #if !defined (GICv3) u32 Offset; u32 Cpu_CoreId; #endif - + /* Validate the input arguments */ Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS); -if (Int_Id >= XSCUGIC_SPI_INT_ID_START) { + if (Int_Id >= XSCUGIC_SPI_INT_ID_START) { #if defined (GICv3) - u32 Temp; - Temp = Int_Id; + u32 Temp; + Temp = Int_Id; - RegValue = XScuGic_ReadReg(DistBaseAddress, - XSCUGIC_IROUTER_OFFSET_CALC(Temp)); - #if defined (VERSAL_NET) - #if defined (ARMR52) - Temp = (Cpu_Id & XSCUGIC_COREID_MASK); - #else - Temp = ((Cpu_Id & XSCUGIC_CLUSTERID_MASK) >> XSCUGIC_CLUSTERID_SHIFT); - Temp = (Temp << XSCUGIC_IROUTER_AFFINITY2_SHIFT); - Temp |= ((Cpu_Id & XSCUGIC_COREID_MASK) << XSCUGIC_IROUTER_AFFINITY1_SHIFT); - #endif - RegValue &= ~Temp; - #else - RegValue &= ~(Cpu_Id); - #endif - XScuGic_WriteReg(DistBaseAddress, XSCUGIC_IROUTER_OFFSET_CALC(Temp), - RegValue); + RegValue = XScuGic_ReadReg(DistBaseAddress, + XSCUGIC_IROUTER_OFFSET_CALC(Temp)); +#if defined (VERSAL_NET) +#if defined (ARMR52) + Temp = (Cpu_Id & XSCUGIC_COREID_MASK); #else - /* - * Call spinlock to protect multiple applications running at separate - * CPUs to write to the same register. This macro also ensures that - * the spinlock mechanism is used only if spinlock is enabled by - * user. - */ - XIL_SPINLOCK(); - - RegValue = XScuGic_ReadReg(DistBaseAddress, - XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id)); - - Offset = (Int_Id & 0x3U); - Cpu_CoreId = ((u32)0x1U << Cpu_Id); - - RegValue &= ~(Cpu_CoreId << (Offset*8U)); - XScuGic_WriteReg(DistBaseAddress, - XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id), RegValue); - - /* - * Release the lock previously taken. This macro ensures that the lock - * is given only if spinlock mechanism is enabled by the user. - */ - XIL_SPINUNLOCK(); + Temp = ((Cpu_Id & XSCUGIC_CLUSTERID_MASK) >> XSCUGIC_CLUSTERID_SHIFT); + Temp = (Temp << XSCUGIC_IROUTER_AFFINITY2_SHIFT); + Temp |= ((Cpu_Id & XSCUGIC_COREID_MASK) << XSCUGIC_IROUTER_AFFINITY1_SHIFT); #endif -} + RegValue &= ~Temp; +#else + RegValue &= ~(Cpu_Id); +#endif + XScuGic_WriteReg(DistBaseAddress, XSCUGIC_IROUTER_OFFSET_CALC(Temp), + RegValue); +#else + /* + * Call spinlock to protect multiple applications running at separate + * CPUs to write to the same register. This macro also ensures that + * the spinlock mechanism is used only if spinlock is enabled by + * user. + */ + XIL_SPINLOCK(); + + RegValue = XScuGic_ReadReg(DistBaseAddress, + XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id)); + + Offset = (Int_Id & 0x3U); + Cpu_CoreId = ((u32)0x1U << Cpu_Id); + + RegValue &= ~(Cpu_CoreId << (Offset * 8U)); + XScuGic_WriteReg(DistBaseAddress, + XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id), RegValue); + + /* + * Release the lock previously taken. This macro ensures that the lock + * is given only if spinlock mechanism is enabled by the user. + */ + XIL_SPINUNLOCK(); +#endif + } } /****************************************************************************/ /** -* Unmaps all SPI interrupts from the target CPU +* Unmaps all SPI interrupts from the target CPU. * -* @param DistBaseAddress is the device base address -* @param Cpu_Id is a CPU number from which the interrupts has to be +* @param DistBaseAddress Device base address +* @param Cpu_Id CPU number from which the interrupts has to be * unmapped * * @return None. * -* @note None * *****************************************************************************/ void XScuGic_UnmapAllInterruptsFromCpuByDistAddr(u32 DistBaseAddress, - u8 Cpu_Id) + u8 Cpu_Id) { u32 Int_Id; u32 Target_Cpu; @@ -878,14 +907,14 @@ void XScuGic_UnmapAllInterruptsFromCpuByDistAddr(u32 DistBaseAddress, LocalCpuID |= LocalCpuID << 16U; for (Int_Id = 32U; Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS; - Int_Id = Int_Id+4U) { + Int_Id = Int_Id + 4U) { Target_Cpu = XScuGic_ReadReg(DistBaseAddress, - XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id)); + XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id)); /* Remove LocalCpuID from interrupt target register */ Target_Cpu &= (~LocalCpuID); XScuGic_WriteReg(DistBaseAddress, - XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id), Target_Cpu); + XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id), Target_Cpu); } @@ -903,13 +932,11 @@ void XScuGic_UnmapAllInterruptsFromCpuByDistAddr(u32 DistBaseAddress, * interrupt condition for the specified Int_Id will occur after this function is * called. * -* @param InstancePtr is a pointer to the XScuGic instance. -* @param Int_Id contains the ID of the interrupt source and should be -* in the range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1 +* @param Int_Id Contains the ID of the interrupt source and should be +* in the range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1. * * @return None. * -* @note None. * ****************************************************************************/ void XScuGic_EnableIntr (u32 DistBaseAddress, u32 Int_Id) @@ -929,21 +956,21 @@ void XScuGic_EnableIntr (u32 DistBaseAddress, u32 Int_Id) Int_Id = 1 << Int_Id; Temp = XScuGic_ReadReg(RedistBaseAddr + - XSCUGIC_RDIST_SGI_PPI_OFFSET, XSCUGIC_RDIST_ISENABLE_OFFSET); + XSCUGIC_RDIST_SGI_PPI_OFFSET, XSCUGIC_RDIST_ISENABLE_OFFSET); Temp |= Int_Id; XScuGic_WriteReg(RedistBaseAddr + XSCUGIC_RDIST_SGI_PPI_OFFSET, - XSCUGIC_RDIST_ISENABLE_OFFSET,Temp); + XSCUGIC_RDIST_ISENABLE_OFFSET, Temp); return; } #endif - #if defined (VERSAL_NET) - #if defined (ARMR52) - Cpu_Id = XGetCoreId(); - #else - Cpu_Id = XGetCoreId(); - Cpu_Id |= (XGetClusterId() << XSCUGIC_CLUSTERID_SHIFT); - #endif - #endif +#if defined (VERSAL_NET) +#if defined (ARMR52) + Cpu_Id = XGetCoreId(); +#else + Cpu_Id = XGetCoreId(); + Cpu_Id |= (XGetClusterId() << XSCUGIC_CLUSTERID_SHIFT); +#endif +#endif XScuGic_InterruptMapFromCpuByDistAddr(DistBaseAddress, Cpu_Id, Int_Id); /* @@ -954,7 +981,7 @@ void XScuGic_EnableIntr (u32 DistBaseAddress, u32 Int_Id) */ XIL_SPINLOCK(); XScuGic_WriteReg((DistBaseAddress), XSCUGIC_ENABLE_SET_OFFSET + - (((Int_Id) / 32U) * 4U), ((u32)0x00000001U << ((Int_Id) % 32U))); + (((Int_Id) / 32U) * 4U), ((u32)0x00000001U << ((Int_Id) % 32U))); /* * Release the lock previously taken. This macro ensures that the lock * is given only if spinlock mechanism is enabled by the user. @@ -965,18 +992,16 @@ void XScuGic_EnableIntr (u32 DistBaseAddress, u32 Int_Id) /*****************************************************************************/ /** * -* Disables the interrupt source provided as the argument Int_Id such that the +* Disables the interrupt source provided as the argument Int_Id so that the * interrupt controller will not cause interrupts for the specified Int_Id. The * interrupt controller will continue to hold an interrupt condition for the * Int_Id, but will not cause an interrupt. * -* @param InstancePtr is a pointer to the XScuGic instance. -* @param Int_Id contains the ID of the interrupt source and should be -* in the range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1 +* @param Int_Id Contains the ID of the interrupt source and should be +* in the range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1. * * @return None. * -* @note None. * ****************************************************************************/ void XScuGic_DisableIntr (u32 DistBaseAddress, u32 Int_Id) @@ -996,21 +1021,21 @@ void XScuGic_DisableIntr (u32 DistBaseAddress, u32 Int_Id) RedistBaseAddr = XScuGic_GetRedistBaseAddr(); Temp = XScuGic_ReadReg(RedistBaseAddr + XSCUGIC_RDIST_SGI_PPI_OFFSET, - XSCUGIC_RDIST_ISENABLE_OFFSET); + XSCUGIC_RDIST_ISENABLE_OFFSET); Temp &= ~Int_Id; XScuGic_WriteReg(RedistBaseAddr + XSCUGIC_RDIST_SGI_PPI_OFFSET, - XSCUGIC_RDIST_ISENABLE_OFFSET,Temp); + XSCUGIC_RDIST_ISENABLE_OFFSET, Temp); return; } #endif - #if defined (VERSAL_NET) - #if defined (ARMR52) - Cpu_Id = XGetCoreId(); - #else - Cpu_Id = XGetCoreId(); - Cpu_Id |= (XGetClusterId() << XSCUGIC_CLUSTERID_SHIFT); - #endif - #endif +#if defined (VERSAL_NET) +#if defined (ARMR52) + Cpu_Id = XGetCoreId(); +#else + Cpu_Id = XGetCoreId(); + Cpu_Id |= (XGetClusterId() << XSCUGIC_CLUSTERID_SHIFT); +#endif +#endif XScuGic_InterruptUnmapFromCpuByDistAddr(DistBaseAddress, Cpu_Id, Int_Id); /* @@ -1021,7 +1046,7 @@ void XScuGic_DisableIntr (u32 DistBaseAddress, u32 Int_Id) */ XIL_SPINLOCK(); XScuGic_WriteReg((DistBaseAddress), XSCUGIC_DISABLE_OFFSET + - (((Int_Id) / 32U) * 4U), ((u32)0x00000001U << ((Int_Id) % 32U))); + (((Int_Id) / 32U) * 4U), ((u32)0x00000001U << ((Int_Id) % 32U))); /* * Release the lock previously taken. This macro ensures that the lock * is given only if spinlock mechanism is enabled by the user. @@ -1033,18 +1058,18 @@ void XScuGic_DisableIntr (u32 DistBaseAddress, u32 Int_Id) /*****************************************************************************/ /** * -* Find redistributor base address for CPU core on which API is executed +* Finds redistributor base address for CPU core on which API is executed. * * @return Redistributor base address or NULL if the device was * not found. * -* @note None. * ******************************************************************************/ -UINTPTR XScuGic_GetRedistBaseAddr(void) { - u32 Cpu_Affinity; - u64 Gicr_Typer; - UINTPTR BaseAddr = 0, Addr; +UINTPTR XScuGic_GetRedistBaseAddr(void) +{ + u32 Cpu_Affinity; + u64 Gicr_Typer; + UINTPTR BaseAddr = 0, Addr; /* * Find redistributor for CPU core on which this API is executed. @@ -1055,25 +1080,25 @@ UINTPTR XScuGic_GetRedistBaseAddr(void) { * as 0, that is why for CortexR52 case, affinity read from GICR_TYPER * is compared with affinity0 (core number) read from CPU register. */ - #if defined (ARMR52) - Cpu_Affinity = (mfcp(XREG_CP15_MULTI_PROC_AFFINITY) & XREG_MPIDR_AFFINITY0_MASK); - #else - Cpu_Affinity = (mfcp(MPIDR_EL1) & XREG_MPIDR_MASK); - #endif +#if defined (ARMR52) + Cpu_Affinity = (mfcp(XREG_CP15_MULTI_PROC_AFFINITY) & XREG_MPIDR_AFFINITY0_MASK); +#else + Cpu_Affinity = (mfcp(MPIDR_EL1) & XREG_MPIDR_MASK); +#endif - for (Addr = XSCUGIC_RDIST_START_ADDR; Addr < XSCUGIC_RDIST_END_ADDR; - Addr += XSCUGIC_RDIST_OFFSET) { + for (Addr = XSCUGIC_RDIST_START_ADDR; Addr < XSCUGIC_RDIST_END_ADDR; + Addr += XSCUGIC_RDIST_OFFSET) { - Gicr_Typer = XScuGic_ReadReg64(Addr, XSCUGIC_RDIST_TYPER_OFFSET); - Gicr_Typer &= XSCUGIC_GICR_TYPER_AFFINITY_MASK; - Gicr_Typer >>= XSCUGIC_GICR_TYPER_AFFINITY_SHIFT; - if (Cpu_Affinity == Gicr_Typer) { - BaseAddr = Addr; - break; - } - } + Gicr_Typer = XScuGic_ReadReg64(Addr, XSCUGIC_RDIST_TYPER_OFFSET); + Gicr_Typer &= XSCUGIC_GICR_TYPER_AFFINITY_MASK; + Gicr_Typer >>= XSCUGIC_GICR_TYPER_AFFINITY_SHIFT; + if (Cpu_Affinity == Gicr_Typer) { + BaseAddr = Addr; + break; + } + } - return BaseAddr; + return BaseAddr; } #endif /** @} */ diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/scugic/src/xscugic_hw.h b/bsp_z7/ps7_cortexa9_0/libsrc/scugic/src/xscugic_hw.h index 0bbd0c4..90637a2 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/scugic/src/xscugic_hw.h +++ b/bsp_z7/ps7_cortexa9_0/libsrc/scugic/src/xscugic_hw.h @@ -1,6 +1,6 @@ /****************************************************************************** * Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved. -* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved. +* Copyright (C) 2022 - 2024 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -8,11 +8,11 @@ /** * * @file xscugic_hw.h -* @addtogroup scugic Overview +* @addtogroup scugic_api SCUGIC APIs * @{ * -* This header file contains identifiers and HW access functions (or -* macros) that can be used to access the device. The user should refer to the +* The xscugic_hw.h header file contains identifiers and hardware access functions (or +* macros) that can be used to access the device. The user should refer to the * hardware device specification for more details of the device operation. * The driver functions/APIs are defined in xscugic.h. * @@ -69,13 +69,14 @@ * based address for specific CPU core. Also, added new macro * XScuGic_ReadReg64 to read 64 bit value from specific address. * 5.1 mus 02/15/23 Added support for VERSAL_NET APU and RPU GIC. -* +* 5.2 ml 03/02/23 Add description to fix Doxygen warnings. +* 5.2 mus 03/26/23 Fixed calculation for XSCUGIC_RDIST_INT_PRIORITY_OFFSET_CALC. * * ******************************************************************************/ -#ifndef XSCUGIC_HW_H /* prevent circular inclusions */ -#define XSCUGIC_HW_H /* by using protection macros */ +#ifndef XSCUGIC_HW_H /**< prevent circular inclusions */ +#define XSCUGIC_HW_H /**< by using protection macros */ #ifdef __cplusplus extern "C" { @@ -110,24 +111,31 @@ extern "C" { * The maximum number of interrupts supported by the hardware. */ #ifdef PLATFORM_ZYNQ -#define XSCUGIC_MAX_NUM_INTR_INPUTS 95U /* Maximum number of interrupt defined by Zynq */ +#define XSCUGIC_MAX_NUM_INTR_INPUTS 95U /**< Maximum number of + interrupt defined by + Zynq */ #elif defined (VERSAL_NET) -#define XSCUGIC_MAX_NUM_INTR_INPUTS 256U /* Maximum number of interrupt sources in VERSAL NET */ +#define XSCUGIC_MAX_NUM_INTR_INPUTS 256U /**< Maximum number of + interrupt sources in + VERSAL NET */ #elif defined (versal) -#define XSCUGIC_MAX_NUM_INTR_INPUTS 192U +#define XSCUGIC_MAX_NUM_INTR_INPUTS 192U /**< Maximum number of + interrupt sources in + VERSAL */ #else -#define XSCUGIC_MAX_NUM_INTR_INPUTS 195U /* Maximum number of interrupt defined by Zynq Ultrascale Mp */ +#define XSCUGIC_MAX_NUM_INTR_INPUTS 195U /**< Maximum number of + interrupt defined by + Zynq Ultrascale Mp */ #endif -/* - * First Interrupt Id for SPI interrupts. - */ -#define XSCUGIC_SPI_INT_ID_START 0x20U -/* - * The maximum priority value that can be used in the GIC. - */ -#define XSCUGIC_MAX_INTR_PRIO_VAL 248U -#define XSCUGIC_INTR_PRIO_MASK 0x000000F8U +#define XSCUGIC_SPI_INT_ID_START 0x20U /**< First Interrupt Id for + SPI interrupts. */ + +#define XSCUGIC_MAX_INTR_PRIO_VAL 248U /**< The maximum priority value + that can be used in + the GIC. */ +#define XSCUGIC_INTR_PRIO_MASK 0x000000F8U /**< The Interrupt + priority mask value */ /** @name Distributor Interface Register Map * @@ -338,7 +346,7 @@ extern "C" { * There are up to 255 of these registers staring at location 0xC08. * @{ */ -#define XSCUGIC_INT_CFG_MASK 0x00000003U /**< */ +#define XSCUGIC_INT_CFG_MASK 0x00000003U /**< Interrupt configuration Mask */ /* @} */ /** @name PPI Status Register @@ -523,6 +531,7 @@ extern "C" { #define XSCUGIC_RDIST_ISENABLE_OFFSET 0x100U #define XSCUGIC_RDIST_IPRIORITYR_OFFSET 0x400U #define XSCUGIC_RDIST_IGROUPR_OFFSET 0x80U + #define XSCUGIC_RDIST_GRPMODR_OFFSET 0xD00U #define XSCUGIC_RDIST_INT_CONFIG_OFFSET 0xC00U #define XSCUGIC_RDIST_TYPER_OFFSET 0x8U @@ -535,7 +544,7 @@ extern "C" { /* * GICR_IGROUPR register definitions */ -#if (defined(ARMR52) || EL3) +#if EL3 #define XSCUGIC_DEFAULT_SECURITY 0x0U #else #define XSCUGIC_DEFAULT_SECURITY 0xFFFFFFFFU @@ -551,13 +560,12 @@ extern "C" { /****************************************************************************/ /** * -* Read the Interrupt Configuration Register offset for an interrupt id. +* Reads the Interrupt Configuration Register offset for an interrupt ID. * -* @param InterruptID is the interrupt number. +* @param InterruptID Interrupt number. * * @return The 32-bit value of the offset * -* @note * *****************************************************************************/ #define XSCUGIC_INT_CFG_OFFSET_CALC(InterruptID) \ @@ -566,13 +574,12 @@ extern "C" { /****************************************************************************/ /** * -* Read the Interrupt Priority Register offset for an interrupt id. +* Reads the Interrupt Priority Register offset for an interrupt ID. * -* @param InterruptID is the interrupt number. +* @param InterruptID Interrupt number. * * @return The 32-bit value of the offset * -* @note * *****************************************************************************/ #define XSCUGIC_PRIORITY_OFFSET_CALC(InterruptID) \ @@ -581,13 +588,12 @@ extern "C" { /****************************************************************************/ /** * -* Read the Interrupt Routing Register offset for an interrupt id. +* Reads the Interrupt Routing Register offset for an interrupt ID. * -* @param InterruptID is the interrupt number. +* @param InterruptID Interrupt number. * * @return The 32-bit value of the offset * -* @note * *****************************************************************************/ #define XSCUGIC_IROUTER_OFFSET_CALC(InterruptID) \ @@ -596,13 +602,12 @@ extern "C" { /****************************************************************************/ /** * -* Read the SPI Target Register offset for an interrupt id. +* Reads the SPI Target Register offset for an interrupt ID. * -* @param InterruptID is the interrupt number. +* @param InterruptID Interrupt number. * -* @return The 32-bit value of the offset +* @return The 32-bit value of the offset. * -* @note * *****************************************************************************/ #define XSCUGIC_SPI_TARGET_OFFSET_CALC(InterruptID) \ @@ -610,13 +615,12 @@ extern "C" { /****************************************************************************/ /** * -* Read the SPI Target Register offset for an interrupt id. +* Reads the SPI Target Register offset for an interrupt ID. * -* @param InterruptID is the interrupt number. +* @param InterruptID Interrupt number. * * @return The 32-bit value of the offset * -* @note * *****************************************************************************/ #define XSCUGIC_SECURITY_TARGET_OFFSET_CALC(InterruptID) \ @@ -625,13 +629,12 @@ extern "C" { /****************************************************************************/ /** * -* Read the Re-distributor Interrupt configuration register offset +* Reads the Re-distributor Interrupt configuration register offset. * -* @param InterruptID is the interrupt number. +* @param InterruptID Interrupt number. * * @return The 32-bit value of the offset * -* @note * *****************************************************************************/ #define XSCUGIC_RDIST_INT_CONFIG_OFFSET_CALC(InterruptID) \ @@ -640,28 +643,26 @@ extern "C" { /****************************************************************************/ /** * -* Read the Re-distributor Interrupt Priority register offset +* Reads the Re-distributor Interrupt Priority register offset. * -* @param InterruptID is the interrupt number. +* @param InterruptID Interrupt number. * * @return The 32-bit value of the offset * -* @note * *****************************************************************************/ #define XSCUGIC_RDIST_INT_PRIORITY_OFFSET_CALC(InterruptID) \ - ((u32)XSCUGIC_RDIST_IPRIORITYR_OFFSET + (InterruptID * 4)) + ((u32)XSCUGIC_RDIST_IPRIORITYR_OFFSET + ((InterruptID/4) * 4)) /****************************************************************************/ /** * -* Read the Interrupt Clear-Enable Register offset for an interrupt ID +* Reads the Interrupt Clear-Enable Register offset for an interrupt ID. * -* @param Register is the register offset for the clear/enable bank. -* @param InterruptID is the interrupt number. +* @param Register Register offset for the clear/enable bank. +* @param InterruptID Interrupt number. * * @return The 32-bit value of the offset * -* @note * *****************************************************************************/ #define XSCUGIC_EN_DIS_OFFSET_CALC(Register, InterruptID) \ @@ -670,16 +671,15 @@ extern "C" { /****************************************************************************/ /** * -* Read the given Intc register. +* Reads the given Intc register. * -* @param BaseAddress is the base address of the device. -* @param RegOffset is the register offset to be read +* @param BaseAddress Base address of the device. +* @param RegOffset Register offset to be read. * * @return The 32-bit value of the register * -* @note -* C-style signature: -* u32 XScuGic_ReadReg(u32 BaseAddress, u32 RegOffset) +* @note C-style signature: +* u32 XScuGic_ReadReg(u32 BaseAddress, u32 RegOffset) * *****************************************************************************/ #define XScuGic_ReadReg(BaseAddress, RegOffset) \ @@ -688,16 +688,15 @@ extern "C" { /****************************************************************************/ /** * -* Read the given Intc register. +* Reads the given Intc register. * -* @param BaseAddress is the base address of the device. -* @param RegOffset is the register offset to be read +* @param BaseAddress Base address of the device. +* @param RegOffset Register offset to be read. * * @return The 64-bit value of the register * -* @note -* C-style signature: -* u32 XScuGic_ReadReg64(UINTPTR BaseAddress, u32 RegOffset) +* @note C-style signature: +* u32 XScuGic_ReadReg64(UINTPTR BaseAddress, u32 RegOffset) * *****************************************************************************/ #define XScuGic_ReadReg64(BaseAddress, RegOffset) \ @@ -706,17 +705,16 @@ extern "C" { /****************************************************************************/ /** * -* Write the given Intc register. +* Writes the given Intc register. * -* @param BaseAddress is the base address of the device. -* @param RegOffset is the register offset to be written -* @param Data is the 32-bit value to write to the register +* @param BaseAddress Base address of the device. +* @param RegOffset Register offset to be written +* @param Data 32-bit value to write to the register * * @return None. * -* @note -* C-style signature: -* void XScuGic_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data) +* @note C-style signature: +* void XScuGic_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data) * *****************************************************************************/ #define XScuGic_WriteReg(BaseAddress, RegOffset, Data) \ diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/scugic/src/xscugic_intr.c b/bsp_z7/ps7_cortexa9_0/libsrc/scugic/src/xscugic_intr.c index 477961e..8cb15ec 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/scugic/src/xscugic_intr.c +++ b/bsp_z7/ps7_cortexa9_0/libsrc/scugic/src/xscugic_intr.c @@ -1,6 +1,6 @@ /****************************************************************************** * Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved. -* Copyright (c) 2022 Advanced Micro Devices, Inc. All Rights Reserved. +* Copyright (c) 2022 - 2024 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -8,22 +8,22 @@ /** * * @file xscugic_intr.c -* @addtogroup scugic Overview +* @addtogroup scugic_api SCUGIC APIs * @{ * -* This file contains the interrupt processing for the driver for the Xilinx -* Interrupt Controller. The interrupt processing is partitioned separately such -* that users are not required to use the provided interrupt processing. This +* The xscugic_intr.c file contains the interrupt processing for the driver for the +* Interrupt Controller. The interrupt processing is partitioned separately such +* that users are not required to use the provided interrupt processing. This * file requires other files of the driver to be linked in also. * -* The interrupt handler, XScuGic_InterruptHandler, uses an input argument which +* The interrupt handler XScuGic_InterruptHandler uses an input argument which * is an instance pointer to an interrupt controller driver such that multiple -* interrupt controllers can be supported. This handler requires the calling +* interrupt controllers can be supported. This handler requires the calling * function to pass it the appropriate argument, so another level of indirection -* may be required. +* can be required. * -* The interrupt processing may be used by connecting the interrupt handler to -* the interrupt system. The handler does not save and restore the processor +* The interrupt processing is used by connecting the interrupt handler to +* the interrupt system. The handler does not save and restore the processor * context but only handles the processing of the Interrupt Controller. The user * is encouraged to supply their own interrupt handler when performance tuning is * deemed necessary. @@ -49,7 +49,7 @@ * This driver assumes that the context of the processor has been saved prior to * the calling of the Interrupt Controller interrupt handler and then restored * after the handler returns. This requires either the running RTOS to save the -* state of the machine or that a wrapper be used as the destination of the +* state of the machine or a wrapper be used as the destination of the * interrupt vector to save the state of the processor and restore the state * after the interrupt handler returns. * @@ -85,11 +85,10 @@ * calling an interrupt handler. * * -* @param InstancePtr is a pointer to the XScuGic instance. +* @param InstancePtr Pointer to the XScuGic instance. * * @return None. * -* @note None. * ******************************************************************************/ void XScuGic_InterruptHandler(XScuGic *InstancePtr) diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/scugic/src/xscugic_selftest.c b/bsp_z7/ps7_cortexa9_0/libsrc/scugic/src/xscugic_selftest.c index 94b29f9..f3ced40 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/scugic/src/xscugic_selftest.c +++ b/bsp_z7/ps7_cortexa9_0/libsrc/scugic/src/xscugic_selftest.c @@ -1,6 +1,6 @@ /****************************************************************************** * Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved. -* Copyright (c) 2022 Advanced Micro Devices, Inc. All Rights Reserved. +* Copyright (C) 2022 - 2024 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -8,10 +8,12 @@ /** * * @file xscugic_selftest.c -* @addtogroup scugic Overview +* @addtogroup scugic_api SCUGIC APIs * @{ * -* Contains diagnostic self-test functions for the XScuGic driver. +* The xscugic_selftest.c file contains diagnostic self-test functions for the XScuGic driver. +* +* * 
 * MODIFICATION HISTORY:
 *
@@ -21,7 +23,8 @@
 * 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
 * 3.10  mus  07/17/18 Updated file to fix the various coding style issues
 *                     reported by checkpatch. It fixes CR#1006344.
-*
+* 5.2   ml   03/02/23 Add description to fix Doxygen warnings.
+* 5.2   ml   09/07/23 Added comments to fix HIS COMF violations.
 *
* ******************************************************************************/ @@ -34,7 +37,7 @@ /************************** Constant Definitions *****************************/ -#define XSCUGIC_PCELL_ID 0xB105F00DU +#define XSCUGIC_PCELL_ID 0xB105F00DU /**< PCELL ID value */ /**************************** Type Definitions *******************************/ @@ -49,17 +52,16 @@ /*****************************************************************************/ /** * -* Run a self-test on the driver/device. This test reads the ID registers and +* Runs a self-test on the driver/device. This test reads the ID registers and * compares them. * -* @param InstancePtr is a pointer to the XScuGic instance. +* @param InstancePtr Pointer to the XScuGic instance. * * @return * * -XST_SUCCESS if self-test is successful. * -XST_FAILURE if the self-test is not successful. * -* @note None. * ******************************************************************************/ s32 XScuGic_SelfTest(XScuGic *InstancePtr) @@ -69,7 +71,7 @@ s32 XScuGic_SelfTest(XScuGic *InstancePtr) s32 Status; /* - * Assert the arguments + * Validate the input arguments */ Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); @@ -79,8 +81,8 @@ s32 XScuGic_SelfTest(XScuGic *InstancePtr) */ for (Index = 0U; Index <= 3U; Index++) { RegValue1 |= XScuGic_DistReadReg(InstancePtr, - ((u32)XSCUGIC_PCELLID_OFFSET + (Index * 4U))) << - (Index * 8U); + ((u32)XSCUGIC_PCELLID_OFFSET + (Index * 4U))) << + (Index * 8U); } if (XSCUGIC_PCELL_ID != RegValue1) { @@ -88,6 +90,7 @@ s32 XScuGic_SelfTest(XScuGic *InstancePtr) } else { Status = XST_SUCCESS; } + /* Return statement */ return Status; } /** @} */ diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/scugic/src/xscugic_sinit.c b/bsp_z7/ps7_cortexa9_0/libsrc/scugic/src/xscugic_sinit.c index 50101cf..1f7ce42 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/scugic/src/xscugic_sinit.c +++ b/bsp_z7/ps7_cortexa9_0/libsrc/scugic/src/xscugic_sinit.c @@ -1,6 +1,6 @@ /****************************************************************************** * Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved. -* Copyright (c) 2022 Advanced Micro Devices, Inc. All Rights Reserved. +* Copyright (C) 2022 - 2024 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -8,11 +8,11 @@ /** * * @file xscugic_sinit.c -* @addtogroup scugic Overview +* @addtogroup scugic_api SCUGIC APIs * @{ * -* Contains static init functions for the XScuGic driver for the Interrupt -* Controller. See xscugic.h for a detailed description of the driver. +* The xscugic_sinit.c contains static init functions for the XScuGic driver for the Interrupt +* Controller. * * 
 * MODIFICATION HISTORY:
@@ -25,7 +25,8 @@
 *                     reported by checkpatch. It fixes CR#1006344.
 * 4.6	sk   08/05/21 Remove XScuGic_Config variable definition to fix
 * 		      misrac violation.
-*
+* 5.2   ml   03/03/23 Add description to fix Doxygen warnings.
+* 5.2   ml   09/07/23 Added comments to fix HIS COMF violations.
 *
* ******************************************************************************/ @@ -34,8 +35,10 @@ #include "xil_types.h" #include "xil_assert.h" -#include "xparameters.h" #include "xscugic.h" +#ifndef SDT +#include "xparameters.h" +#endif /************************** Constant Definitions *****************************/ @@ -56,40 +59,82 @@ * Looks up the device configuration based on the unique device ID. A table * contains the configuration info for each device in the system. * -* @param DeviceId is the unique identifier for a device. +* @param DeviceId Unique identifier for a device. * * @return A pointer to the XScuGic configuration structure for the -* specified device, or NULL if the device was not found. +* specified device, or NULL if the device is not found. * -* @note None. * ******************************************************************************/ +#ifndef SDT XScuGic_Config *XScuGic_LookupConfig(u16 DeviceId) { XScuGic_Config *CfgPtr = NULL; u32 Index; + /* + * checks the device Id in configuration table + * whether it matches or not + */ for (Index = 0U; Index < (u32)XPAR_SCUGIC_NUM_INSTANCES; Index++) { if (XScuGic_ConfigTable[Index].DeviceId == DeviceId) { CfgPtr = &XScuGic_ConfigTable[Index]; break; } } - + /* Return statement */ return (XScuGic_Config *)CfgPtr; } +/*****************************************************************************/ +/** +* +* Looks up the device configuration based on the BaseAddress. The return value +* will refer to an entry in the device configuration table defined in the +* xscugic_g.c file. +* +* @param BaseAddress Base address of the device. +* +* @return A pointer to the XScuGic configuration structure for the +* specified device, or NULL if the device is not found. +* +* +******************************************************************************/ XScuGic_Config *XScuGic_LookupConfigBaseAddr(UINTPTR BaseAddress) { - XScuGic_Config *CfgPtr = NULL; - u32 Index; + XScuGic_Config *CfgPtr = NULL; + u32 Index; - for (Index = 0U; Index < (u32)XPAR_SCUGIC_NUM_INSTANCES; Index++) { - if (XScuGic_ConfigTable[Index].DistBaseAddress == BaseAddress) { - CfgPtr = &XScuGic_ConfigTable[Index]; - break; - } - } - return (XScuGic_Config *)CfgPtr; + /* + * checks the BaseAddress in configuration table + * whether it matches or not + */ + for (Index = 0U; Index < (u32)XPAR_SCUGIC_NUM_INSTANCES; Index++) { + if (XScuGic_ConfigTable[Index].DistBaseAddress == BaseAddress) { + CfgPtr = &XScuGic_ConfigTable[Index]; + break; + } + } + /* Return statement */ + return (XScuGic_Config *)CfgPtr; } +#else +XScuGic_Config *XScuGic_LookupConfig(UINTPTR BaseAddress) +{ + XScuGic_Config *CfgPtr = NULL; + u32 Index; + + /* checks the BaseAddress in configuration table + * whether it matches or not + */ + for (Index = 0U; XScuGic_ConfigTable[Index].Name != NULL; Index++) { + if ((XScuGic_ConfigTable[Index].DistBaseAddress == BaseAddress) || !BaseAddress) { + CfgPtr = &XScuGic_ConfigTable[Index]; + break; + } + } + /* Return statement */ + return (XScuGic_Config *)CfgPtr; +} +#endif /** @} */ diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/scutimer/src/xscutimer.c b/bsp_z7/ps7_cortexa9_0/libsrc/scutimer/src/xscutimer.c index 8cdf4c3..96584cb 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/scutimer/src/xscutimer.c +++ b/bsp_z7/ps7_cortexa9_0/libsrc/scutimer/src/xscutimer.c @@ -1,5 +1,6 @@ /****************************************************************************** * Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved. +* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -7,7 +8,7 @@ /** * * @file xscutimer.c -* @addtogroup scutimer_v2_4 +* @addtogroup scutimer Overview * @{ * * Contains the implementation of interface functions of the SCU Timer driver. @@ -20,6 +21,7 @@ * ----- --- -------- --------------------------------------------- * 1.00a nm 03/10/10 First release * 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance. +* 2.5 dp 07/11/23 Add Support for system device tree flow * * ******************************************************************************/ @@ -58,7 +60,7 @@ * ******************************************************************************/ s32 XScuTimer_CfgInitialize(XScuTimer *InstancePtr, - XScuTimer_Config *ConfigPtr, u32 EffectiveAddress) + XScuTimer_Config *ConfigPtr, u32 EffectiveAddress) { s32 Status; Xil_AssertNonvoid(InstancePtr != NULL); @@ -74,7 +76,9 @@ s32 XScuTimer_CfgInitialize(XScuTimer *InstancePtr, /* * Copy configuration into the instance structure. */ +#ifndef SDT InstancePtr->Config.DeviceId = ConfigPtr->DeviceId; +#endif /* * Save the base address pointer such that the registers of the block @@ -93,9 +97,8 @@ s32 XScuTimer_CfgInitialize(XScuTimer *InstancePtr, InstancePtr->Config.IntrParent = ConfigPtr->IntrParent; #endif - Status =(s32)XST_SUCCESS; - } - else { + Status = (s32)XST_SUCCESS; + } else { Status = (s32)XST_DEVICE_IS_STARTED; } return Status; @@ -124,7 +127,7 @@ void XScuTimer_Start(XScuTimer *InstancePtr) * Read the contents of the Control register. */ Register = XScuTimer_ReadReg(InstancePtr->Config.BaseAddr, - XSCUTIMER_CONTROL_OFFSET); + XSCUTIMER_CONTROL_OFFSET); /* * Set the 'timer enable' bit in the register. @@ -135,7 +138,7 @@ void XScuTimer_Start(XScuTimer *InstancePtr) * Update the Control register with the new value. */ XScuTimer_WriteReg(InstancePtr->Config.BaseAddr, - XSCUTIMER_CONTROL_OFFSET, Register); + XSCUTIMER_CONTROL_OFFSET, Register); /* * Indicate that the device is started. @@ -166,7 +169,7 @@ void XScuTimer_Stop(XScuTimer *InstancePtr) * Read the contents of the Control register. */ Register = XScuTimer_ReadReg(InstancePtr->Config.BaseAddr, - XSCUTIMER_CONTROL_OFFSET); + XSCUTIMER_CONTROL_OFFSET); /* * Clear the 'timer enable' bit in the register. @@ -177,7 +180,7 @@ void XScuTimer_Stop(XScuTimer *InstancePtr) * Update the Control register with the new value. */ XScuTimer_WriteReg(InstancePtr->Config.BaseAddr, - XSCUTIMER_CONTROL_OFFSET, Register); + XSCUTIMER_CONTROL_OFFSET, Register); /* * Indicate that the device is stopped. @@ -211,7 +214,7 @@ void XScuTimer_SetPrescaler(XScuTimer *InstancePtr, u8 PrescalerValue) * Read the Timer control register. */ ControlReg = XScuTimer_ReadReg(InstancePtr->Config.BaseAddr, - XSCUTIMER_CONTROL_OFFSET); + XSCUTIMER_CONTROL_OFFSET); /* * Clear all of the prescaler control bits in the register. @@ -227,7 +230,7 @@ void XScuTimer_SetPrescaler(XScuTimer *InstancePtr, u8 PrescalerValue) * Write the register with the new values. */ XScuTimer_WriteReg(InstancePtr->Config.BaseAddr, - XSCUTIMER_CONTROL_OFFSET, ControlReg); + XSCUTIMER_CONTROL_OFFSET, ControlReg); } /*****************************************************************************/ @@ -256,7 +259,7 @@ u8 XScuTimer_GetPrescaler(XScuTimer *InstancePtr) * Read the Timer control register. */ ControlReg = XScuTimer_ReadReg(InstancePtr->Config.BaseAddr, - XSCUTIMER_CONTROL_OFFSET); + XSCUTIMER_CONTROL_OFFSET); ControlReg &= XSCUTIMER_CONTROL_PRESCALER_MASK; return (u8)(ControlReg >> XSCUTIMER_CONTROL_PRESCALER_SHIFT); diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/scutimer/src/xscutimer.h b/bsp_z7/ps7_cortexa9_0/libsrc/scutimer/src/xscutimer.h index bdce1c6..008b900 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/scutimer/src/xscutimer.h +++ b/bsp_z7/ps7_cortexa9_0/libsrc/scutimer/src/xscutimer.h @@ -1,5 +1,6 @@ /****************************************************************************** * Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved. +* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -7,7 +8,7 @@ /** * * @file xscutimer.h -* @addtogroup scutimer_v2_4 +* @addtogroup scutimer Overview * @{ * @details * @@ -82,6 +83,7 @@ * 2.3 mus 08/31/20 Updated makefile to support parallel make and * incremental builds, it would help to reduce compilation * time. +* 2.5 dp 07/11/23 Add support for system device tree flow * * ******************************************************************************/ @@ -106,7 +108,11 @@ extern "C" { * This typedef contains configuration information for the device. */ typedef struct { +#ifndef SDT u16 DeviceId; /**< Unique ID of device */ +#else + char *Name; +#endif u32 BaseAddr; /**< Base address of the device */ #ifdef XIL_INTERRUPT u32 IntrId; @@ -145,9 +151,9 @@ typedef struct { ******************************************************************************/ #define XScuTimer_IsExpired(InstancePtr) \ ((XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \ - XSCUTIMER_ISR_OFFSET) & \ - XSCUTIMER_ISR_EVENT_FLAG_MASK) == \ - XSCUTIMER_ISR_EVENT_FLAG_MASK) + XSCUTIMER_ISR_OFFSET) & \ + XSCUTIMER_ISR_EVENT_FLAG_MASK) == \ + XSCUTIMER_ISR_EVENT_FLAG_MASK) /****************************************************************************/ /** @@ -165,8 +171,8 @@ typedef struct { ******************************************************************************/ #define XScuTimer_RestartTimer(InstancePtr) \ XScuTimer_LoadTimer((InstancePtr), \ - XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \ - XSCUTIMER_LOAD_OFFSET)) + XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \ + XSCUTIMER_LOAD_OFFSET)) /****************************************************************************/ /** @@ -186,7 +192,7 @@ typedef struct { ******************************************************************************/ #define XScuTimer_LoadTimer(InstancePtr, Value) \ XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \ - XSCUTIMER_LOAD_OFFSET, (Value)) + XSCUTIMER_LOAD_OFFSET, (Value)) /****************************************************************************/ /** @@ -204,7 +210,7 @@ typedef struct { ******************************************************************************/ #define XScuTimer_GetCounterValue(InstancePtr) \ XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \ - XSCUTIMER_COUNTER_OFFSET) + XSCUTIMER_COUNTER_OFFSET) /****************************************************************************/ /** @@ -221,10 +227,10 @@ typedef struct { ******************************************************************************/ #define XScuTimer_EnableAutoReload(InstancePtr) \ XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \ - XSCUTIMER_CONTROL_OFFSET, \ - (XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \ - XSCUTIMER_CONTROL_OFFSET) | \ - XSCUTIMER_CONTROL_AUTO_RELOAD_MASK)) + XSCUTIMER_CONTROL_OFFSET, \ + (XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \ + XSCUTIMER_CONTROL_OFFSET) | \ + XSCUTIMER_CONTROL_AUTO_RELOAD_MASK)) /****************************************************************************/ /** @@ -241,10 +247,10 @@ typedef struct { ******************************************************************************/ #define XScuTimer_DisableAutoReload(InstancePtr) \ XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \ - XSCUTIMER_CONTROL_OFFSET, \ - (XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \ - XSCUTIMER_CONTROL_OFFSET) & \ - ~(XSCUTIMER_CONTROL_AUTO_RELOAD_MASK))) + XSCUTIMER_CONTROL_OFFSET, \ + (XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \ + XSCUTIMER_CONTROL_OFFSET) & \ + ~(XSCUTIMER_CONTROL_AUTO_RELOAD_MASK))) /****************************************************************************/ /** @@ -261,10 +267,10 @@ typedef struct { ******************************************************************************/ #define XScuTimer_EnableInterrupt(InstancePtr) \ XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \ - XSCUTIMER_CONTROL_OFFSET, \ - (XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \ - XSCUTIMER_CONTROL_OFFSET) | \ - XSCUTIMER_CONTROL_IRQ_ENABLE_MASK)) + XSCUTIMER_CONTROL_OFFSET, \ + (XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \ + XSCUTIMER_CONTROL_OFFSET) | \ + XSCUTIMER_CONTROL_IRQ_ENABLE_MASK)) /****************************************************************************/ /** @@ -281,10 +287,10 @@ typedef struct { ******************************************************************************/ #define XScuTimer_DisableInterrupt(InstancePtr) \ XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \ - XSCUTIMER_CONTROL_OFFSET, \ - (XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \ - XSCUTIMER_CONTROL_OFFSET) & \ - ~(XSCUTIMER_CONTROL_IRQ_ENABLE_MASK))) + XSCUTIMER_CONTROL_OFFSET, \ + (XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \ + XSCUTIMER_CONTROL_OFFSET) & \ + ~(XSCUTIMER_CONTROL_IRQ_ENABLE_MASK))) /*****************************************************************************/ /** @@ -301,7 +307,7 @@ typedef struct { ******************************************************************************/ #define XScuTimer_GetInterruptStatus(InstancePtr) \ XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \ - XSCUTIMER_ISR_OFFSET) + XSCUTIMER_ISR_OFFSET) /*****************************************************************************/ /** @@ -318,14 +324,18 @@ typedef struct { ******************************************************************************/ #define XScuTimer_ClearInterruptStatus(InstancePtr) \ XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \ - XSCUTIMER_ISR_OFFSET, XSCUTIMER_ISR_EVENT_FLAG_MASK) + XSCUTIMER_ISR_OFFSET, XSCUTIMER_ISR_EVENT_FLAG_MASK) /************************** Function Prototypes ******************************/ /* * Lookup configuration in xscutimer_sinit.c */ +#ifndef SDT XScuTimer_Config *XScuTimer_LookupConfig(u16 DeviceId); +#else +XScuTimer_Config *XScuTimer_LookupConfig(UINTPTR BaseAddr); +#endif /* * Selftest function in xscutimer_selftest.c diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/scutimer/src/xscutimer_g.c b/bsp_z7/ps7_cortexa9_0/libsrc/scutimer/src/xscutimer_g.c index 75461ce..0ad6dc4 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/scutimer/src/xscutimer_g.c +++ b/bsp_z7/ps7_cortexa9_0/libsrc/scutimer/src/xscutimer_g.c @@ -1,5 +1,6 @@ /****************************************************************************** * Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved. +* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -7,7 +8,7 @@ /** * * @file xscutimer_g.c -* @addtogroup scutimer_v2_4 +* @addtogroup scutimer Overview * @{ * * This file contains a table that specifies the configuration of the SCU diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/scutimer/src/xscutimer_hw.h b/bsp_z7/ps7_cortexa9_0/libsrc/scutimer/src/xscutimer_hw.h index c34acd1..8eb1875 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/scutimer/src/xscutimer_hw.h +++ b/bsp_z7/ps7_cortexa9_0/libsrc/scutimer/src/xscutimer_hw.h @@ -1,5 +1,6 @@ /****************************************************************************** * Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved. +* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -7,7 +8,7 @@ /** * * @file xscutimer_hw.h -* @addtogroup scutimer_v2_4 +* @addtogroup scutimer Overview * @{ * * This file contains the hardware interface to the Timer. diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/scutimer/src/xscutimer_selftest.c b/bsp_z7/ps7_cortexa9_0/libsrc/scutimer/src/xscutimer_selftest.c index 609c217..3d6f9cf 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/scutimer/src/xscutimer_selftest.c +++ b/bsp_z7/ps7_cortexa9_0/libsrc/scutimer/src/xscutimer_selftest.c @@ -1,5 +1,6 @@ /****************************************************************************** * Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved. +* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -7,7 +8,7 @@ /** * * @file xscutimer_selftest.c -* @addtogroup scutimer_v2_4 +* @addtogroup scutimer Overview * @{ * * Contains diagnostic self-test functions for the XScuTimer driver. @@ -74,10 +75,10 @@ s32 XScuTimer_SelfTest(XScuTimer *InstancePtr) * Save the contents of the Control Register and stop the timer. */ CtrlOrig = XScuTimer_ReadReg(InstancePtr->Config.BaseAddr, - XSCUTIMER_CONTROL_OFFSET); + XSCUTIMER_CONTROL_OFFSET); Register = CtrlOrig & (u32)(~XSCUTIMER_CONTROL_ENABLE_MASK); XScuTimer_WriteReg(InstancePtr->Config.BaseAddr, - XSCUTIMER_CONTROL_OFFSET, Register); + XSCUTIMER_CONTROL_OFFSET, Register); /* * Save the contents of the Load Register. @@ -85,17 +86,17 @@ s32 XScuTimer_SelfTest(XScuTimer *InstancePtr) * compare it with the written value. */ LoadOrig = XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, - XSCUTIMER_LOAD_OFFSET); + XSCUTIMER_LOAD_OFFSET); XScuTimer_LoadTimer(InstancePtr, XSCUTIMER_SELFTEST_VALUE); Register = XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, - XSCUTIMER_LOAD_OFFSET); + XSCUTIMER_LOAD_OFFSET); /* * Restore the contents of the Load Register and Control Register. */ XScuTimer_LoadTimer(InstancePtr, LoadOrig); XScuTimer_WriteReg(InstancePtr->Config.BaseAddr, - XSCUTIMER_CONTROL_OFFSET, CtrlOrig); + XSCUTIMER_CONTROL_OFFSET, CtrlOrig); /* * Return a Failure if the contents of the Load Register do not @@ -103,8 +104,7 @@ s32 XScuTimer_SelfTest(XScuTimer *InstancePtr) */ if (Register != XSCUTIMER_SELFTEST_VALUE) { Status = (s32)XST_FAILURE; - } - else { + } else { Status = (s32)XST_SUCCESS; } diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/scutimer/src/xscutimer_sinit.c b/bsp_z7/ps7_cortexa9_0/libsrc/scutimer/src/xscutimer_sinit.c index f68200e..a5335ee 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/scutimer/src/xscutimer_sinit.c +++ b/bsp_z7/ps7_cortexa9_0/libsrc/scutimer/src/xscutimer_sinit.c @@ -1,5 +1,6 @@ /****************************************************************************** * Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved. +* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -7,7 +8,7 @@ /** * * @file xscutimer_sinit.c -* @addtogroup scutimer_v2_4 +* @addtogroup scutimer Overview * @{ * * This file contains method for static initialization (compile-time) of the @@ -20,6 +21,7 @@ * ----- --- -------- --------------------------------------------- * 1.00a nm 03/10/10 First release * 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance. +* 2.5 dp 07/11/23 Add Support for system device tree flow * * ******************************************************************************/ @@ -27,7 +29,9 @@ /***************************** Include Files *********************************/ #include "xscutimer.h" +#ifndef SDT #include "xparameters.h" +#endif /************************** Constant Definitions *****************************/ @@ -36,7 +40,11 @@ /***************** Macros (Inline Functions) Definitions *********************/ /************************** Variable Definitions ****************************/ +#ifndef SDT extern XScuTimer_Config XScuTimer_ConfigTable[XPAR_XSCUTIMER_NUM_INSTANCES]; +#else +extern XScuTimer_Config XScuTimer_ConfigTable[]; +#endif /************************** Function Prototypes ******************************/ @@ -53,6 +61,7 @@ extern XScuTimer_Config XScuTimer_ConfigTable[XPAR_XSCUTIMER_NUM_INSTANCES]; * @note None. * ******************************************************************************/ +#ifndef SDT XScuTimer_Config *XScuTimer_LookupConfig(u16 DeviceId) { XScuTimer_Config *CfgPtr = NULL; @@ -67,4 +76,20 @@ XScuTimer_Config *XScuTimer_LookupConfig(u16 DeviceId) return (XScuTimer_Config *)CfgPtr; } +#else +XScuTimer_Config *XScuTimer_LookupConfig(UINTPTR BaseAddr) +{ + XScuTimer_Config *CfgPtr = NULL; + u32 Index; + + for (Index = 0U; XScuTimer_ConfigTable[Index].Name != NULL; Index++) { + if (XScuTimer_ConfigTable[Index].BaseAddr == BaseAddr) { + CfgPtr = &XScuTimer_ConfigTable[Index]; + break; + } + } + + return (XScuTimer_Config *)CfgPtr; +} +#endif /** @} */ diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/scuwdt/src/xscuwdt.c b/bsp_z7/ps7_cortexa9_0/libsrc/scuwdt/src/xscuwdt.c index 1c392ec..ce9ec2a 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/scuwdt/src/xscuwdt.c +++ b/bsp_z7/ps7_cortexa9_0/libsrc/scuwdt/src/xscuwdt.c @@ -1,5 +1,6 @@ /****************************************************************************** -* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved. +* Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -7,7 +8,7 @@ /** * * @file xscuwdt.c -* @addtogroup scuwdt_v2_4 +* @addtogroup Overview * @{ * * Contains the implementation of interface functions of the XScuWdt driver. @@ -20,6 +21,7 @@ * ----- --- -------- --------------------------------------------- * 1.00a sdm 01/15/10 First release * 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance. +* 2.5 asa 07/18/23 Made updates for workflow decoupling flow. * * ******************************************************************************/ @@ -58,7 +60,7 @@ * ******************************************************************************/ s32 XScuWdt_CfgInitialize(XScuWdt *InstancePtr, - XScuWdt_Config *ConfigPtr, u32 EffectiveAddress) + XScuWdt_Config *ConfigPtr, u32 EffectiveAddress) { s32 CfgStatus; Xil_AssertNonvoid(InstancePtr != NULL); @@ -73,12 +75,13 @@ s32 XScuWdt_CfgInitialize(XScuWdt *InstancePtr, */ if (InstancePtr->IsStarted == XIL_COMPONENT_IS_STARTED) { CfgStatus = (s32)XST_DEVICE_IS_STARTED; - } - else { + } else { /* * Copy configuration into instance. */ +#ifndef SDT InstancePtr->Config.DeviceId = ConfigPtr->DeviceId; +#endif /* * Save the base address pointer such that the registers of the block @@ -97,7 +100,7 @@ s32 XScuWdt_CfgInitialize(XScuWdt *InstancePtr, */ InstancePtr->IsReady = XIL_COMPONENT_IS_READY; - CfgStatus =(s32)XST_SUCCESS; + CfgStatus = (s32)XST_SUCCESS; } return CfgStatus; } @@ -128,7 +131,7 @@ void XScuWdt_Start(XScuWdt *InstancePtr) * Read the contents of the Control register. */ Register = XScuWdt_ReadReg(InstancePtr->Config.BaseAddr, - XSCUWDT_CONTROL_OFFSET); + XSCUWDT_CONTROL_OFFSET); /* * Set the 'watchdog enable' bit in the register. @@ -139,7 +142,7 @@ void XScuWdt_Start(XScuWdt *InstancePtr) * Update the Control register with the new value. */ XScuWdt_WriteReg(InstancePtr->Config.BaseAddr, - XSCUWDT_CONTROL_OFFSET, Register); + XSCUWDT_CONTROL_OFFSET, Register); /* * Indicate that the device is started. @@ -170,7 +173,7 @@ void XScuWdt_Stop(XScuWdt *InstancePtr) * Read the contents of the Control register. */ Register = XScuWdt_ReadReg(InstancePtr->Config.BaseAddr, - XSCUWDT_CONTROL_OFFSET); + XSCUWDT_CONTROL_OFFSET); /* * Clear the 'watchdog enable' bit in the register. @@ -181,7 +184,7 @@ void XScuWdt_Stop(XScuWdt *InstancePtr) * Update the Control register with the new value. */ XScuWdt_WriteReg(InstancePtr->Config.BaseAddr, - XSCUWDT_CONTROL_OFFSET, Register); + XSCUWDT_CONTROL_OFFSET, Register); /* * Indicate that the device is stopped. diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/scuwdt/src/xscuwdt.h b/bsp_z7/ps7_cortexa9_0/libsrc/scuwdt/src/xscuwdt.h index 8d11ff8..9130e4d 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/scuwdt/src/xscuwdt.h +++ b/bsp_z7/ps7_cortexa9_0/libsrc/scuwdt/src/xscuwdt.h @@ -1,5 +1,6 @@ /****************************************************************************** -* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved. +* Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -7,7 +8,7 @@ /** * * @file xscuwdt.h -* @addtogroup scuwdt_v2_4 +* @addtogroup Overview * @{ * @details * @@ -106,6 +107,8 @@ * time. * 2.3 sne 09/16/20 Fixed MISRA-C violations. * 2.4 sne 02/04/21 Fixed Doxygen warnings. +* 2.5 asa 07/18/23 Added support for system device tree based workflow +* decoupling flow. * * ******************************************************************************/ @@ -129,8 +132,18 @@ extern "C" { * This typedef contains configuration information for the device. */ typedef struct { +#ifndef SDT u16 DeviceId; /**< Unique ID of device */ - u32 BaseAddr; /**< Base address of the device */ +#else + char *Name; /**< Unique name of the device */ +#endif + UINTPTR BaseAddr; /**< Register base address */ +#ifdef SDT + u32 IntrId; /** Bits[11:0] Interrupt-id Bits[15:12] + * trigger type and level flags */ + UINTPTR IntrParent; /** Bit[0] Interrupt parent type Bit[64/32:1] + * Parent base address */ +#endif } XScuWdt_Config; /** @@ -168,7 +181,7 @@ extern XScuWdt_Config XScuWdt_ConfigTable[]; #define XScuWdt_IsWdtExpired(InstancePtr) \ ((XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \ XSCUWDT_RST_STS_OFFSET) & \ - XSCUWDT_RST_STS_RESET_FLAG_MASK) == XSCUWDT_RST_STS_RESET_FLAG_MASK) + XSCUWDT_RST_STS_RESET_FLAG_MASK) == XSCUWDT_RST_STS_RESET_FLAG_MASK) /****************************************************************************/ /** @@ -189,7 +202,7 @@ extern XScuWdt_Config XScuWdt_ConfigTable[]; #define XScuWdt_IsTimerExpired(InstancePtr) \ ((XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \ XSCUWDT_ISR_OFFSET) & \ - XSCUWDT_ISR_EVENT_FLAG_MASK) == XSCUWDT_ISR_EVENT_FLAG_MASK) + XSCUWDT_ISR_EVENT_FLAG_MASK) == XSCUWDT_ISR_EVENT_FLAG_MASK) /****************************************************************************/ /** @@ -230,7 +243,7 @@ extern XScuWdt_Config XScuWdt_ConfigTable[]; ******************************************************************************/ #define XScuWdt_LoadWdt(InstancePtr, Value) \ XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \ - XSCUWDT_LOAD_OFFSET, (Value)) + XSCUWDT_LOAD_OFFSET, (Value)) /****************************************************************************/ /** @@ -250,7 +263,7 @@ extern XScuWdt_Config XScuWdt_ConfigTable[]; XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \ XSCUWDT_CONTROL_OFFSET, \ (XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \ - XSCUWDT_CONTROL_OFFSET) | \ + XSCUWDT_CONTROL_OFFSET) | \ (XSCUWDT_CONTROL_WD_MODE_MASK))) /****************************************************************************/ @@ -271,14 +284,14 @@ extern XScuWdt_Config XScuWdt_ConfigTable[]; * ******************************************************************************/ #define XScuWdt_SetTimerMode(InstancePtr) \ -{ \ - XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \ - XSCUWDT_DISABLE_OFFSET, \ - XSCUWDT_DISABLE_VALUE1); \ - XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \ - XSCUWDT_DISABLE_OFFSET, \ - XSCUWDT_DISABLE_VALUE2); \ -} + { \ + XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \ + XSCUWDT_DISABLE_OFFSET, \ + XSCUWDT_DISABLE_VALUE1); \ + XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \ + XSCUWDT_DISABLE_OFFSET, \ + XSCUWDT_DISABLE_VALUE2); \ + } /****************************************************************************/ /** @@ -332,14 +345,18 @@ extern XScuWdt_Config XScuWdt_ConfigTable[]; #define XScuWdt_EnableAutoReload(InstancePtr) \ XScuWdt_SetControlReg((InstancePtr), \ (XScuWdt_GetControlReg(InstancePtr) | \ - XSCUWDT_CONTROL_AUTO_RELOAD_MASK)) + XSCUWDT_CONTROL_AUTO_RELOAD_MASK)) /************************** Function Prototypes ******************************/ /* * Lookup configuration in xscuwdt_sinit.c. */ +#ifndef SDT XScuWdt_Config *XScuWdt_LookupConfig(u16 DeviceId); +#else +XScuWdt_Config *XScuWdt_LookupConfig(UINTPTR BaseAddress); +#endif /* * Selftest function in xscuwdt_selftest.c diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/scuwdt/src/xscuwdt_g.c b/bsp_z7/ps7_cortexa9_0/libsrc/scuwdt/src/xscuwdt_g.c index a8726a6..689e2c5 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/scuwdt/src/xscuwdt_g.c +++ b/bsp_z7/ps7_cortexa9_0/libsrc/scuwdt/src/xscuwdt_g.c @@ -1,5 +1,6 @@ /****************************************************************************** -* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved. +* Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -7,7 +8,7 @@ /** * * @file xscuwdt_g.c -* @addtogroup scuwdt_v2_4 +* @addtogroup Overview * @{ * * This file contains a table that specifies the configuration of the SCU diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/scuwdt/src/xscuwdt_hw.h b/bsp_z7/ps7_cortexa9_0/libsrc/scuwdt/src/xscuwdt_hw.h index 0cdfc1e..3c401ec 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/scuwdt/src/xscuwdt_hw.h +++ b/bsp_z7/ps7_cortexa9_0/libsrc/scuwdt/src/xscuwdt_hw.h @@ -1,5 +1,6 @@ /****************************************************************************** -* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved. +* Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -7,7 +8,7 @@ /** * * @file xscuwdt_hw.h -* @addtogroup scuwdt_v2_4 +* @addtogroup Overview * @{ * * This file contains the hardware interface to the Xilinx SCU private Watch Dog diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/scuwdt/src/xscuwdt_selftest.c b/bsp_z7/ps7_cortexa9_0/libsrc/scuwdt/src/xscuwdt_selftest.c index 4b5c4cd..41af1c7 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/scuwdt/src/xscuwdt_selftest.c +++ b/bsp_z7/ps7_cortexa9_0/libsrc/scuwdt/src/xscuwdt_selftest.c @@ -1,5 +1,6 @@ /****************************************************************************** -* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved. +* Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -7,7 +8,7 @@ /** * * @file xscuwdt_selftest.c -* @addtogroup scuwdt_v2_4 +* @addtogroup Overview * @{ * * Contains diagnostic self-test functions for the XScuWdt driver. @@ -95,8 +96,7 @@ s32 XScuWdt_SelfTest(XScuWdt *InstancePtr) if (Register == 0xFFFFFFFFU) { SelfTestStatus = (s32)XST_FAILURE; - } - else { + } else { SelfTestStatus = (s32)XST_SUCCESS; } diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/scuwdt/src/xscuwdt_sinit.c b/bsp_z7/ps7_cortexa9_0/libsrc/scuwdt/src/xscuwdt_sinit.c index a46afa7..20daf6b 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/scuwdt/src/xscuwdt_sinit.c +++ b/bsp_z7/ps7_cortexa9_0/libsrc/scuwdt/src/xscuwdt_sinit.c @@ -1,5 +1,6 @@ /****************************************************************************** -* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved. +* Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -7,7 +8,7 @@ /** * * @file xscuwdt_sinit.c -* @addtogroup scuwdt_v2_4 +* @addtogroup Overview * @{ * * This file contains method for static initialization (compile-time) of the @@ -20,6 +21,8 @@ * ----- --- -------- --------------------------------------------- * 1.00a sdm 01/15/10 First release * 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance. +* 2.5 asa 07/18/23 Made updates to support system device tree based +* workflow decoupling flow. * * ******************************************************************************/ @@ -27,6 +30,9 @@ /***************************** Include Files *********************************/ #include "xscuwdt.h" +#ifndef SDT +#include "xparameters.h" +#endif /************************** Constant Definitions *****************************/ @@ -49,6 +55,7 @@ * @note None. * ******************************************************************************/ +#ifndef SDT XScuWdt_Config *XScuWdt_LookupConfig(u16 DeviceId) { XScuWdt_Config *CfgPtr = NULL; @@ -63,4 +70,21 @@ XScuWdt_Config *XScuWdt_LookupConfig(u16 DeviceId) return (XScuWdt_Config *)CfgPtr; } +#else +XScuWdt_Config *XScuWdt_LookupConfig(UINTPTR BaseAddress) +{ + XScuWdt_Config *CfgPtr = NULL; + u32 Index; + + for (Index = 0U; XScuWdt_ConfigTable[Index].Name != NULL; Index++) { + if ((XScuWdt_ConfigTable[Index].BaseAddr == BaseAddress) || + !BaseAddress) { + CfgPtr = &XScuWdt_ConfigTable[Index]; + break; + } + } + + return (XScuWdt_Config *)CfgPtr; +} +#endif /** @} */ diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/sdps/src/xsdps.c b/bsp_z7/ps7_cortexa9_0/libsrc/sdps/src/xsdps.c index c4a23e8..7f92284 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/sdps/src/xsdps.c +++ b/bsp_z7/ps7_cortexa9_0/libsrc/sdps/src/xsdps.c @@ -1,6 +1,6 @@ /****************************************************************************** * Copyright (C) 2013 - 2022 Xilinx, Inc. All rights reserved. -* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved. +* Copyright (c) 2022 - 2024 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -8,7 +8,7 @@ /** * * @file xsdps.c -* @addtogroup sdps Overview +* @addtogroup sdps_api SDPS APIs * @{ * * Contains the interface functions of the XSdPs driver. @@ -90,6 +90,8 @@ * 4.0 sk 02/25/22 Add support for eMMC5.1. * sk 04/07/22 Add support to read custom tap delay values from design * for SD/eMMC. +* 4.2 ro 06/12/23 Added support for system device-tree flow. +* 4.3 ap 11/29/23 Add support for Sanitize feature. * * * @@ -109,21 +111,21 @@ /** * * @brief -* Initializes a specific XSdPs instance such that the driver is ready to use. +* Initializes a specific XSdPs instance so that the driver is ready to use. * * -* @param InstancePtr is a pointer to the XSdPs instance. -* @param ConfigPtr is a reference to a structure containing information +* @param InstancePtr Pointer to the XSdPs instance. +* @param ConfigPtr Reference to a structure containing information * about a specific SD device. This function initializes an * InstancePtr object for a specific device specified by the -* contents of Config. -* @param EffectiveAddr is the device base address in the virtual memory +* contents of Configuration. +* @param EffectiveAddr Device base address in the virtual memory * address space. The caller is responsible for keeping the address * mapping from EffectiveAddr to the device physical base address * unchanged once this function is invoked. Unexpected errors may * occur if the address mapping changes after this function is * called. If address translation is not used, use -* ConfigPtr->Config.BaseAddress for this device. +* ConfigPtr->Config. BaseAddress for this device. * * @return * - XST_SUCCESS if successful. @@ -131,15 +133,15 @@ * It must be stopped to re-initialize. * * @note This function initializes the host controller. -* Initial clock of 400KHz is set. -* Voltage of 3.3V is selected as that is supported by host. +* Initial clock of 400 KHz is set. +* Voltage of 3.3 V is selected as that is supported by host. * Interrupts status is enabled and signal disabled by default. * Default data direction is card to host and * 32 bit ADMA2 is selected. Default Block size is 512 bytes. * ******************************************************************************/ s32 XSdPs_CfgInitialize(XSdPs *InstancePtr, XSdPs_Config *ConfigPtr, - u32 EffectiveAddr) + UINTPTR EffectiveAddr) { s32 Status; @@ -157,7 +159,9 @@ s32 XSdPs_CfgInitialize(XSdPs *InstancePtr, XSdPs_Config *ConfigPtr, } /* Set some default values. */ +#ifndef SDT InstancePtr->Config.DeviceId = ConfigPtr->DeviceId; +#endif InstancePtr->Config.BaseAddress = EffectiveAddr; InstancePtr->Config.InputClockHz = ConfigPtr->InputClockHz; InstancePtr->Config.CardDetect = ConfigPtr->CardDetect; @@ -173,6 +177,7 @@ s32 XSdPs_CfgInitialize(XSdPs *InstancePtr, XSdPs_Config *ConfigPtr, InstancePtr->Config.OTapDly_DDR_Clk50 = ConfigPtr->OTapDly_DDR_Clk50; InstancePtr->Config.OTapDly_SDR_Clk100 = ConfigPtr->OTapDly_SDR_Clk100; InstancePtr->Config.OTapDly_SDR_Clk200 = ConfigPtr->OTapDly_SDR_Clk200; + InstancePtr->Config.OTapDly_DDR_Clk200 = ConfigPtr->OTapDly_DDR_Clk200; InstancePtr->SectorCount = 0U; InstancePtr->Mode = XSDPS_DEFAULT_SPEED_MODE; InstancePtr->OTapDelay = 0U; @@ -185,15 +190,15 @@ s32 XSdPs_CfgInitialize(XSdPs *InstancePtr, XSdPs_Config *ConfigPtr, /* Host Controller version is read. */ InstancePtr->HC_Version = - (u8)(XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, - XSDPS_HOST_CTRL_VER_OFFSET) & XSDPS_HC_SPEC_VER_MASK); + (u8)(XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, + XSDPS_HOST_CTRL_VER_OFFSET) & XSDPS_HC_SPEC_VER_MASK); /* * Read capabilities register and update it in Instance pointer. * It is sufficient to read this once on power on. */ InstancePtr->Host_Caps = XSdPs_ReadReg(InstancePtr->Config.BaseAddress, - XSDPS_CAPS_OFFSET); + XSDPS_CAPS_OFFSET); /* Reset the SD bus lines */ Status = XSdPs_ResetConfig(InstancePtr); @@ -219,10 +224,10 @@ RETURN_PATH: /** * * @brief -* Initialize Card with Identification mode sequence +* Initializes Card with Identification mode sequence * * -* @param InstancePtr is a pointer to the instance to be worked on. +* @param InstancePtr Pointer to the instance to be worked on. * * @return * - XST_SUCCESS if initialization was successful @@ -272,7 +277,8 @@ s32 XSdPs_CardInitialize(XSdPs *InstancePtr) Status = XST_FAILURE; goto RETURN_PATH; } - } else { + } + else { Status = XSdPs_MmcCardInitialize(InstancePtr); if (Status != XST_SUCCESS) { Status = XST_FAILURE; @@ -290,13 +296,13 @@ RETURN_PATH: /*****************************************************************************/ /** * @brief -* This function performs SD read in polled mode. +* Performs SD read in polled mode. * -* @param InstancePtr is a pointer to the instance to be worked on. -* @param Arg is the address passed by the user that is to be sent as +* @param InstancePtr Pointer to the instance to be worked on. +* @param Arg Address passed by the user that is to be sent as * argument along with the command. -* @param BlkCnt - Block count passed by the user. -* @param Buff - Pointer to the data buffer for a DMA transfer. +* @param BlkCnt Block count passed by the user. +* @param Buff Pointer to the data buffer for a DMA transfer. * * @return * - XST_SUCCESS if initialization was successful @@ -343,7 +349,7 @@ s32 XSdPs_ReadPolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, u8 *Buff) if (InstancePtr->Config.IsCacheCoherent == 0U) { Xil_DCacheInvalidateRange((INTPTR)Buff, - ((INTPTR)BlkCnt * (INTPTR)InstancePtr->BlkSize)); + ((INTPTR)BlkCnt * (INTPTR)InstancePtr->BlkSize)); } RETURN_PATH: @@ -356,13 +362,13 @@ RETURN_PATH: /*****************************************************************************/ /** * @brief -* This function performs SD write in polled mode. +* Performs SD write in polled mode. * -* @param InstancePtr is a pointer to the instance to be worked on. -* @param Arg is the address passed by the user that is to be sent as +* @param InstancePtr Pointer to the instance to be worked on. +* @param Arg Address passed by the user that is to be sent as * argument along with the command. -* @param BlkCnt - Block count passed by the user. -* @param Buff - Pointer to the data buffer for a DMA transfer. +* @param BlkCnt Block count passed by the user. +* @param Buff Pointer to the data buffer for a DMA transfer. * * @return * - XST_SUCCESS if initialization was successful @@ -418,14 +424,13 @@ RETURN_PATH: /** * * @brief -* API to idle the SDIO Interface +* API to idle the SDIO Interface. * * -* @param InstancePtr is a pointer to the XSdPs instance. +* @param InstancePtr Pointer to the XSdPs instance. * * @return None * -* @note None. * ******************************************************************************/ s32 XSdPs_Idle(XSdPs *InstancePtr) @@ -441,8 +446,8 @@ s32 XSdPs_Idle(XSdPs *InstancePtr) /* Check if the bus is idle */ Status = XSdPs_CheckBusIdle(InstancePtr, XSDPS_PSR_INHIBIT_CMD_MASK - | XSDPS_PSR_INHIBIT_DAT_MASK - | XSDPS_PSR_DAT_ACTIVE_MASK); + | XSDPS_PSR_INHIBIT_DAT_MASK + | XSDPS_PSR_DAT_ACTIVE_MASK); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH ; @@ -469,11 +474,11 @@ RETURN_PATH: /*****************************************************************************/ /** * @brief -* This function performs Erase operation on the given address range. +* Performs Erase operation on the given address range. * -* @param InstancePtr is a pointer to the instance to be worked on. -* @param StartAddr is the address of the first write block to be erased. -* @param EndAddr is the address of the last write block of the continuous +* @param InstancePtr Pointer to the instance to be worked on. +* @param StartAddr Address of the first write block to be erased. +* @param EndAddr Address of the last write block of the continuous * range to be erased. * * @return @@ -501,12 +506,12 @@ s32 XSdPs_Erase(XSdPs *InstancePtr, u32 StartAddr, u32 EndAddr) } if ((InstancePtr->HC_Version != XSDPS_HC_SPEC_V3) || - ((InstancePtr->Host_Caps & XSDPS_CAPS_SLOT_TYPE_MASK) - != XSDPS_CAPS_EMB_SLOT)) { - if(InstancePtr->Config.CardDetect != 0U) { + ((InstancePtr->Host_Caps & XSDPS_CAPS_SLOT_TYPE_MASK) + != XSDPS_CAPS_EMB_SLOT)) { + if (InstancePtr->Config.CardDetect != 0U) { /* Check status to ensure card is present */ PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress, - XSDPS_PRES_STATE_OFFSET); + XSDPS_PRES_STATE_OFFSET); if ((PresentStateReg & XSDPS_PSR_CARD_INSRT_MASK) == 0x0U) { Status = XST_FAILURE; goto RETURN_PATH; @@ -545,4 +550,45 @@ RETURN_PATH: return Status; } +/*****************************************************************************/ +/** +* @brief +* Performs Sanitize operation on the unmapped user address range. +* +* @param InstancePtr Pointer to the instance to be worked on. +* +* @return +* - XST_SUCCESS if Sanitize is successful +* - XST_FAILURE if failure - could be because another transfer +* is in progress or card not present or Sanitize operation failure. +* +******************************************************************************/ +s32 XSdPs_Sanitize(XSdPs *InstancePtr) +{ + s32 Status; + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + +#if defined (XCLOCKING) + Xil_ClockEnable(InstancePtr->Config.RefClk); +#endif + + if (InstancePtr->IsBusy == TRUE) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + + Status = XSdPs_Set_Mmc_ExtCsd(InstancePtr, XSDPS_MMC_START_SANITIZE_ARG); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + +RETURN_PATH: +#if defined (XCLOCKING) + Xil_ClockDisable(InstancePtr->Config.RefClk); +#endif + return Status; +} /** @} */ diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/sdps/src/xsdps.h b/bsp_z7/ps7_cortexa9_0/libsrc/sdps/src/xsdps.h index 77aa9c6..3bdc4f6 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/sdps/src/xsdps.h +++ b/bsp_z7/ps7_cortexa9_0/libsrc/sdps/src/xsdps.h @@ -1,6 +1,6 @@ /****************************************************************************** * Copyright (C) 2013 - 2022 Xilinx, Inc. All rights reserved. -* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved. +* Copyright (c) 2022 - 2024 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -8,75 +8,10 @@ /** * * @file xsdps.h -* @addtogroup sdps Overview +* @addtogroup sdps_api SDPS APIs * @{ * @details * -* This section explains the implementation of the XSdPs driver. -* See xsdps.h for a detailed description of the device and driver. -* -* This driver is used initialize read from and write to the SD card. -* Features such as switching bus width to 4-bit and switching to high speed, -* changing clock frequency, block size etc. are supported. -* SD 2.0 uses 1/4 bus width and speeds of 25/50KHz. Initialization, however -* is done using 1-bit bus width and 400KHz clock frequency. -* SD commands are classified as broadcast and addressed. Commands can be -* those with response only (using only command line) or -* response + data (using command and data lines). -* Only one command can be sent at a time. During a data transfer however, -* when dsta lines are in use, certain commands (which use only the command -* line) can be sent, most often to obtain status. -* This driver does not support multi card slots at present. -* -* Initialization & Configuration -* -* This includes initialization on the host controller side to select -* clock frequency, bus power and default transfer related parameters. -* The default voltage is 3.3V. -* On the SD card side, the initialization and identification state diagram is -* implemented. This resets the card, gives it a unique address/ID and -* identifies key card related specifications. -* -* Data transfer -* -* The SD card is put in transfer state to read from or write to it. -* The default block size is 512 bytes and if supported, -* default bus width is 4-bit and bus speed is High speed. -* The read and write functions are implemented in polled mode using ADMA2. -* -* At any point, when key parameters such as block size or -* clock/speed or bus width are modified, this driver takes care of -* maintaining the same selection on host and card. -* All error bits in host controller are monitored by the driver and in the -* event one of them is set, driver will clear the interrupt status and -* communicate failure to the upper layer. -* -* File system use -* -* This driver can be used with xilffs library to read and write files to SD. -* (Please refer to procedure in diskio.c). The file system read/write example -* in polled mode can used for reference. -* -* There is no example for using SD driver without file system at present. -* However, the driver can be used without the file system. The glue layer -* in filesystem can be used as reference for the same. The block count -* passed to the read/write function in one call is limited by the ADMA2 -* descriptor table and hence care will have to be taken to call read/write -* API's in a loop for large file sizes. -* -* Interrupt mode is not supported because it offers no improvement when used -* with file system. -* -* eMMC support -* -* SD driver supports SD and eMMC based on the "enable MMC" parameter in SDK. -* The features of eMMC supported by the driver will depend on those supported -* by the host controller. The current driver supports read/write on eMMC card -* using 4-bit and high speed mode currently. -* -* Features not supported include - card write protect, password setting, -* lock/unlock, interrupts, SDMA mode, programmed I/O mode and -* 64-bit addressed ADMA2, erase/pre-erase commands. * * 
 * MODIFICATION HISTORY:
@@ -161,6 +96,11 @@
 * 4.1   sa     01/03/23 Report error if Transfer size is greater than 2MB.
 * 4.1	sa     12/19/22 Enable eMMC HS400 mode for Versal Net.
 * 	sa     01/25/23	Use instance structure to store DMA descriptor tables.
+* 4.2   ro     06/12/23 Added support for system device-tree flow.
+* 4.2   ap     08/09/23 Reordered XSdPs_FrameCmd XSdPs_Identify_UhsMode functions
+* 4.3   ap     10/11/23 Resolved compilation errors with Microblaze RISC-V
+* 4.3   ap     11/29/23 Add support for Sanitize feature.
+* 4.3   ap     12/22/23 Add support to read custom HS400 tap delay value from design for eMMC.
 *
 *
* @@ -243,8 +183,12 @@ extern "C" { * This typedef contains configuration information for the device. */ typedef struct { +#ifndef SDT u16 DeviceId; /**< Unique ID of device */ - u32 BaseAddress; /**< Base address of the device */ +#else + char *Name; +#endif + UINTPTR BaseAddress; /**< Base address of the device */ u32 InputClockHz; /**< Input clock frequency */ u32 CardDetect; /**< Card Detect */ u32 WriteProtect; /**< Write Protect */ @@ -253,7 +197,7 @@ typedef struct { u32 HasEMIO; /**< If SD is connected to EMIO */ u8 SlotType; /**< Slot type */ u8 IsCacheCoherent; /**< If SD is Cache Coherent or not */ -#if defined (XCLOCKING) +#if defined (XCLOCKING) || defined (SDT) u32 RefClk; /**< Input clocks */ #endif u32 ITapDly_SDR_Clk50; /**< Input Tap delay for HSD/SDR25 modes */ @@ -262,6 +206,7 @@ typedef struct { u32 OTapDly_DDR_Clk50; /**< Output Tap delay for DDR50 modes */ u32 OTapDly_SDR_Clk100; /**< Input Tap delay for SDR50 modes */ u32 OTapDly_SDR_Clk200; /**< Input Tap delay for SDR104/HS200 modes */ + u32 OTapDly_DDR_Clk200; /**< Input Tap delay for HS400 modes */ } XSdPs_Config; /** @@ -275,7 +220,8 @@ typedef struct { #pragma data_alignment = 32 } XSdPs_Adma2Descriptor32; #else -} __attribute__((__packed__))XSdPs_Adma2Descriptor32; +} +__attribute__((__packed__))XSdPs_Adma2Descriptor32; #endif /** @@ -325,11 +271,11 @@ typedef struct { u8 IsTuningDone; /**< Flag to indicate HS200 tuning complete */ #ifdef __ICCARM__ #pragma data_alignment = 32 - XSdPs_Adma2Descriptor32 Adma2_DescrTbl32[32]; - XSdPs_Adma2Descriptor64 Adma2_DescrTbl64[32]; + XSdPs_Adma2Descriptor32 Adma2_DescrTbl32[32]; /**< ADMA descriptor table 32 Bit */ + XSdPs_Adma2Descriptor64 Adma2_DescrTbl64[32]; /**< ADMA descriptor table 64 Bit */ #else - XSdPs_Adma2Descriptor32 Adma2_DescrTbl32[32] __attribute__ ((aligned(32))); - XSdPs_Adma2Descriptor64 Adma2_DescrTbl64[32] __attribute__ ((aligned(32))); + XSdPs_Adma2Descriptor32 Adma2_DescrTbl32[32] __attribute__ ((aligned(32))); /**< ADMA descriptor table 32 Bit */ + XSdPs_Adma2Descriptor64 Adma2_DescrTbl64[32] __attribute__ ((aligned(32))); /**< ADMA descriptor table 64 Bit */ #endif } XSdPs; @@ -355,10 +301,24 @@ typedef struct { */ #define ENABLE_HS400_MODE +/************************** Variable Definitions *****************************/ +/** + * XSdPs Configuration Table + */ +#ifndef SDT +extern XSdPs_Config XSdPs_ConfigTable[XPAR_XSDPS_NUM_INSTANCES]; +#else +extern XSdPs_Config XSdPs_ConfigTable[]; +#endif + /************************** Function Prototypes ******************************/ +#ifndef SDT XSdPs_Config *XSdPs_LookupConfig(u16 DeviceId); +#else +XSdPs_Config *XSdPs_LookupConfig(u32 BaseAddress); +#endif s32 XSdPs_CfgInitialize(XSdPs *InstancePtr, XSdPs_Config *ConfigPtr, - u32 EffectiveAddr); + UINTPTR EffectiveAddr); s32 XSdPs_CardInitialize(XSdPs *InstancePtr); s32 XSdPs_ReadPolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, u8 *Buff); s32 XSdPs_WritePolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, const u8 *Buff); @@ -380,6 +340,7 @@ s32 XSdPs_CheckReadTransfer(XSdPs *InstancePtr); s32 XSdPs_StartWriteTransfer(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, u8 *Buff); s32 XSdPs_CheckWriteTransfer(XSdPs *InstancePtr); s32 XSdPs_Erase(XSdPs *InstancePtr, u32 StartAddr, u32 EndAddr); +s32 XSdPs_Sanitize(XSdPs *InstancePtr); #ifdef __cplusplus } diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/sdps/src/xsdps_card.c b/bsp_z7/ps7_cortexa9_0/libsrc/sdps/src/xsdps_card.c index 52c5424..49854c1 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/sdps/src/xsdps_card.c +++ b/bsp_z7/ps7_cortexa9_0/libsrc/sdps/src/xsdps_card.c @@ -1,6 +1,6 @@ /****************************************************************************** * Copyright (C) 2013 - 2022 Xilinx, Inc. All rights reserved. -* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved. +* Copyright (c) 2022 - 2024 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -8,7 +8,7 @@ /** * * @file xsdps_card.c -* @addtogroup sdps Overview +* @addtogroup sdps_api SDPS APIs * @{ * * The xsdps_card.c file contains the interface functions of the XSdPs driver. @@ -38,6 +38,8 @@ * sa 01/04/23 Update register bit polling logic to use Xil_WaitForEvent/ * Xil_WaitForEvents API. * sa 01/25/23 Use instance structure to store DMA descriptor tables. +* 4.2 ap 08/09/23 reordered function XSdPs_Identify_UhsMode. +* 4.3 ap 12/22/23 Add support to read custom HS400 tap delay value from design for eMMC. * * ******************************************************************************/ @@ -56,10 +58,10 @@ /*****************************************************************************/ /** * @brief -* This function performs SD read in polled mode. +* Performs SD read in polled mode. * -* @param InstancePtr is a pointer to the instance to be worked on. -* @param Arg is the address passed by the user that is to be sent as +* @param InstancePtr Pointer to the instance to be worked on. +* @param Arg Address passed by the user that is to be sent as * argument along with the command. * @param BlkCnt - Block count passed by the user. * @param Buff - Pointer to the data buffer for a DMA transfer. @@ -78,22 +80,23 @@ s32 XSdPs_Read(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, u8 *Buff) #ifdef XSDPS_DEBUG xil_printf("Max transfer length supported is 2MB\n"); #endif - return XST_FAILURE; - } - - XSdPs_SetupReadDma(InstancePtr, (u16)BlkCnt, (u16)InstancePtr->BlkSize, Buff); - - if (BlkCnt == 1U) { - /* Send single block read command */ - Status = XSdPs_CmdTransfer(InstancePtr, CMD17, Arg, BlkCnt); - if (Status != XST_SUCCESS) { - Status = XST_FAILURE; - } + Status = XST_FAILURE; } else { - /* Send multiple blocks read command */ - Status = XSdPs_CmdTransfer(InstancePtr, CMD18, Arg, BlkCnt); - if (Status != XST_SUCCESS) { - Status = XST_FAILURE; + + XSdPs_SetupReadDma(InstancePtr, (u16)BlkCnt, (u16)InstancePtr->BlkSize, Buff); + + if (BlkCnt == 1U) { + /* Send single block read command */ + Status = XSdPs_CmdTransfer(InstancePtr, CMD17, Arg, BlkCnt); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + } + } else { + /* Send multiple blocks read command */ + Status = XSdPs_CmdTransfer(InstancePtr, CMD18, Arg, BlkCnt); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + } } } @@ -103,10 +106,10 @@ s32 XSdPs_Read(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, u8 *Buff) /*****************************************************************************/ /** * @brief -* This function performs SD write in polled mode. +* Performs SD write in polled mode. * -* @param InstancePtr is a pointer to the instance to be worked on. -* @param Arg is the address passed by the user that is to be sent as +* @param InstancePtr Pointer to the instance to be worked on. +* @param Arg Address passed by the user that is to be sent as * argument along with the command. * @param BlkCnt - Block count passed by the user. * @param Buff - Pointer to the data buffer for a DMA transfer. @@ -125,22 +128,23 @@ s32 XSdPs_Write(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, const u8 *Buff) #ifdef XSDPS_DEBUG xil_printf("Max transfer length supported is 2MB\n"); #endif - return XST_FAILURE; - } - - XSdPs_SetupWriteDma(InstancePtr, (u16)BlkCnt, (u16)InstancePtr->BlkSize, Buff); - - if (BlkCnt == 1U) { - /* Send single block write command */ - Status = XSdPs_CmdTransfer(InstancePtr, CMD24, Arg, BlkCnt); - if (Status != XST_SUCCESS) { - Status = XST_FAILURE; - } + Status = XST_FAILURE; } else { - /* Send multiple blocks write command */ - Status = XSdPs_CmdTransfer(InstancePtr, CMD25, Arg, BlkCnt); - if (Status != XST_SUCCESS) { - Status = XST_FAILURE; + + XSdPs_SetupWriteDma(InstancePtr, (u16)BlkCnt, (u16)InstancePtr->BlkSize, Buff); + + if (BlkCnt == 1U) { + /* Send single block write command */ + Status = XSdPs_CmdTransfer(InstancePtr, CMD24, Arg, BlkCnt); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + } + } else { + /* Send multiple blocks write command */ + Status = XSdPs_CmdTransfer(InstancePtr, CMD25, Arg, BlkCnt); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + } } } @@ -150,9 +154,9 @@ s32 XSdPs_Write(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, const u8 *Buff) /*****************************************************************************/ /** * @brief -* This function is used to check for the transfer complete. +* Checks for the transfer complete. * -* @param InstancePtr is a pointer to the instance to be worked on. +* @param InstancePtr Pointer to the instance to be worked on. * * @return * - XST_SUCCESS if transfer was successful @@ -174,12 +178,12 @@ s32 XSdPs_CheckTransferComplete(XSdPs *InstancePtr) * Check for transfer complete */ StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, - XSDPS_NORM_INTR_STS_OFFSET); + XSDPS_NORM_INTR_STS_OFFSET); if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) { /* Write to clear error bits */ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, - XSDPS_ERR_INTR_STS_OFFSET, - XSDPS_ERROR_INTR_ALL_MASK); + XSDPS_ERR_INTR_STS_OFFSET, + XSDPS_ERROR_INTR_ALL_MASK); Status = XST_FAILURE; goto RETURN_PATH; } @@ -191,7 +195,7 @@ s32 XSdPs_CheckTransferComplete(XSdPs *InstancePtr) /* Write to clear bit */ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, - XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK); + XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK); InstancePtr->IsBusy = FALSE; @@ -205,10 +209,10 @@ RETURN_PATH: /** * * @brief -* Identify type of card using CMD0 + CMD1 sequence +* Identifies type of card using CMD0 + CMD1 sequence * * -* @param InstancePtr is a pointer to the XSdPs instance. +* @param InstancePtr Pointer to the XSdPs instance. * ******************************************************************************/ s32 XSdPs_IdentifyCard(XSdPs *InstancePtr) @@ -216,8 +220,8 @@ s32 XSdPs_IdentifyCard(XSdPs *InstancePtr) s32 Status; if ((InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) && - ((InstancePtr->Host_Caps & XSDPS_CAPS_SLOT_TYPE_MASK) - == XSDPS_CAPS_EMB_SLOT)) { + ((InstancePtr->Host_Caps & XSDPS_CAPS_SLOT_TYPE_MASK) + == XSDPS_CAPS_EMB_SLOT)) { InstancePtr->CardType = XSDPS_CHIP_EMMC; Status = XST_SUCCESS; goto RETURN_PATH; @@ -235,7 +239,7 @@ s32 XSdPs_IdentifyCard(XSdPs *InstancePtr) /* Host High Capacity support & High voltage window */ Status = XSdPs_CmdTransfer(InstancePtr, CMD1, - XSDPS_ACMD41_HCS | XSDPS_CMD1_HIGH_VOL, 0U); + XSDPS_ACMD41_HCS | XSDPS_CMD1_HIGH_VOL, 0U); if (Status != XST_SUCCESS) { InstancePtr->CardType = XSDPS_CARD_SD; } else { @@ -243,9 +247,9 @@ s32 XSdPs_IdentifyCard(XSdPs *InstancePtr) } XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, - XSDPS_NORM_INTR_STS_OFFSET, XSDPS_NORM_INTR_ALL_MASK); + XSDPS_NORM_INTR_STS_OFFSET, XSDPS_NORM_INTR_ALL_MASK); XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, - XSDPS_ERR_INTR_STS_OFFSET, XSDPS_ERROR_INTR_ALL_MASK); + XSDPS_ERR_INTR_STS_OFFSET, XSDPS_ERROR_INTR_ALL_MASK); Status = XSdPs_Reset(InstancePtr, XSDPS_SWRST_CMD_LINE_MASK); if (Status != XST_SUCCESS) { @@ -262,10 +266,10 @@ RETURN_PATH: /*****************************************************************************/ /** * @brief -* SD initialization is done in this function +* This function Initializes SD. * * -* @param InstancePtr is a pointer to the instance to be worked on. +* @param InstancePtr Pointer to the instance to be worked on. * * @return * - XST_SUCCESS if initialization was successful @@ -315,10 +319,10 @@ RETURN_PATH: /*****************************************************************************/ /** * @brief -* Mmc initialization is done in this function +* This function initializes MMC * * -* @param InstancePtr is a pointer to the instance to be worked on. +* @param InstancePtr Pointer to the instance to be worked on. * * @return * - XST_SUCCESS if initialization was successful @@ -347,8 +351,8 @@ s32 XSdPs_MmcCardInitialize(XSdPs *InstancePtr) } if (((InstancePtr->CardType == XSDPS_CARD_MMC) && - (InstancePtr->Card_Version > CSD_SPEC_VER_3)) && - (InstancePtr->HC_Version == XSDPS_HC_SPEC_V2)) { + (InstancePtr->Card_Version > CSD_SPEC_VER_3)) && + (InstancePtr->HC_Version == XSDPS_HC_SPEC_V2)) { Status = XSdPs_MmcModeInit(InstancePtr); if (Status != XST_SUCCESS) { Status = XST_FAILURE; @@ -366,7 +370,7 @@ s32 XSdPs_MmcCardInitialize(XSdPs *InstancePtr) } - if (InstancePtr->Mode != XSDPS_DDR52_MODE && InstancePtr->Mode != XSDPS_HS400_MODE) { + if ((InstancePtr->Mode != XSDPS_DDR52_MODE) && (InstancePtr->Mode != XSDPS_HS400_MODE)) { Status = XSdPs_SetBlkSize(InstancePtr, XSDPS_BLK_SIZE_512_MASK); if (Status != XST_SUCCESS) { Status = XST_FAILURE; @@ -374,7 +378,7 @@ s32 XSdPs_MmcCardInitialize(XSdPs *InstancePtr) } } else { XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, - XSDPS_BLK_SIZE_OFFSET, XSDPS_BLK_SIZE_512_MASK); + XSDPS_BLK_SIZE_OFFSET, XSDPS_BLK_SIZE_512_MASK); InstancePtr->BlkSize = XSDPS_BLK_SIZE_512_MASK; } @@ -387,9 +391,9 @@ RETURN_PATH: /*****************************************************************************/ /** * @brief -* This function checks if the card is present or not. +* Checks if the card is present or not. * -* @param InstancePtr is a pointer to the instance to be worked on. +* @param InstancePtr Pointer to the instance to be worked on. * * @return None * @@ -400,19 +404,19 @@ s32 XSdPs_CheckCardDetect(XSdPs *InstancePtr) s32 Status; if ((InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) && - ((InstancePtr->Host_Caps & XSDPS_CAPS_SLOT_TYPE_MASK) - == XSDPS_CAPS_EMB_SLOT)) { + ((InstancePtr->Host_Caps & XSDPS_CAPS_SLOT_TYPE_MASK) + == XSDPS_CAPS_EMB_SLOT)) { Status = XST_SUCCESS; goto RETURN_PATH; } - if(InstancePtr->Config.CardDetect != 0U) { + if (InstancePtr->Config.CardDetect != 0U) { /* * Check the present state register to make sure * card is inserted and detected by host controller */ PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress, - XSDPS_PRES_STATE_OFFSET); + XSDPS_PRES_STATE_OFFSET); if ((PresentStateReg & XSDPS_PSR_CARD_INSRT_MASK) == 0U) { Status = XST_FAILURE; goto RETURN_PATH; @@ -428,9 +432,9 @@ RETURN_PATH: /*****************************************************************************/ /** * @brief -* This function sends CMD0 to reset the card. +* Sends CMD0 to reset the card. * -* @param InstancePtr is a pointer to the instance to be worked on. +* @param InstancePtr Pointer to the instance to be worked on. * * @return None * @@ -451,9 +455,9 @@ s32 XSdPs_CardReset(XSdPs *InstancePtr) /*****************************************************************************/ /** * @brief -* This function sends command to get the card interface details. +* Sends command to get the card interface details. * -* @param InstancePtr is a pointer to the instance to be worked on. +* @param InstancePtr Pointer to the instance to be worked on. * * @return None * @@ -468,7 +472,7 @@ s32 XSdPs_CardIfCond(XSdPs *InstancePtr) * 0x1AA - Supply Voltage 2.7 - 3.6V and AA is pattern */ Status = XSdPs_CmdTransfer(InstancePtr, CMD8, - XSDPS_CMD8_VOL_PATTERN, 0U); + XSDPS_CMD8_VOL_PATTERN, 0U); if ((Status != XST_SUCCESS) && (Status != XSDPS_CT_ERROR)) { Status = XST_FAILURE; goto RETURN_PATH; @@ -483,7 +487,7 @@ s32 XSdPs_CardIfCond(XSdPs *InstancePtr) } RespOCR = XSdPs_ReadReg(InstancePtr->Config.BaseAddress, - XSDPS_RESP0_OFFSET); + XSDPS_RESP0_OFFSET); if (RespOCR != XSDPS_CMD8_VOL_PATTERN) { InstancePtr->Card_Version = XSDPS_SD_VER_1_0; } else { @@ -499,9 +503,9 @@ RETURN_PATH: /*****************************************************************************/ /** * @brief -* This function sends command to get the card operating condition. +* Sends command to get the card operating condition. * -* @param InstancePtr is a pointer to the instance to be worked on. +* @param InstancePtr Pointer to the instance to be worked on. * * @return None * @@ -524,17 +528,17 @@ s32 XSdPs_CardOpCond(XSdPs *InstancePtr) Arg = XSDPS_ACMD41_HCS | XSDPS_ACMD41_3V3 | (0x1FFU << 15U); if ((InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) && - (InstancePtr->Config.BusWidth == XSDPS_WIDTH_8)) { + (InstancePtr->Config.BusWidth == XSDPS_WIDTH_8)) { Arg |= XSDPS_OCR_S18; } /* 0x40300000 - Host High Capacity support & 3.3V window */ Status = XSdPs_CmdTransfer(InstancePtr, ACMD41, - Arg, 0U); + Arg, 0U); } else { /* Send CMD1 while card is still busy with power up */ Status = XSdPs_CmdTransfer(InstancePtr, CMD1, - XSDPS_ACMD41_HCS | XSDPS_CMD1_HIGH_VOL, 0U); + XSDPS_ACMD41_HCS | XSDPS_CMD1_HIGH_VOL, 0U); } if (Status != XST_SUCCESS) { Status = XST_FAILURE; @@ -542,7 +546,8 @@ s32 XSdPs_CardOpCond(XSdPs *InstancePtr) } /* Response with card capacity */ - Status = Xil_WaitForEvent(InstancePtr->Config.BaseAddress + XSDPS_RESP0_OFFSET, XSDPS_RESPOCR_READY, XSDPS_RESPOCR_READY, 1U); + Status = Xil_WaitForEvent(InstancePtr->Config.BaseAddress + XSDPS_RESP0_OFFSET, XSDPS_RESPOCR_READY, + XSDPS_RESPOCR_READY, 1U); if (Status == XST_SUCCESS) { RespOCR = XSdPs_ReadReg(InstancePtr->Config.BaseAddress, XSDPS_RESP0_OFFSET); break; @@ -578,9 +583,9 @@ RETURN_PATH: /*****************************************************************************/ /** * @brief -* This function is used to get the card ID. +* Gets the card ID. * -* @param InstancePtr is a pointer to the instance to be worked on. +* @param InstancePtr Pointer to the instance to be worked on. * * @return None * @@ -598,19 +603,19 @@ s32 XSdPs_GetCardId(XSdPs *InstancePtr) } InstancePtr->CardID[0] = - XSdPs_ReadReg(InstancePtr->Config.BaseAddress, - XSDPS_RESP0_OFFSET); + XSdPs_ReadReg(InstancePtr->Config.BaseAddress, + XSDPS_RESP0_OFFSET); InstancePtr->CardID[1] = - XSdPs_ReadReg(InstancePtr->Config.BaseAddress, - XSDPS_RESP1_OFFSET); + XSdPs_ReadReg(InstancePtr->Config.BaseAddress, + XSDPS_RESP1_OFFSET); InstancePtr->CardID[2] = - XSdPs_ReadReg(InstancePtr->Config.BaseAddress, - XSDPS_RESP2_OFFSET); + XSdPs_ReadReg(InstancePtr->Config.BaseAddress, + XSDPS_RESP2_OFFSET); InstancePtr->CardID[3] = - XSdPs_ReadReg(InstancePtr->Config.BaseAddress, - XSDPS_RESP3_OFFSET); + XSdPs_ReadReg(InstancePtr->Config.BaseAddress, + XSDPS_RESP3_OFFSET); - if(InstancePtr->CardType == XSDPS_CARD_SD) { + if (InstancePtr->CardType == XSDPS_CARD_SD) { do { Status = XSdPs_CmdTransfer(InstancePtr, CMD3, 0U, 0U); if (Status != XST_SUCCESS) { @@ -625,7 +630,7 @@ s32 XSdPs_GetCardId(XSdPs *InstancePtr) Status = Xil_WaitForEvent(InstancePtr->Config.BaseAddress + XSDPS_RESP0_OFFSET, 0xFFFF0000, 0U, 1U); if (Status != XST_SUCCESS) { InstancePtr->RelCardAddr = XSdPs_ReadReg(InstancePtr->Config.BaseAddress, - XSDPS_RESP0_OFFSET) & 0xFFFF0000U; + XSDPS_RESP0_OFFSET) & 0xFFFF0000U; break; } Count = Count - 1U; @@ -653,9 +658,9 @@ RETURN_PATH: /*****************************************************************************/ /** * @brief -* This function is used to get the CSD register from the card. +* Gets the CSD register from the card. * -* @param InstancePtr is a pointer to the instance to be worked on. +* @param InstancePtr Pointer to the instance to be worked on. * * @return None * @@ -679,13 +684,13 @@ s32 XSdPs_GetCsd(XSdPs *InstancePtr) * Currently not used for any operation. */ CSD[0] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress, - XSDPS_RESP0_OFFSET); + XSDPS_RESP0_OFFSET); CSD[1] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress, - XSDPS_RESP1_OFFSET); + XSDPS_RESP1_OFFSET); CSD[2] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress, - XSDPS_RESP2_OFFSET); + XSDPS_RESP2_OFFSET); CSD[3] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress, - XSDPS_RESP3_OFFSET); + XSDPS_RESP3_OFFSET); InstancePtr->CardSpecData[0] = CSD[0]; InstancePtr->CardSpecData[1] = CSD[1]; @@ -693,7 +698,7 @@ s32 XSdPs_GetCsd(XSdPs *InstancePtr) InstancePtr->CardSpecData[3] = CSD[3]; if (InstancePtr->CardType != XSDPS_CARD_SD) { - InstancePtr->Card_Version = (u8)((u32)(CSD[3] & CSD_SPEC_VER_MASK) >>18U); + InstancePtr->Card_Version = (u8)((u32)(CSD[3] & CSD_SPEC_VER_MASK) >> 18U); Status = XST_SUCCESS; goto RETURN_PATH; } @@ -705,10 +710,10 @@ s32 XSdPs_GetCsd(XSdPs *InstancePtr) DeviceSize |= (CSD[2] & C_SIZE_UPPER_MASK) << 10U; DeviceSize = (DeviceSize + 1U) * Mult; DeviceSize = DeviceSize * BlkLen; - InstancePtr->SectorCount = (DeviceSize/XSDPS_BLK_SIZE_512_MASK); + InstancePtr->SectorCount = (DeviceSize / XSDPS_BLK_SIZE_512_MASK); } else if (((CSD[3] & CSD_STRUCT_MASK) >> 22U) == 1U) { InstancePtr->SectorCount = (((CSD[1] & CSD_V2_C_SIZE_MASK) >> 8U) + - 1U) * 1024U; + 1U) * 1024U; } else { Status = XST_FAILURE; goto RETURN_PATH; @@ -723,9 +728,9 @@ RETURN_PATH: /*****************************************************************************/ /** * @brief -* This function is used to set the card voltage to 1.8V. +* Sets the card voltage to 1.8 V. * -* @param InstancePtr is a pointer to the instance to be worked on. +* @param InstancePtr Pointer to the instance to be worked on. * * @return None * @@ -738,10 +743,10 @@ s32 XSdPs_CardSetVoltage18(XSdPs *InstancePtr) /* Stop the clock */ CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, - XSDPS_CLK_CTRL_OFFSET); + XSDPS_CLK_CTRL_OFFSET); CtrlReg &= (u16)(~(XSDPS_CC_SD_CLK_EN_MASK | XSDPS_CC_INT_CLK_EN_MASK)); XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_CLK_CTRL_OFFSET, - CtrlReg); + CtrlReg); /* Check for 1.8V signal enable bit is cleared by Host */ Status = XSdPs_SetVoltage18(InstancePtr); @@ -751,7 +756,7 @@ s32 XSdPs_CardSetVoltage18(XSdPs *InstancePtr) } ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, - XSDPS_CLK_CTRL_OFFSET); + XSDPS_CLK_CTRL_OFFSET); /* Enable the clock in the controller */ Status = XSdPs_EnableClock(InstancePtr, ClockReg); if (Status != XST_SUCCESS) { @@ -771,9 +776,9 @@ RETURN_PATH: /*****************************************************************************/ /** * @brief -* This function is used to do initial Reset Configuration. +* Configures the initial Reset. * -* @param InstancePtr is a pointer to the instance to be worked on. +* @param InstancePtr Pointer to the instance to be worked on. * * @return None * @@ -786,11 +791,15 @@ s32 XSdPs_ResetConfig(XSdPs *InstancePtr) #ifdef versal if ((InstancePtr->Host_Caps & XSDPS_CAPS_SLOT_TYPE_MASK) - != XSDPS_CAPS_EMB_SLOT) { + != XSDPS_CAPS_EMB_SLOT) { u32 Timeout = 200000U; /* Check for SD Bus Lines low */ - Status = Xil_WaitForEvent(InstancePtr->Config.BaseAddress + XSDPS_PRES_STATE_OFFSET, XSDPS_PSR_DAT30_SG_LVL_MASK, 0U, Timeout); + Status = Xil_WaitForEvent(InstancePtr->Config.BaseAddress + XSDPS_PRES_STATE_OFFSET, XSDPS_PSR_DAT30_SG_LVL_MASK, 0U, + Timeout); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + } } #endif @@ -809,9 +818,9 @@ RETURN_PATH: /*****************************************************************************/ /** * @brief -* This function is used to do initial Host Configuration. +* Configures the initial Host. * -* @param InstancePtr is a pointer to the instance to be worked on. +* @param InstancePtr Pointer to the instance to be worked on. * * @return None * @@ -829,20 +838,20 @@ void XSdPs_HostConfig(XSdPs *InstancePtr) * DMA enabled, block count enabled, data direction card to host(read) */ InstancePtr->TransferMode = XSDPS_TM_DMA_EN_MASK | XSDPS_TM_BLK_CNT_EN_MASK | - XSDPS_TM_DAT_DIR_SEL_MASK; + XSDPS_TM_DAT_DIR_SEL_MASK; /* Set block size to 512 by default */ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, - XSDPS_BLK_SIZE_OFFSET, XSDPS_BLK_SIZE_512_MASK); + XSDPS_BLK_SIZE_OFFSET, XSDPS_BLK_SIZE_512_MASK); } /*****************************************************************************/ /** * @brief -* This function checks for Reset Done bits to be cleared after a reset assert. +* Checks for Reset Done bits to be cleared after a reset assert. * -* @param InstancePtr is a pointer to the instance to be worked on. -* @param Value is the bits to be checked to be cleared. +* @param InstancePtr Pointer to the instance to be worked on. +* @param Value Bits to be checked to be cleared. * * @return None * @@ -855,7 +864,7 @@ s32 XSdPs_CheckResetDone(XSdPs *InstancePtr, u8 Value) /* Proceed with initialization only after reset is complete */ /* Using XSDPS_CLK_CTRL_OFFSET(0x2C) in place of XSDPS_SW_RST_OFFSET(0x2F) for 32bit address aligned reading */ Status = Xil_WaitForEvent(InstancePtr->Config.BaseAddress + XSDPS_CLK_CTRL_OFFSET, - Value << 24, 0U, Timeout); + ((u32)Value) << 24, 0U, Timeout); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH ; @@ -870,9 +879,9 @@ RETURN_PATH: /*****************************************************************************/ /** * @brief -* This function is used to setup the voltage switch. +* Sets up the voltage switch. * -* @param InstancePtr is a pointer to the instance to be worked on. +* @param InstancePtr Pointer to the instance to be worked on. * * @return None * @@ -891,7 +900,7 @@ s32 XSdPs_SetupVoltageSwitch(XSdPs *InstancePtr) /* Wait for CMD and DATA line to go low */ Status = Xil_WaitForEvent(InstancePtr->Config.BaseAddress + XSDPS_PRES_STATE_OFFSET, - XSDPS_PSR_CMD_SG_LVL_MASK | XSDPS_PSR_DAT30_SG_LVL_MASK, 0U, Timeout); + XSDPS_PSR_CMD_SG_LVL_MASK | XSDPS_PSR_DAT30_SG_LVL_MASK, 0U, Timeout); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH ; @@ -904,9 +913,9 @@ RETURN_PATH: /*****************************************************************************/ /** * @brief -* This function is used to check if the Cmd and Dat buses are high. +* Check if the CMD and DAT buses are high. * -* @param InstancePtr is a pointer to the instance to be worked on. +* @param InstancePtr Pointer to the instance to be worked on. * * @return None * @@ -918,8 +927,8 @@ s32 XSdPs_CheckBusHigh(XSdPs *InstancePtr) /* Wait for CMD and DATA line to go high */ Status = Xil_WaitForEvent(InstancePtr->Config.BaseAddress + XSDPS_PRES_STATE_OFFSET, - XSDPS_PSR_CMD_SG_LVL_MASK | XSDPS_PSR_DAT30_SG_LVL_MASK, - XSDPS_PSR_CMD_SG_LVL_MASK | XSDPS_PSR_DAT30_SG_LVL_MASK, Timeout); + XSDPS_PSR_CMD_SG_LVL_MASK | XSDPS_PSR_DAT30_SG_LVL_MASK, + XSDPS_PSR_CMD_SG_LVL_MASK | XSDPS_PSR_DAT30_SG_LVL_MASK, Timeout); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH ; @@ -940,70 +949,31 @@ RETURN_PATH: * supported bus speed. * * -* @param InstancePtr is a pointer to the XSdPs instance. -* @param ReadBuff contains the response for CMD6 +* @param InstancePtr Pointer to the XSdPs instance. +* @param ReadBuff Contains the response for CMD6 * * @return None. * -* @note None. * ******************************************************************************/ void XSdPs_Identify_UhsMode(XSdPs *InstancePtr, u8 *ReadBuff) { if (((ReadBuff[13] & UHS_SDR104_SUPPORT) != 0U) && - (InstancePtr->Config.InputClockHz >= XSDPS_SD_INPUT_MAX_CLK)) { + (InstancePtr->Config.InputClockHz >= XSDPS_SD_INPUT_MAX_CLK)) { InstancePtr->Mode = XSDPS_UHS_SPEED_MODE_SDR104; - if (InstancePtr->Config.OTapDly_SDR_Clk200) { - InstancePtr->OTapDelay = InstancePtr->Config.OTapDly_SDR_Clk200; - } else if (InstancePtr->Config.BankNumber == 2U) { - InstancePtr->OTapDelay = SD_OTAPDLYSEL_HS200_B2; - } else { - InstancePtr->OTapDelay = SD_OTAPDLYSEL_HS200_B0; - } + XSdPs_SetTapDelay_SDR104(InstancePtr); } else if (((ReadBuff[13] & UHS_SDR50_SUPPORT) != 0U) && - (InstancePtr->Config.InputClockHz >= XSDPS_SD_SDR50_MAX_CLK)) { + (InstancePtr->Config.InputClockHz >= XSDPS_SD_SDR50_MAX_CLK)) { InstancePtr->Mode = XSDPS_UHS_SPEED_MODE_SDR50; - if (InstancePtr->Config.OTapDly_SDR_Clk100) { - InstancePtr->OTapDelay = InstancePtr->Config.OTapDly_SDR_Clk100; - } else { - InstancePtr->OTapDelay = SD_OTAPDLYSEL_SD50; - } + XSdPs_SetTapDelay_SDR50(InstancePtr); } else if (((ReadBuff[13] & UHS_DDR50_SUPPORT) != 0U) && - (InstancePtr->Config.InputClockHz >= XSDPS_SD_DDR50_MAX_CLK)) { + (InstancePtr->Config.InputClockHz >= XSDPS_SD_DDR50_MAX_CLK)) { InstancePtr->Mode = XSDPS_UHS_SPEED_MODE_DDR50; - if (InstancePtr->Config.OTapDly_DDR_Clk50 && - InstancePtr->Config.ITapDly_DDR_Clk50) { - InstancePtr->OTapDelay = InstancePtr->Config.OTapDly_DDR_Clk50; - InstancePtr->ITapDelay = InstancePtr->Config.ITapDly_DDR_Clk50; - if ((InstancePtr->Config.SlotType == XSDPS_SLOTTYPE_SDADIR) && - (InstancePtr->ITapDelay == SD_ITAPDLYSEL_SD_DDR50)) { - InstancePtr->ITapDelay = SD_AUTODIR_ITAPDLYSEL_DDR50; - } - } else if (InstancePtr->Config.SlotType == XSDPS_SLOTTYPE_SDADIR) { - InstancePtr->ITapDelay = SD_AUTODIR_ITAPDLYSEL_DDR50; - InstancePtr->OTapDelay = SD_OTAPDLYSEL_SD_DDR50; - } else { - InstancePtr->ITapDelay = SD_ITAPDLYSEL_SD_DDR50; - InstancePtr->OTapDelay = SD_OTAPDLYSEL_SD_DDR50; - } + XSdPs_SetTapDelay_DDR50(InstancePtr); } else if (((ReadBuff[13] & UHS_SDR25_SUPPORT) != 0U) && - (InstancePtr->Config.InputClockHz >= XSDPS_SD_SDR25_MAX_CLK)) { + (InstancePtr->Config.InputClockHz >= XSDPS_SD_SDR25_MAX_CLK)) { InstancePtr->Mode = XSDPS_UHS_SPEED_MODE_SDR25; - if (InstancePtr->Config.OTapDly_SDR_Clk50 && - InstancePtr->Config.ITapDly_SDR_Clk50) { - InstancePtr->OTapDelay = InstancePtr->Config.OTapDly_SDR_Clk50; - InstancePtr->ITapDelay = InstancePtr->Config.ITapDly_SDR_Clk50; - if ((InstancePtr->Config.SlotType == XSDPS_SLOTTYPE_SDADIR) && - (InstancePtr->ITapDelay == SD_ITAPDLYSEL_HSD)) { - InstancePtr->ITapDelay = SD_AUTODIR_ITAPDLYSEL_SDR25; - } - } else if (InstancePtr->Config.SlotType == XSDPS_SLOTTYPE_SDADIR) { - InstancePtr->ITapDelay = SD_AUTODIR_ITAPDLYSEL_SDR25; - InstancePtr->OTapDelay = SD_OTAPDLYSEL_SD_HSD; - } else { - InstancePtr->ITapDelay = SD_ITAPDLYSEL_HSD; - InstancePtr->OTapDelay = SD_OTAPDLYSEL_SD_HSD; - } + XSdPs_SetTapDelay_SDR25(InstancePtr); } else { InstancePtr->Mode = XSDPS_UHS_SPEED_MODE_SDR12; } @@ -1013,20 +983,18 @@ void XSdPs_Identify_UhsMode(XSdPs *InstancePtr, u8 *ReadBuff) /** * * @brief -* API to set Tap Delay w.r.t speed modes +* API to set Tap Delay with respect to the speed modes. * * -* @param InstancePtr is a pointer to the XSdPs instance. +* @param InstancePtr Pointer to the XSdPs instance. * * @return None * -* @note None. -* ******************************************************************************/ void XSdPs_SetTapDelay(XSdPs *InstancePtr) { if ((InstancePtr->Mode == XSDPS_DEFAULT_SPEED_MODE) || - (InstancePtr->Mode == XSDPS_UHS_SPEED_MODE_SDR12)) { + (InstancePtr->Mode == XSDPS_UHS_SPEED_MODE_SDR12)) { return; } @@ -1047,9 +1015,9 @@ void XSdPs_SetTapDelay(XSdPs *InstancePtr) /*****************************************************************************/ /** * @brief -* This function is used to change the SD Bus Speed. +* Changes the SD Bus Speed. * -* @param InstancePtr is a pointer to the instance to be worked on. +* @param InstancePtr Pointer to the instance to be worked on. * * @return None * @@ -1090,11 +1058,11 @@ s32 XSdPs_Change_SdBusSpeed(XSdPs *InstancePtr) if (InstancePtr->Switch1v8 != 0U) { /* Set UHS mode in controller */ CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, - XSDPS_HOST_CTRL2_OFFSET); + XSDPS_HOST_CTRL2_OFFSET); CtrlReg &= (~(u16)XSDPS_HC2_UHS_MODE_MASK); XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, - XSDPS_HOST_CTRL2_OFFSET, - CtrlReg | (u16)InstancePtr->Mode); + XSDPS_HOST_CTRL2_OFFSET, + CtrlReg | (u16)InstancePtr->Mode); } Status = XST_SUCCESS; @@ -1106,9 +1074,9 @@ RETURN_PATH: /*****************************************************************************/ /** * @brief -* This function is used to change the eMMC bus speed. +* Changes the eMMC bus speed. * -* @param InstancePtr is a pointer to the instance to be worked on. +* @param InstancePtr Pointer to the instance to be worked on. * * @return None * @@ -1148,7 +1116,7 @@ RETURN_PATH: * @brief * This function is used to do the Auto tuning. * -* @param InstancePtr is a pointer to the instance to be worked on. +* @param InstancePtr Pointer to the instance to be worked on. * * @return None * @@ -1160,13 +1128,12 @@ s32 XSdPs_AutoTuning(XSdPs *InstancePtr) u8 TuningCount; BlkSize = XSDPS_TUNING_CMD_BLKSIZE; - if(InstancePtr->BusWidth == XSDPS_8_BIT_WIDTH) - { - BlkSize = BlkSize*2U; + if (InstancePtr->BusWidth == XSDPS_8_BIT_WIDTH) { + BlkSize = BlkSize * 2U; } BlkSize &= XSDPS_BLK_SIZE_MASK; XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_BLK_SIZE_OFFSET, - BlkSize); + BlkSize); InstancePtr->TransferMode = XSDPS_TM_DAT_DIR_SEL_MASK; @@ -1192,13 +1159,13 @@ s32 XSdPs_AutoTuning(XSdPs *InstancePtr) } if ((XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, - XSDPS_HOST_CTRL2_OFFSET) & XSDPS_HC2_EXEC_TNG_MASK) == 0U) { + XSDPS_HOST_CTRL2_OFFSET) & XSDPS_HC2_EXEC_TNG_MASK) == 0U) { break; } } if ((XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, - XSDPS_HOST_CTRL2_OFFSET) & XSDPS_HC2_SAMP_CLK_SEL_MASK) == 0U) { + XSDPS_HOST_CTRL2_OFFSET) & XSDPS_HC2_SAMP_CLK_SEL_MASK) == 0U) { Status = XST_FAILURE; goto RETURN_PATH; } @@ -1216,17 +1183,15 @@ RETURN_PATH: /** * * @brief -* API to setup ADMA2 descriptor table +* API to setup ADMA2 descriptor table. * * -* @param InstancePtr is a pointer to the XSdPs instance. -* @param BlkCnt - block count. -* @param Buff pointer to data buffer. +* @param InstancePtr Pointer to the XSdPs instance. +* @param BlkCnt Block count. +* @param Buff Pointer to data buffer. * * @return None * -* @note None. -* ******************************************************************************/ void XSdPs_SetupADMA2DescTbl(XSdPs *InstancePtr, u32 BlkCnt, const u8 *Buff) { @@ -1241,15 +1206,14 @@ void XSdPs_SetupADMA2DescTbl(XSdPs *InstancePtr, u32 BlkCnt, const u8 *Buff) /** * * @brief -* API to setup ADMA2 descriptor table for 64 Bit DMA +* API to setup ADMA2 descriptor table for 64 Bit DMA. * * -* @param InstancePtr is a pointer to the XSdPs instance. -* @param BlkCnt - block count. +* @param InstancePtr Pointer to the XSdPs instance. +* @param BlkCnt Block count. * * @return None * -* @note None. * ******************************************************************************/ void XSdPs_SetupADMA2DescTbl64Bit(XSdPs *InstancePtr, u32 BlkCnt) @@ -1260,16 +1224,16 @@ void XSdPs_SetupADMA2DescTbl64Bit(XSdPs *InstancePtr, u32 BlkCnt) /* Setup ADMA2 - Write descriptor table and point ADMA SAR to it */ BlkSize = (u32)XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, - XSDPS_BLK_SIZE_OFFSET) & - XSDPS_BLK_SIZE_MASK; + XSDPS_BLK_SIZE_OFFSET) & + XSDPS_BLK_SIZE_MASK; - if((BlkCnt*BlkSize) < XSDPS_DESC_MAX_LENGTH) { + if ((BlkCnt * BlkSize) < XSDPS_DESC_MAX_LENGTH) { TotalDescLines = 1U; } else { - TotalDescLines = ((BlkCnt*BlkSize) / XSDPS_DESC_MAX_LENGTH); + TotalDescLines = ((BlkCnt * BlkSize) / XSDPS_DESC_MAX_LENGTH); if (((BlkCnt * BlkSize) % XSDPS_DESC_MAX_LENGTH) != 0U) { TotalDescLines += 1U; } @@ -1278,29 +1242,29 @@ void XSdPs_SetupADMA2DescTbl64Bit(XSdPs *InstancePtr, u32 BlkCnt) for (DescNum = 0U; DescNum < (TotalDescLines - 1U); DescNum++) { InstancePtr->Adma2_DescrTbl64[DescNum].Address = - InstancePtr->Dma64BitAddr + - ((u64)DescNum*XSDPS_DESC_MAX_LENGTH); + InstancePtr->Dma64BitAddr + + ((u64)DescNum * XSDPS_DESC_MAX_LENGTH); InstancePtr->Adma2_DescrTbl64[DescNum].Attribute = - XSDPS_DESC_TRAN | XSDPS_DESC_VALID; + XSDPS_DESC_TRAN | XSDPS_DESC_VALID; InstancePtr->Adma2_DescrTbl64[DescNum].Length = 0U; } InstancePtr->Adma2_DescrTbl64[TotalDescLines - 1U].Address = - InstancePtr->Dma64BitAddr + - ((u64)DescNum*XSDPS_DESC_MAX_LENGTH); + InstancePtr->Dma64BitAddr + + ((u64)DescNum * XSDPS_DESC_MAX_LENGTH); InstancePtr->Adma2_DescrTbl64[TotalDescLines - 1U].Attribute = - XSDPS_DESC_TRAN | XSDPS_DESC_END | XSDPS_DESC_VALID; + XSDPS_DESC_TRAN | XSDPS_DESC_END | XSDPS_DESC_VALID; InstancePtr->Adma2_DescrTbl64[TotalDescLines - 1U].Length = - (u16)((BlkCnt*BlkSize) - (u32)(DescNum*XSDPS_DESC_MAX_LENGTH)); + (u16)((BlkCnt * BlkSize) - (u32)(DescNum * XSDPS_DESC_MAX_LENGTH)); XSdPs_WriteReg(InstancePtr->Config.BaseAddress, XSDPS_ADMA_SAR_OFFSET, - (u32)((UINTPTR)&(InstancePtr->Adma2_DescrTbl64[0]) & ~(u32)0x0U)); + (u32)((UINTPTR) & (InstancePtr->Adma2_DescrTbl64[0]) & ~(u32)0x0U)); if (InstancePtr->Config.IsCacheCoherent == 0U) { - Xil_DCacheFlushRange((INTPTR)&(InstancePtr->Adma2_DescrTbl64[0]), - (INTPTR)sizeof(XSdPs_Adma2Descriptor64) * (INTPTR)32U); + Xil_DCacheFlushRange((INTPTR) & (InstancePtr->Adma2_DescrTbl64[0]), + (INTPTR)sizeof(XSdPs_Adma2Descriptor64) * (INTPTR)32U); } /* Clear the 64-Bit Address variable */ @@ -1312,14 +1276,13 @@ void XSdPs_SetupADMA2DescTbl64Bit(XSdPs *InstancePtr, u32 BlkCnt) /** * * @brief -* API to reset the DLL +* API to reset the DLL. * * -* @param InstancePtr is a pointer to the XSdPs instance. +* @param InstancePtr Pointer to the XSdPs instance. * * @return None * -* @note None. * ******************************************************************************/ s32 XSdPs_DllReset(XSdPs *InstancePtr) @@ -1329,10 +1292,10 @@ s32 XSdPs_DllReset(XSdPs *InstancePtr) /* Disable clock */ ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, - XSDPS_CLK_CTRL_OFFSET); + XSDPS_CLK_CTRL_OFFSET); ClockReg &= ~XSDPS_CC_SD_CLK_EN_MASK; XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, - XSDPS_CLK_CTRL_OFFSET, (u16)ClockReg); + XSDPS_CLK_CTRL_OFFSET, (u16)ClockReg); /* Issue DLL Reset to load zero tap values */ XSdPs_DllRstCtrl(InstancePtr, 1U); @@ -1343,7 +1306,7 @@ s32 XSdPs_DllReset(XSdPs *InstancePtr) XSdPs_DllRstCtrl(InstancePtr, 0U); ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, - XSDPS_CLK_CTRL_OFFSET); + XSDPS_CLK_CTRL_OFFSET); /* Enable the clock in the controller */ Status = XSdPs_EnableClock(InstancePtr, (u16)ClockReg); if (Status != XST_SUCCESS) { @@ -1356,10 +1319,10 @@ s32 XSdPs_DllReset(XSdPs *InstancePtr) /*****************************************************************************/ /** * @brief -* This function is used to identify the eMMC speed mode. +* Identifies the eMMC speed mode. * -* @param InstancePtr is a pointer to the instance to be worked on. -* @param ExtCsd is the extended CSD register from the card +* @param InstancePtr Pointer to the instance to be worked on. +* @param ExtCsd Extended CSD register from the card. * * @return None * @@ -1372,18 +1335,18 @@ void XSdPs_IdentifyEmmcMode(XSdPs *InstancePtr, const u8 *ExtCsd) /* Check for card supported speed */ #if defined (VERSAL_NET) && defined (ENABLE_HS400_MODE) if ((ExtCsd[EXT_CSD_DEVICE_TYPE_BYTE] & - (EXT_CSD_DEVICE_TYPE_DDR_1V8_HS400 | - EXT_CSD_DEVICE_TYPE_DDR_1V2_HS400)) != 0U) { + (EXT_CSD_DEVICE_TYPE_DDR_1V8_HS400 | + EXT_CSD_DEVICE_TYPE_DDR_1V2_HS400)) != 0U) { InstancePtr->Mode = XSDPS_HS400_MODE; InstancePtr->IsTuningDone = 0U; InstancePtr->OTapDelay = SD_OTAPDLYSEL_HS200_B0; } else { #endif if ((ExtCsd[EXT_CSD_DEVICE_TYPE_BYTE] & - (EXT_CSD_DEVICE_TYPE_SDR_1V8_HS200 | - EXT_CSD_DEVICE_TYPE_SDR_1V2_HS200)) != 0U) { + (EXT_CSD_DEVICE_TYPE_SDR_1V8_HS200 | + EXT_CSD_DEVICE_TYPE_SDR_1V2_HS200)) != 0U) { InstancePtr->Mode = XSDPS_HS200_MODE; - if (InstancePtr->Config.OTapDly_SDR_Clk200) { + if (InstancePtr->Config.OTapDly_SDR_Clk200 != 0U) { InstancePtr->OTapDelay = InstancePtr->Config.OTapDly_SDR_Clk200; } else if (InstancePtr->Config.BankNumber == 2U) { InstancePtr->OTapDelay = SD_OTAPDLYSEL_HS200_B2; @@ -1391,11 +1354,11 @@ void XSdPs_IdentifyEmmcMode(XSdPs *InstancePtr, const u8 *ExtCsd) InstancePtr->OTapDelay = SD_OTAPDLYSEL_HS200_B0; } } else if ((ExtCsd[EXT_CSD_DEVICE_TYPE_BYTE] & - (EXT_CSD_DEVICE_TYPE_DDR_1V8_HIGH_SPEED | - EXT_CSD_DEVICE_TYPE_DDR_1V2_HIGH_SPEED)) != 0U) { + (EXT_CSD_DEVICE_TYPE_DDR_1V8_HIGH_SPEED | + EXT_CSD_DEVICE_TYPE_DDR_1V2_HIGH_SPEED)) != 0U) { InstancePtr->Mode = XSDPS_DDR52_MODE; - if (InstancePtr->Config.OTapDly_DDR_Clk50 && - InstancePtr->Config.ITapDly_DDR_Clk50) { + if ((InstancePtr->Config.OTapDly_DDR_Clk50 != 0U) && + (InstancePtr->Config.ITapDly_DDR_Clk50 != 0U)) { InstancePtr->OTapDelay = InstancePtr->Config.OTapDly_DDR_Clk50; InstancePtr->ITapDelay = InstancePtr->Config.ITapDly_DDR_Clk50; } else { @@ -1403,10 +1366,10 @@ void XSdPs_IdentifyEmmcMode(XSdPs *InstancePtr, const u8 *ExtCsd) InstancePtr->ITapDelay = SD_ITAPDLYSEL_EMMC_DDR50; } } else if ((ExtCsd[EXT_CSD_DEVICE_TYPE_BYTE] & - EXT_CSD_DEVICE_TYPE_HIGH_SPEED) != 0U) { + EXT_CSD_DEVICE_TYPE_HIGH_SPEED) != 0U) { InstancePtr->Mode = XSDPS_HIGH_SPEED_MODE; - if (InstancePtr->Config.OTapDly_SDR_Clk50 && - InstancePtr->Config.ITapDly_SDR_Clk50) { + if ((InstancePtr->Config.OTapDly_SDR_Clk50 != 0U) && + (InstancePtr->Config.ITapDly_SDR_Clk50 != 0U)) { InstancePtr->OTapDelay = InstancePtr->Config.OTapDly_SDR_Clk50; InstancePtr->ITapDelay = InstancePtr->Config.ITapDly_SDR_Clk50; } else { @@ -1425,10 +1388,10 @@ void XSdPs_IdentifyEmmcMode(XSdPs *InstancePtr, const u8 *ExtCsd) /*****************************************************************************/ /** * @brief -* This function is used to check the eMMC timing. +* Checks the eMMC timing. * -* @param InstancePtr is a pointer to the instance to be worked on. -* @param ExtCsd is the extended CSD register from the card +* @param InstancePtr Pointer to the instance to be worked on. +* @param ExtCsd Extended CSD register from the card. * * @return None * @@ -1457,7 +1420,7 @@ s32 XSdPs_CheckEmmcTiming(XSdPs *InstancePtr, u8 *ExtCsd) goto RETURN_PATH; } } else if ((InstancePtr->Mode == XSDPS_HIGH_SPEED_MODE) || - (InstancePtr->Mode == XSDPS_DDR52_MODE)) { + (InstancePtr->Mode == XSDPS_DDR52_MODE)) { if (ExtCsd[EXT_CSD_HS_TIMING_BYTE] != EXT_CSD_HS_TIMING_HIGH) { Status = XST_FAILURE; goto RETURN_PATH; @@ -1476,10 +1439,10 @@ RETURN_PATH: /*****************************************************************************/ /** * @brief -* This function is used to set the clock to the passed frequency. +* Sets the clock to the passed frequency. * -* @param InstancePtr is a pointer to the instance to be worked on. -* @param SelFreq is the selected frequency +* @param InstancePtr Pointer to the instance to be worked on. +* @param SelFreq Selected frequency * * @return None * @@ -1493,7 +1456,7 @@ s32 XSdPs_SetClock(XSdPs *InstancePtr, u32 SelFreq) /* Disable clock */ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, - XSDPS_CLK_CTRL_OFFSET, 0U); + XSDPS_CLK_CTRL_OFFSET, 0U); /* If selected frequency is zero, return from here */ if (SelFreq == 0U) { @@ -1504,30 +1467,30 @@ s32 XSdPs_SetClock(XSdPs *InstancePtr, u32 SelFreq) #ifdef VERSAL_NET if (InstancePtr->CardType == XSDPS_CHIP_EMMC) { Reg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress, - XSDPS_PHYCTRLREG2_OFFSET); + XSDPS_PHYCTRLREG2_OFFSET); Reg &= ~XSDPS_PHYREG2_DLL_EN_MASK; if ((InstancePtr->Mode != XSDPS_DEFAULT_SPEED_MODE) && - (SelFreq > XSDPD_MIN_DLL_MODE_CLK)) { + (SelFreq > XSDPD_MIN_DLL_MODE_CLK)) { XSdPs_WriteReg(InstancePtr->Config.BaseAddress, - XSDPS_PHYCTRLREG2_OFFSET, Reg); + XSDPS_PHYCTRLREG2_OFFSET, Reg); Reg &= ~XSDPS_PHYREG2_FREQ_SEL_MASK; Reg &= ~XSDPS_PHYREG2_TRIM_ICP_MASK; Reg &= ~XSDPS_PHYREG2_DLYTX_SEL_MASK; Reg &= ~XSDPS_PHYREG2_DLYRX_SEL_MASK; Reg |= (XSDPS_PHYREG2_TRIM_ICP_DEF_VAL << - XSDPS_PHYREG2_TRIM_ICP_SHIFT); + XSDPS_PHYREG2_TRIM_ICP_SHIFT); if (SelFreq == XSDPS_MMC_DDR_MAX_CLK) { Reg |= (XSDPS_FREQ_SEL_50MHZ_79MHz << - XSDPS_PHYREG2_FREQ_SEL_SHIFT); + XSDPS_PHYREG2_FREQ_SEL_SHIFT); } XSdPs_WriteReg(InstancePtr->Config.BaseAddress, - XSDPS_PHYCTRLREG2_OFFSET, Reg); + XSDPS_PHYCTRLREG2_OFFSET, Reg); } else { Reg |= XSDPS_PHYREG2_DLYTX_SEL_MASK; Reg |= XSDPS_PHYREG2_DLYRX_SEL_MASK; XSdPs_WriteReg(InstancePtr->Config.BaseAddress, - XSDPS_PHYCTRLREG2_OFFSET, Reg); + XSDPS_PHYCTRLREG2_OFFSET, Reg); } } #endif @@ -1543,17 +1506,17 @@ s32 XSdPs_SetClock(XSdPs *InstancePtr, u32 SelFreq) #ifdef VERSAL_NET if ((InstancePtr->CardType == XSDPS_CHIP_EMMC) && - (InstancePtr->Mode != XSDPS_DEFAULT_SPEED_MODE) && - (SelFreq > XSDPD_MIN_DLL_MODE_CLK)) { + (InstancePtr->Mode != XSDPS_DEFAULT_SPEED_MODE) && + (SelFreq > XSDPD_MIN_DLL_MODE_CLK)) { Reg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress, - XSDPS_PHYCTRLREG2_OFFSET); + XSDPS_PHYCTRLREG2_OFFSET); Reg |= XSDPS_PHYREG2_DLL_EN_MASK; XSdPs_WriteReg(InstancePtr->Config.BaseAddress, - XSDPS_PHYCTRLREG2_OFFSET, Reg); + XSDPS_PHYCTRLREG2_OFFSET, Reg); /* Wait for 1000 micro sec for DLL READY */ Status = Xil_WaitForEvent(InstancePtr->Config.BaseAddress + XSDPS_PHYCTRLREG2_OFFSET, - XSDPS_PHYREG2_DLL_RDY_MASK, XSDPS_PHYREG2_DLL_RDY_MASK, Timeout); + XSDPS_PHYREG2_DLL_RDY_MASK, XSDPS_PHYREG2_DLL_RDY_MASK, Timeout); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH ; @@ -1571,9 +1534,9 @@ RETURN_PATH: /*****************************************************************************/ /** * @brief -* This function checks if the voltage is set to 1.8V or not. +* Checks if the voltage is set to 1.8 V or not. * -* @param InstancePtr is a pointer to the instance to be worked on. +* @param InstancePtr Pointer to the instance to be worked on. * * @return * - XST_SUCCESS if voltage is 1.8V @@ -1585,7 +1548,7 @@ s32 XSdPs_CheckVoltage18(XSdPs *InstancePtr) u32 Status; if ((XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, - XSDPS_HOST_CTRL2_OFFSET) & XSDPS_HC2_1V8_EN_MASK) == 0U) { + XSDPS_HOST_CTRL2_OFFSET) & XSDPS_HC2_1V8_EN_MASK) == 0U) { Status = XST_FAILURE; goto RETURN_PATH; } @@ -1599,10 +1562,10 @@ RETURN_PATH: /*****************************************************************************/ /** * @brief -* This function initializes the command sequence. +* Initializes the command sequence. * -* @param InstancePtr is a pointer to the instance to be worked on. -* @param Arg is the address passed by the user that is to be sent as +* @param InstancePtr Pointer to the instance to be worked on. +* @param Arg Address passed by the user that is to be sent as * argument along with the command. * @param BlkCnt - Block count passed by the user. * @@ -1625,19 +1588,19 @@ s32 XSdPs_SetupCmd(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt) /* Write block count register */ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, - XSDPS_BLK_CNT_OFFSET, (u16)BlkCnt); + XSDPS_BLK_CNT_OFFSET, (u16)BlkCnt); XSdPs_WriteReg8(InstancePtr->Config.BaseAddress, XSDPS_TIMEOUT_CTRL_OFFSET, 0xEU); /* Write argument register */ XSdPs_WriteReg(InstancePtr->Config.BaseAddress, - XSDPS_ARGMT_OFFSET, Arg); + XSDPS_ARGMT_OFFSET, Arg); XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, - XSDPS_NORM_INTR_STS_OFFSET, XSDPS_NORM_INTR_ALL_MASK); + XSDPS_NORM_INTR_STS_OFFSET, XSDPS_NORM_INTR_ALL_MASK); XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, - XSDPS_ERR_INTR_STS_OFFSET, XSDPS_ERROR_INTR_ALL_MASK); + XSDPS_ERR_INTR_STS_OFFSET, XSDPS_ERROR_INTR_ALL_MASK); Status = XST_SUCCESS; @@ -1648,10 +1611,10 @@ RETURN_PATH: /*****************************************************************************/ /** * @brief -* This function initiates the Cmd transfer to SD card. +* Initiates the Cmd transfer to SD card. * -* @param InstancePtr is a pointer to the instance to be worked on. -* @param Cmd is the command to be sent +* @param InstancePtr Pointer to the instance to be worked on. +* @param Cmd Command to be sent * * @return * - XST_SUCCESS if initialization was successful @@ -1680,16 +1643,16 @@ s32 XSdPs_SendCmd(XSdPs *InstancePtr, u32 Cmd) */ if ((Cmd != CMD21) && (Cmd != CMD19)) { PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress, - XSDPS_PRES_STATE_OFFSET); + XSDPS_PRES_STATE_OFFSET); if (((PresentStateReg & XSDPS_PSR_INHIBIT_DAT_MASK) != 0U) && - ((CommandReg & XSDPS_DAT_PRESENT_SEL_MASK) != 0U)) { + ((CommandReg & XSDPS_DAT_PRESENT_SEL_MASK) != 0U)) { Status = XST_FAILURE; goto RETURN_PATH; } } XSdPs_WriteReg(InstancePtr->Config.BaseAddress, XSDPS_XFER_MODE_OFFSET, - (CommandReg << 16) | InstancePtr->TransferMode); + (CommandReg << 16) | InstancePtr->TransferMode); Status = XST_SUCCESS; @@ -1701,10 +1664,10 @@ RETURN_PATH: /*****************************************************************************/ /** * @brief -* This function performs Set the address of the first write block to be erased. +* Sets the address of the first write block to be erased. * -* @param InstancePtr is a pointer to the instance to be worked on. -* @param StartAddr is the address of the first write block. +* @param InstancePtr Pointer to the instance to be worked on. +* @param StartAddr Address of the first write block. * * @return * - XST_SUCCESS if Set start Address is successful @@ -1727,10 +1690,10 @@ s32 XSdPs_SetStartAddr(XSdPs *InstancePtr, u32 StartAddr) /*****************************************************************************/ /** * @brief -* This function performs Set the address of the last write block to be erased. +* Sets the address of the last write block to be erased. * -* @param InstancePtr is a pointer to the instance to be worked on. -* @param EndAddr is the address of the last write block. +* @param InstancePtr Pointer to the instance to be worked on. +* @param EndAddr Address of the last write block. * * @return * - XST_SUCCESS if Set End Address is successful. @@ -1753,9 +1716,9 @@ s32 XSdPs_SetEndAddr(XSdPs *InstancePtr, u32 EndAddr) /*****************************************************************************/ /** * @brief -* This function send Erase command to the device and wait for transfer complete +* Sends Erase command to the device and wait for transfer complete. * -* @param InstancePtr is a pointer to the instance to be worked on. +* @param InstancePtr Pointer to the instance to be worked on. * * @return * - XST_SUCCESS if erase operation is successful diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/sdps/src/xsdps_core.h b/bsp_z7/ps7_cortexa9_0/libsrc/sdps/src/xsdps_core.h index 239c2f1..9a5a289 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/sdps/src/xsdps_core.h +++ b/bsp_z7/ps7_cortexa9_0/libsrc/sdps/src/xsdps_core.h @@ -1,6 +1,6 @@ /****************************************************************************** * Copyright (C) 2013 - 2022 Xilinx, Inc. All rights reserved. -* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved. +* Copyright (c) 2022 - 2024 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -8,10 +8,10 @@ /** * * @file xsdps_core.h -* @addtogroup sdps Overview +* @addtogroup sdps_api SDPS APIs * @{ * -* The xsdps_core.h header file contains the identifiers and basic HW access driver +* The xsdps_core.h header file contains the identifiers and basic hardware access driver * functions (or macros) that can be used to access the device. Other driver * functions are defined in xsdps.h. * @@ -27,6 +27,7 @@ * mn 11/28/21 Fix MISRA-C violations. * 4.0 sk 02/25/22 Add support for eMMC5.1. * 4.1 sa 01/06/23 Include xil_util.h in this file. +* 4.2 ap 08/09/23 Add XSdPs_SetTapDelay APIs. * * ******************************************************************************/ @@ -110,6 +111,10 @@ void XSdPs_ConfigInterrupt(XSdPs *InstancePtr); s32 XSdPs_SendErase(XSdPs *InstancePtr); s32 XSdPs_SetEndAddr(XSdPs *InstancePtr, u32 EndAddr); s32 XSdPs_SetStartAddr(XSdPs *InstancePtr, u32 StartAddr); +void XSdPs_SetTapDelay_SDR104(XSdPs *InstancePtr); +void XSdPs_SetTapDelay_SDR50(XSdPs *InstancePtr); +void XSdPs_SetTapDelay_DDR50(XSdPs *InstancePtr); +void XSdPs_SetTapDelay_SDR25(XSdPs *InstancePtr); #ifdef VERSAL_NET u32 XSdPs_Select_HS400(XSdPs *InstancePtr); #endif diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/sdps/src/xsdps_g.c b/bsp_z7/ps7_cortexa9_0/libsrc/sdps/src/xsdps_g.c index 8c533f0..5d3a139 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/sdps/src/xsdps_g.c +++ b/bsp_z7/ps7_cortexa9_0/libsrc/sdps/src/xsdps_g.c @@ -1,6 +1,6 @@ /****************************************************************************** * Copyright (C) 2013 - 2022 Xilinx, Inc. All rights reserved. -* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved. +* Copyright (c) 2022 - 2024 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -8,7 +8,7 @@ /** * * @file xsdps_g.c -* @addtogroup sdps Overview +* @addtogroup sdps_api SDPS APIs * @{ * * The xsdps_g.c file contains a configuration table that specifies the @@ -54,7 +54,8 @@ XSdPs_Config XSdPs_ConfigTable[] = XPAR_XSDPS_0_CLK_50_DDR_ITAP_DLY, XPAR_XSDPS_0_CLK_50_DDR_OTAP_DLY, XPAR_XSDPS_0_CLK_100_SDR_OTAP_DLY, - XPAR_XSDPS_0_CLK_200_SDR_OTAP_DLY + XPAR_XSDPS_0_CLK_200_SDR_OTAP_DLY, + XPAR_XSDPS_0_CLK_200_DDR_OTAP_DLY } }; /** @} */ diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/sdps/src/xsdps_host.c b/bsp_z7/ps7_cortexa9_0/libsrc/sdps/src/xsdps_host.c index 5f4165c..26a25dc 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/sdps/src/xsdps_host.c +++ b/bsp_z7/ps7_cortexa9_0/libsrc/sdps/src/xsdps_host.c @@ -1,6 +1,6 @@ /****************************************************************************** * Copyright (C) 2013 - 2022 Xilinx, Inc. All rights reserved. -* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved. +* Copyright (c) 2022 - 2024 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -8,7 +8,7 @@ /** * * @file xsdps_host.c -* @addtogroup sdps Overview +* @addtogroup sdps_api SDPS APIs * @{ * * The xsdps_host.c file contains the interface functions of the XSdPs driver. @@ -39,6 +39,8 @@ * sa 01/04/23 Update register bit polling logic to use Xil_WaitForEvent/ * Xil_WaitForEvents API. * sa 01/25/23 Use instance structure to store DMA descriptor tables. +* 4.2 ap 08/09/23 Restructured XSdPs_FrameCmd API +* 4.3 ap 12/22/23 Add support to read custom HS400 tap delay value from design for eMMC. * * ******************************************************************************/ @@ -58,11 +60,109 @@ void XSdps_Smc(XSdPs *InstancePtr, u32 RegOffset, u32 Mask, u32 Val) { (void)Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(InstancePtr->SlcrBaseAddr + - RegOffset) | ((u64)Mask << 32), - (u64)Val, 0, 0, 0, 0, 0); + RegOffset) | ((u64)Mask << 32), + (u64)Val, 0, 0, 0, 0, 0); } #endif +/*****************************************************************************/ +/** +* @brief +* Sets the tap delay for SDR104 uhs mode. +* +* @param InstancePtr Pointer to the instance to be worked on. +* +* @return None +* +*******************************************************************************/ +void XSdPs_SetTapDelay_SDR104(XSdPs *InstancePtr) +{ + if (InstancePtr->Config.OTapDly_SDR_Clk200 != 0U) { + InstancePtr->OTapDelay = InstancePtr->Config.OTapDly_SDR_Clk200; + } else if (InstancePtr->Config.BankNumber == 2U) { + InstancePtr->OTapDelay = SD_OTAPDLYSEL_SD104_B2; + } else { + InstancePtr->OTapDelay = SD_OTAPDLYSEL_SD104_B0; + } +} + +/*****************************************************************************/ +/** +* @brief +* Sets the tap delay for SDR50 uhs mode. +* +* @param InstancePtr Pointer to the instance to be worked on. +* +* @return None +* +*******************************************************************************/ +void XSdPs_SetTapDelay_SDR50(XSdPs *InstancePtr) +{ + if (InstancePtr->Config.OTapDly_SDR_Clk100 != 0U) { + InstancePtr->OTapDelay = InstancePtr->Config.OTapDly_SDR_Clk100; + } else { + InstancePtr->OTapDelay = SD_OTAPDLYSEL_SD50; + } +} + +/*****************************************************************************/ +/** +* @brief +* Sets the tap delay for DDR50 uhs mode. +* +* @param InstancePtr Pointer to the instance to be worked on. +* +* @return None +* +*******************************************************************************/ +void XSdPs_SetTapDelay_DDR50(XSdPs *InstancePtr) +{ + if ((InstancePtr->Config.OTapDly_DDR_Clk50 != 0U) && + (InstancePtr->Config.ITapDly_DDR_Clk50 != 0U)) { + InstancePtr->OTapDelay = InstancePtr->Config.OTapDly_DDR_Clk50; + InstancePtr->ITapDelay = InstancePtr->Config.ITapDly_DDR_Clk50; + if ((InstancePtr->Config.SlotType == XSDPS_SLOTTYPE_SDADIR) && + (InstancePtr->ITapDelay == SD_ITAPDLYSEL_SD_DDR50)) { + InstancePtr->ITapDelay = SD_AUTODIR_ITAPDLYSEL_DDR50; + } + } else if (InstancePtr->Config.SlotType == XSDPS_SLOTTYPE_SDADIR) { + InstancePtr->ITapDelay = SD_AUTODIR_ITAPDLYSEL_DDR50; + InstancePtr->OTapDelay = SD_OTAPDLYSEL_SD_DDR50; + } else { + InstancePtr->ITapDelay = SD_ITAPDLYSEL_SD_DDR50; + InstancePtr->OTapDelay = SD_OTAPDLYSEL_SD_DDR50; + } +} + +/*****************************************************************************/ +/** +* @brief +* Sets the tap delay for SDR25 uhs mode. +* +* @param InstancePtr Pointer to the instance to be worked on. +* +* @return None +* +*******************************************************************************/ +void XSdPs_SetTapDelay_SDR25(XSdPs *InstancePtr) +{ + if ((InstancePtr->Config.OTapDly_SDR_Clk50 != 0U) && + (InstancePtr->Config.ITapDly_SDR_Clk50 != 0U)) { + InstancePtr->OTapDelay = InstancePtr->Config.OTapDly_SDR_Clk50; + InstancePtr->ITapDelay = InstancePtr->Config.ITapDly_SDR_Clk50; + if ((InstancePtr->Config.SlotType == XSDPS_SLOTTYPE_SDADIR) && + (InstancePtr->ITapDelay == SD_ITAPDLYSEL_HSD)) { + InstancePtr->ITapDelay = SD_AUTODIR_ITAPDLYSEL_SDR25; + } + } else if (InstancePtr->Config.SlotType == XSDPS_SLOTTYPE_SDADIR) { + InstancePtr->ITapDelay = SD_AUTODIR_ITAPDLYSEL_SDR25; + InstancePtr->OTapDelay = SD_OTAPDLYSEL_SD_HSD; + } else { + InstancePtr->ITapDelay = SD_ITAPDLYSEL_HSD; + InstancePtr->OTapDelay = SD_OTAPDLYSEL_SD_HSD; + } +} + /*****************************************************************************/ /** * @@ -70,7 +170,7 @@ void XSdps_Smc(XSdPs *InstancePtr, u32 RegOffset, u32 Mask, u32 Val) * Switches the SD card voltage from 3v3 to 1v8 * * -* @param InstancePtr is a pointer to the XSdPs instance. +* @param InstancePtr Pointer to the XSdPs instance. * ******************************************************************************/ s32 XSdPs_Switch_Voltage(XSdPs *InstancePtr) @@ -104,9 +204,9 @@ RETURN_PATH: /*****************************************************************************/ /** * @brief -* This function initiates the transfer to or from SD card. +* Initiates the transfer to or from SD card. * -* @param InstancePtr is a pointer to the instance to be worked on. +* @param InstancePtr Pointer to the instance to be worked on. * * @return * - XST_SUCCESS if initialization was successful @@ -119,12 +219,12 @@ s32 XSdPs_SetupTransfer(XSdPs *InstancePtr) s32 Status; if ((InstancePtr->HC_Version != XSDPS_HC_SPEC_V3) || - ((InstancePtr->Host_Caps & XSDPS_CAPS_SLOT_TYPE_MASK) - != XSDPS_CAPS_EMB_SLOT)) { - if(InstancePtr->Config.CardDetect != 0U) { + ((InstancePtr->Host_Caps & XSDPS_CAPS_SLOT_TYPE_MASK) + != XSDPS_CAPS_EMB_SLOT)) { + if (InstancePtr->Config.CardDetect != 0U) { /* Check status to ensure card is initialized */ PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress, - XSDPS_PRES_STATE_OFFSET); + XSDPS_PRES_STATE_OFFSET); if ((PresentStateReg & XSDPS_PSR_CARD_INSRT_MASK) == 0x0U) { Status = XST_FAILURE; goto RETURN_PATH; @@ -133,10 +233,10 @@ s32 XSdPs_SetupTransfer(XSdPs *InstancePtr) } /* Set block size to 512 if not already set */ - if(XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, - XSDPS_BLK_SIZE_OFFSET) != XSDPS_BLK_SIZE_512_MASK ) { + if (XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, + XSDPS_BLK_SIZE_OFFSET) != XSDPS_BLK_SIZE_512_MASK ) { Status = XSdPs_SetBlkSize(InstancePtr, - XSDPS_BLK_SIZE_512_MASK); + XSDPS_BLK_SIZE_512_MASK); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; @@ -153,10 +253,10 @@ RETURN_PATH: /*****************************************************************************/ /** * @brief -* This function resets the SD card. +* Resets the SD card. * -* @param InstancePtr is a pointer to the instance to be worked on. -* @param Value is the type of reset +* @param InstancePtr Pointer to the instance to be worked on. +* @param Value Type of reset * * @return * - XST_SUCCESS if initialization was successful @@ -177,16 +277,16 @@ s32 XSdPs_Reset(XSdPs *InstancePtr, u8 Value) goto RETURN_PATH ; } - RETURN_PATH: - return Status; +RETURN_PATH: + return Status; } /*****************************************************************************/ /** * @brief -* This function sets bit to start execution of tuning. +* Sets bit to start execution of tuning. * -* @param InstancePtr is a pointer to the instance to be worked on. +* @param InstancePtr Pointer to the instance to be worked on. * * @return None * @@ -196,18 +296,18 @@ void XSdPs_SetExecTuning(XSdPs *InstancePtr) u16 CtrlReg; CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, - XSDPS_HOST_CTRL2_OFFSET); + XSDPS_HOST_CTRL2_OFFSET); CtrlReg |= XSDPS_HC2_EXEC_TNG_MASK; XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, - XSDPS_HOST_CTRL2_OFFSET, CtrlReg); + XSDPS_HOST_CTRL2_OFFSET, CtrlReg); } /*****************************************************************************/ /** * @brief -* This function does SD mode initialization. +* Initializes SD mode. * -* @param InstancePtr is a pointer to the instance to be worked on. +* @param InstancePtr Pointer to the instance to be worked on. * * @return * - XST_SUCCESS if initialization is successful @@ -250,9 +350,9 @@ s32 XSdPs_SdModeInit(XSdPs *InstancePtr) } if (((SCR[2] & SCR_SPEC_VER_3) != 0U) && - (ReadBuff[13] >= UHS_SDR50_SUPPORT) && - (InstancePtr->Config.BusWidth == XSDPS_WIDTH_8) && - (InstancePtr->Switch1v8 == 0U)) { + (ReadBuff[13] >= UHS_SDR50_SUPPORT) && + (InstancePtr->Config.BusWidth == XSDPS_WIDTH_8) && + (InstancePtr->Switch1v8 == 0U)) { InstancePtr->Switch1v8 = 1U; @@ -282,14 +382,14 @@ s32 XSdPs_SdModeInit(XSdPs *InstancePtr) if (SCR[0] != 0U) { /* Check for high speed support */ if (((ReadBuff[13] & HIGH_SPEED_SUPPORT) != 0U) && - (InstancePtr->BusWidth >= XSDPS_4_BIT_WIDTH)) { + (InstancePtr->BusWidth >= XSDPS_4_BIT_WIDTH)) { InstancePtr->Mode = XSDPS_HIGH_SPEED_MODE; if (InstancePtr->Config.OTapDly_SDR_Clk50 && - InstancePtr->Config.ITapDly_SDR_Clk50) { + InstancePtr->Config.ITapDly_SDR_Clk50) { InstancePtr->OTapDelay = InstancePtr->Config.OTapDly_SDR_Clk50; InstancePtr->ITapDelay = InstancePtr->Config.ITapDly_SDR_Clk50; if ((InstancePtr->Config.SlotType == XSDPS_SLOTTYPE_SDADIR) && - (InstancePtr->ITapDelay == SD_ITAPDLYSEL_HSD)) { + (InstancePtr->ITapDelay == SD_ITAPDLYSEL_HSD)) { InstancePtr->ITapDelay = SD_AUTODIR_ITAPDLYSEL_HSD; } } else if (InstancePtr->Config.SlotType == XSDPS_SLOTTYPE_SDADIR) { @@ -325,9 +425,9 @@ RETURN_PATH: /*****************************************************************************/ /** * @brief -* This function does MMC mode initialization. +* Initializes MMC mode. * -* @param InstancePtr is a pointer to the instance to be worked on. +* @param InstancePtr Pointer to the instance to be worked on. * * @return * - XST_SUCCESS if initialization is successful @@ -363,8 +463,8 @@ s32 XSdPs_MmcModeInit(XSdPs *InstancePtr) InstancePtr->SectorCount |= (u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE1]; if (((ExtCsd[EXT_CSD_DEVICE_TYPE_BYTE] & - EXT_CSD_DEVICE_TYPE_HIGH_SPEED) != 0U) && - (InstancePtr->BusWidth >= XSDPS_4_BIT_WIDTH)) { + EXT_CSD_DEVICE_TYPE_HIGH_SPEED) != 0U) && + (InstancePtr->BusWidth >= XSDPS_4_BIT_WIDTH)) { InstancePtr->Mode = XSDPS_HIGH_SPEED_MODE; Status = XSdPs_Change_BusSpeed(InstancePtr); if (Status != XST_SUCCESS) { @@ -393,9 +493,9 @@ RETURN_PATH: /*****************************************************************************/ /** * @brief -* This function does eMMC mode initialization. +* Initializes eMMC mode. * -* @param InstancePtr is a pointer to the instance to be worked on. +* @param InstancePtr Pointer to the instance to be worked on. * * @return * - XST_SUCCESS if initialization is successful @@ -414,7 +514,7 @@ s32 XSdPs_EmmcModeInit(XSdPs *InstancePtr) #endif if ((InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) && - (InstancePtr->Config.BusWidth == XSDPS_WIDTH_8)) { + (InstancePtr->Config.BusWidth == XSDPS_WIDTH_8)) { /* in case of eMMC data width 8-bit */ InstancePtr->BusWidth = XSDPS_8_BIT_WIDTH; } else if (InstancePtr->Config.BusWidth == XSDPS_WIDTH_4) { @@ -468,7 +568,7 @@ s32 XSdPs_EmmcModeInit(XSdPs *InstancePtr) } /* Enable Rst_n_Fun bit if it is disabled */ - if(ExtCsd[EXT_CSD_RST_N_FUN_BYTE] == EXT_CSD_RST_N_FUN_TEMP_DIS) { + if (ExtCsd[EXT_CSD_RST_N_FUN_BYTE] == EXT_CSD_RST_N_FUN_TEMP_DIS) { Status = XSdPs_Set_Mmc_ExtCsd(InstancePtr, XSDPS_MMC_RST_FUN_EN_ARG); if (Status != XST_SUCCESS) { Status = XST_FAILURE; @@ -485,9 +585,9 @@ RETURN_PATH: /*****************************************************************************/ /** * @brief -* This function disables the bus power. +* Disables the bus power. * -* @param InstancePtr is a pointer to the instance to be worked on. +* @param InstancePtr Pointer to the instance to be worked on. * * @return None * @@ -510,9 +610,9 @@ void XSdPs_DisableBusPower(XSdPs *InstancePtr) /*****************************************************************************/ /** * @brief -* This function enables the bus power. +* Enables the bus power. * -* @param InstancePtr is a pointer to the instance to be worked on. +* @param InstancePtr Pointer to the instance to be worked on. * * @return None * @@ -538,9 +638,9 @@ void XSdPs_EnableBusPower(XSdPs *InstancePtr) /*****************************************************************************/ /** * @brief -* This function enumerates the SD card. +* Enumerates the SD card. * -* @param InstancePtr is a pointer to the instance to be worked on. +* @param InstancePtr Pointer to the instance to be worked on. * * @return None * @@ -617,16 +717,16 @@ s32 XSdPs_SdCardEnum(XSdPs *InstancePtr) Status = XST_SUCCESS; - RETURN_PATH: - return Status; +RETURN_PATH: + return Status; } /*****************************************************************************/ /** * @brief -* This function enumerates the MMC card. +* Enumerates the MMC card. * -* @param InstancePtr is a pointer to the instance to be worked on. +* @param InstancePtr Pointer to the instance to be worked on. * * @return None * @@ -694,9 +794,9 @@ RETURN_PATH: /*****************************************************************************/ /** * @brief -* This function performs SD tuning. +* Performs SD tuning. * -* @param InstancePtr is a pointer to the instance to be worked on. +* @param InstancePtr Pointer to the instance to be worked on. * * @return None * @@ -742,10 +842,10 @@ RETURN_PATH: /*****************************************************************************/ /** * @brief -* This function is used to enable the clock. +* Enables the clock. * -* @param InstancePtr is a pointer to the instance to be worked on. -* @param ClockReg is the clock value to be set. +* @param InstancePtr Pointer to the instance to be worked on. +* @param ClockReg Clock value to be set. * * @return * - XST_SUCCESS if success @@ -760,11 +860,11 @@ s32 XSdPs_EnableClock(XSdPs *InstancePtr, u16 ClockReg) ClkReg |= (u16)XSDPS_CC_INT_CLK_EN_MASK; XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, - XSDPS_CLK_CTRL_OFFSET, ClkReg); + XSDPS_CLK_CTRL_OFFSET, ClkReg); /* Wait for 150ms for internal clock to stabilize */ Status = Xil_WaitForEvent(InstancePtr->Config.BaseAddress + XSDPS_CLK_CTRL_OFFSET, - XSDPS_CC_INT_CLK_STABLE_MASK, XSDPS_CC_INT_CLK_STABLE_MASK, Timeout); + XSDPS_CC_INT_CLK_STABLE_MASK, XSDPS_CC_INT_CLK_STABLE_MASK, Timeout); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH ; @@ -773,7 +873,7 @@ s32 XSdPs_EnableClock(XSdPs *InstancePtr, u16 ClockReg) /* Enable SD clock */ ClkReg |= XSDPS_CC_SD_CLK_EN_MASK; XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, - XSDPS_CLK_CTRL_OFFSET, ClkReg); + XSDPS_CLK_CTRL_OFFSET, ClkReg); Status = XST_SUCCESS; @@ -784,10 +884,10 @@ RETURN_PATH: /*****************************************************************************/ /** * @brief -* This function is used to calculate the bus speed. +* Calculates the bus speed. * -* @param InstancePtr is a pointer to the instance to be worked on. -* @param Arg is the argument to be sent along with the command. +* @param InstancePtr Pointer to the instance to be worked on. +* @param Arg Argument to be sent along with the command. * This could be address or any other information * * @return @@ -801,61 +901,61 @@ s32 XSdPs_CalcBusSpeed(XSdPs *InstancePtr, u32 *Arg) if (InstancePtr->CardType == XSDPS_CARD_SD) { switch (InstancePtr->Mode) { - case XSDPS_UHS_SPEED_MODE_SDR12: - *Arg = XSDPS_SWITCH_CMD_SDR12_SET; - InstancePtr->BusSpeed = XSDPS_SD_SDR12_MAX_CLK; - break; - case XSDPS_UHS_SPEED_MODE_SDR25: - *Arg = XSDPS_SWITCH_CMD_SDR25_SET; - InstancePtr->BusSpeed = XSDPS_SD_SDR25_MAX_CLK; - break; - case XSDPS_UHS_SPEED_MODE_SDR50: - *Arg = XSDPS_SWITCH_CMD_SDR50_SET; - InstancePtr->BusSpeed = XSDPS_SD_SDR50_MAX_CLK; - break; - case XSDPS_UHS_SPEED_MODE_SDR104: - *Arg = XSDPS_SWITCH_CMD_SDR104_SET; - InstancePtr->BusSpeed = XSDPS_SD_SDR104_MAX_CLK; - break; - case XSDPS_UHS_SPEED_MODE_DDR50: - *Arg = XSDPS_SWITCH_CMD_DDR50_SET; - InstancePtr->BusSpeed = XSDPS_SD_DDR50_MAX_CLK; - break; - case XSDPS_HIGH_SPEED_MODE: - *Arg = XSDPS_SWITCH_CMD_HS_SET; - InstancePtr->BusSpeed = XSDPS_CLK_50_MHZ; - break; - default: - Status = XST_FAILURE; - break; + case XSDPS_UHS_SPEED_MODE_SDR12: + *Arg = XSDPS_SWITCH_CMD_SDR12_SET; + InstancePtr->BusSpeed = XSDPS_SD_SDR12_MAX_CLK; + break; + case XSDPS_UHS_SPEED_MODE_SDR25: + *Arg = XSDPS_SWITCH_CMD_SDR25_SET; + InstancePtr->BusSpeed = XSDPS_SD_SDR25_MAX_CLK; + break; + case XSDPS_UHS_SPEED_MODE_SDR50: + *Arg = XSDPS_SWITCH_CMD_SDR50_SET; + InstancePtr->BusSpeed = XSDPS_SD_SDR50_MAX_CLK; + break; + case XSDPS_UHS_SPEED_MODE_SDR104: + *Arg = XSDPS_SWITCH_CMD_SDR104_SET; + InstancePtr->BusSpeed = XSDPS_SD_SDR104_MAX_CLK; + break; + case XSDPS_UHS_SPEED_MODE_DDR50: + *Arg = XSDPS_SWITCH_CMD_DDR50_SET; + InstancePtr->BusSpeed = XSDPS_SD_DDR50_MAX_CLK; + break; + case XSDPS_HIGH_SPEED_MODE: + *Arg = XSDPS_SWITCH_CMD_HS_SET; + InstancePtr->BusSpeed = XSDPS_CLK_50_MHZ; + break; + default: + Status = XST_FAILURE; + break; } } else { switch (InstancePtr->Mode) { #ifdef VERSAL_NET - case XSDPS_HS400_MODE: - if (InstancePtr->IsTuningDone == 0U) { - *Arg = XSDPS_MMC_HS200_ARG; - } else { - *Arg = XSDPS_MMC_HS400_ARG; - } - InstancePtr->BusSpeed = XSDPS_MMC_HS200_MAX_CLK; - break; + case XSDPS_HS400_MODE: + if (InstancePtr->IsTuningDone == 0U) { + *Arg = XSDPS_MMC_HS200_ARG; + } else { + *Arg = XSDPS_MMC_HS400_ARG; + } + InstancePtr->BusSpeed = XSDPS_MMC_HS200_MAX_CLK; + break; #endif - case XSDPS_HS200_MODE: - *Arg = XSDPS_MMC_HS200_ARG; - InstancePtr->BusSpeed = XSDPS_MMC_HS200_MAX_CLK; - break; - case XSDPS_DDR52_MODE: - *Arg = XSDPS_MMC_HIGH_SPEED_ARG; - InstancePtr->BusSpeed = XSDPS_MMC_DDR_MAX_CLK; - break; - case XSDPS_HIGH_SPEED_MODE: - *Arg = XSDPS_MMC_HIGH_SPEED_ARG; - InstancePtr->BusSpeed = XSDPS_MMC_HSD_MAX_CLK; - break; - default: - Status = XST_FAILURE; - break; + case XSDPS_HS200_MODE: + *Arg = XSDPS_MMC_HS200_ARG; + InstancePtr->BusSpeed = XSDPS_MMC_HS200_MAX_CLK; + break; + case XSDPS_DDR52_MODE: + *Arg = XSDPS_MMC_HIGH_SPEED_ARG; + InstancePtr->BusSpeed = XSDPS_MMC_DDR_MAX_CLK; + break; + case XSDPS_HIGH_SPEED_MODE: + *Arg = XSDPS_MMC_HIGH_SPEED_ARG; + InstancePtr->BusSpeed = XSDPS_MMC_HSD_MAX_CLK; + break; + default: + Status = XST_FAILURE; + break; } } @@ -867,10 +967,10 @@ s32 XSdPs_CalcBusSpeed(XSdPs *InstancePtr, u32 *Arg) * @brief * This function is used to do the DMA transfer to or from SD card. * -* @param InstancePtr is a pointer to the instance to be worked on. -* @param BlkCnt - Block count passed by the user. -* @param BlkSize - Block size passed by the user. -* @param Buff - Pointer to the data buffer for a DMA transfer. +* @param InstancePtr Pointer to the instance to be worked on. +* @param BlkCnt Block count passed by the user. +* @param BlkSize Block size passed by the user. +* @param Buff Pointer to the data buffer for a DMA transfer. * * @return * - XST_SUCCESS if initialization was successful @@ -883,7 +983,7 @@ void XSdPs_SetupReadDma(XSdPs *InstancePtr, u16 BlkCnt, u16 BlkSize, u8 *Buff) BlkSize &= XSDPS_BLK_SIZE_MASK; XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, - XSDPS_BLK_SIZE_OFFSET, BlkSize); + XSDPS_BLK_SIZE_OFFSET, BlkSize); if (InstancePtr->Dma64BitAddr >= ADDRESS_BEYOND_32BIT) { XSdPs_SetupADMA2DescTbl64Bit(InstancePtr, BlkCnt); @@ -891,17 +991,17 @@ void XSdPs_SetupReadDma(XSdPs *InstancePtr, u16 BlkCnt, u16 BlkSize, u8 *Buff) XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, Buff); if (InstancePtr->Config.IsCacheCoherent == 0U) { Xil_DCacheInvalidateRange((INTPTR)Buff, - ((INTPTR)BlkCnt * (INTPTR)BlkSize)); + ((INTPTR)BlkCnt * (INTPTR)BlkSize)); } } if (BlkCnt == 1U) { InstancePtr->TransferMode = XSDPS_TM_BLK_CNT_EN_MASK | - XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK; + XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK; } else { InstancePtr->TransferMode = XSDPS_TM_AUTO_CMD12_EN_MASK | - XSDPS_TM_BLK_CNT_EN_MASK | XSDPS_TM_DAT_DIR_SEL_MASK | - XSDPS_TM_DMA_EN_MASK | XSDPS_TM_MUL_SIN_BLK_SEL_MASK; + XSDPS_TM_BLK_CNT_EN_MASK | XSDPS_TM_DAT_DIR_SEL_MASK | + XSDPS_TM_DMA_EN_MASK | XSDPS_TM_MUL_SIN_BLK_SEL_MASK; } } @@ -910,10 +1010,10 @@ void XSdPs_SetupReadDma(XSdPs *InstancePtr, u16 BlkCnt, u16 BlkSize, u8 *Buff) * @brief * This function is used to do the DMA transfer to or from SD card. * -* @param InstancePtr is a pointer to the instance to be worked on. -* @param BlkCnt - Block count passed by the user. -* @param BlkSize - Block size passed by the user. -* @param Buff - Pointer to the data buffer for a DMA transfer. +* @param InstancePtr Pointer to the instance to be worked on. +* @param BlkCnt Block count passed by the user. +* @param BlkSize Block size passed by the user. +* @param Buff Pointer to the data buffer for a DMA transfer. * * @return * - XST_SUCCESS if initialization was successful @@ -926,7 +1026,7 @@ void XSdPs_SetupWriteDma(XSdPs *InstancePtr, u16 BlkCnt, u16 BlkSize, const u8 * BlkSize &= XSDPS_BLK_SIZE_MASK; XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, - XSDPS_BLK_SIZE_OFFSET, BlkSize); + XSDPS_BLK_SIZE_OFFSET, BlkSize); if (InstancePtr->Dma64BitAddr >= ADDRESS_BEYOND_32BIT) { XSdPs_SetupADMA2DescTbl64Bit(InstancePtr, BlkCnt); @@ -934,17 +1034,17 @@ void XSdPs_SetupWriteDma(XSdPs *InstancePtr, u16 BlkCnt, u16 BlkSize, const u8 * XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, Buff); if (InstancePtr->Config.IsCacheCoherent == 0U) { Xil_DCacheFlushRange((INTPTR)Buff, - ((INTPTR)BlkCnt * (INTPTR)BlkSize)); + ((INTPTR)BlkCnt * (INTPTR)BlkSize)); } } if (BlkCnt == 1U) { InstancePtr->TransferMode = XSDPS_TM_BLK_CNT_EN_MASK | - XSDPS_TM_DMA_EN_MASK; + XSDPS_TM_DMA_EN_MASK; } else { InstancePtr->TransferMode = XSDPS_TM_AUTO_CMD12_EN_MASK | - XSDPS_TM_BLK_CNT_EN_MASK | - XSDPS_TM_MUL_SIN_BLK_SEL_MASK | XSDPS_TM_DMA_EN_MASK; + XSDPS_TM_BLK_CNT_EN_MASK | + XSDPS_TM_MUL_SIN_BLK_SEL_MASK | XSDPS_TM_DMA_EN_MASK; } } @@ -952,16 +1052,15 @@ void XSdPs_SetupWriteDma(XSdPs *InstancePtr, u16 BlkCnt, u16 BlkSize, const u8 * /** * * @brief -* API to setup ADMA2 descriptor table for 32-bit DMA +* API to setup ADMA2 descriptor table for 32-bit DMA. * * -* @param InstancePtr is a pointer to the XSdPs instance. -* @param BlkCnt - block count. -* @param Buff pointer to data buffer. +* @param InstancePtr Pointer to the XSdPs instance. +* @param BlkCnt Block count. +* @param Buff Pointer to data buffer. * * @return None * -* @note None. * ******************************************************************************/ void XSdPs_Setup32ADMA2DescTbl(XSdPs *InstancePtr, u32 BlkCnt, const u8 *Buff) @@ -972,13 +1071,13 @@ void XSdPs_Setup32ADMA2DescTbl(XSdPs *InstancePtr, u32 BlkCnt, const u8 *Buff) /* Setup ADMA2 - Write descriptor table and point ADMA SAR to it */ BlkSize = (u32)XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, - XSDPS_BLK_SIZE_OFFSET) & - XSDPS_BLK_SIZE_MASK; + XSDPS_BLK_SIZE_OFFSET) & + XSDPS_BLK_SIZE_MASK; - if((BlkCnt*BlkSize) < XSDPS_DESC_MAX_LENGTH) { + if ((BlkCnt * BlkSize) < XSDPS_DESC_MAX_LENGTH) { TotalDescLines = 1U; } else { - TotalDescLines = ((BlkCnt*BlkSize) / XSDPS_DESC_MAX_LENGTH); + TotalDescLines = ((BlkCnt * BlkSize) / XSDPS_DESC_MAX_LENGTH); if (((BlkCnt * BlkSize) % XSDPS_DESC_MAX_LENGTH) != 0U) { TotalDescLines += 1U; } @@ -986,27 +1085,27 @@ void XSdPs_Setup32ADMA2DescTbl(XSdPs *InstancePtr, u32 BlkCnt, const u8 *Buff) for (DescNum = 0U; DescNum < (TotalDescLines - 1U); DescNum++) { InstancePtr->Adma2_DescrTbl32[DescNum].Address = - (u32)((UINTPTR)Buff + ((UINTPTR)DescNum*XSDPS_DESC_MAX_LENGTH)); + (u32)((UINTPTR)Buff + ((UINTPTR)DescNum * XSDPS_DESC_MAX_LENGTH)); InstancePtr->Adma2_DescrTbl32[DescNum].Attribute = - XSDPS_DESC_TRAN | XSDPS_DESC_VALID; + XSDPS_DESC_TRAN | XSDPS_DESC_VALID; InstancePtr->Adma2_DescrTbl32[DescNum].Length = 0U; } InstancePtr->Adma2_DescrTbl32[TotalDescLines - 1U].Address = - (u32)((UINTPTR)Buff + ((UINTPTR)DescNum*XSDPS_DESC_MAX_LENGTH)); + (u32)((UINTPTR)Buff + ((UINTPTR)DescNum * XSDPS_DESC_MAX_LENGTH)); InstancePtr->Adma2_DescrTbl32[TotalDescLines - 1U].Attribute = - XSDPS_DESC_TRAN | XSDPS_DESC_END | XSDPS_DESC_VALID; + XSDPS_DESC_TRAN | XSDPS_DESC_END | XSDPS_DESC_VALID; InstancePtr->Adma2_DescrTbl32[TotalDescLines - 1U].Length = - (u16)((BlkCnt*BlkSize) - (u32)(DescNum*XSDPS_DESC_MAX_LENGTH)); + (u16)((BlkCnt * BlkSize) - (u32)(DescNum * XSDPS_DESC_MAX_LENGTH)); XSdPs_WriteReg(InstancePtr->Config.BaseAddress, XSDPS_ADMA_SAR_OFFSET, - (u32)((UINTPTR)&(InstancePtr->Adma2_DescrTbl32[0]) & ~(u32)0x0U)); + (u32)((UINTPTR) & (InstancePtr->Adma2_DescrTbl32[0]) & ~(u32)0x0U)); if (InstancePtr->Config.IsCacheCoherent == 0U) { - Xil_DCacheFlushRange((INTPTR)&(InstancePtr->Adma2_DescrTbl32[0]), - (INTPTR)sizeof(XSdPs_Adma2Descriptor32) * (INTPTR)32U); + Xil_DCacheFlushRange((INTPTR) & (InstancePtr->Adma2_DescrTbl32[0]), + (INTPTR)sizeof(XSdPs_Adma2Descriptor32) * (INTPTR)32U); } } @@ -1014,17 +1113,15 @@ void XSdPs_Setup32ADMA2DescTbl(XSdPs *InstancePtr, u32 BlkCnt, const u8 *Buff) /** * * @brief -* API to setup ADMA2 descriptor table for 64-bit DMA +* API to setup ADMA2 descriptor table for 64-bit DMA. * * -* @param InstancePtr is a pointer to the XSdPs instance. -* @param BlkCnt - block count. -* @param Buff pointer to data buffer. +* @param InstancePtr Pointer to the XSdPs instance. +* @param BlkCnt Block count. +* @param Buff Pointer to data buffer. * * @return None * -* @note None. -* ******************************************************************************/ void XSdPs_Setup64ADMA2DescTbl(XSdPs *InstancePtr, u32 BlkCnt, const u8 *Buff) { @@ -1034,13 +1131,13 @@ void XSdPs_Setup64ADMA2DescTbl(XSdPs *InstancePtr, u32 BlkCnt, const u8 *Buff) /* Setup ADMA2 - Write descriptor table and point ADMA SAR to it */ BlkSize = (u32)XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, - XSDPS_BLK_SIZE_OFFSET) & - XSDPS_BLK_SIZE_MASK; + XSDPS_BLK_SIZE_OFFSET) & + XSDPS_BLK_SIZE_MASK; - if((BlkCnt*BlkSize) < XSDPS_DESC_MAX_LENGTH) { + if ((BlkCnt * BlkSize) < XSDPS_DESC_MAX_LENGTH) { TotalDescLines = 1U; } else { - TotalDescLines = ((BlkCnt*BlkSize) / XSDPS_DESC_MAX_LENGTH); + TotalDescLines = ((BlkCnt * BlkSize) / XSDPS_DESC_MAX_LENGTH); if (((BlkCnt * BlkSize) % XSDPS_DESC_MAX_LENGTH) != 0U) { TotalDescLines += 1U; } @@ -1048,42 +1145,42 @@ void XSdPs_Setup64ADMA2DescTbl(XSdPs *InstancePtr, u32 BlkCnt, const u8 *Buff) for (DescNum = 0U; DescNum < (TotalDescLines - 1U); DescNum++) { InstancePtr->Adma2_DescrTbl64[DescNum].Address = - ((UINTPTR)Buff + ((UINTPTR)DescNum*XSDPS_DESC_MAX_LENGTH)); + ((UINTPTR)Buff + ((UINTPTR)DescNum * XSDPS_DESC_MAX_LENGTH)); InstancePtr->Adma2_DescrTbl64[DescNum].Attribute = - XSDPS_DESC_TRAN | XSDPS_DESC_VALID; + XSDPS_DESC_TRAN | XSDPS_DESC_VALID; InstancePtr->Adma2_DescrTbl64[DescNum].Length = 0U; } InstancePtr->Adma2_DescrTbl64[TotalDescLines - 1U].Address = - (u64)((UINTPTR)Buff + ((UINTPTR)DescNum*XSDPS_DESC_MAX_LENGTH)); + (u64)((UINTPTR)Buff + ((UINTPTR)DescNum * XSDPS_DESC_MAX_LENGTH)); InstancePtr->Adma2_DescrTbl64[TotalDescLines - 1U].Attribute = - XSDPS_DESC_TRAN | XSDPS_DESC_END | XSDPS_DESC_VALID; + XSDPS_DESC_TRAN | XSDPS_DESC_END | XSDPS_DESC_VALID; InstancePtr->Adma2_DescrTbl64[TotalDescLines - 1U].Length = - (u16)((BlkCnt*BlkSize) - (u32)(DescNum*XSDPS_DESC_MAX_LENGTH)); + (u16)((BlkCnt * BlkSize) - (u32)(DescNum * XSDPS_DESC_MAX_LENGTH)); #if defined(__aarch64__) || defined(__arch64__) XSdPs_WriteReg(InstancePtr->Config.BaseAddress, XSDPS_ADMA_SAR_EXT_OFFSET, - (u32)((UINTPTR)(InstancePtr->Adma2_DescrTbl64)>>32U)); + (u32)((UINTPTR)(InstancePtr->Adma2_DescrTbl64) >> 32U)); #endif XSdPs_WriteReg(InstancePtr->Config.BaseAddress, XSDPS_ADMA_SAR_OFFSET, - (u32)((UINTPTR)&(InstancePtr->Adma2_DescrTbl64[0]) & ~(u32)0x0U)); + (u32)((UINTPTR) & (InstancePtr->Adma2_DescrTbl64[0]) & ~(u32)0x0U)); if (InstancePtr->Config.IsCacheCoherent == 0U) { - Xil_DCacheFlushRange((INTPTR)&(InstancePtr->Adma2_DescrTbl64[0]), - (INTPTR)sizeof(XSdPs_Adma2Descriptor64) * (INTPTR)32U); + Xil_DCacheFlushRange((INTPTR) & (InstancePtr->Adma2_DescrTbl64[0]), + (INTPTR)sizeof(XSdPs_Adma2Descriptor64) * (INTPTR)32U); } } /*****************************************************************************/ /** * @brief -* This function is used calculate the clock divisor value. +* Calculates the clock divisor value. * -* @param InstancePtr is a pointer to the instance to be worked on. -* @param SelFreq is the selected frequency +* @param InstancePtr Pointer to the instance to be worked on. +* @param SelFreq Selected frequency * * @return Clock divisor value * @@ -1126,11 +1223,11 @@ u32 XSdPs_CalcClock(XSdPs *InstancePtr, u32 SelFreq) /** * * @brief -* API to Set or Reset the DLL +* API to Set or Reset the DLL. * * -* @param InstancePtr is a pointer to the XSdPs instance. -* @param EnRst is a flag indicating whether to Assert or De-assert Reset. +* @param InstancePtr Pointer to the XSdPs instance. +* @param EnRst Flag indicating whether to Assert or De-assert Reset. * * @return None * @@ -1186,11 +1283,10 @@ void XSdPs_DllRstCtrl(XSdPs *InstancePtr, u8 EnRst) * Function to configure the Tap Delays. * * -* @param InstancePtr is a pointer to the XSdPs instance. +* @param InstancePtr Pointer to the XSdPs instance. * * @return None * -* @note None. * ******************************************************************************/ void XSdPs_ConfigTapDelay(XSdPs *InstancePtr) @@ -1238,7 +1334,7 @@ void XSdPs_ConfigTapDelay(XSdPs *InstancePtr) XSdps_Smc(InstancePtr, SD_ITAPDLY, SD0_ITAPCHGWIN, 0U); } else { XSdps_Smc(InstancePtr, SD_ITAPDLY, (SD0_ITAPDLY_SEL_MASK | - SD0_ITAPCHGWIN | SD0_ITAPDLYENA), 0x0); + SD0_ITAPCHGWIN | SD0_ITAPDLYENA), 0x0); } if (OTapDelay != 0U) { XSdps_Smc(InstancePtr, SD_OTAPDLY, SD0_OTAPDLY_SEL_MASK, OTapDelay); @@ -1287,7 +1383,7 @@ void XSdPs_ConfigTapDelay(XSdPs *InstancePtr) XSdps_Smc(InstancePtr, SD_ITAPDLY, SD1_ITAPCHGWIN, 0U); } else { XSdps_Smc(InstancePtr, SD_ITAPDLY, (SD1_ITAPDLY_SEL_MASK | - SD1_ITAPCHGWIN | SD1_ITAPDLYENA), 0x0); + SD1_ITAPCHGWIN | SD1_ITAPDLYENA), 0x0); } if (OTapDelay != 0U) { XSdps_Smc(InstancePtr, SD_OTAPDLY, SD1_OTAPDLY_SEL_MASK, OTapDelay); @@ -1331,9 +1427,9 @@ void XSdPs_ConfigTapDelay(XSdPs *InstancePtr) /*****************************************************************************/ /** * @brief -* This function is used to set voltage to 1.8V. +* Sets voltage to 1.8 V. * -* @param InstancePtr is a pointer to the instance to be worked on. +* @param InstancePtr Pointer to the instance to be worked on. * * @return * - XST_SUCCESS if successful @@ -1347,10 +1443,10 @@ s32 XSdPs_SetVoltage18(XSdPs *InstancePtr) /* Enabling 1.8V in controller */ CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, - XSDPS_HOST_CTRL2_OFFSET); + XSDPS_HOST_CTRL2_OFFSET); CtrlReg |= XSDPS_HC2_1V8_EN_MASK; XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_HOST_CTRL2_OFFSET, - CtrlReg); + CtrlReg); /* Wait minimum 5mSec */ (void)usleep(5000U); @@ -1367,9 +1463,9 @@ s32 XSdPs_SetVoltage18(XSdPs *InstancePtr) /*****************************************************************************/ /** * @brief -* This function is used configure the Power Level. +* Configures the Power Level. * -* @param InstancePtr is a pointer to the instance to be worked on. +* @param InstancePtr Pointer to the instance to be worked on. * * @return None * @@ -1397,9 +1493,9 @@ void XSdPs_ConfigPower(XSdPs *InstancePtr) /*****************************************************************************/ /** * @brief -* This function is used configure the DMA. +* Configures the DMA. * -* @param InstancePtr is a pointer to the instance to be worked on. +* @param InstancePtr Pointer to the instance to be worked on. * * @return None * @@ -1422,9 +1518,9 @@ void XSdPs_ConfigDma(XSdPs *InstancePtr) /*****************************************************************************/ /** * @brief -* This function is used configure the Interrupts. +* Configures the Interrupts. * -* @param InstancePtr is a pointer to the instance to be worked on. +* @param InstancePtr Pointer to the instance to be worked on. * * @return None * @@ -1433,30 +1529,30 @@ void XSdPs_ConfigInterrupt(XSdPs *InstancePtr) { /* Enable all interrupt status except card interrupt initially */ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, - XSDPS_NORM_INTR_STS_EN_OFFSET, - XSDPS_NORM_INTR_ALL_MASK & (~XSDPS_INTR_CARD_MASK)); + XSDPS_NORM_INTR_STS_EN_OFFSET, + XSDPS_NORM_INTR_ALL_MASK & (~XSDPS_INTR_CARD_MASK)); XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, - XSDPS_ERR_INTR_STS_EN_OFFSET, - XSDPS_ERROR_INTR_ALL_MASK); + XSDPS_ERR_INTR_STS_EN_OFFSET, + XSDPS_ERROR_INTR_ALL_MASK); /* Disable all interrupt signals by default. */ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, - XSDPS_NORM_INTR_SIG_EN_OFFSET, 0x0U); + XSDPS_NORM_INTR_SIG_EN_OFFSET, 0x0U); XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, - XSDPS_ERR_INTR_SIG_EN_OFFSET, 0x0U); + XSDPS_ERR_INTR_SIG_EN_OFFSET, 0x0U); } /*****************************************************************************/ /** -* This function does SD command generation. +* Generates SD command. * -* @param InstancePtr is a pointer to the instance to be worked on. -* @param Cmd is the command to be sent. -* @param Arg is the argument to be sent along with the command. +* @param InstancePtr Pointer to the instance to be worked on. +* @param Cmd Command to be sent. +* @param Arg Argument to be sent along with the command. * This could be address or any other information -* @param BlkCnt - Block count passed by the user. +* @param BlkCnt Block count passed by the user. * * @return * - XST_SUCCESS if initialization was successful @@ -1485,50 +1581,51 @@ s32 XSdPs_CmdTransfer(XSdPs *InstancePtr, u32 Cmd, u32 Arg, u32 BlkCnt) /* Polling for response for now */ Mask = XSDPS_INTR_ERR_MASK | XSDPS_INTR_CC_MASK; - if ((Cmd == CMD21) || (Cmd == CMD19)) + if ((Cmd == CMD21) || (Cmd == CMD19)) { Mask |= XSDPS_INTR_BRR_MASK; + } Status = Xil_WaitForEvents(InstancePtr->Config.BaseAddress + XSDPS_NORM_INTR_STS_OFFSET, - Mask, Mask, Timeout, &StatusReg); + Mask, Mask, Timeout, &StatusReg); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; - } - - if (((Cmd == CMD21) || (Cmd == CMD19)) && (StatusReg & XSDPS_INTR_BRR_MASK)) { - XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, - XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_BRR_MASK); } - if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0) { + + if (((Cmd == CMD21) || (Cmd == CMD19)) && (StatusReg & XSDPS_INTR_BRR_MASK) != 0U) { + XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, + XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_BRR_MASK); + } + if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) { Status = (s32)XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, - XSDPS_ERR_INTR_STS_OFFSET); + XSDPS_ERR_INTR_STS_OFFSET); if (((u32)Status & ~XSDPS_INTR_ERR_CT_MASK) == 0U) { Status = XSDPS_CT_ERROR; } /* Write to clear error bits */ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, - XSDPS_ERR_INTR_STS_OFFSET, - XSDPS_ERROR_INTR_ALL_MASK); + XSDPS_ERR_INTR_STS_OFFSET, + XSDPS_ERROR_INTR_ALL_MASK); goto RETURN_PATH; } /* Write to clear bit */ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, - XSDPS_NORM_INTR_STS_OFFSET, - XSDPS_INTR_CC_MASK); + XSDPS_NORM_INTR_STS_OFFSET, + XSDPS_INTR_CC_MASK); Status = XST_SUCCESS; RETURN_PATH: - return Status; + return Status; } /*****************************************************************************/ /** -* This function is used to check if the transfer is completed successfully. +* Checks if the transfer is completed successfully. * -* @param InstancePtr is a pointer to the instance to be worked on. +* @param InstancePtr Pointer to the instance to be worked on. * * @return None * @@ -1546,24 +1643,24 @@ s32 XSdps_CheckTransferDone(XSdPs *InstancePtr) */ Mask = XSDPS_INTR_ERR_MASK | XSDPS_INTR_TC_MASK; Status = Xil_WaitForEvents(InstancePtr->Config.BaseAddress + XSDPS_NORM_INTR_STS_OFFSET, - Mask, Mask, Timeout, &StatusReg); + Mask, Mask, Timeout, &StatusReg); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; } - if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0) { + if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) { /* Write to clear error bits */ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, - XSDPS_ERR_INTR_STS_OFFSET, - XSDPS_ERROR_INTR_ALL_MASK); + XSDPS_ERR_INTR_STS_OFFSET, + XSDPS_ERROR_INTR_ALL_MASK); Status = XST_FAILURE; goto RETURN_PATH; } /* Write to clear bit */ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, - XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK); + XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK); Status = XST_SUCCESS; @@ -1574,10 +1671,10 @@ RETURN_PATH: /*****************************************************************************/ /** * @brief -* This function is used to check if the CMD/DATA bus is idle or not. +* Checks if the CMD/DATA bus is idle or not. * -* @param InstancePtr is a pointer to the instance to be worked on. -* @param Value is to selct Cmd bus or Dat bus +* @param InstancePtr Pointer to the instance to be worked on. +* @param Value Value to be selected Cmd bus or Dat bus. * * @return None * @@ -1589,12 +1686,12 @@ s32 XSdPs_CheckBusIdle(XSdPs *InstancePtr, u32 Value) s32 Status; PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress, - XSDPS_PRES_STATE_OFFSET); + XSDPS_PRES_STATE_OFFSET); /* Check for Card Present */ if ((PresentStateReg & XSDPS_PSR_CARD_INSRT_MASK) != 0U) { /* Check for SD idle */ Status = Xil_WaitForEvent(InstancePtr->Config.BaseAddress + XSDPS_PRES_STATE_OFFSET, - Value, 0U, Timeout); + Value, 0U, Timeout); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH ; @@ -1610,17 +1707,19 @@ RETURN_PATH: /** * @brief * This function frames the Command register for a particular command. -* Note that this generates only the command register value i.e. -* the upper 16 bits of the transfer mode and command register. -* This value is already shifted to be upper 16 bits and can be directly -* OR'ed with transfer mode register value. * -* @param InstancePtr is a pointer to the instance to be worked on. -* @param Cmd is the Command to be sent. +* +* @param InstancePtr Pointer to the instance to be worked on. +* @param Cmd Command to be sent. * * @return Command register value complete with response type and * data, CRC and index related flags. * +* @note This generates only the command register value i.e. +* the upper 16 bits of the transfer mode and command register. +* This value is already shifted to be upper 16 bits and can be directly +* OR'ed with transfer mode register value. +* ******************************************************************************/ u32 XSdPs_FrameCmd(XSdPs *InstancePtr, u32 Cmd) { @@ -1628,102 +1727,76 @@ u32 XSdPs_FrameCmd(XSdPs *InstancePtr, u32 Cmd) RetVal = Cmd; - switch(Cmd) { - case CMD0: - RetVal |= RESP_NONE; - break; - case CMD1: - RetVal |= RESP_R3; - break; - case CMD2: - RetVal |= RESP_R2; - break; - case CMD3: - if (InstancePtr->CardType == XSDPS_CARD_SD) { - RetVal |= RESP_R6; - } else { - RetVal |= RESP_R1; - } - break; - case CMD4: - RetVal |= RESP_NONE; - break; - case CMD5: - RetVal |= RESP_R1B; - break; - case CMD6: - if (InstancePtr->CardType == XSDPS_CARD_SD) { - RetVal |= RESP_R1 | (u32)XSDPS_DAT_PRESENT_SEL_MASK; - } else { + switch (Cmd) { + case CMD0: + case CMD4: + RetVal |= RESP_NONE; + break; + case CMD1: + case ACMD41: + RetVal |= RESP_R3; + break; + case CMD2: + case CMD9: + RetVal |= RESP_R2; + break; + case CMD3: + if (InstancePtr->CardType == XSDPS_CARD_SD) { + RetVal |= RESP_R6; + } else { + RetVal |= RESP_R1; + } + break; + case CMD5: + case CMD38: RetVal |= RESP_R1B; - } - break; - case ACMD6: - RetVal |= RESP_R1; - break; - case CMD7: - RetVal |= RESP_R1; - break; - case CMD8: - if (InstancePtr->CardType == XSDPS_CARD_SD) { + break; + case CMD6: + if (InstancePtr->CardType == XSDPS_CARD_SD) { + RetVal |= RESP_R1 | (u32)XSDPS_DAT_PRESENT_SEL_MASK; + } else { + RetVal |= RESP_R1B; + } + break; + case ACMD6: + case CMD7: + case CMD10: + case CMD11: + case CMD12: + case CMD16: + case CMD32: + case CMD33: + case CMD35: + case CMD36: + case ACMD42: + case CMD52: + case CMD55: RetVal |= RESP_R1; - } else { + break; + case CMD8: + if (InstancePtr->CardType == XSDPS_CARD_SD) { + RetVal |= RESP_R1; + } else { + RetVal |= RESP_R1 | (u32)XSDPS_DAT_PRESENT_SEL_MASK; + } + break; + case ACMD13: + case CMD17: + case CMD18: + case CMD19: + case CMD21: + case CMD23: + case ACMD23: + case CMD24: + case CMD25: + case ACMD51: RetVal |= RESP_R1 | (u32)XSDPS_DAT_PRESENT_SEL_MASK; - } - break; - case CMD9: - RetVal |= RESP_R2; - break; - case CMD11: - case CMD10: - case CMD12: - RetVal |= RESP_R1; - break; - case ACMD13: - RetVal |= RESP_R1 | (u32)XSDPS_DAT_PRESENT_SEL_MASK; - break; - case CMD16: - RetVal |= RESP_R1; - break; - case CMD17: - case CMD18: - case CMD19: - case CMD21: - RetVal |= RESP_R1 | (u32)XSDPS_DAT_PRESENT_SEL_MASK; - break; - case CMD23: - case ACMD23: - case CMD24: - case CMD25: - RetVal |= RESP_R1 | (u32)XSDPS_DAT_PRESENT_SEL_MASK; - break; - case CMD32: - case CMD33: - case CMD35: - case CMD36: - RetVal |= RESP_R1; - break; - case CMD38: - RetVal |= RESP_R1B; - break; - case ACMD41: - RetVal |= RESP_R3; - break; - case ACMD42: - RetVal |= RESP_R1; - break; - case ACMD51: - RetVal |= RESP_R1 | (u32)XSDPS_DAT_PRESENT_SEL_MASK; - break; - case CMD52: - case CMD55: - RetVal |= RESP_R1; - break; - case CMD58: - break; - default : - RetVal |= Cmd; - break; + break; + case CMD58: + break; + default : + RetVal |= Cmd; + break; } return RetVal; @@ -1733,9 +1806,9 @@ u32 XSdPs_FrameCmd(XSdPs *InstancePtr, u32 Cmd) /*****************************************************************************/ /** * @brief -* This function selects the HS400 timing mode. +* Selects the HS400 timing mode. * -* @param InstancePtr is a pointer to the instance to be worked on. +* @param InstancePtr Pointer to the instance to be worked on. * * @return - XST_SUCCESS if successful * - XST_FAILURE if failure occurred. @@ -1773,7 +1846,11 @@ u32 XSdPs_Select_HS400(XSdPs *InstancePtr) goto RETURN_PATH; } - InstancePtr->OTapDelay = SD_OTAPDLYSEL_HS400; + if (InstancePtr->Config.OTapDly_DDR_Clk200 != 0U){ + InstancePtr->OTapDelay = InstancePtr->Config.OTapDly_DDR_Clk200; + } else { + InstancePtr->OTapDelay = SD_OTAPDLYSEL_HS400; + } Status = XSdPs_Change_ClkFreq(InstancePtr, InstancePtr->BusSpeed); if (Status != XST_SUCCESS) { Status = XST_FAILURE; @@ -1781,11 +1858,11 @@ u32 XSdPs_Select_HS400(XSdPs *InstancePtr) } StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, - XSDPS_HOST_CTRL2_OFFSET); + XSDPS_HOST_CTRL2_OFFSET); StatusReg &= (~(u32)XSDPS_HC2_UHS_MODE_MASK); StatusReg |= XSDPS_HC2_HS400_MASK; XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, - XSDPS_HOST_CTRL2_OFFSET, (u16)StatusReg); + XSDPS_HOST_CTRL2_OFFSET, (u16)StatusReg); RETURN_PATH: return Status; diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/sdps/src/xsdps_hw.h b/bsp_z7/ps7_cortexa9_0/libsrc/sdps/src/xsdps_hw.h index 7ee7774..9257158 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/sdps/src/xsdps_hw.h +++ b/bsp_z7/ps7_cortexa9_0/libsrc/sdps/src/xsdps_hw.h @@ -1,6 +1,6 @@ /****************************************************************************** * Copyright (C) 2013 - 2022 Xilinx, Inc. All rights reserved. -* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved. +* Copyright (c) 2022 - 2024 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -8,7 +8,7 @@ /** * * @file xsdps_hw.h -* @addtogroup sdps Overview +* @addtogroup sdps_api SDPS APIs * @{{ * * The xsdps_hw.h header file contains the identifiers and basic HW access driver @@ -45,6 +45,9 @@ * 4.0 sk 02/25/22 Add support for eMMC5.1. * sk 04/07/22 Fix typo in 'XSDPS_MMC_1_BIT_BUS_ARG' macro definition. * 4.1 sk 11/10/22 Add SD/eMMC Tap delay support for Versal Net. +* 4.2 ro 06/12/23 Added support for system device-tree flow. +* 4.3 ap 11/29/23 Add support for Sanitize feature. +* 4.3 ap 12/22/23 Add support to read custom HS400 tap delay value from design for eMMC. * * * @@ -63,8 +66,8 @@ extern "C" { #include "xil_types.h" #include "xil_assert.h" #include "xil_io.h" +#include "bspconfig.h" #include "xparameters.h" - /************************** Constant Definitions *****************************/ /** @name Register Map @@ -76,8 +79,8 @@ extern "C" { #define XSDPS_SDMA_SYS_ADDR_OFFSET 0x00U /**< SDMA System Address Register */ #define XSDPS_SDMA_SYS_ADDR_LO_OFFSET XSDPS_SDMA_SYS_ADDR_OFFSET - /**< SDMA System Address - Low Register */ +/**< SDMA System Address + Low Register */ #define XSDPS_ARGMT2_LO_OFFSET 0x00U /**< Argument2 Low Register */ #define XSDPS_SDMA_SYS_ADDR_HI_OFFSET 0x02U /**< SDMA System Address High Register */ @@ -87,7 +90,7 @@ extern "C" { #define XSDPS_BLK_CNT_OFFSET 0x06U /**< Block Count Register */ #define XSDPS_ARGMT_OFFSET 0x08U /**< Argument Register */ #define XSDPS_ARGMT1_LO_OFFSET XSDPS_ARGMT_OFFSET - /**< Argument1 Register */ +/**< Argument1 Register */ #define XSDPS_ARGMT1_HI_OFFSET 0x0AU /**< Argument1 Register */ #define XSDPS_XFER_MODE_OFFSET 0x0CU /**< Transfer Mode Register */ @@ -714,16 +717,16 @@ extern "C" { #define RESP_NONE (u32)XSDPS_CMD_RESP_NONE_MASK #define RESP_R1 (u32)XSDPS_CMD_RESP_L48_MASK | (u32)XSDPS_CMD_CRC_CHK_EN_MASK | \ - (u32)XSDPS_CMD_INX_CHK_EN_MASK + (u32)XSDPS_CMD_INX_CHK_EN_MASK #define RESP_R1B (u32)XSDPS_CMD_RESP_L48_BSY_CHK_MASK | \ - (u32)XSDPS_CMD_CRC_CHK_EN_MASK | (u32)XSDPS_CMD_INX_CHK_EN_MASK + (u32)XSDPS_CMD_CRC_CHK_EN_MASK | (u32)XSDPS_CMD_INX_CHK_EN_MASK #define RESP_R2 (u32)XSDPS_CMD_RESP_L136_MASK | (u32)XSDPS_CMD_CRC_CHK_EN_MASK #define RESP_R3 (u32)XSDPS_CMD_RESP_L48_MASK #define RESP_R6 (u32)XSDPS_CMD_RESP_L48_BSY_CHK_MASK | \ - (u32)XSDPS_CMD_CRC_CHK_EN_MASK | (u32)XSDPS_CMD_INX_CHK_EN_MASK + (u32)XSDPS_CMD_CRC_CHK_EN_MASK | (u32)XSDPS_CMD_INX_CHK_EN_MASK /** @} */ @@ -929,18 +932,24 @@ extern "C" { #define EXT_CSD_PART_CONFIG_ACC_BOOT1 (0x2U) #define EXT_CSD_PART_CONFIG_ACC_RPMB (0x3U) #define EXT_CSD_PART_CONFIG_ACC_GP0 (0x4U) +#define EXT_CSD_SANITIZE_START (0x1U) #define EXT_CSD_PART_CONFIG_BYTE (179U) +#define EXT_CSD_SANIT_CONFIG_BYTE (165U) #define XSDPS_MMC_PART_CFG_0_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24U) \ - | ((u32)EXT_CSD_PART_CONFIG_BYTE << 16U) \ - | ((u32)(0U) << 8U)) + | ((u32)EXT_CSD_PART_CONFIG_BYTE << 16U) \ + | ((u32)(0U) << 8U)) #define XSDPS_MMC_PART_CFG_1_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24U) \ - | ((u32)EXT_CSD_PART_CONFIG_BYTE << 16U) \ - | ((u32)EXT_CSD_PART_CONFIG_ACC_BOOT0 << 8U)) + | ((u32)EXT_CSD_PART_CONFIG_BYTE << 16U) \ + | ((u32)EXT_CSD_PART_CONFIG_ACC_BOOT0 << 8U)) #define XSDPS_MMC_PART_CFG_2_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24U) \ - | ((u32)EXT_CSD_PART_CONFIG_BYTE << 16U) \ - | ((u32)EXT_CSD_PART_CONFIG_ACC_BOOT1 << 8U)) + | ((u32)EXT_CSD_PART_CONFIG_BYTE << 16U) \ + | ((u32)EXT_CSD_PART_CONFIG_ACC_BOOT1 << 8U)) + +#define XSDPS_MMC_START_SANITIZE_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24U) \ + | ((u32)EXT_CSD_SANIT_CONFIG_BYTE << 16U) \ + | ((u32)EXT_CSD_SANITIZE_START << 8U)) #define EXT_CSD_PART_SUPPORT_PART_EN (0x1U) @@ -952,14 +961,14 @@ extern "C" { #define EXT_CSD_CARD_TYPE_52 (1U<<1) /* Card can run at 52MHz */ #define EXT_CSD_CARD_TYPE_MASK 0x3FU /* Mask out reserved bits */ #define EXT_CSD_CARD_TYPE_DDR_1_8V (1U<<2) /* Card can run at 52MHz */ - /* DDR mode @1.8V or 3V I/O */ +/* DDR mode @1.8V or 3V I/O */ #define EXT_CSD_CARD_TYPE_DDR_1_2V (1U<<3) /* Card can run at 52MHz */ - /* DDR mode @1.2V I/O */ +/* DDR mode @1.2V I/O */ #define EXT_CSD_CARD_TYPE_DDR_52 (EXT_CSD_CARD_TYPE_DDR_1_8V \ - | EXT_CSD_CARD_TYPE_DDR_1_2V) + | EXT_CSD_CARD_TYPE_DDR_1_2V) #define EXT_CSD_CARD_TYPE_SDR_1_8V (1U<<4) /* Card can run at 200MHz */ #define EXT_CSD_CARD_TYPE_SDR_1_2V (1U<<5) /* Card can run at 200MHz */ - /* SDR mode @1.2V I/O */ +/* SDR mode @1.2V I/O */ #define EXT_CSD_BUS_WIDTH_BYTE 183U #define EXT_CSD_BUS_WIDTH_1_BIT 0U /* Card is in 1 bit mode */ #define EXT_CSD_BUS_WIDTH_4_BIT 1U /* Card is in 4 bit mode */ @@ -992,44 +1001,44 @@ extern "C" { * SD/MMC Arguments for Bus Speed and Bus Width. */ #define XSDPS_MMC_DEF_SPEED_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \ - | ((u32)EXT_CSD_HS_TIMING_BYTE << 16) \ - | ((u32)EXT_CSD_HS_TIMING_DEF << 8)) + | ((u32)EXT_CSD_HS_TIMING_BYTE << 16) \ + | ((u32)EXT_CSD_HS_TIMING_DEF << 8)) #define XSDPS_MMC_HIGH_SPEED_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \ - | ((u32)EXT_CSD_HS_TIMING_BYTE << 16) \ - | ((u32)EXT_CSD_HS_TIMING_HIGH << 8)) + | ((u32)EXT_CSD_HS_TIMING_BYTE << 16) \ + | ((u32)EXT_CSD_HS_TIMING_HIGH << 8)) #define XSDPS_MMC_HS200_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \ - | ((u32)EXT_CSD_HS_TIMING_BYTE << 16) \ - | ((u32)EXT_CSD_HS_TIMING_HS200 << 8)) + | ((u32)EXT_CSD_HS_TIMING_BYTE << 16) \ + | ((u32)EXT_CSD_HS_TIMING_HS200 << 8)) #define XSDPS_MMC_HS400_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \ - | ((u32)EXT_CSD_HS_TIMING_BYTE << 16) \ - | ((u32)EXT_CSD_HS_TIMING_HS400 << 8)) + | ((u32)EXT_CSD_HS_TIMING_BYTE << 16) \ + | ((u32)EXT_CSD_HS_TIMING_HS400 << 8)) #define XSDPS_MMC_1_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \ - | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \ - | ((u32)EXT_CSD_BUS_WIDTH_1_BIT << 8)) + | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \ + | ((u32)EXT_CSD_BUS_WIDTH_1_BIT << 8)) #define XSDPS_MMC_4_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \ - | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \ - | ((u32)EXT_CSD_BUS_WIDTH_4_BIT << 8)) + | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \ + | ((u32)EXT_CSD_BUS_WIDTH_4_BIT << 8)) #define XSDPS_MMC_8_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \ - | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \ - | ((u32)EXT_CSD_BUS_WIDTH_8_BIT << 8)) + | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \ + | ((u32)EXT_CSD_BUS_WIDTH_8_BIT << 8)) #define XSDPS_MMC_DDR_4_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \ - | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \ - | ((u32)EXT_CSD_BUS_WIDTH_DDR_4_BIT << 8)) + | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \ + | ((u32)EXT_CSD_BUS_WIDTH_DDR_4_BIT << 8)) #define XSDPS_MMC_DDR_8_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \ - | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \ - | ((u32)EXT_CSD_BUS_WIDTH_DDR_8_BIT << 8)) + | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \ + | ((u32)EXT_CSD_BUS_WIDTH_DDR_8_BIT << 8)) #define XSDPS_MMC_RST_FUN_EN_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \ - | ((u32)EXT_CSD_RST_N_FUN_BYTE << 16) \ - | ((u32)EXT_CSD_RST_N_FUN_PERM_EN << 8)) + | ((u32)EXT_CSD_RST_N_FUN_BYTE << 16) \ + | ((u32)EXT_CSD_RST_N_FUN_PERM_EN << 8)) #define XSDPS_MMC_DELAY_FOR_SWITCH 1000U @@ -1196,6 +1205,8 @@ extern "C" { #define SD_ITAPCHGWIN 0x00000200U #define SD_ITAPDLYENA 0x00000100U #define SD_OTAPDLYENA 0x00000040U +#define SD_OTAPDLYSEL_SD104_B0 0x00000002U +#define SD_OTAPDLYSEL_SD104_B2 0x00000002U #define SD_OTAPDLYSEL_HS200_B0 0x00000007U #define SD_OTAPDLYSEL_HS200_B2 0x00000007U #define SD_OTAPDLYSEL_HS400 0x00000004U @@ -1224,6 +1235,8 @@ extern "C" { #define SD_ITAPCHGWIN 0x00000200U #define SD_ITAPDLYENA 0x00000100U #define SD_OTAPDLYENA 0x00000040U +#define SD_OTAPDLYSEL_SD104_B0 0x00000002U +#define SD_OTAPDLYSEL_SD104_B2 0x00000002U #define SD_OTAPDLYSEL_HS200_B0 0x00000002U #define SD_OTAPDLYSEL_HS200_B2 0x00000002U #define SD_ITAPDLYSEL_SD50 0x0000000EU @@ -1255,6 +1268,8 @@ extern "C" { #define SD1_ITAPCHGWIN 0x02000000U #define SD1_ITAPDLYENA 0x01000000U #define SD1_OTAPDLYENA 0x00400000U +#define SD_OTAPDLYSEL_SD104_B0 0x00000003U +#define SD_OTAPDLYSEL_SD104_B2 0x00000002U #define SD_OTAPDLYSEL_HS200_B0 0x00000003U #define SD_OTAPDLYSEL_HS200_B2 0x00000002U #define SD_ITAPDLYSEL_SD50 0x00000014U @@ -1273,7 +1288,7 @@ extern "C" { #endif /** @} */ -#ifdef __MICROBLAZE__ +#if defined (__MICROBLAZE__) || defined (__riscv) #define XPS_SYS_CTRL_BASEADDR 0xFF180000U /**< System controller Baseaddress */ #endif @@ -1294,16 +1309,16 @@ extern "C" { /****************************************************************************/ /** -* Read a register. +* Reads a register. * -* @param InstancePtr is the pointer to the sdps instance. -* @param RegOffset contains the offset from the 1st register of the +* @param InstancePtr Pointer to the sdps instance. +* @param RegOffset Contains the offset from the 1st register of the * device to the target register. * * @return The value read from the register. * * @note C-Style signature: -* u32 XSdPs_ReadReg(XSdPs *InstancePtr. s32 RegOffset) +* u32 XSdPs_ReadReg(XSdPs *InstancePtr. s32 RegOffset) * ******************************************************************************/ #define XSdPs_ReadReg64(InstancePtr, RegOffset) \ @@ -1311,36 +1326,36 @@ extern "C" { /***************************************************************************/ /** -* Write to a register. +* Writes to a register. * -* @param InstancePtr is the pointer to the sdps instance. -* @param RegOffset contains the offset from the 1st register of the +* @param InstancePtr Pointer to the sdps instance. +* @param RegOffset Contains the offset from the 1st register of the * device to target register. -* @param RegisterValue is the value to be written to the register. +* @param RegisterValue Value to be written to the register. * * @return None. * * @note C-Style signature: -* void XSdPs_WriteReg(XSdPs *InstancePtr, s32 RegOffset, -* u64 RegisterValue) +* void XSdPs_WriteReg(XSdPs *InstancePtr, s32 RegOffset, +* u64 RegisterValue) * ******************************************************************************/ #define XSdPs_WriteReg64(InstancePtr, RegOffset, RegisterValue) \ XSdPs_Out64((InstancePtr->Config.BaseAddress) + (RegOffset), \ - (RegisterValue)) + (RegisterValue)) /****************************************************************************/ /** -* Read a register. +* Reads a register. * -* @param BaseAddress contains the base address of the device. -* @param RegOffset contains the offset from the 1st register of the +* @param BaseAddress Contains the base address of the device. +* @param RegOffset Contains the offset from the 1st register of the * device to the target register. * * @return The value read from the register. * * @note C-Style signature: -* u32 XSdPs_ReadReg(u32 BaseAddress. int RegOffset) +* u32 XSdPs_ReadReg(UINTPTR BaseAddress. int RegOffset) * ******************************************************************************/ #define XSdPs_ReadReg(BaseAddress, RegOffset) \ @@ -1348,18 +1363,18 @@ extern "C" { /***************************************************************************/ /** -* Write to a register. +* Writes to a register. * -* @param BaseAddress contains the base address of the device. -* @param RegOffset contains the offset from the 1st register of the +* @param BaseAddress Contains the base address of the device. +* @param RegOffset Contains the offset from the 1st register of the * device to target register. -* @param RegisterValue is the value to be written to the register. +* @param RegisterValue Value to be written to the register. * * @return None. * * @note C-Style signature: -* void XSdPs_WriteReg(u32 BaseAddress, int RegOffset, -* u32 RegisterValue) +* void XSdPs_WriteReg(UINTPTR BaseAddress, int RegOffset, +* u32 RegisterValue) * ******************************************************************************/ #define XSdPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \ @@ -1367,25 +1382,25 @@ extern "C" { /****************************************************************************/ /** -* Read a register. +* Reads a register. * -* @param BaseAddress contains the base address of the device. -* @param RegOffset contains the offset from the 1st register of the +* @param BaseAddress Contains the base address of the device. +* @param RegOffset Contains the offset from the 1st register of the * device to the target register. * * @return The value read from the register. * * @note C-Style signature: -* u16 XSdPs_ReadReg(u32 BaseAddress. int RegOffset) +* u16 XSdPs_ReadReg(UINTPTR BaseAddress. int RegOffset) * ******************************************************************************/ -static INLINE u16 XSdPs_ReadReg16(u32 BaseAddress, u8 RegOffset) +static INLINE u16 XSdPs_ReadReg16(UINTPTR BaseAddress, u8 RegOffset) { -#if defined (__MICROBLAZE__) +#if defined (__MICROBLAZE__) || defined (__riscv) u32 Reg; BaseAddress += RegOffset & 0xFC; Reg = XSdPs_In32(BaseAddress); - Reg >>= ((RegOffset & 0x3)*8); + Reg >>= ((RegOffset & 0x3) * 8); return (u16)Reg; #else return XSdPs_In16((UINTPTR)(BaseAddress) + (UINTPTR)(RegOffset)); @@ -1394,29 +1409,29 @@ static INLINE u16 XSdPs_ReadReg16(u32 BaseAddress, u8 RegOffset) /***************************************************************************/ /** -* Write to a register. +* Writes to a register. * -* @param BaseAddress contains the base address of the device. -* @param RegOffset contains the offset from the 1st register of the +* @param BaseAddress Contains the base address of the device. +* @param RegOffset Contains the offset from the 1st register of the * device to target register. -* @param RegisterValue is the value to be written to the register. +* @param RegisterValue Value to be written to the register. * * @return None. * * @note C-Style signature: -* void XSdPs_WriteReg(u32 BaseAddress, int RegOffset, -* u16 RegisterValue) +* void XSdPs_WriteReg(UINTPTR BaseAddress, int RegOffset, +* u16 RegisterValue) * ******************************************************************************/ -static INLINE void XSdPs_WriteReg16(u32 BaseAddress, u8 RegOffset, u16 RegisterValue) +static INLINE void XSdPs_WriteReg16(UINTPTR BaseAddress, u8 RegOffset, u16 RegisterValue) { -#if defined (__MICROBLAZE__) +#if defined (__MICROBLAZE__) || defined (__riscv) u32 Reg; BaseAddress += RegOffset & 0xFC; Reg = XSdPs_In32(BaseAddress); - Reg &= ~(0xFFFFU<<((RegOffset & 0x3)*8)); - Reg |= RegisterValue <<((RegOffset & 0x3)*8); + Reg &= ~(0xFFFFU << ((RegOffset & 0x3) * 8)); + Reg |= RegisterValue << ((RegOffset & 0x3) * 8); XSdPs_Out32(BaseAddress, Reg); #else XSdPs_Out16((UINTPTR)(BaseAddress) + (UINTPTR)(RegOffset), (RegisterValue)); @@ -1425,25 +1440,25 @@ static INLINE void XSdPs_WriteReg16(u32 BaseAddress, u8 RegOffset, u16 RegisterV /****************************************************************************/ /** -* Read a register. +* Reads a register. * -* @param BaseAddress contains the base address of the device. -* @param RegOffset contains the offset from the 1st register of the +* @param BaseAddress Contains the base address of the device. +* @param RegOffset Contains the offset from the 1st register of the * device to the target register. * * @return The value read from the register. * * @note C-Style signature: -* u8 XSdPs_ReadReg(u32 BaseAddress. int RegOffset) +* u8 XSdPs_ReadReg(UINTPTR BaseAddress. int RegOffset) * ******************************************************************************/ -static INLINE u8 XSdPs_ReadReg8(u32 BaseAddress, u8 RegOffset) +static INLINE u8 XSdPs_ReadReg8(UINTPTR BaseAddress, u8 RegOffset) { -#if defined (__MICROBLAZE__) +#if defined (__MICROBLAZE__) || defined (__riscv) u32 Reg; BaseAddress += RegOffset & 0xFC; Reg = XSdPs_In32(BaseAddress); - Reg >>= ((RegOffset & 0x3)*8); + Reg >>= ((RegOffset & 0x3) * 8); return (u8)Reg; #else return XSdPs_In8((UINTPTR)(BaseAddress) + (UINTPTR)(RegOffset)); @@ -1451,28 +1466,28 @@ static INLINE u8 XSdPs_ReadReg8(u32 BaseAddress, u8 RegOffset) } /***************************************************************************/ /** -* Write to a register. +* Writes to a register. * -* @param BaseAddress contains the base address of the device. -* @param RegOffset contains the offset from the 1st register of the +* @param BaseAddress Contains the base address of the device. +* @param RegOffset Contains the offset from the 1st register of the * device to target register. -* @param RegisterValue is the value to be written to the register. +* @param RegisterValue Value to be written to the register. * * @return None. * * @note C-Style signature: -* void XSdPs_WriteReg(u32 BaseAddress, int RegOffset, -* u8 RegisterValue) +* void XSdPs_WriteReg(UINTPTR BaseAddress, int RegOffset, +* u8 RegisterValue) * ******************************************************************************/ -static INLINE void XSdPs_WriteReg8(u32 BaseAddress, u8 RegOffset, u8 RegisterValue) +static INLINE void XSdPs_WriteReg8(UINTPTR BaseAddress, u8 RegOffset, u8 RegisterValue) { -#if defined (__MICROBLAZE__) +#if defined (__MICROBLAZE__) || defined (__riscv) u32 Reg; BaseAddress += RegOffset & 0xFC; Reg = XSdPs_In32(BaseAddress); - Reg &= ~(0xFFU<<((RegOffset & 0x3)*8)); - Reg |= RegisterValue <<((RegOffset & 0x3)*8); + Reg &= ~(0xFFU << ((RegOffset & 0x3) * 8)); + Reg |= RegisterValue << ((RegOffset & 0x3) * 8); XSdPs_Out32(BaseAddress, Reg); #else XSdPs_Out8((UINTPTR)(BaseAddress) + (UINTPTR)(RegOffset), (RegisterValue)); @@ -1480,19 +1495,19 @@ static INLINE void XSdPs_WriteReg8(u32 BaseAddress, u8 RegOffset, u8 RegisterVal } /***************************************************************************/ /** -* Macro to get present status register +* Macro to get present status register. * -* @param BaseAddress contains the base address of the device. +* @param BaseAddress Contains the base address of the device. * * @return None. * * @note C-Style signature: -* void XSdPs_WriteReg(u32 BaseAddress, int RegOffset, -* u8 RegisterValue) +* void XSdPs_WriteReg(UINTPTR BaseAddress, int RegOffset, +* u8 RegisterValue) * ******************************************************************************/ #define XSdPs_GetPresentStatusReg(BaseAddress) \ - XSdPs_In32((BaseAddress) + (XSDPS_PRES_STATE_OFFSET)) + XSdPs_In32((BaseAddress) + (XSDPS_PRES_STATE_OFFSET)) /************************** Function Prototypes ******************************/ diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/sdps/src/xsdps_options.c b/bsp_z7/ps7_cortexa9_0/libsrc/sdps/src/xsdps_options.c index fa9a421..e7e166a 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/sdps/src/xsdps_options.c +++ b/bsp_z7/ps7_cortexa9_0/libsrc/sdps/src/xsdps_options.c @@ -1,6 +1,6 @@ /****************************************************************************** * Copyright (C) 2013 - 2022 Xilinx, Inc. All rights reserved. -* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved. +* Copyright (c) 2022 - 2024 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -8,7 +8,7 @@ /** * * @file xsdps_options.c -* @addtogroup sdps Overview +* @addtogroup sdps_api SDPS APIs * @{ * * The xsdps_options.c file ontains APIs for changing the various options in host and card. @@ -82,11 +82,11 @@ /** * * @brief -* API to change clock freq to given value. +* API to change clock frequency to a given value. * * -* @param InstancePtr is a pointer to the XSdPs instance. -* @param SelFreq - Clock frequency in Hz. +* @param InstancePtr Pointer to the XSdPs instance. +* @param SelFreq Clock frequency in Hz. * * @return None * @@ -148,10 +148,10 @@ s32 XSdPs_Change_ClkFreq(XSdPs *InstancePtr, u32 SelFreq) /*****************************************************************************/ /** * @brief -* Update Block size for read/write operations. +* Updates Block size for read/write operations. * -* @param InstancePtr is a pointer to the instance to be worked on. -* @param BlkSize - Block size passed by the user. +* @param InstancePtr Pointer to the instance to be worked on. +* @param BlkSize Block size passed by the user. * * @return None * @@ -193,11 +193,11 @@ RETURN_PATH: /** * * @brief -* API to get bus width support by card. +* Gets bus width support by card. * * -* @param InstancePtr is a pointer to the XSdPs instance. -* @param ReadBuff - buffer to store SCR register returned by card. +* @param InstancePtr Pointer to the XSdPs instance. +* @param ReadBuff Buffer to store SCR register returned by card. * * @return * - XST_SUCCESS if successful. @@ -262,16 +262,15 @@ s32 XSdPs_Get_BusWidth(XSdPs *InstancePtr, u8 *ReadBuff) /** * * @brief -* API to set bus width to 4-bit in card and host +* Sets bus width to 4-bit in card and host. * * -* @param InstancePtr is a pointer to the XSdPs instance. +* @param InstancePtr Pointer to the XSdPs instance. * * @return * - XST_SUCCESS if successful. * - XST_FAILURE if fail. * -* @note None. * ******************************************************************************/ s32 XSdPs_Change_BusWidth(XSdPs *InstancePtr) @@ -366,11 +365,11 @@ s32 XSdPs_Change_BusWidth(XSdPs *InstancePtr) /** * * @brief -* API to get bus speed supported by card. +* Gets bus speed supported by card. * * -* @param InstancePtr is a pointer to the XSdPs instance. -* @param ReadBuff - buffer to store function group support data +* @param InstancePtr Pointer to the XSdPs instance. +* @param ReadBuff Buffer to store function group support data * returned by card. * * @return @@ -431,17 +430,16 @@ s32 XSdPs_Get_BusSpeed(XSdPs *InstancePtr, u8 *ReadBuff) /** * * @brief -* API to get SD card status information. +* Gets SD card status information. * * -* @param InstancePtr is a pointer to the XSdPs instance. -* @param SdStatReg - buffer to store status data returned by card. +* @param InstancePtr Pointer to the XSdPs instance. +* @param SdStatReg Buffer to store status data returned by card. * * @return * - XST_SUCCESS if successful. * - XST_FAILURE if fail. * -* @note None. * ******************************************************************************/ s32 XSdPs_Get_Status(XSdPs *InstancePtr, u8 *SdStatReg) @@ -494,16 +492,15 @@ s32 XSdPs_Get_Status(XSdPs *InstancePtr, u8 *SdStatReg) /** * * @brief -* API to set high speed in card and host. Changes clock in host accordingly. +* Sets high speed in card and host. Changes clock in host accordingly. * * -* @param InstancePtr is a pointer to the XSdPs instance. +* @param InstancePtr Pointer to the XSdPs instance. * * @return * - XST_SUCCESS if successful. * - XST_FAILURE if fail. * -* @note None. * ******************************************************************************/ s32 XSdPs_Change_BusSpeed(XSdPs *InstancePtr) @@ -575,17 +572,16 @@ s32 XSdPs_Change_BusSpeed(XSdPs *InstancePtr) /** * * @brief -* API to get EXT_CSD register of eMMC. +* Gets EXT_CSD register of eMMC. * * -* @param InstancePtr is a pointer to the XSdPs instance. -* @param ReadBuff - buffer to store EXT_CSD +* @param InstancePtr Pointer to the XSdPs instance. +* @param ReadBuff Buffer to store EXT_CSD * * @return * - XST_SUCCESS if successful. * - XST_FAILURE if fail. * -* @note None. * ******************************************************************************/ s32 XSdPs_Get_Mmc_ExtCsd(XSdPs *InstancePtr, u8 *ReadBuff) @@ -638,17 +634,16 @@ s32 XSdPs_Get_Mmc_ExtCsd(XSdPs *InstancePtr, u8 *ReadBuff) /** * * @brief -* API to write EXT_CSD register of eMMC. +* Writes EXT_CSD register of eMMC. * * -* @param InstancePtr is a pointer to the XSdPs instance. -* @param Arg is the argument to be sent along with the command +* @param InstancePtr Pointer to the XSdPs instance. +* @param Arg Argument to be sent along with the command. * * @return * - XST_SUCCESS if successful. * - XST_FAILURE if fail. * -* @note None. * ******************************************************************************/ s32 XSdPs_Set_Mmc_ExtCsd(XSdPs *InstancePtr, u32 Arg) @@ -682,16 +677,15 @@ s32 XSdPs_Set_Mmc_ExtCsd(XSdPs *InstancePtr, u32 Arg) /** * * @brief -* API to send pullup command to card before using DAT line 3(using 4-bit bus) +* Sends pullup command to card before using DAT line 3(using 4-bit bus). * * -* @param InstancePtr is a pointer to the XSdPs instance. +* @param InstancePtr Pointer to the XSdPs instance. * * @return * - XST_SUCCESS if successful. * - XST_FAILURE if fail. * -* @note None. * ******************************************************************************/ s32 XSdPs_Pullup(XSdPs *InstancePtr) @@ -728,14 +722,13 @@ s32 XSdPs_Pullup(XSdPs *InstancePtr) * Selects card and sets default block size * * -* @param InstancePtr is a pointer to the XSdPs instance. +* @param InstancePtr Pointer to the XSdPs instance. * * @return * - XST_SUCCESS if successful. * - XST_FAILURE if fail. * - XSDPS_CT_ERROR if Command Transfer fail. * -* @note None. * ******************************************************************************/ s32 XSdPs_Select_Card (XSdPs *InstancePtr) @@ -755,13 +748,13 @@ s32 XSdPs_Select_Card (XSdPs *InstancePtr) /*****************************************************************************/ /** * @brief -* This function performs SD read in polled mode. +* Performs SD read in polled mode. * -* @param InstancePtr is a pointer to the instance to be worked on. -* @param Arg is the address passed by the user that is to be sent as +* @param InstancePtr Pointer to the instance to be worked on. +* @param Arg Address passed by the user that is to be sent as * argument along with the command. -* @param BlkCnt - Block count passed by the user. -* @param Buff - Pointer to the data buffer for a DMA transfer. +* @param BlkCnt Block count passed by the user. +* @param Buff Pointer to the data buffer for a DMA transfer. * * @return * - XST_SUCCESS if Transfer initialization was successful @@ -803,13 +796,13 @@ RETURN_PATH: /*****************************************************************************/ /** * @brief -* This function start SD write transfer. +* Starts SD write transfer. * -* @param InstancePtr is a pointer to the instance to be worked on. -* @param Arg is the address passed by the user that is to be sent as +* @param InstancePtr Pointer to the instance to be worked on. +* @param Arg Address passed by the user that is to be sent as * argument along with the command. -* @param BlkCnt - Block count passed by the user. -* @param Buff - Pointer to the data buffer for a DMA transfer. +* @param BlkCnt Block count passed by the user. +* @param Buff Pointer to the data buffer for a DMA transfer. * * @return * - XST_SUCCESS if Transfer initialization was successful @@ -851,9 +844,9 @@ RETURN_PATH: /*****************************************************************************/ /** * @brief -* This function is used to check if the transfer is completed successfully. +* Checks if the transfer is completed successfully. * -* @param InstancePtr is a pointer to the instance to be worked on. +* @param InstancePtr Pointer to the instance to be worked on. * * @return * - XST_SUCCESS if transfer was successful @@ -876,9 +869,9 @@ s32 XSdPs_CheckReadTransfer(XSdPs *InstancePtr) /*****************************************************************************/ /** * @brief -* This function is used to check for the write transfer completed. +* Checks for the write transfer completed. * -* @param InstancePtr is a pointer to the instance to be worked on. +* @param InstancePtr Pointer to the instance to be worked on. * * @return * - XST_SUCCESS if transfer was successful diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/sdps/src/xsdps_sinit.c b/bsp_z7/ps7_cortexa9_0/libsrc/sdps/src/xsdps_sinit.c index 22a4b7f..50a4915 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/sdps/src/xsdps_sinit.c +++ b/bsp_z7/ps7_cortexa9_0/libsrc/sdps/src/xsdps_sinit.c @@ -1,6 +1,6 @@ /****************************************************************************** * Copyright (C) 2013 - 2022 Xilinx, Inc. All rights reserved. -* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved. +* Copyright (c) 2022 - 2024 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -8,11 +8,11 @@ /** * * @file xsdps_sinit.c -* @addtogroup sdps Overview +* @addtogroup sdps_api SDPS APIs * @{ * -* The implementation of the XSdPs component's static initialization -* functionality. +* The file contains the implementation of the static initialization +* functionality of the XSdPs component. * * 
 * MODIFICATION HISTORY:
@@ -22,6 +22,7 @@
 * 1.00a hk/sg  10/17/13 Initial release
 *       kvn    07/15/15 Modified the code according to MISRAC-2012.
 * 3.7   aru    03/12/19 Modified the code according to MISRAC-2012.
+* 4.2   ro     06/12/23 Added support for system device-tree flow.
 *
 *
* @@ -40,10 +41,6 @@ /************************** Function Prototypes ******************************/ /************************** Variable Definitions *****************************/ -/** - * XSdPs Configuration Table - */ -extern XSdPs_Config XSdPs_ConfigTable[XPAR_XSDPS_NUM_INSTANCES]; /*****************************************************************************/ /** @@ -52,7 +49,7 @@ extern XSdPs_Config XSdPs_ConfigTable[XPAR_XSDPS_NUM_INSTANCES]; * Looks up the device configuration based on the unique device ID. A table * contains the configuration info for each device in the system. * -* @param DeviceId contains the ID of the device to look up the +* @param DeviceId Contains the ID of the device to look up the * configuration for. * * @return @@ -60,9 +57,9 @@ extern XSdPs_Config XSdPs_ConfigTable[XPAR_XSDPS_NUM_INSTANCES]; * A pointer to the configuration found or NULL if the specified device ID was * not found. See xsdps.h for the definition of XSdPs_Config. * -* @note None. * ******************************************************************************/ +#ifndef SDT XSdPs_Config *XSdPs_LookupConfig(u16 DeviceId) { XSdPs_Config *CfgPtr = NULL; @@ -76,4 +73,21 @@ XSdPs_Config *XSdPs_LookupConfig(u16 DeviceId) } return (XSdPs_Config *)CfgPtr; } +#else +XSdPs_Config *XSdPs_LookupConfig(u32 BaseAddress) +{ + XSdPs_Config *CfgPtr = NULL; + u32 Index; + + for (Index = 0U; XSdPs_ConfigTable[Index].Name != NULL; Index++) { + if ((XSdPs_ConfigTable[Index].BaseAddress == BaseAddress) || + !BaseAddress) { + CfgPtr = &XSdPs_ConfigTable[Index]; + break; + } + } + return (XSdPs_Config *)CfgPtr; +} +#endif + /** @} */ diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/boot.S b/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/boot.S index 3ee6914..5305e14 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/boot.S +++ b/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/boot.S @@ -1,5 +1,6 @@ /****************************************************************************** * Copyright (c) 2010 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ /*****************************************************************************/ @@ -64,6 +65,8 @@ * 742230 and 743622. These do not apply to * Cortex-A9 revision r3p0 being used in Zynq * platforms. +* 9.0 mus 07/27/23 Removed dependency on XPAR_CPU_ID, updated logic to use +* CPU affinity register to read CPU ID. * * * @@ -73,7 +76,10 @@ * ******************************************************************************/ +#include "bspconfig.h" +#ifndef SDT #include "xparameters.h" +#endif #include "xil_errata.h" .globl MMUTable @@ -146,16 +152,12 @@ _prestart: _boot: - -#if XPAR_CPU_ID==0 /* only allow cpu0 through */ mrc p15,0,r1,c0,c0,5 and r1, r1, #0xf cmp r1, #0 beq CheckEFUSE - EndlessLoop0: - wfe - b EndlessLoop0 + b OKToRun CheckEFUSE: ldr r0,=EFUSEStaus @@ -177,24 +179,6 @@ CheckEFUSE: ldr r1,=SLCRlockKey /* set lock key */ str r1, [r0] /* lock SLCR */ -#elif XPAR_CPU_ID==1 - /* only allow cpu1 through */ - mrc p15,0,r1,c0,c0,5 - and r1, r1, #0xf - cmp r1, #1 - beq CheckEFUSE1 - b EndlessLoop1 - -CheckEFUSE1: - ldr r0,=EFUSEStaus - ldr r1,[r0] /* Read eFuse setting */ - ands r1,r1,#0x80 /* Check whether device is having single core */ - beq OKToRun - EndlessLoop1: - wfe - b EndlessLoop1 -#endif - OKToRun: mrc p15, 0, r0, c0, c0, 0 /* Get the revision */ and r5, r0, #0x00f00000 @@ -204,7 +188,6 @@ OKToRun: /* set VBAR to the _vector_table address in linker script */ ldr r0, =vector_base mcr p15, 0, r0, c12, c0, 0 - MRC p15, 0, r1, c12, c0, 0 /*invalidate scu*/ #if USE_AMP!=1 diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/outbyte.c b/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/outbyte.c index 1080862..db60e6d 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/outbyte.c +++ b/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/outbyte.c @@ -8,12 +8,12 @@ #ifdef __cplusplus extern "C" { #endif -void outbyte(uint8_t c); +void outbyte(char c); #ifdef __cplusplus } #endif -void outbyte(uint8_t c) { +void outbyte(char c) { XUartPs_SendByte(STDOUT_BASEADDRESS, c); } diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/pm_api_version.h b/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/pm_api_version.h new file mode 100644 index 0000000..5498048 --- /dev/null +++ b/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/pm_api_version.h @@ -0,0 +1,268 @@ +/****************************************************************************** +* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** + * @file pm_api_version.h + * + * @addtogroup xpm_versal_apis XilPM APIs + *****************************************************************************/ + + +#ifndef PM_API_VERSION_H_ +#define PM_API_VERSION_H_ + +/*****************************************************************************/ +/** + * @section EEMI_API_DETAIL XilPM EEMI API Version Detail + * + * This section provides details of EEMI API version and it's history for PM APIs of XilPM library. + * + * | NAME | ID | Platform | Version| Description | + * |----------------------------|-------|---------------|:------:|---------------------------------------------------------------------------| + * | PM_GET_API_VERSION | 0x1 | Both | 1 | The API is used to request the version number of the API | + * | PM_SET_CONFIGURATION | 0x2 | ZynqMP | 1 | The API is used to configure the power management framework | + * | ^ | ^ | ^ | ^ | Note: Deprecated in Versal but supported in ZynqMP | + * | PM_GET_NODE_STATUS | 0x3 | Both | 1 | The API is used to obtain information about current status of a device | + * | PM_GET_OP_CHARACTERISTIC | 0x4 | Both | 2 | V1 - The API is used to get operating characteristics of a device | + * | ^ | ^ | ^ | ^ | V2 - Added support of bitmask functionality, user can check the supported\n "type" first before performing the actual functionality | + * | PM_REGISTER_NOTIFIER | 0x5 | Both | 2 | V1 - The API is used to register a subsystem to be notified about the\n device event | + * | ^ | ^ | ^ | ^ | V2 - Added support of event management functionality | + * | ^ | ^ | ^ | ^ | Note: V2 is supported in Versal but ZynqMP supports only V1 | + * | PM_REQUEST_SUSPEND | 0x6 | Both | 1 | The API is used to send suspend request to another subsystem | + * | PM_SELF_SUSPEND | 0x7 | Both | 3 | V1 - The API is used to suspend a child subsystem | + * | ^ | ^ | ^ | ^ | V2 - Added support of cpu idle functionality during force powerdown | + * | ^ | ^ | ^ | ^ | V3 - Added support of CPU off state | + * | ^ | ^ | ^ | ^ | Note: V3 is supported in Versal and Versal NET but ZynqMP supports only V1| + * | PM_FORCE_POWERDOWN | 0x8 | Both | 2 | V1 - The API is used to Powerdown other processor or node | + * | ^ | ^ | ^ | ^ | V2 - Added support of cpu idle functionality during force powerdown | + * | ^ | ^ | ^ | ^ | Note: V2 is supported in Versal but ZynqMP supports only V1 | + * | PM_ABORT_SUSPEND | 0x9 | Both | 1 | The API is used by a subsystem to abort suspend of a child subsystem | + * | PM_REQUEST_WAKEUP | 0xA | Both | 1 | The API is used to start-up and wake-up a child subsystem | + * | PM_SET_WAKEUP_SOURCE | 0xB | Both | 1 | The API is used to set wakeup source | + * | PM_SYSTEM_SHUTDOWN | 0xC | Both | 1 | The API is used to shutdown or restart the system | + * | PM_REQUEST_NODE | 0xD | Both | 2 | V1 - The API is used to request the usage of a device | + * | ^ | ^ | ^ | ^ | V2 - Added support of security policy handling during request device | + * | ^ | ^ | ^ | ^ | Note: V2 is supported in Versal but ZynqMP supports only V1 | + * | PM_RELEASE_NODE | 0xE | Both | 2 | V1 - The API is used to release the usage of a device | + * | ^ | ^ | ^ | ^ | V2 - Added support of security policy handling during request device | + * | ^ | ^ | ^ | ^ | Note: V2 is supported in Versal but ZynqMP supports only V1 | + * | PM_SET_REQUIREMENT | 0xF | Both | 1 | The API is used to announce a change in requirement for a specific slave\n node which is currently in use | + * | PM_SET_MAX_LATENCY | 0x10 | Both | 1 | The API is used to set maximum allowed latency for the device | + * | PM_RESET_ASSERT | 0x11 | Both | 1 | The API is used to reset or de-reset a device | + * | PM_RESET_GET_STATUS | 0x12 | Both | 1 | The API is used to read the device reset state | + * | PM_MMIO_WRITE | 0x13 | ZynqMP | 1 | The API is used to write a value into a register | + * | ^ | ^ | ^ | ^ | Note: Deprecated in Versal but supported in ZynqMP | + * | PM_MMIO_READ | 0x14 | ZynqMP | 1 | The API is used to read a value from a register | + * | ^ | ^ | ^ | ^ | Note: Deprecated in Versal but supported in ZynqMP | + * | PM_INIT_FINALIZE | 0x15 | Both | 1 | The API is used to initialize subsystem and release unused devices | + * | PM_GET_CHIPID | 0x18 | Both | 1 | The API is used to request the version and ID code of a chip | + * | PM_PINCTRL_REQUEST | 0x1C | Both | 1 | The API is used to request the pin | + * | PM_PINCTRL_RELEASE | 0x1D | Both | 1 | The API is used to release the pin | + * | PM_PINCTRL_GET_FUNCTION | 0x1E | Both | 1 | The API is used to read the pin function | + * | PM_PINCTRL_SET_FUNCTION | 0x1F | Both | 1 | The API is used to set the pin function | + * | PM_PINCTRL_CONFIG_PARAM_GET| 0x20 | Both | 1 | The API is used to read the pin parameter value | + * | PM_PINCTRL_CONFIG_PARAM_SET| 0x21 | Both | 2 | V1 - The API is used to set the pin parameter value | + * | ^ | ^ | ^ | ^ | V2 - Added support of MIO tri-state controlling functionality | + * | ^ | ^ | ^ | ^ | Note: V2 is supported in ZynqMP but Versal supports only V1 | + * | PM_IOCTL | 0x22 | Both | 3 | V1 - The API is used to perform driver-like IOCTL functions on shared\n system devices | + * | ^ | ^ | ^ | ^ | V2 - Added support of bitmask functionality, user can check the supported\n ID first before performing the actual functionality | + * | ^ | ^ | ^ | ^ | V3 - Add support of zeroization of AIE data and program memory separately | + * | ^ | ^ | ^ | ^ | Note: V3 is supported in Versal but ZynqMP supports only V2 | + * | PM_QUERY_DATA | 0x23 | Both | 2 | V1 - The API is used to query information about the platform resources | + * | ^ | ^ | ^ | ^ | V2 - Added support of bitmask functionality, user can check the supported\n ID first before performing the actual functionality | + * | PM_CLOCK_ENABLE | 0x24 | Both | 1 | The API is used to enable the clock | + * | PM_CLOCK_DISABLE | 0x25 | Both | 1 | The API is used to disable the clock | + * | PM_CLOCK_GETSTATE | 0x26 | Both | 1 | The API is used to read the clock state | + * | PM_CLOCK_SETDIVIDER | 0x27 | Both | 1 | The API is used to set the divider value of the clock | + * | PM_CLOCK_GETDIVIDER | 0x28 | Both | 1 | The API is used to read the clock divider | + * | PM_CLOCK_SETPARENT | 0x2B | Both | 1 | The API is used to set the parent of the clock | + * | PM_CLOCK_GETPARENT | 0x2C | Both | 1 | The API is used to read the clock parent | + * | PM_PLL_SET_PARAM | 0x30 | Both | 1 | The API is used to set the parameter of PLL clock | + * | PM_PLL_GET_PARAM | 0x31 | Both | 1 | The API is used to read the parameter of PLL clock | + * | PM_PLL_SET_MODE | 0x32 | Both | 1 | The API is used to set the mode of PLL clock | + * | PM_PLL_GET_MODE | 0x33 | Both | 1 | The API is used to read the mode of PLL clock | + * | PM_REGISTER_ACCESS | 0x34 | ZynqMP | 1 | The API is used for register read/write access data | + * | ^ | ^ | ^ | ^ | Note: Deprecated in Versal but supported in ZynqMP | + * | PM_EFUSE_ACCESS | 0x35 | ZynqMP | 1 | The API is used to provide access to efuse memory | + * | ^ | ^ | ^ | ^ | Note: Deprecated in Versal but supported in ZynqMP | + * | PM_FEATURE_CHECK | 0x3F | Both | 2 | V1 - The API is used to return supported version of the given API | + * | ^ | ^ | ^ | ^ | V2 - Added support of bitmask payload functionality | + * + *****************************************************************************/ + +/*****************************************************************************/ +/** + * @section IOCTL_ID_DETAIL XilPM IOCTL IDs Detail + * + * This section provides the details of the IOCTL IDs which are supported across the different platforms and their brief descriptions. + * + * | Name | ID | Platform | Description | + * |------------------------------------|-------|---------------|---------------------------------------| + * | IOCTL_GET_RPU_OPER_MODE | 0 | Both | Get RPU mode | + * | IOCTL_SET_RPU_OPER_MODE | 1 | Both | Set RPU mode | + * | IOCTL_RPU_BOOT_ADDR_CONFIG | 2 | Both | RPU boot address config | + * | IOCTL_TCM_COMB_CONFIG | 3 | Both | TCM config | + * | IOCTL_SET_TAPDELAY_BYPASS | 4 | Both | TAP delay bypass | + * | IOCTL_SD_DLL_RESET | 6 | Both | SD DLL reset | + * | IOCTL_SET_SD_TAPDELAY | 7 | Both | SD TAP delay | + * | IOCTL_SET_PLL_FRAC_MODE | 8 | Both | Set PLL frac mode | + * | IOCTL_GET_PLL_FRAC_MODE | 9 | Both | Get PLL frac mode | + * | IOCTL_SET_PLL_FRAC_DATA | 10 | Both | Set PLL frac data | + * | IOCTL_GET_PLL_FRAC_DATA | 11 | Both | Get PLL frac data | + * | IOCTL_WRITE_GGS | 12 | Both | Write GGS | + * | IOCTL_READ_GGS | 13 | Both | Read GGS | + * | IOCTL_WRITE_PGGS | 14 | Both | Write PGGS | + * | IOCTL_READ_PGGS | 15 | Both | Read PGGS | + * | IOCTL_ULPI_RESET | 16 | ZynqMP | ULPI reset | + * | IOCTL_SET_BOOT_HEALTH_STATUS | 17 | Both | Set boot status | + * | IOCTL_AFI | 18 | ZynqMP | AFI | + * | IOCTL_OSPI_MUX_SELECT | 21 | Versal | OSPI mux select | + * | IOCTL_USB_SET_STATE | 22 | Versal | USB set state | + * | IOCTL_GET_LAST_RESET_REASON | 23 | Versal | Get last reset reason | + * | IOCTL_AIE_ISR_CLEAR | 24 | Versal | AIE ISR clear | + * | IOCTL_REGISTER_SGI | 25 | None | Register SGI to ATF | + * | IOCTL_SET_FEATURE_CONFIG | 26 | ZynqMP | Set runtime feature config | + * | IOCTL_GET_FEATURE_CONFIG | 27 | ZynqMP | Get runtime feature config | + * | IOCTL_READ_REG | 28 | Versal | Read a 32-bit register | + * | IOCTL_MASK_WRITE_REG | 29 | Versal | RMW a 32-bit register | + * | IOCTL_SET_SD_CONFIG | 30 | ZynqMP | Set SD config register value | + * | IOCTL_SET_GEM_CONFIG | 31 | ZynqMP | Set GEM config register value | + * | IOCTL_SET_USB_CONFIG | 32 | ZynqMP | Set USB config register value | + * | IOCTL_AIE_OPS | 33 | Versal | AIE1/AIEML Run Time Operations | + * | IOCTL_GET_QOS | 34 | Versal | Get Device QoS value | + * | IOCTL_GET_APU_OPER_MODE | 35 | Versal | Get APU operation mode | + * | IOCTL_SET_APU_OPER_MODE | 36 | Versal | Set APU operation mode | + * | IOCTL_PREPARE_DDR_SHUTDOWN | 37 | Versal | Prepare DDR for shut down | + * | IOCTL_GET_SSIT_TEMP | 38 | Versal | Get secondary SLR min/max temperature | + * + *****************************************************************************/ + +/*****************************************************************************/ +/** + * @section QUERY_ID_DETAIL XilPM QUERY IDs Detail + * + * This section provides the details of the QUERY IDs which are supported across the different platforms and their brief descriptions. + * + * | Name | ID | Platform | Description | + * |--------------------------------------------|-------|---------------|---------------------------------------| + * | XPM_QID_INVALID | 0 | Both | Invalid Query ID | + * | XPM_QID_CLOCK_GET_NAME | 1 | Both | Get clock name | + * | XPM_QID_CLOCK_GET_TOPOLOGY | 2 | Both | Get clock topology | + * | XPM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS | 3 | Both | Get clock fixedfactor parameter | + * | XPM_QID_CLOCK_GET_MUXSOURCES | 4 | Both | Get clock mux sources | + * | XPM_QID_CLOCK_GET_ATTRIBUTES | 5 | Both | Get clock attributes | + * | XPM_QID_PINCTRL_GET_NUM_PINS | 6 | Both | Get total pins | + * | XPM_QID_PINCTRL_GET_NUM_FUNCTIONS | 7 | Both | Get total pin functions | + * | XPM_QID_PINCTRL_GET_NUM_FUNCTION_GROUPS | 8 | Both | Get total pin function groups | + * | XPM_QID_PINCTRL_GET_FUNCTION_NAME | 9 | Both | Get pin function name | + * | XPM_QID_PINCTRL_GET_FUNCTION_GROUPS | 10 | Both | Get pin function groups | + * | XPM_QID_PINCTRL_GET_PIN_GROUPS | 11 | Both | Get pin groups | + * | XPM_QID_CLOCK_GET_NUM_CLOCKS | 12 | Both | Get number of clocks | + * | XPM_QID_CLOCK_GET_MAX_DIVISOR | 13 | Both | Get max clock divisor | + * | XPM_QID_PLD_GET_PARENT | 14 | Versal | Get PLD parent | + * | XPM_QID_PINCTRL_GET_ATTRIBUTES | 15 | Versal | Get pin attributes | + * + *****************************************************************************/ + + +/*****************************************************************************/ +/** + * @section GET_OP_CHAR_DETAIL XilPM GET_OP_CHAR IDs Detail + * + * This section provides the details of the GET_OP_CHAR IDs which are supported across the different platforms and their brief descriptions. + * + * | Name | ID | Platform | Description | + * |------------------------------------|-------|---------------|-----------------------------------------------| + * | PM_OPCHAR_TYPE_POWER | 1 | ZynqMP | Operating characteristic ID power | + * | PM_OPCHAR_TYPE_TEMP | 2 | Versal | Operating characteristic ID temperature | + * | PM_OPCHAR_TYPE_LATENCY | 3 | Both | Operating characteristic ID latency | + * + *****************************************************************************/ + + +/** + * PM API IDs + */ +typedef enum { + PM_API_MIN, /**< 0x0 */ + PM_GET_API_VERSION, /**< 0x1 */ + PM_SET_CONFIGURATION, /**< 0x2 */ + PM_GET_NODE_STATUS, /**< 0x3 */ + PM_GET_OP_CHARACTERISTIC, /**< 0x4 */ + PM_REGISTER_NOTIFIER, /**< 0x5 */ + PM_REQUEST_SUSPEND, /**< 0x6 */ + PM_SELF_SUSPEND, /**< 0x7 */ + PM_FORCE_POWERDOWN, /**< 0x8 */ + PM_ABORT_SUSPEND, /**< 0x9 */ + PM_REQUEST_WAKEUP, /**< 0xA */ + PM_SET_WAKEUP_SOURCE, /**< 0xB */ + PM_SYSTEM_SHUTDOWN, /**< 0xC */ + PM_REQUEST_NODE, /**< 0xD */ + PM_RELEASE_NODE, /**< 0xE */ + PM_SET_REQUIREMENT, /**< 0xF */ + PM_SET_MAX_LATENCY, /**< 0x10 */ + PM_RESET_ASSERT, /**< 0x11 */ + PM_RESET_GET_STATUS, /**< 0x12 */ + PM_MMIO_WRITE, /**< 0x13 */ + PM_MMIO_READ, /**< 0x14 */ + PM_INIT_FINALIZE, /**< 0x15 */ + PM_FPGA_LOAD, /**< 0x16 */ + PM_FPGA_GET_STATUS, /**< 0x17 */ + PM_GET_CHIPID, /**< 0x18 */ + PM_SECURE_RSA_AES, /**< 0x19 */ + PM_SECURE_SHA, /**< 0x1A */ + PM_SECURE_RSA, /**< 0x1B */ + PM_PINCTRL_REQUEST, /**< 0x1C */ + PM_PINCTRL_RELEASE, /**< 0x1D */ + PM_PINCTRL_GET_FUNCTION, /**< 0x1E */ + PM_PINCTRL_SET_FUNCTION, /**< 0x1F */ + PM_PINCTRL_CONFIG_PARAM_GET, /**< 0x20 */ + PM_PINCTRL_CONFIG_PARAM_SET, /**< 0x21 */ + PM_IOCTL, /**< 0x22 */ + PM_QUERY_DATA, /**< 0x23 */ + PM_CLOCK_ENABLE, /**< 0x24 */ + PM_CLOCK_DISABLE, /**< 0x25 */ + PM_CLOCK_GETSTATE, /**< 0x26 */ + PM_CLOCK_SETDIVIDER, /**< 0x27 */ + PM_CLOCK_GETDIVIDER, /**< 0x28 */ + PM_CLOCK_SETRATE, /**< 0x29 */ + /* PM_CLOCK_GETRATE API is deprecated */ + PM_RESERVE_ID, /**< 0x2A */ + PM_CLOCK_SETPARENT, /**< 0x2B */ + PM_CLOCK_GETPARENT, /**< 0x2C */ + PM_SECURE_IMAGE, /**< 0x2D */ + PM_FPGA_READ, /**< 0x2E */ + PM_SECURE_AES, /**< 0x2F */ + PM_PLL_SET_PARAMETER, /**< 0x30 */ + PM_PLL_GET_PARAMETER, /**< 0x31 */ + PM_PLL_SET_MODE, /**< 0x32 */ + PM_PLL_GET_MODE, /**< 0x33 */ + PM_REGISTER_ACCESS, /**< 0x34 */ + PM_EFUSE_ACCESS, /**< 0x35 */ + PM_ADD_SUBSYSTEM, /**< 0x36 */ + PM_DESTROY_SUBSYSTEM, /**< 0x37 */ + PM_DESCRIBE_NODES, /**< 0x38 */ + PM_ADD_NODE, /**< 0x39 */ + PM_ADD_NODE_PARENT, /**< 0x3A */ + PM_ADD_NODE_NAME, /**< 0x3B */ + PM_ADD_REQUIREMENT, /**< 0x3C */ + PM_SET_CURRENT_SUBSYSTEM, /**< 0x3D */ + PM_INIT_NODE, /**< 0x3E */ + PM_FEATURE_CHECK, /**< 0x3F */ + PM_ISO_CONTROL, /**< 0x40 */ + PM_ACTIVATE_SUBSYSTEM, /**< 0x41 */ + PM_SET_NODE_ACCESS, /**< 0x42 */ + PM_BISR, /**< 0x43 */ + PM_APPLY_TRIM, /**< 0x44 */ + PM_NOC_CLOCK_ENABLE, /**< 0x45 */ + PM_IF_NOC_CLOCK_ENABLE, /**< 0x46 */ + PM_FORCE_HOUSECLEAN, /**< 0x47 */ + PM_FPGA_GET_VERSION, /**< 0x48 */ + PM_FPGA_GET_FEATURE_LIST, /**< 0x49 */ + PM_API_MAX /**< 0x4A */ +} XPm_ApiId; + +#endif /* PM_API_VERSION_H_ */ diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/print.c b/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/print.c index e8ac3d4..cb66494 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/print.c +++ b/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/print.c @@ -12,19 +12,22 @@ * the new terms are clearly indicated on the first page of each file where * they apply. * - */ + *****************************************************************************/ +/***************************** Include Files *********************************/ -/* - * print -- do a raw print of a string - */ #include "xil_printf.h" +/*****************************************************************************/ +/** +* print -- do a raw print of a string +* +******************************************************************************/ void print(const char8 *ptr) { #if defined (__aarch64__) && (HYP_GUEST == 1) && (EL1_NONSECURE == 1) && defined (XEN_USE_PV_CONSOLE) XPVXenConsole_Write(ptr); #else -#ifdef STDOUT_BASEADDRESS +#if defined(STDOUT_BASEADDRESS) || defined(SDT) while (*ptr != (char8)0) { outbyte (*ptr); ptr++; diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/putnum.c b/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/putnum.c index a4c5e47..3582ffe 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/putnum.c +++ b/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/putnum.c @@ -11,11 +11,7 @@ * and need not follow the licensing terms described here, provided that * the new terms are clearly indicated on the first page of each file where * they apply. - */ - -/* - * putnum -- print a 32 bit number in hex - */ + *****************************************************************************/ /***************************** Include Files *********************************/ #include "xil_types.h" @@ -24,6 +20,11 @@ /************************** Function Prototypes ******************************/ void putnum(u32 num); +/*****************************************************************************/ +/** +* putnum -- print a 32 bit number in hex +* +******************************************************************************/ void putnum(u32 num) { char8 buf[9]; diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/read.c b/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/read.c index eb81317..decf665 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/read.c +++ b/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/read.c @@ -1,5 +1,6 @@ /****************************************************************************** * Copyright (c) 2009 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -8,7 +9,10 @@ */ #ifndef UNDEFINE_FILE_OPS #include "xil_printf.h" +#include "bspconfig.h" +#ifndef SDT #include "xparameters.h" +#endif #ifdef __cplusplus extern "C" { @@ -28,7 +32,7 @@ __attribute__((weak)) s32 read (s32 fd, char8* buf, s32 nbytes); __attribute__((weak)) s32 read (s32 fd, char8* buf, s32 nbytes) { -#ifdef STDIN_BASEADDRESS +#if defined (STDIN_BASEADDRESS) || defined(SDT) s32 i; s32 numbytes = 0; char8* LocalBuf = buf; @@ -56,7 +60,7 @@ read (s32 fd, char8* buf, s32 nbytes) __attribute__((weak)) s32 _read (s32 fd, char8* buf, s32 nbytes) { -#ifdef STDIN_BASEADDRESS +#if defined(STDIN_BASEADDRESS) || defined(SDT) s32 i; s32 numbytes = 0; char8* LocalBuf = buf; diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/sleep.c b/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/sleep.c index efa60da..d3e3d76 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/sleep.c +++ b/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/sleep.c @@ -1,5 +1,6 @@ /****************************************************************************** -* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved. +* Copyright (C) 2009 - 2020 Xilinx, Inc. All rights reserved. +* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -21,7 +22,7 @@ * 6.6 srm 10/18/17 Updated sleep routines to support user configurable * implementation. Now sleep routines will use Timer * specified by the user (i.e. Global timer/TTC timer) -* +* 9.0 ml 03/03/23 Add description to fix doxygen warnings. * * ******************************************************************************/ @@ -36,7 +37,7 @@ #endif /*****************************************************************************/ -/* +/** * * This API is used to provide delays in seconds * @@ -46,7 +47,7 @@ * * @note None. * -****************************************************************************/ +******************************************************************************/ unsigned sleep_A9(unsigned int seconds) { #if defined (SLEEP_TIMER_BASEADDR) diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/sleep.h b/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/sleep.h index 3c9c788..c41750f 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/sleep.h +++ b/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/sleep.h @@ -1,5 +1,6 @@ /****************************************************************************** -* Copyright (c) 2014 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (C) 2014 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -30,7 +31,8 @@ * 8.0 sk 03/17/22 Modify sleep_MB parameter type from unsigned int to * u32 and usleep_MB parameter type from unsigned long to * ULONG to fix misra_c_2012_rule_4_6 violation. -* +* 9.0 ml 03/03/23 Add description to fix doxygen warnings. +* 9.1 mus 10/24/23 Add support for RISC-V. * * ******************************************************************************/ @@ -87,6 +89,7 @@ extern "C" { (timeout>0) ? 0 : -1; \ } ) +/************************** Function Prototypes ******************************/ void usleep(ULONG useconds); void sleep(u32 seconds); void usleep_R5(ULONG useconds); @@ -97,6 +100,10 @@ int usleep_A53(unsigned long useconds); unsigned sleep_A53(unsigned int seconds); int usleep_A9(unsigned long useconds); unsigned sleep_A9(unsigned int seconds); +void sleep_riscv(u32 seconds); +void usleep_riscv(ULONG useconds); + +/*****************************************************************************/ #ifdef __cplusplus } diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/translation_table.S b/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/translation_table.S index 125fe7f..cd8e49f 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/translation_table.S +++ b/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/translation_table.S @@ -1,5 +1,6 @@ /****************************************************************************** * Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved. +* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ /*****************************************************************************/ @@ -67,7 +68,12 @@ * * ******************************************************************************/ +#include "bspconfig.h" +#ifndef SDT #include "xparameters.h" +#else +#include "xmem_config.h" +#endif .globl MMUTable .section .mmu_tbl,"a" @@ -84,6 +90,11 @@ MMUTable: .set DDR_END, XPAR_PS7_DDR_0_S_AXI_HIGHADDR .set DDR_SIZE, (DDR_END - DDR_START)+1 .set DDR_REG, DDR_SIZE/0x100000 +#elif defined(XPAR_PS7_DDR_0_BASEADDRESS) +.set DDR_START, XPAR_PS7_DDR_0_BASEADDRESS +.set DDR_END, XPAR_PS7_DDR_0_HIGHADDRESS +.set DDR_SIZE, (DDR_END - DDR_START)+1 +.set DDR_REG, DDR_SIZE/0x100000 #else .set DDR_REG, 0 #endif diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/usleep.c b/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/usleep.c index 26966bf..82f15ce 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/usleep.c +++ b/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/usleep.c @@ -1,5 +1,6 @@ /****************************************************************************** * Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved. +* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -25,6 +26,7 @@ * 6.6 srm 10/18/17 Updated sleep routines to support user configurable * implementation. Now sleep routines will use Timer * specified by the user (i.e. Global timer/TTC timer) +* 9.0 ml 03/03/23 Added description to fix doxygen warnings. * * ******************************************************************************/ @@ -45,7 +47,7 @@ #if defined (SLEEP_TIMER_BASEADDR) #define COUNTS_PER_USECOND (SLEEP_TIMER_FREQUENCY / 1000000) #else -/* Global Timer is always clocked at half of the CPU frequency */ +/**< Global Timer is always clocked at half of the CPU frequency */ #define COUNTS_PER_USECOND (XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ / (2U*1000000U)) #endif diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/write.c b/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/write.c index cf1d35e..279a0cd 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/write.c +++ b/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/write.c @@ -1,5 +1,6 @@ /****************************************************************************** * Copyright (c) 2009 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -8,7 +9,10 @@ */ #ifndef UNDEFINE_FILE_OPS #include "xil_printf.h" +#include "bspconfig.h" +#ifndef SDT #include "xparameters.h" +#endif #ifdef __cplusplus extern "C" { @@ -30,7 +34,7 @@ __attribute__((weak)) sint32 write (sint32 fd, char8* buf, sint32 nbytes) { -#ifdef STDOUT_BASEADDRESS +#if defined(STDOUT_BASEADDRESS) || defined(SDT) s32 i; char8* LocalBuf = buf; @@ -69,7 +73,7 @@ _write (sint32 fd, char8* buf, sint32 nbytes) length = XPVXenConsole_Write(buf); return length; #else -#ifdef STDOUT_BASEADDRESS +#if defined(STDOUT_BASEADDRESS) || defined(SDT) s32 i; char8* LocalBuf = buf; diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xcortexa9.h b/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xcortexa9.h new file mode 100644 index 0000000..65a9db0 --- /dev/null +++ b/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xcortexa9.h @@ -0,0 +1,18 @@ +/****************************************************************************** +* Copyright (c) 2021-2022 Xilinx, Inc. All rights reserved. +* Copyright (c) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ +#ifndef XIL_XCORTEXA9_H_ /* prevent circular inclusions */ +#define XIL_XCORTEXA9_H_ /* by using protection macros */ + +/***************************** Include Files ********************************/ + +#include "xil_types.h" + +/**************************** Type Definitions ******************************/ +typedef struct { + u32 CpuFreq; +} XCortexa9_Config; + +#endif /* XIL_XCORTEXA9_H_ */ diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xcortexa9_config.h b/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xcortexa9_config.h new file mode 100644 index 0000000..1a774f1 --- /dev/null +++ b/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xcortexa9_config.h @@ -0,0 +1,18 @@ +/****************************************************************************** +* Copyright (c) 2021-2022 Xilinx, Inc. All rights reserved. +* Copyright (c) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ +#ifndef XIL_XCORTEXA9_CONFIG_H_ /* prevent circular inclusions */ +#define XIL_XCORTEXA9_CONFIG_H_ /* by using protection macros */ + +/***************************** Include Files ********************************/ + +#include "xcortexa9.h" + +/************************** Variable Definitions ****************************/ +extern XCortexa9_Config XCortexa9_ConfigTable; + +/***************** Macros (Inline Functions) Definitions ********************/ +#define XGet_CpuFreq() XCortexa9_ConfigTable.CpuFreq +#endif /* XIL_XCORTEXA9_CONFIG_H_ */ diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xdebug.h b/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xdebug.h index 8e6b3ef..74bfdb0 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xdebug.h +++ b/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xdebug.h @@ -1,6 +1,6 @@ /****************************************************************************** * Copyright (C) 2002 - 2021 Xilinx, Inc. All rights reserved. -* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved. +* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -61,13 +61,13 @@ int printf(const char *format, ...); #else /* defined(DEBUG) && !defined(NDEBUG) */ -#define xdbg_stmnt(x) +#define xdbg_stmnt(x) /**< Debug statement */ /* See VxWorks comments above */ #if defined(XENV_VXWORKS) && defined(_WRS_GNU_VAR_MACROS) #define xdbg_printf(type, args...) #else /* ANSI Syntax */ -#define xdbg_printf(...) +#define xdbg_printf(...) /**< Debug printf */ #endif #endif /* defined(DEBUG) && !defined(NDEBUG) */ diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xil-crt0.S b/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xil-crt0.S index a560286..5d87bc1 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xil-crt0.S +++ b/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xil-crt0.S @@ -1,5 +1,6 @@ /****************************************************************************** * Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved. +* Copyright (c) 2024 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ /*****************************************************************************/ @@ -25,6 +26,7 @@ * Now the TTC instance as specified by the user will be * started. * 7.7 adk 11/30/21 Added support for xiltimer library. +* 9.1 dp 01/24/24 Dont invoke XTime_StartTTCTimer when xiltimer is enabled * * * @note @@ -93,7 +95,7 @@ _start: mov r1, #0x0 /* Reset and start Triple Timer Counter */ - #if defined SLEEP_TIMER_BASEADDR + #if defined SLEEP_TIMER_BASEADDR && !defined(XPAR_XILTIMER_ENABLED) bl XTime_StartTTCTimer #endif diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xil_cache.c b/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xil_cache.c index f00fb25..23cbb7b 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xil_cache.c +++ b/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xil_cache.c @@ -1,6 +1,6 @@ /****************************************************************************** * Copyright (c) 2010 - 2022 Xilinx, Inc. All rights reserved. -* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved. +* Copyright (c) 2022 - 2024 Advanced Micro Devices, Inc. All rights reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -89,6 +89,18 @@ * 8.1 asa 02/13/23 The existing Xil_DCacheInvalidateRange has a bug where * the last cache line will not get invalidated under certain * scenarios. Changes are made to fix the same. +* 9.0 ml 03/03/23 Added description to fix doxygen warnings. +* mus 09/21/23 Fix infinite loop in Xil_DCacheInvalidateRange when +* USE_AMP=1. +* 9.1 asa 01/12/24 Fix issues in Xil_DCacheInvalidateRange. +* 9.1 asa 01/29/24 In an unlikely scenario where the start address +* passed is 0x0 and length is less than 0x20 (cache line), +* the XilDCacheInvalidateRange API will result in +* a probable crash as it will try to invalidate the +* complete 4 GB address range. +* Changes are made to fix the same. +* 9.1 asa 31/01/24 Fix overflow issues under corner cases for various +* cache maintenance APIs. * * ******************************************************************************/ @@ -109,7 +121,9 @@ /************************** Variable Definitions *****************************/ -#define IRQ_FIQ_MASK 0xC0U /* Mask IRQ and FIQ interrupts in cpsr */ +#define IRQ_FIQ_MASK 0xC0U /**< Mask IRQ and FIQ interrupts in cpsr */ +#define MAX_ADDR 0xFFFFFFFFU +#define LAST_CACHELINE_START 0xFFFFFFE0U #ifdef __GNUC__ extern s32 _stack_end; @@ -117,7 +131,8 @@ #endif #ifndef USE_AMP -/**************************************************************************** +/***************************************************************************/ +/** * * Access L2 Debug Control Register. * @@ -139,7 +154,8 @@ static void Xil_L2WriteDebugCtrl(u32 Value) #endif } -/**************************************************************************** +/***************************************************************************/ +/** * * Perform L2 Cache Sync Operation. * @@ -300,13 +316,14 @@ void Xil_DCacheInvalidateLine(u32 adr) * @return None. * ****************************************************************************/ -void Xil_DCacheInvalidateRange(INTPTR opstartaddr, u32 len) +void Xil_DCacheInvalidateRange(INTPTR adr, u32 len) { const u32 cacheline = 32U; INTPTR tempadr; INTPTR opendaddr; INTPTR endaddr; u32 currmask; + u32 unalignedstart = 0x0; volatile u32 *L2CCOffset = (volatile u32 *)(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INVLD_PA_OFFSET); @@ -314,27 +331,29 @@ void Xil_DCacheInvalidateRange(INTPTR opstartaddr, u32 len) mtcpsr(currmask | IRQ_FIQ_MASK); if (len != 0U) { - opendaddr = opstartaddr + len; + ((MAX_ADDR - (u32)adr) < len) ? (opendaddr = MAX_ADDR) : (opendaddr = adr + len); endaddr = opendaddr; - if ((opstartaddr & (cacheline-1U)) != 0U) { - opstartaddr &= (~(cacheline - 1U)); + if ((adr & (cacheline-1U)) != 0U) { + adr &= (~(cacheline - 1U)); + unalignedstart = 1; - Xil_L1DCacheFlushLine(opstartaddr); + Xil_L1DCacheFlushLine(adr); #ifndef USE_AMP /* Disable Write-back and line fills */ Xil_L2WriteDebugCtrl(0x3U); - Xil_L2CacheFlushLine(opstartaddr); + Xil_L2CacheFlushLine(adr); /* Enable Write-back and line fills */ Xil_L2WriteDebugCtrl(0x0U); Xil_L2CacheSync(); #endif - opstartaddr += cacheline; + tempadr = adr; + (u32)adr >= LAST_CACHELINE_START ? (adr = endaddr) : (adr += cacheline); } if ((opendaddr & (cacheline-1U)) != 0U) { opendaddr &= (~(cacheline - 1U)); - if (opendaddr != opstartaddr) { + if ((opendaddr != tempadr) || (unalignedstart == 0x0U)) { Xil_L1DCacheFlushLine(opendaddr); #ifndef USE_AMP /* Disable Write-back and line fills */ @@ -343,31 +362,32 @@ void Xil_DCacheInvalidateRange(INTPTR opstartaddr, u32 len) /* Enable Write-back and line fills */ Xil_L2WriteDebugCtrl(0x0U); Xil_L2CacheSync(); + (u32)endaddr >= cacheline ? (endaddr -= cacheline) : (endaddr = 0); #endif } } - tempadr = opstartaddr; + tempadr = adr; - while (tempadr < endaddr) { #ifndef USE_AMP + while (tempadr < endaddr) { /* Invalidate L2 cache line */ *L2CCOffset = tempadr; Xil_L2CacheSync(); - tempadr += cacheline; -#endif + ((MAX_ADDR - (u32)tempadr) < cacheline) ? (tempadr = MAX_ADDR) : (tempadr += cacheline) ; } +#endif - while (opstartaddr < endaddr) { + while (adr < endaddr) { /* Invalidate L1 Data cache line */ #if defined (__GNUC__) || defined (__ICCARM__) - asm_cp15_inval_dc_line_mva_poc(opstartaddr); + asm_cp15_inval_dc_line_mva_poc(adr); #else { volatile register u32 Reg __asm(XREG_CP15_INVAL_DC_LINE_MVA_POC); - Reg = opstartaddr; } + Reg = adr; } #endif - opstartaddr += cacheline; + ((MAX_ADDR - (u32)adr) < cacheline) ? (adr = MAX_ADDR) : (adr += cacheline) ; } /* Wait for L1 cache invalidation to complete */ dsb(); @@ -444,7 +464,7 @@ void Xil_DCacheFlushLine(u32 adr) * @return None. * ****************************************************************************/ -void Xil_DCacheFlushRange(INTPTR opstartadr, u32 len) +void Xil_DCacheFlushRange(INTPTR adr, u32 len) { const u32 cacheline = 32U; u32 opendadr; @@ -458,10 +478,10 @@ void Xil_DCacheFlushRange(INTPTR opstartadr, u32 len) mtcpsr(currmask | IRQ_FIQ_MASK); if (len != 0U) { - opendadr = opstartadr + len; - opstartadr &= ~(cacheline - 1U); + ((MAX_ADDR - (u32)adr) < len) ? (opendadr = MAX_ADDR) : (opendadr = adr + len); + adr &= ~(cacheline - 1U); - tempadr = opstartadr; + tempadr = adr; while (tempadr < opendadr) { /* Flush L1 Data cache line */ @@ -472,7 +492,7 @@ void Xil_DCacheFlushRange(INTPTR opstartadr, u32 len) __asm(XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC); Reg = tempadr; } #endif - tempadr += cacheline; + ((MAX_ADDR - (u32)tempadr) < cacheline) ? (tempadr = MAX_ADDR) : (tempadr += cacheline); } /* Wait for L1 cache clean and invalidation to complete */ dsb(); @@ -480,11 +500,11 @@ void Xil_DCacheFlushRange(INTPTR opstartadr, u32 len) #ifndef USE_AMP /* Disable Write-back and line fills */ Xil_L2WriteDebugCtrl(0x3U); - while ((u32)opstartadr < opendadr) { + while ((u32)adr < opendadr) { /* Flush L2 cache line */ - *L2CCOffset = opstartadr; + *L2CCOffset = adr; Xil_L2CacheSync(); - opstartadr += cacheline; + ((MAX_ADDR - (u32)adr) < cacheline) ? (adr = MAX_ADDR) : (adr += cacheline); } Xil_L2WriteDebugCtrl(0x0U); #endif @@ -627,7 +647,7 @@ void Xil_ICacheInvalidateRange(INTPTR adr, u32 len) /* Back the starting address up to the start of a cache line * perform cache operations until adr+len */ - end = LocalAddr + len; + ((MAX_ADDR - LocalAddr) < len) ? (end = MAX_ADDR) : (end = LocalAddr + len); LocalAddr = LocalAddr & ~(cacheline - 1U); while (LocalAddr < end) { @@ -645,7 +665,7 @@ void Xil_ICacheInvalidateRange(INTPTR adr, u32 len) __asm(XREG_CP15_INVAL_IC_LINE_MVA_POU); Reg = LocalAddr; } #endif - LocalAddr += cacheline; + ((MAX_ADDR - LocalAddr) < cacheline) ? (LocalAddr = MAX_ADDR) : (LocalAddr += cacheline) ; } /* Wait for L1 I cache invalidation to complete */ dsb(); @@ -860,7 +880,7 @@ void Xil_L1DCacheInvalidateRange(u32 adr, u32 len) /* Back the starting address up to the start of a cache line * perform cache operations until adr+len */ - end = LocalAddr + len; + ((MAX_ADDR - LocalAddr) < len) ? (end = MAX_ADDR) : (end = LocalAddr + len); LocalAddr = LocalAddr & ~(cacheline - 1U); while (LocalAddr < end) { @@ -872,7 +892,7 @@ void Xil_L1DCacheInvalidateRange(u32 adr, u32 len) __asm(XREG_CP15_INVAL_DC_LINE_MVA_POC); Reg = LocalAddr; } #endif - LocalAddr += cacheline; + ((MAX_ADDR - LocalAddr) < cacheline) ? (LocalAddr = MAX_ADDR) : (LocalAddr += cacheline); } /* Wait for L1 cache invalidation to complete */ @@ -1006,7 +1026,7 @@ void Xil_L1DCacheFlushRange(u32 adr, u32 len) /* Back the starting address up to the start of a cache line * perform cache operations until adr+len */ - end = LocalAddr + len; + ((MAX_ADDR - LocalAddr) < len) ? (end = MAX_ADDR) : (end = LocalAddr + len); LocalAddr = LocalAddr & ~(cacheline - 1U); while (LocalAddr < end) { @@ -1018,7 +1038,7 @@ void Xil_L1DCacheFlushRange(u32 adr, u32 len) __asm(XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC); Reg = LocalAddr; } #endif - LocalAddr += cacheline; + ((MAX_ADDR - LocalAddr) < cacheline) ? (LocalAddr = MAX_ADDR) : (LocalAddr += cacheline); } /* Wait for L1 cache clean and invalidation to complete */ @@ -1182,7 +1202,7 @@ void Xil_L1ICacheInvalidateRange(u32 adr, u32 len) /* Back the starting address up to the start of a cache line * perform cache operations until adr+len */ - end = LocalAddr + len; + ((MAX_ADDR - LocalAddr) < len) ? (end = MAX_ADDR) : (end = LocalAddr + len); LocalAddr = LocalAddr & ~(cacheline - 1U); while (LocalAddr < end) { @@ -1194,7 +1214,7 @@ void Xil_L1ICacheInvalidateRange(u32 adr, u32 len) __asm(XREG_CP15_INVAL_IC_LINE_MVA_POU); Reg = LocalAddr; } #endif - LocalAddr += cacheline; + ((MAX_ADDR - LocalAddr) < cacheline) ? (LocalAddr = MAX_ADDR) : (LocalAddr += cacheline); } /* Wait for L1 cache invalidation to complete */ @@ -1378,7 +1398,7 @@ void Xil_L2CacheInvalidateRange(u32 adr, u32 len) /* Back the starting address up to the start of a cache line * perform cache operations until adr+len */ - end = LocalAddr + len; + ((MAX_ADDR - LocalAddr) < len) ? (end = MAX_ADDR) : (end = LocalAddr + len); LocalAddr = LocalAddr & ~(cacheline - 1U); /* Disable Write-back and line fills */ @@ -1387,7 +1407,7 @@ void Xil_L2CacheInvalidateRange(u32 adr, u32 len) while (LocalAddr < end) { *L2CCOffset = LocalAddr; Xil_L2CacheSync(); - LocalAddr += cacheline; + ((MAX_ADDR - LocalAddr) < cacheline) ? (LocalAddr = MAX_ADDR) : (LocalAddr += cacheline); } /* Enable Write-back and line fills */ @@ -1489,7 +1509,7 @@ void Xil_L2CacheFlushRange(u32 adr, u32 len) /* Back the starting address up to the start of a cache line * perform cache operations until adr+len */ - end = LocalAddr + len; + ((MAX_ADDR - LocalAddr) < len) ? (end = MAX_ADDR) : (end = LocalAddr + len); LocalAddr = LocalAddr & ~(cacheline - 1U); /* Disable Write-back and line fills */ @@ -1498,7 +1518,7 @@ void Xil_L2CacheFlushRange(u32 adr, u32 len) while (LocalAddr < end) { *L2CCOffset = LocalAddr; Xil_L2CacheSync(); - LocalAddr += cacheline; + ((MAX_ADDR - LocalAddr) < cacheline) ? (LocalAddr = MAX_ADDR) : (LocalAddr += cacheline); } /* Enable Write-back and line fills */ diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xil_cache.h b/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xil_cache.h index 75cd6f6..7c94568 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xil_cache.h +++ b/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xil_cache.h @@ -1,5 +1,6 @@ /****************************************************************************** -* Copyright (c) 2010 - 2021 Xilinx, Inc. All rights reserved. +* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved. +* Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -26,6 +27,7 @@ * 3.04a sdm 01/02/12 Remove redundant dsb/dmb instructions in cache maintenance * APIs. * 6.8 aru 09/06/18 Removed compilation warnings for ARMCC toolchain. +* 9.0 ml 03/03/23 Updated function prototypes. * * ******************************************************************************/ diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xil_cryptoalginfo.h b/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xil_cryptoalginfo.h new file mode 100644 index 0000000..df95b88 --- /dev/null +++ b/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xil_cryptoalginfo.h @@ -0,0 +1,50 @@ +/******************************************************************************/ +/** +* Copyright (c) 2023 Advanced Micro Devices, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/****************************************************************************/ +/** +* @file xil_cryptoalginfo.h +* @{ +* @details +* +* Crypto algotithm information structure declaration. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 9.0   mmd      07/04/23 First release.
+*
+* +*****************************************************************************/ +#ifndef XIL_CRYPTOALGINFO_H +#define XIL_CRYPTOALGINFO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ +#include "xil_types.h" + +/**************************** Type Definitions *******************************/ +typedef enum _Xil_CryptoAlgNistStatus { + NOT_APPLICABLE = 0x00, + NIST_COMPLIANT = 0x11, + NIST_NON_COMPLIANT = 0xFE, +} Xil_CryptoAlgNistStatus; + +typedef struct _Xil_CryptoAlgInfo { + u32 Version; + Xil_CryptoAlgNistStatus NistStatus; +} Xil_CryptoAlgInfo; + +#ifdef __cplusplus +} +#endif + +#endif /* XIL_CRYPTOALGINFO_H */ diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xil_exception.c b/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xil_exception.c index 4388d52..e08ecb9 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xil_exception.c +++ b/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xil_exception.c @@ -1,7 +1,6 @@ /****************************************************************************** * Copyright (c) 2015 - 2022 Xilinx, Inc. All rights reserved. * Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved. -* * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -44,10 +43,11 @@ * file to fix misra_c_2012_rule_5_6 violation. * 8.1 asa 02/12/23 Updated data abort and prefetch abort fault * status reporting for ARMv7. -* Updated Sync and SError fault status reporting -* for ARMv8. -* -* +* Updated Sync and SError fault status reporting +* for ARMv8. +* 9.0 ml 03/03/23 Add description to fix doxygen warnings. +* 9.0 ml 14/04/23 Add comment to default case in switch statement to fix +* misra-c violation. * * *****************************************************************************/ @@ -159,14 +159,14 @@ void Xil_ExceptionInit(void) /*****************************************************************************/ /** * @brief Register a handler for a specific exception. This handler is being -* called when the processor encounters the specified exception. +* called when the processor encounters the specified exception. * * @param Exception_id contains the ID of the exception source and should -* be in the range of 0 to XIL_EXCEPTION_ID_LAST. -* See xil_exception.h for further information. +* be in the range of 0 to XIL_EXCEPTION_ID_LAST. +* See xil_exception.h for further information. * @param Handler to the Handler for that exception. * @param Data is a reference to Data that will be passed to the -* Handler when it gets called. +* Handler when it gets called. * * @return None. * @@ -175,7 +175,7 @@ void Xil_ExceptionRegisterHandler(u32 Exception_id, Xil_ExceptionHandler Handler, void *Data) { -#if (defined (versal) && !defined(ARMR5) && EL3) || defined(ARMR52) +#if (defined (versal) && !defined(ARMR5) && EL3) if ( XIL_EXCEPTION_ID_IRQ_INT == Exception_id ) { /* @@ -209,7 +209,7 @@ void Xil_GetExceptionRegisterHandler(u32 Exception_id, Xil_ExceptionHandler *Handler, void **Data) { -#if (defined (versal) && !defined(ARMR5) && EL3) || defined(ARMR52) +#if (defined (versal) && !defined(ARMR5) && EL3) if ( XIL_EXCEPTION_ID_IRQ_INT == Exception_id ) { /* @@ -229,12 +229,12 @@ void Xil_GetExceptionRegisterHandler(u32 Exception_id, /*****************************************************************************/ /** * -* @brief Removes the Handler for a specific exception Id. The stub Handler -* is then registered for this exception Id. +* @brief Removes the Handler for a specific exception id. The stub Handler +* is then registered for this exception id. * * @param Exception_id contains the ID of the exception source and should -* be in the range of 0 to XIL_EXCEPTION_ID_LAST. -* See xil_exception.h for further information. +* be in the range of 0 to XIL_EXCEPTION_ID_LAST. +* See xil_exception.h for further information. * * @return None. * @@ -852,6 +852,8 @@ static u32 NotifyFaultStatusDetails(u32 Fault_Type, u32 FaultStatus) break; #endif default: + /* if above cases doesn't match, then + default case will execute and terminate a statement sequence */ break; } diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xil_exception.h b/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xil_exception.h index 3a5bb29..b517983 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xil_exception.h +++ b/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xil_exception.h @@ -75,8 +75,10 @@ #include "xil_types.h" #include "xpseudo_asm.h" #include "bspconfig.h" +#ifndef SDT #include "xparameters.h" #include "xdebug.h" +#endif #ifdef __cplusplus extern "C" { @@ -228,7 +230,7 @@ extern "C" { /* * XIL_EXCEPTION_ID_INT is defined for all Xilinx processors. */ -#if (defined (versal) && !defined(ARMR5) && EL3) || defined(ARMR52) +#if (defined (versal) && !defined(ARMR5) && EL3) #define XIL_EXCEPTION_ID_INT XIL_EXCEPTION_ID_FIQ_INT #else #define XIL_EXCEPTION_ID_INT XIL_EXCEPTION_ID_IRQ_INT @@ -267,7 +269,7 @@ extern XExc_VectorTableEntry XExc_VectorTable[]; * C-Style signature: void Xil_ExceptionEnableMask(Mask) * ******************************************************************************/ -#if (defined (versal) && !defined(ARMR5) && EL3) || defined(ARMR52) +#if (defined (versal) && !defined(ARMR5) && EL3) /* * Cortexa72 processor in versal is coupled with GIC-500, and GIC-500 supports * only FIQ at EL3. Hence, tweaking this macro to always enable FIQ @@ -295,7 +297,7 @@ extern XExc_VectorTableEntry XExc_VectorTable[]; * @note None. * ******************************************************************************/ -#if (defined (versal) && !defined(ARMR5) && EL3) || defined(ARMR52) +#if (defined (versal) && !defined(ARMR5) && EL3) #define Xil_ExceptionEnable() \ Xil_ExceptionEnableMask(XIL_EXCEPTION_FIQ) #else @@ -315,7 +317,7 @@ extern XExc_VectorTableEntry XExc_VectorTable[]; * C-Style signature: Xil_ExceptionDisableMask(Mask) * ******************************************************************************/ -#if (defined (versal) && !defined(ARMR5) && EL3) || defined(ARMR52) +#if (defined (versal) && !defined(ARMR5) && EL3) /* * Cortexa72 processor in versal is coupled with GIC-500, and GIC-500 supports * only FIQ at EL3. Hence, tweaking this macro to always disable FIQ diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xil_io.h b/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xil_io.h index 853ef6b..382bc87 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xil_io.h +++ b/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xil_io.h @@ -1,5 +1,6 @@ /****************************************************************************** -* Copyright (c) 2014 - 2021 Xilinx, Inc. All rights reserved. +* Copyright (C) 2014 - 2021 Xilinx, Inc. All rights reserved. +* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -32,12 +33,12 @@ * 7.50 dp 02/12/21 Fix compilation error in Xil_EndianSwap32() that occur * when -Werror=conversion compiler flag is enabled * 7.5 mus 05/17/21 Update the functions with comments. It fixes CR#1067739. -* +* 9.0 ml 03/03/23 Add description and remove comments to fix doxygen warnings. * ******************************************************************************/ -#ifndef XIL_IO_H /* prevent circular inclusions */ -#define XIL_IO_H /* by using protection macros */ +#ifndef XIL_IO_H /**< prevent circular inclusions */ +#define XIL_IO_H /**< by using protection macros */ #ifdef __cplusplus extern "C" { @@ -63,25 +64,25 @@ extern u32 XStl_RegUpdate(u32 RegAddr, u32 RegVal); /***************** Macros (Inline Functions) Definitions *********************/ #if defined __GNUC__ #if defined (__MICROBLAZE__) -# define INST_SYNC mbar(0) -# define DATA_SYNC mbar(1) +# define INST_SYNC mbar(0) /**< Instruction Synchronization Barrier */ +# define DATA_SYNC mbar(1) /**< Data Synchronization Barrier */ # else -# define SYNCHRONIZE_IO dmb() -# define INST_SYNC isb() -# define DATA_SYNC dsb() +# define SYNCHRONIZE_IO dmb() /**< Data Memory Barrier */ +# define INST_SYNC isb() /**< Instruction Synchronization Barrier */ +# define DATA_SYNC dsb() /**< Data Synchronization Barrier */ # endif #else -# define SYNCHRONIZE_IO -# define INST_SYNC -# define DATA_SYNC -# define INST_SYNC -# define DATA_SYNC +# define SYNCHRONIZE_IO /**< Data Memory Barrier */ +# define INST_SYNC /**< Instruction Synchronization Barrier */ +# define DATA_SYNC /**< Data Synchronization Barrier */ +# define INST_SYNC /**< Instruction Synchronization Barrier */ +# define DATA_SYNC /**< Data Synchronization Barrier */ #endif #if defined (__GNUC__) || defined (__ICCARM__) || defined (__MICROBLAZE__) -#define INLINE inline +#define INLINE inline /**< static inline keyword */ #else -#define INLINE __inline +#define INLINE __inline /** * *****************************************************************************/ -#ifndef XIL_MEM_H /* prevent circular inclusions */ -#define XIL_MEM_H /* by using protection macros */ +#ifndef XIL_MEM_H /**< prevent circular inclusions */ +#define XIL_MEM_H /**< by using protection macros */ #ifdef __cplusplus extern "C" { diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xil_misc_psreset_api.h b/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xil_misc_psreset_api.h index 878d575..de0ff25 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xil_misc_psreset_api.h +++ b/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xil_misc_psreset_api.h @@ -1,5 +1,6 @@ /****************************************************************************** -* Copyright (c) 2013 - 2021 Xilinx, Inc. All rights reserved. +* Copyright (C) 2013 - 2021 Xilinx, Inc. All rights reserved. +* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -15,12 +16,13 @@ * Ver Who Date Changes * ----- ---- -------- ------------------------------------------------------- * 1.00b kpc 03/07/13 First release. +* 9.0 ml 03/03/23 Add description to fix doxygen warnings. * * ******************************************************************************/ -#ifndef XIL_MISC_RESET_H /* prevent circular inclusions */ -#define XIL_MISC_RESET_H /* by using protection macros */ +#ifndef XIL_MISC_RESET_H /**< prevent circular inclusions */ +#define XIL_MISC_RESET_H /**< by using protection macros */ #ifdef __cplusplus extern "C" { diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xil_mmu.c b/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xil_mmu.c index 85a1af4..9e15c6a 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xil_mmu.c +++ b/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xil_mmu.c @@ -1,5 +1,6 @@ /****************************************************************************** * Copyright (c) 2012 - 2021 Xilinx, Inc. All rights reserved. +* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -31,6 +32,7 @@ * redundant TLB invalidation in the same API at the beginning. * 6.8 aru 09/06/18 Removed compilation warnings for ARMCC toolchain. * It fixes CR#1008309. +* 9.0 ml 03/03/23 Add description to fix doxygen warnings. * * * @note @@ -52,8 +54,12 @@ /**************************** Type Definitions *******************************/ /************************** Constant Definitions *****************************/ -#define ARM_AR_MEM_TTB_SECT_SIZE 1024*1024 -#define ARM_AR_MEM_TTB_SECT_SIZE_MASK (~(ARM_AR_MEM_TTB_SECT_SIZE-1UL)) + +#define ARM_AR_MEM_TTB_SECT_SIZE 1024*1024 /**< Each TTB descriptor + * covers a 1MB region */ +#define ARM_AR_MEM_TTB_SECT_SIZE_MASK (~(ARM_AR_MEM_TTB_SECT_SIZE-1UL)) +/**< Mask off lower bits of addr */ + /************************** Variable Definitions *****************************/ extern u32 MMUTable; @@ -65,8 +71,8 @@ extern u32 MMUTable; * @brief This function sets the memory attributes for a section covering 1MB * of memory in the translation table. * -* @param Addr: 32-bit address for which memory attributes need to be set. -* @param attrib: Attribute for the given memory region. xil_mmu.h contains +* @param Addr 32-bit address for which memory attributes need to be set. +* @param attrib Attribute for the given memory region. xil_mmu.h contains * definitions of commonly used memory attributes which can be * utilized for this function. * @@ -167,11 +173,11 @@ void Xil_DisableMMU(void) /** * @brief Memory mapping for Cortex A9 processor. * -* @param PhysAddr is physical address. -* @param size is size of region. -* @param flags is flags used to set translation table. +* @param PhysAddr is physical address. +* @param size is size of region. +* @param flags is flags used to set translation table. * -* @return Pointer to virtual address. +* @return Pointer to virtual address. * * @note: Previously this was implemented in libmetal. Move to embeddedsw as this * functionality is specific to A9 processor. diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xil_printf.c b/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xil_printf.c index bf104fd..0f718bf 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xil_printf.c +++ b/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xil_printf.c @@ -1,5 +1,6 @@ /****************************************************************************** -* Copyright (c) 1995 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (C) 1995 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (C) 2023 - 2024 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT *******************************************************************************/ /*---------------------------------------------------*/ @@ -12,24 +13,38 @@ #include "xil_printf.h" #include "xil_types.h" #include "xil_assert.h" +#include "bspconfig.h" #include #include #include -static void padding( const s32 l_flag,const struct params_s *par); +/************************** Function Prototypes ******************************/ + +static void padding( const s32 l_flag, const struct params_s *par); static void outs(const charptr lp, struct params_s *par); -static s32 getnum( charptr* linep); +static s32 getnum( charptr *linep); + +/**************************** Type Definitions *******************************/ typedef struct params_s { - s32 len; - s32 num1; - s32 num2; - char8 pad_character; - s32 do_padding; - s32 left_flag; - s32 unsigned_flag; + s32 len; /**< length */ + s32 num1; /**< number 1 */ + s32 num2; /**< number 2 */ + char8 pad_character; /**< pad character */ + s32 do_padding; /**< do padding */ + s32 left_flag; /**< left flag */ + s32 unsigned_flag; /**< unsigned flag */ } params_t; +/***************** Macros (Inline Functions) Definitions *********************/ + +#if (defined(__MICROBLAZE__)) && (!defined(__arch64__)) +#define MICROBLAZE32 +#endif + +#if (!defined(MICROBLAZE32)) && (!defined(ZYNQMP_R5_FSBL_BSP)) && (!defined(DISABLE_64BIT_PRINT)) +#define SUPPORT_64BIT_PRINT +#endif /*---------------------------------------------------*/ /* The purpose of this routine is to output data the */ @@ -40,107 +55,109 @@ typedef struct params_s { /*---------------------------------------------------*/ -/*---------------------------------------------------*/ -/* */ -/* This routine puts pad characters into the output */ -/* buffer. */ -/* */ + +/*****************************************************************************/ +/** +* This routine puts pad characters into the output buffer. +* +******************************************************************************/ static void padding( const s32 l_flag, const struct params_s *par) { - s32 i; + s32 i; - if ((par->do_padding != 0) && (l_flag != 0) && (par->len < par->num1)) { - i=(par->len); - for (; i<(par->num1); i++) { -#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM) - outbyte( par->pad_character); + if ((par->do_padding != 0) && (l_flag != 0) && (par->len < par->num1)) { + i = (par->len); + for (; i < (par->num1); i++) { +#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM) || defined(SDT) + outbyte( par->pad_character); #endif } - } + } } -/*---------------------------------------------------*/ -/* */ -/* This routine moves a string to the output buffer */ -/* as directed by the padding and positioning flags. */ -/* */ +/******************************************************************************/ +/** +* This routine moves a string to the output buffer +* as directed by the padding and positioning flags. +* +*******************************************************************************/ static void outs(const charptr lp, struct params_s *par) { - charptr LocalPtr; + charptr LocalPtr; LocalPtr = lp; - /* pad on left if needed */ - if(LocalPtr != NULL) { + /* pad on left if needed */ + if (LocalPtr != NULL) { par->len = (s32)strlen( LocalPtr); padding( !(par->left_flag), par); /* Move string to the buffer */ while (((*LocalPtr) != (char8)0) && ((par->num2) != 0)) { (par->num2)--; -#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM) +#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM) || defined(SDT) outbyte(*LocalPtr); #endif LocalPtr += 1; } + } + + /* Pad on right if needed */ + /* CR 439175 - elided next stmt. Seemed bogus. */ + padding( par->left_flag, par); } - /* Pad on right if needed */ - /* CR 439175 - elided next stmt. Seemed bogus. */ - padding( par->left_flag, par); -} - -/*---------------------------------------------------*/ -/* */ -/* This routine moves a number to the output buffer */ -/* as directed by the padding and positioning flags. */ -/* */ - +/*****************************************************************************/ +/** +* +* This routine moves a number to the output buffer +* as directed by the padding and positioning flags. +* +******************************************************************************/ static void outnum( const s32 n, const s32 base, struct params_s *par) { - s32 negative; + s32 negative; s32 i; - char8 outbuf[32]; - const char8 digits[] = "0123456789ABCDEF"; - u32 num; - for(i = 0; i<32; i++) { - outbuf[i] = '0'; - } + char8 outbuf[32]; + const char8 digits[] = "0123456789ABCDEF"; + u32 num; + for (i = 0; i < 32; i++) { + outbuf[i] = '0'; + } - /* Check if number is negative */ - if ((par->unsigned_flag == 0) && (base == 10) && (n < 0L)) { - negative = 1; - num =(-(n)); - } - else{ - num = n; - negative = 0; - } + /* Check if number is negative */ + if ((par->unsigned_flag == 0) && (base == 10) && (n < 0L)) { + negative = 1; + num = (-(n)); + } else { + num = n; + negative = 0; + } - /* Build number (backwards) in outbuf */ - i = 0; - do { + /* Build number (backwards) in outbuf */ + i = 0; + do { outbuf[i] = digits[(num % (u32)base)]; i++; num /= base; - } while (num > 0U); + } while (num > 0U); - if (negative != 0) { + if (negative != 0) { outbuf[i] = '-'; i++; } - outbuf[i] = '\0'; - i--; + outbuf[i] = '\0'; + i--; - /* Move the converted number to the buffer and */ - /* add in the padding where needed. */ - par->len = (s32)strlen(outbuf); - padding( !(par->left_flag), par); - while (&outbuf[i] >= outbuf) { -#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM) - outbyte( outbuf[i] ); + /* Move the converted number to the buffer and */ + /* add in the padding where needed. */ + par->len = (s32)strlen(outbuf); + padding( !(par->left_flag), par); + while (&outbuf[i] >= outbuf) { +#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM) || defined(SDT) + outbyte( outbuf[i] ); #endif i--; -} - padding( par->left_flag, par); + } + padding( par->left_flag, par); } /*---------------------------------------------------*/ /* */ @@ -148,96 +165,98 @@ static void outnum( const s32 n, const s32 base, struct params_s *par) /* buffer as directed by the padding and positioning */ /* flags. */ /* */ -#if defined (__aarch64__) || defined (__arch64__) +#if defined (SUPPORT_64BIT_PRINT) static void outnum1( const s64 n, const s32 base, params_t *par) { - s32 negative; + s32 negative; s32 i; - char8 outbuf[64]; - const char8 digits[] = "0123456789ABCDEF"; - u64 num; - for(i = 0; i<64; i++) { - outbuf[i] = '0'; - } + char8 outbuf[64]; + const char8 digits[] = "0123456789ABCDEF"; + u64 num; + for (i = 0; i < 64; i++) { + outbuf[i] = '0'; + } - /* Check if number is negative */ - if ((par->unsigned_flag == 0) && (base == 10) && (n < 0L)) { - negative = 1; - num =(-(n)); - } - else{ - num = (n); - negative = 0; - } + /* Check if number is negative */ + if ((par->unsigned_flag == 0) && (base == 10) && (n < 0L)) { + negative = 1; + num = (-(n)); + } else { + num = (n); + negative = 0; + } - /* Build number (backwards) in outbuf */ - i = 0; - do { + /* Build number (backwards) in outbuf */ + i = 0; + do { outbuf[i] = digits[(num % base)]; i++; num /= base; - } while (num > 0); + } while (num > 0); - if (negative != 0) { + if (negative != 0) { outbuf[i] = '-'; i++; } - outbuf[i] = '\0'; - i--; + outbuf[i] = '\0'; + i--; - /* Move the converted number to the buffer and */ - /* add in the padding where needed. */ - par->len = (s32)strlen(outbuf); - padding( !(par->left_flag), par); - while (&outbuf[i] >= outbuf) { - outbyte( outbuf[i] ); + /* Move the converted number to the buffer and */ + /* add in the padding where needed. */ + par->len = (s32)strlen(outbuf); + padding( !(par->left_flag), par); + while (&outbuf[i] >= outbuf) { + outbyte( outbuf[i] ); i--; -} - padding( par->left_flag, par); + } + padding( par->left_flag, par); } #endif -/*---------------------------------------------------*/ -/* */ -/* This routine gets a number from the format */ -/* string. */ -/* */ -static s32 getnum(charptr* linep) + +/*****************************************************************************/ +/** +* +* This routine gets a number from the format string. +* +******************************************************************************/ +static s32 getnum(charptr *linep) { s32 n = 0; s32 ResultIsDigit = 0; charptr cptr = *linep; while (cptr != NULL) { - ResultIsDigit = isdigit(((u8)*cptr)); + ResultIsDigit = isdigit(((u8) * cptr)); if (ResultIsDigit == 0) { break; } - n = ((n*10) + (((s32)*cptr) - (s32)'0')); + n = ((n * 10) + (((s32) * cptr) - (s32)'0')); cptr += 1; } *linep = ((charptr)(cptr)); - return(n); + return (n); } -/*---------------------------------------------------*/ -/* */ -/* This routine operates just like a printf/sprintf */ -/* routine. It outputs a set of data under the */ -/* control of a formatting string. Not all of the */ -/* standard C format control are supported. The ones */ -/* provided are primarily those needed for embedded */ -/* systems work. Primarily the floating point */ -/* routines are omitted. Other formats could be */ -/* added easily by following the examples shown for */ -/* the supported formats. */ -/* */ - -/* void esp_printf( const func_ptr f_ptr, - const charptr ctrl1, ...) */ +/*****************************************************************************/ +/** +* This routine operates just like a printf/sprintf +* routine. It outputs a set of data under the +* control of a formatting string. Not all of the +* standard C format control are supported. The ones +* provided are primarily those needed for embedded +* systems work. Primarily the floating point +* routines are omitted. Other formats could be +* added easily by following the examples shown for +* the supported formats. +* void esp_printf( const func_ptr f_ptr, +* const charptr ctrl1, ...) +* +*******************************************************************************/ #if defined (__aarch64__) && HYP_GUEST && EL1_NONSECURE && XEN_USE_PV_CONSOLE -void xil_printf( const char8 *ctrl1, ...){ +void xil_printf( const char8 *ctrl1, ...) +{ XPVXenConsole_Printf(ctrl1); } #else @@ -253,195 +272,205 @@ void xil_printf( const char8 *ctrl1, ...) } #endif -/* This routine is equivalent to vprintf routine */ +/*****************************************************************************/ +/** +* This routine is equivalent to vprintf routine +******************************************************************************/ void xil_vprintf(const char8 *ctrl1, va_list argp) { s32 Check; -#if defined (__aarch64__) || defined (__arch64__) - s32 long_flag; +#if defined (SUPPORT_64BIT_PRINT) + s32 long_flag; #endif - s32 dot_flag; + s32 dot_flag; + u32 width, index; + params_t par; - params_t par; + u8 ch; + char8 *ctrl = (char8 *)ctrl1; + const char *string; - u8 ch; - char8 *ctrl = (char8 *)ctrl1; + while ((ctrl != NULL) && (*ctrl != (char8)0)) { - while ((ctrl != NULL) && (*ctrl != (char8)0)) { - - /* move format string chars to buffer until a */ - /* format control is found. */ - if (*ctrl != '%') { -#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM) - outbyte(*ctrl); + /* move format string chars to buffer until a */ + /* format control is found. */ + if (*ctrl != '%') { +#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM) || defined(SDT) + outbyte(*ctrl); #endif ctrl += 1; - continue; - } + continue; + } - /* initialize all the flags for this format. */ - dot_flag = 0; -#if defined (__aarch64__) || defined (__arch64__) + /* initialize all the flags for this format. */ + dot_flag = 0; +#if defined (SUPPORT_64BIT_PRINT) long_flag = 0; #endif - par.unsigned_flag = 0; + par.unsigned_flag = 0; par.left_flag = 0; par.do_padding = 0; - par.pad_character = ' '; - par.num2=32767; - par.num1=0; - par.len=0; + par.pad_character = ' '; + par.num2 = 32767; + par.num1 = 0; + par.len = 0; - try_next: - if(ctrl != NULL) { +try_next: + if (ctrl != NULL) { ctrl += 1; } - if(ctrl != NULL) { - ch = (u8)*ctrl; + if (ctrl != NULL) { + ch = (u8) * ctrl; } else { break; } - if (isdigit(ch) != 0) { - if (dot_flag != 0) { - par.num2 = getnum(&ctrl); - } - else { - if (ch == (u8)'0') { - par.pad_character = '0'; + if (isdigit(ch) != 0) { + if (dot_flag != 0) { + par.num2 = getnum(&ctrl); + } else { + if (ch == (u8)'0') { + par.pad_character = '0'; } - if(ctrl != NULL) { - par.num1 = getnum(&ctrl); + if (ctrl != NULL) { + par.num1 = getnum(&ctrl); } - par.do_padding = 1; - } - if(ctrl != NULL) { - ctrl -= 1; + par.do_padding = 1; } - goto try_next; - } + if (ctrl != NULL) { + ctrl -= 1; + } + goto try_next; + } - switch (tolower(ch)) { - case '%': -#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM) - outbyte( '%'); + switch (tolower(ch)) { + case '%': +#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM) || defined(SDT) + outbyte( '%'); #endif - Check = 1; - break; - - case '-': - par.left_flag = 1; - Check = 0; - break; - - case '.': - dot_flag = 1; - Check = 0; - break; - - case 'l': - #if defined (__aarch64__) || defined (__arch64__) - long_flag = 1; - #endif - Check = 0; - break; - - case 'u': - par.unsigned_flag = 1; - /* fall through */ - case 'i': - case 'd': - #if defined (__aarch64__) || defined (__arch64__) - if (long_flag != 0){ - outnum1((s64)va_arg(argp, s64), 10L, &par); - } - else { - outnum( va_arg(argp, s32), 10L, &par); - } - #else - outnum( va_arg(argp, s32), 10L, &par); - #endif Check = 1; - break; - case 'p': - #if defined (__aarch64__) || defined (__arch64__) - par.unsigned_flag = 1; - outnum1((s64)va_arg(argp, s64), 16L, &par); - Check = 1; - break; - #endif - case 'X': - case 'x': - par.unsigned_flag = 1; - #if defined (__aarch64__) || defined (__arch64__) - if (long_flag != 0) { - outnum1((s64)va_arg(argp, s64), 16L, &par); + break; + + case '-': + par.left_flag = 1; + Check = 0; + break; + + case '.': + if ((*(ctrl + 1) == '*') && (*(ctrl + 2) == 's')) { + width = va_arg(argp, u32); + string = va_arg(argp, const char *); + for (index = 0; index < width && string[index] != '\0' ; index++) { + outbyte(string[index]); + } + ctrl += 2; + } else { + dot_flag = 1; + Check = 0; } - else { - outnum((s32)va_arg(argp, s32), 16L, &par); - } - #else - outnum((s32)va_arg(argp, s32), 16L, &par); - #endif - Check = 1; - break; + break; - case 's': - outs( va_arg( argp, char *), &par); - Check = 1; - break; + case 'l': +#if defined (SUPPORT_64BIT_PRINT) + long_flag = 1; +#endif + Check = 0; + break; - case 'c': -#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM) - outbyte( (char8)va_arg( argp, s32)); + case 'u': + par.unsigned_flag = 1; + /* fall through */ + case 'i': + case 'd': +#if defined (SUPPORT_64BIT_PRINT) + if (long_flag != 0) { + outnum1((s64)va_arg(argp, s64), 10L, &par); + } else { + outnum( va_arg(argp, s32), 10L, &par); + } +#else + outnum( va_arg(argp, s32), 10L, &par); #endif - Check = 1; - break; + Check = 1; + break; + case 'p': +#if defined (__aarch64__) || defined (__arch64__) + par.unsigned_flag = 1; + outnum1((s64)va_arg(argp, s64), 16L, &par); + Check = 1; + break; +#endif + case 'X': + case 'x': + par.unsigned_flag = 1; +#if defined (SUPPORT_64BIT_PRINT) + if (long_flag != 0) { + outnum1((s64)va_arg(argp, s64), 16L, &par); + } else { + outnum((s32)va_arg(argp, s32), 16L, &par); + } +#else + outnum((s32)va_arg(argp, s32), 16L, &par); +#endif + Check = 1; + break; - case '\\': - switch (*ctrl) { - case 'a': -#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM) - outbyte( ((char8)0x07)); -#endif - break; - case 'h': -#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM) - outbyte( ((char8)0x08)); -#endif - break; - case 'r': -#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM) - outbyte( ((char8)0x0D)); -#endif - break; - case 'n': -#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM) - outbyte( ((char8)0x0D)); - outbyte( ((char8)0x0A)); -#endif - break; - default: -#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM) - outbyte( *ctrl); -#endif - break; - } - ctrl += 1; - Check = 0; - break; + case 's': + outs( va_arg( argp, char *), &par); + Check = 1; + break; - default: - Check = 1; - break; - } - if(Check == 1) { - if(ctrl != NULL) { + case 'c': +#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM) || defined(SDT) + outbyte( (char8)va_arg( argp, s32)); +#endif + Check = 1; + break; + + case '\\': + switch (*ctrl) { + case 'a': +#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM) || defined(SDT) + outbyte( ((char8)0x07)); +#endif + break; + case 'h': +#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM) || defined(SDT) + outbyte( ((char8)0x08)); +#endif + break; + case 'r': +#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM) || defined(SDT) + outbyte( ((char8)0x0D)); +#endif + break; + case 'n': +#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM) || defined(SDT) + outbyte( ((char8)0x0D)); + outbyte( ((char8)0x0A)); +#endif + break; + default: +#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM) || defined(SDT) + outbyte( *ctrl); +#endif + break; + } + ctrl += 1; + Check = 0; + break; + + default: + Check = 1; + break; + } + if (Check == 1) { + if (ctrl != NULL) { ctrl += 1; } - continue; - } - goto try_next; - } + continue; + } + goto try_next; + } } /*---------------------------------------------------*/ diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xil_printf.h b/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xil_printf.h index 062ad6b..c69af0f 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xil_printf.h +++ b/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xil_printf.h @@ -1,5 +1,6 @@ /****************************************************************************** -* Copyright (c) 1995 - 2021 Xilinx, Inc. All rights reserved. +* Copyright (C) 1995 - 2021 Xilinx, Inc. All rights reserved. +* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT *******************************************************************************/ #ifndef XIL_PRINTF_H @@ -13,8 +14,10 @@ extern "C" { #include #include #include "xil_types.h" -#include "xparameters.h" #include "bspconfig.h" +#ifndef SDT +#include "xparameters.h" +#endif #if defined (__aarch64__) && HYP_GUEST && EL1_NONSECURE && XEN_USE_PV_CONSOLE #include "xen_console.h" #endif @@ -38,13 +41,14 @@ struct params_s; typedef char8* charptr; typedef s32 (*func_ptr)(int c); -/* */ - +/************************** Function Prototypes ******************************/ +/**< prints the statement */ void xil_printf( const char8 *ctrl1, ...); +/**< This routine is equivalent to vprintf routine */ void xil_vprintf(const char8 *ctrl1, va_list argp); void print( const char8 *ptr); -extern void outbyte (char c); -extern char inbyte(void); +extern void outbyte (char c); /**< To send byte */ +extern char inbyte(void); /**< To receive byte */ #ifdef __cplusplus } diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xil_sleepcommon.c b/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xil_sleepcommon.c index aba3a08..f4322db 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xil_sleepcommon.c +++ b/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xil_sleepcommon.c @@ -1,5 +1,6 @@ /****************************************************************************** * Copyright (c) 2017 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -21,6 +22,7 @@ * violation. * 8.0 sk 03/02/22 Update usleep argument type to fix misra_c_2012_ * directive_4_6 violation. +* 9.1 mus 10/24/23 Add support for RISC-V. * ******************************************************************************/ @@ -52,6 +54,8 @@ sleep_A53(seconds); #elif defined (__MICROBLAZE__) sleep_MB(seconds); +#elif defined (__riscv) + sleep_riscv(seconds); #else sleep_A9(seconds); #endif @@ -78,6 +82,8 @@ usleep_A53(useconds); #elif defined (__MICROBLAZE__) usleep_MB(useconds); +#elif defined (__riscv) + usleep_riscv(useconds); #else usleep_A9(useconds); #endif diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xil_sleeptimer.h b/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xil_sleeptimer.h index b133eaf..adcb7e6 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xil_sleeptimer.h +++ b/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xil_sleeptimer.h @@ -1,5 +1,6 @@ /****************************************************************************** -* Copyright (c) 2017 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (C) 2017 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -24,7 +25,7 @@ * misra_c_2012_rule_12_1 violation. * 7.7 sk 01/10/22 Add void to XTime_StartTTCTimer function declaration * to fix misra_c_2012_rule_8_2 violation. -* +* 9.0 ml 03/03/23 Add description to fix doxygen warnings. * *****************************************************************************/ @@ -103,8 +104,12 @@ extern "C" { */ /************************** Function Prototypes ******************************/ +/**< This is a helper function used by sleep/usleep APIs to +* have delay in sec/usec */ void Xil_SleepTTCCommon(u32 delay, u64 frequency); -void XTime_StartTTCTimer(void); + +void XTime_StartTTCTimer(void); /**< This API starts the Triple + * Timer Counter */ #endif diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xil_spinlock.h b/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xil_spinlock.h index 0cdf288..b61d7d3 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xil_spinlock.h +++ b/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xil_spinlock.h @@ -1,5 +1,6 @@ /****************************************************************************** -* Copyright (c) 2021 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (C) 2021 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -23,12 +24,13 @@ * if condition to fix misrac violations. * 7.7 sk 01/10/22 Update XIL_SPINLOCK_ENABLED from signed to unsigned to * fix misra_c_2012_rule_10_4 violation. +* 9.0 ml 03/03/23 Add description to fix doxygen warnings. * * ******************************************************************************/ -#ifndef XIL_SPINLOCK_H /* prevent circular inclusions */ -#define XIL_SPINLOCK_H /* by using protection macros */ +#ifndef XIL_SPINLOCK_H /**< prevent circular inclusions */ +#define XIL_SPINLOCK_H /**< by using protection macros */ /***************************** Include Files ********************************/ #include "xil_types.h" @@ -61,7 +63,8 @@ u32 Xil_IsSpinLockEnabled(void); if(Xil_IsSpinLockEnabled()!=(u32)0) { \ Xil_SpinLock(); } #else -#define XIL_SPINLOCK() +#define XIL_SPINLOCK() /**< protect multiple applications running at separate + * CPUs to write to the same register */ #endif /* !(__aarch64__) && (__GNUC__) && !(__clang__)*/ #if !defined (__aarch64__) && defined(__GNUC__) && !defined(__clang__) @@ -69,7 +72,7 @@ u32 Xil_IsSpinLockEnabled(void); if(Xil_IsSpinLockEnabled()!=(u32)0) { \ Xil_SpinUnlock(); } #else -#define XIL_SPINUNLOCK() +#define XIL_SPINUNLOCK() /**< Release the lock previously taken */ #endif /* !(__aarch64__) && (__GNUC__) && !(__clang__)*/ diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xil_testio.c b/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xil_testio.c index c05acd9..0fe1204 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xil_testio.c +++ b/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xil_testio.c @@ -1,5 +1,6 @@ /****************************************************************************** * Copyright (c) 2009 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -16,6 +17,7 @@ * Ver Who Date Changes * ----- ---- -------- ----------------------------------------------- * 1.00a hbm 08/25/09 First release +* 9.00 ml 04/26/23 Updated code to fix sizeof_mismatch coverity warnings. * * *****************************************************************************/ @@ -90,9 +92,9 @@ s32 Xil_TestIO8(u8 *Addr, s32 Length, u8 Value) s32 Status = 0; for (Index = 0; Index < Length; Index++) { - Xil_Out8((INTPTR)Addr, Value); + Xil_Out8((UINTPTR)Addr, Value); - ValueIn = Xil_In8((INTPTR)Addr); + ValueIn = Xil_In8((UINTPTR)Addr); if ((Value != ValueIn) && (Status == 0)) { Status = -1; @@ -134,23 +136,24 @@ s32 Xil_TestIO16(u16 *Addr, s32 Length, u16 Value, s32 Kind, s32 Swap) u16 *TempAddr16; u16 ValueIn = 0U; s32 Index; + u32 Size_16; TempAddr16 = Addr; Xil_AssertNonvoid(TempAddr16 != NULL); for (Index = 0; Index < Length; Index++) { switch (Kind) { - case XIL_TESTIO_LE: - Xil_Out16LE((INTPTR)TempAddr16, Value); - break; - case XIL_TESTIO_BE: - Xil_Out16BE((INTPTR)TempAddr16, Value); - break; - default: - Xil_Out16((INTPTR)TempAddr16, Value); - break; + case XIL_TESTIO_LE: + Xil_Out16LE((UINTPTR)TempAddr16, Value); + break; + case XIL_TESTIO_BE: + Xil_Out16BE((UINTPTR)TempAddr16, Value); + break; + default: + Xil_Out16((UINTPTR)TempAddr16, Value); + break; } - ValueIn = Xil_In16((INTPTR)TempAddr16); + ValueIn = Xil_In16((UINTPTR)TempAddr16); if ((Kind != 0) && (Swap != 0)) { ValueIn = Swap16(ValueIn); @@ -161,18 +164,18 @@ s32 Xil_TestIO16(u16 *Addr, s32 Length, u16 Value, s32 Kind, s32 Swap) } /* second round */ - Xil_Out16((INTPTR)TempAddr16, Value); + Xil_Out16((UINTPTR)TempAddr16, Value); switch (Kind) { - case XIL_TESTIO_LE: - ValueIn = Xil_In16LE((INTPTR)TempAddr16); - break; - case XIL_TESTIO_BE: - ValueIn = Xil_In16BE((INTPTR)TempAddr16); - break; - default: - ValueIn = Xil_In16((INTPTR)TempAddr16); - break; + case XIL_TESTIO_LE: + ValueIn = Xil_In16LE((UINTPTR)TempAddr16); + break; + case XIL_TESTIO_BE: + ValueIn = Xil_In16BE((UINTPTR)TempAddr16); + break; + default: + ValueIn = Xil_In16((UINTPTR)TempAddr16); + break; } @@ -183,7 +186,8 @@ s32 Xil_TestIO16(u16 *Addr, s32 Length, u16 Value, s32 Kind, s32 Swap) if (Value != ValueIn) { return -1; } - TempAddr16 += sizeof(u16); + Size_16 = sizeof(u16); + TempAddr16 += Size_16; } return 0; } @@ -218,23 +222,24 @@ s32 Xil_TestIO32(u32 *Addr, s32 Length, u32 Value, s32 Kind, s32 Swap) u32 *TempAddr; u32 ValueIn = 0U; s32 Index; + u32 Size_32; TempAddr = Addr; Xil_AssertNonvoid(TempAddr != NULL); for (Index = 0; Index < Length; Index++) { switch (Kind) { - case XIL_TESTIO_LE: - Xil_Out32LE((INTPTR)TempAddr, Value); - break; - case XIL_TESTIO_BE: - Xil_Out32BE((INTPTR)TempAddr, Value); - break; - default: - Xil_Out32((INTPTR)TempAddr, Value); - break; + case XIL_TESTIO_LE: + Xil_Out32LE((UINTPTR)TempAddr, Value); + break; + case XIL_TESTIO_BE: + Xil_Out32BE((UINTPTR)TempAddr, Value); + break; + default: + Xil_Out32((UINTPTR)TempAddr, Value); + break; } - ValueIn = Xil_In32((INTPTR)TempAddr); + ValueIn = Xil_In32((UINTPTR)TempAddr); if ((Kind != 0) && (Swap != 0)) { ValueIn = Swap32(ValueIn); @@ -245,19 +250,19 @@ s32 Xil_TestIO32(u32 *Addr, s32 Length, u32 Value, s32 Kind, s32 Swap) } /* second round */ - Xil_Out32((INTPTR)TempAddr, Value); + Xil_Out32((UINTPTR)TempAddr, Value); switch (Kind) { - case XIL_TESTIO_LE: - ValueIn = Xil_In32LE((INTPTR)TempAddr); - break; - case XIL_TESTIO_BE: - ValueIn = Xil_In32BE((INTPTR)TempAddr); - break; - default: - ValueIn = Xil_In32((INTPTR)TempAddr); - break; + case XIL_TESTIO_LE: + ValueIn = Xil_In32LE((UINTPTR)TempAddr); + break; + case XIL_TESTIO_BE: + ValueIn = Xil_In32BE((UINTPTR)TempAddr); + break; + default: + ValueIn = Xil_In32((UINTPTR)TempAddr); + break; } if ((Kind != 0) && (Swap != 0)) { @@ -267,7 +272,8 @@ s32 Xil_TestIO32(u32 *Addr, s32 Length, u32 Value, s32 Kind, s32 Swap) if (Value != ValueIn) { return -1; } - TempAddr += sizeof(u32); + Size_32 = sizeof(u32); + TempAddr += Size_32; } return 0; } diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xil_testmem.c b/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xil_testmem.c index aaa0617..7c35553 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xil_testmem.c +++ b/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xil_testmem.c @@ -1,5 +1,6 @@ /****************************************************************************** * Copyright (c) 2009 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (C) 2022 - 2024 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -34,6 +35,10 @@ * 21_2 violation. * 7.7 sk 01/10/22 Remove arithematic operations on pointer varaible to fix * misra_c_2012_rule_18_4 violation. +* 9.0 ml 08/30/23 Update Memory tests API in BSP, to not to stress test by + default. +* 9.1 ml 02/02/23 Fix compilation warnings report with +* XIL_ENABLE_MEMORY_STRESS_TEST * * *****************************************************************************/ @@ -46,7 +51,9 @@ /************************** Constant Definitions ****************************/ /************************** Function Prototypes *****************************/ +#ifdef XIL_ENABLE_MEMORY_STRESS_TEST static u32 RotateLeft(u32 Input, u8 Width); +#endif /* define ROTATE_RIGHT to give access to this functionality */ #ifdef ROTATE_RIGHT @@ -86,11 +93,15 @@ static u32 RotateRight(u32 Input, u8 Width); s32 Xil_TestMem8(u32 Addrlow, u32 Addrhigh, u32 Words, u8 Pattern, u8 Subtest) { u32 I; - u32 j; u8 Val; u8 WordMem8; s32 Status = 0; u64 Addr = (Addrlow + ((u64)Addrhigh << 32)); +#ifdef XIL_ENABLE_MEMORY_STRESS_TEST + u32 j; +#else + (void)Pattern; +#endif Xil_AssertNonvoid(Words != (u32)0); Xil_AssertNonvoid(Subtest <= XIL_TESTMEM_MAXTEST); @@ -104,14 +115,14 @@ s32 Xil_TestMem8(u32 Addrlow, u32 Addrhigh, u32 Words, u8 Pattern, u8 Subtest) * select the proper Subtest(s) */ - if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) { + if ((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) { /* * Fill the memory with incrementing * values starting from XIL_TESTMEM_INIT_VALUE */ for (I = 0U; I < Words; I++) { /* write memory location */ - sbea(Addr+I, Val); + sbea(Addr + I, Val); Val++; } /* @@ -128,7 +139,7 @@ s32 Xil_TestMem8(u32 Addrlow, u32 Addrhigh, u32 Words, u8 Pattern, u8 Subtest) for (I = 0U; I < Words; I++) { /* read memory location */ - WordMem8 = lbuea(Addr+I); + WordMem8 = lbuea(Addr + I); if (WordMem8 != Val) { Status = -1; goto End_Label; @@ -136,8 +147,8 @@ s32 Xil_TestMem8(u32 Addrlow, u32 Addrhigh, u32 Words, u8 Pattern, u8 Subtest) Val++; } } - - if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) { +#ifdef XIL_ENABLE_MEMORY_STRESS_TEST + if ((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) { /* * set up to cycle through all possible initial * test Patterns for walking ones test @@ -155,7 +166,7 @@ s32 Xil_TestMem8(u32 Addrlow, u32 Addrhigh, u32 Words, u8 Pattern, u8 Subtest) */ for (I = 0U; I < NUM_OF_BITS_IN_BYTE; I++) { /* write memory location */ - sbea(Addr+I, Val); + sbea(Addr + I, Val); Val = (u8)RotateLeft(Val, 8U); } /* @@ -166,7 +177,7 @@ s32 Xil_TestMem8(u32 Addrlow, u32 Addrhigh, u32 Words, u8 Pattern, u8 Subtest) /* Read the values from each location that was written */ for (I = 0U; I < NUM_OF_BITS_IN_BYTE; I++) { /* read memory location */ - WordMem8 = lbuea(Addr+I); + WordMem8 = lbuea(Addr + I); if (WordMem8 != Val) { Status = -1; goto End_Label; @@ -176,7 +187,7 @@ s32 Xil_TestMem8(u32 Addrlow, u32 Addrhigh, u32 Words, u8 Pattern, u8 Subtest) } } - if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) { + if ((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) { /* * set up to cycle through all possible initial test * Patterns for walking zeros test @@ -194,7 +205,7 @@ s32 Xil_TestMem8(u32 Addrlow, u32 Addrhigh, u32 Words, u8 Pattern, u8 Subtest) */ for (I = 0U; I < NUM_OF_BITS_IN_BYTE; I++) { /* write memory location */ - sbea(Addr+I, Val); + sbea(Addr + I, Val); Val = ~((u8)RotateLeft(~Val, NUM_OF_BITS_IN_BYTE)); } /* @@ -205,7 +216,7 @@ s32 Xil_TestMem8(u32 Addrlow, u32 Addrhigh, u32 Words, u8 Pattern, u8 Subtest) /* Read the values from each location that was written */ for (I = 0U; I < NUM_OF_BITS_IN_BYTE; I++) { /* read memory location */ - WordMem8 = lbuea(Addr+I); + WordMem8 = lbuea(Addr + I); if (WordMem8 != Val) { Status = -1; goto End_Label; @@ -216,12 +227,12 @@ s32 Xil_TestMem8(u32 Addrlow, u32 Addrhigh, u32 Words, u8 Pattern, u8 Subtest) } } - if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) { + if ((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) { /* Fill the memory with inverse of address */ for (I = 0U; I < Words; I++) { /* write memory location */ Val = (u8) (~((INTPTR) (Addr + I))); - sbea(Addr+I, Val); + sbea(Addr + I, Val); } /* @@ -231,8 +242,8 @@ s32 Xil_TestMem8(u32 Addrlow, u32 Addrhigh, u32 Words, u8 Pattern, u8 Subtest) for (I = 0U; I < Words; I++) { /* read memory location */ - WordMem8 = lbuea(Addr+I); - Val = (u8) (~((INTPTR) (Addr+I))); + WordMem8 = lbuea(Addr + I); + Val = (u8) (~((INTPTR) (Addr + I))); if ((WordMem8 ^ Val) != 0x00U) { Status = -1; goto End_Label; @@ -240,7 +251,7 @@ s32 Xil_TestMem8(u32 Addrlow, u32 Addrhigh, u32 Words, u8 Pattern, u8 Subtest) } } - if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) { + if ((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) { /* * Generate an initial value for * memory testing @@ -248,8 +259,7 @@ s32 Xil_TestMem8(u32 Addrlow, u32 Addrhigh, u32 Words, u8 Pattern, u8 Subtest) if (Pattern == (u8)0) { Val = 0xA5U; - } - else { + } else { Val = Pattern; } /* @@ -257,7 +267,7 @@ s32 Xil_TestMem8(u32 Addrlow, u32 Addrhigh, u32 Words, u8 Pattern, u8 Subtest) */ for (I = 0U; I < Words; I++) { /* write memory location */ - sbea(Addr+I, Val); + sbea(Addr + I, Val); } /* * Check every word within the words @@ -267,14 +277,14 @@ s32 Xil_TestMem8(u32 Addrlow, u32 Addrhigh, u32 Words, u8 Pattern, u8 Subtest) for (I = 0U; I < Words; I++) { /* read memory location */ - WordMem8 = lbuea(Addr+I); + WordMem8 = lbuea(Addr + I); if (WordMem8 != Val) { Status = -1; goto End_Label; } } } - +#endif End_Label: return Status; } @@ -308,14 +318,18 @@ End_Label: * patterns used not to repeat over the region tested. * *****************************************************************************/ -s32 Xil_TestMem16(u32 Addrlow,u32 Addrhigh, u32 Words, u16 Pattern, u8 Subtest) +s32 Xil_TestMem16(u32 Addrlow, u32 Addrhigh, u32 Words, u16 Pattern, u8 Subtest) { u32 I; - u32 j; u16 Val; u16 WordMem16; s32 Status = 0; u64 Addr = (Addrlow + ((u64)Addrhigh << 32)); +#ifdef XIL_ENABLE_MEMORY_STRESS_TEST + u32 j; +#else + (void)Pattern; +#endif Xil_AssertNonvoid(Words != (u32)0); Xil_AssertNonvoid(Subtest <= XIL_TESTMEM_MAXTEST); @@ -329,14 +343,14 @@ s32 Xil_TestMem16(u32 Addrlow,u32 Addrhigh, u32 Words, u16 Pattern, u8 Subtest) * selectthe proper Subtest(s) */ - if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) { + if ((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) { /* * Fill the memory with incrementing * values starting from 'XIL_TESTMEM_INIT_VALUE' */ for (I = 0U; I < (NUM_OF_BYTES_IN_HW * Words);) { /* write memory location */ - shea(Addr+I, Val); + shea(Addr + I, Val); Val++; I = I + NUM_OF_BYTES_IN_HW; } @@ -355,7 +369,7 @@ s32 Xil_TestMem16(u32 Addrlow,u32 Addrhigh, u32 Words, u16 Pattern, u8 Subtest) for (I = 0U; I < (NUM_OF_BYTES_IN_HW * Words);) { /* read memory location */ - WordMem16 = lhuea(Addr+I); + WordMem16 = lhuea(Addr + I); if (WordMem16 != Val) { Status = -1; goto End_Label; @@ -364,8 +378,8 @@ s32 Xil_TestMem16(u32 Addrlow,u32 Addrhigh, u32 Words, u16 Pattern, u8 Subtest) I = I + NUM_OF_BYTES_IN_HW; } } - - if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) { +#ifdef XIL_ENABLE_MEMORY_STRESS_TEST + if ((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) { /* * set up to cycle through all possible initial test * Patterns for walking ones test @@ -385,7 +399,7 @@ s32 Xil_TestMem16(u32 Addrlow,u32 Addrhigh, u32 Words, u16 Pattern, u8 Subtest) for (I = 0U; I < (NUM_OF_BYTES_IN_HW * NUM_OF_BITS_IN_HW); ) { /* write memory location */ - shea(Addr+I,Val); + shea(Addr + I, Val); Val = (u16)RotateLeft(Val, 16U); I = I + NUM_OF_BYTES_IN_HW; } @@ -397,7 +411,7 @@ s32 Xil_TestMem16(u32 Addrlow,u32 Addrhigh, u32 Words, u16 Pattern, u8 Subtest) /* Read the values from each location that was written */ for (I = 0U; I < (NUM_OF_BYTES_IN_HW * NUM_OF_BITS_IN_HW); ) { /* read memory location */ - WordMem16 = lhuea(Addr+I); + WordMem16 = lhuea(Addr + I); if (WordMem16 != Val) { Status = -1; goto End_Label; @@ -408,7 +422,7 @@ s32 Xil_TestMem16(u32 Addrlow,u32 Addrhigh, u32 Words, u16 Pattern, u8 Subtest) } } - if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) { + if ((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) { /* * set up to cycle through all possible initial * test Patterns for walking zeros test @@ -428,7 +442,7 @@ s32 Xil_TestMem16(u32 Addrlow,u32 Addrhigh, u32 Words, u16 Pattern, u8 Subtest) */ for (I = 0U; I < (NUM_OF_BYTES_IN_HW * NUM_OF_BITS_IN_HW);) { - shea(Addr+I, Val); + shea(Addr + I, Val); Val = ~((u16)RotateLeft(~Val, 16U)); I = I + NUM_OF_BYTES_IN_HW; } @@ -439,7 +453,7 @@ s32 Xil_TestMem16(u32 Addrlow,u32 Addrhigh, u32 Words, u16 Pattern, u8 Subtest) Val = ~(1U << j); /* Read the values from each location that was written */ for (I = 0U; I < (NUM_OF_BYTES_IN_HW * NUM_OF_BITS_IN_HW); ) { - WordMem16= lhuea(Addr+I); + WordMem16 = lhuea(Addr + I); if (WordMem16 != Val) { Status = -1; goto End_Label; @@ -451,12 +465,12 @@ s32 Xil_TestMem16(u32 Addrlow,u32 Addrhigh, u32 Words, u16 Pattern, u8 Subtest) } } - if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) { + if ((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) { /* Fill the memory with inverse of address */ for (I = 0U; I < (NUM_OF_BYTES_IN_HW * Words);) { /* write memory location */ - Val = (u16) (~((INTPTR)((Addr+I)))); - shea(Addr+I, Val); + Val = (u16) (~((INTPTR)((Addr + I)))); + shea(Addr + I, Val); I = I + NUM_OF_BYTES_IN_HW; } /* @@ -464,10 +478,10 @@ s32 Xil_TestMem16(u32 Addrlow,u32 Addrhigh, u32 Words, u16 Pattern, u8 Subtest) * of tested memory */ - for (I = 0U; I < (NUM_OF_BYTES_IN_HW*Words); ) { + for (I = 0U; I < (NUM_OF_BYTES_IN_HW * Words); ) { /* read memory location */ - WordMem16 = lhuea(Addr+I); - Val = (u16) (~((INTPTR) ((Addr+I)))); + WordMem16 = lhuea(Addr + I); + Val = (u16) (~((INTPTR) ((Addr + I)))); if ((WordMem16 ^ Val) != 0x0000U) { Status = -1; goto End_Label; @@ -476,15 +490,14 @@ s32 Xil_TestMem16(u32 Addrlow,u32 Addrhigh, u32 Words, u16 Pattern, u8 Subtest) } } - if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) { + if ((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) { /* * Generate an initial value for * memory testing */ if (Pattern == (u16)0) { Val = 0xDEADU; - } - else { + } else { Val = Pattern; } @@ -492,9 +505,9 @@ s32 Xil_TestMem16(u32 Addrlow,u32 Addrhigh, u32 Words, u16 Pattern, u8 Subtest) * Fill the memory with fixed pattern */ - for (I = 0U; I < (2*Words);) { + for (I = 0U; I < (2 * Words);) { /* write memory location */ - shea(Addr+I, Val); + shea(Addr + I, Val); I = I + NUM_OF_BYTES_IN_HW; } @@ -506,7 +519,7 @@ s32 Xil_TestMem16(u32 Addrlow,u32 Addrhigh, u32 Words, u16 Pattern, u8 Subtest) for (I = 0U; I < (NUM_OF_BYTES_IN_HW * Words);) { /* read memory location */ - WordMem16=lhuea(Addr+I); + WordMem16 = lhuea(Addr + I); if (WordMem16 != Val) { Status = -1; goto End_Label; @@ -514,6 +527,7 @@ s32 Xil_TestMem16(u32 Addrlow,u32 Addrhigh, u32 Words, u16 Pattern, u8 Subtest) I = I + NUM_OF_BYTES_IN_HW; } } +#endif End_Label: return Status; } @@ -549,11 +563,15 @@ End_Label: s32 Xil_TestMem32(u32 Addrlow, u32 Addrhigh, u32 Words, u32 Pattern, u8 Subtest) { u32 I; - u32 j; u32 Val; u32 WordMem32; s32 Status = 0; u64 Addr = (Addrlow + ((u64)Addrhigh << 32)); +#ifdef XIL_ENABLE_MEMORY_STRESS_TEST + u32 j; +#else + (void)Pattern; +#endif Xil_AssertNonvoid(Words != (u32)0); Xil_AssertNonvoid(Subtest <= (u8)XIL_TESTMEM_MAXTEST); @@ -564,13 +582,13 @@ s32 Xil_TestMem32(u32 Addrlow, u32 Addrhigh, u32 Words, u32 Pattern, u8 Subtest) Val = XIL_TESTMEM_INIT_VALUE; - if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) { + if ((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) { /* * Fill the memory with incrementing * values starting from 'XIL_TESTMEM_INIT_VALUE' */ - for (I = 0U; I <(NUM_OF_BYTES_IN_WORD * Words);) { - swea(Addr+I, Val); + for (I = 0U; I < (NUM_OF_BYTES_IN_WORD * Words);) { + swea(Addr + I, Val); Val++; I = I + NUM_OF_BYTES_IN_WORD; } @@ -589,7 +607,7 @@ s32 Xil_TestMem32(u32 Addrlow, u32 Addrhigh, u32 Words, u32 Pattern, u8 Subtest) */ for (I = 0U; I < ( NUM_OF_BYTES_IN_WORD * Words);) { - WordMem32 = lwea(Addr+I); + WordMem32 = lwea(Addr + I); if (WordMem32 != Val) { Status = -1; @@ -600,8 +618,8 @@ s32 Xil_TestMem32(u32 Addrlow, u32 Addrhigh, u32 Words, u32 Pattern, u8 Subtest) I = I + NUM_OF_BYTES_IN_WORD; } } - - if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) { +#ifdef XIL_ENABLE_MEMORY_STRESS_TEST + if ((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) { /* * set up to cycle through all possible initial * test Patterns for walking ones test @@ -622,7 +640,7 @@ s32 Xil_TestMem32(u32 Addrlow, u32 Addrhigh, u32 Words, u32 Pattern, u8 Subtest) for (I = 0U; I < (NUM_OF_BYTES_IN_WORD * NUM_OF_BITS_IN_WORD);) { /* write memory location */ - swea(Addr+I, Val); + swea(Addr + I, Val); Val = (u32) RotateLeft(Val, NUM_OF_BITS_IN_WORD); I = I + NUM_OF_BYTES_IN_WORD; } @@ -638,7 +656,7 @@ s32 Xil_TestMem32(u32 Addrlow, u32 Addrhigh, u32 Words, u32 Pattern, u8 Subtest) for (I = 0U; I < ((u32)32 * NUM_OF_BYTES_IN_WORD);) { /* read memory location */ - WordMem32 = lwea(Addr+I); + WordMem32 = lwea(Addr + I); if (WordMem32 != Val) { Status = -1; @@ -651,7 +669,7 @@ s32 Xil_TestMem32(u32 Addrlow, u32 Addrhigh, u32 Words, u32 Pattern, u8 Subtest) } } - if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) { + if ((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) { /* * set up to cycle through all possible * initial test Patterns for walking zeros test @@ -673,7 +691,7 @@ s32 Xil_TestMem32(u32 Addrlow, u32 Addrhigh, u32 Words, u32 Pattern, u8 Subtest) for (I = 0U; I < (NUM_OF_BITS_IN_WORD * NUM_OF_BYTES_IN_WORD);) { /* write memory location */ - swea(Addr+I, Val); + swea(Addr + I, Val); Val = ~((u32)RotateLeft(~Val, NUM_OF_BITS_IN_WORD)); I = I + NUM_OF_BYTES_IN_WORD; } @@ -689,7 +707,7 @@ s32 Xil_TestMem32(u32 Addrlow, u32 Addrhigh, u32 Words, u32 Pattern, u8 Subtest) * written */ for (I = 0U; I < (NUM_OF_BITS_IN_WORD * NUM_OF_BYTES_IN_WORD);) { /* read memory location */ - WordMem32 = lwea(Addr+I); + WordMem32 = lwea(Addr + I); if (WordMem32 != Val) { Status = -1; goto End_Label; @@ -701,12 +719,12 @@ s32 Xil_TestMem32(u32 Addrlow, u32 Addrhigh, u32 Words, u32 Pattern, u8 Subtest) } } - if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) { + if ((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) { /* Fill the memory with inverse of address */ for (I = 0U; I < (NUM_OF_BYTES_IN_WORD * Words);) { /* write memory location */ - Val = (u32) (~((INTPTR) (Addr+I))); - swea(Addr+I, Val); + Val = (u32) (~((INTPTR) (Addr + I))); + swea(Addr + I, Val); I = I + NUM_OF_BYTES_IN_WORD; } @@ -717,8 +735,8 @@ s32 Xil_TestMem32(u32 Addrlow, u32 Addrhigh, u32 Words, u32 Pattern, u8 Subtest) for (I = 0U; I < (NUM_OF_BYTES_IN_WORD * Words);) { /* Read the location */ - WordMem32 = lwea(Addr+I); - Val = (u32) (~((INTPTR) (Addr+I))); + WordMem32 = lwea(Addr + I); + Val = (u32) (~((INTPTR) (Addr + I))); if ((WordMem32 ^ Val) != 0x00000000U) { Status = -1; @@ -728,7 +746,7 @@ s32 Xil_TestMem32(u32 Addrlow, u32 Addrhigh, u32 Words, u32 Pattern, u8 Subtest) } } - if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) { + if ((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) { /* * Generate an initial value for * memory testing @@ -736,8 +754,7 @@ s32 Xil_TestMem32(u32 Addrlow, u32 Addrhigh, u32 Words, u32 Pattern, u8 Subtest) if (Pattern == (u32)0) { Val = 0xDEADBEEFU; - } - else { + } else { Val = Pattern; } @@ -747,7 +764,7 @@ s32 Xil_TestMem32(u32 Addrlow, u32 Addrhigh, u32 Words, u32 Pattern, u8 Subtest) for (I = 0U; I < (NUM_OF_BYTES_IN_WORD * Words);) { /* write memory location */ - swea(Addr+I, Val); + swea(Addr + I, Val); I = I + NUM_OF_BYTES_IN_WORD; } @@ -761,7 +778,7 @@ s32 Xil_TestMem32(u32 Addrlow, u32 Addrhigh, u32 Words, u32 Pattern, u8 Subtest) /* read memory location */ - WordMem32 = lwea(Addr+I); + WordMem32 = lwea(Addr + I); if (WordMem32 != Val) { Status = -1; goto End_Label; @@ -769,7 +786,7 @@ s32 Xil_TestMem32(u32 Addrlow, u32 Addrhigh, u32 Words, u32 Pattern, u8 Subtest) I = I + NUM_OF_BYTES_IN_WORD; } } - +#endif End_Label: return Status; } @@ -805,11 +822,15 @@ End_Label: s32 Xil_TestMem32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest) { u32 i; - u32 j; u32 Val; u32 FirtVal; u32 WordMem32; s32 Status = 0; +#ifdef XIL_ENABLE_MEMORY_STRESS_TEST + u32 j; +#else + (void)Pattern; +#endif Xil_AssertNonvoid(Words != (u32)0); Xil_AssertNonvoid(Subtest <= (u8)XIL_TESTMEM_MAXTEST); @@ -821,7 +842,7 @@ s32 Xil_TestMem32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest) FirtVal = XIL_TESTMEM_INIT_VALUE; - if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) { + if ((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) { /* * Fill the memory with incrementing * values starting from 'FirtVal' @@ -855,8 +876,8 @@ s32 Xil_TestMem32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest) Val++; } } - - if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) { +#ifdef XIL_ENABLE_MEMORY_STRESS_TEST + if ((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) { /* * set up to cycle through all possible initial * test Patterns for walking ones test @@ -904,7 +925,7 @@ s32 Xil_TestMem32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest) } } - if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) { + if ((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) { /* * set up to cycle through all possible * initial test Patterns for walking zeros test @@ -952,7 +973,7 @@ s32 Xil_TestMem32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest) } } - if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) { + if ((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) { /* Fill the memory with inverse of address */ for (i = 0U; i < Words; i++) { /* write memory location */ @@ -977,7 +998,7 @@ s32 Xil_TestMem32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest) } } - if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) { + if ((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) { /* * Generate an initial value for * memory testing @@ -985,8 +1006,7 @@ s32 Xil_TestMem32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest) if (Pattern == (u32)0) { Val = 0xDEADBEEFU; - } - else { + } else { Val = Pattern; } @@ -1016,7 +1036,7 @@ s32 Xil_TestMem32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest) } } } - +#endif End_Label: return Status; } @@ -1051,11 +1071,15 @@ End_Label: s32 Xil_TestMem16(u16 *Addr, u32 Words, u16 Pattern, u8 Subtest) { u32 i; - u32 j; u16 Val; u16 FirtVal; u16 WordMem16; s32 Status = 0; +#ifdef XIL_ENABLE_MEMORY_STRESS_TEST + u32 j; +#else + (void)Pattern; +#endif Xil_AssertNonvoid(Words != (u32)0); Xil_AssertNonvoid(Subtest <= XIL_TESTMEM_MAXTEST); @@ -1070,7 +1094,7 @@ s32 Xil_TestMem16(u16 *Addr, u32 Words, u16 Pattern, u8 Subtest) * selectthe proper Subtest(s) */ - if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) { + if ((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) { /* * Fill the memory with incrementing * values starting from 'FirtVal' @@ -1102,8 +1126,8 @@ s32 Xil_TestMem16(u16 *Addr, u32 Words, u16 Pattern, u8 Subtest) Val++; } } - - if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) { +#ifdef XIL_ENABLE_MEMORY_STRESS_TEST + if ((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) { /* * set up to cycle through all possible initial test * Patterns for walking ones test @@ -1144,7 +1168,7 @@ s32 Xil_TestMem16(u16 *Addr, u32 Words, u16 Pattern, u8 Subtest) } } - if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) { + if ((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) { /* * set up to cycle through all possible initial * test Patterns for walking zeros test @@ -1187,7 +1211,7 @@ s32 Xil_TestMem16(u16 *Addr, u32 Words, u16 Pattern, u8 Subtest) } } - if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) { + if ((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) { /* Fill the memory with inverse of address */ for (i = 0U; i < Words; i++) { /* write memory location */ @@ -1210,15 +1234,14 @@ s32 Xil_TestMem16(u16 *Addr, u32 Words, u16 Pattern, u8 Subtest) } } - if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) { + if ((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) { /* * Generate an initial value for * memory testing */ if (Pattern == (u16)0) { Val = 0xDEADU; - } - else { + } else { Val = Pattern; } @@ -1246,7 +1269,7 @@ s32 Xil_TestMem16(u16 *Addr, u32 Words, u16 Pattern, u8 Subtest) } } } - +#endif End_Label: return Status; } @@ -1282,11 +1305,15 @@ End_Label: s32 Xil_TestMem8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest) { u32 i; - u32 j; u8 Val; u8 FirtVal; u8 WordMem8; s32 Status = 0; +#ifdef XIL_ENABLE_MEMORY_STRESS_TEST + u32 j; +#else + (void)Pattern; +#endif Xil_AssertNonvoid(Words != (u32)0); Xil_AssertNonvoid(Subtest <= XIL_TESTMEM_MAXTEST); @@ -1301,7 +1328,7 @@ s32 Xil_TestMem8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest) * select the proper Subtest(s) */ - if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) { + if ((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) { /* * Fill the memory with incrementing * values starting from 'FirtVal' @@ -1333,8 +1360,8 @@ s32 Xil_TestMem8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest) Val++; } } - - if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) { +#ifdef XIL_ENABLE_MEMORY_STRESS_TEST + if ((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) { /* * set up to cycle through all possible initial * test Patterns for walking ones test @@ -1373,7 +1400,7 @@ s32 Xil_TestMem8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest) } } - if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) { + if ((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) { /* * set up to cycle through all possible initial test * Patterns for walking zeros test @@ -1413,7 +1440,7 @@ s32 Xil_TestMem8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest) } } - if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) { + if ((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) { /* Fill the memory with inverse of address */ for (i = 0U; i < Words; i++) { /* write memory location */ @@ -1437,7 +1464,7 @@ s32 Xil_TestMem8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest) } } - if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) { + if ((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) { /* * Generate an initial value for * memory testing @@ -1445,8 +1472,7 @@ s32 Xil_TestMem8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest) if (Pattern == (u8)0) { Val = 0xA5U; - } - else { + } else { Val = Pattern; } /* @@ -1471,7 +1497,7 @@ s32 Xil_TestMem8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest) } } } - +#endif End_Label: return Status; } @@ -1489,6 +1515,7 @@ End_Label: * * *****************************************************************************/ +#ifdef XIL_ENABLE_MEMORY_STRESS_TEST static u32 RotateLeft(u32 Input, u8 Width) { u32 Msb; @@ -1524,6 +1551,7 @@ static u32 RotateLeft(u32 Input, u8 Width) return ReturnVal; } +#endif #ifdef ROTATE_RIGHT /*****************************************************************************/ diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xil_testmem.h b/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xil_testmem.h index 7e29233..9fddbc5 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xil_testmem.h +++ b/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xil_testmem.h @@ -1,5 +1,6 @@ /****************************************************************************** * Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved. +* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -103,7 +104,10 @@ extern "C" { /***************************** Include Files *********************************/ #include "xil_types.h" +#include "bspconfig.h" +#ifndef SDT #include "xparameters.h" +#endif /************************** Constant Definitions *****************************/ diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xil_types.h b/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xil_types.h index 100bddd..4c37fbc 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xil_types.h +++ b/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xil_types.h @@ -1,6 +1,6 @@ /****************************************************************************** * Copyright (c) 2010 - 2021 Xilinx, Inc. All rights reserved. -* Copyright (c) 2022 Advanced Micro Devices, Inc. All Rights Reserved. +* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -27,8 +27,9 @@ * 7.00 mus 01/07/19 Add cpp extern macro * 7.1 aru 08/19/19 Shift the value in UPPER_32_BITS only if it * is 64-bit processor -* 8.1 dp 12/23/22 Updated UINTPTR and INTPTR to point to 64bit data types +* 8.1 dp 12/23/22 Updated UINTPTR and INTPTR to point to 64bit data types * incase of microblaze 32-bit with extended address enabled +* 9.0 ml 14/04/23 Add parenthesis on sub-expression to fix misra-c violation. * * ******************************************************************************/ @@ -45,7 +46,10 @@ extern "C" { #include #include +#include "bspconfig.h" +#ifndef SDT #include "xparameters.h" +#endif /************************** Constant Definitions *****************************/ @@ -163,6 +167,10 @@ typedef void (*XInterruptHandler) (void *InstancePtr); */ typedef void (*XExceptionHandler) (void *InstancePtr); +#if defined (__riscv_xlen) && (__riscv_xlen == 64) +#define __arch64__ +#endif + /** * @brief Returns 32-63 bits of a number. * @param n : Number being accessed. diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xil_util.c b/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xil_util.c index b056c3c..7e9f2b5 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xil_util.c +++ b/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xil_util.c @@ -1,7 +1,7 @@ /******************************************************************************/ /** -* Copyright (c) 2019 - 2022 Xilinx, Inc. All rights reserved. -* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved. +* Copyright (C) 2019 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (C) 2022 - 2024 Advanced Micro Devices, Inc. All rights reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -85,6 +85,12 @@ * 8.1 sa 10/20/22 Change the type of first argument passed to Xil_WaitForEvents * API from u32 to UINTPTR for supporting 64 bit addressing. * 8.1 akm 01/02/23 Added Xil_RegisterPlmHandler() & Xil_PlmStubHandler() APIs. +* 9.0 ml 03/03/23 Add description to fix doxygen warnings. +* 9.0 ml 04/26/23 Updated code to fix DC.STRING BUFFER and VARARGS coverity warnings. +* 9.0 ml 09/13/23 Replaced numerical types (int) with proper typedefs(s32) to +* fix MISRA-C violations for Rule 4.6 +* 9.1 kpt 02/21/24 Added Xil_SChangeEndiannessAndCpy function +* * * *****************************************************************************/ @@ -94,7 +100,7 @@ #include "sleep.h" /************************** Constant Definitions ****************************/ -#define MAX_NIBBLES 8U +#define MAX_NIBBLES 8U /**< maximum nibbles */ /************************** Function Prototypes *****************************/ void (*fptr)(void) = NULL; @@ -119,8 +125,7 @@ static size_t strnlen (const char *StartPtr, size_t StrSize) EndPtr = memchr(StartPtr, '\0', StrSize); if (EndPtr == NULL) { StrLen = StrSize; - } - else { + } else { StrLen = (size_t) (EndPtr - StartPtr); } @@ -140,13 +145,13 @@ static size_t strnlen (const char *StartPtr, size_t StrSize) *******************************************************************************/ s32 Xil_Ceil(float Value) { - s32 Result = Value; + s32 Result = Value; if (Value > Result) { - Result = Result + 1; - } + Result = Result + 1; + } - return Result; + return Result; } /****************************************************************************/ @@ -174,16 +179,13 @@ u32 Xil_ConvertCharToNibble(u8 InChar, u8 *Num) if ((InChar >= (u8)'0') && (InChar <= (u8)'9')) { *Num = InChar - (u8)'0'; Status = XST_SUCCESS; - } - else if ((InChar >= (u8)'a') && (InChar <= (u8)'f')) { + } else if ((InChar >= (u8)'a') && (InChar <= (u8)'f')) { *Num = InChar - (u8)'a' + 10U; Status = XST_SUCCESS; - } - else if ((InChar >= (u8)'A') && (InChar <= (u8)'F')) { + } else if ((InChar >= (u8)'A') && (InChar <= (u8)'F')) { *Num = InChar - (u8)'A' + 10U; Status = XST_SUCCESS; - } - else { + } else { Status = XST_FAILURE; } @@ -218,8 +220,8 @@ u32 Xil_ConvertStringToHex(const char *Str, u32 *buf, u8 Len) while (ConvertedLen < Len) { for (i = 0U; i < MAX_NIBBLES; i++) { Status = Xil_ConvertCharToNibble((u8)Str[ConvertedLen], - &Nibble[i]); - ConvertedLen = ConvertedLen +1U; + &Nibble[i]); + ConvertedLen = ConvertedLen + 1U; if (Status != XST_SUCCESS) { /* Error converting char to nibble */ goto END; @@ -227,9 +229,9 @@ u32 Xil_ConvertStringToHex(const char *Str, u32 *buf, u8 Len) } buf[index] = (((u32)Nibble[0] << (u8)28U) | ((u32)Nibble[1] << (u8)24U) | - ((u32)Nibble[2] << (u8)20U) | ((u32)Nibble[3] << (u8)16U) | - ((u32)Nibble[4] << (u8)12U) | ((u32)Nibble[5] << (u8)8U) | - ((u32)Nibble[6] << (u8)4U) | (u32)Nibble[7]); + ((u32)Nibble[2] << (u8)20U) | ((u32)Nibble[3] << (u8)16U) | + ((u32)Nibble[4] << (u8)12U) | ((u32)Nibble[5] << (u8)8U) | + ((u32)Nibble[6] << (u8)4U) | (u32)Nibble[7]); index++; } END: @@ -246,7 +248,8 @@ END: * @return None. * *****************************************************************************/ -void Xil_RegisterPlmHandler(void (*PlmAlive) (void)) { +void Xil_RegisterPlmHandler(void (*PlmAlive) (void)) +{ fptr = PlmAlive; } @@ -259,7 +262,8 @@ void Xil_RegisterPlmHandler(void (*PlmAlive) (void)) { * @return None. * *****************************************************************************/ -void Xil_PlmStubHandler(void) { +void Xil_PlmStubHandler(void) +{ if (fptr != NULL) { fptr(); } @@ -288,7 +292,7 @@ u32 Xil_WaitForEvent(UINTPTR RegAddr, u32 EventMask, u32 Event, u32 Timeout) u32 PollCount = Timeout; u32 Status = XST_FAILURE; - while(PollCount > 0U) { + while (PollCount > 0U) { EventStatus = Xil_In32(RegAddr) & EventMask; if (EventStatus == Event) { Status = XST_SUCCESS; @@ -323,7 +327,7 @@ u32 Xil_WaitForEvent(UINTPTR RegAddr, u32 EventMask, u32 Event, u32 Timeout) * ******************************************************************************/ u32 Xil_WaitForEvents(UINTPTR EventsRegAddr, u32 EventsMask, u32 WaitEvents, - u32 Timeout, u32* Events) + u32 Timeout, u32 *Events) { u32 EventStatus; u32 PollCount = Timeout; @@ -333,7 +337,7 @@ u32 Xil_WaitForEvents(UINTPTR EventsRegAddr, u32 EventsMask, u32 WaitEvents, do { EventStatus = Xil_In32(EventsRegAddr); EventStatus &= EventsMask; - if((EventStatus & WaitEvents) != 0U) { + if ((EventStatus & WaitEvents) != 0U) { Status = XST_SUCCESS; *Events = EventStatus; break; @@ -343,8 +347,7 @@ u32 Xil_WaitForEvents(UINTPTR EventsRegAddr, u32 EventsMask, u32 WaitEvents, Xil_PlmStubHandler(); #endif usleep(1U); - } - while(PollCount > 0U); + } while (PollCount > 0U); return Status; } @@ -366,12 +369,12 @@ u32 Xil_IsValidHexChar(const char *Ch) { u32 Status = XST_FAILURE; - if(NULL == Ch) { + if (NULL == Ch) { goto END; } - if (((*Ch >= '0') && (*Ch <='9'))|| - ((*Ch >= 'a') && (*Ch <='f'))|| - ((*Ch >= 'A') && (*Ch <='F'))) { + if (((*Ch >= '0') && (*Ch <= '9')) || + ((*Ch >= 'a') && (*Ch <= 'f')) || + ((*Ch >= 'A') && (*Ch <= 'F'))) { Status = XST_SUCCESS; } @@ -399,7 +402,7 @@ u32 Xil_ValidateHexStr(const char *HexStr) u32 Len; u32 Status = XST_INVALID_PARAM; - if(NULL == HexStr) { + if (NULL == HexStr) { goto END; } @@ -466,21 +469,20 @@ u32 Xil_ConvertStringToHexBE(const char *Str, u8 *Buf, u32 Len) goto END; } - if(Len != (strlen(Str) * XIL_SIZE_OF_NIBBLE_IN_BITS)) { + if (Len != (strlen(Str) * XIL_SIZE_OF_NIBBLE_IN_BITS)) { Status = (u32)XST_INVALID_PARAM; goto END; } ConvertedLen = 0U; while (ConvertedLen < (Len / XIL_SIZE_OF_NIBBLE_IN_BITS)) { - if ((Xil_ConvertCharToNibble(((u8)Str[ConvertedLen]),&UpperNibble) - == (u32)XST_SUCCESS) && (Xil_ConvertCharToNibble(((u8)Str[ConvertedLen+1U]), - &LowerNibble) == (u32)XST_SUCCESS)) { - Buf[ConvertedLen/2U] = + if ((Xil_ConvertCharToNibble(((u8)Str[ConvertedLen]), &UpperNibble) + == (u32)XST_SUCCESS) && (Xil_ConvertCharToNibble(((u8)Str[ConvertedLen + 1U]), + &LowerNibble) == (u32)XST_SUCCESS)) { + Buf[ConvertedLen / 2U] = (UpperNibble << XIL_SIZE_OF_NIBBLE_IN_BITS) | - LowerNibble; - } - else { + LowerNibble; + } else { Status = (u32)XST_INVALID_PARAM; goto END; } @@ -528,7 +530,7 @@ u32 Xil_ConvertStringToHexLE(const char *Str, u8 *Buf, u32 Len) goto END; } - if(Len != (strlen(Str) * XIL_SIZE_OF_NIBBLE_IN_BITS)) { + if (Len != (strlen(Str) * XIL_SIZE_OF_NIBBLE_IN_BITS)) { Status = XST_INVALID_PARAM; goto END; } @@ -537,15 +539,14 @@ u32 Xil_ConvertStringToHexLE(const char *Str, u8 *Buf, u32 Len) ConvertedLen = 0U; while (ConvertedLen < (Len / XIL_SIZE_OF_NIBBLE_IN_BITS)) { if ((Xil_ConvertCharToNibble(((u8)Str[ConvertedLen]), - &UpperNibble) == XST_SUCCESS) && - (Xil_ConvertCharToNibble(((u8)Str[ConvertedLen + 1U]), - &LowerNibble) == XST_SUCCESS)) { - Buf[StrIndex] = - (UpperNibble << XIL_SIZE_OF_NIBBLE_IN_BITS) | - LowerNibble; - StrIndex = StrIndex - 1U; - } - else { + &UpperNibble) == XST_SUCCESS) && + (Xil_ConvertCharToNibble(((u8)Str[ConvertedLen + 1U]), + &LowerNibble) == XST_SUCCESS)) { + Buf[StrIndex] = + (UpperNibble << XIL_SIZE_OF_NIBBLE_IN_BITS) | + LowerNibble; + StrIndex = StrIndex - 1U; + } else { Status = XST_INVALID_PARAM; goto END; } @@ -580,7 +581,7 @@ u32 Xil_Strnlen(const char *Str, u32 MaxLen) goto END; } - while(StrLen < MaxLen) { + while (StrLen < MaxLen) { if ('\0' == *InStr) { break; } @@ -625,7 +626,7 @@ void Xil_UtilRMW32(u32 Addr, u32 Mask, u32 Value) * @return XST_SUCCESS on success and error code on failure * ******************************************************************************/ -int Xil_Strcpy(char *DestPtr, const char *SrcPtr, const u32 Size) +s32 Xil_Strcpy(char *DestPtr, const char *SrcPtr, const u32 Size) { int Status = XST_FAILURE; u32 Count; @@ -665,8 +666,8 @@ END: * @note None * ****************************************************************************/ -int Xil_StrCpyRange(const u8 *Src, u8 *Dest, u32 From, u32 To, u32 MaxSrcLen, - u32 MaxDstLen) +s32 Xil_StrCpyRange(const u8 *Src, u8 *Dest, u32 From, u32 To, u32 MaxSrcLen, + u32 MaxDstLen) { int Status = XST_FAILURE; u32 SrcLength; @@ -693,7 +694,7 @@ int Xil_StrCpyRange(const u8 *Src, u8 *Dest, u32 From, u32 To, u32 MaxSrcLen, goto END; } - for (Index = From; (Index <= To) && (Src[Index]!= (u8)'\0'); Index++) { + for (Index = From; (Index <= To) && (Src[Index] != (u8)'\0'); Index++) { Dest[Index - From] = Src[Index]; } @@ -716,7 +717,7 @@ END: * @return XST_SUCCESS on success and error code on failure * ******************************************************************************/ -int Xil_Strcat(char* Str1Ptr, const char* Str2Ptr, const u32 Size) +s32 Xil_Strcat(char *Str1Ptr, const char *Str2Ptr, const u32 Size) { int Status = XST_FAILURE; u32 Count = 0U; @@ -761,7 +762,7 @@ END: * @return XST_SUCCESS on success and error code on failure * ******************************************************************************/ -int Xil_SecureMemCpy(void * DestPtr, u32 DestPtrLen, const void * SrcPtr, u32 Len) +s32 Xil_SecureMemCpy(void *DestPtr, u32 DestPtrLen, const void *SrcPtr, u32 Len) { int Status = XST_FAILURE; u8 *Dest = (u8 *)DestPtr; @@ -807,7 +808,7 @@ END: * 1 if first non-matching character is greater value in Buf1Ptr * ******************************************************************************/ -int Xil_MemCmp(const void * Buf1Ptr, const void * Buf2Ptr, u32 Len) +s32 Xil_MemCmp(const void *Buf1Ptr, const void *Buf2Ptr, u32 Len) { volatile int RetVal = 1; const u8 *Buf1 = Buf1Ptr; @@ -854,7 +855,7 @@ END: * - XST_SUCCESS: If Zeroization is successful. * - XST_FAILURE: If Zeroization is not successful. ********************************************************************************/ -int Xil_SecureZeroize(u8 *DataPtr, const u32 Length) +s32 Xil_SecureZeroize(u8 *DataPtr, const u32 Length) { u32 Index; int Status = XST_FAILURE; @@ -863,7 +864,7 @@ int Xil_SecureZeroize(u8 *DataPtr, const u32 Length) (void)memset(DataPtr, 0, Length); /* Read it back to verify */ - for (Index = 0U; Index < Length; Index++) { + for (Index = 0U; Index < Length; Index++) { if (DataPtr[Index] != 0x00U) { goto END; } @@ -895,18 +896,16 @@ END: * XST_INVALID_PARAM - Invalid inputs * *****************************************************************************/ -int Xil_SMemCmp(const void *Src1, const u32 Src1Size, - const void *Src2, const u32 Src2Size, const u32 CmpLen) +s32 Xil_SMemCmp(const void *Src1, const u32 Src1Size, + const void *Src2, const u32 Src2Size, const u32 CmpLen) { int Status = XST_FAILURE; if ((Src1 == NULL) || (Src2 == NULL)) { Status = XST_INVALID_PARAM; - } - else if ((CmpLen == 0U) || (Src1Size < CmpLen) || (Src2Size < CmpLen)) { + } else if ((CmpLen == 0U) || (Src1Size < CmpLen) || (Src2Size < CmpLen)) { Status = XST_INVALID_PARAM; - } - else { + } else { Status = memcmp (Src1, Src2, CmpLen); if (Status != 0) { Status = XST_FAILURE; @@ -937,8 +936,8 @@ int Xil_SMemCmp(const void *Src1, const u32 Src1Size, * XST_INVALID_PARAM - Invalid inputs * *****************************************************************************/ -int Xil_SMemCmp_CT(const void *Src1, const u32 Src1Size, - const void *Src2, const u32 Src2Size, const u32 CmpLen) +s32 Xil_SMemCmp_CT(const void *Src1, const u32 Src1Size, + const void *Src2, const u32 Src2Size, const u32 CmpLen) { volatile int Status = XST_FAILURE; volatile int StatusRedundant = XST_FAILURE; @@ -951,13 +950,11 @@ int Xil_SMemCmp_CT(const void *Src1, const u32 Src1Size, if ((Src1 == NULL) || (Src2 == NULL)) { Status = XST_INVALID_PARAM; - } - else if ((CmpLen == 0U) || (Src1Size < CmpLen) || (Src2Size < CmpLen)) { + } else if ((CmpLen == 0U) || (Src1Size < CmpLen) || (Src2Size < CmpLen)) { Status = XST_INVALID_PARAM; - } - else { + } else { while (Cnt >= sizeof(u32)) { - Data |= (*(const u32 *)Src_1 ^ *(const u32 *)Src_2); + Data |= (*(const u32 *)Src_1 ^ * (const u32 *)Src_2); DataRedundant &= ~Data; Src_1 += sizeof(u32); Src_2 += sizeof(u32); @@ -998,29 +995,26 @@ int Xil_SMemCmp_CT(const void *Src1, const u32 Src1Size, * XST_INVALID_PARAM - Invalid inputs * *****************************************************************************/ -int Xil_SMemCpy(void *Dest, const u32 DestSize, - const void *Src, const u32 SrcSize, const u32 CopyLen) +s32 Xil_SMemCpy(void *Dest, const u32 DestSize, + const void *Src, const u32 SrcSize, const u32 CopyLen) { int Status = XST_FAILURE; const u8 *Src8 = (const u8 *) Src; const u8 *Dst8 = (u8 *) Dest; - void * volatile DestTemp = Dest; - const void * volatile SrcTemp = Src; + void *volatile DestTemp = Dest; + const void *volatile SrcTemp = Src; if ((Dest == NULL) || (Src == NULL)) { Status = XST_INVALID_PARAM; - } - else if ((CopyLen == 0U) || (DestSize < CopyLen) || (SrcSize < CopyLen)) { + } else if ((CopyLen == 0U) || (DestSize < CopyLen) || (SrcSize < CopyLen)) { Status = XST_INVALID_PARAM; } /* Return error for overlap string */ else if ((Src8 < Dst8) && (&Src8[CopyLen - 1U] >= Dst8)) { Status = XST_INVALID_PARAM; - } - else if ((Dst8 < Src8) && (&Dst8[CopyLen - 1U] >= Src8)) { + } else if ((Dst8 < Src8) && (&Dst8[CopyLen - 1U] >= Src8)) { Status = XST_INVALID_PARAM; - } - else { + } else { (void)memcpy(DestTemp, SrcTemp, CopyLen); Status = XST_SUCCESS; } @@ -1045,15 +1039,14 @@ int Xil_SMemCpy(void *Dest, const u32 DestSize, * XST_INVALID_PARAM - Invalid inputs * *****************************************************************************/ -int Xil_SMemSet(void *Dest, const u32 DestSize, - const u8 Data, const u32 Len) +s32 Xil_SMemSet(void *Dest, const u32 DestSize, + const u8 Data, const u32 Len) { int Status = XST_FAILURE; if ((Dest == NULL) || (DestSize < Len) || (Len == 0U)) { Status = XST_INVALID_PARAM; - } - else { + } else { (void)memset(Dest, (s32)Data, Len); Status = XST_SUCCESS; } @@ -1077,29 +1070,29 @@ int Xil_SMemSet(void *Dest, const u32 DestSize, * XST_INVALID_PARAM - Invalid inputs * *****************************************************************************/ -int Xil_SStrCat (u8 *DestStr, const u32 DestSize, - const u8 *SrcStr, const u32 SrcSize) +s32 Xil_SStrCat (u8 *DestStr, const u32 DestSize, + const u8 *SrcStr, const u32 SrcSize) { int Status = XST_FAILURE; u32 SrcLen; u32 DstLen; + u32 Length; if ((DestStr == NULL) || (SrcStr == NULL)) { Status = XST_INVALID_PARAM; goto END; } - SrcLen = strnlen((const char*)SrcStr, SrcSize); - DstLen = strnlen((const char*)DestStr, DestSize); + SrcLen = strnlen((const char *)SrcStr, SrcSize); + DstLen = strnlen((const char *)DestStr, DestSize); + Length = SrcLen + DstLen; if ((DestSize <= DstLen) || (SrcSize <= SrcLen)) { Status = XST_INVALID_PARAM; - } - else if (DestSize <= (SrcLen + DstLen)) { + } else if (DestSize <= Length) { Status = XST_INVALID_PARAM; - } - else { - (void)strcat((char*)DestStr, (const char*)SrcStr); + } else { + (void)strncat((char *)DestStr, (const char *)SrcStr, Length); Status = XST_SUCCESS; } @@ -1124,8 +1117,8 @@ END: * XST_INVALID_PARAM - Invalid inputs * *****************************************************************************/ -int Xil_SStrCmp(const u8 *Str1, const u32 Str1Size, - const u8 *Str2, const u32 Str2Size) +s32 Xil_SStrCmp(const u8 *Str1, const u32 Str1Size, + const u8 *Str2, const u32 Str2Size) { int Status = XST_FAILURE; u32 Str1Len = 0U; @@ -1136,16 +1129,14 @@ int Xil_SStrCmp(const u8 *Str1, const u32 Str1Size, goto END; } - Str1Len = strnlen((const char*)Str1, Str1Size); - Str2Len = strnlen((const char*)Str2, Str2Size); + Str1Len = strnlen((const char *)Str1, Str1Size); + Str2Len = strnlen((const char *)Str2, Str2Size); if ((Str1Size <= Str1Len) || (Str2Size <= Str2Len)) { Status = XST_INVALID_PARAM; - } - else if ((Str1Len < Str2Len) || (Str1Len > Str2Len)) { + } else if ((Str1Len < Str2Len) || (Str1Len > Str2Len)) { Status = XST_FAILURE; - } - else { + } else { Status = memcmp(Str1, Str2, Str1Len); if (Status != 0) { Status = XST_FAILURE; @@ -1177,8 +1168,8 @@ END: * XST_INVALID_PARAM - Invalid inputs * *****************************************************************************/ -int Xil_SStrCmp_CT (const u8 *Str1, const u32 Str1Size, - const u8 *Str2, const u32 Str2Size) +s32 Xil_SStrCmp_CT (const u8 *Str1, const u32 Str1Size, + const u8 *Str2, const u32 Str2Size) { int Status = XST_FAILURE; u32 Str1Len = 0U; @@ -1189,16 +1180,14 @@ int Xil_SStrCmp_CT (const u8 *Str1, const u32 Str1Size, goto END; } - Str1Len = strnlen((const char*)Str1, Str1Size); - Str2Len = strnlen((const char*)Str2, Str2Size); + Str1Len = strnlen((const char *)Str1, Str1Size); + Str2Len = strnlen((const char *)Str2, Str2Size); if ((Str1Size <= Str1Len) || (Str2Size <= Str2Len)) { Status = XST_INVALID_PARAM; - } - else if (Str1Len != Str2Len) { + } else if (Str1Len != Str2Len) { Status = XST_FAILURE; - } - else { + } else { Status = Xil_SMemCmp_CT (Str1, Str1Size, Str2, Str2Size, Str1Len); } @@ -1222,8 +1211,8 @@ END: * XST_INVALID_PARAM - Invalid inputs * *****************************************************************************/ -int Xil_SStrCpy(u8 *DestStr, const u32 DestSize, - const u8 *SrcStr, const u32 SrcSize) +s32 Xil_SStrCpy(u8 *DestStr, const u32 DestSize, + const u8 *SrcStr, const u32 SrcSize) { int Status = XST_FAILURE; u32 SrcLen = 0U; @@ -1233,12 +1222,11 @@ int Xil_SStrCpy(u8 *DestStr, const u32 DestSize, goto END; } - SrcLen = strnlen((const char*)SrcStr, SrcSize); + SrcLen = strnlen((const char *)SrcStr, SrcSize); if ((DestSize <= SrcLen) || (SrcSize <= SrcLen)) { Status = XST_INVALID_PARAM; - } - else { + } else { (void)memcpy(DestStr, SrcStr, SrcLen + 1U); Status = XST_SUCCESS; } @@ -1263,19 +1251,17 @@ END: * XST_INVALID_PARAM - Invalid inputs * *****************************************************************************/ -int Xil_SMemMove(void *Dest, const u32 DestSize, - const void *Src, const u32 SrcSize, const u32 CopyLen) +s32 Xil_SMemMove(void *Dest, const u32 DestSize, + const void *Src, const u32 SrcSize, const u32 CopyLen) { volatile int Status = XST_FAILURE; const void *Output = NULL; if ((Dest == NULL) || (Src == NULL)) { Status = XST_INVALID_PARAM; - } - else if ((CopyLen == 0U) || (DestSize < CopyLen) || (SrcSize < CopyLen)) { + } else if ((CopyLen == 0U) || (DestSize < CopyLen) || (SrcSize < CopyLen)) { Status = XST_INVALID_PARAM; - } - else { + } else { Output = memmove(Dest, Src, CopyLen); if (Output != NULL) { Status = XST_SUCCESS; @@ -1313,7 +1299,7 @@ u32 Xil_WaitForEventSet(u32 Timeout, u32 NumOfEvents, volatile u32 *EventAddr, . va_start(Event, EventAddr); /* wait for all events to complete */ for (i = 0; i < NumOfEvents; i++) { - while(PollCount > 0U) { + while (PollCount > 0U) { if (Xil_In32((UINTPTR)EventAddr)) { LoopCnt++; break; @@ -1330,13 +1316,13 @@ u32 Xil_WaitForEventSet(u32 Timeout, u32 NumOfEvents, volatile u32 *EventAddr, . EventAddr = va_arg(Event, volatile u32 *); PollCount = Timeout; } - va_end(Event); END: if (LoopCnt == NumOfEvents) { Status = XST_SUCCESS; } + va_end(Event); return Status; } @@ -1369,9 +1355,58 @@ s32 Xil_SecureRMW32(UINTPTR Addr, u32 Mask, u32 Value) /* verify value written to specified address */ ReadReg = Xil_In32(Addr) & Mask; - if(ReadReg == (Mask & Value)) { + if (ReadReg == (Mask & Value)) { Status = XST_SUCCESS; } return Status; } + +/*****************************************************************************/ +/** + * @brief This function changes the endianness of source data and copies it + * into destination buffer. + * + * @param Dest - Pointer to destination memory + * @param DestSize - Memory available at destination + * @param Src - Pointer to source memory + * @param SrcSize - Maximum data that can be copied from source + * @param CopyLen - Number of bytes to be copied + * + * @return + * XST_SUCCESS - Copy is successful + * XST_INVALID_PARAM - Invalid inputs + * XST_FAILURE - On failure + * + *****************************************************************************/ +s32 Xil_SChangeEndiannessAndCpy(void *Dest, const u32 DestSize, + const void *Src, const u32 SrcSize, const u32 CopyLen) +{ + s32 Status = XST_FAILURE; + volatile u32 Index; + const u8 *Src8 = (const u8 *) Src; + const u8 *Dst8 = (u8 *) Dest; + u8 *DestTemp = Dest; + const u8 *SrcTemp = Src; + + if ((Dest == NULL) || (Src == NULL)) { + Status = XST_INVALID_PARAM; + } else if ((CopyLen == 0U) || (DestSize < CopyLen) || (SrcSize < CopyLen)) { + Status = XST_INVALID_PARAM; + } + /* Return error for overlap string */ + else if ((Src8 < Dst8) && (&Src8[CopyLen - 1U] >= Dst8)) { + Status = XST_INVALID_PARAM; + } else if ((Dst8 < Src8) && (&Dst8[CopyLen - 1U] >= Src8)) { + Status = XST_INVALID_PARAM; + } else { + for (Index = 0U; Index < CopyLen; Index++) { + DestTemp[Index] = SrcTemp[CopyLen - Index - 1U]; + } + if (Index == CopyLen) { + Status = XST_SUCCESS; + } + } + + return Status; +} diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xil_util.h b/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xil_util.h index d65854c..981c7ee 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xil_util.h +++ b/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xil_util.h @@ -1,7 +1,7 @@ /******************************************************************************/ /** -* Copyright (c) 2019 - 2022 Xilinx, Inc. All rights reserved. -* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved. +* Copyright (C) 2019 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (C) 2022 - 2024 Advanced Micro Devices, Inc. All rights reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -61,6 +61,12 @@ * 8.1 akm 01/02/23 Added Xil_RegisterPlmHandler() & Xil_PlmStubHandler() APIs. * bm 03/14/23 Added XSECURE_REDUNDANT_CALL and XSECURE_REDUNDANT_IMPL macros * sk 03/14/23 Added Status Check Glitch detect Macro +* 9.0 ml 03/03/23 Add description to fix doxygen warnings. +* mmd 07/09/23 Added macro to build version +* ml 09/13/23 Replaced numerical types (int) with proper typedefs(s32) to +* fix MISRA-C violations for Rule 4.6 +* 9.1 kpt 02/21/24 Added Xil_SChangeEndiannessAndCpy function +* * * *****************************************************************************/ @@ -72,19 +78,33 @@ extern "C" { #endif +/******************************* Include Files ********************************/ #include "xil_types.h" #include "xil_io.h" #include "xstatus.h" /*************************** Constant Definitions *****************************/ -#define XIL_SIZE_OF_NIBBLE_IN_BITS 4U -#define XIL_SIZE_OF_BYTE_IN_BITS 8U - -/* Maximum string length handled by Xil_ValidateHexStr function */ -#define XIL_MAX_HEX_STR_LEN 512U +#define XIL_SIZE_OF_NIBBLE_IN_BITS 4U /**< size of nibble in bits */ +#define XIL_SIZE_OF_BYTE_IN_BITS 8U /**< size of byte in bits */ +#define XIL_MAX_HEX_STR_LEN 512U /**< Maximum string length handled by + Xil_ValidateHexStr function */ /****************** Macros (Inline Functions) Definitions *********************/ + +/******************************************************************************/ +/** + * + * Builds version number by concatenates 16-bit Major version and Minor version. + * + * @param Major is the 16-bit major version number + * @param Minor is the 16-bit minor version number + * + * @return 32-bit version number + * + ******************************************************************************/ +#define XIL_BUILD_VERSION(Major, Minor) ((((u32)Major) << 16U) | (Minor)) + #ifdef __GNUC__ /******************************************************************************/ /** @@ -103,12 +123,12 @@ extern "C" { * ******************************************************************************/ #define XSECURE_TEMPORAL_IMPL(Var, VarTmp, Function, ...) \ - { \ - Var = XST_FAILURE; \ - VarTmp = XST_FAILURE; \ - Var = Function(__VA_ARGS__); \ - VarTmp = Var; \ - } + { \ + Var = XST_FAILURE; \ + VarTmp = XST_FAILURE; \ + Var = Function(__VA_ARGS__); \ + VarTmp = Var; \ + } /******************************************************************************/ /** @@ -133,14 +153,14 @@ extern "C" { volatile int StatusTmp; \ XSECURE_TEMPORAL_IMPL(Status, StatusTmp, Function, __VA_ARGS__); \ if ((Status != XST_SUCCESS) || \ - (StatusTmp != XST_SUCCESS)) { \ + (StatusTmp != XST_SUCCESS)) { \ if (((Status) != (StatusTmp)) || \ - (Status == XST_SUCCESS)) { \ + (Status == XST_SUCCESS)) { \ Status = XST_GLITCH_ERROR; \ }\ goto Label; \ } \ - } + } /******************************************************************************/ /** @@ -163,7 +183,7 @@ extern "C" { { \ Status = Function(__VA_ARGS__); \ StatusTmp = Function(__VA_ARGS__); \ - } + } /******************************************************************************/ /** @@ -182,7 +202,7 @@ extern "C" { { \ Function(__VA_ARGS__); \ Function(__VA_ARGS__); \ - } + } /******************************************************************************/ /** @@ -204,110 +224,114 @@ extern "C" { #endif /*************************** Function Prototypes ******************************/ -/* Ceils the provided float value */ +/**< Ceils the provided float value */ s32 Xil_Ceil(float Value); -/* Converts input character to nibble */ +/**< Converts input character to nibble */ u32 Xil_ConvertCharToNibble(u8 InChar, u8 *Num); -/* Convert input hex string to array of 32-bits integers */ +/**< Convert input hex string to array of 32-bits integers */ u32 Xil_ConvertStringToHex(const char *Str, u32 *buf, u8 Len); #ifdef VERSAL_PLM -/* Register PLM handler */ +/**< Register PLM handler */ void Xil_RegisterPlmHandler(void (*PlmAlive) (void)); -/* Call PLM handler */ +/**< Call PLM handler */ void Xil_PlmStubHandler(void); #endif -/* Waits for specified event */ +/**< Waits for specified event */ u32 Xil_WaitForEvent(UINTPTR RegAddr, u32 EventMask, u32 Event, u32 Timeout); -/* Waits for specified events */ +/**< Waits for specified events */ u32 Xil_WaitForEvents(UINTPTR EventsRegAddr, u32 EventsMask, u32 WaitEvents, - u32 Timeout, u32* Events); + u32 Timeout, u32 *Events); -/* Validate input hex character */ +/**< Validate input hex character */ u32 Xil_IsValidHexChar(const char *Ch); -/* Validate the input string contains only hexadecimal characters */ +/**< Validate the input string contains only hexadecimal characters */ u32 Xil_ValidateHexStr(const char *HexStr); -/* Convert string to hex numbers in little enidian format */ +/**< Convert string to hex numbers in little enidian format */ u32 Xil_ConvertStringToHexLE(const char *Str, u8 *Buf, u32 Len); -/* Returns length of the input string */ +/**< Returns length of the input string */ u32 Xil_Strnlen(const char *Str, u32 MaxLen); -/* Convert string to hex numbers in big endian format */ -u32 Xil_ConvertStringToHexBE(const char * Str, u8 * Buf, u32 Len); +/**< Convert string to hex numbers in big endian format */ +u32 Xil_ConvertStringToHexBE(const char *Str, u8 *Buf, u32 Len); -/*Read, Modify and Write to an address*/ +/**< Read, Modify and Write to an address*/ void Xil_UtilRMW32(u32 Addr, u32 Mask, u32 Value); -/* Copies source string to destination string */ -int Xil_Strcpy(char *DestPtr, const char *SrcPtr, const u32 Size); +/**< Copies source string to destination string */ +s32 Xil_Strcpy(char *DestPtr, const char *SrcPtr, const u32 Size); -/* Copies specified range from source string to destination string */ -int Xil_StrCpyRange(const u8 *Src, u8 *Dest, u32 From, u32 To, u32 MaxSrcLen, - u32 MaxDstLen); +/**< Copies specified range from source string to destination string */ +s32 Xil_StrCpyRange(const u8 *Src, u8 *Dest, u32 From, u32 To, u32 MaxSrcLen, + u32 MaxDstLen); -/* Appends string2 to string1 */ -int Xil_Strcat(char* Str1Ptr, const char* Str2Ptr, const u32 Size); +/**< Appends string2 to string1 */ +s32 Xil_Strcat(char *Str1Ptr, const char *Str2Ptr, const u32 Size); -/* Copies Len bytes from source memory to destination memory */ -int Xil_SecureMemCpy(void * DestPtr, u32 DestPtrLen, const void * SrcPtr, u32 Len); +/**< Copies Len bytes from source memory to destination memory */ +s32 Xil_SecureMemCpy(void *DestPtr, u32 DestPtrLen, const void *SrcPtr, u32 Len); -/* Compares Len bytes from memory1 and memory2 */ -int Xil_MemCmp(const void * Buf1Ptr, const void * Buf2Ptr, u32 Len); +/**< Compares Len bytes from memory1 and memory2 */ +s32 Xil_MemCmp(const void *Buf1Ptr, const void *Buf2Ptr, u32 Len); -/* Zeroizes the memory of given length */ -int Xil_SecureZeroize(u8 *DataPtr, const u32 Length); +/**< Zeroizes the memory of given length */ +s32 Xil_SecureZeroize(u8 *DataPtr, const u32 Length); -/* Copies Len bytes from source memory to destination memory */ -int Xil_SMemCpy (void *Dest, const u32 DestSize, - const void *Src, const u32 SrcSize, const u32 CopyLen); +/**< Copies Len bytes from source memory to destination memory */ +s32 Xil_SMemCpy (void *Dest, const u32 DestSize, + const void *Src, const u32 SrcSize, const u32 CopyLen); -/* Copies Len bytes from source memory to destination memory, allows +/**< Copies Len bytes from source memory to destination memory, allows overlapped memory between source and destination */ -int Xil_SMemMove(void *Dest, const u32 DestSize, - const void *Src, const u32 SrcSize, const u32 CopyLen); +s32 Xil_SMemMove(void *Dest, const u32 DestSize, + const void *Src, const u32 SrcSize, const u32 CopyLen); -/* Compares Len bytes between source and destination memory */ -int Xil_SMemCmp (const void *Src1, const u32 Src1Size, - const void *Src2, const u32 Src2Size, const u32 CmpLen); +/**< Compares Len bytes between source and destination memory */ +s32 Xil_SMemCmp (const void *Src1, const u32 Src1Size, + const void *Src2, const u32 Src2Size, const u32 CmpLen); -/* Compares Len bytes between source and destination memory with constant time */ -int Xil_SMemCmp_CT (const void *Src1, const u32 Src1Size, - const void *Src2, const u32 Src2Size, const u32 CmpLen); +/**< Compares Len bytes between source and destination memory with constant time */ +s32 Xil_SMemCmp_CT (const void *Src1, const u32 Src1Size, + const void *Src2, const u32 Src2Size, const u32 CmpLen); -/* Sets the destination memory of given length with given data */ -int Xil_SMemSet (void *Dest, const u32 DestSize, - const u8 Data, const u32 Len); +/**< Sets the destination memory of given length with given data */ +s32 Xil_SMemSet (void *Dest, const u32 DestSize, + const u8 Data, const u32 Len); -/* Copies source string to destination string */ -int Xil_SStrCpy (u8 *DestStr, const u32 DestSize, - const u8 *SrcStr, const u32 SrcSize); +/**< Copies source string to destination string */ +s32 Xil_SStrCpy (u8 *DestStr, const u32 DestSize, + const u8 *SrcStr, const u32 SrcSize); -/* Compares source string with destination string */ -int Xil_SStrCmp (const u8 *Str1, const u32 Str1Size, - const u8 *Str2, const u32 Str2Size); +/**< Compares source string with destination string */ +s32 Xil_SStrCmp (const u8 *Str1, const u32 Str1Size, + const u8 *Str2, const u32 Str2Size); -/* Compares source string with destination string with constant time */ -int Xil_SStrCmp_CT (const u8 *Str1, const u32 Str1Size, - const u8 *Str2, const u32 Str2Size); +/**< Compares source string with destination string with constant time */ +s32 Xil_SStrCmp_CT (const u8 *Str1, const u32 Str1Size, + const u8 *Str2, const u32 Str2Size); -/* Concatenates source string to destination string */ -int Xil_SStrCat (u8 *DestStr, const u32 DestSize, - const u8 *SrcStr, const u32 SrcSize); +/**< Concatenates source string to destination string */ +s32 Xil_SStrCat (u8 *DestStr, const u32 DestSize, + const u8 *SrcStr, const u32 SrcSize); -/* Waits for event timeout */ +/**< Waits for event timeout */ u32 Xil_WaitForEventSet(u32 Timeout, u32 NumOfEvents, volatile u32 *EventAddr, ...); -/* Implements Read Modify Writes securely */ +/**< Implements Read Modify Writes securely */ s32 Xil_SecureRMW32(UINTPTR Addr, u32 Mask, u32 Value); +/**< Changes byte endianness of source buffer and copies it into destination */ +s32 Xil_SChangeEndiannessAndCpy(void *Dest, const u32 DestSize, + const void *Src, const u32 SrcSize, const u32 CopyLen); + #ifdef __cplusplus } #endif diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xplatform_info.c b/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xplatform_info.c index 83692d8..bdb7c6a 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xplatform_info.c +++ b/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xplatform_info.c @@ -43,6 +43,9 @@ * reported with "-Wundef" flag CR#1111453 * 8.1 mus 02/13/23 Added new API's XGetCoreId and XGetClusterId. As of now * they are supported only for VERSAL_NET APU and RPU. +* 9.0 mus 03/28/23 Added new API XGetBootStatus for VERSAL_NET. It can be +* used to identify type of boot (cold/warm). +* 9.0 mus 07/27/23 Updated XGetCoreId API to support A9, R5 and A53 processor. * * ******************************************************************************/ @@ -102,17 +105,17 @@ u32 XGet_Zynq_UltraMp_Platform_info(void) { #if defined (__aarch64__) && (EL1_NONSECURE == 1) XSmc_OutVar reg; - /* + /* * This SMC call will return, - * idcode - upper 32 bits of reg.Arg0 - * version - lower 32 bits of reg.Arg1 + * idcode - upper 32 bits of reg.Arg0 + * version - lower 32 bits of reg.Arg1 */ - reg = Xil_Smc(GET_CHIPID_SMC_FID,0,0, 0, 0, 0, 0, 0); + reg = Xil_Smc(GET_CHIPID_SMC_FID, 0, 0, 0, 0, 0, 0, 0); return (u32)((reg.Arg1 >> XPLAT_INFO_SHIFT) & XPLAT_INFO_MASK); #else u32 reg; reg = ((Xil_In32(XPLAT_PS_VERSION_ADDRESS) >> XPLAT_INFO_SHIFT ) - & XPLAT_INFO_MASK); + & XPLAT_INFO_MASK); return reg; #endif } @@ -130,24 +133,71 @@ u32 XGet_Zynq_UltraMp_Platform_info(void) u32 XGetPSVersion_Info(void) { #if defined (__aarch64__) && (EL1_NONSECURE == 1) - /* - * This SMC call will return, - * idcode - upper 32 bits of reg.Arg0 - * version - lower 32 bits of reg.Arg1 - */ - XSmc_OutVar reg; - reg = Xil_Smc(GET_CHIPID_SMC_FID,0,0, 0, 0, 0, 0, 0); - return (u32)((reg.Arg1 & XPS_VERSION_INFO_MASK) >> - XPS_VERSION_INFO_SHIFT); + /* + * This SMC call will return, + * idcode - upper 32 bits of reg.Arg0 + * version - lower 32 bits of reg.Arg1 + */ + XSmc_OutVar reg; + reg = Xil_Smc(GET_CHIPID_SMC_FID, 0, 0, 0, 0, 0, 0, 0); + return (u32)((reg.Arg1 & XPS_VERSION_INFO_MASK) >> + XPS_VERSION_INFO_SHIFT); #else u32 reg; reg = (Xil_In32(XPLAT_PS_VERSION_ADDRESS) - & XPS_VERSION_INFO_MASK); + & XPS_VERSION_INFO_MASK); return (reg >> XPS_VERSION_INFO_SHIFT); #endif } #endif +#if ! defined(__microblaze__) && ! defined(__riscv) +/*****************************************************************************/ +/** +* +* @brief This API is used to provide infomation about core id of the +* CPU core from which it is executed. +* +* @return Core id of the core on which API is executed. +* +******************************************************************************/ +u8 XGetCoreId(void) +{ + UINTPTR CoreId; + +#if (defined (__aarch64__) && ! defined (VERSAL_NET)) + /* CortexA53 and CortexA72 */ + CoreId = (mfcp(MPIDR_EL1) & XREG_MPIDR_MASK); + CoreId = ((CoreId & XREG_MPIDR_AFFINITY0_MASK) >> \ + XREG_MPIDR_AFFINITY0_SHIFT); +#elif (defined (__aarch64__) && defined (VERSAL_NET)) + /* CortexA78 */ + CoreId = (mfcp(MPIDR_EL1) & XREG_MPIDR_MASK); + CoreId = ((CoreId & XREG_MPIDR_AFFINITY0_MASK) >> \ + XREG_MPIDR_AFFINITY0_SHIFT); +#else + /* CortexA9, CortexR5 and CortexR52 */ +#ifdef __GNUC__ + CoreId = (mfcp(XREG_CP15_MULTI_PROC_AFFINITY) & XREG_MPIDR_MASK); +#elif defined (__ICCARM__) + mfcp(XREG_CP15_MULTI_PROC_AFFINITY, CoreId); + CoreId &= XREG_MPIDR_MASK; +#else + { + register u32 C15Reg __asm(XREG_CP15_MULTI_PROC_AFFINITY); + CoreId = C15Reg; + } + CoreId &= XREG_MPIDR_MASK; +#endif + + CoreId = ((CoreId & XREG_MPIDR_AFFINITY0_MASK) >> \ + XREG_MPIDR_AFFINITY0_SHIFT); +#endif + + return (u8)CoreId; +} +#endif + #if (defined (__aarch64__) && defined (VERSAL_NET)) || defined (ARMR52) /*****************************************************************************/ /** @@ -165,11 +215,11 @@ u8 XGetClusterId(void) #if defined (ARMR52) ClusterId = (mfcp(XREG_CP15_MULTI_PROC_AFFINITY) & XREG_MPIDR_MASK); ClusterId = ((ClusterId & XREG_MPIDR_AFFINITY1_MASK) >> \ - XREG_MPIDR_AFFINITY1_SHIFT); + XREG_MPIDR_AFFINITY1_SHIFT); #else ClusterId = (mfcp(MPIDR_EL1) & XREG_MPIDR_MASK); ClusterId = ((ClusterId & XREG_MPIDR_AFFINITY2_MASK) >> \ - XREG_MPIDR_AFFINITY2_SHIFT); + XREG_MPIDR_AFFINITY2_SHIFT); #endif return (u8)ClusterId; @@ -178,27 +228,38 @@ u8 XGetClusterId(void) /*****************************************************************************/ /** * -* @brief This API is used to provide infomation about core id of the -* CPU core from which it is executed. +* @brief This API returns boot status of core from which it is executed. +* 0th bit of CORE_X_PWRDWN/RPU_PCIL_X_PWRDWN register indicates boot type. * -* @return Core id of the core on which API is executed. +* @return - 0 for cold boot +* - 1 for warm boot * ******************************************************************************/ -u8 XGetCoreId(void) +u8 XGetBootStatus(void) { - u64 CoreId; + u32 Status; + UINTPTR Addr; -#if defined (ARMR52) - CoreId = (mfcp(XREG_CP15_MULTI_PROC_AFFINITY) & XREG_MPIDR_MASK); - CoreId = ((CoreId & XREG_MPIDR_AFFINITY0_MASK) >> \ - XREG_MPIDR_AFFINITY0_SHIFT); +#if (__aarch64__) + u8 CpuNum; + + CpuNum = XGetClusterId(); + CpuNum *= XPS_NUM_OF_CORES_PER_CLUSTER; + CpuNum += XGetCoreId(); + + Addr = XPS_CORE_X_PWRDWN_BASEADDR + (CpuNum * XPS_CORE_X_PWRDWN_OFFSET); + Status = Xil_In32(Addr); + + return (Status & XPS_CORE_X_PWRDWN_EN_MASK); #else - CoreId = (mfcp(MPIDR_EL1) & XREG_MPIDR_MASK); - CoreId = ((CoreId & XREG_MPIDR_AFFINITY1_MASK) >> \ - XREG_MPIDR_AFFINITY1_SHIFT); + Addr = (XPS_RPU_PCIL_CLUSTER_OFFSET * XGetClusterId()) + XPS_RPU_PCIL_A0_PWRDWN; + Addr += (XGetCoreId() * XPS_RPU_PCIL_CORE_OFFSET); + + Status = Xil_In32(Addr); + + return (Status & XPS_RPU_PCIL_X_PWRDWN_EN_MASK); #endif - return (u8)CoreId; } #endif diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xplatform_info.h b/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xplatform_info.h index 3e5df15..251a697 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xplatform_info.h +++ b/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xplatform_info.h @@ -36,6 +36,11 @@ * misra_c_2012_rule_10_4 violation. * 8.1 mus 02/13/23 Added new API's XGetCoreId and XGetClusterId. As of now * they are supported only for VERSAL_NET APU and RPU. +* 9.0 mus 03/28/23 Added new API XGetBootStatus for VERSAL_NET. It can be +* used to identify type of boot (cold/warm). +* 9.0 mus 07/27/23 Updated XGetCoreId API to support A9, R5 and A53 processor +* 9.0 ml 09/14/23 Added U to numerical to fix MISRA-C violation for Rule +* 10.1 and 10.4 * * ******************************************************************************/ @@ -60,12 +65,12 @@ extern "C" { #define XPAR_PMC_TAP_BASEADDR 0xF11A0000U #define XPAR_PMC_TAP_VERSION_OFFSET 0x00000004U #define XPLAT_PS_VERSION_ADDRESS (XPAR_PMC_TAP_BASEADDR + \ - XPAR_PMC_TAP_VERSION_OFFSET) + XPAR_PMC_TAP_VERSION_OFFSET) #else #define XPAR_CSU_BASEADDR 0xFFCA0000U #define XPAR_CSU_VER_OFFSET 0x00000044U #define XPLAT_PS_VERSION_ADDRESS (XPAR_CSU_BASEADDR + \ - XPAR_CSU_VER_OFFSET) + XPAR_CSU_VER_OFFSET) #endif #define XPLAT_ZYNQ_ULTRA_MP_SILICON 0x0 #define XPLAT_ZYNQ_ULTRA_MP 0x1 @@ -84,11 +89,37 @@ extern "C" { #define XPS_VERSION_INFO_SHIFT 0x8U #define XPLAT_INFO_SHIFT 0x18U #else -#define XPS_VERSION_INFO_MASK (0xF) +#define XPS_VERSION_INFO_MASK 0xFU #define XPS_VERSION_INFO_SHIFT 0x0U #define XPLAT_INFO_SHIFT 0xCU #endif +#if defined (VERSAL_NET) +#if defined (ARMR52) +#define XPS_NUM_OF_CORES_PER_CLUSTER 2U +#define XPS_RPU_PCIL_A0_PWRDWN 0xEB4200C0U +/* + * Offset between RPU_PCIL_X_PWRDWN registers of consecutive + * CPU cores in given cluster + */ +#define XPS_RPU_PCIL_CORE_OFFSET 0x100U + +/* + * Offset between RPU_PCIL_A0_PWRDWN registers of 2 clusters + */ +#define XPS_RPU_PCIL_CLUSTER_OFFSET 0x1000U +#define XPS_RPU_PCIL_X_PWRDWN_EN_MASK 1U +#else +#define XPS_NUM_OF_CORES_PER_CLUSTER 4U +#define XPS_CORE_X_PWRDWN_BASEADDR 0xECB10000U +/* + * Offset between CORE_X_PWRDWN registers of consecutive + * CPU cores + */ +#define XPS_CORE_X_PWRDWN_OFFSET 48U +#define XPS_CORE_X_PWRDWN_EN_MASK 1U +#endif +#endif /**************************** Type Definitions *******************************/ /** *@endcond @@ -97,6 +128,9 @@ extern "C" { u32 XGetPlatform_Info(void); +#if ! defined(__microblaze__) && ! defined(__riscv) +u8 XGetCoreId(void); +#endif #if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32) || defined (PSU_PMU) || defined (versal) u32 XGetPSVersion_Info(void); @@ -109,6 +143,7 @@ u32 XGet_Zynq_UltraMp_Platform_info(void); #if (defined (__aarch64__) && defined (VERSAL_NET)) || defined (ARMR52) u8 XGetClusterId(void); u8 XGetCoreId(void); +u8 XGetBootStatus(void); #endif /************************** Function Prototypes ******************************/ diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xpm_counter.c b/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xpm_counter.c index 73a69d9..70156c4 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xpm_counter.c +++ b/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xpm_counter.c @@ -1,6 +1,6 @@ /****************************************************************************** * Copyright (c) 2014 - 2022 Xilinx, Inc. All rights reserved. -* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved. +* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -30,7 +30,16 @@ * 8.00 mus 07/14/22 Existing PMU APIs dont have support for CortexA53 32 * bit processor, added check to skip PMU APIs * compilation in case of CortexA53 32 bit BSP. -* 8.1 adk 03/13/23 Include xstatus.h when xiltimer is enabled. +* 8.2 asa 02/23/23 Add instruction sync barrier as mandated by ARM specs. +* Do other clean ups. +* Remove xil_printfs for failure cases where we return +* appropriate error return value. It is expected that +* callers of the APIs would check for return value to +* know the cause of the error. +* 8.2 asa 03/09/23 Xpm_SetEvents and Xpm_GetEventCounters are deprecated +* APIs. They need not be supported for Versal Net. +* 8.2 adk 03/13/23 Include xstatus.h when xiltimer is enabled. +* 9.0 ml 14/04/23 Add U to numericals to fix misra-c violation * * ******************************************************************************/ @@ -38,7 +47,7 @@ /***************************** Include Files *********************************/ #if !defined(ARMA53_32) #include "xpm_counter.h" -#ifndef XPAR_XILTIMER_ENABLED +#if !defined(XPAR_XILTIMER_ENABLED) && !defined(SDT) #include "xil_sleeptimer.h" #include "xtime_l.h" #else @@ -83,8 +92,8 @@ void Xpm_DisableEventCounters(void) #endif #endif - RegVal &= 0x7FFFFFFF; - RegVal |= (XPM_EVENT_CNTRS_MASK & 0x7FFFFFFF); + RegVal &= 0x7FFFFFFFU; + RegVal |= XPM_EVENT_CNTRS_MASK; #if defined(__aarch64__) mtcp(PMCNTENCLR_EL0, RegVal); #else @@ -161,6 +170,7 @@ void Xpm_ResetEventCounters(void) #else mtcp(XREG_CP15_PERF_MONITOR_CTRL, Reg); #endif + isb(); } /*****************************************************************************/ @@ -183,7 +193,6 @@ u32 Xpm_DisableEvent(u32 EventCntrId) u32 CntrMask = 0x1U; if (EventCntrId > XPM_MAX_EVENTHANDLER_ID) { - xil_printf("Invalid EventHandlerID\r\n"); return XST_FAILURE; } else { CntrMask = CntrMask << EventCntrId; @@ -248,7 +257,6 @@ u32 Xpm_SetUpAnEvent(u32 EventID) OriginalCounters &= XPM_EVENT_CNTRS_BIT_MASK; Counters = OriginalCounters; if (Counters == XPM_ALL_EVENT_CNTRS_IN_USE) { - xil_printf("No counters available\r\n"); return XPM_NO_COUNTERS_AVAILABLE; } else { for(Index = 0U; Index < XPM_CTRCOUNT; Index++) { @@ -263,6 +271,7 @@ u32 Xpm_SetUpAnEvent(u32 EventID) #if defined(__aarch64__) /* Select event counter */ mtcp(PMSELR_EL0, Index); + isb(); /* Set the event */ mtcp( PMXEVTYPER_EL0, EventID); /* Enable event counter */ @@ -270,6 +279,7 @@ u32 Xpm_SetUpAnEvent(u32 EventID) #else /* Select event counter */ mtcp(XREG_CP15_EVENT_CNTR_SEL, Index); + isb(); /* Set the event */ mtcp(XREG_CP15_EVENT_TYPE_SEL, EventID); /* Enable event counter */ @@ -301,16 +311,17 @@ u32 Xpm_SetUpAnEvent(u32 EventID) u32 Xpm_GetEventCounter(u32 EventCntrId, u32 *CntVal) { if (EventCntrId > XPM_MAX_EVENTHANDLER_ID) { - xil_printf("Invalid Event Handler ID\r\n"); return XST_FAILURE; } else { #if defined(__aarch64__) mtcp(PMSELR_EL0, EventCntrId); - *CntVal = mfcp(PMXEVCNTR_EL0); + isb(); + *CntVal = mfcp(PMXEVCNTR_EL0); #else - mtcp(XREG_CP15_EVENT_CNTR_SEL, EventCntrId); + mtcp(XREG_CP15_EVENT_CNTR_SEL, EventCntrId); + isb(); #ifdef __GNUC__ - *CntVal = mfcp(XREG_CP15_PERF_MONITOR_COUNT); + *CntVal = mfcp(XREG_CP15_PERF_MONITOR_COUNT); #elif defined (__ICCARM__) mfcp(XREG_CP15_PERF_MONITOR_COUNT, (*CntVal)); #else @@ -364,7 +375,7 @@ void Xpm_SleepPerfCounter(u32 delay, u64 frequency) }while (tCur < tEnd); } #endif -#if !defined(__aarch64__) +#if !defined(__aarch64__) && !defined(VERSAL_NET) /****************************************************************************/ /** * diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xpm_init.c b/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xpm_init.c new file mode 100644 index 0000000..fca4d5e --- /dev/null +++ b/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xpm_init.c @@ -0,0 +1,224 @@ +/****************************************************************************** +* Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xpm_init.c +* @addtogroup xpm_init xpm APIs +* +* This file contains the xpm node data and API's. +* @{ +* @details +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+*  1.0  gm      14/06/23 Initial release.
+*
+******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "bspconfig.h" +#if defined (XPM_SUPPORT) +#include "xil_assert.h" +#include "xparameters.h" +#include "pm_api_sys.h" +#include "xpm_nodeid.h" +#include "xstatus.h" +#include "xpm_init.h" + +/************************** Constant Definitions *****************************/ + +#define XPMU_IPI_CHANNEL_ID XPAR_XIPIPSU_0_DEVICE_ID + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Variable Definitions *****************************/ + +static XIpiPsu IpiInst; +/************************** Function Prototypes ******************************/ + +/************************** Global Variables ********************************/ + +#ifdef VERSAL_NET +XpmNodeInfo XpmNodeData[] = { + /* { Base Address, Node ID, Reset ID } */ + { 0xF1B00000U, PM_DEV_USB_0, PM_RST_USB_0 }, /* USB_0 */ + { 0xF1C00000U, PM_DEV_USB_1, PM_RST_USB_1 }, /* USB_1 */ + { 0xF19E0000U, PM_DEV_GEM_0, PM_RST_GEM_0 }, /* GEM_0 */ + { 0xF19F0000U, PM_DEV_GEM_1, PM_RST_GEM_1 }, /* GEM_1 */ + { 0xF1960000U, PM_DEV_SPI_0, PM_RST_SPI_0 }, /* SPI_0 */ + { 0xF1970000U, PM_DEV_SPI_1, PM_RST_SPI_1 }, /* SPI_1 */ + { 0xF1940000U, PM_DEV_I2C_0, PM_RST_I2C_0 }, /* I2C_0 */ + { 0xF1950000U, PM_DEV_I2C_1, PM_RST_I2C_1 }, /* I2C_1 */ + { 0xF1980000U, PM_DEV_CAN_FD_0, PM_RST_CAN_FD_0 }, /* CAN_FD_0 */ + { 0xF1990000U, PM_DEV_CAN_FD_1, PM_RST_CAN_FD_1 }, /* CAN_FD_1 */ + { 0xF1920000U, PM_DEV_UART_0, PM_RST_UART_0 }, /* UART_0 */ + { 0xF1930000U, PM_DEV_UART_1, PM_RST_UART_1 }, /* UART_1 */ + { 0xF19D0000U, PM_DEV_GPIO, PM_RST_GPIO_LPD }, /* GPIO */ + { 0xF1DC0000U, PM_DEV_TTC_0, PM_RST_TTC_0 }, /* TTC_0 */ + { 0xF1DD0000U, PM_DEV_TTC_1, PM_RST_TTC_1 }, /* TTC_1 */ + { 0xF1DE0000U, PM_DEV_TTC_2, PM_RST_TTC_2 }, /* TTC_2 */ + { 0xF1DF0000U, PM_DEV_TTC_3, PM_RST_TTC_3 }, /* TTC_3 */ + { 0xEA420000U, PM_DEV_LPD_SWDT_0, PM_RST_SWDT_0 }, /* LPD_SWDT_0 */ + { 0xEA430000U, PM_DEV_LPD_SWDT_1, PM_RST_SWDT_1 }, /* LPD_SWDT_1 */ + { 0xECC10000U, PM_DEV_FPD_SWDT_0, PM_RST_FPD_SWDT_0 }, /* FPD_SWDT_0 */ + { 0xECD10000U, PM_DEV_FPD_SWDT_1, PM_RST_FPD_SWDT_1 }, /* FPD_SWDT_1 */ + { 0xECE10000U, PM_DEV_FPD_SWDT_2, PM_RST_FPD_SWDT_2 }, /* FPD_SWDT_2 */ + { 0xECF10000U, PM_DEV_FPD_SWDT_3, PM_RST_FPD_SWDT_3 }, /* FPD_SWDT_3 */ + { 0xF1010000U, PM_DEV_OSPI, PM_RST_OSPI }, /* OSPI */ + { 0xF1030000U, PM_DEV_QSPI, PM_RST_QSPI }, /* QSPI */ + { 0xF1020000U, PM_DEV_GPIO_PMC, PM_RST_GPIO_PMC }, /* GPIO_PMC */ + { 0xF1000000U, PM_DEV_I2C_PMC, PM_RST_I2C_PMC }, /* I2C_PMC */ + { 0xF1040000U, PM_DEV_SDIO_0, PM_RST_SDIO_0 }, /* SDIO_0 */ + { 0xF1050000U, PM_DEV_SDIO_1, PM_RST_SDIO_1 }, /* EMMC */ + { 0xEBD00000U, PM_DEV_ADMA_0, PM_RST_ADMA }, /* ADMA_0 */ + { 0xEBD10000U, PM_DEV_ADMA_1, PM_RST_ADMA }, /* ADMA_1 */ + { 0xEBD20000U, PM_DEV_ADMA_2, PM_RST_ADMA }, /* ADMA_2 */ + { 0xEBD30000U, PM_DEV_ADMA_3, PM_RST_ADMA }, /* ADMA_3 */ + { 0xEBD40000U, PM_DEV_ADMA_4, PM_RST_ADMA }, /* ADMA_4 */ + { 0xEBD50000U, PM_DEV_ADMA_5, PM_RST_ADMA }, /* ADMA_5 */ + { 0xEBD60000U, PM_DEV_ADMA_6, PM_RST_ADMA }, /* ADMA_6 */ + { 0xEBD70000U, PM_DEV_ADMA_7, PM_RST_ADMA }, /* ADMA_7 */ + { 0xEB300000U, PM_DEV_IPI_0, PM_RST_IPI }, /* IPI */ +}; +#elif defined(versal) +XpmNodeInfo XpmNodeData[] = { + /* { Base Address, Node ID, Reset ID } */ + { 0xFE200000U, PM_DEV_USB_0, PM_RST_USB_0 }, /* USB_0 */ + { 0xFF0C0000U, PM_DEV_GEM_0, PM_RST_GEM_0 }, /* GEM_0 */ + { 0xFF0D0000U, PM_DEV_GEM_1, PM_RST_GEM_1 }, /* GEM_1 */ + { 0xFF040000U, PM_DEV_SPI_0, PM_RST_SPI_0 }, /* SPI_0 */ + { 0xFF050000U, PM_DEV_SPI_1, PM_RST_SPI_1 }, /* SPI_1 */ + { 0xFF020000U, PM_DEV_I2C_0, PM_RST_I2C_0 }, /* I2C_0 */ + { 0xFF030000U, PM_DEV_I2C_1, PM_RST_I2C_1 }, /* I2C_1 */ + { 0xFF060000U, PM_DEV_CAN_FD_0, PM_RST_CAN_FD_0 }, /* CAN_FD_0 */ + { 0xFF070000U, PM_DEV_CAN_FD_1, PM_RST_CAN_FD_1 }, /* CAN_FD_1 */ + { 0xFF000000U, PM_DEV_UART_0, PM_RST_UART_0 }, /* UART_0 */ + { 0xFF010000U, PM_DEV_UART_1, PM_RST_UART_1 }, /* UART_1 */ + { 0xFF0B0000U, PM_DEV_GPIO, PM_RST_GPIO_LPD }, /* GPIO */ + { 0xFF0E0000U, PM_DEV_TTC_0, PM_RST_TTC_0 }, /* TTC_0 */ + { 0xFF0F0000U, PM_DEV_TTC_1, PM_RST_TTC_1 }, /* TTC_1 */ + { 0xFF100000U, PM_DEV_TTC_2, PM_RST_TTC_2 }, /* TTC_2 */ + { 0xFF110000U, PM_DEV_TTC_3, PM_RST_TTC_3 }, /* TTC_3 */ + { 0xFF120000U, PM_DEV_SWDT_LPD, PM_RST_SWDT_LPD }, /* SWDT_LPD */ + { 0xFD4D0000U, PM_DEV_SWDT_FPD, PM_RST_SWDT_FPD }, /* SWDT_FPD */ + { 0xF1010000U, PM_DEV_OSPI, PM_RST_OSPI }, /* OSPI */ + { 0xF1030000U, PM_DEV_QSPI, PM_RST_QSPI }, /* QSPI */ + { 0xF1020000U, PM_DEV_GPIO_PMC, PM_RST_GPIO_PMC }, /* GPIO_PMC */ + { 0xF1000000U, PM_DEV_I2C_PMC, PM_RST_I2C_PMC }, /* I2C_PMC */ + { 0xF1040000U, PM_DEV_SDIO_0, PM_RST_SDIO_0 }, /* SDIO_0 */ + { 0xF1050000U, PM_DEV_SDIO_1, PM_RST_SDIO_1 }, /* SDIO_1 */ + { 0xFFA80000U, PM_DEV_ADMA_0, PM_RST_ADMA }, /* ADMA_0 */ + { 0xFFA90000U, PM_DEV_ADMA_1, PM_RST_ADMA }, /* ADMA_1 */ + { 0xFFAA0000U, PM_DEV_ADMA_2, PM_RST_ADMA }, /* ADMA_2 */ + { 0xFFAB0000U, PM_DEV_ADMA_3, PM_RST_ADMA }, /* ADMA_3 */ + { 0xFFAC0000U, PM_DEV_ADMA_4, PM_RST_ADMA }, /* ADMA_4 */ + { 0xFFAD0000U, PM_DEV_ADMA_5, PM_RST_ADMA }, /* ADMA_5 */ + { 0xFFAE0000U, PM_DEV_ADMA_6, PM_RST_ADMA }, /* ADMA_6 */ + { 0xFFAF0000U, PM_DEV_ADMA_7, PM_RST_ADMA }, /* ADMA_7 */ + { 0xFF300000U, PM_DEV_IPI_0, PM_RST_IPI }, /* IPI */ +}; +#endif + +/****************************************************************************/ +/** + * * + * * @brief This API is used to provide the node id. + * * + * * @return Node ID if successful, otherwise XST_FAILURE. + * * + * * @note none + * * + * *****************************************************************************/ +UINTPTR XpmGetNodeId(UINTPTR BaseAddress) +{ + u32 id; + + for (id = 0; id < MAX_NODE_COUNT; id++) { + if (BaseAddress == XpmNodeData[id].BaseAddress) { + return XpmNodeData[id].NodeId; + } + } + return (UINTPTR)XST_FAILURE; +} + +/****************************************************************************/ +/** + * * + * * @brief This API is used to provide the reset id. + * * + * * @return Reset ID if successful, otherwise XST_FAILURE. + * * + * * @note none + * * + * *****************************************************************************/ +UINTPTR XpmGetResetId(UINTPTR BaseAddress) +{ + u32 id; + + for (id = 0; id < MAX_NODE_COUNT; id++) { + if (BaseAddress == XpmNodeData[id].BaseAddress) { + return XpmNodeData[id].ResetId; + } + } + return (UINTPTR)XST_FAILURE; +} + +static XStatus XpmIpiConfig(XIpiPsu *const IpiInst) +{ + XStatus status; + XIpiPsu_Config *IpiCfgPtr; + + Xil_AssertNonvoid(IpiInst != NULL); + + /* Look Up the config data */ + IpiCfgPtr = XIpiPsu_LookupConfig(XPMU_IPI_CHANNEL_ID); + if (NULL == IpiCfgPtr) { + status = XST_FAILURE; + xil_printf("%s ERROR in getting CfgPtr\n", __func__); + return status; + } + + /* Init with the Cfg Data */ + status = XIpiPsu_CfgInitialize(IpiInst, IpiCfgPtr, + IpiCfgPtr->BaseAddress); + if (XST_SUCCESS != status) { + xil_printf("%s ERROR #%d in configuring IPI\n", __func__, status); + } + return status; +} + +/****************************************************************************/ +/** + * * + * * This API initializes the ipi and xilpm through constructor. + * * + * * @return none + * * + * * @note none + * * + * *****************************************************************************/ +void __attribute__ ((constructor)) xpminit() +{ + XStatus status; + + status = XpmIpiConfig(&IpiInst); + if (XST_SUCCESS != status) { + xil_printf("IPI configuration failed.\n"); + } + + status = XPm_InitXilpm(&IpiInst); + if (XST_SUCCESS != status) { + xil_printf("Xilpm library initialization failed.\n"); + } +} +#endif diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xpm_init.h b/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xpm_init.h new file mode 100644 index 0000000..f2856be --- /dev/null +++ b/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xpm_init.h @@ -0,0 +1,46 @@ +/****************************************************************************** +*Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved. +*SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xpm_init.h +* @addtogroup xpm_init xpm_init APIs +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+*  1.0  gm      14/06/23 Initial release.
+*
+******************************************************************************/ + +#ifndef XPM_INIT_H +#define XPM_INIT_H + +/************************** Constant Definitions *****************************/ + +#if defined (XPM_SUPPORT) +#ifdef VERSAL_NET +#define MAX_NODE_COUNT 38 +#elif defined(versal) +#define MAX_NODE_COUNT 33 +#endif + +/**************************** Type Definitions *******************************/ + +typedef struct { + UINTPTR BaseAddress; + UINTPTR NodeId; + UINTPTR ResetId; +} XpmNodeInfo; + +/************************** Function Prototypes ******************************/ + +UINTPTR XpmGetNodeId(UINTPTR BaseAddress); +UINTPTR XpmGetResetId(UINTPTR BaseAddress); + +#endif +#endif diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xpseudo_asm_gcc.h b/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xpseudo_asm_gcc.h index b8517d3..5721b4c 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xpseudo_asm_gcc.h +++ b/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xpseudo_asm_gcc.h @@ -1,6 +1,6 @@ /****************************************************************************** * Copyright (c) 2014 - 2022 Xilinx, Inc. All rights reserved. -* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved. +* Copyright (c) 2022 - 2024 Advanced Micro Devices, Inc. All rights reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -23,6 +23,7 @@ * 7.2 dp 04/30/20 Added clobber "cc" to mtcpsr for aarch32 processors * 8.0 mus 02/24/22 Added macro mfcpnotoken and mtcpnotoken. * 8.1 asa 02/13/23 Create macros to read ESR, FAR and ELR registers. +* 9.1 ml 11/15/23 Fix compilation errors reported with -std=c2x compiler flag * * ******************************************************************************/ @@ -56,9 +57,9 @@ extern "C" { #if defined (__aarch64__) /* pseudo assembler instructions */ #define mfcpsr() ({u32 rval = 0U; \ - asm volatile("mrs %0, DAIF" : "=r" (rval));\ - rval;\ - }) + __asm volatile("mrs %0, DAIF" : "=r" (rval));\ + rval;\ + }) #define mtcpsr(v) __asm__ __volatile__ ("msr DAIF, %0" : : "r" (v)) @@ -68,12 +69,10 @@ extern "C" { #define cpsief() //__asm__ __volatile__("cpsie f\n") #define cpsidf() //__asm__ __volatile__("cpsid f\n") - - #define mtgpr(rn, v) /*__asm__ __volatile__(\ "mov r" stringify(rn) ", %0 \n"\ : : "r" (v)\ - )*/ +)*/ #define mfgpr(rn) /*({u32 rval; \ __asm__ __volatile__(\ @@ -81,7 +80,7 @@ extern "C" { : "=r" (rval)\ );\ rval;\ - })*/ +})*/ /* memory synchronization operations */ @@ -94,47 +93,45 @@ extern "C" { /* Data Memory Barrier */ #define dmb() __asm__ __volatile__("dmb sy") - /* Memory Operations */ #define ldr(adr) ({u64 rval; \ - __asm__ __volatile__(\ - "ldr %0,[%1]"\ - : "=r" (rval) : "r" (adr)\ - );\ - rval;\ - }) + __asm__ __volatile__(\ + "ldr %0,[%1]"\ + : "=r" (rval) : "r" (adr)\ + );\ + rval;\ + }) #if (EL3 == 1) #define mfelrel3() ({u64 rval = 0U; \ - asm volatile("mrs %0, ELR_EL3" : "=r" (rval));\ - rval;\ - }) + __asm volatile("mrs %0, ELR_EL3" : "=r" (rval));\ + rval;\ + }) #define mfesrel3() ({u64 rval = 0U; \ - asm volatile("mrs %0, ESR_EL3" : "=r" (rval));\ - rval;\ - }) + __asm volatile("mrs %0, ESR_EL3" : "=r" (rval));\ + rval;\ + }) #define mffarel3() ({u64 rval = 0U; \ - asm volatile("mrs %0, FAR_EL3" : "=r" (rval));\ - rval;\ - }) + __asm volatile("mrs %0, FAR_EL3" : "=r" (rval));\ + rval;\ + }) #else #define mfelrel1() ({u64 rval = 0U; \ - asm volatile("mrs %0, ELR_EL1" : "=r" (rval));\ - rval;\ - }) + __asm volatile("mrs %0, ELR_EL1" : "=r" (rval));\ + rval;\ + }) #define mfesrel1() ({u64 rval = 0U; \ - asm volatile("mrs %0, ESR_EL1" : "=r" (rval));\ - rval;\ - }) + __asm volatile("mrs %0, ESR_EL1" : "=r" (rval));\ + rval;\ + }) #define mffarel1() ({u64 rval = 0U; \ - asm volatile("mrs %0, FAR_EL1" : "=r" (rval));\ - rval;\ - }) - + __asm volatile("mrs %0, FAR_EL1" : "=r" (rval));\ + rval;\ + }) #endif @@ -144,17 +141,17 @@ extern "C" { /* pseudo assembler instructions */ #define mfcpsr() ({u32 rval = 0U; \ - __asm__ __volatile__(\ - "mrs %0, cpsr\n"\ - : "=r" (rval)\ - );\ - rval;\ - }) + __asm__ __volatile__(\ + "mrs %0, cpsr\n"\ + : "=r" (rval)\ + );\ + rval;\ + }) #define mtcpsr(v) __asm__ __volatile__(\ - "msr cpsr,%0\n"\ - : : "r" (v) : "cc" \ - ) + "msr cpsr,%0\n"\ + : : "r" (v) : "cc" \ + ) #define cpsiei() __asm__ __volatile__("cpsie i\n") #define cpsidi() __asm__ __volatile__("cpsid i\n") @@ -162,20 +159,18 @@ extern "C" { #define cpsief() __asm__ __volatile__("cpsie f\n") #define cpsidf() __asm__ __volatile__("cpsid f\n") - - #define mtgpr(rn, v) __asm__ __volatile__(\ - "mov r" stringify(rn) ", %0 \n"\ - : : "r" (v)\ - ) + "mov r" stringify(rn) ", %0 \n"\ + : : "r" (v)\ + ) #define mfgpr(rn) ({u32 rval; \ - __asm__ __volatile__(\ - "mov %0,r" stringify(rn) "\n"\ - : "=r" (rval)\ - );\ - rval;\ - }) + __asm__ __volatile__(\ + "mov %0,r" stringify(rn) "\n"\ + : "=r" (rval)\ + );\ + rval;\ + }) /* memory synchronization operations */ @@ -188,44 +183,43 @@ extern "C" { /* Data Memory Barrier */ #define dmb() __asm__ __volatile__ ("dmb" : : : "memory") - /* Memory Operations */ #define ldr(adr) ({u32 rval; \ - __asm__ __volatile__(\ - "ldr %0,[%1]"\ - : "=r" (rval) : "r" (adr)\ - );\ - rval;\ - }) + __asm__ __volatile__(\ + "ldr %0,[%1]"\ + : "=r" (rval) : "r" (adr)\ + );\ + rval;\ + }) #endif #define ldrb(adr) ({u8 rval; \ - __asm__ __volatile__(\ - "ldrb %0,[%1]"\ - : "=r" (rval) : "r" (adr)\ - );\ - rval;\ - }) + __asm__ __volatile__(\ + "ldrb %0,[%1]"\ + : "=r" (rval) : "r" (adr)\ + );\ + rval;\ + }) #define strw(adr, val) __asm__ __volatile__(\ - "str %0,[%1]\n"\ - : : "r" (val), "r" (adr)\ - ) + "str %0,[%1]\n"\ + : : "r" (val), "r" (adr)\ + ) #define strb(adr, val) __asm__ __volatile__(\ - "strb %0,[%1]\n"\ - : : "r" (val), "r" (adr)\ - ) + "strb %0,[%1]\n"\ + : : "r" (val), "r" (adr)\ + ) /* Count leading zeroes (clz) */ #define clz(arg) ({u8 rval; \ - __asm__ __volatile__(\ - "clz %0,%1"\ - : "=r" (rval) : "r" (arg)\ - );\ - rval;\ - }) + __asm__ __volatile__(\ + "clz %0,%1"\ + : "=r" (rval) : "r" (arg)\ + );\ + rval;\ + }) #if defined (__aarch64__) #define mtcpdc(reg,val) __asm__ __volatile__("dc " #reg ",%0" : : "r" (val)) @@ -236,14 +230,14 @@ extern "C" { #define mtcpat(reg,val) __asm__ __volatile__("at " #reg ",%0" : : "r" (val)) /* CP15 operations */ #define mfcp(reg) ({u64 rval = 0U;\ - __asm__ __volatile__("mrs %0, " #reg : "=r" (rval));\ - rval;\ - }) + __asm__ __volatile__("mrs %0, " #reg : "=r" (rval));\ + rval;\ + }) #define mfcpnotoken(reg) ({u64 rval = 0U;\ - __asm__ __volatile__("mrs %0, " reg : "=r" (rval));\ - rval;\ - }) + __asm__ __volatile__("mrs %0, " reg : "=r" (rval));\ + rval;\ + }) #define mtcp(reg,val) __asm__ __volatile__("msr " #reg ",%0" : : "r" (val)) #define mtcpnotoken(reg,val) __asm__ __volatile__("msr " reg ",%0" : : "r" (val)) @@ -251,22 +245,22 @@ extern "C" { #else /* CP15 operations */ #define mtcp(rn, v) __asm__ __volatile__(\ - "mcr " rn "\n"\ - : : "r" (v)\ - ); + "mcr " rn "\n"\ + : : "r" (v)\ + ); #define mfcp(rn) ({u32 rval = 0U; \ - __asm__ __volatile__(\ - "mrc " rn "\n"\ - : "=r" (rval)\ - );\ - rval;\ - }) + __asm__ __volatile__(\ + "mrc " rn "\n"\ + : "=r" (rval)\ + );\ + rval;\ + }) #define mtcp2(rn, v) __asm__ __volatile__(\ - "mcrr " rn "\n"\ - : : "r" (v), "r" (0)\ - ); + "mcrr " rn "\n"\ + : : "r" (v), "r" (0)\ + ); #endif diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xreg_cortexa9.h b/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xreg_cortexa9.h index 2a4fff2..0d2c7b1 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xreg_cortexa9.h +++ b/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xreg_cortexa9.h @@ -1,5 +1,6 @@ /****************************************************************************** * Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved. +* Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -20,6 +21,7 @@ * Ver Who Date Changes * ----- -------- -------- ----------------------------------------------- * 1.00a ecm/sdm 10/20/09 First release +* 9.0 mus 07/29/23 Added definitions for processor affinity register. * * ******************************************************************************/ @@ -489,7 +491,10 @@ extern "C" { #define XREG_CP15_MAIN_TLB_ATTR "cp15:5:c15:c7:2" #endif - +/* Affinity register bits */ +#define XREG_MPIDR_MASK 0xFFFFFFFFU +#define XREG_MPIDR_AFFINITY0_MASK 0x3U +#define XREG_MPIDR_AFFINITY0_SHIFT 0x0U /* MPE register definitions */ #define XREG_FPSID c0 #define XREG_FPSCR c1 diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xstatus.h b/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xstatus.h index 85d1e73..f534bdf 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xstatus.h +++ b/bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xstatus.h @@ -32,6 +32,7 @@ extern "C" { #include "xil_types.h" #include "xil_assert.h" +#include "bspconfig.h" /************************** Constant Definitions *****************************/ diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/ttcps/src/xttcps.c b/bsp_z7/ps7_cortexa9_0/libsrc/ttcps/src/xttcps.c index 56727eb..49f2c5b 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/ttcps/src/xttcps.c +++ b/bsp_z7/ps7_cortexa9_0/libsrc/ttcps/src/xttcps.c @@ -1,6 +1,6 @@ /****************************************************************************** * Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved. -* Copyright (c) 2022 Advanced Micro Devices, Inc. All Rights Reserved. +* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -41,6 +41,17 @@ * 3.10 aru 05/06/19 Added assert check for driver instance and freq * parameter in XTtcPs_CalcIntervalFromFreq(). * 3.10 aru 05/30/19 Added interrupt handler to clear ISR +* 3.18 gm 06/26/23 Added PM Request node support. +* 3.18 gm 07/17/23 Added PM Release node support. +* 3.18 ml 09/08/23 Updated code by using ternary operator +* to fix MISRA-C violation for Rule 10.3 +* 3.18 ml 09/08/23 Replaced TRUE with Numerical value to fix +* MISRA-C violation for Rule 10.5 +* 3.18 ml 09/07/23 Removed XTtcPs_ClearInterruptStatus function call to avoid the +* the same operation for 2 times. +* 3.18 ml 09/07/23 Added U to numerical to fix MISRA-C violation for Rule 10.4 +* 3.18 ml 09/08/23 Typecast with u32 to fix MISRA-C violation for Rule 12.2 and 10.7 +* 3.18 ml 09/08/23 Added comments to fix HIS COMF violations. * * ******************************************************************************/ @@ -48,6 +59,14 @@ /***************************** Include Files *********************************/ #include "xttcps.h" +#if defined (XPM_SUPPORT) +#include "pm_defs.h" +#include "pm_api_sys.h" +#include "xil_types.h" +#include "pm_client.h" +#include "xpm_init.h" +#include "xdebug.h" +#endif /************************** Constant Definitions *****************************/ @@ -59,6 +78,35 @@ static void StubStatusHandler(const void *CallBackRef, u32 StatusEvent); /************************** Variable Definitions *****************************/ +#if defined (XPM_SUPPORT) +/* + * Instance - counters list + * Ttc0 - 0 to 2 + * Ttc1 - 3 to 5 + * Ttc2 - 6 to 8 + * Ttc3 - 9 to 11 + * + * TtcNodeState is an array which holds the present state of the counter + * in it's corresponding index value. Index value will be incremented + * during ttc counter request node and decremented during release node. + * + */ +static u32 TtcNodeState[XPAR_XTTCPS_NUM_INSTANCES]; + +extern XTtcPs_Config XTtcPs_ConfigTable[XPAR_XTTCPS_NUM_INSTANCES]; + +static u32 GetTtcNodeAddress(u16 DeviceId) +{ + u32 Index; + + for (Index = 0U; Index < (u32)XPAR_XTTCPS_NUM_INSTANCES; Index++) { + if (XTtcPs_ConfigTable[Index].DeviceId == DeviceId) { + return XTtcPs_ConfigTable[Index].BaseAddress; + } + } + return 0; +} +#endif /*****************************************************************************/ /** @@ -97,34 +145,68 @@ static void StubStatusHandler(const void *CallBackRef, u32 StatusEvent); * ******************************************************************************/ s32 XTtcPs_CfgInitialize(XTtcPs *InstancePtr, XTtcPs_Config *ConfigPtr, - u32 EffectiveAddr) + u32 EffectiveAddr) { s32 Status; u32 IsStartResult; +#if defined (XPM_SUPPORT) + u32 TtcNodeAddr; +#endif +#ifdef SDT + u16 Count; +#endif + /* * Assert to validate input arguments. */ Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(ConfigPtr != NULL); +#if defined (XPM_SUPPORT) + TtcNodeAddr = GetTtcNodeAddress((ConfigPtr->DeviceId / 3) * 3); + + Status = XPm_RequestNode(XpmGetNodeId((UINTPTR)TtcNodeAddr), PM_CAP_ACCESS, MAX_QOS, REQUEST_ACK_BLOCKING); + if (XST_SUCCESS != Status) { + xdbg_printf(XDBG_DEBUG_ERROR, "Ttc: XPm_RequestNode failed\r\n"); + return Status; + } + + Status = XPm_ResetAssert(XpmGetResetId((UINTPTR)TtcNodeAddr), XILPM_RESET_ACTION_RELEASE); + if (XST_SUCCESS != Status) { + xdbg_printf(XDBG_DEBUG_ERROR, "Ttc: XPm_ResetAssert() ERROR=0x%x \r\n", Status); + return Status; + } + + TtcNodeState[ConfigPtr->DeviceId]++; +#endif + /* * Set some default values */ +#ifndef SDT InstancePtr->Config.DeviceId = ConfigPtr->DeviceId; +#endif InstancePtr->Config.BaseAddress = EffectiveAddr; InstancePtr->Config.InputClockHz = ConfigPtr->InputClockHz; InstancePtr->StatusHandler = StubStatusHandler; -#ifdef XIL_INTERRUPT +#if defined(XIL_INTERRUPT) && !defined(SDT) InstancePtr->Config.IntrId = ConfigPtr->IntrId; InstancePtr->Config.IntrParent = ConfigPtr->IntrParent; #endif - IsStartResult = XTtcPs_IsStarted(InstancePtr); +#ifdef SDT + for (Count = 0; Count < XTTCPS_NUM_COUNTERS; Count++) { + InstancePtr->Config.IntrId[Count] = ConfigPtr->IntrId[Count]; + } + InstancePtr->Config.IntrParent = ConfigPtr->IntrParent; +#endif + + IsStartResult = XTtcPs_IsStarted(InstancePtr) ? 1U : 0U; /* * If the timer counter has already started, return an error * Device should be stopped first. */ - if(IsStartResult == (u32)TRUE) { + if (IsStartResult == 1U) { Status = XST_DEVICE_IS_STARTED; } else { @@ -136,26 +218,26 @@ s32 XTtcPs_CfgInitialize(XTtcPs *InstancePtr, XTtcPs_Config *ConfigPtr, * Reset the count control register to it's default value. */ XTtcPs_WriteReg(InstancePtr->Config.BaseAddress, - XTTCPS_CNT_CNTRL_OFFSET, - XTTCPS_CNT_CNTRL_RESET_VALUE); + XTTCPS_CNT_CNTRL_OFFSET, + XTTCPS_CNT_CNTRL_RESET_VALUE); /* * Reset the rest of the registers to the default values. */ XTtcPs_WriteReg(InstancePtr->Config.BaseAddress, - XTTCPS_CLK_CNTRL_OFFSET, 0x00U); + XTTCPS_CLK_CNTRL_OFFSET, 0x00U); XTtcPs_WriteReg(InstancePtr->Config.BaseAddress, - XTTCPS_INTERVAL_VAL_OFFSET, 0x00U); + XTTCPS_INTERVAL_VAL_OFFSET, 0x00U); XTtcPs_WriteReg(InstancePtr->Config.BaseAddress, - XTTCPS_MATCH_0_OFFSET, 0x00U); + XTTCPS_MATCH_0_OFFSET, 0x00U); XTtcPs_WriteReg(InstancePtr->Config.BaseAddress, - XTTCPS_MATCH_1_OFFSET, 0x00U); + XTTCPS_MATCH_1_OFFSET, 0x00U); XTtcPs_WriteReg(InstancePtr->Config.BaseAddress, - XTTCPS_MATCH_2_OFFSET, 0x00U); + XTTCPS_MATCH_2_OFFSET, 0x00U); XTtcPs_WriteReg(InstancePtr->Config.BaseAddress, - XTTCPS_IER_OFFSET, 0x00U); + XTTCPS_IER_OFFSET, 0x00U); XTtcPs_WriteReg(InstancePtr->Config.BaseAddress, - XTTCPS_ISR_OFFSET, XTTCPS_IXR_ALL_MASK); + XTTCPS_ISR_OFFSET, XTTCPS_IXR_ALL_MASK); InstancePtr->IsReady = XIL_COMPONENT_IS_READY; @@ -168,6 +250,81 @@ s32 XTtcPs_CfgInitialize(XTtcPs *InstancePtr, XTtcPs_Config *ConfigPtr, return Status; } +#if defined (XPM_SUPPORT) +static u32 CheckTtcNodeState(u16 TtcNodeId) +{ + u8 IdOffset; + u16 TtcBaseNodeId; + u32 State = FALSE; + + TtcBaseNodeId = ((TtcNodeId / 3) * 3); + + for (IdOffset = TtcBaseNodeId; IdOffset < (TtcBaseNodeId + 3); IdOffset++) { + if (TtcNodeState[IdOffset] == 0) { + continue; + } else { + if (IdOffset == TtcNodeId) { + if ((TtcNodeState[IdOffset] - 1) == 0) { + continue; + } + } + State = TRUE; + break; + } + } + return State; +} +#endif + +/*****************************************************************************/ +/** +* +* This routine releases resources of XTtcPs instance/driver. +* +* @param None +* @return - XST_SUCCESS if node release was successful +* - XST_FAILURE if node release was fail, Node won't be released +* if any other counter/counters in that TTC in use. +* +* @note None. +* +******************************************************************************/ +u32 XTtcPs_Release(XTtcPs *InstancePtr) +{ + u32 Status = XST_SUCCESS; +#if defined (XPM_SUPPORT) + u32 TtcNodeAddr; +#endif + + Xil_AssertNonvoid(InstancePtr != NULL); + +#if defined (XPM_SUPPORT) + if (InstancePtr->Config.DeviceId >= XPAR_XTTCPS_NUM_INSTANCES) { + Status = XST_FAILURE; + } else { + /* Stop ttc */ + XTtcPs_Stop(InstancePtr); + + /* Clear interrupt status */ + XTtcPs_ClearInterruptStatus(InstancePtr, + XTtcPs_GetInterruptStatus(InstancePtr)); + + /* Disable interrupts */ + XTtcPs_DisableInterrupts(InstancePtr, XTTCPS_IXR_ALL_MASK); + + /* Release node, if no other counter in use under that ttc node */ + if (TRUE == CheckTtcNodeState(InstancePtr->Config.DeviceId)) { + Status = XST_FAILURE; + } else { + TtcNodeAddr = GetTtcNodeAddress((InstancePtr->Config.DeviceId / 3) * 3); + Status = XPm_ReleaseNode(XpmGetNodeId((UINTPTR)TtcNodeAddr)); + TtcNodeState[InstancePtr->Config.DeviceId]--; + } + } +#endif + return Status; +} + /*****************************************************************************/ /** * @@ -196,7 +353,7 @@ s32 XTtcPs_CfgInitialize(XTtcPs *InstancePtr, XTtcPs_Config *ConfigPtr, void XTtcPs_SetMatchValue(XTtcPs *InstancePtr, u8 MatchIndex, XMatchRegValue Value) { /* - * Assert to validate input arguments. + * Validate input arguments and in case of error conditions assert. */ Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); @@ -206,7 +363,7 @@ void XTtcPs_SetMatchValue(XTtcPs *InstancePtr, u8 MatchIndex, XMatchRegValue Val * Write the value to the correct match register with MatchIndex */ XTtcPs_WriteReg(InstancePtr->Config.BaseAddress, - XTtcPs_Match_N_Offset(MatchIndex), Value); + XTtcPs_Match_N_Offset(MatchIndex), Value); } /*****************************************************************************/ @@ -230,14 +387,14 @@ XMatchRegValue XTtcPs_GetMatchValue(XTtcPs *InstancePtr, u8 MatchIndex) u32 MatchReg; /* - * Assert to validate input arguments. + * Validate input arguments and in case of error conditions assert. */ Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); Xil_AssertNonvoid(MatchIndex < XTTCPS_NUM_MATCH_REG); MatchReg = XTtcPs_ReadReg(InstancePtr->Config.BaseAddress, - XTtcPs_Match_N_Offset(MatchIndex)); + XTtcPs_Match_N_Offset(MatchIndex)); return (XMatchRegValue) MatchReg; } @@ -278,7 +435,7 @@ void XTtcPs_SetPrescaler(XTtcPs *InstancePtr, u8 PrescalerValue) * Read the clock control register */ ClockReg = XTtcPs_ReadReg(InstancePtr->Config.BaseAddress, - XTTCPS_CLK_CNTRL_OFFSET); + XTTCPS_CLK_CNTRL_OFFSET); /* * Clear all of the prescaler control bits in the register @@ -291,7 +448,7 @@ void XTtcPs_SetPrescaler(XTtcPs *InstancePtr, u8 PrescalerValue) * Set the prescaler value and enable prescaler */ ClockReg |= (u32)(((u32)PrescalerValue << (u32)XTTCPS_CLK_CNTRL_PS_VAL_SHIFT) & - (u32)XTTCPS_CLK_CNTRL_PS_VAL_MASK); + (u32)XTTCPS_CLK_CNTRL_PS_VAL_MASK); ClockReg |= (u32)XTTCPS_CLK_CNTRL_PS_EN_MASK; } @@ -299,7 +456,7 @@ void XTtcPs_SetPrescaler(XTtcPs *InstancePtr, u8 PrescalerValue) * Write the register with the new values. */ XTtcPs_WriteReg(InstancePtr->Config.BaseAddress, - XTTCPS_CLK_CNTRL_OFFSET, ClockReg); + XTTCPS_CLK_CNTRL_OFFSET, ClockReg); } /*****************************************************************************/ @@ -341,18 +498,17 @@ u8 XTtcPs_GetPrescaler(XTtcPs *InstancePtr) * Read the clock control register */ ClockReg = XTtcPs_ReadReg(InstancePtr->Config.BaseAddress, - XTTCPS_CLK_CNTRL_OFFSET); + XTTCPS_CLK_CNTRL_OFFSET); - if (0 == (ClockReg & XTTCPS_CLK_CNTRL_PS_EN_MASK)) { + if (0U == (ClockReg & XTTCPS_CLK_CNTRL_PS_EN_MASK)) { /* * Prescaler is disabled. Return the correct flag value */ Status = (u8)XTTCPS_CLK_CNTRL_PS_DISABLE; - } - else { + } else { Status = (u8)((ClockReg & (u32)XTTCPS_CLK_CNTRL_PS_VAL_MASK) >> - (u32)XTTCPS_CLK_CNTRL_PS_VAL_SHIFT); + (u32)XTTCPS_CLK_CNTRL_PS_VAL_SHIFT); } return Status; } @@ -382,17 +538,17 @@ u8 XTtcPs_GetPrescaler(XTtcPs *InstancePtr) * ****************************************************************************/ void XTtcPs_CalcIntervalFromFreq(XTtcPs *InstancePtr, u32 Freq, - XInterval *Interval, u8 *Prescaler) + XInterval *Interval, u8 *Prescaler) { u8 TmpPrescaler; UINTPTR TempValue; u32 InputClock; /* - * Assert to validate input arguments. - */ + * Assert to validate input arguments. + */ Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(Freq > 0U); + Xil_AssertVoid(Freq > 0U); InputClock = InstancePtr->Config.InputClockHz; /* @@ -400,7 +556,7 @@ void XTtcPs_CalcIntervalFromFreq(XTtcPs *InstancePtr, u32 Freq, * smaller the prescaler, the larger the count and the more accurate the * PWM setting. */ - TempValue = InputClock/ Freq; + TempValue = InputClock / Freq; if (TempValue < 4U) { /* @@ -427,7 +583,7 @@ void XTtcPs_CalcIntervalFromFreq(XTtcPs *InstancePtr, u32 Freq, for (TmpPrescaler = 0U; TmpPrescaler < XTTCPS_CLK_CNTRL_PS_DISABLE; TmpPrescaler++) { - TempValue = InputClock/ (Freq * (1U << (TmpPrescaler + 1U))); + TempValue = InputClock / (Freq * ((u32)1U << (TmpPrescaler + 1U))); /* * The first value less than 2^16 is the best bet @@ -469,16 +625,10 @@ u32 XTtcPs_InterruptHandler(XTtcPs *InstancePtr) { u32 XTtcPsStatusReg; - Xil_AssertNonvoid(InstancePtr != NULL); - XTtcPsStatusReg = XTtcPs_GetInterruptStatus(InstancePtr); - XTtcPs_ClearInterruptStatus(InstancePtr, XTtcPsStatusReg); InstancePtr->StatusHandler(InstancePtr->StatusRef, - XTtcPsStatusReg); + XTtcPsStatusReg); return XST_SUCCESS; - - - } /*****************************************************************************/ @@ -505,12 +655,14 @@ u32 XTtcPs_InterruptHandler(XTtcPs *InstancePtr) * ******************************************************************************/ void XTtcPs_SetStatusHandler(XTtcPs *InstancePtr, void *CallBackRef, - XTtcPs_StatusHandler FuncPointer) + XTtcPs_StatusHandler FuncPointer) { + /* + * Validate input arguments and in case of error conditions assert. + */ Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid(FuncPointer != NULL); Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - InstancePtr->StatusHandler = FuncPointer; InstancePtr->StatusRef = CallBackRef; } diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/ttcps/src/xttcps.h b/bsp_z7/ps7_cortexa9_0/libsrc/ttcps/src/xttcps.h index 643e73e..e62fc6f 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/ttcps/src/xttcps.h +++ b/bsp_z7/ps7_cortexa9_0/libsrc/ttcps/src/xttcps.h @@ -1,6 +1,6 @@ /****************************************************************************** * Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved. -* Copyright (c) 2022 Advanced Micro Devices, Inc. All Rights Reserved. +* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -149,6 +149,7 @@ * It fixes CR#1084697. * 3.16 adk 04/19/22 Fix infinite loop in the examples by adding polled * timeout loop. +* 3.18 adk 04/14/23 Added support for system device-tree flow. * * ******************************************************************************/ @@ -181,6 +182,7 @@ typedef void (*XTtcPs_StatusHandler) (const void *CallBackRef, u32 StatusEvent); #define XTTCPS_MAX_INTERVAL_COUNT 0xFFFFFFFFU #endif +#define XTTCPS_NUM_COUNTERS 3U /** @name Configuration options * * Options for the device. Each of the options is bit field, so more than one @@ -203,11 +205,18 @@ typedef void (*XTtcPs_StatusHandler) (const void *CallBackRef, u32 StatusEvent); * This typedef contains configuration information for the device. */ typedef struct { +#ifndef SDT u16 DeviceId; /**< Unique ID for device */ +#else + char *Name; +#endif u32 BaseAddress; /**< Base address for device */ u32 InputClockHz; /**< Input clock frequency */ -#ifdef XIL_INTERRUPT - u16 IntrId; +#if !defined(SDT) && defined(XIL_INTERRUPT) + u32 IntrId; + UINTPTR IntrParent; /** Bit[0] Interrupt parent type Bit[64/32:1] Parent base address */ +#elif defined(SDT) + u32 IntrId[XTTCPS_NUM_COUNTERS]; /** Bits[11:0] Interrupt-id Bits[15:12] trigger type and level flags */ UINTPTR IntrParent; /** Bit[0] Interrupt parent type Bit[64/32:1] Parent base address */ #endif } XTtcPs_Config; @@ -487,7 +496,11 @@ typedef u32 XMatchRegValue; /* * Initialization functions in xttcps_sinit.c */ +#ifndef SDT XTtcPs_Config *XTtcPs_LookupConfig(u16 DeviceId); +#else +XTtcPs_Config *XTtcPs_LookupConfig(u32 BaseAddress); +#endif /* * Required functions, in xttcps.c @@ -495,6 +508,7 @@ XTtcPs_Config *XTtcPs_LookupConfig(u16 DeviceId); s32 XTtcPs_CfgInitialize(XTtcPs *InstancePtr, XTtcPs_Config * ConfigPtr, u32 EffectiveAddr); +u32 XTtcPs_Release(XTtcPs *InstancePtr); void XTtcPs_SetMatchValue(XTtcPs *InstancePtr, u8 MatchIndex, XMatchRegValue Value); XMatchRegValue XTtcPs_GetMatchValue(XTtcPs *InstancePtr, u8 MatchIndex); diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/ttcps/src/xttcps_options.c b/bsp_z7/ps7_cortexa9_0/libsrc/ttcps/src/xttcps_options.c index 6da2260..a65f29a 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/ttcps/src/xttcps_options.c +++ b/bsp_z7/ps7_cortexa9_0/libsrc/ttcps/src/xttcps_options.c @@ -1,6 +1,6 @@ /****************************************************************************** * Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved. -* Copyright (c) 2022 Advanced Micro Devices, Inc. All Rights Reserved. +* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -23,6 +23,8 @@ * compilation warnings. * 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance. * 3.10 aru 05/16/19 Removed the redudant code from XTtcPs_SetOptions(). +* 3.18 ml 09/08/23 Updated code to fix MISRA-C violation for Rule 14.3 +* 3.18 ml 09/08/23 Added comments to fix HIS COMF violations. * * ******************************************************************************/ @@ -57,24 +59,38 @@ typedef struct { } OptionsMap; static OptionsMap TmrCtrOptionsTable[] = { - {XTTCPS_OPTION_EXTERNAL_CLK, XTTCPS_CLK_CNTRL_SRC_MASK, - XTTCPS_CLK_CNTRL_OFFSET}, - {XTTCPS_OPTION_CLK_EDGE_NEG, XTTCPS_CLK_CNTRL_EXT_EDGE_MASK, - XTTCPS_CLK_CNTRL_OFFSET}, - {XTTCPS_OPTION_INTERVAL_MODE, XTTCPS_CNT_CNTRL_INT_MASK, - XTTCPS_CNT_CNTRL_OFFSET}, - {XTTCPS_OPTION_DECREMENT, XTTCPS_CNT_CNTRL_DECR_MASK, - XTTCPS_CNT_CNTRL_OFFSET}, - {XTTCPS_OPTION_MATCH_MODE, XTTCPS_CNT_CNTRL_MATCH_MASK, - XTTCPS_CNT_CNTRL_OFFSET}, - {XTTCPS_OPTION_WAVE_DISABLE, XTTCPS_CNT_CNTRL_EN_WAVE_MASK, - XTTCPS_CNT_CNTRL_OFFSET}, - {XTTCPS_OPTION_WAVE_POLARITY, XTTCPS_CNT_CNTRL_POL_WAVE_MASK, - XTTCPS_CNT_CNTRL_OFFSET}, + { + XTTCPS_OPTION_EXTERNAL_CLK, XTTCPS_CLK_CNTRL_SRC_MASK, + XTTCPS_CLK_CNTRL_OFFSET + }, + { + XTTCPS_OPTION_CLK_EDGE_NEG, XTTCPS_CLK_CNTRL_EXT_EDGE_MASK, + XTTCPS_CLK_CNTRL_OFFSET + }, + { + XTTCPS_OPTION_INTERVAL_MODE, XTTCPS_CNT_CNTRL_INT_MASK, + XTTCPS_CNT_CNTRL_OFFSET + }, + { + XTTCPS_OPTION_DECREMENT, XTTCPS_CNT_CNTRL_DECR_MASK, + XTTCPS_CNT_CNTRL_OFFSET + }, + { + XTTCPS_OPTION_MATCH_MODE, XTTCPS_CNT_CNTRL_MATCH_MASK, + XTTCPS_CNT_CNTRL_OFFSET + }, + { + XTTCPS_OPTION_WAVE_DISABLE, XTTCPS_CNT_CNTRL_EN_WAVE_MASK, + XTTCPS_CNT_CNTRL_OFFSET + }, + { + XTTCPS_OPTION_WAVE_POLARITY, XTTCPS_CNT_CNTRL_POL_WAVE_MASK, + XTTCPS_CNT_CNTRL_OFFSET + }, }; #define XTTCPS_NUM_TMRCTR_OPTIONS (sizeof(TmrCtrOptionsTable) / \ - sizeof(OptionsMap)) + sizeof(OptionsMap)) /*****************************************************************************/ /** @@ -100,48 +116,43 @@ s32 XTtcPs_SetOptions(XTtcPs *InstancePtr, u32 Options) u32 CountReg; u32 ClockReg; u32 Index; - s32 Status = XST_SUCCESS; - + /* + * Validate input arguments and in case of error conditions assert. + */ Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - ClockReg = XTtcPs_ReadReg(InstancePtr->Config.BaseAddress, - XTTCPS_CLK_CNTRL_OFFSET); + XTTCPS_CLK_CNTRL_OFFSET); CountReg = XTtcPs_ReadReg(InstancePtr->Config.BaseAddress, - XTTCPS_CNT_CNTRL_OFFSET); - + XTTCPS_CNT_CNTRL_OFFSET); /* * Loop through the options table, turning the option on or off * depending on whether the bit is set in the incoming options flag. */ for (Index = 0U; Index < XTTCPS_NUM_TMRCTR_OPTIONS; Index++) { if ((Options & TmrCtrOptionsTable[Index].Option) != (u32)0) { - if(TmrCtrOptionsTable[Index].Register == XTTCPS_CLK_CNTRL_OFFSET) { + if (TmrCtrOptionsTable[Index].Register == XTTCPS_CLK_CNTRL_OFFSET) { ClockReg |= TmrCtrOptionsTable[Index].Mask; } else { CountReg |= TmrCtrOptionsTable[Index].Mask; } } else { - if(TmrCtrOptionsTable[Index].Register == XTTCPS_CLK_CNTRL_OFFSET) { + if (TmrCtrOptionsTable[Index].Register == XTTCPS_CLK_CNTRL_OFFSET) { ClockReg &= ~TmrCtrOptionsTable[Index].Mask; } else { CountReg &= ~TmrCtrOptionsTable[Index].Mask; } } } - /* * Now write the registers. Leave it to the upper layers to restart the * device. */ - if (Status != (s32)XST_FAILURE ) { - XTtcPs_WriteReg(InstancePtr->Config.BaseAddress, - XTTCPS_CLK_CNTRL_OFFSET, ClockReg); - XTtcPs_WriteReg(InstancePtr->Config.BaseAddress, - XTTCPS_CNT_CNTRL_OFFSET, CountReg); - } - - return Status; + XTtcPs_WriteReg(InstancePtr->Config.BaseAddress, + XTTCPS_CLK_CNTRL_OFFSET, ClockReg); + XTtcPs_WriteReg(InstancePtr->Config.BaseAddress, + XTTCPS_CNT_CNTRL_OFFSET, CountReg); + return XST_SUCCESS; } /*****************************************************************************/ @@ -167,6 +178,9 @@ u32 XTtcPs_GetOptions(XTtcPs *InstancePtr) u32 Register; u32 Index; + /* + * Validate input arguments and in case of error conditions assert. + */ Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); @@ -180,14 +194,13 @@ u32 XTtcPs_GetOptions(XTtcPs *InstancePtr) * currently set. */ Register = XTtcPs_ReadReg(InstancePtr->Config.BaseAddress, - TmrCtrOptionsTable[Index]. - Register); + TmrCtrOptionsTable[Index]. + Register); if ((Register & TmrCtrOptionsTable[Index].Mask) != (u32)0) { OptionsFlag |= TmrCtrOptionsTable[Index].Option; } } - return OptionsFlag; } /** @} */ diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/ttcps/src/xttcps_selftest.c b/bsp_z7/ps7_cortexa9_0/libsrc/ttcps/src/xttcps_selftest.c index a0be259..f1a4676 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/ttcps/src/xttcps_selftest.c +++ b/bsp_z7/ps7_cortexa9_0/libsrc/ttcps/src/xttcps_selftest.c @@ -1,6 +1,6 @@ /****************************************************************************** * Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved. -* Copyright (c) 2022 Advanced Micro Devices, Inc. All Rights Reserved. +* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -21,6 +21,7 @@ * ----- ------ -------- --------------------------------------------- * 1.00a drg/jz 01/21/10 First release * 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance. +* 3.18 ml 09/08/23 Added comments to fix HIS COMF violations. * * ******************************************************************************/ @@ -65,6 +66,9 @@ s32 XTtcPs_SelfTest(XTtcPs *InstancePtr) s32 Status; u32 TempReg; + /* + * Validate input arguments and in case of error conditions assert. + */ Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); @@ -72,11 +76,10 @@ s32 XTtcPs_SelfTest(XTtcPs *InstancePtr) * All the TTC registers should be in their default state right now. */ TempReg = XTtcPs_ReadReg(InstancePtr->Config.BaseAddress, - XTTCPS_CNT_CNTRL_OFFSET); + XTTCPS_CNT_CNTRL_OFFSET); if (XTTCPS_CNT_CNTRL_RESET_VALUE != (u32)TempReg) { Status = XST_FAILURE; - } - else { + } else { Status = XST_SUCCESS; } return Status; diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/ttcps/src/xttcps_sinit.c b/bsp_z7/ps7_cortexa9_0/libsrc/ttcps/src/xttcps_sinit.c index 5d50de9..4b104b8 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/ttcps/src/xttcps_sinit.c +++ b/bsp_z7/ps7_cortexa9_0/libsrc/ttcps/src/xttcps_sinit.c @@ -1,6 +1,6 @@ /****************************************************************************** * Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved. -* Copyright (c) 2022 Advanced Micro Devices, Inc. All Rights Reserved. +* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -27,7 +27,9 @@ /***************************** Include Files *********************************/ #include "xttcps.h" +#ifndef SDT #include "xparameters.h" +#endif /************************** Constant Definitions *****************************/ @@ -38,7 +40,11 @@ /************************** Function Prototypes ******************************/ /************************** Variable Definitions *****************************/ +#ifndef SDT extern XTtcPs_Config XTtcPs_ConfigTable[XPAR_XTTCPS_NUM_INSTANCES]; +#else +extern XTtcPs_Config XTtcPs_ConfigTable[]; +#endif /*****************************************************************************/ /** @@ -56,6 +62,7 @@ extern XTtcPs_Config XTtcPs_ConfigTable[XPAR_XTTCPS_NUM_INSTANCES]; * @note None. * ******************************************************************************/ +#ifndef SDT XTtcPs_Config *XTtcPs_LookupConfig(u16 DeviceId) { XTtcPs_Config *CfgPtr = NULL; @@ -70,4 +77,21 @@ XTtcPs_Config *XTtcPs_LookupConfig(u16 DeviceId) return (XTtcPs_Config *)CfgPtr; } +#else +XTtcPs_Config *XTtcPs_LookupConfig(u32 BaseAddress) +{ + XTtcPs_Config *CfgPtr = NULL; + u32 Index; + + for (Index = 0U; XTtcPs_ConfigTable[Index].Name != NULL; Index++) { + if ((XTtcPs_ConfigTable[Index].BaseAddress == BaseAddress) || + !BaseAddress) { + CfgPtr = &XTtcPs_ConfigTable[Index]; + break; + } + } + + return (XTtcPs_Config *)CfgPtr; +} +#endif /** @} */ diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/uartps/src/xuartps.c b/bsp_z7/ps7_cortexa9_0/libsrc/uartps/src/xuartps.c index 86af54d..a5ec877 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/uartps/src/xuartps.c +++ b/bsp_z7/ps7_cortexa9_0/libsrc/uartps/src/xuartps.c @@ -1,6 +1,6 @@ /****************************************************************************** * Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved. -* Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. +* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -124,6 +124,11 @@ s32 XUartPs_CfgInitialize(XUartPs *InstancePtr, #endif InstancePtr->Config.ModemPinsConnected = Config->ModemPinsConnected; +#if defined(SDT) + InstancePtr->Config.IntrId = Config->IntrId; + InstancePtr->Config.IntrParent = Config->IntrParent; +#endif + /* Initialize other instance data to default values */ InstancePtr->Handler = (XUartPs_Handler)XUartPs_StubHandler; diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/uartps/src/xuartps.h b/bsp_z7/ps7_cortexa9_0/libsrc/uartps/src/xuartps.h index 20dd99f..89ed5fd 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/uartps/src/xuartps.h +++ b/bsp_z7/ps7_cortexa9_0/libsrc/uartps/src/xuartps.h @@ -1,6 +1,6 @@ /****************************************************************************** * Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved. -* Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. +* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -149,6 +149,7 @@ * 3.9 rna 12/03/19 Modified the XUARTPS_MAX_RATE macro. * 3.9 sd 02/06/20 Added clock support * 3.12 gm 11/04/22 Added timeout support using Xil_WaitForEvent +* 3.13 adk 14/04/23 Added support for system device-tree flow. * * * @@ -272,13 +273,23 @@ extern "C" { * This typedef contains configuration information for the device. */ typedef struct { +#ifndef SDT u16 DeviceId; /**< Unique ID of device */ +#else + char *Name; +#endif u32 BaseAddress; /**< Base address of device (IPIF) */ u32 InputClockHz;/**< Input clock frequency */ s32 ModemPinsConnected; /** Specifies whether modem pins are connected * to MIO or FMIO */ -#if defined (XCLOCKING) - u32 RefClk; /**< Input clock frequency */ +#if defined (XCLOCKING) || defined(SDT) + u32 RefClk; /**< Input clock frequency */ +#endif +#if defined(SDT) + u32 IntrId; /** Bits[11:0] Interrupt-id Bits[15:12] + * trigger type and level flags */ + UINTPTR IntrParent; /** Bit[0] Interrupt parent type Bit[64/32:1] + * Parent base address */ #endif } XUartPs_Config; @@ -444,7 +455,11 @@ typedef struct { /************************** Function Prototypes *****************************/ /* Static lookup function implemented in xuartps_sinit.c */ +#ifndef SDT XUartPs_Config *XUartPs_LookupConfig(u16 DeviceId); +#else +XUartPs_Config *XUartPs_LookupConfig(u32 BaseAddress); +#endif /* Interface functions implemented in xuartps.c */ s32 XUartPs_CfgInitialize(XUartPs *InstancePtr, diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/uartps/src/xuartps_hw.c b/bsp_z7/ps7_cortexa9_0/libsrc/uartps/src/xuartps_hw.c index ec5c088..6fde0e6 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/uartps/src/xuartps_hw.c +++ b/bsp_z7/ps7_cortexa9_0/libsrc/uartps/src/xuartps_hw.c @@ -1,6 +1,6 @@ /****************************************************************************** * Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved. -* Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. +* Copyright (C) 2022 - 2024 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -20,6 +20,7 @@ * 1.00 drg/jz 01/12/10 First Release * 1.05a hk 08/22/13 Added reset function * 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance. +* 4.00 sd 02/02/24 Added wait for transmission done function * * *****************************************************************************/ @@ -152,4 +153,39 @@ void XUartPs_ResetHw(u32 BaseAddress) (u32)XUARTPS_CR_STOPBRK)); } + +/****************************************************************************/ +/** +* +* This function waits for transmission to complete +* +* @return None +* +* @note None. +* +*****************************************************************************/ +void XUartPs_WaitTransmitDone(u32 BaseAddress) +{ + /* Wait until Transmitter FIFO is empty */ + while (!XUartPs_IsTransmitEmpty(BaseAddress)) { + ; + } + /* Wait until Transmitter state machine is In-Active */ + while (XUartPs_IsTransmitActive(BaseAddress)) { + ; + } +} + + +#ifdef SDT +#ifdef XPAR_STDIN_IS_UARTPS +void outbyte(char c) { + XUartPs_SendByte(STDOUT_BASEADDRESS, c); +} + +char inbyte(void) { + return XUartPs_RecvByte(STDIN_BASEADDRESS); +} +#endif +#endif /** @} */ diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/uartps/src/xuartps_hw.h b/bsp_z7/ps7_cortexa9_0/libsrc/uartps/src/xuartps_hw.h index 59d4ccf..f45d5c8 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/uartps/src/xuartps_hw.h +++ b/bsp_z7/ps7_cortexa9_0/libsrc/uartps/src/xuartps_hw.h @@ -1,6 +1,6 @@ /****************************************************************************** * Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved. -* Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. +* Copyright (C) 2022 - 2024 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -32,6 +32,8 @@ * 3.1 kvn 04/10/15 Modified code for latest RTL changes. * 3.6 ms 02/16/18 Updates flow control mode offset value in * modem control register. +* 4.0 sd 02/02/24 Added macros for transmission FIFO empty check +* and transmission active state check * * * @@ -48,6 +50,7 @@ extern "C" { #include "xil_types.h" #include "xil_assert.h" #include "xil_io.h" +#include "xstatus.h" /************************** Constant Definitions *****************************/ @@ -408,6 +411,36 @@ extern "C" { ((Xil_In32((BaseAddress) + XUARTPS_SR_OFFSET) & \ (u32)XUARTPS_SR_TXFULL) == (u32)XUARTPS_SR_TXFULL) +/****************************************************************************/ +/** +* Check if transmission FIFO is empty +* +* @return TRUE if the TX FIFO is empty, FALSE if Tx FIFO is not empty +* +* @note C-Style signature: +* u32 XUartPs_IsTransmitEmpty(u32 BaseAddress) +* +******************************************************************************/ +#define XUartPs_IsTransmitEmpty(BaseAddress) \ + ((Xil_In32((BaseAddress) + XUARTPS_SR_OFFSET) & \ + (u32)XUARTPS_SR_TXEMPTY) == (u32)XUARTPS_SR_TXEMPTY) + +/****************************************************************************/ +/** +* Check if transmission state machine is active +* +* @return TRUE if the TX state machine is active, FALSE if Tx state machine +* is In-active +* +* @note C-Style signature: +* u32 XUartPs_IsTransmitActive(u32 BaseAddress) +* +******************************************************************************/ +#define XUartPs_IsTransmitActive(BaseAddress) \ + ((Xil_In32((BaseAddress) + XUARTPS_SR_OFFSET) & \ + (u32)XUARTPS_SR_TACTIVE) == (u32)XUARTPS_SR_TACTIVE) + + /************************** Function Prototypes ******************************/ void XUartPs_SendByte(u32 BaseAddress, u8 Data); @@ -416,6 +449,8 @@ u8 XUartPs_RecvByte(u32 BaseAddress); void XUartPs_ResetHw(u32 BaseAddress); +void XUartPs_WaitTransmitDone(u32 BaseAddress); + /************************** Variable Definitions *****************************/ #ifdef __cplusplus diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/uartps/src/xuartps_sinit.c b/bsp_z7/ps7_cortexa9_0/libsrc/uartps/src/xuartps_sinit.c index de64a8c..50d95bc 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/uartps/src/xuartps_sinit.c +++ b/bsp_z7/ps7_cortexa9_0/libsrc/uartps/src/xuartps_sinit.c @@ -1,6 +1,6 @@ /****************************************************************************** * Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved. -* Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. +* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -28,7 +28,9 @@ /***************************** Include Files ********************************/ #include "xstatus.h" +#ifndef SDT #include "xparameters.h" +#endif #include "xuartps.h" /************************** Constant Definitions ****************************/ @@ -38,7 +40,12 @@ /***************** Macros (Inline Functions) Definitions ********************/ /************************** Variable Definitions ****************************/ +#ifndef SDT extern XUartPs_Config XUartPs_ConfigTable[XPAR_XUARTPS_NUM_INSTANCES]; +#else +extern XUartPs_Config XUartPs_ConfigTable[]; +#endif + /************************** Function Prototypes *****************************/ @@ -56,6 +63,7 @@ extern XUartPs_Config XUartPs_ConfigTable[XPAR_XUARTPS_NUM_INSTANCES]; * @note None. * ******************************************************************************/ +#ifndef SDT XUartPs_Config *XUartPs_LookupConfig(u16 DeviceId) { XUartPs_Config *CfgPtr = NULL; @@ -71,4 +79,21 @@ XUartPs_Config *XUartPs_LookupConfig(u16 DeviceId) return (XUartPs_Config *)CfgPtr; } +#else +XUartPs_Config *XUartPs_LookupConfig(u32 BaseAddress) +{ + XUartPs_Config *CfgPtr = NULL; + u32 Index; + + for (Index = 0U; XUartPs_ConfigTable[Index].Name != NULL; Index++) { + if ((XUartPs_ConfigTable[Index].BaseAddress == BaseAddress) || + !BaseAddress) { + CfgPtr = &XUartPs_ConfigTable[Index]; + break; + } + } + + return (XUartPs_Config *)CfgPtr; +} +#endif /** @} */ diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/usbps/src/xusbps.c b/bsp_z7/ps7_cortexa9_0/libsrc/usbps/src/xusbps.c index c3dabfc..a5c5b21 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/usbps/src/xusbps.c +++ b/bsp_z7/ps7_cortexa9_0/libsrc/usbps/src/xusbps.c @@ -1,12 +1,13 @@ /****************************************************************************** * Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved. +* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ /******************************************************************************/ /** * @file xusbps.c -* @addtogroup usbps_v2_7 +* @addtogroup usbps Overview * @{ * * The XUsbPs driver. Functions in this file are the minimum required @@ -74,7 +75,7 @@ * ******************************************************************************/ int XUsbPs_CfgInitialize(XUsbPs *InstancePtr, - const XUsbPs_Config *ConfigPtr, u32 VirtBaseAddress) + const XUsbPs_Config *ConfigPtr, u32 VirtBaseAddress) { Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(ConfigPtr != NULL); @@ -118,16 +119,16 @@ void XUsbPs_DeviceReset(XUsbPs *InstancePtr) * itself. */ XUsbPs_WriteReg(InstancePtr->Config.BaseAddress, XUSBPS_EPSTAT_OFFSET, - XUsbPs_ReadReg(InstancePtr->Config.BaseAddress, - XUSBPS_EPSTAT_OFFSET)); + XUsbPs_ReadReg(InstancePtr->Config.BaseAddress, + XUSBPS_EPSTAT_OFFSET)); /* Clear all the endpoint complete status bits by reading the * XUSBPS_EPCOMPL_OFFSET register and writings its value back * to itself. */ XUsbPs_WriteReg(InstancePtr->Config.BaseAddress, XUSBPS_EPCOMPL_OFFSET, - XUsbPs_ReadReg(InstancePtr->Config.BaseAddress, - XUSBPS_EPCOMPL_OFFSET)); + XUsbPs_ReadReg(InstancePtr->Config.BaseAddress, + XUSBPS_EPCOMPL_OFFSET)); /* Cancel all endpoint prime status by waiting until all bits * in XUSBPS_EPPRIME_OFFSET are 0 and then writing 0xFFFFFFFF @@ -137,25 +138,25 @@ void XUsbPs_DeviceReset(XUsbPs *InstancePtr) */ Timeout = XUSBPS_TIMEOUT_COUNTER; while ((XUsbPs_ReadReg(InstancePtr->Config.BaseAddress, - XUSBPS_EPPRIME_OFFSET) & - XUSBPS_EP_ALL_MASK) && --Timeout) { + XUSBPS_EPPRIME_OFFSET) & + XUSBPS_EP_ALL_MASK) && --Timeout) { /* NOP */ } XUsbPs_WriteReg(InstancePtr->Config.BaseAddress, - XUSBPS_EPFLUSH_OFFSET, 0xFFFFFFFF); + XUSBPS_EPFLUSH_OFFSET, 0xFFFFFFFF); XUsbPs_Stop(InstancePtr); /* Write to CR register for controller reset */ - XUsbPs_WriteReg(InstancePtr->Config.BaseAddress, XUSBPS_CMD_OFFSET, - XUsbPs_ReadReg(InstancePtr->Config.BaseAddress, - XUSBPS_CMD_OFFSET) | XUSBPS_CMD_RST_MASK); + XUsbPs_WriteReg(InstancePtr->Config.BaseAddress, XUSBPS_CMD_OFFSET, + XUsbPs_ReadReg(InstancePtr->Config.BaseAddress, + XUSBPS_CMD_OFFSET) | XUSBPS_CMD_RST_MASK); /* Wait for reset to finish, hardware clears the reset bit once done */ Timeout = 1000000; - while((XUsbPs_ReadReg(InstancePtr->Config.BaseAddress, - XUSBPS_CMD_OFFSET) & - XUSBPS_CMD_RST_MASK) && --Timeout) { + while ((XUsbPs_ReadReg(InstancePtr->Config.BaseAddress, + XUSBPS_CMD_OFFSET) & + XUSBPS_CMD_RST_MASK) && --Timeout) { /* NOP */ } } @@ -196,14 +197,14 @@ int XUsbPs_Reset(XUsbPs *InstancePtr) * system) this can lead to _very_ long Timeout periods. */ XUsbPs_WriteReg(InstancePtr->Config.BaseAddress, - XUSBPS_CMD_OFFSET, XUSBPS_CMD_RST_MASK); + XUSBPS_CMD_OFFSET, XUSBPS_CMD_RST_MASK); /* Wait for the RESET bit to be cleared by HW. */ Timeout = XUSBPS_TIMEOUT_COUNTER; while ((XUsbPs_ReadReg(InstancePtr->Config.BaseAddress, - XUSBPS_CMD_OFFSET) & - XUSBPS_CMD_RST_MASK) && --Timeout) { + XUSBPS_CMD_OFFSET) & + XUSBPS_CMD_RST_MASK) && --Timeout) { /* NOP */ } @@ -320,8 +321,8 @@ int XUsbPs_SetDeviceAddress(XUsbPs *InstancePtr, u8 Address) Xil_AssertNonvoid(InstancePtr != NULL); if ((InstancePtr->AppData != NULL) && - (InstancePtr->AppData->State == - XUSBPS_STATE_CONFIGURED)) { + (InstancePtr->AppData->State == + XUSBPS_STATE_CONFIGURED)) { return XST_FAILURE; } @@ -335,15 +336,16 @@ int XUsbPs_SetDeviceAddress(XUsbPs *InstancePtr, u8 Address) * after an IN occurred and has been ACKed on the endpoint. */ XUsbPs_WriteReg(InstancePtr->Config.BaseAddress, - XUSBPS_DEVICEADDR_OFFSET, - (Address << XUSBPS_DEVICEADDR_ADDR_SHIFT) | - XUSBPS_DEVICEADDR_DEVICEAADV_MASK); + XUSBPS_DEVICEADDR_OFFSET, + (Address << XUSBPS_DEVICEADDR_ADDR_SHIFT) | + XUSBPS_DEVICEADDR_DEVICEAADV_MASK); if (InstancePtr->AppData != NULL) { - if (Address) + if (Address) { InstancePtr->AppData->State = XUSBPS_STATE_ADDRESS; - else + } else { InstancePtr->AppData->State = XUSBPS_STATE_DEFAULT; + } } return XST_SUCCESS; } diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/usbps/src/xusbps.h b/bsp_z7/ps7_cortexa9_0/libsrc/usbps/src/xusbps.h index 5c01051..d215b77 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/usbps/src/xusbps.h +++ b/bsp_z7/ps7_cortexa9_0/libsrc/usbps/src/xusbps.h @@ -1,5 +1,6 @@ /****************************************************************************** * Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved. +* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -7,7 +8,7 @@ /** * * @file xusbps.h -* @addtogroup usbps_v2_7 +* @addtogroup usbps Overview * @{ * @details * @@ -163,6 +164,7 @@ * examples. * 2.5 pm 02/20/20 Added ISO support for usb 2.0 and ch9 common framework * calls. + * 2.8 pm 07/07/23 Added support for system device-tree flow. * * ******************************************************************************/ @@ -256,13 +258,13 @@ extern "C" { #define XUSBPS_EP_STS_CONTROLLER_STATE 2 /**< Current controller state. */ /* @} */ - /* - * Device Speeds - */ - #define XUSBPS_SPEED_UNKNOWN 0U - #define XUSBPS_SPEED_LOW 1U - #define XUSBPS_SPEED_FULL 2U - #define XUSBPS_SPEED_HIGH 3U +/* + * Device Speeds + */ +#define XUSBPS_SPEED_UNKNOWN 0U +#define XUSBPS_SPEED_LOW 1U +#define XUSBPS_SPEED_FULL 2U +#define XUSBPS_SPEED_HIGH 3U /** * @name USB Default alternate setting @@ -272,15 +274,15 @@ extern "C" { #define XUSBPS_DEFAULT_ALT_SETTING 0 /**< The default alternate setting is 0 */ /* @} */ - /* - * Device States - */ - #define XUSBPS_STATE_ATTACHED 0U - #define XUSBPS_STATE_POWERED 1U - #define XUSBPS_STATE_DEFAULT 2U - #define XUSBPS_STATE_ADDRESS 3U - #define XUSBPS_STATE_CONFIGURED 4U - #define XUSBPS_STATE_SUSPENDED 5U +/* + * Device States + */ +#define XUSBPS_STATE_ATTACHED 0U +#define XUSBPS_STATE_POWERED 1U +#define XUSBPS_STATE_DEFAULT 2U +#define XUSBPS_STATE_ADDRESS 3U +#define XUSBPS_STATE_CONFIGURED 4U +#define XUSBPS_STATE_SUSPENDED 5U /** * @name Endpoint event types @@ -290,11 +292,11 @@ extern "C" { * @{ */ #define XUSBPS_EP_EVENT_SETUP_DATA_RECEIVED 0x01 - /**< Setup data has been received on the endpoint. */ +/**< Setup data has been received on the endpoint. */ #define XUSBPS_EP_EVENT_DATA_RX 0x02 - /**< Data frame has been received on the endpoint. */ +/**< Data frame has been received on the endpoint. */ #define XUSBPS_EP_EVENT_DATA_TX 0x03 - /**< Data frame has been sent on the endpoint. */ +/**< Data frame has been sent on the endpoint. */ /* @} */ @@ -303,7 +305,7 @@ extern "C" { * @{ */ #define XUSBPS_MAX_PACKET_SIZE 1024 - /**< Maximum value can be put into the queue head */ +/**< Maximum value can be put into the queue head */ /* @} */ /**************************** Type Definitions *******************************/ @@ -320,7 +322,7 @@ extern "C" { * was registered. */ typedef void (*XUsbPs_EpHandlerFunc)(void *CallBackRef, - u8 EpNum, u8 EventType, void *Data); + u8 EpNum, u8 EventType, void *Data); /****************************************************************************** * This data type defines the callback function to be used for Endpoint @@ -369,24 +371,24 @@ typedef u8 XUsbPs_dTD[XUSBPS_dTD_ALIGN]; */ typedef struct { XUsbPs_dQH *dQH; - /**< Pointer to the Queue Head structure of the endpoint. */ + /**< Pointer to the Queue Head structure of the endpoint. */ XUsbPs_dTD *dTDs; - /**< Pointer to the first dTD of the dTD list for this - * endpoint. */ + /**< Pointer to the first dTD of the dTD list for this + * endpoint. */ XUsbPs_dTD *dTDCurr; - /**< Buffer to the currently processed descriptor. */ + /**< Buffer to the currently processed descriptor. */ u8 *dTDBufs; - /**< Pointer to the first buffer of the buffer list for this - * endpoint. */ + /**< Pointer to the first buffer of the buffer list for this + * endpoint. */ XUsbPs_EpHandlerFunc HandlerFunc; XUsbPs_EpIsoHandlerFunc HandlerIsoFunc; - /**< Handler function for this endpoint. */ + /**< Handler function for this endpoint. */ void *HandlerRef; - /**< User data reference for the handler. */ + /**< User data reference for the handler. */ u32 RequestedBytes; /**< RequestedBytes for transfer */ u32 BytesTxed; /**< Actual Bytes transferred */ u8 *BufferPtr; /**< Buffer location */ @@ -400,23 +402,23 @@ typedef struct { */ typedef struct { XUsbPs_dQH *dQH; - /**< Pointer to the Queue Head structure of the endpoint. */ + /**< Pointer to the Queue Head structure of the endpoint. */ XUsbPs_dTD *dTDs; - /**< List of pointers to the Transfer Descriptors of the - * endpoint. */ + /**< List of pointers to the Transfer Descriptors of the + * endpoint. */ XUsbPs_dTD *dTDHead; - /**< Buffer to the next available descriptor in the list. */ + /**< Buffer to the next available descriptor in the list. */ XUsbPs_dTD *dTDTail; - /**< Buffer to the last unsent descriptor in the list*/ + /**< Buffer to the last unsent descriptor in the list*/ XUsbPs_EpHandlerFunc HandlerFunc; XUsbPs_EpIsoHandlerFunc HandlerIsoFunc; - /**< Handler function for this endpoint. */ + /**< Handler function for this endpoint. */ void *HandlerRef; - /**< User data reference for the handler. */ + /**< User data reference for the handler. */ u32 RequestedBytes; /**< RequestedBytes for transfer */ u32 BytesTxed; /**< Actual Bytes transferred */ u8 *BufferPtr; /**< Buffer location */ @@ -462,21 +464,21 @@ XUsbPs_SetupData; */ typedef struct { u32 Type; - /**< Endpoint type: - - XUSBPS_EP_TYPE_CONTROL - - XUSBPS_EP_TYPE_ISOCHRONOUS - - XUSBPS_EP_TYPE_BULK - - XUSBPS_EP_TYPE_INTERRUPT */ + /**< Endpoint type: + - XUSBPS_EP_TYPE_CONTROL + - XUSBPS_EP_TYPE_ISOCHRONOUS + - XUSBPS_EP_TYPE_BULK + - XUSBPS_EP_TYPE_INTERRUPT */ u32 NumBufs; - /**< Number of buffers to be handled by this endpoint. */ + /**< Number of buffers to be handled by this endpoint. */ u32 BufSize; - /**< Buffer size. Only relevant for OUT (receive) Endpoints. */ + /**< Buffer size. Only relevant for OUT (receive) Endpoints. */ u16 MaxPacketSize; - /**< Maximum packet size for this endpoint. This number will - * define the maximum number of bytes sent on the wire per - * transaction. Range: 0..1024 */ + /**< Maximum packet size for this endpoint. This number will + * define the maximum number of bytes sent on the wire per + * transaction. Range: 0..1024 */ } XUsbPs_EpSetup; @@ -502,7 +504,7 @@ typedef struct { in the core. */ XUsbPs_EpConfig EpCfg[XUSBPS_MAX_ENDPOINTS]; - /**< List of endpoint configurations. */ + /**< List of endpoint configurations. */ u32 DMAMemPhys; /**< Physical base address of DMAable memory @@ -518,7 +520,7 @@ typedef struct { * structure which is allocated by the caller. */ XUsbPs_Endpoint Ep[XUSBPS_MAX_ENDPOINTS]; - /**< List of endpoint metadata structures. */ + /**< List of endpoint metadata structures. */ u32 PhysAligned; /**< 64 byte aligned base address of the DMA memory block. Will be computed and set by @@ -536,8 +538,17 @@ typedef struct { * XUsbPs_ConfigureDevice() function call */ typedef struct { +#ifndef SDT u16 DeviceID; /**< Unique ID of controller. */ +#else + char *Name; /**< Unique Name of controller */ +#endif u32 BaseAddress; /**< Core register base address. */ +#ifdef SDT + u16 IntrId; /** Bits[11:0] Interrupt-id Bits[15:12] trigger type */ + /** level flags */ + UINTPTR IntrParent; /** Bit[0] Interrupt parent type Bit[64/32:1] */ +#endif } XUsbPs_Config; typedef XUsbPs_Config Usb_Config; @@ -556,7 +567,7 @@ struct Usb_DevData { */ typedef struct { XUsbPs_SetupData SetupData; - /**< Setup Packet buffer */ + /**< Setup Packet buffer */ XUsbPs_Config Config; /**< Configuration structure */ int CurrentAltSetting; /**< Current alternative setting of interface */ @@ -573,15 +584,15 @@ typedef struct { * XUsbPs_ConfigureDevice() function call. */ XUsbPs_DeviceConfig DeviceConfig; - /**< Configuration for the DEVICE mode. */ + /**< Configuration for the DEVICE mode. */ XUsbPs_IntrHandlerFunc HandlerFunc; - /**< Handler function for the controller. */ + /**< Handler function for the controller. */ void *HandlerRef; - /**< User data reference for the handler. */ + /**< User data reference for the handler. */ u32 HandlerMask; - /**< User interrupt mask. Defines which interrupts will cause - * the callback to be called. */ + /**< User interrupt mask. Defines which interrupts will cause + * the callback to be called. */ struct Usb_DevData *AppData; u8 IsConfigDone; void *data_ptr; /* pointer for storing applications data */ @@ -655,7 +666,7 @@ typedef struct { ******************************************************************************/ #define XUsbPs_ForceFS(InstancePtr) \ XUsbPs_SetBits(InstancePtr, XUSBPS_PORTSCR1_OFFSET, \ - XUSBPS_PORTSCR_PFSC_MASK) + XUSBPS_PORTSCR_PFSC_MASK) /*****************************************************************************/ @@ -671,14 +682,14 @@ typedef struct { * ******************************************************************************/ #define XUsbPs_StartTimer0(InstancePtr, Interval) \ -{ \ - XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress, \ - XUSBPS_TIMER0_LD_OFFSET, (Interval)); \ - XUsbPs_SetBits(InstancePtr, XUSBPS_TIMER0_CTL_OFFSET, \ - XUSBPS_TIMER_RUN_MASK | \ - XUSBPS_TIMER_RESET_MASK | \ - XUSBPS_TIMER_REPEAT_MASK); \ -} \ + { \ + XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress, \ + XUSBPS_TIMER0_LD_OFFSET, (Interval)); \ + XUsbPs_SetBits(InstancePtr, XUSBPS_TIMER0_CTL_OFFSET, \ + XUSBPS_TIMER_RUN_MASK | \ + XUSBPS_TIMER_RESET_MASK | \ + XUSBPS_TIMER_REPEAT_MASK); \ + } \ /*****************************************************************************/ @@ -693,7 +704,7 @@ typedef struct { ******************************************************************************/ #define XUsbPs_StopTimer0(InstancePtr) \ XUsbPs_ClrBits(InstancePtr, XUSBPS_TIMER0_CTL_OFFSET, \ - XUSBPS_TIMER_RUN_MASK) + XUSBPS_TIMER_RUN_MASK) /*****************************************************************************/ @@ -708,8 +719,8 @@ typedef struct { ******************************************************************************/ #define XUsbPs_ReadTimer0(InstancePtr) \ XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress, \ - XUSBPS_TIMER0_CTL_OFFSET) & \ - XUSBPS_TIMER_COUNTER_MASK + XUSBPS_TIMER0_CTL_OFFSET) & \ + XUSBPS_TIMER_COUNTER_MASK /*****************************************************************************/ @@ -724,7 +735,7 @@ typedef struct { ******************************************************************************/ #define XUsbPs_RemoteWakeup(InstancePtr) \ XUsbPs_SetBits(InstancePtr, XUSBPS_PORTSCR1_OFFSET, \ - XUSBPS_PORTSCR_FPR_MASK) + XUSBPS_PORTSCR_FPR_MASK) /****************************************************************************** @@ -749,8 +760,8 @@ typedef struct { ******************************************************************************/ #define XUsbPs_EpEnable(InstancePtr, EpNum, Dir) \ XUsbPs_SetBits(InstancePtr, XUSBPS_EPCRn_OFFSET(EpNum), \ - ((Dir) & XUSBPS_EP_DIRECTION_OUT ? XUSBPS_EPCR_RXE_MASK : 0) | \ - ((Dir) & XUSBPS_EP_DIRECTION_IN ? XUSBPS_EPCR_TXE_MASK : 0)) + ((Dir) & XUSBPS_EP_DIRECTION_OUT ? XUSBPS_EPCR_RXE_MASK : 0) | \ + ((Dir) & XUSBPS_EP_DIRECTION_IN ? XUSBPS_EPCR_TXE_MASK : 0)) /*****************************************************************************/ @@ -770,8 +781,8 @@ typedef struct { ******************************************************************************/ #define XUsbPs_EpDisable(InstancePtr, EpNum, Dir) \ XUsbPs_ClrBits(InstancePtr, XUSBPS_EPCRn_OFFSET(EpNum), \ - ((Dir) & XUSBPS_EP_DIRECTION_OUT ? XUSBPS_EPCR_RXE_MASK : 0) | \ - ((Dir) & XUSBPS_EP_DIRECTION_IN ? XUSBPS_EPCR_TXE_MASK : 0)) + ((Dir) & XUSBPS_EP_DIRECTION_OUT ? XUSBPS_EPCR_RXE_MASK : 0) | \ + ((Dir) & XUSBPS_EP_DIRECTION_IN ? XUSBPS_EPCR_TXE_MASK : 0)) /*****************************************************************************/ @@ -792,8 +803,8 @@ typedef struct { ******************************************************************************/ #define XUsbPs_EpStall(InstancePtr, EpNum, Dir) \ XUsbPs_SetBits(InstancePtr, XUSBPS_EPCRn_OFFSET(EpNum), \ - ((Dir) & XUSBPS_EP_DIRECTION_OUT ? XUSBPS_EPCR_RXS_MASK : 0) | \ - ((Dir) & XUSBPS_EP_DIRECTION_IN ? XUSBPS_EPCR_TXS_MASK : 0)) + ((Dir) & XUSBPS_EP_DIRECTION_OUT ? XUSBPS_EPCR_RXS_MASK : 0) | \ + ((Dir) & XUSBPS_EP_DIRECTION_IN ? XUSBPS_EPCR_TXS_MASK : 0)) /*****************************************************************************/ @@ -813,8 +824,8 @@ typedef struct { ******************************************************************************/ #define XUsbPs_EpUnStall(InstancePtr, EpNum, Dir) \ XUsbPs_ClrBits(InstancePtr, XUSBPS_EPCRn_OFFSET(EpNum), \ - ((Dir) & XUSBPS_EP_DIRECTION_OUT ? XUSBPS_EPCR_RXS_MASK : 0) | \ - ((Dir) & XUSBPS_EP_DIRECTION_IN ? XUSBPS_EPCR_TXS_MASK : 0)) + ((Dir) & XUSBPS_EP_DIRECTION_OUT ? XUSBPS_EPCR_RXS_MASK : 0) | \ + ((Dir) & XUSBPS_EP_DIRECTION_IN ? XUSBPS_EPCR_TXS_MASK : 0)) /*****************************************************************************/ @@ -834,8 +845,8 @@ typedef struct { ******************************************************************************/ #define XUsbPs_EpFlush(InstancePtr, EpNum, Dir) \ XUsbPs_SetBits(InstancePtr, XUSBPS_EPFLUSH_OFFSET, \ - 1 << (EpNum + ((Dir) & XUSBPS_EP_DIRECTION_OUT ? \ - XUSBPS_EPFLUSH_RX_SHIFT:XUSBPS_EPFLUSH_TX_SHIFT))) \ + 1 << (EpNum + ((Dir) & XUSBPS_EP_DIRECTION_OUT ? \ + XUSBPS_EPFLUSH_RX_SHIFT:XUSBPS_EPFLUSH_TX_SHIFT))) \ /*****************************************************************************/ /** @@ -849,7 +860,7 @@ typedef struct { * ******************************************************************************/ #define XUsbPs_IntrEnable(InstancePtr, IntrMask) \ - XUsbPs_SetBits(InstancePtr, XUSBPS_IER_OFFSET, IntrMask) + XUsbPs_SetBits(InstancePtr, XUSBPS_IER_OFFSET, IntrMask) /*****************************************************************************/ @@ -865,7 +876,7 @@ typedef struct { * ******************************************************************************/ #define XUsbPs_IntrDisable(InstancePtr, IntrMask) \ - XUsbPs_ClrBits(InstancePtr, XUSBPS_IER_OFFSET, IntrMask) + XUsbPs_ClrBits(InstancePtr, XUSBPS_IER_OFFSET, IntrMask) /*****************************************************************************/ @@ -914,7 +925,7 @@ typedef struct { ******************************************************************************/ #define XUsbPs_NakIntrClear(InstancePtr, NakIntrMask) \ XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress, \ - XUSBPS_EPNAKISR_OFFSET, NakIntrMask) + XUSBPS_EPNAKISR_OFFSET, NakIntrMask) @@ -940,8 +951,8 @@ typedef struct { * ******************************************************************************/ #define XUsbPs_SetIntrThreshold(InstancePtr, Threshold) \ - XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress, \ - XUSBPS_CMD_OFFSET, (Threshold))\ + XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress, \ + XUSBPS_CMD_OFFSET, (Threshold))\ /*****************************************************************************/ @@ -955,8 +966,8 @@ typedef struct { * ******************************************************************************/ #define XUsbPs_SetSetupTripwire(InstancePtr) \ - XUsbPs_SetBits(InstancePtr, XUSBPS_CMD_OFFSET, \ - XUSBPS_CMD_SUTW_MASK) + XUsbPs_SetBits(InstancePtr, XUSBPS_CMD_OFFSET, \ + XUSBPS_CMD_SUTW_MASK) /*****************************************************************************/ @@ -970,8 +981,8 @@ typedef struct { * ******************************************************************************/ #define XUsbPs_ClrSetupTripwire(InstancePtr) \ - XUsbPs_ClrBits(InstancePtr, XUSBPS_CMD_OFFSET, \ - XUSBPS_CMD_SUTW_MASK) + XUsbPs_ClrBits(InstancePtr, XUSBPS_CMD_OFFSET, \ + XUSBPS_CMD_SUTW_MASK) /*****************************************************************************/ @@ -989,9 +1000,9 @@ typedef struct { * ******************************************************************************/ #define XUsbPs_SetupTripwireIsSet(InstancePtr) \ - (XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress, \ - XUSBPS_CMD_OFFSET) & \ - XUSBPS_CMD_SUTW_MASK ? TRUE : FALSE) + (XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress, \ + XUSBPS_CMD_OFFSET) & \ + XUSBPS_CMD_SUTW_MASK ? TRUE : FALSE) /****************************************************************************** @@ -1015,8 +1026,8 @@ typedef struct { *****************************************************************************/ #define XUsbPs_SetBits(InstancePtr, RegOffset, Bits) \ XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress, RegOffset, \ - XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress, \ - RegOffset) | (Bits)); + XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress, \ + RegOffset) | (Bits)); /****************************************************************************/ @@ -1037,8 +1048,8 @@ typedef struct { *****************************************************************************/ #define XUsbPs_ClrBits(InstancePtr, RegOffset, Bits) \ XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress, RegOffset, \ - XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress, \ - RegOffset) & ~(Bits)); + XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress, \ + RegOffset) & ~(Bits)); /************************** Function Prototypes ******************************/ @@ -1049,10 +1060,10 @@ typedef struct { * Implemented in file xusbps.c */ int XUsbPs_CfgInitialize(XUsbPs *InstancePtr, - const XUsbPs_Config *ConfigPtr, u32 BaseAddress); + const XUsbPs_Config *ConfigPtr, u32 BaseAddress); int XUsbPs_ConfigureDevice(XUsbPs *InstancePtr, - const XUsbPs_DeviceConfig *CfgPtr); + const XUsbPs_DeviceConfig *CfgPtr); /** * Common functions used for DEVICE/HOST mode. @@ -1086,23 +1097,23 @@ int XUsbPs_RequestHostResume(const XUsbPs *InstancePtr); int XUsbPs_EpBufferSend(XUsbPs *InstancePtr, u8 EpNum, const u8 *BufferPtr, u32 BufferLen); int XUsbPs_EpBufferSendWithZLT(XUsbPs *InstancePtr, u8 EpNum, - const u8 *BufferPtr, u32 BufferLen); + const u8 *BufferPtr, u32 BufferLen); int XUsbPs_EpBufferReceive(XUsbPs *InstancePtr, u8 EpNum, - u8 **BufferPtr, u32 *BufferLenPtr, u32 *Handle); + u8 **BufferPtr, u32 *BufferLenPtr, u32 *Handle); void XUsbPs_EpBufferRelease(u32 Handle); int XUsbPs_EpSetHandler(XUsbPs *InstancePtr, u8 EpNum, u8 Direction, XUsbPs_EpHandlerFunc CallBackFunc, void *CallBackRef); s32 XUsbPs_EpSetIsoHandler(XUsbPs *InstancePtr, u8 EpNum, u8 Direction, - XUsbPs_EpIsoHandlerFunc CallBackFunc); + XUsbPs_EpIsoHandlerFunc CallBackFunc); int XUsbPs_EpGetSetupData(XUsbPs *InstancePtr, int EpNum, - XUsbPs_SetupData *SetupDataPtr); + XUsbPs_SetupData *SetupDataPtr); int XUsbPs_EpPrime(XUsbPs *InstancePtr, u8 EpNum, u8 Direction); int XUsbPs_ReconfigureEp(XUsbPs *InstancePtr, XUsbPs_DeviceConfig *CfgPtr, - int EpNum, unsigned short NewDirection, int DirectionChanged); + int EpNum, unsigned short NewDirection, int DirectionChanged); /* * Interrupt handling functions @@ -1112,17 +1123,21 @@ int XUsbPs_ReconfigureEp(XUsbPs *InstancePtr, XUsbPs_DeviceConfig *CfgPtr, void XUsbPs_IntrHandler(void *InstancePtr); int XUsbPs_IntrSetHandler(XUsbPs *InstancePtr, - XUsbPs_IntrHandlerFunc CallBackFunc, - void *CallBackRef, u32 Mask); + XUsbPs_IntrHandlerFunc CallBackFunc, + void *CallBackRef, u32 Mask); void XUsbPs_EpGetData(XUsbPs *InstancePtr, u8 EpNum, u32 BufferLen); s32 XUsbPs_EpDataBufferReceive(XUsbPs *InstancePtr, u8 EpNum, - u8 *BufferPtr, u32 BufferLen); + u8 *BufferPtr, u32 BufferLen); /* * Helper functions for static configuration. * Implemented in xusbps_sinit.c */ +#ifndef SDT XUsbPs_Config *XUsbPs_LookupConfig(u16 DeviceId); +#else +XUsbPs_Config *XUsbPs_LookupConfig(u32 BaseAddress); +#endif #ifdef __cplusplus } diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/usbps/src/xusbps_endpoint.c b/bsp_z7/ps7_cortexa9_0/libsrc/usbps/src/xusbps_endpoint.c index a22510e..de7b77e 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/usbps/src/xusbps_endpoint.c +++ b/bsp_z7/ps7_cortexa9_0/libsrc/usbps/src/xusbps_endpoint.c @@ -1,12 +1,13 @@ /****************************************************************************** * Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved. +* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ /******************************************************************************/ /** * @file xusbps_endpoint.c -* @addtogroup usbps_v2_7 +* @addtogroup usbps Overview * @{ * * Endpoint specific function implementations. @@ -22,7 +23,7 @@ * 1.03a nm 09/21/12 Fixed CR#678977. Added proper sequence for setup packet * handling. * 1.04a nm 11/02/12 Fixed CR#683931. Mult bits are set properly in dQH. - * 2.00a kpc 04/03/14 Fixed CR#777763. Updated the macro names + * 2.00a kpc 04/03/14 Fixed CR#777763. Updated the macro names * 2.1 kpc 04/28/14 Added XUsbPs_EpBufferSendWithZLT api and merged common * code to XUsbPs_EpQueueRequest. * 2.3 bss 01/19/16 Modified XUsbPs_EpQueueRequest function to fix CR#873972 @@ -52,7 +53,7 @@ static void XUsbPs_EpListInit(XUsbPs_DeviceConfig *DevCfgPtr); static void XUsbPs_dQHInit(XUsbPs_DeviceConfig *DevCfgPtr); static int XUsbPs_dTDInit(XUsbPs_DeviceConfig *DevCfgPtr); static int XUsbPs_dTDAttachBuffer(XUsbPs_dTD *dTDPtr, - const u8 *BufferPtr, u32 BufferLen); + const u8 *BufferPtr, u32 BufferLen); static void XUsbPs_dQHSetMaxPacketLenISO(XUsbPs_dQH *dQHPtr, u32 Len); @@ -60,11 +61,11 @@ static void XUsbPs_dQHSetMaxPacketLenISO(XUsbPs_dQH *dQHPtr, u32 Len); * request. */ static void XUsbPs_dQHReinitEp(XUsbPs_DeviceConfig *DevCfgPtr, - int EpNum, unsigned short NewDirection); + int EpNum, unsigned short NewDirection); static int XUsbPs_dTDReinitEp(XUsbPs_DeviceConfig *DevCfgPtr, - int EpNum, unsigned short NewDirection); + int EpNum, unsigned short NewDirection); static int XUsbPs_EpQueueRequest(XUsbPs *InstancePtr, u8 EpNum, - const u8 *BufferPtr, u32 BufferLen, u8 ReqZero); + const u8 *BufferPtr, u32 BufferLen, u8 ReqZero); /******************************* Functions ************************************/ @@ -92,7 +93,7 @@ static int XUsbPs_EpQueueRequest(XUsbPs *InstancePtr, u8 EpNum, * ******************************************************************************/ int XUsbPs_ConfigureDevice(XUsbPs *InstancePtr, - const XUsbPs_DeviceConfig *CfgPtr) + const XUsbPs_DeviceConfig *CfgPtr) { int Status; u32 ModeValue = 0x0; @@ -107,8 +108,8 @@ int XUsbPs_ConfigureDevice(XUsbPs *InstancePtr, /* Align the buffer to a 2048 byte (XUSBPS_dQH_BASE_ALIGN) boundary.*/ InstancePtr->DeviceConfig.PhysAligned = (InstancePtr->DeviceConfig.DMAMemPhys + - XUSBPS_dQH_BASE_ALIGN) & - ~(XUSBPS_dQH_BASE_ALIGN -1); + XUSBPS_dQH_BASE_ALIGN) & + ~(XUSBPS_dQH_BASE_ALIGN - 1); /* Initialize the endpoint pointer list data structure. */ XUsbPs_EpListInit(&InstancePtr->DeviceConfig); @@ -131,8 +132,8 @@ int XUsbPs_ConfigureDevice(XUsbPs *InstancePtr, /* Set the Queue Head List address. */ XUsbPs_WriteReg(InstancePtr->Config.BaseAddress, - XUSBPS_EPLISTADDR_OFFSET, - InstancePtr->DeviceConfig.PhysAligned); + XUSBPS_EPLISTADDR_OFFSET, + InstancePtr->DeviceConfig.PhysAligned); /* Set the USB mode register to configure DEVICE mode. * @@ -144,10 +145,10 @@ int XUsbPs_ConfigureDevice(XUsbPs *InstancePtr, ModeValue = XUSBPS_MODE_CM_DEVICE_MASK | XUSBPS_MODE_SLOM_MASK; XUsbPs_WriteReg(InstancePtr->Config.BaseAddress, - XUSBPS_MODE_OFFSET, ModeValue); + XUSBPS_MODE_OFFSET, ModeValue); XUsbPs_SetBits(InstancePtr, XUSBPS_OTGCSR_OFFSET, - XUSBPS_OTGSC_OT_MASK); + XUSBPS_OTGSC_OT_MASK); return XST_SUCCESS; } @@ -169,13 +170,13 @@ int XUsbPs_ConfigureDevice(XUsbPs *InstancePtr, * ******************************************************************************/ int XUsbPs_EpBufferSend(XUsbPs *InstancePtr, u8 EpNum, - const u8 *BufferPtr, u32 BufferLen) + const u8 *BufferPtr, u32 BufferLen) { Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(EpNum < InstancePtr->DeviceConfig.NumEndpoints); return XUsbPs_EpQueueRequest(InstancePtr, EpNum, BufferPtr, - BufferLen, FALSE); + BufferLen, FALSE); } /*****************************************************************************/ @@ -196,7 +197,7 @@ int XUsbPs_EpBufferSend(XUsbPs *InstancePtr, u8 EpNum, * ******************************************************************************/ int XUsbPs_EpBufferSendWithZLT(XUsbPs *InstancePtr, u8 EpNum, - const u8 *BufferPtr, u32 BufferLen) + const u8 *BufferPtr, u32 BufferLen) { u8 ReqZero = FALSE; XUsbPs_EpSetup *Ep; @@ -207,12 +208,12 @@ int XUsbPs_EpBufferSendWithZLT(XUsbPs *InstancePtr, u8 EpNum, Ep = &InstancePtr->DeviceConfig.EpCfg[EpNum].In; if ((BufferLen >= Ep->MaxPacketSize) && - (BufferLen % Ep->MaxPacketSize == 0)) { + (BufferLen % Ep->MaxPacketSize == 0)) { ReqZero = TRUE; } return XUsbPs_EpQueueRequest(InstancePtr, EpNum, BufferPtr, - BufferLen, ReqZero); + BufferLen, ReqZero); } /*****************************************************************************/ @@ -234,7 +235,7 @@ int XUsbPs_EpBufferSendWithZLT(XUsbPs *InstancePtr, u8 EpNum, * ******************************************************************************/ static int XUsbPs_EpQueueRequest(XUsbPs *InstancePtr, u8 EpNum, - const u8 *BufferPtr, u32 BufferLen, u8 ReqZero) + const u8 *BufferPtr, u32 BufferLen, u8 ReqZero) { int Status; u32 Token; @@ -259,7 +260,7 @@ static int XUsbPs_EpQueueRequest(XUsbPs *InstancePtr, u8 EpNum, Xil_DCacheFlushRange((unsigned int)BufferPtr, BufferLen); - if(Ep->dTDTail != Ep->dTDHead) { + if (Ep->dTDTail != Ep->dTDHead) { PipeEmpty = 0; } XUsbPs_dTDInvalidateCache(Ep->dTDHead); @@ -298,11 +299,12 @@ static int XUsbPs_EpQueueRequest(XUsbPs *InstancePtr, u8 EpNum, InstancePtr-> DeviceConfig.EpCfg[EpNum].Out.MaxPacketSize; if (BufferLen == 0 || - (BufferLen % - InstancePtr-> - DeviceConfig.EpCfg[EpNum]. - Out.MaxPacketSize)) + (BufferLen % + InstancePtr-> + DeviceConfig.EpCfg[EpNum]. + Out.MaxPacketSize)) { Multo++; + } XUsbPs_dTDSetMultO(Ep->dTDHead, (Multo << 10)); } @@ -324,32 +326,32 @@ static int XUsbPs_EpQueueRequest(XUsbPs *InstancePtr, u8 EpNum, ReqZero = FALSE; } - } while(BufferLen || exit); + } while (BufferLen || exit); XUsbPs_dTDSetTerminate(Ep->dTDHead); XUsbPs_dTDFlushCache(Ep->dTDHead); - if(!PipeEmpty) { + if (!PipeEmpty) { /* Read the endpoint prime register. */ RegValue = XUsbPs_ReadReg(InstancePtr->Config.BaseAddress, XUSBPS_EPPRIME_OFFSET); - if(RegValue & BitMask) { + if (RegValue & BitMask) { return XST_SUCCESS; } do { RegValue = XUsbPs_ReadReg(InstancePtr->Config.BaseAddress, XUSBPS_CMD_OFFSET); XUsbPs_WriteReg(InstancePtr->Config.BaseAddress, XUSBPS_CMD_OFFSET, - RegValue | XUSBPS_CMD_ATDTW_MASK); + RegValue | XUSBPS_CMD_ATDTW_MASK); Temp = XUsbPs_ReadReg(InstancePtr->Config.BaseAddress, XUSBPS_EPRDY_OFFSET) - & BitMask; - } while(!(XUsbPs_ReadReg(InstancePtr->Config.BaseAddress, XUSBPS_CMD_OFFSET) & - XUSBPS_CMD_ATDTW_MASK)); + & BitMask; + } while (!(XUsbPs_ReadReg(InstancePtr->Config.BaseAddress, XUSBPS_CMD_OFFSET) & + XUSBPS_CMD_ATDTW_MASK)); RegValue = XUsbPs_ReadReg(InstancePtr->Config.BaseAddress, XUSBPS_CMD_OFFSET); XUsbPs_WriteReg(InstancePtr->Config.BaseAddress, XUSBPS_CMD_OFFSET, - RegValue & ~XUSBPS_CMD_ATDTW_MASK); + RegValue & ~XUSBPS_CMD_ATDTW_MASK); - if(Temp) { + if (Temp) { return XST_SUCCESS; } } @@ -412,10 +414,10 @@ void XUsbPs_EpGetData(XUsbPs *InstancePtr, u8 EpNum, u32 BufferLen) XUsbPs_dTDInvalidateCache(Ep->dTDCurr); DataBuff = (u8 *) XUsbPs_ReaddTD(Ep->dTDCurr, - XUSBPS_dTDUSERDATA); + XUSBPS_dTDUSERDATA); length = EpSetup->BufSize - - XUsbPs_dTDGetTransferLen(Ep->dTDCurr); + XUsbPs_dTDGetTransferLen(Ep->dTDCurr); if (length > 0) { BufferLen = length; @@ -426,11 +428,11 @@ void XUsbPs_EpGetData(XUsbPs *InstancePtr, u8 EpNum, u32 BufferLen) /* Invalidate the Buffer Pointer */ InavalidateLen = BufferLen; if (BufferLen % 32) { - InavalidateLen = (BufferLen/32) * 32 + 32; + InavalidateLen = (BufferLen / 32) * 32 + 32; } Xil_DCacheInvalidateRange((unsigned int)DataBuff, - InavalidateLen); + InavalidateLen); memcpy(Ep->BufferPtr, DataBuff, BufferLen); @@ -460,12 +462,12 @@ void XUsbPs_EpGetData(XUsbPs *InstancePtr, u8 EpNum, u32 BufferLen) * or lesser data. */ if ((Ep->RequestedBytes <= Ep->BytesTxed) || - (Ep->BytesTxed % EpSetup->MaxPacketSize)) { + (Ep->BytesTxed % EpSetup->MaxPacketSize)) { Ep->MemAlloted = 0; if (Ep->HandlerIsoFunc) { Ep->HandlerIsoFunc(Ep->HandlerRef, - Ep->RequestedBytes, - Ep->BytesTxed); + Ep->RequestedBytes, + Ep->BytesTxed); } break; @@ -501,7 +503,7 @@ void XUsbPs_EpGetData(XUsbPs *InstancePtr, u8 EpNum, u32 BufferLen) * ******************************************************************************/ int XUsbPs_EpBufferReceive(XUsbPs *InstancePtr, u8 EpNum, - u8 **BufferPtr, u32 *BufferLenPtr, u32 *Handle) + u8 **BufferPtr, u32 *BufferLenPtr, u32 *Handle) { XUsbPs_EpOut *Ep; XUsbPs_EpSetup *EpSetup; @@ -534,14 +536,14 @@ int XUsbPs_EpBufferReceive(XUsbPs *InstancePtr, u8 EpNum, * Transfer Descriptor. */ *BufferPtr = (u8 *) XUsbPs_ReaddTD(Ep->dTDCurr, - XUSBPS_dTDUSERDATA); + XUSBPS_dTDUSERDATA); length = EpSetup->BufSize - - XUsbPs_dTDGetTransferLen(Ep->dTDCurr); + XUsbPs_dTDGetTransferLen(Ep->dTDCurr); - if(length > 0) { + if (length > 0) { *BufferLenPtr = length; - }else { + } else { *BufferLenPtr = 0; } @@ -616,7 +618,7 @@ void XUsbPs_EpBufferRelease(u32 Handle) * ******************************************************************************/ s32 XUsbPs_EpDataBufferReceive(XUsbPs *InstancePtr, u8 EpNum, - u8 *BufferPtr, u32 BufferLen) + u8 *BufferPtr, u32 BufferLen) { XUsbPs_EpOut *Ep; @@ -670,8 +672,8 @@ s32 XUsbPs_EpDataBufferReceive(XUsbPs *InstancePtr, u8 EpNum, * ******************************************************************************/ int XUsbPs_EpSetHandler(XUsbPs *InstancePtr, u8 EpNum, u8 Direction, - XUsbPs_EpHandlerFunc CallBackFunc, - void *CallBackRef) + XUsbPs_EpHandlerFunc CallBackFunc, + void *CallBackRef) { XUsbPs_Endpoint *Ep; @@ -681,12 +683,12 @@ int XUsbPs_EpSetHandler(XUsbPs *InstancePtr, u8 EpNum, u8 Direction, Ep = &InstancePtr->DeviceConfig.Ep[EpNum]; - if(Direction & XUSBPS_EP_DIRECTION_OUT) { + if (Direction & XUSBPS_EP_DIRECTION_OUT) { Ep->Out.HandlerFunc = CallBackFunc; Ep->Out.HandlerRef = CallBackRef; } - if(Direction & XUSBPS_EP_DIRECTION_IN) { + if (Direction & XUSBPS_EP_DIRECTION_IN) { Ep->In.HandlerFunc = CallBackFunc; Ep->In.HandlerRef = CallBackRef; } @@ -718,7 +720,7 @@ int XUsbPs_EpSetHandler(XUsbPs *InstancePtr, u8 EpNum, u8 Direction, * ******************************************************************************/ s32 XUsbPs_EpSetIsoHandler(XUsbPs *InstancePtr, u8 EpNum, u8 Direction, - XUsbPs_EpIsoHandlerFunc CallBackFunc) + XUsbPs_EpIsoHandlerFunc CallBackFunc) { XUsbPs_Endpoint *Ep; void *CallBackRef = (void *) InstancePtr->AppData; @@ -770,21 +772,21 @@ int XUsbPs_EpPrime(XUsbPs *InstancePtr, u8 EpNum, u8 Direction) /* Get the right bit mask for the endpoint direction. */ switch (Direction) { - case XUSBPS_EP_DIRECTION_OUT: - Mask = 0x00000001; - break; + case XUSBPS_EP_DIRECTION_OUT: + Mask = 0x00000001; + break; - case XUSBPS_EP_DIRECTION_IN: - Mask = 0x00010000; - break; + case XUSBPS_EP_DIRECTION_IN: + Mask = 0x00010000; + break; - default: - return XST_INVALID_PARAM; + default: + return XST_INVALID_PARAM; } /* Write the endpoint prime register. */ XUsbPs_WriteReg(InstancePtr->Config.BaseAddress, - XUSBPS_EPPRIME_OFFSET, Mask << EpNum); + XUSBPS_EPPRIME_OFFSET, Mask << EpNum); return XST_SUCCESS; } @@ -807,7 +809,7 @@ int XUsbPs_EpPrime(XUsbPs *InstancePtr, u8 EpNum, u8 Direction) * @note None. ******************************************************************************/ int XUsbPs_EpGetSetupData(XUsbPs *InstancePtr, int EpNum, - XUsbPs_SetupData *SetupDataPtr) + XUsbPs_SetupData *SetupDataPtr) { XUsbPs_EpOut *Ep; @@ -844,7 +846,7 @@ int XUsbPs_EpGetSetupData(XUsbPs *InstancePtr, int EpNum, /* Clear the pending endpoint setup stat bit. */ XUsbPs_WriteReg(InstancePtr->Config.BaseAddress, - XUSBPS_EPSTAT_OFFSET, 1 << EpNum); + XUSBPS_EPSTAT_OFFSET, 1 << EpNum); /* Clear the Tripwire bit and continue. */ @@ -877,8 +879,8 @@ int XUsbPs_EpGetSetupData(XUsbPs *InstancePtr, int EpNum, */ Timeout = XUSBPS_TIMEOUT_COUNTER; while ((XUsbPs_ReadReg(InstancePtr->Config.BaseAddress, - XUSBPS_EPSTAT_OFFSET) & - (1 << EpNum)) && --Timeout) { + XUSBPS_EPSTAT_OFFSET) & + (1 << EpNum)) && --Timeout) { /* NOP */ } if (0 == Timeout) { @@ -1063,18 +1065,18 @@ static void XUsbPs_dQHInit(XUsbPs_DeviceConfig *DevCfgPtr) * values in queue head than other types. * Also enable ZLT for isochronous. */ - if(XUSBPS_EP_TYPE_ISOCHRONOUS == EpCfg[EpNum].Out.Type) { + if (XUSBPS_EP_TYPE_ISOCHRONOUS == EpCfg[EpNum].Out.Type) { XUsbPs_dQHSetMaxPacketLenISO(Ep[EpNum].Out.dQH, - EpCfg[EpNum].Out.MaxPacketSize); + EpCfg[EpNum].Out.MaxPacketSize); XUsbPs_dQHEnableZLT(Ep[EpNum].Out.dQH); - }else { + } else { XUsbPs_dQHSetMaxPacketLen(Ep[EpNum].Out.dQH, - EpCfg[EpNum].Out.MaxPacketSize); + EpCfg[EpNum].Out.MaxPacketSize); XUsbPs_dQHDisableZLT(Ep[EpNum].Out.dQH); } /* Only control OUT needs this */ - if(XUSBPS_EP_TYPE_CONTROL == EpCfg[EpNum].Out.Type) { + if (XUSBPS_EP_TYPE_CONTROL == EpCfg[EpNum].Out.Type) { XUsbPs_dQHSetIOS(Ep[EpNum].Out.dQH); } @@ -1089,17 +1091,17 @@ static void XUsbPs_dQHInit(XUsbPs_DeviceConfig *DevCfgPtr) /* IN Queue Heads. */ if (XUSBPS_EP_TYPE_NONE != EpCfg[EpNum].In.Type) { XUsbPs_WritedQH(Ep[EpNum].In.dQH, - XUSBPS_dQHCPTR, Ep[EpNum].In.dTDs); + XUSBPS_dQHCPTR, Ep[EpNum].In.dTDs); /* Isochronous ep packet size can be larger than 1024.*/ - if(XUSBPS_EP_TYPE_ISOCHRONOUS == EpCfg[EpNum].In.Type) { + if (XUSBPS_EP_TYPE_ISOCHRONOUS == EpCfg[EpNum].In.Type) { XUsbPs_dQHSetMaxPacketLenISO(Ep[EpNum].In.dQH, - EpCfg[EpNum].In.MaxPacketSize); + EpCfg[EpNum].In.MaxPacketSize); XUsbPs_dQHEnableZLT(Ep[EpNum].In.dQH); - }else { + } else { XUsbPs_dQHSetMaxPacketLen(Ep[EpNum].In.dQH, - EpCfg[EpNum].In.MaxPacketSize); + EpCfg[EpNum].In.MaxPacketSize); XUsbPs_dQHDisableZLT(Ep[EpNum].In.dQH); } @@ -1154,8 +1156,7 @@ static int XUsbPs_dTDInit(XUsbPs_DeviceConfig *DevCfgPtr) */ if (XUSBPS_EP_TYPE_NONE != EpCfg[EpNum].Out.Type) { NumdTD = EpCfg[EpNum].Out.NumBufs; - } - else { + } else { NumdTD = 0; } @@ -1168,7 +1169,7 @@ static int XUsbPs_dTDInit(XUsbPs_DeviceConfig *DevCfgPtr) /* Set NEXT link pointer. */ XUsbPs_WritedTD(&Out->dTDs[Td], XUSBPS_dTDNLP, - &Out->dTDs[NextTd]); + &Out->dTDs[NextTd]); /* Set the OUT descriptor ACTIVE and enable the * interrupt on complete. @@ -1187,10 +1188,10 @@ static int XUsbPs_dTDInit(XUsbPs_DeviceConfig *DevCfgPtr) } Status = XUsbPs_dTDAttachBuffer( - &Out->dTDs[Td], - Out->dTDBufs + - (Td * EpCfg[EpNum].Out.BufSize), - EpCfg[EpNum].Out.BufSize); + &Out->dTDs[Td], + Out->dTDBufs + + (Td * EpCfg[EpNum].Out.BufSize), + EpCfg[EpNum].Out.BufSize); if (XST_SUCCESS != Status) { return XST_FAILURE; } @@ -1207,8 +1208,7 @@ static int XUsbPs_dTDInit(XUsbPs_DeviceConfig *DevCfgPtr) */ if (XUSBPS_EP_TYPE_NONE != EpCfg[EpNum].In.Type) { NumdTD = EpCfg[EpNum].In.NumBufs; - } - else { + } else { NumdTD = 0; } @@ -1219,7 +1219,7 @@ static int XUsbPs_dTDInit(XUsbPs_DeviceConfig *DevCfgPtr) /* Set NEXT link pointer. */ XUsbPs_WritedTD(In->dTDs[Td], XUSBPS_dTDNLP, - In->dTDs[NextTd]); + In->dTDs[NextTd]); /* Set the IN descriptor's TERMINATE bits. */ XUsbPs_dTDSetTerminate(In->dTDs[Td]); @@ -1255,7 +1255,7 @@ static int XUsbPs_dTDInit(XUsbPs_DeviceConfig *DevCfgPtr) * ******************************************************************************/ static int XUsbPs_dTDAttachBuffer(XUsbPs_dTD *dTDPtr, - const u8 *BufferPtr, u32 BufferLen) + const u8 *BufferPtr, u32 BufferLen) { u32 BufAddr; u32 BufEnd; @@ -1286,7 +1286,7 @@ static int XUsbPs_dTDAttachBuffer(XUsbPs_dTD *dTDPtr, * Only do this check, if we are not sending a 0-length buffer. */ if (BufferLen > 0) { - BufEnd = BufAddr + BufferLen -1; + BufEnd = BufAddr + BufferLen - 1; PtrNum = 1; while ((BufAddr & 0xFFFFF000) != (BufEnd & 0xFFFFF000)) { @@ -1297,7 +1297,7 @@ static int XUsbPs_dTDAttachBuffer(XUsbPs_dTD *dTDPtr, */ BufAddr = (BufAddr + 0x1000) & 0xFFFFF000; XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDBPTR(PtrNum), - BufAddr); + BufAddr); PtrNum++; } } @@ -1344,14 +1344,14 @@ static void XUsbPs_dQHSetMaxPacketLenISO(XUsbPs_dQH *dQHPtr, u32 Len) /* Set Max packet size */ XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, - (XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) & - ~XUSBPS_dQHCFG_MPL_MASK) | + (XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) & + ~XUSBPS_dQHCFG_MPL_MASK) | (MaxPktSize << XUSBPS_dQHCFG_MPL_SHIFT)); /* Set Mult to tell hardware how many transactions in each microframe */ XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, - (XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) & - ~XUSBPS_dQHCFG_MULT_MASK) | + (XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) & + ~XUSBPS_dQHCFG_MULT_MASK) | (Mult << XUSBPS_dQHCFG_MULT_SHIFT)); } @@ -1382,8 +1382,9 @@ static void XUsbPs_dQHSetMaxPacketLenISO(XUsbPs_dQH *dQHPtr, u32 Len) * ******************************************************************************/ int XUsbPs_ReconfigureEp(XUsbPs *InstancePtr, XUsbPs_DeviceConfig *CfgPtr, - int EpNum, unsigned short NewDirection, - int DirectionChanged) { + int EpNum, unsigned short NewDirection, + int DirectionChanged) +{ int Status = XST_SUCCESS; XUsbPs_Endpoint *Ep; @@ -1398,8 +1399,8 @@ int XUsbPs_ReconfigureEp(XUsbPs *InstancePtr, XUsbPs_DeviceConfig *CfgPtr, /* If transfer direction changes, dTDs has to be reset * Number of buffers are preset and should not to be changed. */ - if(DirectionChanged) { - if(NewDirection == XUSBPS_EP_DIRECTION_OUT) { + if (DirectionChanged) { + if (NewDirection == XUSBPS_EP_DIRECTION_OUT) { u8 *p; /* Swap the pointer to the dTDs. @@ -1409,19 +1410,19 @@ int XUsbPs_ReconfigureEp(XUsbPs *InstancePtr, XUsbPs_DeviceConfig *CfgPtr, /* Set the OUT buffer if buffer size is not zero */ - if(EpCfg[EpNum].Out.BufSize > 0) { + if (EpCfg[EpNum].Out.BufSize > 0) { Ep[EpNum].Out.dTDBufs = p; } - } else if(NewDirection == XUSBPS_EP_DIRECTION_IN) { + } else if (NewDirection == XUSBPS_EP_DIRECTION_IN) { Ep[EpNum].In.dTDs = Ep[EpNum].Out.dTDs; } } /* Reset dTD progress tracking pointers */ - if(NewDirection == XUSBPS_EP_DIRECTION_IN) { + if (NewDirection == XUSBPS_EP_DIRECTION_IN) { Ep[EpNum].In.dTDHead = Ep[EpNum].In.dTDTail = Ep[EpNum].In.dTDs; - } else if(NewDirection == XUSBPS_EP_DIRECTION_OUT) { + } else if (NewDirection == XUSBPS_EP_DIRECTION_OUT) { Ep[EpNum].Out.dTDCurr = Ep[EpNum].Out.dTDs; } @@ -1432,7 +1433,7 @@ int XUsbPs_ReconfigureEp(XUsbPs *InstancePtr, XUsbPs_DeviceConfig *CfgPtr, /* Reinitialize the dTD linked list, and flush the cache */ Status = XUsbPs_dTDReinitEp(CfgPtr, EpNum, NewDirection); - if(Status != XST_SUCCESS) { + if (Status != XST_SUCCESS) { return Status; } @@ -1458,7 +1459,7 @@ int XUsbPs_ReconfigureEp(XUsbPs *InstancePtr, XUsbPs_DeviceConfig *CfgPtr, * ******************************************************************************/ static void XUsbPs_dQHReinitEp(XUsbPs_DeviceConfig *DevCfgPtr, -int EpNum, unsigned short NewDirection) + int EpNum, unsigned short NewDirection) { XUsbPs_Endpoint *Ep; XUsbPs_EpConfig *EpCfg; @@ -1477,23 +1478,23 @@ int EpNum, unsigned short NewDirection) * - Enable Interrupt On Setup (IOS) * */ - if(NewDirection == XUSBPS_EP_DIRECTION_OUT) { + if (NewDirection == XUSBPS_EP_DIRECTION_OUT) { /* OUT Queue Heads. */ XUsbPs_WritedQH(Ep[EpNum].Out.dQH, - XUSBPS_dQHCPTR, Ep[EpNum].Out.dTDs); + XUSBPS_dQHCPTR, Ep[EpNum].Out.dTDs); /* For isochronous, ep max packet size translates to different * values in queue head than other types. * Also enable ZLT for isochronous. */ - if(XUSBPS_EP_TYPE_ISOCHRONOUS == EpCfg[EpNum].Out.Type) { + if (XUSBPS_EP_TYPE_ISOCHRONOUS == EpCfg[EpNum].Out.Type) { XUsbPs_dQHSetMaxPacketLenISO(Ep[EpNum].Out.dQH, - EpCfg[EpNum].Out.MaxPacketSize); + EpCfg[EpNum].Out.MaxPacketSize); XUsbPs_dQHEnableZLT(Ep[EpNum].Out.dQH); - }else { + } else { XUsbPs_dQHSetMaxPacketLen(Ep[EpNum].Out.dQH, - EpCfg[EpNum].Out.MaxPacketSize); + EpCfg[EpNum].Out.MaxPacketSize); XUsbPs_dQHDisableZLT(Ep[EpNum].Out.dQH); } @@ -1506,21 +1507,21 @@ int EpNum, unsigned short NewDirection) XUsbPs_dQHFlushCache(Ep[EpNum].Out.dQH); - } else if(NewDirection == XUSBPS_EP_DIRECTION_IN) { + } else if (NewDirection == XUSBPS_EP_DIRECTION_IN) { /* IN Queue Heads. */ XUsbPs_WritedQH(Ep[EpNum].In.dQH, - XUSBPS_dQHCPTR, Ep[EpNum].In.dTDs); + XUSBPS_dQHCPTR, Ep[EpNum].In.dTDs); /* Isochronous ep packet size can be larger than 1024. */ - if(XUSBPS_EP_TYPE_ISOCHRONOUS == EpCfg[EpNum].In.Type) { + if (XUSBPS_EP_TYPE_ISOCHRONOUS == EpCfg[EpNum].In.Type) { XUsbPs_dQHSetMaxPacketLenISO(Ep[EpNum].In.dQH, - EpCfg[EpNum].In.MaxPacketSize); + EpCfg[EpNum].In.MaxPacketSize); XUsbPs_dQHEnableZLT(Ep[EpNum].In.dQH); - }else { + } else { XUsbPs_dQHSetMaxPacketLen(Ep[EpNum].In.dQH, - EpCfg[EpNum].In.MaxPacketSize); + EpCfg[EpNum].In.MaxPacketSize); XUsbPs_dQHDisableZLT(Ep[EpNum].In.dQH); } @@ -1553,7 +1554,7 @@ int EpNum, unsigned short NewDirection) * ******************************************************************************/ static int XUsbPs_dTDReinitEp(XUsbPs_DeviceConfig *DevCfgPtr, -int EpNum, unsigned short NewDirection) + int EpNum, unsigned short NewDirection) { XUsbPs_Endpoint *Ep; XUsbPs_EpConfig *EpCfg; @@ -1567,7 +1568,7 @@ int EpNum, unsigned short NewDirection) EpCfg = DevCfgPtr->EpCfg; - if(NewDirection == XUSBPS_EP_DIRECTION_OUT) { + if (NewDirection == XUSBPS_EP_DIRECTION_OUT) { XUsbPs_EpOut *Out = &Ep[EpNum].Out; /* OUT Descriptors @@ -1589,7 +1590,7 @@ int EpNum, unsigned short NewDirection) /* Set NEXT link pointer. */ XUsbPs_WritedTD(&Out->dTDs[Td], XUSBPS_dTDNLP, - &Out->dTDs[NextTd]); + &Out->dTDs[NextTd]); /* Set the OUT descriptor ACTIVE and enable the * interrupt on complete. @@ -1604,17 +1605,17 @@ int EpNum, unsigned short NewDirection) if (Out->dTDBufs != NULL) { Status = XUsbPs_dTDAttachBuffer( - &Out->dTDs[Td], - Out->dTDBufs + - (Td * EpCfg[EpNum].Out.BufSize), - EpCfg[EpNum].Out.BufSize); + &Out->dTDs[Td], + Out->dTDBufs + + (Td * EpCfg[EpNum].Out.BufSize), + EpCfg[EpNum].Out.BufSize); if (Status != XST_SUCCESS) { return XST_FAILURE; } } XUsbPs_dTDFlushCache(&Out->dTDs[Td]); } - } else if(NewDirection == XUSBPS_EP_DIRECTION_IN) { + } else if (NewDirection == XUSBPS_EP_DIRECTION_IN) { XUsbPs_EpIn *In = &Ep[EpNum].In; /* IN Descriptors @@ -1633,7 +1634,7 @@ int EpNum, unsigned short NewDirection) /* Set NEXT link pointer. */ XUsbPs_WritedTD(&In->dTDs[Td], XUSBPS_dTDNLP, - &In->dTDs[NextTd]); + &In->dTDs[NextTd]); /* Set the IN descriptor's TERMINATE bits. */ diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/usbps/src/xusbps_endpoint.h b/bsp_z7/ps7_cortexa9_0/libsrc/usbps/src/xusbps_endpoint.h index b924726..2869929 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/usbps/src/xusbps_endpoint.h +++ b/bsp_z7/ps7_cortexa9_0/libsrc/usbps/src/xusbps_endpoint.h @@ -1,5 +1,6 @@ /****************************************************************************** * Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved. +* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -7,7 +8,7 @@ /** * * @file xusbps_endpoint.h -* @addtogroup usbps_v2_7 +* @addtogroup usbps Overview * @{ * * This is an internal file containung the definitions for endpoints. It is @@ -67,9 +68,9 @@ extern "C" { * @{ */ #define XUSBPS_dTDNLP_T_MASK 0x00000001 - /**< USB dTD Next Link Pointer Terminate Bit */ +/**< USB dTD Next Link Pointer Terminate Bit */ #define XUSBPS_dTDNLP_ADDR_MASK 0xFFFFFFE0 - /**< USB dTD Next Link Pointer Address [31:5] */ +/**< USB dTD Next Link Pointer Address [31:5] */ /* @} */ @@ -108,16 +109,16 @@ extern "C" { * ******************************************************************************/ #define XUsbPs_dTDInvalidateCache(dTDPtr) \ - Xil_DCacheInvalidateRange((unsigned int)dTDPtr, sizeof(XUsbPs_dTD)) + Xil_DCacheInvalidateRange((unsigned int)dTDPtr, sizeof(XUsbPs_dTD)) #define XUsbPs_dTDFlushCache(dTDPtr) \ - Xil_DCacheFlushRange((unsigned int)dTDPtr, sizeof(XUsbPs_dTD)) + Xil_DCacheFlushRange((unsigned int)dTDPtr, sizeof(XUsbPs_dTD)) #define XUsbPs_dQHInvalidateCache(dQHPtr) \ - Xil_DCacheInvalidateRange((unsigned int)dQHPtr, sizeof(XUsbPs_dQH)) + Xil_DCacheInvalidateRange((unsigned int)dQHPtr, sizeof(XUsbPs_dQH)) #define XUsbPs_dQHFlushCache(dQHPtr) \ - Xil_DCacheFlushRange((unsigned int)dQHPtr, sizeof(XUsbPs_dQH)) + Xil_DCacheFlushRange((unsigned int)dQHPtr, sizeof(XUsbPs_dQH)) /*****************************************************************************/ /** @@ -132,9 +133,9 @@ extern "C" { * ******************************************************************************/ #define XUsbPs_dTDSetTransferLen(dTDPtr, Len) \ - XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDTOKEN, \ + XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDTOKEN, \ (XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) & \ - ~XUSBPS_dTDTOKEN_LEN_MASK) | ((Len) << 16)) + ~XUSBPS_dTDTOKEN_LEN_MASK) | ((Len) << 16)) /*****************************************************************************/ @@ -151,8 +152,8 @@ extern "C" { * ******************************************************************************/ #define XUsbPs_dTDGetNLP(dTDPtr) \ - (XUsbPs_dTD *) ((XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDNLP)\ - & XUSBPS_dTDNLP_ADDR_MASK)) + (XUsbPs_dTD *) ((XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDNLP)\ + & XUSBPS_dTDNLP_ADDR_MASK)) /*****************************************************************************/ @@ -168,10 +169,10 @@ extern "C" { * ******************************************************************************/ #define XUsbPs_dTDSetNLP(dTDPtr, NLP) \ - XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDNLP, \ + XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDNLP, \ (XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDNLP) & \ - ~XUSBPS_dTDNLP_ADDR_MASK) | \ - ((NLP) & XUSBPS_dTDNLP_ADDR_MASK)) + ~XUSBPS_dTDNLP_ADDR_MASK) | \ + ((NLP) & XUSBPS_dTDNLP_ADDR_MASK)) /*****************************************************************************/ @@ -188,8 +189,8 @@ extern "C" { * ******************************************************************************/ #define XUsbPs_dTDGetTransferLen(dTDPtr) \ - (u32) ((XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) \ - & XUSBPS_dTDTOKEN_LEN_MASK) >> 16) + (u32) ((XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) \ + & XUSBPS_dTDTOKEN_LEN_MASK) >> 16) /*****************************************************************************/ @@ -205,9 +206,9 @@ extern "C" { * ******************************************************************************/ #define XUsbPs_dTDSetIOC(dTDPtr) \ - XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDTOKEN, \ + XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDTOKEN, \ XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) | \ - XUSBPS_dTDTOKEN_IOC_MASK) + XUSBPS_dTDTOKEN_IOC_MASK) /*****************************************************************************/ @@ -222,9 +223,9 @@ extern "C" { * ******************************************************************************/ #define XUsbPs_dTDSetTerminate(dTDPtr) \ - XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDNLP, \ + XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDNLP, \ XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDNLP) | \ - XUSBPS_dTDNLP_T_MASK) + XUSBPS_dTDNLP_T_MASK) /*****************************************************************************/ @@ -239,9 +240,9 @@ extern "C" { * ******************************************************************************/ #define XUsbPs_dTDClrTerminate(dTDPtr) \ - XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDNLP, \ + XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDNLP, \ XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDNLP) & \ - ~XUSBPS_dTDNLP_T_MASK) + ~XUSBPS_dTDNLP_T_MASK) /*****************************************************************************/ @@ -260,8 +261,8 @@ extern "C" { * ******************************************************************************/ #define XUsbPs_dTDIsActive(dTDPtr) \ - ((XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) & \ - XUSBPS_dTDTOKEN_ACTIVE_MASK) ? TRUE : FALSE) + ((XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) & \ + XUSBPS_dTDTOKEN_ACTIVE_MASK) ? TRUE : FALSE) /*****************************************************************************/ @@ -276,9 +277,9 @@ extern "C" { * ******************************************************************************/ #define XUsbPs_dTDSetActive(dTDPtr) \ - XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDTOKEN, \ + XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDTOKEN, \ XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) | \ - XUSBPS_dTDTOKEN_ACTIVE_MASK) + XUSBPS_dTDTOKEN_ACTIVE_MASK) /*****************************************************************************/ /** @@ -293,9 +294,9 @@ extern "C" { * ******************************************************************************/ #define XUsbPs_dTDSetMultO(dTDPtr, val) \ - XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDTOKEN, \ + XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDTOKEN, \ (XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) & \ - (~XUSBPS_dTDTOKEN_MULTO_MASK)) | val) + (~XUSBPS_dTDTOKEN_MULTO_MASK)) | val) /*****************************************************************************/ @@ -326,7 +327,7 @@ extern "C" { * ******************************************************************************/ #define XUsbPs_WritedTD(dTDPtr, Id, Val) \ - (*(u32 *) ((u32)(dTDPtr) + (u32)(Id)) = (u32)(Val)) + (*(u32 *) ((u32)(dTDPtr) + (u32)(Id)) = (u32)(Val)) /******************************************************************************/ @@ -368,17 +369,17 @@ extern "C" { * @{ */ #define XUSBPS_dQHCFG_IOS_MASK 0x00008000 - /**< USB dQH Interrupt on Setup Bit */ +/**< USB dQH Interrupt on Setup Bit */ #define XUSBPS_dQHCFG_MPL_MASK 0x07FF0000 - /**< USB dQH Maximum Packet Length - * Field [10:0] */ +/**< USB dQH Maximum Packet Length + * Field [10:0] */ #define XUSBPS_dQHCFG_MPL_SHIFT 16 #define XUSBPS_dQHCFG_ZLT_MASK 0x20000000 - /**< USB dQH Zero Length Termination - * Select Bit */ +/**< USB dQH Zero Length Termination + * Select Bit */ #define XUSBPS_dQHCFG_MULT_MASK 0xC0000000 - /* USB dQH Number of Transactions Field - * [1:0] */ +/* USB dQH Number of Transactions Field + * [1:0] */ #define XUSBPS_dQHCFG_MULT_SHIFT 30 /* @} */ @@ -396,9 +397,9 @@ extern "C" { * ******************************************************************************/ #define XUsbPs_dQHSetMaxPacketLen(dQHPtr, Len) \ - XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, \ + XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, \ (XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) & \ - ~XUSBPS_dQHCFG_MPL_MASK) | ((Len) << 16)) + ~XUSBPS_dQHCFG_MPL_MASK) | ((Len) << 16)) /*****************************************************************************/ /** @@ -412,9 +413,9 @@ extern "C" { * ******************************************************************************/ #define XUsbPs_dQHSetIOS(dQHPtr) \ - XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, \ + XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, \ XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) | \ - XUSBPS_dQHCFG_IOS_MASK) + XUSBPS_dQHCFG_IOS_MASK) /*****************************************************************************/ /** @@ -428,9 +429,9 @@ extern "C" { * ******************************************************************************/ #define XUsbPs_dQHClrIOS(dQHPtr) \ - XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, \ + XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, \ XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) & \ - ~XUSBPS_dQHCFG_IOS_MASK) + ~XUSBPS_dQHCFG_IOS_MASK) /*****************************************************************************/ /** @@ -445,9 +446,9 @@ extern "C" { * ******************************************************************************/ #define XUsbPs_dQHEnableZLT(dQHPtr) \ - XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, \ + XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, \ XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) & \ - ~XUSBPS_dQHCFG_ZLT_MASK) + ~XUSBPS_dQHCFG_ZLT_MASK) /*****************************************************************************/ @@ -463,9 +464,9 @@ extern "C" { * ******************************************************************************/ #define XUsbPs_dQHDisableZLT(dQHPtr) \ - XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, \ + XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, \ XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) | \ - XUSBPS_dQHCFG_ZLT_MASK) + XUSBPS_dQHCFG_ZLT_MASK) /*****************************************************************************/ /** @@ -495,7 +496,7 @@ extern "C" { * ******************************************************************************/ #define XUsbPs_WritedQH(dQHPtr, Id, Val) \ - (*(u32 *) ((u32)(dQHPtr) + (u32)(Id)) = (u32)(Val)) + (*(u32 *) ((u32)(dQHPtr) + (u32)(Id)) = (u32)(Val)) diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/usbps/src/xusbps_g.c b/bsp_z7/ps7_cortexa9_0/libsrc/usbps/src/xusbps_g.c index 6f90f51..20921f3 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/usbps/src/xusbps_g.c +++ b/bsp_z7/ps7_cortexa9_0/libsrc/usbps/src/xusbps_g.c @@ -1,5 +1,6 @@ /****************************************************************************** * Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved. +* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -7,7 +8,7 @@ /** * * @file xusbps_g.c -* @addtogroup usbps_v2_7 +* @addtogroup usbps Overview * @{ * This file contains a configuration table where each entry is a configuration * structure for an XUsbPs device in the system. @@ -41,13 +42,13 @@ XUsbPs_Config XUsbPs_ConfigTable[] = { { - 0, - XPAR_XUSBPS_0_BASEADDR + 0, + XPAR_XUSBPS_0_BASEADDR }, #ifdef XPAR_XUSBPS_1_BASEADDR { - 1, - XPAR_XUSBPS_1_BASEADDR + 1, + XPAR_XUSBPS_1_BASEADDR } #endif }; diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/usbps/src/xusbps_hw.c b/bsp_z7/ps7_cortexa9_0/libsrc/usbps/src/xusbps_hw.c index f06656a..7829eb8 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/usbps/src/xusbps_hw.c +++ b/bsp_z7/ps7_cortexa9_0/libsrc/usbps/src/xusbps_hw.c @@ -1,5 +1,6 @@ /****************************************************************************** * Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved. +* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -7,7 +8,7 @@ /** * * @file xusbps_hw.c -* @addtogroup usbps_v2_7 +* @addtogroup usbps Overview * @{ * * The implementation of the XUsbPs interface reset functionality @@ -43,7 +44,7 @@ /*****************************************************************************/ /** -* This function perform the reset sequence to the given usbps interface by +* This function perform the reset sequence to the given usbps interface by * configuring the appropriate control bits in the usbps specific registers. * the usbps reset sequence involves the below steps * Disable the interrupts @@ -61,34 +62,33 @@ void XUsbPs_ResetHw(u32 BaseAddress) { u32 RegVal; u32 Timeout = 0; - + /* Host and device mode */ /* Disable the interrupts */ - XUsbPs_WriteReg(BaseAddress,XUSBPS_IER_OFFSET,0x0); + XUsbPs_WriteReg(BaseAddress, XUSBPS_IER_OFFSET, 0x0); /* Clear the interuupt status */ - RegVal = XUsbPs_ReadReg(BaseAddress,XUSBPS_ISR_OFFSET); - XUsbPs_WriteReg(BaseAddress,XUSBPS_ISR_OFFSET,RegVal); + RegVal = XUsbPs_ReadReg(BaseAddress, XUSBPS_ISR_OFFSET); + XUsbPs_WriteReg(BaseAddress, XUSBPS_ISR_OFFSET, RegVal); - /* Perform the reset operation using USB CMD register */ - RegVal = XUsbPs_ReadReg(BaseAddress,XUSBPS_CMD_OFFSET); + /* Perform the reset operation using USB CMD register */ + RegVal = XUsbPs_ReadReg(BaseAddress, XUSBPS_CMD_OFFSET); RegVal = RegVal | XUSBPS_CMD_RST_MASK; - XUsbPs_WriteReg(BaseAddress,XUSBPS_CMD_OFFSET,RegVal); - RegVal = XUsbPs_ReadReg(BaseAddress,XUSBPS_CMD_OFFSET); + XUsbPs_WriteReg(BaseAddress, XUSBPS_CMD_OFFSET, RegVal); + RegVal = XUsbPs_ReadReg(BaseAddress, XUSBPS_CMD_OFFSET); /* Wait till the reset operation returns success */ /* * FIX ME: right now no indication to the caller or user about * timeout overflow */ - while ((RegVal & XUSBPS_CMD_RST_MASK) && (Timeout < XUSBPS_RESET_TIMEOUT)) - { - RegVal = XUsbPs_ReadReg(BaseAddress,XUSBPS_CMD_OFFSET); + while ((RegVal & XUSBPS_CMD_RST_MASK) && (Timeout < XUSBPS_RESET_TIMEOUT)) { + RegVal = XUsbPs_ReadReg(BaseAddress, XUSBPS_CMD_OFFSET); Timeout++; } - /* Update periodic list base address register with reset value */ - XUsbPs_WriteReg(BaseAddress,XUSBPS_LISTBASE_OFFSET,0x0); - /* Update async/endpoint list base address register with reset value */ - XUsbPs_WriteReg(BaseAddress,XUSBPS_ASYNCLISTADDR_OFFSET,0x0); - + /* Update periodic list base address register with reset value */ + XUsbPs_WriteReg(BaseAddress, XUSBPS_LISTBASE_OFFSET, 0x0); + /* Update async/endpoint list base address register with reset value */ + XUsbPs_WriteReg(BaseAddress, XUSBPS_ASYNCLISTADDR_OFFSET, 0x0); + } diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/usbps/src/xusbps_hw.h b/bsp_z7/ps7_cortexa9_0/libsrc/usbps/src/xusbps_hw.h index 4f985dc..2f057a6 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/usbps/src/xusbps_hw.h +++ b/bsp_z7/ps7_cortexa9_0/libsrc/usbps/src/xusbps_hw.h @@ -1,5 +1,6 @@ /****************************************************************************** * Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved. +* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -7,7 +8,7 @@ /** * * @file xusbps_hw.h -* @addtogroup usbps_v2_7 +* @addtogroup usbps Overview * @{ * * This header file contains identifiers and low-level driver functions (or @@ -22,7 +23,7 @@ * 1.00a wgr 10/10/10 First release * 1.04a nm 10/23/12 Fixed CR# 679106. * 1.05a kpc 07/03/13 Added XUsbPs_ResetHw function prototype - * 2.00a kpc 04/03/14 Fixed CR#777764. Corrected max endpoint vale and masks + * 2.00a kpc 04/03/14 Fixed CR#777764. Corrected max endpoint vale and masks * 2.5 pm 02/20/20 Added Endpoint Control Register bit positions for Rx & Tx * * @@ -110,7 +111,7 @@ extern "C" { /* NOTE: The Port Control / Status Register index is 1-based. */ #define XUSBPS_PORTSCRn_OFFSET(n) \ - (XUSBPS_PORTSCR1_OFFSET + (((n)-1) * XUSBPS_REG_SPACING)) + (XUSBPS_PORTSCR1_OFFSET + (((n)-1) * XUSBPS_REG_SPACING)) #define XUSBPS_OTGCSR_OFFSET 0x000001A4 /**< OTG Status and Control */ @@ -133,7 +134,7 @@ extern "C" { #define XUSBPS_EP_ALL_MASK 0x0FFF0FFF /**< Mask used for endpoint control * registers */ #define XUSBPS_EPCRn_OFFSET(n) \ - (XUSBPS_EPCR0_OFFSET + ((n) * XUSBPS_REG_SPACING)) + (XUSBPS_EPCR0_OFFSET + ((n) * XUSBPS_REG_SPACING)) #define XUSBPS_EPFLUSH_RX_SHIFT 0 #define XUSBPS_EPFLUSH_TX_SHIFT 16 @@ -251,24 +252,24 @@ extern "C" { #define XUSBPS_IXR_TI1_MASK 0x02000000 /**< Timer 1 Interrupt */ #define XUSBPS_IXR_ALL (XUSBPS_IXR_UI_MASK | \ - XUSBPS_IXR_UE_MASK | \ - XUSBPS_IXR_PC_MASK | \ - XUSBPS_IXR_FRE_MASK | \ - XUSBPS_IXR_AA_MASK | \ - XUSBPS_IXR_UR_MASK | \ - XUSBPS_IXR_SR_MASK | \ - XUSBPS_IXR_SLE_MASK | \ - XUSBPS_IXR_ULPI_MASK | \ - XUSBPS_IXR_HCH_MASK | \ - XUSBPS_IXR_RCL_MASK | \ - XUSBPS_IXR_PS_MASK | \ - XUSBPS_IXR_AS_MASK | \ - XUSBPS_IXR_NAK_MASK | \ - XUSBPS_IXR_UA_MASK | \ - XUSBPS_IXR_UP_MASK | \ - XUSBPS_IXR_TI0_MASK | \ - XUSBPS_IXR_TI1_MASK) - /**< Mask for ALL IRQ types */ + XUSBPS_IXR_UE_MASK | \ + XUSBPS_IXR_PC_MASK | \ + XUSBPS_IXR_FRE_MASK | \ + XUSBPS_IXR_AA_MASK | \ + XUSBPS_IXR_UR_MASK | \ + XUSBPS_IXR_SR_MASK | \ + XUSBPS_IXR_SLE_MASK | \ + XUSBPS_IXR_ULPI_MASK | \ + XUSBPS_IXR_HCH_MASK | \ + XUSBPS_IXR_RCL_MASK | \ + XUSBPS_IXR_PS_MASK | \ + XUSBPS_IXR_AS_MASK | \ + XUSBPS_IXR_NAK_MASK | \ + XUSBPS_IXR_UA_MASK | \ + XUSBPS_IXR_UP_MASK | \ + XUSBPS_IXR_TI0_MASK | \ + XUSBPS_IXR_TI1_MASK) +/**< Mask for ALL IRQ types */ /* @} */ @@ -291,13 +292,13 @@ extern "C" { * @{ */ #define XUSBPS_DEVICEADDR_DEVICEAADV_MASK 0x01000000 - /**< Device Addr Auto Advance */ +/**< Device Addr Auto Advance */ #define XUSBPS_DEVICEADDR_ADDR_MASK 0xFE000000 - /**< Device Address */ +/**< Device Address */ #define XUSBPS_DEVICEADDR_ADDR_SHIFT 25 - /**< Address shift */ +/**< Address shift */ #define XUSBPS_DEVICEADDR_MAX 127 - /**< Biggest allowed address */ +/**< Biggest allowed address */ /* @} */ /** @name USB TT Control Register (TTCTRL) bit positions. @@ -319,11 +320,11 @@ extern "C" { * @{ */ #define XUSBPS_TXFILL_OVERHEAD_MASK 0x000000FF - /**< Scheduler Overhead */ +/**< Scheduler Overhead */ #define XUSBPS_TXFILL_HEALTH_MASK 0x00001F00 - /**< Scheduler Health Cntr */ +/**< Scheduler Health Cntr */ #define XUSBPS_TXFILL_BURST_MASK 0x003F0000 - /**< FIFO Burst Threshold */ +/**< FIFO Burst Threshold */ /* @} */ @@ -411,22 +412,22 @@ extern "C" { * Enable Bit */ #define XUSBPS_OTG_ISB_ALL (XUSBPS_OTGSC_IDIS_MASK |\ - XUSBPS_OTGSC_AVVIS_MASK | \ - XUSBPS_OTGSC_ASVIS_MASK | \ - XUSBPS_OTGSC_BSVIS_MASK | \ - XUSBPS_OTGSC_BSEIS_MASK | \ - XUSBPS_OTGSC_1MSS_MASK | \ - XUSBPS_OTGSC_DPIS_MASK) - /** Mask for All IRQ status masks */ + XUSBPS_OTGSC_AVVIS_MASK | \ + XUSBPS_OTGSC_ASVIS_MASK | \ + XUSBPS_OTGSC_BSVIS_MASK | \ + XUSBPS_OTGSC_BSEIS_MASK | \ + XUSBPS_OTGSC_1MSS_MASK | \ + XUSBPS_OTGSC_DPIS_MASK) +/** Mask for All IRQ status masks */ #define XUSBPS_OTG_IEB_ALL (XUSBPS_OTGSC_IDIE_MASK |\ - XUSBPS_OTGSC_AVVIE_MASK | \ - XUSBPS_OTGSC_ASVIE_MASK | \ - XUSBPS_OTGSC_BSVIE_MASK | \ - XUSBPS_OTGSC_BSEE_IEB_MASK | \ - XUSBPS_OTGSC_1MSE_MASK | \ - XUSBPS_OTGSC_DPIE_MASK) - /** Mask for All IRQ Enable masks */ + XUSBPS_OTGSC_AVVIE_MASK | \ + XUSBPS_OTGSC_ASVIE_MASK | \ + XUSBPS_OTGSC_BSVIE_MASK | \ + XUSBPS_OTGSC_BSEE_IEB_MASK | \ + XUSBPS_OTGSC_1MSE_MASK | \ + XUSBPS_OTGSC_DPIE_MASK) +/** Mask for All IRQ Enable masks */ /* @} */ @@ -468,7 +469,7 @@ extern "C" { * *****************************************************************************/ #define XUsbPs_ReadReg(BaseAddress, RegOffset) \ - Xil_In32(BaseAddress + (RegOffset)) + Xil_In32(BaseAddress + (RegOffset)) /****************************************************************************/ @@ -487,7 +488,7 @@ extern "C" { * *****************************************************************************/ #define XUsbPs_WriteReg(BaseAddress, RegOffset, Data) \ - Xil_Out32(BaseAddress + (RegOffset), (Data)) + Xil_Out32(BaseAddress + (RegOffset), (Data)) /************************** Function Prototypes ******************************/ diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/usbps/src/xusbps_intr.c b/bsp_z7/ps7_cortexa9_0/libsrc/usbps/src/xusbps_intr.c index 061825a..2acfaaf 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/usbps/src/xusbps_intr.c +++ b/bsp_z7/ps7_cortexa9_0/libsrc/usbps/src/xusbps_intr.c @@ -1,12 +1,13 @@ /****************************************************************************** * Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved. +* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ /******************************************************************************/ /** * @file xusbps_intr.c -* @addtogroup usbps_v2_7 +* @addtogroup usbps Overview * @{ * * This file contains the functions that are related to interrupt processing @@ -83,15 +84,15 @@ void XUsbPs_IntrHandler(void *HandlerRef) /* Clear the interrupt status register. */ XUsbPs_WriteReg(InstancePtr->Config.BaseAddress, - XUSBPS_ISR_OFFSET, IrqSts); + XUSBPS_ISR_OFFSET, IrqSts); /* Nak interrupt, used to respond to host's IN request */ - if(IrqSts & XUSBPS_IXR_NAK_MASK) { + if (IrqSts & XUSBPS_IXR_NAK_MASK) { /* Ack the hardware */ XUsbPs_WriteReg(InstancePtr->Config.BaseAddress, - XUSBPS_EPNAKISR_OFFSET, - XUsbPs_ReadReg(InstancePtr->Config.BaseAddress, - XUSBPS_EPNAKISR_OFFSET)); + XUSBPS_EPNAKISR_OFFSET, + XUsbPs_ReadReg(InstancePtr->Config.BaseAddress, + XUSBPS_EPNAKISR_OFFSET)); } @@ -134,25 +135,25 @@ void XUsbPs_IntrHandler(void *HandlerRef) * is possible to send setup packets on other endpoints). */ EpStat = XUsbPs_ReadReg(InstancePtr->Config.BaseAddress, - XUSBPS_EPSTAT_OFFSET); + XUSBPS_EPSTAT_OFFSET); if (EpStat & 0x0001) { /* Handle the setup packet */ XUsbPs_IntrHandleEp0Setup(InstancePtr); /* Re-Prime the endpoint. * Endpoint is de-primed if a setup packet comes in. - */ + */ XUsbPs_EpPrime(InstancePtr, 0, XUSBPS_EP_DIRECTION_OUT); } /* Check for RX and TX complete interrupts. */ EpCompl = XUsbPs_ReadReg(InstancePtr->Config.BaseAddress, - XUSBPS_EPCOMPL_OFFSET); + XUSBPS_EPCOMPL_OFFSET); /* ACK the complete interrupts. */ XUsbPs_WriteReg(InstancePtr->Config.BaseAddress, - XUSBPS_EPCOMPL_OFFSET, EpCompl); + XUSBPS_EPCOMPL_OFFSET, EpCompl); /* Check OUT (RX) endpoints. */ if (EpCompl & XUSBPS_EP_OUT_MASK) { @@ -189,8 +190,8 @@ void XUsbPs_IntrHandler(void *HandlerRef) * ******************************************************************************/ int XUsbPs_IntrSetHandler(XUsbPs *InstancePtr, - XUsbPs_IntrHandlerFunc CallBackFunc, - void *CallBackRef, u32 Mask) + XUsbPs_IntrHandlerFunc CallBackFunc, + void *CallBackRef, u32 Mask) { Xil_AssertNonvoid(InstancePtr != NULL); @@ -256,27 +257,27 @@ static void XUsbPs_IntrHandleTX(XUsbPs *InstancePtr, u32 EpCompl) if (InstancePtr->DeviceConfig.EpCfg[Index].In.Type == - XUSBPS_EP_TYPE_ISOCHRONOUS) { + XUSBPS_EP_TYPE_ISOCHRONOUS) { if (Ep->HandlerIsoFunc) { Ep->HandlerIsoFunc(Ep->HandlerRef, - Ep->RequestedBytes, - Ep->BytesTxed); + Ep->RequestedBytes, + Ep->BytesTxed); } } else { if (Ep->HandlerFunc) { - void *BufPtr; + void *BufPtr; - BufPtr = (void *) XUsbPs_ReaddTD(Ep->dTDTail, - XUSBPS_dTDUSERDATA); + BufPtr = (void *) XUsbPs_ReaddTD(Ep->dTDTail, + XUSBPS_dTDUSERDATA); - Ep->HandlerFunc(Ep->HandlerRef, Index, - XUSBPS_EP_EVENT_DATA_TX, - BufPtr); + Ep->HandlerFunc(Ep->HandlerRef, Index, + XUSBPS_EP_EVENT_DATA_TX, + BufPtr); } } Ep->dTDTail = XUsbPs_dTDGetNLP(Ep->dTDTail); - } while(Ep->dTDTail != Ep->dTDHead); + } while (Ep->dTDTail != Ep->dTDHead); } } @@ -329,25 +330,26 @@ static void XUsbPs_IntrHandleRX(XUsbPs *InstancePtr, u32 EpCompl) * taken. */ if (InstancePtr->DeviceConfig.EpCfg[Index].Out.Type == - XUSBPS_EP_TYPE_ISOCHRONOUS){ + XUSBPS_EP_TYPE_ISOCHRONOUS) { if (Index == 0) { u8 BufferPtr[64] = {0}; /* Get the data buffer. */ XUsbPs_EpDataBufferReceive(InstancePtr, - 0, &BufferPtr[0], 64); + 0, &BufferPtr[0], 64); Ep->MemAlloted = 0; } if (Ep->MemAlloted == 1) { XUsbPs_EpGetData(InstancePtr, Index, - Ep->RequestedBytes); - } else + Ep->RequestedBytes); + } else { break; + } } else { if (Ep->HandlerFunc) { - Ep->HandlerFunc(Ep->HandlerRef, Index, - XUSBPS_EP_EVENT_DATA_RX, NULL); + Ep->HandlerFunc(Ep->HandlerRef, Index, + XUSBPS_EP_EVENT_DATA_RX, NULL); } Ep->dTDCurr = XUsbPs_dTDGetNLP(Ep->dTDCurr); @@ -379,11 +381,12 @@ static void XUsbPs_IntrHandleReset(XUsbPs *InstancePtr, u32 IrqSts) u32 Timeout; u8 Index; - if (InstancePtr->AppData != NULL) + if (InstancePtr->AppData != NULL) { InstancePtr->AppData->State = XUSBPS_STATE_DEFAULT; + } for (Index = 0; Index < InstancePtr->DeviceConfig.NumEndpoints; - Index++) { + Index++) { InstancePtr->DeviceConfig.Ep[Index].Out.MemAlloted = 0; InstancePtr->DeviceConfig.Ep[Index].Out.BufferPtr = NULL; InstancePtr->DeviceConfig.Ep[Index].Out.BytesTxed = 0; @@ -398,8 +401,8 @@ static void XUsbPs_IntrHandleReset(XUsbPs *InstancePtr, u32 IrqSts) * itself. */ XUsbPs_WriteReg(InstancePtr->Config.BaseAddress, XUSBPS_EPSTAT_OFFSET, - XUsbPs_ReadReg(InstancePtr->Config.BaseAddress, - XUSBPS_EPSTAT_OFFSET)); + XUsbPs_ReadReg(InstancePtr->Config.BaseAddress, + XUSBPS_EPSTAT_OFFSET)); /* Clear all the endpoint complete status bits by reading the * XUSBPS_EPCOMPL_OFFSET register and writings its value back @@ -407,8 +410,8 @@ static void XUsbPs_IntrHandleReset(XUsbPs *InstancePtr, u32 IrqSts) */ XUsbPs_WriteReg(InstancePtr->Config.BaseAddress, XUSBPS_EPCOMPL_OFFSET, - XUsbPs_ReadReg(InstancePtr->Config.BaseAddress, - XUSBPS_EPCOMPL_OFFSET)); + XUsbPs_ReadReg(InstancePtr->Config.BaseAddress, + XUSBPS_EPCOMPL_OFFSET)); /* Cancel all endpoint prime status by waiting until all bits * in XUSBPS_EPPRIME_OFFSET are 0 and then writing 0xFFFFFFFF @@ -418,12 +421,12 @@ static void XUsbPs_IntrHandleReset(XUsbPs *InstancePtr, u32 IrqSts) */ Timeout = XUSBPS_TIMEOUT_COUNTER; while ((XUsbPs_ReadReg(InstancePtr->Config.BaseAddress, - XUSBPS_EPPRIME_OFFSET) & - XUSBPS_EP_ALL_MASK) && --Timeout) { + XUSBPS_EPPRIME_OFFSET) & + XUSBPS_EP_ALL_MASK) && --Timeout) { /* NOP */ } XUsbPs_WriteReg(InstancePtr->Config.BaseAddress, - XUSBPS_EPFLUSH_OFFSET, 0xFFFFFFFF); + XUSBPS_EPFLUSH_OFFSET, 0xFFFFFFFF); /* Make sure that the reset bit in XUSBPS_PORTSCR1_OFFSET is * still set at this point. If the code gets to this point and @@ -431,8 +434,8 @@ static void XUsbPs_IntrHandleReset(XUsbPs *InstancePtr, u32 IrqSts) * hardware reset is necessary. */ if (!(XUsbPs_ReadReg(InstancePtr->Config.BaseAddress, - XUSBPS_PORTSCR1_OFFSET) & - XUSBPS_PORTSCR_PR_MASK)) { + XUSBPS_PORTSCR1_OFFSET) & + XUSBPS_PORTSCR_PR_MASK)) { /* Send a notification to the user that a hardware * RESET is required. At this point we can only hope * that the user registered an interrupt handler and @@ -441,8 +444,7 @@ static void XUsbPs_IntrHandleReset(XUsbPs *InstancePtr, u32 IrqSts) if (InstancePtr->HandlerFunc) { (InstancePtr->HandlerFunc)(InstancePtr->HandlerRef, IrqSts); - } - else { + } else { for (;;); } diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/usbps/src/xusbps_sinit.c b/bsp_z7/ps7_cortexa9_0/libsrc/usbps/src/xusbps_sinit.c index bc53739..fc0daa6 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/usbps/src/xusbps_sinit.c +++ b/bsp_z7/ps7_cortexa9_0/libsrc/usbps/src/xusbps_sinit.c @@ -1,5 +1,6 @@ /****************************************************************************** * Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved. +* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -7,7 +8,7 @@ /** * * @file xusbps_sinit.c -* @addtogroup usbps_v2_7 +* @addtogroup usbps Overview * @{ * * The implementation of the XUsbPs driver's static initialization @@ -19,6 +20,7 @@ * Ver Who Date Changes * ----- ---- -------- ----------------------------------------------- * 1.00a wgr 10/10/10 First release + * 2.8 pm 07/07/23 Added support for system device-tree flow. * * *****************************************************************************/ @@ -55,6 +57,7 @@ extern XUsbPs_Config XUsbPs_ConfigTable[]; * controller ID was not found. * ******************************************************************************/ +#ifndef SDT XUsbPs_Config *XUsbPs_LookupConfig(u16 DeviceID) { XUsbPs_Config *CfgPtr = NULL; @@ -70,4 +73,22 @@ XUsbPs_Config *XUsbPs_LookupConfig(u16 DeviceID) return CfgPtr; } +#else +XUsbPs_Config *XUsbPs_LookupConfig(u32 BaseAddress) +{ + XUsbPs_Config *CfgPtr = NULL; + + int Index; + + for (Index = 0U; XUsbPs_ConfigTable[Index].Name != NULL; Index++) { + if ((XUsbPs_ConfigTable[Index].BaseAddress == BaseAddress) || + !BaseAddress) { + CfgPtr = &XUsbPs_ConfigTable[Index]; + break; + } + } + + return CfgPtr; +} +#endif /** @} */ diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/xadcps/src/Makefile b/bsp_z7/ps7_cortexa9_0/libsrc/xadcps/src/Makefile index 5feeb49..66f37aa 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/xadcps/src/Makefile +++ b/bsp_z7/ps7_cortexa9_0/libsrc/xadcps/src/Makefile @@ -1,4 +1,5 @@ -DRIVER_LIB_VERSION = 1.0 +# Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved. +DRIVER_LIB_VERSION = 2.7 COMPILER= ARCHIVER= CP=cp diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/xadcps/src/xadcps.c b/bsp_z7/ps7_cortexa9_0/libsrc/xadcps/src/xadcps.c index e8eb9ee..644900f 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/xadcps/src/xadcps.c +++ b/bsp_z7/ps7_cortexa9_0/libsrc/xadcps/src/xadcps.c @@ -1,5 +1,6 @@ /****************************************************************************** * Copyright (C) 2011 - 2020 Xilinx, Inc. All rights reserved. +* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -7,7 +8,7 @@ /** * * @file xadcps.c -* @addtogroup xadcps_v2_6 +* @addtogroup Overview * @{ * * This file contains the driver API functions that can be used to access @@ -33,6 +34,8 @@ * (CR#854437). * 2.3 mn 07/09/18 Fix Doxygen warning * 2.6 aad 11/02/20 Fix MISRAC Mandatory and Advisory errors. +* 2.7 cog 07/24/23 Added support for SDT flow +* * * * @@ -94,11 +97,13 @@ int XAdcPs_CfgInitialize(XAdcPs *InstancePtr, XAdcPs_Config *ConfigPtr, /* * Set the values read from the device config and the base address. */ +#ifndef SDT InstancePtr->Config.DeviceId = ConfigPtr->DeviceId; +#endif InstancePtr->Config.BaseAddress = EffectiveAddr; /* Write Unlock value to Device Config Unlock register */ - XAdcPs_WriteReg(XPAR_XDCFG_0_BASEADDR, + XAdcPs_WriteReg((InstancePtr)->Config.BaseAddress, XADCPS_UNLK_OFFSET, XADCPS_UNLK_VALUE); /* Enable the PS access of xadc and set FIFO thresholds */ diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/xadcps/src/xadcps.h b/bsp_z7/ps7_cortexa9_0/libsrc/xadcps/src/xadcps.h index 980f394..f73ff96 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/xadcps/src/xadcps.h +++ b/bsp_z7/ps7_cortexa9_0/libsrc/xadcps/src/xadcps.h @@ -1,5 +1,6 @@ /****************************************************************************** * Copyright (C) 2011 - 2020 Xilinx, Inc. All rights reserved. +* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -7,7 +8,7 @@ /** * * @file xadcps.h -* @addtogroup xadcps_v2_6 +* @addtogroup Overview * @{ * @details * @@ -157,6 +158,8 @@ * 2.6 aad 11/02/20 Fix MISRAC Mandatory and Advisory errors. * aad 12/17/20 Added missing function declarations and removed * functions with no definitions. +* 2.7 cog 07/24/23 Added support for SDT flow +* * * * @@ -300,7 +303,11 @@ extern "C" { * device. */ typedef struct { +#ifndef SDT u16 DeviceId; /**< Unique ID of device */ +#else + char *Name; +#endif u32 BaseAddress; /**< Device base address */ } XAdcPs_Config; @@ -472,7 +479,11 @@ typedef struct { /** * Functions in xadcps_sinit.c */ +#ifndef SDT XAdcPs_Config *XAdcPs_LookupConfig(u16 DeviceId); +#else +XAdcPs_Config *XAdcPs_LookupConfig(u32 BaseAddress); +#endif /** * Functions in xadcps.c diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/xadcps/src/xadcps_g.c b/bsp_z7/ps7_cortexa9_0/libsrc/xadcps/src/xadcps_g.c index 338bb94..521805c 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/xadcps/src/xadcps_g.c +++ b/bsp_z7/ps7_cortexa9_0/libsrc/xadcps/src/xadcps_g.c @@ -1,5 +1,6 @@ /****************************************************************************** * Copyright (C) 2011 - 2020 Xilinx, Inc. All rights reserved. +* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -7,7 +8,7 @@ /** * * @file xadcps_g.c -* @addtogroup xadcps_v2_6 +* @addtogroup Overview * @{ * * This file contains a configuration table that specifies the configuration diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/xadcps/src/xadcps_hw.h b/bsp_z7/ps7_cortexa9_0/libsrc/xadcps/src/xadcps_hw.h index 51cc7c5..1477617 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/xadcps/src/xadcps_hw.h +++ b/bsp_z7/ps7_cortexa9_0/libsrc/xadcps/src/xadcps_hw.h @@ -1,5 +1,6 @@ /****************************************************************************** * Copyright (C) 2011 - 2020 Xilinx, Inc. All rights reserved. +* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -7,7 +8,7 @@ /** * * @file xadcps_hw.h -* @addtogroup xadcps_v2_6 +* @addtogroup Overview * @{ * * This header file contains identifiers and basic driver functions (or diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/xadcps/src/xadcps_intr.c b/bsp_z7/ps7_cortexa9_0/libsrc/xadcps/src/xadcps_intr.c index dfb1d2d..2bbd1f3 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/xadcps/src/xadcps_intr.c +++ b/bsp_z7/ps7_cortexa9_0/libsrc/xadcps/src/xadcps_intr.c @@ -1,5 +1,6 @@ /****************************************************************************** * Copyright (C) 2011 - 2020 Xilinx, Inc. All rights reserved. +* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -7,7 +8,7 @@ /** * * @file xadcps_intr.c -* @addtogroup xadcps_v2_6 +* @addtogroup Overview * @{ * * This file contains interrupt handling API functions of the XADC diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/xadcps/src/xadcps_selftest.c b/bsp_z7/ps7_cortexa9_0/libsrc/xadcps/src/xadcps_selftest.c index b144c7a..f403f49 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/xadcps/src/xadcps_selftest.c +++ b/bsp_z7/ps7_cortexa9_0/libsrc/xadcps/src/xadcps_selftest.c @@ -1,5 +1,6 @@ /****************************************************************************** * Copyright (C) 2011 - 2020 Xilinx, Inc. All rights reserved. +* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -7,7 +8,7 @@ /** * * @file xadcps_selftest.c -* @addtogroup xadcps_v2_6 +* @addtogroup Overview * @{ * * This file contains a diagnostic self test function for the XAdcPs driver. diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/xadcps/src/xadcps_sinit.c b/bsp_z7/ps7_cortexa9_0/libsrc/xadcps/src/xadcps_sinit.c index e06988a..a1649e6 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/xadcps/src/xadcps_sinit.c +++ b/bsp_z7/ps7_cortexa9_0/libsrc/xadcps/src/xadcps_sinit.c @@ -1,5 +1,6 @@ /****************************************************************************** * Copyright (C) 2011 - 2020 Xilinx, Inc. All rights reserved. +* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ @@ -7,7 +8,7 @@ /** * * @file xadcps_sinit.c -* @addtogroup xadcps_v2_6 +* @addtogroup Overview * @{ * * This file contains the implementation of the XAdcPs driver's static @@ -23,6 +24,7 @@ * ----- ----- -------- ----------------------------------------------------- * 1.00a ssb 12/22/11 First release based on the XPS/AXI XADC driver * 2.6 aad 11/02/20 Fix MISRAC Mandatory and Advisory errors. +* 2.7 cog 07/24/23 Added support for SDT flow * * * @@ -30,8 +32,10 @@ /***************************** Include Files *********************************/ -#include "xparameters.h" #include "xadcps.h" +#ifndef SDT +#include "xparameters.h" +#endif /************************** Constant Definitions *****************************/ @@ -61,6 +65,7 @@ extern XAdcPs_Config XAdcPs_ConfigTable[]; * @note None. * ******************************************************************************/ +#ifndef SDT XAdcPs_Config *XAdcPs_LookupConfig(u16 DeviceId) { XAdcPs_Config *CfgPtr = NULL; @@ -75,4 +80,21 @@ XAdcPs_Config *XAdcPs_LookupConfig(u16 DeviceId) return CfgPtr; } +#else +XAdcPs_Config *XAdcPs_LookupConfig(u32 BaseAddress) +{ + XAdcPs_Config *CfgPtr = NULL; + u32 Index; + + for (Index=0; XAdcPs_ConfigTable[Index].Name != NULL; Index++) { + if ((XAdcPs_ConfigTable[Index].BaseAddress == BaseAddress) || + !BaseAddress) { + CfgPtr = &XAdcPs_ConfigTable[Index]; + break; + } + } + + return CfgPtr; +} +#endif /** @} */ diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/xilffs/data/xilffs.mld b/bsp_z7/ps7_cortexa9_0/libsrc/xilffs/data/xilffs.mld index ef73eb5..5a13408 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/xilffs/data/xilffs.mld +++ b/bsp_z7/ps7_cortexa9_0/libsrc/xilffs/data/xilffs.mld @@ -11,6 +11,8 @@ # 1.00 srm 02/16/18 Updated to pick up latest freertos port 10.0 # 4.1 hk 11/21/18 Add additional LFN options # 4.2 aru 07/10/19 Fix coverity warnings +# 5.2 ht 09/12/23 Added code for versioning of library. +# 5.2 ap 10/11/23 Add TRIM option for SDT flow. ############################################################################## OPTION psf_version = 2.1; @@ -20,8 +22,8 @@ BEGIN LIBRARY xilffs OPTION copyfiles = all; OPTION REQUIRES_OS = (standalone freertos10_xilinx); OPTION APP_LINKER_FLAGS = "-Wl,--start-group,-lxilffs,-lxil,-lgcc,-lc,--end-group"; - OPTION desc = "Generic Fat File System Library"; - OPTION VERSION = 5.0; + OPTION desc = "Generic Fat File System Library R0.15"; + OPTION VERSION = 5.2; OPTION NAME = xilffs; PARAM name = fs_interface, desc = "Enables file system with selected interface. Enter 1 for SD. Enter 2 for RAM", type = int, default = 1; PARAM name = read_only, desc = "Enables the file system in Read_Only mode if true. ZynqMP fsbl will set this to true", type = bool, default = false; diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/xilffs/data/xilffs.tcl b/bsp_z7/ps7_cortexa9_0/libsrc/xilffs/data/xilffs.tcl index ac14532..45708cb 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/xilffs/data/xilffs.tcl +++ b/bsp_z7/ps7_cortexa9_0/libsrc/xilffs/data/xilffs.tcl @@ -1,5 +1,6 @@ ############################################################################### # Copyright (c) 2013 - 2022 Xilinx, Inc. All rights reserved. +# Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved. # SPDX-License-Identifier: MIT # # Modification History @@ -9,6 +10,7 @@ # 1.00a hk/sg 10/17/13 First release # 2.0 hk 12/13/13 Modified to use new TCL API's # 4.1 hk 11/21/18 Use additional LFN options +# 5.2 ap 12/11/23 Added support for microblaze risc-v # ############################################################################## @@ -112,7 +114,7 @@ proc xgen_opts_file {libhandle} { if {$ramfs_start_addr == ""} { puts $file_handle "\#define RAMFS_START_ADDR 0x10000000" - if {$proc_type == "microblaze"} { + if {$proc_type == "microblaze" || $proc_type == "microblaze_riscv"} { puts "WARNING : Specify RAM FS start address \ in system.mss for Microblaze\n" } @@ -184,7 +186,7 @@ proc xgen_opts_file {libhandle} { puts $file_handle "\#define FILE_SYSTEM_SET_FS_RPATH $set_fs_rpath" # MB does not allow word access from RAM - if {$proc_type != "microblaze" && $word_access == true} { + if {$proc_type != "microblaze" && $proc_type != "microblaze_riscv" && $word_access == true} { puts $file_handle "\#define FILE_SYSTEM_WORD_ACCESS" } } else { diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/xilffs/examples/xilffs_polled_example.c b/bsp_z7/ps7_cortexa9_0/libsrc/xilffs/examples/xilffs_polled_example.c deleted file mode 100644 index aa73e38..0000000 --- a/bsp_z7/ps7_cortexa9_0/libsrc/xilffs/examples/xilffs_polled_example.c +++ /dev/null @@ -1,234 +0,0 @@ -/****************************************************************************** -* Copyright (c) 2013 - 2022 Xilinx, Inc. All rights reserved. -* Copyright (c) 2022 Advanced Micro Devices, Inc. All Rights Reserved. -* SPDX-License-Identifier: MIT -******************************************************************************/ - -/*****************************************************************************/ -/** -* -* @file xilffs_polled_example.c -* -* -* @note This example uses file system with SD to write to and read from -* an SD card using ADMA2 in polled mode. -* To test this example File System should not be in Read Only mode. -* To test this example USE_MKFS option should be true. -* -* This example was tested using SD2.0 card and eMMC (using eMMC to SD adaptor). -* -* To test with different logical drives, drive number should be mentioned in -* both FileName and Path variables. By default, it will take drive 0 if drive -* number is not mentioned in the FileName variable. -* For example, to test logical drive 1 -* FileName = "1:/" and Path = "1:/" -* Similarly to test logical drive N, FileName = "N:/" and -* Path = "N:/" -* -* None. -* -* 
-* MODIFICATION HISTORY:
-*
-* Ver   Who Date     Changes
-* ----- --- -------- -----------------------------------------------
-* 1.00a hk  10/17/13 First release
-* 2.2   hk  07/28/14 Make changes to enable use of data cache.
-* 2.5   sk  07/15/15 Used File size as 8KB to test on emulation platform.
-* 2.9   sk  06/09/16 Added support for mkfs.
-* 3.10  mn  08/18/18 Change file size to 8MB from 8KB for ZynqMP platform
-*
-*
-* -******************************************************************************/ - -/***************************** Include Files *********************************/ - -#include "xparameters.h" /* SDK generated parameters */ -#include "xsdps.h" /* SD device driver */ -#include "xil_printf.h" -#include "ff.h" -#include "xil_cache.h" -#include "xplatform_info.h" - -/************************** Constant Definitions *****************************/ - - -/**************************** Type Definitions *******************************/ - -/***************** Macros (Inline Functions) Definitions *********************/ - -/************************** Function Prototypes ******************************/ -int FfsSdPolledExample(void); - -/************************** Variable Definitions *****************************/ -static FIL fil; /* File object */ -static FATFS fatfs; -/* - * To test logical drive 0, FileName should be "0:/" or - * "". For logical drive 1, FileName should be "1:/" - */ -static char FileName[32] = "Test.bin"; -static char *SD_File; - -#ifdef __ICCARM__ -#pragma data_alignment = 32 -u8 DestinationAddress[10*1024]; -#pragma data_alignment = 32 -u8 SourceAddress[10*1024]; -#else -u8 DestinationAddress[10*1024] __attribute__ ((aligned(32))); -u8 SourceAddress[10*1024] __attribute__ ((aligned(32))); -#endif - -#define TEST 7 -MKFS_PARM mkfs_parm; -/*****************************************************************************/ -/** -* -* Main function to call the SD example. -* -* @param None -* -* @return XST_SUCCESS if successful, otherwise XST_FAILURE. -* -* @note None -* -******************************************************************************/ -int main(void) -{ - int Status; - - xil_printf("SD Polled File System Example Test \r\n"); - - Status = FfsSdPolledExample(); - if (Status != XST_SUCCESS) { - xil_printf("SD Polled File System Example Test failed \r\n"); - return XST_FAILURE; - } - - xil_printf("Successfully ran SD Polled File System Example Test \r\n"); - - return XST_SUCCESS; - -} - -/*****************************************************************************/ -/** -* -* File system example using SD driver to write to and read from an SD card -* in polled mode. This example creates a new file on an -* SD card (which is previously formatted with FATFS), write data to the file -* and reads the same data back to verify. -* -* @param None -* -* @return XST_SUCCESS if successful, otherwise XST_FAILURE. -* -* @note None -* -******************************************************************************/ -int FfsSdPolledExample(void) -{ - FRESULT Res; - UINT NumBytesRead; - UINT NumBytesWritten; - u32 BuffCnt; - BYTE work[FF_MAX_SS]; - u32 FileSize = (8*1024); - - /* - * To test logical drive 0, Path should be "0:/" - * For logical drive 1, Path should be "1:/" - */ - TCHAR *Path = "0:/"; - - for(BuffCnt = 0; BuffCnt < FileSize; BuffCnt++){ - SourceAddress[BuffCnt] = TEST + BuffCnt; - } - - /* - * Register volume work area, initialize device - */ - Res = f_mount(&fatfs, Path, 0); - - if (Res != FR_OK) { - return XST_FAILURE; - } - - mkfs_parm.fmt = FM_FAT32; - /* - * Path - Path to logical driver, 0 - FDISK format. - * 0 - Cluster size is automatically determined based on Vol size. - */ - Res = f_mkfs(Path, &mkfs_parm , work, sizeof work); - if (Res != FR_OK) { - return XST_FAILURE; - } - - /* - * Open file with required permissions. - * Here - Creating new file with read/write permissions. . - * To open file with write permissions, file system should not - * be in Read Only mode. - */ - SD_File = (char *)FileName; - - Res = f_open(&fil, SD_File, FA_CREATE_ALWAYS | FA_WRITE | FA_READ); - if (Res) { - return XST_FAILURE; - } - - /* - * Pointer to beginning of file . - */ - Res = f_lseek(&fil, 0); - if (Res) { - return XST_FAILURE; - } - - /* - * Write data to file. - */ - Res = f_write(&fil, (const void*)SourceAddress, FileSize, - &NumBytesWritten); - if (Res) { - return XST_FAILURE; - } - - /* - * Pointer to beginning of file . - */ - Res = f_lseek(&fil, 0); - if (Res) { - return XST_FAILURE; - } - - /* - * Read data from file. - */ - Res = f_read(&fil, (void*)DestinationAddress, FileSize, - &NumBytesRead); - if (Res) { - return XST_FAILURE; - } - - /* - * Data verification - */ - for(BuffCnt = 0; BuffCnt < FileSize; BuffCnt++){ - if(SourceAddress[BuffCnt] != DestinationAddress[BuffCnt]){ - return XST_FAILURE; - } - } - - /* - * Close file. - */ - Res = f_close(&fil); - if (Res) { - return XST_FAILURE; - } - - return XST_SUCCESS; -} diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/xilffs/src/diskio.c b/bsp_z7/ps7_cortexa9_0/libsrc/xilffs/src/diskio.c index 5ec7c0d..d5513bb 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/xilffs/src/diskio.c +++ b/bsp_z7/ps7_cortexa9_0/libsrc/xilffs/src/diskio.c @@ -1,9 +1,9 @@ /*-----------------------------------------------------------------------*/ -/* Low level disk I/O module skeleton for FatFs (C)ChaN, 2016 */ +/* Low level disk I/O module skeleton for FatFs Copyright (C)ChaN, 2016 */ /*-----------------------------------------------------------------------*/ /****************************************************************************** * Copyright (c) 2015 - 2022 Xilinx, Inc. All rights reserved. -* Copyright (c) 2022 Advanced Micro Devices, Inc. All Rights Reserved. +* Copyright (c) 2022 - 2024 Advanced Micro Devices, Inc. All Rights Reserved. ******************************************************************************/ /*****************************************************************************/ @@ -67,6 +67,9 @@ * 4.5 sk 03/31/21 Maintain discrete global variables for each controller. * 4.6 sk 07/20/21 Fixed compilation warning in RAM interface. * 4.8 sk 05/05/22 Replace standard lib functions with Xilinx functions. +* 5.1 ro 06/12/23 Added support for system device-tree flow. +* 5.2 ap 12/05/23 Add SDT check to fix bug in disk_initialize. +* ap 01/11/24 Fix Doxygen warnings. * * * @@ -76,6 +79,11 @@ #include "diskio.h" #include "ff.h" #include "xil_types.h" +#include "xstatus.h" + +#ifdef SDT +#include "xilffs_config.h" +#endif #ifdef FILE_SYSTEM_INTERFACE_SD #include "xsdps.h" /* SD device driver */ @@ -84,8 +92,8 @@ #include "xil_printf.h" #include "xil_util.h" -#define SD_CD_DELAY 10000U -#define XSDPS_NUM_INSTANCES 2 +#define SD_CD_DELAY 10000U /**< SD card detection delay */ +#define XSDPS_NUM_INSTANCES 2 /**< Number of SD instances */ #ifdef FILE_SYSTEM_INTERFACE_RAM #include "xparameters.h" @@ -110,7 +118,7 @@ static DSTATUS Stat[XSDPS_NUM_INSTANCES] = {STA_NOINIT, STA_NOINIT}; /* Disk sta #ifdef FILE_SYSTEM_INTERFACE_SD static XSdPs SdInstance[XSDPS_NUM_INSTANCES]; -static u32 BaseAddress[XSDPS_NUM_INSTANCES]; +static UINTPTR BaseAddress[XSDPS_NUM_INSTANCES]; static u32 CardDetect[XSDPS_NUM_INSTANCES]; static u32 WriteProtect[XSDPS_NUM_INSTANCES]; static u32 SlotType[XSDPS_NUM_INSTANCES]; @@ -140,7 +148,7 @@ static u8 HostCntrlrVer[XSDPS_NUM_INSTANCES]; * ******************************************************************************/ DSTATUS disk_status ( - BYTE pdrv /* Drive number (0) */ + BYTE pdrv /* Drive number (0) */ ) { DSTATUS s = Stat[pdrv]; @@ -148,68 +156,80 @@ DSTATUS disk_status ( u32 StatusReg; u32 DelayCount = 0; - if (SdInstance[pdrv].Config.BaseAddress == (u32)0) { - XSdPs_Config *SdConfig; + if (SdInstance[pdrv].Config.BaseAddress == (u32)0) { + XSdPs_Config *SdConfig; - SdConfig = XSdPs_LookupConfig((u16)pdrv); - if (NULL == SdConfig) { - s |= STA_NOINIT; - return s; - } - - BaseAddress[pdrv] = SdConfig->BaseAddress; - CardDetect[pdrv] = SdConfig->CardDetect; - WriteProtect[pdrv] = SdConfig->WriteProtect; - - HostCntrlrVer[pdrv] = (u8)(XSdPs_ReadReg16(BaseAddress[pdrv], - XSDPS_HOST_CTRL_VER_OFFSET) & XSDPS_HC_SPEC_VER_MASK); - if (HostCntrlrVer[pdrv] == XSDPS_HC_SPEC_V3) { - SlotType[pdrv] = XSdPs_ReadReg(BaseAddress[pdrv], - XSDPS_CAPS_OFFSET) & XSDPS_CAPS_SLOT_TYPE_MASK; - } else { - SlotType[pdrv] = 0; - } +#ifndef SDT + SdConfig = XSdPs_LookupConfig((u16)pdrv); +#else + if (pdrv < XPAR_XSDPS_NUM_INSTANCES) { + SdConfig = XSdPs_LookupConfig(XSdPs_ConfigTable[pdrv].BaseAddress); } - - /* If SD is not powered up then mark it as not initialized */ - if ((XSdPs_ReadReg8((u32)BaseAddress[pdrv], XSDPS_POWER_CTRL_OFFSET) & - XSDPS_PC_BUS_PWR_MASK) == 0U) { + else { + SdConfig = NULL; + } +#endif + if (NULL == SdConfig) { s |= STA_NOINIT; + return s; } - StatusReg = XSdPs_GetPresentStatusReg((u32)BaseAddress[pdrv]); - if (SlotType[pdrv] != XSDPS_CAPS_EMB_SLOT) { - if (CardDetect[pdrv]) { - while ((StatusReg & XSDPS_PSR_CARD_INSRT_MASK) == 0U) { - if (DelayCount == 500U) { - s = STA_NODISK | STA_NOINIT; - goto Label; - } else { - /* Wait for 10 msec */ - usleep(SD_CD_DELAY); - DelayCount++; - StatusReg = XSdPs_GetPresentStatusReg((u32)BaseAddress[pdrv]); - } + BaseAddress[pdrv] = SdConfig->BaseAddress; + CardDetect[pdrv] = SdConfig->CardDetect; + WriteProtect[pdrv] = SdConfig->WriteProtect; + + HostCntrlrVer[pdrv] = (u8)(XSdPs_ReadReg16(BaseAddress[pdrv], + XSDPS_HOST_CTRL_VER_OFFSET) & XSDPS_HC_SPEC_VER_MASK); + if (HostCntrlrVer[pdrv] == XSDPS_HC_SPEC_V3) { + SlotType[pdrv] = XSdPs_ReadReg(BaseAddress[pdrv], + XSDPS_CAPS_OFFSET) & XSDPS_CAPS_SLOT_TYPE_MASK; + } + else { + SlotType[pdrv] = 0; + } + } + + /* If SD is not powered up then mark it as not initialized */ + if ((XSdPs_ReadReg8(BaseAddress[pdrv], XSDPS_POWER_CTRL_OFFSET) & + XSDPS_PC_BUS_PWR_MASK) == 0U) { + s |= STA_NOINIT; + } + + StatusReg = XSdPs_GetPresentStatusReg(BaseAddress[pdrv]); + if (SlotType[pdrv] != XSDPS_CAPS_EMB_SLOT) { + if (CardDetect[pdrv]) { + while ((StatusReg & XSDPS_PSR_CARD_INSRT_MASK) == 0U) { + if (DelayCount == 500U) { + s = STA_NODISK | STA_NOINIT; + goto Label; + } + else { + /* Wait for 10 msec */ + usleep(SD_CD_DELAY); + DelayCount++; + StatusReg = XSdPs_GetPresentStatusReg(BaseAddress[pdrv]); } } - s &= ~STA_NODISK; - if (WriteProtect[pdrv]) { - if ((StatusReg & XSDPS_PSR_WPS_PL_MASK) == 0U){ - s |= STA_PROTECT; - goto Label; - } - } - s &= ~STA_PROTECT; - } else { - s &= ~STA_NODISK & ~STA_PROTECT; } + s &= ~STA_NODISK; + if (WriteProtect[pdrv]) { + if ((StatusReg & XSDPS_PSR_WPS_PL_MASK) == 0U) { + s |= STA_PROTECT; + goto Label; + } + } + s &= ~STA_PROTECT; + } + else { + s &= ~STA_NODISK & ~STA_PROTECT; + } Label: - Stat[pdrv] = s; + Stat[pdrv] = s; #endif - return s; + return s; } /*-----------------------------------------------------------------------*/ @@ -235,7 +255,7 @@ Label: * ******************************************************************************/ DSTATUS disk_initialize ( - BYTE pdrv /* Physical drive number (0) */ + BYTE pdrv /* Physical drive number (0) */ ) { DSTATUS s; @@ -256,23 +276,31 @@ DSTATUS disk_initialize ( #ifdef FILE_SYSTEM_INTERFACE_SD if (CardDetect[pdrv]) { - /* - * Card detection check - * If the HC detects the No Card State, power will be cleared - */ - while(!((XSDPS_PSR_CARD_DPL_MASK | - XSDPS_PSR_CARD_STABLE_MASK | - XSDPS_PSR_CARD_INSRT_MASK) == - (XSdPs_GetPresentStatusReg((u32)BaseAddress[pdrv]) & - (XSDPS_PSR_CARD_DPL_MASK | - XSDPS_PSR_CARD_STABLE_MASK | - XSDPS_PSR_CARD_INSRT_MASK)))); + /* + * Card detection check + * If the HC detects the No Card State, power will be cleared + */ + while (!((XSDPS_PSR_CARD_DPL_MASK | + XSDPS_PSR_CARD_STABLE_MASK | + XSDPS_PSR_CARD_INSRT_MASK) == + (XSdPs_GetPresentStatusReg(BaseAddress[pdrv]) & + (XSDPS_PSR_CARD_DPL_MASK | + XSDPS_PSR_CARD_STABLE_MASK | + XSDPS_PSR_CARD_INSRT_MASK)))); } /* * Initialize the host controller */ +#ifndef SDT SdConfig = XSdPs_LookupConfig((u16)pdrv); +#else + if (pdrv < XPAR_XSDPS_NUM_INSTANCES) { + SdConfig = XSdPs_LookupConfig(XSdPs_ConfigTable[pdrv].BaseAddress); + } else { + SdConfig = NULL; + } +#endif if (NULL == SdConfig) { s |= STA_NOINIT; return s; @@ -281,7 +309,7 @@ DSTATUS disk_initialize ( SdInstance[pdrv].IsReady = 0U; Status = XSdPs_CfgInitialize(&SdInstance[pdrv], SdConfig, - SdConfig->BaseAddress); + SdConfig->BaseAddress); if (Status != XST_SUCCESS) { s |= STA_NOINIT; return s; @@ -326,7 +354,7 @@ DSTATUS disk_initialize ( * In case of SD, it reads the SD card using ADMA2 in polled mode. * * @param pdrv - Drive number -* @param *buff - Pointer to the data buffer to store read data +* @param buff - Pointer to the data buffer to store read data * @param sector - Start sector number * @param count - Sector count * @@ -374,7 +402,7 @@ DRESULT disk_read ( #ifdef FILE_SYSTEM_INTERFACE_RAM Xil_SMemCpy(buff, count * SECTORSIZE, dataramfs + (sector * SECTORSIZE), - count * SECTORSIZE, count * SECTORSIZE); + count * SECTORSIZE, count * SECTORSIZE); #endif #if !defined(FILE_SYSTEM_INTERFACE_SD) && !defined(FILE_SYSTEM_INTERFACE_RAM) @@ -382,13 +410,32 @@ DRESULT disk_read ( (void)sector; #endif - return RES_OK; + return RES_OK; } /*-----------------------------------------------------------------------*/ /* Miscellaneous Functions */ /*-----------------------------------------------------------------------*/ +/*****************************************************************************/ +/** +* +* List specific features and do miscellaneous functions on device. +* In case of SD, it control device specific features and miscellaneous functions other than generic read/write. +* +* @param pdrv - Drive number +* @param cmd - Command code +* @param buff - Pointer to the parameter depends on the command code. +* +* @return +* RES_OK Command successful +* RES_PARERR Command is invalid +* RES_NOTRDY Drive not initialized +* RES_ERROR Error occured +* +* @note +* +******************************************************************************/ DRESULT disk_ioctl ( BYTE pdrv, /* Physical drive number (0) */ BYTE cmd, /* Control code */ @@ -436,24 +483,24 @@ DRESULT disk_ioctl ( #ifdef FILE_SYSTEM_INTERFACE_RAM switch (cmd) { - case (BYTE)CTRL_SYNC: - res = RES_OK; - break; - case (BYTE)GET_BLOCK_SIZE: - *(WORD *)buff = BLOCKSIZE; - res = RES_OK; - break; - case (BYTE)GET_SECTOR_SIZE: - *(WORD *)buff = SECTORSIZE; - res = RES_OK; - break; - case (BYTE)GET_SECTOR_COUNT: - *(DWORD *)buff = SECTORCNT; - res = RES_OK; - break; - default: - res = RES_PARERR; - break; + case (BYTE)CTRL_SYNC: + res = RES_OK; + break; + case (BYTE)GET_BLOCK_SIZE: + *(WORD *)buff = BLOCKSIZE; + res = RES_OK; + break; + case (BYTE)GET_SECTOR_SIZE: + *(WORD *)buff = SECTORSIZE; + res = RES_OK; + break; + case (BYTE)GET_SECTOR_COUNT: + *(DWORD *)buff = SECTORCNT; + res = RES_OK; + break; + default: + res = RES_PARERR; + break; } (void)pdrv; @@ -496,7 +543,7 @@ DWORD get_fattime (void) * In case of SD, it reads the SD card using ADMA2 in polled mode. * * @param pdrv - Drive number -* @param *buff - Pointer to the data to be written +* @param buff - Pointer to the data to be written * @param sector - Sector address * @param count - Sector count * @@ -545,7 +592,7 @@ DRESULT disk_write ( #ifdef FILE_SYSTEM_INTERFACE_RAM Xil_SMemCpy(dataramfs + (sector * SECTORSIZE), count * SECTORSIZE, buff, - count * SECTORSIZE, count * SECTORSIZE); + count * SECTORSIZE, count * SECTORSIZE); #endif #if !defined(FILE_SYSTEM_INTERFACE_SD) && !defined(FILE_SYSTEM_INTERFACE_RAM) @@ -555,4 +602,4 @@ DRESULT disk_write ( return RES_OK; } -#endif \ No newline at end of file +#endif diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/xilffs/src/ff.c b/bsp_z7/ps7_cortexa9_0/libsrc/xilffs/src/ff.c index b674af9..424e1b7 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/xilffs/src/ff.c +++ b/bsp_z7/ps7_cortexa9_0/libsrc/xilffs/src/ff.c @@ -1,8 +1,8 @@ /*----------------------------------------------------------------------------/ -/ FatFs - Generic FAT Filesystem Module R0.15 w/patch1 / +/ FatFs - Generic FAT Filesystem Module R0.15 w/patch3 / /-----------------------------------------------------------------------------/ / -/ Copyright (C) 2022, ChaN, all right reserved. +/ Copyright (C) 2023, ChaN, all right reserved. / / FatFs module is an open source software. Redistribution and use of FatFs in / source and binary forms, with or without modification, are permitted provided @@ -31,8 +31,15 @@ * mn 04/23/20 Add partition 0 for supporting default partition * 4.7 sk 11/11/21 Add DCache invalidate for last unaligned byte count * (< 512 bytes) in f_read(). +* 5.1 ro 06/12/23 Added support for system device-tree flow. ******************************************************************************/ #include "xparameters.h" +#include "xstatus.h" + +#ifdef SDT +#include "xilffs_config.h" +#endif + #if (defined FILE_SYSTEM_INTERFACE_SD) || (defined FILE_SYSTEM_INTERFACE_RAM) #include "ff.h" /* Declarations of FatFs API */ #include "diskio.h" /* Declarations of device I/O functions */ @@ -300,7 +307,7 @@ #error FF_FS_LOCK must be 0 at read-only configuration #endif typedef struct { - FATFS* fs; /* Object ID 1, volume (NULL:blank entry) */ + FATFS *fs; /* Object ID 1, volume (NULL:blank entry) */ DWORD clu; /* Object ID 2, containing directory (0:root) */ DWORD ofs; /* Object ID 3, offset in the directory */ UINT ctr; /* Object open counter, 0:none, 0x01..0xFF:read mode open count, 0x100:write mode */ @@ -310,141 +317,141 @@ typedef struct { /* SBCS up-case tables (\x80-\xFF) */ #define TBL_CT437 {0x80,0x9A,0x45,0x41,0x8E,0x41,0x8F,0x80,0x45,0x45,0x45,0x49,0x49,0x49,0x8E,0x8F, \ - 0x90,0x92,0x92,0x4F,0x99,0x4F,0x55,0x55,0x59,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ - 0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \ - 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ - 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ - 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \ - 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} + 0x90,0x92,0x92,0x4F,0x99,0x4F,0x55,0x55,0x59,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ + 0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \ + 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ + 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \ + 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} #define TBL_CT720 {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \ - 0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ - 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \ - 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ - 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ - 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \ - 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} + 0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ + 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \ + 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ + 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \ + 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} #define TBL_CT737 {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \ - 0x90,0x92,0x92,0x93,0x94,0x95,0x96,0x97,0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87, \ - 0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0xAA,0x92,0x93,0x94,0x95,0x96, \ - 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ - 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ - 0x97,0xEA,0xEB,0xEC,0xE4,0xED,0xEE,0xEF,0xF5,0xF0,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \ - 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} + 0x90,0x92,0x92,0x93,0x94,0x95,0x96,0x97,0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87, \ + 0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0xAA,0x92,0x93,0x94,0x95,0x96, \ + 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ + 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0x97,0xEA,0xEB,0xEC,0xE4,0xED,0xEE,0xEF,0xF5,0xF0,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \ + 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} #define TBL_CT771 {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \ - 0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ - 0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \ - 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ - 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDC,0xDE,0xDE, \ - 0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ - 0xF0,0xF0,0xF2,0xF2,0xF4,0xF4,0xF6,0xF6,0xF8,0xF8,0xFA,0xFA,0xFC,0xFC,0xFE,0xFF} + 0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ + 0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \ + 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ + 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDC,0xDE,0xDE, \ + 0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ + 0xF0,0xF0,0xF2,0xF2,0xF4,0xF4,0xF6,0xF6,0xF8,0xF8,0xFA,0xFA,0xFC,0xFC,0xFE,0xFF} #define TBL_CT775 {0x80,0x9A,0x91,0xA0,0x8E,0x95,0x8F,0x80,0xAD,0xED,0x8A,0x8A,0xA1,0x8D,0x8E,0x8F, \ - 0x90,0x92,0x92,0xE2,0x99,0x95,0x96,0x97,0x97,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \ - 0xA0,0xA1,0xE0,0xA3,0xA3,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \ - 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ - 0xB5,0xB6,0xB7,0xB8,0xBD,0xBE,0xC6,0xC7,0xA5,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ - 0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE3,0xE8,0xE8,0xEA,0xEA,0xEE,0xED,0xEE,0xEF, \ - 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} + 0x90,0x92,0x92,0xE2,0x99,0x95,0x96,0x97,0x97,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \ + 0xA0,0xA1,0xE0,0xA3,0xA3,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \ + 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ + 0xB5,0xB6,0xB7,0xB8,0xBD,0xBE,0xC6,0xC7,0xA5,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE3,0xE8,0xE8,0xEA,0xEA,0xEE,0xED,0xEE,0xEF, \ + 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} #define TBL_CT850 {0x43,0x55,0x45,0x41,0x41,0x41,0x41,0x43,0x45,0x45,0x45,0x49,0x49,0x49,0x41,0x41, \ - 0x45,0x92,0x92,0x4F,0x4F,0x4F,0x55,0x55,0x59,0x4F,0x55,0x4F,0x9C,0x4F,0x9E,0x9F, \ - 0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \ - 0xB0,0xB1,0xB2,0xB3,0xB4,0x41,0x41,0x41,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0x41,0x41,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ - 0xD1,0xD1,0x45,0x45,0x45,0x49,0x49,0x49,0x49,0xD9,0xDA,0xDB,0xDC,0xDD,0x49,0xDF, \ - 0x4F,0xE1,0x4F,0x4F,0x4F,0x4F,0xE6,0xE8,0xE8,0x55,0x55,0x55,0x59,0x59,0xEE,0xEF, \ - 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} + 0x45,0x92,0x92,0x4F,0x4F,0x4F,0x55,0x55,0x59,0x4F,0x55,0x4F,0x9C,0x4F,0x9E,0x9F, \ + 0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \ + 0xB0,0xB1,0xB2,0xB3,0xB4,0x41,0x41,0x41,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0x41,0x41,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ + 0xD1,0xD1,0x45,0x45,0x45,0x49,0x49,0x49,0x49,0xD9,0xDA,0xDB,0xDC,0xDD,0x49,0xDF, \ + 0x4F,0xE1,0x4F,0x4F,0x4F,0x4F,0xE6,0xE8,0xE8,0x55,0x55,0x55,0x59,0x59,0xEE,0xEF, \ + 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} #define TBL_CT852 {0x80,0x9A,0x90,0xB6,0x8E,0xDE,0x8F,0x80,0x9D,0xD3,0x8A,0x8A,0xD7,0x8D,0x8E,0x8F, \ - 0x90,0x91,0x91,0xE2,0x99,0x95,0x95,0x97,0x97,0x99,0x9A,0x9B,0x9B,0x9D,0x9E,0xAC, \ - 0xB5,0xD6,0xE0,0xE9,0xA4,0xA4,0xA6,0xA6,0xA8,0xA8,0xAA,0x8D,0xAC,0xB8,0xAE,0xAF, \ - 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBD,0xBF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC6,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ - 0xD1,0xD1,0xD2,0xD3,0xD2,0xD5,0xD6,0xD7,0xB7,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ - 0xE0,0xE1,0xE2,0xE3,0xE3,0xD5,0xE6,0xE6,0xE8,0xE9,0xE8,0xEB,0xED,0xED,0xDD,0xEF, \ - 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xEB,0xFC,0xFC,0xFE,0xFF} + 0x90,0x91,0x91,0xE2,0x99,0x95,0x95,0x97,0x97,0x99,0x9A,0x9B,0x9B,0x9D,0x9E,0xAC, \ + 0xB5,0xD6,0xE0,0xE9,0xA4,0xA4,0xA6,0xA6,0xA8,0xA8,0xAA,0x8D,0xAC,0xB8,0xAE,0xAF, \ + 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBD,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC6,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ + 0xD1,0xD1,0xD2,0xD3,0xD2,0xD5,0xD6,0xD7,0xB7,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE3,0xD5,0xE6,0xE6,0xE8,0xE9,0xE8,0xEB,0xED,0xED,0xDD,0xEF, \ + 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xEB,0xFC,0xFC,0xFE,0xFF} #define TBL_CT855 {0x81,0x81,0x83,0x83,0x85,0x85,0x87,0x87,0x89,0x89,0x8B,0x8B,0x8D,0x8D,0x8F,0x8F, \ - 0x91,0x91,0x93,0x93,0x95,0x95,0x97,0x97,0x99,0x99,0x9B,0x9B,0x9D,0x9D,0x9F,0x9F, \ - 0xA1,0xA1,0xA3,0xA3,0xA5,0xA5,0xA7,0xA7,0xA9,0xA9,0xAB,0xAB,0xAD,0xAD,0xAE,0xAF, \ - 0xB0,0xB1,0xB2,0xB3,0xB4,0xB6,0xB6,0xB8,0xB8,0xB9,0xBA,0xBB,0xBC,0xBE,0xBE,0xBF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ - 0xD1,0xD1,0xD3,0xD3,0xD5,0xD5,0xD7,0xD7,0xDD,0xD9,0xDA,0xDB,0xDC,0xDD,0xE0,0xDF, \ - 0xE0,0xE2,0xE2,0xE4,0xE4,0xE6,0xE6,0xE8,0xE8,0xEA,0xEA,0xEC,0xEC,0xEE,0xEE,0xEF, \ - 0xF0,0xF2,0xF2,0xF4,0xF4,0xF6,0xF6,0xF8,0xF8,0xFA,0xFA,0xFC,0xFC,0xFD,0xFE,0xFF} + 0x91,0x91,0x93,0x93,0x95,0x95,0x97,0x97,0x99,0x99,0x9B,0x9B,0x9D,0x9D,0x9F,0x9F, \ + 0xA1,0xA1,0xA3,0xA3,0xA5,0xA5,0xA7,0xA7,0xA9,0xA9,0xAB,0xAB,0xAD,0xAD,0xAE,0xAF, \ + 0xB0,0xB1,0xB2,0xB3,0xB4,0xB6,0xB6,0xB8,0xB8,0xB9,0xBA,0xBB,0xBC,0xBE,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ + 0xD1,0xD1,0xD3,0xD3,0xD5,0xD5,0xD7,0xD7,0xDD,0xD9,0xDA,0xDB,0xDC,0xDD,0xE0,0xDF, \ + 0xE0,0xE2,0xE2,0xE4,0xE4,0xE6,0xE6,0xE8,0xE8,0xEA,0xEA,0xEC,0xEC,0xEE,0xEE,0xEF, \ + 0xF0,0xF2,0xF2,0xF4,0xF4,0xF6,0xF6,0xF8,0xF8,0xFA,0xFA,0xFC,0xFC,0xFD,0xFE,0xFF} #define TBL_CT857 {0x80,0x9A,0x90,0xB6,0x8E,0xB7,0x8F,0x80,0xD2,0xD3,0xD4,0xD8,0xD7,0x49,0x8E,0x8F, \ - 0x90,0x92,0x92,0xE2,0x99,0xE3,0xEA,0xEB,0x98,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9E, \ - 0xB5,0xD6,0xE0,0xE9,0xA5,0xA5,0xA6,0xA6,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \ - 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ - 0xD0,0xD1,0xD2,0xD3,0xD4,0x49,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ - 0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xDE,0xED,0xEE,0xEF, \ - 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} + 0x90,0x92,0x92,0xE2,0x99,0xE3,0xEA,0xEB,0x98,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9E, \ + 0xB5,0xD6,0xE0,0xE9,0xA5,0xA5,0xA6,0xA6,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \ + 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ + 0xD0,0xD1,0xD2,0xD3,0xD4,0x49,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xDE,0xED,0xEE,0xEF, \ + 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} #define TBL_CT860 {0x80,0x9A,0x90,0x8F,0x8E,0x91,0x86,0x80,0x89,0x89,0x92,0x8B,0x8C,0x98,0x8E,0x8F, \ - 0x90,0x91,0x92,0x8C,0x99,0xA9,0x96,0x9D,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ - 0x86,0x8B,0x9F,0x96,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \ - 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ - 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ - 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \ - 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} + 0x90,0x91,0x92,0x8C,0x99,0xA9,0x96,0x9D,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ + 0x86,0x8B,0x9F,0x96,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \ + 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ + 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \ + 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} #define TBL_CT861 {0x80,0x9A,0x90,0x41,0x8E,0x41,0x8F,0x80,0x45,0x45,0x45,0x8B,0x8B,0x8D,0x8E,0x8F, \ - 0x90,0x92,0x92,0x4F,0x99,0x8D,0x55,0x97,0x97,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \ - 0xA4,0xA5,0xA6,0xA7,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \ - 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ - 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ - 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \ - 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} + 0x90,0x92,0x92,0x4F,0x99,0x8D,0x55,0x97,0x97,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \ + 0xA4,0xA5,0xA6,0xA7,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \ + 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ + 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \ + 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} #define TBL_CT862 {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \ - 0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ - 0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \ - 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ - 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ - 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \ - 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} + 0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ + 0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \ + 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ + 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \ + 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} #define TBL_CT863 {0x43,0x55,0x45,0x41,0x41,0x41,0x86,0x43,0x45,0x45,0x45,0x49,0x49,0x8D,0x41,0x8F, \ - 0x45,0x45,0x45,0x4F,0x45,0x49,0x55,0x55,0x98,0x4F,0x55,0x9B,0x9C,0x55,0x55,0x9F, \ - 0xA0,0xA1,0x4F,0x55,0xA4,0xA5,0xA6,0xA7,0x49,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \ - 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ - 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ - 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \ - 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} + 0x45,0x45,0x45,0x4F,0x45,0x49,0x55,0x55,0x98,0x4F,0x55,0x9B,0x9C,0x55,0x55,0x9F, \ + 0xA0,0xA1,0x4F,0x55,0xA4,0xA5,0xA6,0xA7,0x49,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \ + 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ + 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \ + 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} #define TBL_CT864 {0x80,0x9A,0x45,0x41,0x8E,0x41,0x8F,0x80,0x45,0x45,0x45,0x49,0x49,0x49,0x8E,0x8F, \ - 0x90,0x92,0x92,0x4F,0x99,0x4F,0x55,0x55,0x59,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ - 0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \ - 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ - 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ - 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \ - 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} + 0x90,0x92,0x92,0x4F,0x99,0x4F,0x55,0x55,0x59,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ + 0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \ + 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ + 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \ + 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} #define TBL_CT865 {0x80,0x9A,0x90,0x41,0x8E,0x41,0x8F,0x80,0x45,0x45,0x45,0x49,0x49,0x49,0x8E,0x8F, \ - 0x90,0x92,0x92,0x4F,0x99,0x4F,0x55,0x55,0x59,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ - 0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \ - 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ - 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ - 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \ - 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} + 0x90,0x92,0x92,0x4F,0x99,0x4F,0x55,0x55,0x59,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ + 0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \ + 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ + 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \ + 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} #define TBL_CT866 {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \ - 0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ - 0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \ - 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ - 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ - 0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ - 0xF0,0xF0,0xF2,0xF2,0xF4,0xF4,0xF6,0xF6,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} + 0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ + 0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \ + 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ + 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ + 0xF0,0xF0,0xF2,0xF2,0xF4,0xF4,0xF6,0xF6,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} #define TBL_CT869 {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \ - 0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x86,0x9C,0x8D,0x8F,0x90, \ - 0x91,0x90,0x92,0x95,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \ - 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ - 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xA4,0xA5,0xA6,0xD9,0xDA,0xDB,0xDC,0xA7,0xA8,0xDF, \ - 0xA9,0xAA,0xAC,0xAD,0xB5,0xB6,0xB7,0xB8,0xBD,0xBE,0xC6,0xC7,0xCF,0xCF,0xD0,0xEF, \ - 0xF0,0xF1,0xD1,0xD2,0xD3,0xF5,0xD4,0xF7,0xF8,0xF9,0xD5,0x96,0x95,0x98,0xFE,0xFF} + 0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x86,0x9C,0x8D,0x8F,0x90, \ + 0x91,0x90,0x92,0x95,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \ + 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ + 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xA4,0xA5,0xA6,0xD9,0xDA,0xDB,0xDC,0xA7,0xA8,0xDF, \ + 0xA9,0xAA,0xAC,0xAD,0xB5,0xB6,0xB7,0xB8,0xBD,0xBE,0xC6,0xC7,0xCF,0xCF,0xD0,0xEF, \ + 0xF0,0xF1,0xD1,0xD2,0xD3,0xF5,0xD4,0xF7,0xF8,0xF9,0xD5,0x96,0x95,0x98,0xFE,0xFF} /* DBCS code range |----- 1st byte -----| |----------- 2nd byte -----------| */ @@ -485,10 +492,11 @@ static WORD Fsid; /* Filesystem mount ID */ static BYTE CurrVol; /* Current drive set by f_chdrive() */ #endif -#if FF_FS_LOCK != 0 +#if FF_FS_LOCK static FILESEM Files[FF_FS_LOCK]; /* Open object lock semaphores */ #if FF_FS_REENTRANT -static BYTE SysLock; /* System lock flag (0:no mutex, 1:unlocked, 2:locked) */ +static volatile BYTE SysLock; /* System lock flag to protect Files[] (0:no mutex, 1:unlocked, 2:locked) */ +static volatile BYTE SysLockVolume; /* Volume id who is locking Files[] */ #endif #endif @@ -502,7 +510,7 @@ static const char *const VolumeStr[FF_VOLUMES] = {FF_VOLUME_STRS}; /* Pre-define #if FF_MIN_GPT > 0x100000000 #error Wrong FF_MIN_GPT setting #endif -static const BYTE GUID_MS_Basic[16] = {0xA2,0xA0,0xD0,0xEB,0xE5,0xB9,0x33,0x44,0x87,0xC0,0x68,0xB6,0xB7,0x26,0x99,0xC7}; +static const BYTE GUID_MS_Basic[16] = {0xA2, 0xA0, 0xD0, 0xEB, 0xE5, 0xB9, 0x33, 0x44, 0x87, 0xC0, 0x68, 0xB6, 0xB7, 0x26, 0x99, 0xC7}; #endif @@ -530,7 +538,7 @@ static const BYTE GUID_MS_Basic[16] = {0xA2,0xA0,0xD0,0xEB,0xE5,0xB9,0x33,0x44,0 #if FF_LFN_UNICODE < 0 || FF_LFN_UNICODE > 3 #error Wrong setting of FF_LFN_UNICODE #endif -static const BYTE LfnOfs[] = {1,3,5,7,9,14,16,18,20,22,24,28,30}; /* FAT: Offset of LFN characters in the directory entry */ +static const BYTE LfnOfs[] = {1, 3, 5, 7, 9, 14, 16, 18, 20, 22, 24, 28, 30}; /* FAT: Offset of LFN characters in the directory entry */ #define MAXDIRB(nc) ((nc + 44U) / 15 * SZDIRE) /* exFAT: Size of directory entry block scratchpad buffer needed for the name length */ #if FF_USE_LFN == 1 /* LFN enabled with static working buffer */ @@ -583,8 +591,8 @@ static WCHAR LfnBuf[FF_MAX_LFN + 1]; /* LFN working buffer */ #if FF_CODE_PAGE == 0 /* Run-time code page configuration */ #define CODEPAGE CodePage static WORD CodePage; /* Current code page */ -static const BYTE* ExCvt; /* Ptr to SBCS up-case table Ct???[] (null:not used) */ -static const BYTE* DbcTbl; /* Ptr to DBCS code range table Dc???[] (null:not used) */ +static const BYTE *ExCvt; /* Ptr to SBCS up-case table Ct???[] (null:not used) */ +static const BYTE *DbcTbl; /* Ptr to DBCS code range table Dc???[] (null:not used) */ static const BYTE Ct437[] = TBL_CT437; static const BYTE Ct720[] = TBL_CT720; @@ -646,7 +654,7 @@ PARTITION VolToPart[] = { /* Load/Store multi-byte word in the FAT structure */ /*-----------------------------------------------------------------------*/ -static WORD ld_word (const BYTE* ptr) /* Load a 2-byte little-endian word */ +static WORD ld_word (const BYTE *ptr) /* Load a 2-byte little-endian word */ { WORD rv; @@ -655,7 +663,7 @@ static WORD ld_word (const BYTE* ptr) /* Load a 2-byte little-endian word */ return rv; } -static DWORD ld_dword (const BYTE* ptr) /* Load a 4-byte little-endian word */ +static DWORD ld_dword (const BYTE *ptr) /* Load a 4-byte little-endian word */ { DWORD rv; @@ -667,7 +675,7 @@ static DWORD ld_dword (const BYTE* ptr) /* Load a 4-byte little-endian word */ } #if FF_FS_EXFAT -static QWORD ld_qword (const BYTE* ptr) /* Load an 8-byte little-endian word */ +static QWORD ld_qword (const BYTE *ptr) /* Load an 8-byte little-endian word */ { QWORD rv; @@ -684,30 +692,41 @@ static QWORD ld_qword (const BYTE* ptr) /* Load an 8-byte little-endian word */ #endif #if !FF_FS_READONLY -static void st_word (BYTE* ptr, WORD val) /* Store a 2-byte word in little-endian */ +static void st_word (BYTE *ptr, WORD val) /* Store a 2-byte word in little-endian */ { - *ptr++ = (BYTE)val; val >>= 8; + *ptr++ = (BYTE)val; + val >>= 8; *ptr++ = (BYTE)val; } -static void st_dword (BYTE* ptr, DWORD val) /* Store a 4-byte word in little-endian */ +static void st_dword (BYTE *ptr, DWORD val) /* Store a 4-byte word in little-endian */ { - *ptr++ = (BYTE)val; val >>= 8; - *ptr++ = (BYTE)val; val >>= 8; - *ptr++ = (BYTE)val; val >>= 8; + *ptr++ = (BYTE)val; + val >>= 8; + *ptr++ = (BYTE)val; + val >>= 8; + *ptr++ = (BYTE)val; + val >>= 8; *ptr++ = (BYTE)val; } #if FF_FS_EXFAT -static void st_qword (BYTE* ptr, QWORD val) /* Store an 8-byte word in little-endian */ +static void st_qword (BYTE *ptr, QWORD val) /* Store an 8-byte word in little-endian */ { - *ptr++ = (BYTE)val; val >>= 8; - *ptr++ = (BYTE)val; val >>= 8; - *ptr++ = (BYTE)val; val >>= 8; - *ptr++ = (BYTE)val; val >>= 8; - *ptr++ = (BYTE)val; val >>= 8; - *ptr++ = (BYTE)val; val >>= 8; - *ptr++ = (BYTE)val; val >>= 8; + *ptr++ = (BYTE)val; + val >>= 8; + *ptr++ = (BYTE)val; + val >>= 8; + *ptr++ = (BYTE)val; + val >>= 8; + *ptr++ = (BYTE)val; + val >>= 8; + *ptr++ = (BYTE)val; + val >>= 8; + *ptr++ = (BYTE)val; + val >>= 8; + *ptr++ = (BYTE)val; + val >>= 8; *ptr++ = (BYTE)val; } #endif @@ -720,21 +739,23 @@ static void st_qword (BYTE* ptr, QWORD val) /* Store an 8-byte word in little-en /*-----------------------------------------------------------------------*/ /* Copy memory to memory */ -static void mem_cpy (void* dst, const void* src, UINT cnt) +static void mem_cpy (void *dst, const void *src, UINT cnt) { - BYTE *d = (BYTE*)dst; - const BYTE *s = (const BYTE*)src; + BYTE *d = (BYTE *)dst; + const BYTE *s = (const BYTE *)src; #if FF_WORD_ACCESS == 1 while (cnt >= sizeof (int)) { - *(int*)d = *(int*)s; - d += sizeof (int); s += sizeof (int); + *(int *)d = *(int *)s; + d += sizeof (int); + s += sizeof (int); cnt -= sizeof (int); } #endif if (cnt != 0) { do { *d++ = *s++; - } while (--cnt); + } + while (--cnt); } } /* Test if the byte is DBC 1st byte */ @@ -742,16 +763,26 @@ static int dbc_1st (BYTE c) { #if FF_CODE_PAGE == 0 /* Variable code page */ if (DbcTbl && c >= DbcTbl[0]) { - if (c <= DbcTbl[1]) return 1; /* 1st byte range 1 */ - if (c >= DbcTbl[2] && c <= DbcTbl[3]) return 1; /* 1st byte range 2 */ + if (c <= DbcTbl[1]) { + return 1; /* 1st byte range 1 */ + } + if (c >= DbcTbl[2] && c <= DbcTbl[3]) { + return 1; /* 1st byte range 2 */ + } } #elif FF_CODE_PAGE >= 900 /* DBCS fixed code page */ if (c >= DbcTbl[0]) { - if (c <= DbcTbl[1]) return 1; - if (c >= DbcTbl[2] && c <= DbcTbl[3]) return 1; + if (c <= DbcTbl[1]) { + return 1; + } + if (c >= DbcTbl[2] && c <= DbcTbl[3]) { + return 1; + } } #else /* SBCS fixed code page */ - if (c != 0) return 0; /* Always false */ + if (c != 0) { + return 0; /* Always false */ + } #endif return 0; } @@ -762,18 +793,32 @@ static int dbc_2nd (BYTE c) { #if FF_CODE_PAGE == 0 /* Variable code page */ if (DbcTbl && c >= DbcTbl[4]) { - if (c <= DbcTbl[5]) return 1; /* 2nd byte range 1 */ - if (c >= DbcTbl[6] && c <= DbcTbl[7]) return 1; /* 2nd byte range 2 */ - if (c >= DbcTbl[8] && c <= DbcTbl[9]) return 1; /* 2nd byte range 3 */ + if (c <= DbcTbl[5]) { + return 1; /* 2nd byte range 1 */ + } + if (c >= DbcTbl[6] && c <= DbcTbl[7]) { + return 1; /* 2nd byte range 2 */ + } + if (c >= DbcTbl[8] && c <= DbcTbl[9]) { + return 1; /* 2nd byte range 3 */ + } } #elif FF_CODE_PAGE >= 900 /* DBCS fixed code page */ if (c >= DbcTbl[4]) { - if (c <= DbcTbl[5]) return 1; - if (c >= DbcTbl[6] && c <= DbcTbl[7]) return 1; - if (c >= DbcTbl[8] && c <= DbcTbl[9]) return 1; + if (c <= DbcTbl[5]) { + return 1; + } + if (c >= DbcTbl[6] && c <= DbcTbl[7]) { + return 1; + } + if (c >= DbcTbl[8] && c <= DbcTbl[9]) { + return 1; + } } #else /* SBCS fixed code page */ - if (c != 0) return 0; /* Always false */ + if (c != 0) { + return 0; /* Always false */ + } #endif return 0; } @@ -782,8 +827,9 @@ static int dbc_2nd (BYTE c) #if FF_USE_LFN /* Get a Unicode code point from the TCHAR string in defined API encodeing */ -static DWORD tchar2uni ( /* Returns a character in UTF-16 encoding (>=0x10000 on surrogate pair, 0xFFFFFFFF on decode error) */ - const TCHAR** str /* Pointer to pointer to TCHAR string in configured encoding */ +static DWORD +tchar2uni ( /* Returns a character in UTF-16 encoding (>=0x10000 on surrogate pair, 0xFFFFFFFF on decode error) */ + const TCHAR **str /* Pointer to pointer to TCHAR string in configured encoding */ ) { DWORD uc; @@ -795,7 +841,9 @@ static DWORD tchar2uni ( /* Returns a character in UTF-16 encoding (>=0x10000 on uc = *p++; /* Get a unit */ if (IsSurrogate(uc)) { /* Surrogate? */ wc = *p++; /* Get low surrogate */ - if (!IsSurrogateH(uc) || !IsSurrogateL(wc)) return 0xFFFFFFFF; /* Wrong surrogate? */ + if (!IsSurrogateH(uc) || !IsSurrogateL(wc)) { + return 0xFFFFFFFF; /* Wrong surrogate? */ + } uc = uc << 16 | wc; } @@ -803,44 +851,65 @@ static DWORD tchar2uni ( /* Returns a character in UTF-16 encoding (>=0x10000 on BYTE b; int nf; - uc = (BYTE)*p++; /* Get an encoding unit */ + uc = (BYTE) * p++; /* Get an encoding unit */ if (uc & 0x80) { /* Multiple byte code? */ if ((uc & 0xE0) == 0xC0) { /* 2-byte sequence? */ - uc &= 0x1F; nf = 1; - } else if ((uc & 0xF0) == 0xE0) { /* 3-byte sequence? */ - uc &= 0x0F; nf = 2; - } else if ((uc & 0xF8) == 0xF0) { /* 4-byte sequence? */ - uc &= 0x07; nf = 3; - } else { /* Wrong sequence */ + uc &= 0x1F; + nf = 1; + } + else if ((uc & 0xF0) == 0xE0) { /* 3-byte sequence? */ + uc &= 0x0F; + nf = 2; + } + else if ((uc & 0xF8) == 0xF0) { /* 4-byte sequence? */ + uc &= 0x07; + nf = 3; + } + else { /* Wrong sequence */ return 0xFFFFFFFF; } do { /* Get trailing bytes */ - b = (BYTE)*p++; - if ((b & 0xC0) != 0x80) return 0xFFFFFFFF; /* Wrong sequence? */ + b = (BYTE) * p++; + if ((b & 0xC0) != 0x80) { + return 0xFFFFFFFF; /* Wrong sequence? */ + } uc = uc << 6 | (b & 0x3F); - } while (--nf != 0); - if (uc < 0x80 || IsSurrogate(uc) || uc >= 0x110000) return 0xFFFFFFFF; /* Wrong code? */ - if (uc >= 0x010000) uc = 0xD800DC00 | ((uc - 0x10000) << 6 & 0x3FF0000) | (uc & 0x3FF); /* Make a surrogate pair if needed */ + } + while (--nf != 0); + if (uc < 0x80 || IsSurrogate(uc) || uc >= 0x110000) { + return 0xFFFFFFFF; /* Wrong code? */ + } + if (uc >= 0x010000) { + uc = 0xD800DC00 | ((uc - 0x10000) << 6 & 0x3FF0000) | (uc & 0x3FF); /* Make a surrogate pair if needed */ + } } #elif FF_LFN_UNICODE == 3 /* UTF-32 input */ - uc = (TCHAR)*p++; /* Get a unit */ - if (uc >= 0x110000 || IsSurrogate(uc)) return 0xFFFFFFFF; /* Wrong code? */ - if (uc >= 0x010000) uc = 0xD800DC00 | ((uc - 0x10000) << 6 & 0x3FF0000) | (uc & 0x3FF); /* Make a surrogate pair if needed */ + uc = (TCHAR) * p++; /* Get a unit */ + if (uc >= 0x110000 || IsSurrogate(uc)) { + return 0xFFFFFFFF; /* Wrong code? */ + } + if (uc >= 0x010000) { + uc = 0xD800DC00 | ((uc - 0x10000) << 6 & 0x3FF0000) | (uc & 0x3FF); /* Make a surrogate pair if needed */ + } #else /* ANSI/OEM input */ BYTE b; WCHAR wc; - wc = (BYTE)*p++; /* Get a byte */ + wc = (BYTE) * p++; /* Get a byte */ if (dbc_1st((BYTE)wc)) { /* Is it a DBC 1st byte? */ - b = (BYTE)*p++; /* Get 2nd byte */ - if (!dbc_2nd(b)) return 0xFFFFFFFF; /* Invalid code? */ + b = (BYTE) * p++; /* Get 2nd byte */ + if (!dbc_2nd(b)) { + return 0xFFFFFFFF; /* Invalid code? */ + } wc = (wc << 8) + b; /* Make a DBC */ } if (wc != 0) { wc = ff_oem2uni(wc, CODEPAGE); /* ANSI/OEM ==> Unicode */ - if (wc == 0) return 0xFFFFFFFF; /* Invalid code? */ + if (wc == 0) { + return 0xFFFFFFFF; /* Invalid code? */ + } } uc = wc; @@ -853,7 +922,7 @@ static DWORD tchar2uni ( /* Returns a character in UTF-16 encoding (>=0x10000 on /* Store a Unicode char in defined API encoding */ static UINT put_utf ( /* Returns number of encoding units written (0:buffer overflow or wrong encoding) */ DWORD chr, /* UTF-16 encoded character (Surrogate pair if >=0x10000) */ - TCHAR* buf, /* Output buffer */ + TCHAR *buf, /* Output buffer */ UINT szb /* Size of the buffer */ ) { @@ -863,11 +932,15 @@ static UINT put_utf ( /* Returns number of encoding units written (0:buffer over hs = (WCHAR)(chr >> 16); wc = (WCHAR)chr; if (hs == 0) { /* Single encoding unit? */ - if (szb < 1 || IsSurrogate(wc)) return 0; /* Buffer overflow or wrong code? */ + if (szb < 1 || IsSurrogate(wc)) { + return 0; /* Buffer overflow or wrong code? */ + } *buf = wc; return 1; } - if (szb < 2 || !IsSurrogateH(hs) || !IsSurrogateL(wc)) return 0; /* Buffer overflow or wrong surrogate? */ + if (szb < 2 || !IsSurrogateH(hs) || !IsSurrogateL(wc)) { + return 0; /* Buffer overflow or wrong surrogate? */ + } *buf++ = hs; *buf++ = wc; return 2; @@ -876,28 +949,38 @@ static UINT put_utf ( /* Returns number of encoding units written (0:buffer over DWORD hc; if (chr < 0x80) { /* Single byte code? */ - if (szb < 1) return 0; /* Buffer overflow? */ + if (szb < 1) { + return 0; /* Buffer overflow? */ + } *buf = (TCHAR)chr; return 1; } if (chr < 0x800) { /* 2-byte sequence? */ - if (szb < 2) return 0; /* Buffer overflow? */ + if (szb < 2) { + return 0; /* Buffer overflow? */ + } *buf++ = (TCHAR)(0xC0 | (chr >> 6 & 0x1F)); *buf++ = (TCHAR)(0x80 | (chr >> 0 & 0x3F)); return 2; } if (chr < 0x10000) { /* 3-byte sequence? */ - if (szb < 3 || IsSurrogate(chr)) return 0; /* Buffer overflow or wrong code? */ + if (szb < 3 || IsSurrogate(chr)) { + return 0; /* Buffer overflow or wrong code? */ + } *buf++ = (TCHAR)(0xE0 | (chr >> 12 & 0x0F)); *buf++ = (TCHAR)(0x80 | (chr >> 6 & 0x3F)); *buf++ = (TCHAR)(0x80 | (chr >> 0 & 0x3F)); return 3; } /* 4-byte sequence */ - if (szb < 4) return 0; /* Buffer overflow? */ + if (szb < 4) { + return 0; /* Buffer overflow? */ + } hc = ((chr & 0xFFFF0000) - 0xD8000000) >> 6; /* Get high 10 bits */ chr = (chr & 0xFFFF) - 0xDC00; /* Get low 10 bits */ - if (hc >= 0x100000 || chr >= 0x400) return 0; /* Wrong surrogate? */ + if (hc >= 0x100000 || chr >= 0x400) { + return 0; /* Wrong surrogate? */ + } chr = (hc | chr) + 0x10000; *buf++ = (TCHAR)(0xF0 | (chr >> 18 & 0x07)); *buf++ = (TCHAR)(0x80 | (chr >> 12 & 0x3F)); @@ -908,11 +991,15 @@ static UINT put_utf ( /* Returns number of encoding units written (0:buffer over #elif FF_LFN_UNICODE == 3 /* UTF-32 output */ DWORD hc; - if (szb < 1) return 0; /* Buffer overflow? */ + if (szb < 1) { + return 0; /* Buffer overflow? */ + } if (chr >= 0x10000) { /* Out of BMP? */ hc = ((chr & 0xFFFF0000) - 0xD8000000) >> 6; /* Get high 10 bits */ chr = (chr & 0xFFFF) - 0xDC00; /* Get low 10 bits */ - if (hc >= 0x100000 || chr >= 0x400) return 0; /* Wrong surrogate? */ + if (hc >= 0x100000 || chr >= 0x400) { + return 0; /* Wrong surrogate? */ + } chr = (hc | chr) + 0x10000; } *buf++ = (TCHAR)chr; @@ -923,12 +1010,16 @@ static UINT put_utf ( /* Returns number of encoding units written (0:buffer over wc = ff_uni2oem(chr, CODEPAGE); if (wc >= 0x100) { /* Is this a DBC? */ - if (szb < 2) return 0; + if (szb < 2) { + return 0; + } *buf++ = (char)(wc >> 8); /* Store DBC 1st byte */ *buf++ = (TCHAR)wc; /* Store DBC 2nd byte */ return 2; } - if (wc == 0 || szb < 1) return 0; /* Invalid char or buffer overflow? */ + if (wc == 0 || szb < 1) { + return 0; /* Invalid char or buffer overflow? */ + } *buf++ = (TCHAR)wc; /* Store the character */ return 1; #endif @@ -942,7 +1033,7 @@ static UINT put_utf ( /* Returns number of encoding units written (0:buffer over /*-----------------------------------------------------------------------*/ static int lock_volume ( /* 1:Ok, 0:timeout */ - FATFS* fs, /* Filesystem object to lock */ + FATFS *fs, /* Filesystem object to lock */ int syslock /* System lock required */ ) { @@ -954,26 +1045,29 @@ static int lock_volume ( /* 1:Ok, 0:timeout */ if (rv && syslock) { /* System lock reqiered? */ rv = ff_mutex_take(FF_VOLUMES); /* Lock the system */ if (rv) { + SysLockVolume = fs->ldrv; SysLock = 2; /* System lock succeeded */ - } else { + } + else { ff_mutex_give(fs->ldrv); /* Failed system lock */ } } #else - rv = syslock ? ff_mutex_take(fs->ldrv) : ff_mutex_take(fs->ldrv); /* Lock the volume (this is to prevent compiler warning) */ + rv = syslock ? ff_mutex_take(fs->ldrv) : ff_mutex_take( + fs->ldrv); /* Lock the volume (this is to prevent compiler warning) */ #endif return rv; } static void unlock_volume ( - FATFS* fs, /* Filesystem object */ + FATFS *fs, /* Filesystem object */ FRESULT res /* Result code to be returned */ ) { if (fs && res != FR_NOT_ENABLED && res != FR_INVALID_DRIVE && res != FR_TIMEOUT) { #if FF_FS_LOCK - if (SysLock == 2) { /* Is the system locked? */ + if (SysLock == 2 && SysLockVolume == fs->ldrv) { /* Unlock system if it has been locked by this task */ SysLock = 1; ff_mutex_give(FF_VOLUMES); } @@ -992,7 +1086,7 @@ static void unlock_volume ( /*-----------------------------------------------------------------------*/ static FRESULT chk_share ( /* Check if the file can be accessed */ - DIR* dp, /* Directory object pointing the file to be checked */ + DIR *dp, /* Directory object pointing the file to be checked */ int acc /* Desired access type (0:Read mode open, 1:Write mode open, 2:Delete or rename) */ ) { @@ -1003,9 +1097,12 @@ static FRESULT chk_share ( /* Check if the file can be accessed */ for (i = 0; i < FF_FS_LOCK; i++) { if (Files[i].fs) { /* Existing entry */ if (Files[i].fs == dp->obj.fs && /* Check if the object matches with an open object */ - Files[i].clu == dp->obj.sclust && - Files[i].ofs == dp->dptr) break; - } else { /* Blank entry */ + Files[i].clu == dp->obj.sclust && + Files[i].ofs == dp->dptr) { + break; + } + } + else { /* Blank entry */ be = 1; } } @@ -1028,7 +1125,7 @@ static int enq_share (void) /* Check if an entry is available for a new object * static UINT inc_share ( /* Increment object open counter and returns its index (0:Internal error) */ - DIR* dp, /* Directory object pointing the file to register or increment */ + DIR *dp, /* Directory object pointing the file to register or increment */ int acc /* Desired access (0:Read, 1:Write, 2:Delete/Rename) */ ) { @@ -1037,20 +1134,26 @@ static UINT inc_share ( /* Increment object open counter and returns its index ( for (i = 0; i < FF_FS_LOCK; i++) { /* Find the object */ if (Files[i].fs == dp->obj.fs - && Files[i].clu == dp->obj.sclust - && Files[i].ofs == dp->dptr) break; + && Files[i].clu == dp->obj.sclust + && Files[i].ofs == dp->dptr) { + break; + } } if (i == FF_FS_LOCK) { /* Not opened. Register it as new. */ for (i = 0; i < FF_FS_LOCK && Files[i].fs; i++) ; /* Find a free entry */ - if (i == FF_FS_LOCK) return 0; /* No free entry to register (int err) */ + if (i == FF_FS_LOCK) { + return 0; /* No free entry to register (int err) */ + } Files[i].fs = dp->obj.fs; Files[i].clu = dp->obj.sclust; Files[i].ofs = dp->dptr; Files[i].ctr = 0; } - if (acc >= 1 && Files[i].ctr) return 0; /* Access violation (int err) */ + if (acc >= 1 && Files[i].ctr) { + return 0; /* Access violation (int err) */ + } Files[i].ctr = acc ? 0x100 : Files[i].ctr + 1; /* Set semaphore value */ @@ -1068,14 +1171,20 @@ static FRESULT dec_share ( /* Decrement object open counter */ if (--i < FF_FS_LOCK) { /* Index number origin from 0 */ n = Files[i].ctr; - if (n == 0x100) n = 0; /* If write mode open, delete the object semaphore */ - if (n > 0) n--; /* Decrement read mode open count */ + if (n == 0x100) { + n = 0; /* If write mode open, delete the object semaphore */ + } + if (n > 0) { + n--; /* Decrement read mode open count */ + } Files[i].ctr = n; if (n == 0) { /* Delete the object semaphore if open count becomes zero */ - Files[i].fs = 0; /* Free the entry << 1, there is a potential error in this process >>> */ + Files[i].fs = + 0; /* Free the entry << 1, there is a potential error in this process >>> */ } res = FR_OK; - } else { + } + else { res = FR_INT_ERR; /* Invalid index number */ } return res; @@ -1083,13 +1192,15 @@ static FRESULT dec_share ( /* Decrement object open counter */ static void clear_share ( /* Clear all lock entries of the volume */ - FATFS* fs + FATFS *fs ) { UINT i; for (i = 0; i < FF_FS_LOCK; i++) { - if (Files[i].fs == fs) Files[i].fs = 0; + if (Files[i].fs == fs) { + Files[i].fs = 0; + } } } @@ -1102,7 +1213,7 @@ static void clear_share ( /* Clear all lock entries of the volume */ /*-----------------------------------------------------------------------*/ #if !FF_FS_READONLY static FRESULT sync_window ( /* Returns FR_OK or FR_DISK_ERR */ - FATFS* fs /* Filesystem object */ + FATFS *fs /* Filesystem object */ ) { FRESULT res = FR_DISK_ERR; @@ -1112,11 +1223,14 @@ static FRESULT sync_window ( /* Returns FR_OK or FR_DISK_ERR */ if (disk_write(fs->pdrv, fs->win, fs->winsect, 1) == RES_OK) { /* Write it back into the volume */ fs->wflag = 0; /* Clear window dirty flag */ if (fs->winsect - fs->fatbase < fs->fsize) { /* Is it in the 1st FAT? */ - if (fs->n_fats == 2) disk_write(fs->pdrv, fs->win, fs->winsect + fs->fsize, 1); /* Reflect it to 2nd FAT if needed */ + if (fs->n_fats == 2) { + disk_write(fs->pdrv, fs->win, fs->winsect + fs->fsize, 1); /* Reflect it to 2nd FAT if needed */ + } } res = FR_OK; } - } else { + } + else { res = FR_OK; } @@ -1126,7 +1240,7 @@ static FRESULT sync_window ( /* Returns FR_OK or FR_DISK_ERR */ static FRESULT move_window ( /* Returns FR_OK or FR_DISK_ERR */ - FATFS* fs, /* Filesystem object */ + FATFS *fs, /* Filesystem object */ LBA_t sect /* Sector LBA to make appearance in the fs->win[] */ ) { @@ -1140,14 +1254,16 @@ static FRESULT move_window ( /* Returns FR_OK or FR_DISK_ERR */ if (disk_read(fs->pdrv, fs->win, sect, 1) != RES_OK) { sect = (LBA_t)0 - 1; /* Invalidate window if read data is not valid */ res = FR_DISK_ERR; - } else { + } + else { res = FR_OK; } fs->winsect = sect; #if !FF_FS_READONLY } #endif - } else { + } + else { res = FR_OK; } return res; @@ -1162,7 +1278,7 @@ static FRESULT move_window ( /* Returns FR_OK or FR_DISK_ERR */ /*-----------------------------------------------------------------------*/ static FRESULT sync_fs ( /* Returns FR_OK or FR_DISK_ERR */ - FATFS* fs /* Filesystem object */ + FATFS *fs /* Filesystem object */ ) { FRESULT res = FR_DISK_ERR; @@ -1183,7 +1299,9 @@ static FRESULT sync_fs ( /* Returns FR_OK or FR_DISK_ERR */ fs->fsi_flag = 0; } /* Make sure that no pending write process in the lower layer */ - if (disk_ioctl(fs->pdrv, CTRL_SYNC, 0) != RES_OK) res = FR_DISK_ERR; + if (disk_ioctl(fs->pdrv, CTRL_SYNC, 0) != RES_OK) { + res = FR_DISK_ERR; + } } return res; @@ -1198,12 +1316,14 @@ static FRESULT sync_fs ( /* Returns FR_OK or FR_DISK_ERR */ /*-----------------------------------------------------------------------*/ static LBA_t clst2sect ( /* !=0:Sector number, 0:Failed (invalid cluster#) */ - FATFS* fs, /* Filesystem object */ + FATFS *fs, /* Filesystem object */ DWORD clst /* Cluster# to be converted */ ) { clst -= 2; /* Cluster number is origin from 2 */ - if (clst >= fs->n_fatent - 2) return 0; /* Is it invalid cluster number? */ + if (clst >= fs->n_fatent - 2) { + return 0; /* Is it invalid cluster number? */ + } return fs->database + (LBA_t)fs->csize * clst; /* Start sector number of the cluster */ } @@ -1215,7 +1335,7 @@ static LBA_t clst2sect ( /* !=0:Sector number, 0:Failed (invalid cluster#) */ /*-----------------------------------------------------------------------*/ static DWORD get_fat ( /* 0xFFFFFFFF:Disk error, 1:Internal error, 2..0x7FFFFFFF:Cluster status */ - FFOBJID* obj, /* Corresponding object */ + FFOBJID *obj, /* Corresponding object */ DWORD clst /* Cluster number to get the value */ ) { @@ -1227,57 +1347,71 @@ static DWORD get_fat ( /* 0xFFFFFFFF:Disk error, 1:Internal error, 2..0x7FFFFFF if (clst < 2 || clst >= fs->n_fatent) { /* Check if in valid range */ val = 1; /* Internal error */ - } else { + } + else { val = 0xFFFFFFFF; /* Default value falls on disk error */ switch (fs->fs_type) { - case FS_FAT12 : - bc = (UINT)clst; bc += bc / 2; - if (move_window(fs, fs->fatbase + (bc / SS(fs))) != FR_OK) break; - wc = fs->win[bc++ % SS(fs)]; /* Get 1st byte of the entry */ - if (move_window(fs, fs->fatbase + (bc / SS(fs))) != FR_OK) break; - wc |= fs->win[bc % SS(fs)] << 8; /* Merge 2nd byte of the entry */ - val = (clst & 1) ? (wc >> 4) : (wc & 0xFFF); /* Adjust bit position */ - break; + case FS_FAT12 : + bc = (UINT)clst; + bc += bc / 2; + if (move_window(fs, fs->fatbase + (bc / SS(fs))) != FR_OK) { + break; + } + wc = fs->win[bc++ % SS(fs)]; /* Get 1st byte of the entry */ + if (move_window(fs, fs->fatbase + (bc / SS(fs))) != FR_OK) { + break; + } + wc |= fs->win[bc % SS(fs)] << 8; /* Merge 2nd byte of the entry */ + val = (clst & 1) ? (wc >> 4) : (wc & 0xFFF); /* Adjust bit position */ + break; - case FS_FAT16 : - if (move_window(fs, fs->fatbase + (clst / (SS(fs) / 2))) != FR_OK) break; - val = ld_word(fs->win + clst * 2 % SS(fs)); /* Simple WORD array */ - break; + case FS_FAT16 : + if (move_window(fs, fs->fatbase + (clst / (SS(fs) / 2))) != FR_OK) { + break; + } + val = ld_word(fs->win + clst * 2 % SS(fs)); /* Simple WORD array */ + break; - case FS_FAT32 : - if (move_window(fs, fs->fatbase + (clst / (SS(fs) / 4))) != FR_OK) break; - val = ld_dword(fs->win + clst * 4 % SS(fs)) & 0x0FFFFFFF; /* Simple DWORD array but mask out upper 4 bits */ - break; + case FS_FAT32 : + if (move_window(fs, fs->fatbase + (clst / (SS(fs) / 4))) != FR_OK) { + break; + } + val = ld_dword(fs->win + clst * 4 % SS(fs)) & 0x0FFFFFFF; /* Simple DWORD array but mask out upper 4 bits */ + break; #if FF_FS_EXFAT - case FS_EXFAT : - if ((obj->objsize != 0 && obj->sclust != 0) || obj->stat == 0) { /* Object except root dir must have valid data length */ - DWORD cofs = clst - obj->sclust; /* Offset from start cluster */ - DWORD clen = (DWORD)((LBA_t)((obj->objsize - 1) / SS(fs)) / fs->csize); /* Number of clusters - 1 */ + case FS_EXFAT : + if ((obj->objsize != 0 && obj->sclust != 0) + || obj->stat == 0) { /* Object except root dir must have valid data length */ + DWORD cofs = clst - obj->sclust; /* Offset from start cluster */ + DWORD clen = (DWORD)((LBA_t)((obj->objsize - 1) / SS(fs)) / fs->csize); /* Number of clusters - 1 */ - if (obj->stat == 2 && cofs <= clen) { /* Is it a contiguous chain? */ - val = (cofs == clen) ? 0x7FFFFFFF : clst + 1; /* No data on the FAT, generate the value */ - break; - } - if (obj->stat == 3 && cofs < obj->n_cont) { /* Is it in the 1st fragment? */ - val = clst + 1; /* Generate the value */ - break; - } - if (obj->stat != 2) { /* Get value from FAT if FAT chain is valid */ - if (obj->n_frag != 0) { /* Is it on the growing edge? */ - val = 0x7FFFFFFF; /* Generate EOC */ - } else { - if (move_window(fs, fs->fatbase + (clst / (SS(fs) / 4))) != FR_OK) break; - val = ld_dword(fs->win + clst * 4 % SS(fs)) & 0x7FFFFFFF; + if (obj->stat == 2 && cofs <= clen) { /* Is it a contiguous chain? */ + val = (cofs == clen) ? 0x7FFFFFFF : clst + 1; /* No data on the FAT, generate the value */ + break; + } + if (obj->stat == 3 && cofs < obj->n_cont) { /* Is it in the 1st fragment? */ + val = clst + 1; /* Generate the value */ + break; + } + if (obj->stat != 2) { /* Get value from FAT if FAT chain is valid */ + if (obj->n_frag != 0) { /* Is it on the growing edge? */ + val = 0x7FFFFFFF; /* Generate EOC */ + } + else { + if (move_window(fs, fs->fatbase + (clst / (SS(fs) / 4))) != FR_OK) { + break; + } + val = ld_dword(fs->win + clst * 4 % SS(fs)) & 0x7FFFFFFF; + } + break; } - break; } - } - val = 1; /* Internal error */ - break; + val = 1; /* Internal error */ + break; #endif - default: - val = 1; /* Internal error */ + default: + val = 1; /* Internal error */ } } @@ -1293,7 +1427,7 @@ static DWORD get_fat ( /* 0xFFFFFFFF:Disk error, 1:Internal error, 2..0x7FFFFFF /*-----------------------------------------------------------------------*/ static FRESULT put_fat ( /* FR_OK(0):succeeded, !=0:error */ - FATFS* fs, /* Corresponding filesystem object */ + FATFS *fs, /* Corresponding filesystem object */ DWORD clst, /* FAT index number (cluster number) to be changed */ DWORD val /* New value to be set to the entry */ ) @@ -1305,39 +1439,48 @@ static FRESULT put_fat ( /* FR_OK(0):succeeded, !=0:error */ if (clst >= 2 && clst < fs->n_fatent) { /* Check if in valid range */ switch (fs->fs_type) { - case FS_FAT12: - bc = (UINT)clst; bc += bc / 2; /* bc: byte offset of the entry */ - res = move_window(fs, fs->fatbase + (bc / SS(fs))); - if (res != FR_OK) break; - p = fs->win + bc++ % SS(fs); - *p = (clst & 1) ? ((*p & 0x0F) | ((BYTE)val << 4)) : (BYTE)val; /* Update 1st byte */ - fs->wflag = 1; - res = move_window(fs, fs->fatbase + (bc / SS(fs))); - if (res != FR_OK) break; - p = fs->win + bc % SS(fs); - *p = (clst & 1) ? (BYTE)(val >> 4) : ((*p & 0xF0) | ((BYTE)(val >> 8) & 0x0F)); /* Update 2nd byte */ - fs->wflag = 1; - break; + case FS_FAT12: + bc = (UINT)clst; + bc += bc / 2; /* bc: byte offset of the entry */ + res = move_window(fs, fs->fatbase + (bc / SS(fs))); + if (res != FR_OK) { + break; + } + p = fs->win + bc++ % SS(fs); + *p = (clst & 1) ? ((*p & 0x0F) | ((BYTE)val << 4)) : (BYTE)val; /* Update 1st byte */ + fs->wflag = 1; + res = move_window(fs, fs->fatbase + (bc / SS(fs))); + if (res != FR_OK) { + break; + } + p = fs->win + bc % SS(fs); + *p = (clst & 1) ? (BYTE)(val >> 4) : ((*p & 0xF0) | ((BYTE)(val >> 8) & 0x0F)); /* Update 2nd byte */ + fs->wflag = 1; + break; - case FS_FAT16: - res = move_window(fs, fs->fatbase + (clst / (SS(fs) / 2))); - if (res != FR_OK) break; - st_word(fs->win + clst * 2 % SS(fs), (WORD)val); /* Simple WORD array */ - fs->wflag = 1; - break; + case FS_FAT16: + res = move_window(fs, fs->fatbase + (clst / (SS(fs) / 2))); + if (res != FR_OK) { + break; + } + st_word(fs->win + clst * 2 % SS(fs), (WORD)val); /* Simple WORD array */ + fs->wflag = 1; + break; - case FS_FAT32: + case FS_FAT32: #if FF_FS_EXFAT - case FS_EXFAT: + case FS_EXFAT: #endif - res = move_window(fs, fs->fatbase + (clst / (SS(fs) / 4))); - if (res != FR_OK) break; - if (!FF_FS_EXFAT || fs->fs_type != FS_EXFAT) { - val = (val & 0x0FFFFFFF) | (ld_dword(fs->win + clst * 4 % SS(fs)) & 0xF0000000); - } - st_dword(fs->win + clst * 4 % SS(fs), val); - fs->wflag = 1; - break; + res = move_window(fs, fs->fatbase + (clst / (SS(fs) / 4))); + if (res != FR_OK) { + break; + } + if (!FF_FS_EXFAT || fs->fs_type != FS_EXFAT) { + val = (val & 0x0FFFFFFF) | (ld_dword(fs->win + clst * 4 % SS(fs)) & 0xF0000000); + } + st_dword(fs->win + clst * 4 % SS(fs), val); + fs->wflag = 1; + break; } } return res; @@ -1358,7 +1501,7 @@ static FRESULT put_fat ( /* FR_OK(0):succeeded, !=0:error */ /*--------------------------------------*/ static DWORD find_bitmap ( /* 0:Not found, 2..:Cluster block found, 0xFFFFFFFF:Disk error */ - FATFS* fs, /* Filesystem object */ + FATFS *fs, /* Filesystem object */ DWORD clst, /* Cluster number to scan from */ DWORD ncl /* Number of contiguous clusters to find (1..) */ ) @@ -1369,26 +1512,43 @@ static DWORD find_bitmap ( /* 0:Not found, 2..:Cluster block found, 0xFFFFFFFF:D clst -= 2; /* The first bit in the bitmap corresponds to cluster #2 */ - if (clst >= fs->n_fatent - 2) clst = 0; - scl = val = clst; ctr = 0; + if (clst >= fs->n_fatent - 2) { + clst = 0; + } + scl = val = clst; + ctr = 0; for (;;) { - if (move_window(fs, fs->bitbase + val / 8 / SS(fs)) != FR_OK) return 0xFFFFFFFF; - i = val / 8 % SS(fs); bm = 1 << (val % 8); + if (move_window(fs, fs->bitbase + val / 8 / SS(fs)) != FR_OK) { + return 0xFFFFFFFF; + } + i = val / 8 % SS(fs); + bm = 1 << (val % 8); do { do { - bv = fs->win[i] & bm; bm <<= 1; /* Get bit value */ + bv = fs->win[i] & bm; + bm <<= 1; /* Get bit value */ if (++val >= fs->n_fatent - 2) { /* Next cluster (with wrap-around) */ - val = 0; bm = 0; i = SS(fs); + val = 0; + bm = 0; + i = SS(fs); } if (bv == 0) { /* Is it a free cluster? */ - if (++ctr == ncl) return scl + 2; /* Check if run length is sufficient for required */ - } else { - scl = val; ctr = 0; /* Encountered a cluster in-use, restart to scan */ + if (++ctr == ncl) { + return scl + 2; /* Check if run length is sufficient for required */ + } } - if (val == clst) return 0; /* All cluster scanned? */ - } while (bm != 0); + else { + scl = val; + ctr = 0; /* Encountered a cluster in-use, restart to scan */ + } + if (val == clst) { + return 0; /* All cluster scanned? */ + } + } + while (bm != 0); bm = 1; - } while (++i < SS(fs)); + } + while (++i < SS(fs)); } } @@ -1398,7 +1558,7 @@ static DWORD find_bitmap ( /* 0:Not found, 2..:Cluster block found, 0xFFFFFFFF:D /*----------------------------------------*/ static FRESULT change_bitmap ( - FATFS* fs, /* Filesystem object */ + FATFS *fs, /* Filesystem object */ DWORD clst, /* Cluster number to change from */ DWORD ncl, /* Number of clusters to be changed */ int bv /* bit value to be set (0 or 1) */ @@ -1414,16 +1574,24 @@ static FRESULT change_bitmap ( i = clst / 8 % SS(fs); /* Byte offset in the sector */ bm = 1 << (clst % 8); /* Bit mask in the byte */ for (;;) { - if (move_window(fs, sect++) != FR_OK) return FR_DISK_ERR; + if (move_window(fs, sect++) != FR_OK) { + return FR_DISK_ERR; + } do { do { - if (bv == (int)((fs->win[i] & bm) != 0)) return FR_INT_ERR; /* Is the bit expected value? */ + if (bv == (int)((fs->win[i] & bm) != 0)) { + return FR_INT_ERR; /* Is the bit expected value? */ + } fs->win[i] ^= bm; /* Flip the bit */ fs->wflag = 1; - if (--ncl == 0) return FR_OK; /* All bits processed? */ - } while (bm <<= 1); /* Next bit */ + if (--ncl == 0) { + return FR_OK; /* All bits processed? */ + } + } + while (bm <<= 1); /* Next bit */ bm = 1; - } while (++i < SS(fs)); /* Next byte */ + } + while (++i < SS(fs)); /* Next byte */ i = 0; } } @@ -1434,7 +1602,7 @@ static FRESULT change_bitmap ( /*---------------------------------------------*/ static FRESULT fill_first_frag ( - FFOBJID* obj /* Pointer to the corresponding object */ + FFOBJID *obj /* Pointer to the corresponding object */ ) { FRESULT res = FR_DISK_ERR; @@ -1444,7 +1612,9 @@ static FRESULT fill_first_frag ( if (obj->stat == 3) { /* Has the object been changed 'fragmented' in this session? */ for (cl = obj->sclust, n = obj->n_cont; n; cl++, n--) { /* Create cluster chain on the FAT */ res = put_fat(obj->fs, cl, cl + 1); - if (res != FR_OK) return res; + if (res != FR_OK) { + return res; + } } obj->stat = 0; /* Change status 'FAT chain is valid' */ } @@ -1457,7 +1627,7 @@ static FRESULT fill_first_frag ( /*---------------------------------------------*/ static FRESULT fill_last_frag ( - FFOBJID* obj, /* Pointer to the corresponding object */ + FFOBJID *obj, /* Pointer to the corresponding object */ DWORD lcl, /* Last cluster of the fragment */ DWORD term /* Value to set the last FAT entry */ ) @@ -1467,7 +1637,9 @@ static FRESULT fill_last_frag ( while (obj->n_frag > 0) { /* Create the chain of last fragment */ res = put_fat(obj->fs, lcl - obj->n_frag + 1, (obj->n_frag > 1) ? lcl - obj->n_frag + 2 : term); - if (res != FR_OK) return res; + if (res != FR_OK) { + return res; + } obj->n_frag--; } return FR_OK; @@ -1483,7 +1655,7 @@ static FRESULT fill_last_frag ( /*-----------------------------------------------------------------------*/ static FRESULT remove_chain ( /* FR_OK(0):succeeded, !=0:error */ - FFOBJID* obj, /* Corresponding object */ + FFOBJID *obj, /* Corresponding object */ DWORD clst, /* Cluster to remove a chain from */ DWORD pclst /* Previous cluster of clst (0 if entire chain) */ ) @@ -1498,23 +1670,35 @@ static FRESULT remove_chain ( /* FR_OK(0):succeeded, !=0:error */ LBA_t rt[2]; #endif - if (clst < 2 || clst >= fs->n_fatent) return FR_INT_ERR; /* Check if in valid range */ + if (clst < 2 || clst >= fs->n_fatent) { + return FR_INT_ERR; /* Check if in valid range */ + } /* Mark the previous cluster 'EOC' on the FAT if it exists */ if (pclst != 0 && (!FF_FS_EXFAT || fs->fs_type != FS_EXFAT || obj->stat != 2)) { res = put_fat(fs, pclst, 0xFFFFFFFF); - if (res != FR_OK) return res; + if (res != FR_OK) { + return res; + } } /* Remove the chain */ do { nxt = get_fat(obj, clst); /* Get cluster status */ - if (nxt == 0) break; /* Empty cluster? */ - if (nxt == 1) return FR_INT_ERR; /* Internal error? */ - if (nxt == 0xFFFFFFFF) return FR_DISK_ERR; /* Disk error? */ + if (nxt == 0) { + break; /* Empty cluster? */ + } + if (nxt == 1) { + return FR_INT_ERR; /* Internal error? */ + } + if (nxt == 0xFFFFFFFF) { + return FR_DISK_ERR; /* Disk error? */ + } if (!FF_FS_EXFAT || fs->fs_type != FS_EXFAT) { res = put_fat(fs, clst, 0); /* Mark the cluster 'free' on the FAT */ - if (res != FR_OK) return res; + if (res != FR_OK) { + return res; + } } if (fs->free_clst < fs->n_fatent - 2) { /* Update FSINFO */ fs->free_clst++; @@ -1523,11 +1707,14 @@ static FRESULT remove_chain ( /* FR_OK(0):succeeded, !=0:error */ #if FF_FS_EXFAT || FF_USE_TRIM if (ecl + 1 == nxt) { /* Is next cluster contiguous? */ ecl = nxt; - } else { /* End of contiguous cluster block */ + } + else { /* End of contiguous cluster block */ #if FF_FS_EXFAT if (fs->fs_type == FS_EXFAT) { res = change_bitmap(fs, scl, ecl - scl + 1, 0); /* Mark the cluster block 'free' on the bitmap */ - if (res != FR_OK) return res; + if (res != FR_OK) { + return res; + } } #endif #if FF_USE_TRIM @@ -1539,28 +1726,38 @@ static FRESULT remove_chain ( /* FR_OK(0):succeeded, !=0:error */ } #endif clst = nxt; /* Next cluster */ - } while (clst < fs->n_fatent); /* Repeat while not the last link */ + } + while (clst < fs->n_fatent); /* Repeat while not the last link */ #if FF_FS_EXFAT /* Some post processes for chain status */ if (fs->fs_type == FS_EXFAT) { if (pclst == 0) { /* Has the entire chain been removed? */ obj->stat = 0; /* Change the chain status 'initial' */ - } else { + } + else { if (obj->stat == 0) { /* Is it a fragmented chain from the beginning of this session? */ clst = obj->sclust; /* Follow the chain to check if it gets contiguous */ while (clst != pclst) { nxt = get_fat(obj, clst); - if (nxt < 2) return FR_INT_ERR; - if (nxt == 0xFFFFFFFF) return FR_DISK_ERR; - if (nxt != clst + 1) break; /* Not contiguous? */ + if (nxt < 2) { + return FR_INT_ERR; + } + if (nxt == 0xFFFFFFFF) { + return FR_DISK_ERR; + } + if (nxt != clst + 1) { + break; /* Not contiguous? */ + } clst++; } if (clst == pclst) { /* Has the chain got contiguous again? */ obj->stat = 2; /* Change the chain status 'contiguous' */ } - } else { - if (obj->stat == 3 && pclst >= obj->sclust && pclst <= obj->sclust + obj->n_cont) { /* Was the chain fragmented in this session and got contiguous again? */ + } + else { + if (obj->stat == 3 && pclst >= obj->sclust + && pclst <= obj->sclust + obj->n_cont) { /* Was the chain fragmented in this session and got contiguous again? */ obj->stat = 2; /* Change the chain status 'contiguous' */ } } @@ -1578,7 +1775,7 @@ static FRESULT remove_chain ( /* FR_OK(0):succeeded, !=0:error */ /*-----------------------------------------------------------------------*/ static DWORD create_chain ( /* 0:No free cluster, 1:Internal error, 0xFFFFFFFF:Disk error, >=2:New cluster# */ - FFOBJID* obj, /* Corresponding object */ + FFOBJID *obj, /* Corresponding object */ DWORD clst /* Cluster# to stretch, 0:Create a new chain */ ) { @@ -1589,27 +1786,44 @@ static DWORD create_chain ( /* 0:No free cluster, 1:Internal error, 0xFFFFFFFF:D if (clst == 0) { /* Create a new chain */ scl = fs->last_clst; /* Suggested cluster to start to find */ - if (scl == 0 || scl >= fs->n_fatent) scl = 1; + if (scl == 0 || scl >= fs->n_fatent) { + scl = 1; + } } else { /* Stretch a chain */ cs = get_fat(obj, clst); /* Check the cluster status */ - if (cs < 2) return 1; /* Test for insanity */ - if (cs == 0xFFFFFFFF) return cs; /* Test for disk error */ - if (cs < fs->n_fatent) return cs; /* It is already followed by next cluster */ + if (cs < 2) { + return 1; /* Test for insanity */ + } + if (cs == 0xFFFFFFFF) { + return cs; /* Test for disk error */ + } + if (cs < fs->n_fatent) { + return cs; /* It is already followed by next cluster */ + } scl = clst; /* Cluster to start to find */ } - if (fs->free_clst == 0) return 0; /* No free cluster */ + if (fs->free_clst == 0) { + return 0; /* No free cluster */ + } #if FF_FS_EXFAT if (fs->fs_type == FS_EXFAT) { /* On the exFAT volume */ ncl = find_bitmap(fs, scl, 1); /* Find a free cluster */ - if (ncl == 0 || ncl == 0xFFFFFFFF) return ncl; /* No free cluster or hard error? */ + if (ncl == 0 || ncl == 0xFFFFFFFF) { + return ncl; /* No free cluster or hard error? */ + } res = change_bitmap(fs, ncl, 1, 1); /* Mark the cluster 'in use' */ - if (res == FR_INT_ERR) return 1; - if (res == FR_DISK_ERR) return 0xFFFFFFFF; + if (res == FR_INT_ERR) { + return 1; + } + if (res == FR_DISK_ERR) { + return 0xFFFFFFFF; + } if (clst == 0) { /* Is it a new chain? */ obj->stat = 2; /* Set status 'contiguous' */ - } else { /* It is a stretched chain */ + } + else { /* It is a stretched chain */ if (obj->stat == 2 && ncl != scl + 1) { /* Is the chain got fragmented? */ obj->n_cont = scl - obj->sclust; /* Set size of the contiguous part */ obj->stat = 3; /* Change status 'just fragmented' */ @@ -1618,24 +1832,36 @@ static DWORD create_chain ( /* 0:No free cluster, 1:Internal error, 0xFFFFFFFF:D if (obj->stat != 2) { /* Is the file non-contiguous? */ if (ncl == clst + 1) { /* Is the cluster next to previous one? */ obj->n_frag = obj->n_frag ? obj->n_frag + 1 : 2; /* Increment size of last framgent */ - } else { /* New fragment */ - if (obj->n_frag == 0) obj->n_frag = 1; + } + else { /* New fragment */ + if (obj->n_frag == 0) { + obj->n_frag = 1; + } res = fill_last_frag(obj, clst, ncl); /* Fill last fragment on the FAT and link it to new one */ - if (res == FR_OK) obj->n_frag = 1; + if (res == FR_OK) { + obj->n_frag = 1; + } } } - } else + } + else #endif { /* On the FAT/FAT32 volume */ ncl = 0; if (scl == clst) { /* Stretching an existing chain? */ ncl = scl + 1; /* Test if next cluster is free */ - if (ncl >= fs->n_fatent) ncl = 2; + if (ncl >= fs->n_fatent) { + ncl = 2; + } cs = get_fat(obj, ncl); /* Get next cluster status */ - if (cs == 1 || cs == 0xFFFFFFFF) return cs; /* Test for error */ + if (cs == 1 || cs == 0xFFFFFFFF) { + return cs; /* Test for error */ + } if (cs != 0) { /* Not free? */ cs = fs->last_clst; /* Start at suggested cluster if it is valid */ - if (cs >= 2 && cs < fs->n_fatent) scl = cs; + if (cs >= 2 && cs < fs->n_fatent) { + scl = cs; + } ncl = 0; } } @@ -1645,12 +1871,20 @@ static DWORD create_chain ( /* 0:No free cluster, 1:Internal error, 0xFFFFFFFF:D ncl++; /* Next cluster */ if (ncl >= fs->n_fatent) { /* Check wrap-around */ ncl = 2; - if (ncl > scl) return 0; /* No free cluster found? */ + if (ncl > scl) { + return 0; /* No free cluster found? */ + } } cs = get_fat(obj, ncl); /* Get the cluster status */ - if (cs == 0) break; /* Found a free cluster? */ - if (cs == 1 || cs == 0xFFFFFFFF) return cs; /* Test for error */ - if (ncl == scl) return 0; /* No free cluster found? */ + if (cs == 0) { + break; /* Found a free cluster? */ + } + if (cs == 1 || cs == 0xFFFFFFFF) { + return cs; /* Test for error */ + } + if (ncl == scl) { + return 0; /* No free cluster found? */ + } } } res = put_fat(fs, ncl, 0xFFFFFFFF); /* Mark the new cluster 'EOC' */ @@ -1661,9 +1895,12 @@ static DWORD create_chain ( /* 0:No free cluster, 1:Internal error, 0xFFFFFFFF:D if (res == FR_OK) { /* Update FSINFO if function succeeded. */ fs->last_clst = ncl; - if (fs->free_clst <= fs->n_fatent - 2) fs->free_clst--; + if (fs->free_clst <= fs->n_fatent - 2) { + fs->free_clst--; + } fs->fsi_flag |= 1; - } else { + } + else { ncl = (res == FR_DISK_ERR) ? 0xFFFFFFFF : 1; /* Failed. Generate error status */ } @@ -1681,7 +1918,7 @@ static DWORD create_chain ( /* 0:No free cluster, 1:Internal error, 0xFFFFFFFF:D /*-----------------------------------------------------------------------*/ static DWORD clmt_clust ( /* <2:Error, >=2:Cluster number */ - FIL* fp, /* Pointer to the file object */ + FIL *fp, /* Pointer to the file object */ FSIZE_t ofs /* File offset to be converted to cluster# */ ) { @@ -1694,9 +1931,14 @@ static DWORD clmt_clust ( /* <2:Error, >=2:Cluster number */ cl = (DWORD)(ofs / SS(fs) / fs->csize); /* Cluster order from top of the file */ for (;;) { ncl = *tbl++; /* Number of cluters in the fragment */ - if (ncl == 0) return 0; /* End of table? (error) */ - if (cl < ncl) break; /* In this fragment? */ - cl -= ncl; tbl++; /* Next fragment */ + if (ncl == 0) { + return 0; /* End of table? (error) */ + } + if (cl < ncl) { + break; /* In this fragment? */ + } + cl -= ncl; + tbl++; /* Next fragment */ } return cl + *tbl; /* Return the cluster number */ } @@ -1721,23 +1963,30 @@ static FRESULT dir_clear ( /* Returns FR_OK or FR_DISK_ERR */ BYTE *ibuf; - if (sync_window(fs) != FR_OK) return FR_DISK_ERR; /* Flush disk access window */ + if (sync_window(fs) != FR_OK) { + return FR_DISK_ERR; /* Flush disk access window */ + } sect = clst2sect(fs, clst); /* Top of the cluster */ fs->winsect = sect; /* Set window to top of the cluster */ memset(fs->win, 0, sizeof fs->win); /* Clear window buffer */ #if FF_USE_LFN == 3 /* Quick table clear by using multi-secter write */ /* Allocate a temporary buffer */ - for (szb = ((DWORD)fs->csize * SS(fs) >= MAX_MALLOC) ? MAX_MALLOC : fs->csize * SS(fs), ibuf = 0; szb > SS(fs) && (ibuf = ff_memalloc(szb)) == 0; szb /= 2) ; + for (szb = ((DWORD)fs->csize * SS(fs) >= MAX_MALLOC) ? MAX_MALLOC : fs->csize * SS(fs), ibuf = 0; szb > SS(fs) + && (ibuf = ff_memalloc(szb)) == 0; szb /= 2) ; if (szb > SS(fs)) { /* Buffer allocated? */ memset(ibuf, 0, szb); szb /= SS(fs); /* Bytes -> Sectors */ - for (n = 0; n < fs->csize && disk_write(fs->pdrv, ibuf, sect + n, szb) == RES_OK; n += szb) ; /* Fill the cluster with 0 */ + for (n = 0; n < fs->csize + && disk_write(fs->pdrv, ibuf, sect + n, szb) == RES_OK; n += szb) ; /* Fill the cluster with 0 */ ff_memfree(ibuf); - } else + } + else #endif { - ibuf = fs->win; szb = 1; /* Use window buffer (many single-sector writes may take a time) */ - for (n = 0; n < fs->csize && disk_write(fs->pdrv, ibuf, sect + n, szb) == RES_OK; n += szb) ; /* Fill the cluster with 0 */ + ibuf = fs->win; + szb = 1; /* Use window buffer (many single-sector writes may take a time) */ + for (n = 0; n < fs->csize + && disk_write(fs->pdrv, ibuf, sect + n, szb) == RES_OK; n += szb) ; /* Fill the cluster with 0 */ } return (n == fs->csize) ? FR_OK : FR_DISK_ERR; } @@ -1751,7 +2000,7 @@ static FRESULT dir_clear ( /* Returns FR_OK or FR_DISK_ERR */ /*-----------------------------------------------------------------------*/ static FRESULT dir_sdi ( /* FR_OK(0):succeeded, !=0:error */ - DIR* dp, /* Pointer to directory object */ + DIR *dp, /* Pointer to directory object */ DWORD ofs /* Offset of directory table */ ) { @@ -1759,32 +2008,44 @@ static FRESULT dir_sdi ( /* FR_OK(0):succeeded, !=0:error */ FATFS *fs = dp->obj.fs; - if (ofs >= (DWORD)((FF_FS_EXFAT && fs->fs_type == FS_EXFAT) ? MAX_DIR_EX : MAX_DIR) || ofs % SZDIRE) { /* Check range of offset and alignment */ + if (ofs >= (DWORD)((FF_FS_EXFAT && fs->fs_type == FS_EXFAT) ? MAX_DIR_EX : MAX_DIR) + || ofs % SZDIRE) { /* Check range of offset and alignment */ return FR_INT_ERR; } dp->dptr = ofs; /* Set current offset */ clst = dp->obj.sclust; /* Table start cluster (0:root) */ if (clst == 0 && fs->fs_type >= FS_FAT32) { /* Replace cluster# 0 with root cluster# */ clst = (DWORD)fs->dirbase; - if (FF_FS_EXFAT) dp->obj.stat = 0; /* exFAT: Root dir has an FAT chain */ + if (FF_FS_EXFAT) { + dp->obj.stat = 0; /* exFAT: Root dir has an FAT chain */ + } } if (clst == 0) { /* Static table (root-directory on the FAT volume) */ - if (ofs / SZDIRE >= fs->n_rootdir) return FR_INT_ERR; /* Is index out of range? */ + if (ofs / SZDIRE >= fs->n_rootdir) { + return FR_INT_ERR; /* Is index out of range? */ + } dp->sect = fs->dirbase; - } else { /* Dynamic table (sub-directory or root-directory on the FAT32/exFAT volume) */ + } + else { /* Dynamic table (sub-directory or root-directory on the FAT32/exFAT volume) */ csz = (DWORD)fs->csize * SS(fs); /* Bytes per cluster */ while (ofs >= csz) { /* Follow cluster chain */ clst = get_fat(&dp->obj, clst); /* Get next cluster */ - if (clst == 0xFFFFFFFF) return FR_DISK_ERR; /* Disk error */ - if (clst < 2 || clst >= fs->n_fatent) return FR_INT_ERR; /* Reached to end of table or internal error */ + if (clst == 0xFFFFFFFF) { + return FR_DISK_ERR; /* Disk error */ + } + if (clst < 2 || clst >= fs->n_fatent) { + return FR_INT_ERR; /* Reached to end of table or internal error */ + } ofs -= csz; } dp->sect = clst2sect(fs, clst); } dp->clust = clst; /* Current cluster# */ - if (dp->sect == 0) return FR_INT_ERR; + if (dp->sect == 0) { + return FR_INT_ERR; + } dp->sect += ofs / SS(fs); /* Sector# of the directory entry */ dp->dir = fs->win + (ofs % SS(fs)); /* Pointer to the entry in the win[] */ @@ -1799,7 +2060,7 @@ static FRESULT dir_sdi ( /* FR_OK(0):succeeded, !=0:error */ /*-----------------------------------------------------------------------*/ static FRESULT dir_next ( /* FR_OK(0):succeeded, FR_NO_FILE:End of table, FR_DENIED:Could not stretch */ - DIR* dp, /* Pointer to the directory object */ + DIR *dp, /* Pointer to the directory object */ int stretch /* 0: Do not stretch table, 1: Stretch table if needed */ ) { @@ -1808,36 +2069,59 @@ static FRESULT dir_next ( /* FR_OK(0):succeeded, FR_NO_FILE:End of table, FR_DEN ofs = dp->dptr + SZDIRE; /* Next entry */ - if (ofs >= (DWORD)((FF_FS_EXFAT && fs->fs_type == FS_EXFAT) ? MAX_DIR_EX : MAX_DIR)) dp->sect = 0; /* Disable it if the offset reached the max value */ - if (dp->sect == 0) return FR_NO_FILE; /* Report EOT if it has been disabled */ + if (ofs >= (DWORD)((FF_FS_EXFAT && fs->fs_type == FS_EXFAT) ? MAX_DIR_EX : MAX_DIR)) { + dp->sect = 0; /* Disable it if the offset reached the max value */ + } + if (dp->sect == 0) { + return FR_NO_FILE; /* Report EOT if it has been disabled */ + } if (ofs % SS(fs) == 0) { /* Sector changed? */ dp->sect++; /* Next sector */ if (dp->clust == 0) { /* Static table */ if (ofs / SZDIRE >= fs->n_rootdir) { /* Report EOT if it reached end of static table */ - dp->sect = 0; return FR_NO_FILE; + dp->sect = 0; + return FR_NO_FILE; } } else { /* Dynamic table */ if ((ofs / SS(fs) & (fs->csize - 1)) == 0) { /* Cluster changed? */ clst = get_fat(&dp->obj, dp->clust); /* Get next cluster */ - if (clst <= 1) return FR_INT_ERR; /* Internal error */ - if (clst == 0xFFFFFFFF) return FR_DISK_ERR; /* Disk error */ + if (clst <= 1) { + return FR_INT_ERR; /* Internal error */ + } + if (clst == 0xFFFFFFFF) { + return FR_DISK_ERR; /* Disk error */ + } if (clst >= fs->n_fatent) { /* It reached end of dynamic table */ #if !FF_FS_READONLY if (!stretch) { /* If no stretch, report EOT */ - dp->sect = 0; return FR_NO_FILE; + dp->sect = 0; + return FR_NO_FILE; } clst = create_chain(&dp->obj, dp->clust); /* Allocate a cluster */ - if (clst == 0) return FR_DENIED; /* No free cluster */ - if (clst == 1) return FR_INT_ERR; /* Internal error */ - if (clst == 0xFFFFFFFF) return FR_DISK_ERR; /* Disk error */ - if (dir_clear(fs, clst) != FR_OK) return FR_DISK_ERR; /* Clean up the stretched table */ - if (FF_FS_EXFAT) dp->obj.stat |= 4; /* exFAT: The directory has been stretched */ + if (clst == 0) { + return FR_DENIED; /* No free cluster */ + } + if (clst == 1) { + return FR_INT_ERR; /* Internal error */ + } + if (clst == 0xFFFFFFFF) { + return FR_DISK_ERR; /* Disk error */ + } + if (dir_clear(fs, clst) != FR_OK) { + return FR_DISK_ERR; /* Clean up the stretched table */ + } + if (FF_FS_EXFAT) { + dp->obj.stat |= 4; /* exFAT: The directory has been stretched */ + } #else - if (!stretch) dp->sect = 0; /* (this line is to suppress compiler warning) */ - dp->sect = 0; return FR_NO_FILE; /* Report EOT */ + if (!stretch) { + dp->sect = 0; /* (this line is to suppress compiler warning) */ + } + dp->sect = 0; + return FR_NO_FILE; /* Report EOT */ #endif } dp->clust = clst; /* Initialize data for new cluster */ @@ -1860,7 +2144,7 @@ static FRESULT dir_next ( /* FR_OK(0):succeeded, FR_NO_FILE:End of table, FR_DEN /*-----------------------------------------------------------------------*/ static FRESULT dir_alloc ( /* FR_OK(0):succeeded, !=0:error */ - DIR* dp, /* Pointer to the directory object */ + DIR *dp, /* Pointer to the directory object */ UINT n_ent /* Number of contiguous entries to allocate */ ) { @@ -1874,21 +2158,30 @@ static FRESULT dir_alloc ( /* FR_OK(0):succeeded, !=0:error */ n = 0; do { res = move_window(fs, dp->sect); - if (res != FR_OK) break; + if (res != FR_OK) { + break; + } #if FF_FS_EXFAT - if ((fs->fs_type == FS_EXFAT) ? (int)((dp->dir[XDIR_Type] & 0x80) == 0) : (int)(dp->dir[DIR_Name] == DDEM || dp->dir[DIR_Name] == 0)) { /* Is the entry free? */ + if ((fs->fs_type == FS_EXFAT) ? (int)((dp->dir[XDIR_Type] & 0x80) == 0) : (int)(dp->dir[DIR_Name] == DDEM + || dp->dir[DIR_Name] == 0)) { /* Is the entry free? */ #else if (dp->dir[DIR_Name] == DDEM || dp->dir[DIR_Name] == 0) { /* Is the entry free? */ #endif - if (++n == n_ent) break; /* Is a block of contiguous free entries found? */ - } else { + if (++n == n_ent) { + break; /* Is a block of contiguous free entries found? */ + } + } + else { n = 0; /* Not a free entry, restart to search */ } res = dir_next(dp, 1); /* Next entry with table stretch enabled */ - } while (res == FR_OK); + } + while (res == FR_OK); } - if (res == FR_NO_FILE) res = FR_DENIED; /* No directory entry to allocate */ + if (res == FR_NO_FILE) { + res = FR_DENIED; /* No directory entry to allocate */ + } return res; } @@ -1902,8 +2195,8 @@ static FRESULT dir_alloc ( /* FR_OK(0):succeeded, !=0:error */ /*-----------------------------------------------------------------------*/ static DWORD ld_clust ( /* Returns the top cluster value of the SFN entry */ - FATFS* fs, /* Pointer to the fs object */ - const BYTE* dir /* Pointer to the key entry */ + FATFS *fs, /* Pointer to the fs object */ + const BYTE *dir /* Pointer to the key entry */ ) { DWORD cl; @@ -1919,8 +2212,8 @@ static DWORD ld_clust ( /* Returns the top cluster value of the SFN entry */ #if !FF_FS_READONLY static void st_clust ( - FATFS* fs, /* Pointer to the fs object */ - BYTE* dir, /* Pointer to the key entry */ + FATFS *fs, /* Pointer to the fs object */ + BYTE *dir, /* Pointer to the key entry */ DWORD cl /* Value to be set */ ) { @@ -1939,15 +2232,17 @@ static void st_clust ( /*--------------------------------------------------------*/ static int cmp_lfn ( /* 1:matched, 0:not matched */ - const WCHAR* lfnbuf, /* Pointer to the LFN working buffer to be compared */ - BYTE* dir /* Pointer to the directory entry containing the part of LFN */ + const WCHAR *lfnbuf, /* Pointer to the LFN working buffer to be compared */ + BYTE *dir /* Pointer to the directory entry containing the part of LFN */ ) { UINT i, s; WCHAR wc, uc; - if (ld_word(dir + LDIR_FstClusLO) != 0) return 0; /* Check LDIR_FstClusLO */ + if (ld_word(dir + LDIR_FstClusLO) != 0) { + return 0; /* Check LDIR_FstClusLO */ + } i = ((dir[LDIR_Ord] & 0x3F) - 1) * 13; /* Offset in the LFN buffer */ @@ -1958,12 +2253,17 @@ static int cmp_lfn ( /* 1:matched, 0:not matched */ return 0; /* Not matched */ } wc = uc; - } else { - if (uc != 0xFFFF) return 0; /* Check filler */ + } + else { + if (uc != 0xFFFF) { + return 0; /* Check filler */ + } } } - if ((dir[LDIR_Ord] & LLEF) && wc && lfnbuf[i]) return 0; /* Last segment matched but different length */ + if ((dir[LDIR_Ord] & LLEF) && wc && lfnbuf[i]) { + return 0; /* Last segment matched but different length */ + } return 1; /* The part of LFN matched */ } @@ -1975,30 +2275,39 @@ static int cmp_lfn ( /* 1:matched, 0:not matched */ /*-----------------------------------------------------*/ static int pick_lfn ( /* 1:succeeded, 0:buffer overflow or invalid LFN entry */ - WCHAR* lfnbuf, /* Pointer to the LFN working buffer */ - BYTE* dir /* Pointer to the LFN entry */ + WCHAR *lfnbuf, /* Pointer to the LFN working buffer */ + BYTE *dir /* Pointer to the LFN entry */ ) { UINT i, s; WCHAR wc, uc; - if (ld_word(dir + LDIR_FstClusLO) != 0) return 0; /* Check LDIR_FstClusLO is 0 */ + if (ld_word(dir + LDIR_FstClusLO) != 0) { + return 0; /* Check LDIR_FstClusLO is 0 */ + } i = ((dir[LDIR_Ord] & ~LLEF) - 1) * 13; /* Offset in the LFN buffer */ for (wc = 1, s = 0; s < 13; s++) { /* Process all characters in the entry */ uc = ld_word(dir + LfnOfs[s]); /* Pick an LFN character */ if (wc != 0) { - if (i >= FF_MAX_LFN + 1) return 0; /* Buffer overflow? */ + if (i >= FF_MAX_LFN + 1) { + return 0; /* Buffer overflow? */ + } lfnbuf[i++] = wc = uc; /* Store it */ - } else { - if (uc != 0xFFFF) return 0; /* Check filler */ + } + else { + if (uc != 0xFFFF) { + return 0; /* Check filler */ + } } } if (dir[LDIR_Ord] & LLEF && wc != 0) { /* Put terminator if it is the last LFN part and not terminated */ - if (i >= FF_MAX_LFN + 1) return 0; /* Buffer overflow? */ + if (i >= FF_MAX_LFN + 1) { + return 0; /* Buffer overflow? */ + } lfnbuf[i] = 0; } @@ -2013,8 +2322,8 @@ static int pick_lfn ( /* 1:succeeded, 0:buffer overflow or invalid LFN entry */ /*-----------------------------------------*/ static void put_lfn ( - const WCHAR* lfn, /* Pointer to the LFN */ - BYTE* dir, /* Pointer to the LFN entry to be created */ + const WCHAR *lfn, /* Pointer to the LFN */ + BYTE *dir, /* Pointer to the LFN entry to be created */ BYTE ord, /* LFN order (1-20) */ BYTE sum /* Checksum of the corresponding SFN */ ) @@ -2031,11 +2340,18 @@ static void put_lfn ( i = (ord - 1) * 13; /* Get offset in the LFN working buffer */ s = wc = 0; do { - if (wc != 0xFFFF) wc = lfn[i++]; /* Get an effective character */ + if (wc != 0xFFFF) { + wc = lfn[i++]; /* Get an effective character */ + } st_word(dir + LfnOfs[s], wc); /* Put it */ - if (wc == 0) wc = 0xFFFF; /* Padding characters for following items */ - } while (++s < 13); - if (wc == 0xFFFF || !lfn[i]) ord |= LLEF; /* Last LFN part is the start of LFN sequence */ + if (wc == 0) { + wc = 0xFFFF; /* Padding characters for following items */ + } + } + while (++s < 13); + if (wc == 0xFFFF || !lfn[i]) { + ord |= LLEF; /* Last LFN part is the start of LFN sequence */ + } dir[LDIR_Ord] = ord; /* Set the LFN order */ } @@ -2050,9 +2366,9 @@ static void put_lfn ( /*-----------------------------------------------------------------------*/ static void gen_numname ( - BYTE* dst, /* Pointer to the buffer to store numbered SFN */ - const BYTE* src, /* Pointer to SFN in directory form */ - const WCHAR* lfn, /* Pointer to LFN */ + BYTE *dst, /* Pointer to the buffer to store numbered SFN */ + const BYTE *src, /* Pointer to SFN in directory form */ + const WCHAR *lfn, /* Pointer to LFN */ UINT seq /* Sequence number */ ) { @@ -2071,7 +2387,9 @@ static void gen_numname ( for (i = 0; i < 16; i++) { sreg = (sreg << 1) + (wc & 1); wc >>= 1; - if (sreg & 0x10000) sreg ^= 0x11021; + if (sreg & 0x10000) { + sreg ^= 0x11021; + } } } seq = (UINT)sreg; @@ -2080,22 +2398,29 @@ static void gen_numname ( /* Make suffix (~ + hexadecimal) */ i = 7; do { - c = (BYTE)((seq % 16) + '0'); seq /= 16; - if (c > '9') c += 7; + c = (BYTE)((seq % 16) + '0'); + seq /= 16; + if (c > '9') { + c += 7; + } ns[i--] = c; - } while (i && seq); + } + while (i && seq); ns[i] = '~'; /* Append the suffix to the SFN body */ for (j = 0; j < i && dst[j] != ' '; j++) { /* Find the offset to append */ if (dbc_1st(dst[j])) { /* To avoid DBC break up */ - if (j == i - 1) break; + if (j == i - 1) { + break; + } j++; } } do { /* Append the suffix */ dst[j++] = (i < 8) ? ns[i++] : ' '; - } while (j < 8); + } + while (j < 8); } #endif /* FF_USE_LFN && !FF_FS_READONLY */ @@ -2107,7 +2432,7 @@ static void gen_numname ( /*-----------------------------------------------------------------------*/ static BYTE sum_sfn ( - const BYTE* dir /* Pointer to the SFN entry */ + const BYTE *dir /* Pointer to the SFN entry */ ) { BYTE sum = 0; @@ -2115,7 +2440,8 @@ static BYTE sum_sfn ( do { sum = (sum >> 1) + (sum << 7) + *dir++; - } while (--n); + } + while (--n); return sum; } @@ -2129,7 +2455,7 @@ static BYTE sum_sfn ( /*-----------------------------------------------------------------------*/ static WORD xdir_sum ( /* Get checksum of the directoly entry block */ - const BYTE* dir /* Directory entry block to be calculated */ + const BYTE *dir /* Directory entry block to be calculated */ ) { UINT i, szblk; @@ -2140,7 +2466,8 @@ static WORD xdir_sum ( /* Get checksum of the directoly entry block */ for (i = sum = 0; i < szblk; i++) { if (i == XDIR_SetSum) { /* Skip 2-byte sum field */ i++; - } else { + } + else { sum = ((sum & 1) ? 0x8000 : 0) + (sum >> 1) + dir[i]; } } @@ -2150,7 +2477,7 @@ static WORD xdir_sum ( /* Get checksum of the directoly entry block */ static WORD xname_sum ( /* Get check sum (to be used as hash) of the file name */ - const WCHAR* name /* File name to be calculated */ + const WCHAR *name /* File name to be calculated */ ) { WCHAR chr; @@ -2184,7 +2511,7 @@ static DWORD xsum32 ( /* Returns 32-bit checksum */ /*------------------------------------*/ static FRESULT load_xdir ( /* FR_INT_ERR: invalid entry block */ - DIR* dp /* Reading directory object pointing top of the entry block to load */ + DIR *dp /* Reading directory object pointing top of the entry block to load */ ) { FRESULT res = FR_DISK_ERR; @@ -2194,37 +2521,66 @@ static FRESULT load_xdir ( /* FR_INT_ERR: invalid entry block */ /* Load file directory entry */ res = move_window(dp->obj.fs, dp->sect); - if (res != FR_OK) return res; - if (dp->dir[XDIR_Type] != ET_FILEDIR) return FR_INT_ERR; /* Invalid order */ + if (res != FR_OK) { + return res; + } + if (dp->dir[XDIR_Type] != ET_FILEDIR) { + return FR_INT_ERR; /* Invalid order */ + } mem_cpy(dirb + 0 * SZDIRE, dp->dir, SZDIRE); sz_ent = (dirb[XDIR_NumSec] + 1) * SZDIRE; - if (sz_ent < 3 * SZDIRE || sz_ent > 19 * SZDIRE) return FR_INT_ERR; + if (sz_ent < 3 * SZDIRE || sz_ent > 19 * SZDIRE) { + return FR_INT_ERR; + } /* Load stream extension entry */ res = dir_next(dp, 0); - if (res == FR_NO_FILE) res = FR_INT_ERR; /* It cannot be */ - if (res != FR_OK) return res; + if (res == FR_NO_FILE) { + res = FR_INT_ERR; /* It cannot be */ + } + if (res != FR_OK) { + return res; + } res = move_window(dp->obj.fs, dp->sect); - if (res != FR_OK) return res; - if (dp->dir[XDIR_Type] != ET_STREAM) return FR_INT_ERR; /* Invalid order */ + if (res != FR_OK) { + return res; + } + if (dp->dir[XDIR_Type] != ET_STREAM) { + return FR_INT_ERR; /* Invalid order */ + } mem_cpy(dirb + 1 * SZDIRE, dp->dir, SZDIRE); - if (MAXDIRB(dirb[XDIR_NumName]) > sz_ent) return FR_INT_ERR; + if (MAXDIRB(dirb[XDIR_NumName]) > sz_ent) { + return FR_INT_ERR; + } /* Load file name entries */ i = 2 * SZDIRE; /* Name offset to load */ do { res = dir_next(dp, 0); - if (res == FR_NO_FILE) res = FR_INT_ERR; /* It cannot be */ - if (res != FR_OK) return res; + if (res == FR_NO_FILE) { + res = FR_INT_ERR; /* It cannot be */ + } + if (res != FR_OK) { + return res; + } res = move_window(dp->obj.fs, dp->sect); - if (res != FR_OK) return res; - if (dp->dir[XDIR_Type] != ET_FILENAME) return FR_INT_ERR; /* Invalid order */ - if (i < MAXDIRB(FF_MAX_LFN)) mem_cpy(dirb + i, dp->dir, SZDIRE); - } while ((i += SZDIRE) < sz_ent); + if (res != FR_OK) { + return res; + } + if (dp->dir[XDIR_Type] != ET_FILENAME) { + return FR_INT_ERR; /* Invalid order */ + } + if (i < MAXDIRB(FF_MAX_LFN)) { + mem_cpy(dirb + i, dp->dir, SZDIRE); + } + } + while ((i += SZDIRE) < sz_ent); /* Sanity check (do it for only accessible object) */ if (i <= MAXDIRB(FF_MAX_LFN)) { - if (xdir_sum(dirb) != ld_word(dirb + XDIR_SetSum)) return FR_INT_ERR; + if (xdir_sum(dirb) != ld_word(dirb + XDIR_SetSum)) { + return FR_INT_ERR; + } } return FR_OK; } @@ -2235,8 +2591,8 @@ static FRESULT load_xdir ( /* FR_INT_ERR: invalid entry block */ /*------------------------------------------------------------------*/ static void init_alloc_info ( - FATFS* fs, /* Filesystem object */ - FFOBJID* obj /* Object allocation information to be initialized */ + FATFS *fs, /* Filesystem object */ + FFOBJID *obj /* Object allocation information to be initialized */ ) { obj->sclust = ld_dword(fs->dirbuf + XDIR_FstClus); /* Start cluster */ @@ -2253,8 +2609,8 @@ static void init_alloc_info ( /*------------------------------------------------*/ static FRESULT load_obj_xdir ( - DIR* dp, /* Blank directory object to be used to access containing directory */ - const FFOBJID* obj /* Object with its containing directory information */ + DIR *dp, /* Blank directory object to be used to access containing directory */ + const FFOBJID *obj /* Object with its containing directory information */ ) { FRESULT res = FR_DISK_ERR; @@ -2282,7 +2638,7 @@ static FRESULT load_obj_xdir ( /*----------------------------------------*/ static FRESULT store_xdir ( - DIR* dp /* Pointer to the directory object */ + DIR *dp /* Pointer to the directory object */ ) { FRESULT res = FR_DISK_ERR; @@ -2297,10 +2653,14 @@ static FRESULT store_xdir ( res = dir_sdi(dp, dp->blk_ofs); while (res == FR_OK) { res = move_window(dp->obj.fs, dp->sect); - if (res != FR_OK) break; + if (res != FR_OK) { + break; + } mem_cpy(dp->dir, dirb, SZDIRE); dp->obj.fs->wflag = 1; - if (--nent == 0) break; + if (--nent == 0) { + break; + } dirb += SZDIRE; res = dir_next(dp, 0); } @@ -2314,8 +2674,8 @@ static FRESULT store_xdir ( /*-------------------------------------------*/ static void create_xdir ( - BYTE* dirb, /* Pointer to the directory entry block buffer */ - const WCHAR* lfn /* Pointer to the object name */ + BYTE *dirb, /* Pointer to the directory entry block buffer */ + const WCHAR *lfn /* Pointer to the object name */ ) { UINT i; @@ -2330,16 +2690,22 @@ static void create_xdir ( /* Create file-name entries */ i = SZDIRE * 2; /* Top of file_name entries */ - nlen = nc1 = 0; wc = 1; + nlen = nc1 = 0; + wc = 1; do { - dirb[i++] = ET_FILENAME; dirb[i++] = 0; + dirb[i++] = ET_FILENAME; + dirb[i++] = 0; do { /* Fill name field */ - if (wc != 0 && (wc = lfn[nlen]) != 0) nlen++; /* Get a character if exist */ + if (wc != 0 && (wc = lfn[nlen]) != 0) { + nlen++; /* Get a character if exist */ + } st_word(dirb + i, wc); /* Store it */ i += 2; - } while (i % SZDIRE != 0); + } + while (i % SZDIRE != 0); nc1++; - } while (lfn[nlen]); /* Fill next entry if any char follows */ + } + while (lfn[nlen]); /* Fill next entry if any char follows */ dirb[XDIR_NumName] = nlen; /* Set name length */ dirb[XDIR_NumSec] = 1 + nc1; /* Set secondary count (C0 + C1s) */ @@ -2360,7 +2726,7 @@ static void create_xdir ( #define DIR_READ_LABEL(dp) dir_read(dp, 1) static FRESULT dir_read ( - DIR* dp, /* Pointer to the directory object */ + DIR *dp, /* Pointer to the directory object */ int vol /* Filtered by 0:file/directory or 1:volume label */ ) { @@ -2373,16 +2739,22 @@ static FRESULT dir_read ( while (dp->sect) { res = move_window(fs, dp->sect); - if (res != FR_OK) break; + if (res != FR_OK) { + break; + } b = dp->dir[DIR_Name]; /* Test for the entry type */ if (b == 0) { - res = FR_NO_FILE; break; /* Reached to end of the directory */ + res = FR_NO_FILE; + break; /* Reached to end of the directory */ } #if FF_FS_EXFAT if (fs->fs_type == FS_EXFAT) { /* On the exFAT volume */ if (FF_USE_LABEL && vol) { - if (b == ET_VLABEL) break; /* Volume label entry? */ - } else { + if (b == ET_VLABEL) { + break; /* Volume label entry? */ + } + } + else { if (b == ET_FILEDIR) { /* Start of the file entry block? */ dp->blk_ofs = dp->dptr; /* Get location of the block */ res = load_xdir(dp); /* Load the entry block */ @@ -2392,23 +2764,27 @@ static FRESULT dir_read ( break; } } - } else + } + else #endif { /* On the FAT/FAT32 volume */ dp->obj.attr = attr = dp->dir[DIR_Attr] & AM_MASK; /* Get attribute */ #if FF_USE_LFN /* LFN configuration */ if (b == DDEM || b == '.' || (int)((attr & ~AM_ARC) == AM_VOL) != vol) { /* An entry without valid data */ ord = 0xFF; - } else { + } + else { if (attr == AM_LFN) { /* An LFN entry is found */ if (b & LLEF) { /* Is it start of an LFN sequence? */ sum = dp->dir[LDIR_Chksum]; - b &= (BYTE)~LLEF; ord = b; + b &= (BYTE)~LLEF; + ord = b; dp->blk_ofs = dp->dptr; } /* Check LFN validity and capture it */ ord = (b == ord && sum == dp->dir[LDIR_Chksum] && pick_lfn(fs->lfnbuf, dp->dir)) ? ord - 1 : 0xFF; - } else { /* An SFN entry is found */ + } + else { /* An SFN entry is found */ if (ord != 0 || sum != sum_sfn(dp->dir)) { /* Is there a valid LFN? */ dp->blk_ofs = 0xFFFFFFFF; /* It has no LFN. */ } @@ -2422,10 +2798,14 @@ static FRESULT dir_read ( #endif } res = dir_next(dp, 0); /* Next entry */ - if (res != FR_OK) break; + if (res != FR_OK) { + break; + } } - if (res != FR_OK) dp->sect = 0; /* Terminate the read operation on error or EOT */ + if (res != FR_OK) { + dp->sect = 0; /* Terminate the read operation on error or EOT */ + } return res; } @@ -2438,7 +2818,7 @@ static FRESULT dir_read ( /*-----------------------------------------------------------------------*/ static FRESULT dir_find ( /* FR_OK(0):succeeded, !=0:error */ - DIR* dp /* Pointer to the directory object with the file name */ + DIR *dp /* Pointer to the directory object with the file name */ ) { FRESULT res = FR_DISK_ERR; @@ -2449,7 +2829,9 @@ static FRESULT dir_find ( /* FR_OK(0):succeeded, !=0:error */ #endif res = dir_sdi(dp, 0); /* Rewind directory object */ - if (res != FR_OK) return res; + if (res != FR_OK) { + return res; + } #if FF_FS_EXFAT if (fs->fs_type == FS_EXFAT) { /* On the exFAT volume */ BYTE nc; @@ -2458,54 +2840,82 @@ static FRESULT dir_find ( /* FR_OK(0):succeeded, !=0:error */ while ((res = DIR_READ_FILE(dp)) == FR_OK) { /* Read an item */ #if FF_MAX_LFN < 255 - if (fs->dirbuf[XDIR_NumName] > FF_MAX_LFN) continue; /* Skip comparison if inaccessible object name */ -#endif - if (ld_word(fs->dirbuf + XDIR_NameHash) != hash) continue; /* Skip comparison if hash mismatched */ - for (nc = fs->dirbuf[XDIR_NumName], di = SZDIRE * 2, ni = 0; nc; nc--, di += 2, ni++) { /* Compare the name */ - if ((di % SZDIRE) == 0) di += 2; - if (ff_wtoupper(ld_word(fs->dirbuf + di)) != ff_wtoupper(fs->lfnbuf[ni])) break; + if (fs->dirbuf[XDIR_NumName] > FF_MAX_LFN) { + continue; /* Skip comparison if inaccessible object name */ + } +#endif + if (ld_word(fs->dirbuf + XDIR_NameHash) != hash) { + continue; /* Skip comparison if hash mismatched */ + } + for (nc = fs->dirbuf[XDIR_NumName], di = SZDIRE * 2, ni = 0; nc; nc--, di += 2, ni++) { /* Compare the name */ + if ((di % SZDIRE) == 0) { + di += 2; + } + if (ff_wtoupper(ld_word(fs->dirbuf + di)) != ff_wtoupper(fs->lfnbuf[ni])) { + break; + } + } + if (nc == 0 && !fs->lfnbuf[ni]) { + break; /* Name matched? */ } - if (nc == 0 && !fs->lfnbuf[ni]) break; /* Name matched? */ } return res; } #endif /* On the FAT/FAT32 volume */ #if FF_USE_LFN - ord = sum = 0xFF; dp->blk_ofs = 0xFFFFFFFF; /* Reset LFN sequence */ + ord = sum = 0xFF; + dp->blk_ofs = 0xFFFFFFFF; /* Reset LFN sequence */ #endif do { res = move_window(fs, dp->sect); - if (res != FR_OK) break; + if (res != FR_OK) { + break; + } c = dp->dir[DIR_Name]; - if (c == 0) { res = FR_NO_FILE; break; } /* Reached to end of table */ + if (c == 0) { + res = FR_NO_FILE; /* Reached to end of table */ + break; + } #if FF_USE_LFN /* LFN configuration */ dp->obj.attr = a = dp->dir[DIR_Attr] & AM_MASK; if (c == DDEM || ((a & AM_VOL) && a != AM_LFN)) { /* An entry without valid data */ - ord = 0xFF; dp->blk_ofs = 0xFFFFFFFF; /* Reset LFN sequence */ - } else { + ord = 0xFF; + dp->blk_ofs = 0xFFFFFFFF; /* Reset LFN sequence */ + } + else { if (a == AM_LFN) { /* An LFN entry is found */ if (!(dp->fn[NSFLAG] & NS_NOLFN)) { if (c & LLEF) { /* Is it start of LFN sequence? */ sum = dp->dir[LDIR_Chksum]; - c &= (BYTE)~LLEF; ord = c; /* LFN start order */ + c &= (BYTE)~LLEF; + ord = c; /* LFN start order */ dp->blk_ofs = dp->dptr; /* Start offset of LFN */ } /* Check validity of the LFN entry and compare it with given name */ ord = (c == ord && sum == dp->dir[LDIR_Chksum] && cmp_lfn(fs->lfnbuf, dp->dir)) ? ord - 1 : 0xFF; } - } else { /* An SFN entry is found */ - if (ord == 0 && sum == sum_sfn(dp->dir)) break; /* LFN matched? */ - if (!(dp->fn[NSFLAG] & NS_LOSS) && !memcmp(dp->dir, dp->fn, 11)) break; /* SFN matched? */ - ord = 0xFF; dp->blk_ofs = 0xFFFFFFFF; /* Reset LFN sequence */ + } + else { /* An SFN entry is found */ + if (ord == 0 && sum == sum_sfn(dp->dir)) { + break; /* LFN matched? */ + } + if (!(dp->fn[NSFLAG] & NS_LOSS) && !memcmp(dp->dir, dp->fn, 11)) { + break; /* SFN matched? */ + } + ord = 0xFF; + dp->blk_ofs = 0xFFFFFFFF; /* Reset LFN sequence */ } } #else /* Non LFN configuration */ dp->obj.attr = dp->dir[DIR_Attr] & AM_MASK; - if (!(dp->dir[DIR_Attr] & AM_VOL) && !memcmp(dp->dir, dp->fn, 11)) break; /* Is it a valid entry? */ + if (!(dp->dir[DIR_Attr] & AM_VOL) && !memcmp(dp->dir, dp->fn, 11)) { + break; /* Is it a valid entry? */ + } #endif res = dir_next(dp, 0); /* Next entry */ - } while (res == FR_OK); + } + while (res == FR_OK); return res; } @@ -2518,8 +2928,9 @@ static FRESULT dir_find ( /* FR_OK(0):succeeded, !=0:error */ /* Register an object to the directory */ /*-----------------------------------------------------------------------*/ -static FRESULT dir_register ( /* FR_OK:succeeded, FR_DENIED:no free entry or too many SFN collision, FR_DISK_ERR:disk error */ - DIR* dp /* Target directory with object name to be created */ +static FRESULT +dir_register ( /* FR_OK:succeeded, FR_DENIED:no free entry or too many SFN collision, FR_DISK_ERR:disk error */ + DIR *dp /* Target directory with object name to be created */ ) { FRESULT res = FR_DISK_ERR; @@ -2529,33 +2940,45 @@ static FRESULT dir_register ( /* FR_OK:succeeded, FR_DENIED:no free entry or too BYTE sn[12], sum; - if (dp->fn[NSFLAG] & (NS_DOT | NS_NONAME)) return FR_INVALID_NAME; /* Check name validity */ + if (dp->fn[NSFLAG] & (NS_DOT | NS_NONAME)) { + return FR_INVALID_NAME; /* Check name validity */ + } for (len = 0; fs->lfnbuf[len]; len++) ; /* Get lfn length */ #if FF_FS_EXFAT if (fs->fs_type == FS_EXFAT) { /* On the exFAT volume */ n_ent = (len + 14) / 15 + 2; /* Number of entries to allocate (85+C0+C1s) */ res = dir_alloc(dp, n_ent); /* Allocate directory entries */ - if (res != FR_OK) return res; + if (res != FR_OK) { + return res; + } dp->blk_ofs = dp->dptr - SZDIRE * (n_ent - 1); /* Set the allocated entry block offset */ if (dp->obj.stat & 4) { /* Has the directory been stretched by new allocation? */ dp->obj.stat &= ~4; res = fill_first_frag(&dp->obj); /* Fill the first fragment on the FAT if needed */ - if (res != FR_OK) return res; + if (res != FR_OK) { + return res; + } res = fill_last_frag(&dp->obj, dp->clust, 0xFFFFFFFF); /* Fill the last fragment on the FAT if needed */ - if (res != FR_OK) return res; + if (res != FR_OK) { + return res; + } if (dp->obj.sclust != 0) { /* Is it a sub-directory? */ DIR dj; res = load_obj_xdir(&dj, &dp->obj); /* Load the object status */ - if (res != FR_OK) return res; + if (res != FR_OK) { + return res; + } dp->obj.objsize += (DWORD)fs->csize * SS(fs); /* Increase the directory size by cluster size */ st_qword(fs->dirbuf + XDIR_FileSize, dp->obj.objsize); st_qword(fs->dirbuf + XDIR_ValidFileSize, dp->obj.objsize); fs->dirbuf[XDIR_GenFlags] = dp->obj.stat | 1; /* Update the allocation status */ res = store_xdir(&dj); /* Store the object status */ - if (res != FR_OK) return res; + if (res != FR_OK) { + return res; + } } } @@ -2570,10 +2993,16 @@ static FRESULT dir_register ( /* FR_OK:succeeded, FR_DENIED:no free entry or too for (n = 1; n < 100; n++) { gen_numname(dp->fn, sn, fs->lfnbuf, n); /* Generate a numbered name */ res = dir_find(dp); /* Check if the name collides with existing SFN */ - if (res != FR_OK) break; + if (res != FR_OK) { + break; + } + } + if (n == 100) { + return FR_DENIED; /* Abort if too many collisions */ + } + if (res != FR_NO_FILE) { + return res; /* Abort if the result is other than 'not collided' */ } - if (n == 100) return FR_DENIED; /* Abort if too many collisions */ - if (res != FR_NO_FILE) return res; /* Abort if the result is other than 'not collided' */ dp->fn[NSFLAG] = sn[NSFLAG]; } @@ -2586,11 +3015,14 @@ static FRESULT dir_register ( /* FR_OK:succeeded, FR_DENIED:no free entry or too sum = sum_sfn(dp->fn); /* Checksum value of the SFN tied to the LFN */ do { /* Store LFN entries in bottom first */ res = move_window(fs, dp->sect); - if (res != FR_OK) break; + if (res != FR_OK) { + break; + } put_lfn(fs->lfnbuf, dp->dir, (BYTE)n_ent, sum); fs->wflag = 1; res = dir_next(dp, 0); /* Next entry */ - } while (res == FR_OK && --n_ent); + } + while (res == FR_OK && --n_ent); } } @@ -2625,7 +3057,7 @@ static FRESULT dir_register ( /* FR_OK:succeeded, FR_DENIED:no free entry or too /*-----------------------------------------------------------------------*/ static FRESULT dir_remove ( /* FR_OK:Succeeded, FR_DISK_ERR:A disk error */ - DIR* dp /* Directory object pointing the entry to be removed */ + DIR *dp /* Directory object pointing the entry to be removed */ ) { FRESULT res = FR_DISK_ERR; @@ -2637,17 +3069,25 @@ static FRESULT dir_remove ( /* FR_OK:Succeeded, FR_DISK_ERR:A disk error */ if (res == FR_OK) { do { res = move_window(fs, dp->sect); - if (res != FR_OK) break; + if (res != FR_OK) { + break; + } if (FF_FS_EXFAT && fs->fs_type == FS_EXFAT) { /* On the exFAT volume */ dp->dir[XDIR_Type] &= 0x7F; /* Clear the entry InUse flag. */ - } else { /* On the FAT/FAT32 volume */ + } + else { /* On the FAT/FAT32 volume */ dp->dir[DIR_Name] = DDEM; /* Mark the entry 'deleted'. */ } fs->wflag = 1; - if (dp->dptr >= last) break; /* If reached last entry then all entries of the object has been deleted. */ + if (dp->dptr >= last) { + break; /* If reached last entry then all entries of the object has been deleted. */ + } res = dir_next(dp, 0); /* Next entry */ - } while (res == FR_OK); - if (res == FR_NO_FILE) res = FR_INT_ERR; + } + while (res == FR_OK); + if (res == FR_NO_FILE) { + res = FR_INT_ERR; + } } #else /* Non LFN configuration */ @@ -2671,8 +3111,8 @@ static FRESULT dir_remove ( /* FR_OK:Succeeded, FR_DISK_ERR:A disk error */ /*-----------------------------------------------------------------------*/ static void get_fileinfo ( - DIR* dp, /* Pointer to the directory object */ - FILINFO* fno /* Pointer to the file information to be filled */ + DIR *dp, /* Pointer to the directory object */ + FILINFO *fno /* Pointer to the file information to be filled */ ) { UINT si, di; @@ -2687,33 +3127,47 @@ static void get_fileinfo ( fno->fname[0] = 0; /* Invaidate file info */ - if (dp->sect == 0) return; /* Exit if read pointer has reached end of directory */ + if (dp->sect == 0) { + return; /* Exit if read pointer has reached end of directory */ + } #if FF_USE_LFN /* LFN configuration */ #if FF_FS_EXFAT if (fs->fs_type == FS_EXFAT) { /* exFAT volume */ UINT nc = 0; - si = SZDIRE * 2; di = 0; /* 1st C1 entry in the entry block */ + si = SZDIRE * 2; + di = 0; /* 1st C1 entry in the entry block */ hs = 0; while (nc < fs->dirbuf[XDIR_NumName]) { if (si >= MAXDIRB(FF_MAX_LFN)) { /* Truncated directory block? */ - di = 0; break; + di = 0; + break; } - if ((si % SZDIRE) == 0) si += 2; /* Skip entry type field */ - wc = ld_word(fs->dirbuf + si); si += 2; nc++; /* Get a character */ + if ((si % SZDIRE) == 0) { + si += 2; /* Skip entry type field */ + } + wc = ld_word(fs->dirbuf + si); + si += 2; + nc++; /* Get a character */ if (hs == 0 && IsSurrogate(wc)) { /* Is it a surrogate? */ - hs = wc; continue; /* Get low surrogate */ + hs = wc; + continue; /* Get low surrogate */ } nw = put_utf((DWORD)hs << 16 | wc, &fno->fname[di], FF_LFN_BUF - di); /* Store it in API encoding */ if (nw == 0) { /* Buffer overflow or wrong char? */ - di = 0; break; + di = 0; + break; } di += nw; hs = 0; } - if (hs != 0) di = 0; /* Broken surrogate pair? */ - if (di == 0) fno->fname[di++] = '\?'; /* Inaccessible object name? */ + if (hs != 0) { + di = 0; /* Broken surrogate pair? */ + } + if (di == 0) { + fno->fname[di++] = '\?'; /* Inaccessible object name? */ + } fno->fname[di] = 0; /* Terminate the name */ fno->altname[0] = 0; /* exFAT does not support SFN */ @@ -2722,7 +3176,8 @@ static void get_fileinfo ( fno->ftime = ld_word(fs->dirbuf + XDIR_ModTime + 0); /* Time */ fno->fdate = ld_word(fs->dirbuf + XDIR_ModTime + 2); /* Date */ return; - } else + } + else #endif { /* FAT/FAT32 volume */ if (dp->blk_ofs != 0xFFFFFFFF) { /* Get LFN if available */ @@ -2731,16 +3186,20 @@ static void get_fileinfo ( while (fs->lfnbuf[si] != 0) { wc = fs->lfnbuf[si++]; /* Get an LFN character (UTF-16) */ if (hs == 0 && IsSurrogate(wc)) { /* Is it a surrogate? */ - hs = wc; continue; /* Get low surrogate */ + hs = wc; + continue; /* Get low surrogate */ } nw = put_utf((DWORD)hs << 16 | wc, &fno->fname[di], FF_LFN_BUF - di); /* Store it in API encoding */ if (nw == 0) { /* Buffer overflow or wrong char? */ - di = 0; break; + di = 0; + break; } di += nw; hs = 0; } - if (hs != 0) di = 0; /* Broken surrogate pair? */ + if (hs != 0) { + di = 0; /* Broken surrogate pair? */ + } fno->fname[di] = 0; /* Terminate the LFN (null string means LFN is invalid) */ } } @@ -2748,20 +3207,28 @@ static void get_fileinfo ( si = di = 0; while (si < 11) { /* Get SFN from SFN entry */ wc = dp->dir[si++]; /* Get a char */ - if (wc == ' ') continue; /* Skip padding spaces */ - if (wc == RDDEM) wc = DDEM; /* Restore replaced DDEM character */ - if (si == 9 && di < FF_SFN_BUF) fno->altname[di++] = '.'; /* Insert a . if extension is exist */ + if (wc == ' ') { + continue; /* Skip padding spaces */ + } + if (wc == RDDEM) { + wc = DDEM; /* Restore replaced DDEM character */ + } + if (si == 9 && di < FF_SFN_BUF) { + fno->altname[di++] = '.'; /* Insert a . if extension is exist */ + } #if FF_LFN_UNICODE >= 1 /* Unicode output */ if (dbc_1st((BYTE)wc) && si != 8 && si != 11 && dbc_2nd(dp->dir[si])) { /* Make a DBC if needed */ wc = wc << 8 | dp->dir[si++]; } wc = ff_oem2uni(wc, CODEPAGE); /* ANSI/OEM -> Unicode */ if (wc == 0) { /* Wrong char in the current code page? */ - di = 0; break; + di = 0; + break; } nw = put_utf(wc, &fno->altname[di], FF_SFN_BUF - di); /* Store it in API encoding */ if (nw == 0) { /* Buffer overflow? */ - di = 0; break; + di = 0; + break; } di += nw; #else /* ANSI/OEM output */ @@ -2773,25 +3240,38 @@ static void get_fileinfo ( if (fno->fname[0] == 0) { /* If LFN is invalid, altname[] needs to be copied to fname[] */ if (di == 0) { /* If LFN and SFN both are invalid, this object is inaccessible */ fno->fname[di++] = '\?'; - } else { + } + else { for (si = di = 0, lcf = NS_BODY; fno->altname[si]; si++, di++) { /* Copy altname[] to fname[] with case information */ wc = (WCHAR)fno->altname[si]; - if (wc == '.') lcf = NS_EXT; - if (IsUpper(wc) && (dp->dir[DIR_NTres] & lcf)) wc += 0x20; + if (wc == '.') { + lcf = NS_EXT; + } + if (IsUpper(wc) && (dp->dir[DIR_NTres] & lcf)) { + wc += 0x20; + } fno->fname[di] = (TCHAR)wc; } } fno->fname[di] = 0; /* Terminate the LFN */ - if (!dp->dir[DIR_NTres]) fno->altname[0] = 0; /* Altname is not needed if neither LFN nor case info is exist. */ + if (!dp->dir[DIR_NTres]) { + fno->altname[0] = 0; /* Altname is not needed if neither LFN nor case info is exist. */ + } } #else /* Non-LFN configuration */ si = di = 0; while (si < 11) { /* Copy name body and extension */ c = (TCHAR)dp->dir[si++]; - if (c == ' ') continue; /* Skip padding spaces */ - if (c == RDDEM) c = DDEM; /* Restore replaced DDEM character */ - if (si == 9) fno->fname[di++] = '.';/* Insert a . if extension is exist */ + if (c == ' ') { + continue; /* Skip padding spaces */ + } + if (c == RDDEM) { + c = DDEM; /* Restore replaced DDEM character */ + } + if (si == 9) { + fno->fname[di++] = '.'; /* Insert a . if extension is exist */ + } fno->fname[di++] = c; } fno->fname[di] = 0; /* Terminate the SFN */ @@ -2816,7 +3296,7 @@ static void get_fileinfo ( static DWORD get_achar ( /* Get a character and advance ptr */ - const TCHAR** ptr /* Pointer to pointer to the ANSI/OEM or Unicode string */ + const TCHAR **ptr /* Pointer to pointer to the ANSI/OEM or Unicode string */ ) { DWORD chr; @@ -2824,20 +3304,28 @@ static DWORD get_achar ( /* Get a character and advance ptr */ #if FF_USE_LFN && FF_LFN_UNICODE >= 1 /* Unicode input */ chr = tchar2uni(ptr); - if (chr == 0xFFFFFFFF) chr = 0; /* Wrong UTF encoding is recognized as end of the string */ + if (chr == 0xFFFFFFFF) { + chr = 0; /* Wrong UTF encoding is recognized as end of the string */ + } chr = ff_wtoupper(chr); #else /* ANSI/OEM input */ - chr = (BYTE)*(*ptr)++; /* Get a byte */ - if (IsLower(chr)) chr -= 0x20; /* To upper ASCII char */ + chr = (BYTE) * (*ptr)++; /* Get a byte */ + if (IsLower(chr)) { + chr -= 0x20; /* To upper ASCII char */ + } #if FF_CODE_PAGE == 0 - if (ExCvt && chr >= 0x80) chr = ExCvt[chr - 0x80]; /* To upper SBCS extended char */ + if (ExCvt && chr >= 0x80) { + chr = ExCvt[chr - 0x80]; /* To upper SBCS extended char */ + } #elif FF_CODE_PAGE < 900 - if (chr >= 0x80) chr = ExCvt[chr - 0x80]; /* To upper SBCS extended char */ + if (chr >= 0x80) { + chr = ExCvt[chr - 0x80]; /* To upper SBCS extended char */ + } #endif #if FF_CODE_PAGE == 0 || FF_CODE_PAGE >= 900 if (dbc_1st((BYTE)chr)) { /* Get DBC 2nd byte if needed */ - chr = dbc_2nd((BYTE)**ptr) ? chr << 8 | (BYTE)*(*ptr)++ : 0; + chr = dbc_2nd((BYTE) **ptr) ? chr << 8 | (BYTE) * (*ptr)++ : 0; } #endif @@ -2847,8 +3335,8 @@ static DWORD get_achar ( /* Get a character and advance ptr */ static int pattern_match ( /* 0:mismatched, 1:matched */ - const TCHAR* pat, /* Matching pattern */ - const TCHAR* nam, /* String to be tested */ + const TCHAR *pat, /* Matching pattern */ + const TCHAR *nam, /* String to be tested */ UINT skip, /* Number of pre-skip chars (number of ?s, b8:infinite (* specified)) */ UINT recur /* Recursion count */ ) @@ -2860,34 +3348,51 @@ static int pattern_match ( /* 0:mismatched, 1:matched */ while ((skip & 0xFF) != 0) { /* Pre-skip name chars */ - if (!get_achar(&nam)) return 0; /* Branch mismatched if less name chars */ + if (!get_achar(&nam)) { + return 0; /* Branch mismatched if less name chars */ + } skip--; } - if (*pat == 0 && skip) return 1; /* Matched? (short circuit) */ + if (*pat == 0 && skip) { + return 1; /* Matched? (short circuit) */ + } do { - pptr = pat; nptr = nam; /* Top of pattern and name to match */ + pptr = pat; + nptr = nam; /* Top of pattern and name to match */ for (;;) { if (*pptr == '\?' || *pptr == '*') { /* Wildcard term? */ - if (recur == 0) return 0; /* Too many wildcard terms? */ + if (recur == 0) { + return 0; /* Too many wildcard terms? */ + } sk = 0; do { /* Analyze the wildcard term */ if (*pptr++ == '\?') { sk++; - } else { + } + else { sk |= 0x100; } - } while (*pptr == '\?' || *pptr == '*'); - if (pattern_match(pptr, nptr, sk, recur - 1)) return 1; /* Test new branch (recursive call) */ - nchr = *nptr; break; /* Branch mismatched */ + } + while (*pptr == '\?' || *pptr == '*'); + if (pattern_match(pptr, nptr, sk, recur - 1)) { + return 1; /* Test new branch (recursive call) */ + } + nchr = *nptr; + break; /* Branch mismatched */ } pchr = get_achar(&pptr); /* Get a pattern char */ nchr = get_achar(&nptr); /* Get a name char */ - if (pchr != nchr) break; /* Branch mismatched? */ - if (pchr == 0) return 1; /* Branch matched? (matched at end of both strings) */ + if (pchr != nchr) { + break; /* Branch mismatched? */ + } + if (pchr == 0) { + return 1; /* Branch matched? (matched at end of both strings) */ + } } get_achar(&nam); /* nam++ */ - } while (skip && nchr); /* Retry until end of name if infinite search is specified */ + } + while (skip && nchr); /* Retry until end of name if infinite search is specified */ return 0; } @@ -2901,43 +3406,60 @@ static int pattern_match ( /* 0:mismatched, 1:matched */ /*-----------------------------------------------------------------------*/ static FRESULT create_name ( /* FR_OK: successful, FR_INVALID_NAME: could not create */ - DIR* dp, /* Pointer to the directory object */ - const TCHAR** path /* Pointer to pointer to the segment in the path string */ + DIR *dp, /* Pointer to the directory object */ + const TCHAR **path /* Pointer to pointer to the segment in the path string */ ) { #if FF_USE_LFN /* LFN configuration */ BYTE b, cf; WCHAR wc; WCHAR *lfn; - const TCHAR* p; + const TCHAR *p; DWORD uc; UINT i, ni, si, di; /* Create LFN into LFN working buffer */ - p = *path; lfn = dp->obj.fs->lfnbuf; di = 0; + p = *path; + lfn = dp->obj.fs->lfnbuf; + di = 0; for (;;) { uc = tchar2uni(&p); /* Get a character */ - if (uc == 0xFFFFFFFF) return FR_INVALID_NAME; /* Invalid code or UTF decode error */ - if (uc >= 0x10000) lfn[di++] = (WCHAR)(uc >> 16); /* Store high surrogate if needed */ + if (uc == 0xFFFFFFFF) { + return FR_INVALID_NAME; /* Invalid code or UTF decode error */ + } + if (uc >= 0x10000) { + lfn[di++] = (WCHAR)(uc >> 16); /* Store high surrogate if needed */ + } wc = (WCHAR)uc; - if (wc < ' ' || IsSeparator(wc)) break; /* Break if end of the path or a separator is found */ - if (wc < 0x80 && strchr("*:<>|\"\?\x7F", (int)wc)) return FR_INVALID_NAME; /* Reject illegal characters for LFN */ - if (di >= FF_MAX_LFN) return FR_INVALID_NAME; /* Reject too long name */ + if (wc < ' ' || IsSeparator(wc)) { + break; /* Break if end of the path or a separator is found */ + } + if (wc < 0x80 && strchr("*:<>|\"\?\x7F", (int)wc)) { + return FR_INVALID_NAME; /* Reject illegal characters for LFN */ + } + if (di >= FF_MAX_LFN) { + return FR_INVALID_NAME; /* Reject too long name */ + } lfn[di++] = wc; /* Store the Unicode character */ } if (wc < ' ') { /* Stopped at end of the path? */ cf = NS_LAST; /* Last segment */ - } else { /* Stopped at a separator */ - while (IsSeparator(*p)) p++; /* Skip duplicated separators if exist */ + } + else { /* Stopped at a separator */ + while (IsSeparator(*p)) { + p++; /* Skip duplicated separators if exist */ + } cf = 0; /* Next segment may follow */ - if (IsTerminator(*p)) cf = NS_LAST; /* Ignore terminating separator */ + if (IsTerminator(*p)) { + cf = NS_LAST; /* Ignore terminating separator */ + } } *path = p; /* Return pointer to the next segment */ #if FF_FS_RPATH != 0 if ((di == 1 && lfn[di - 1] == '.') || - (di == 2 && lfn[di - 1] == '.' && lfn[di - 2] == '.')) { /* Is this segment a dot name? */ + (di == 2 && lfn[di - 1] == '.' && lfn[di - 2] == '.')) { /* Is this segment a dot name? */ lfn[di] = 0; for (i = 0; i < 11; i++) { /* Create dot name for SFN entry */ dp->fn[i] = (i < di) ? '.' : ' '; @@ -2948,22 +3470,33 @@ static FRESULT create_name ( /* FR_OK: successful, FR_INVALID_NAME: could not cr #endif while (di) { /* Snip off trailing spaces and dots if exist */ wc = lfn[di - 1]; - if (wc != ' ' && wc != '.') break; + if (wc != ' ' && wc != '.') { + break; + } di--; } lfn[di] = 0; /* LFN is created into the working buffer */ - if (di == 0) return FR_INVALID_NAME; /* Reject null name */ + if (di == 0) { + return FR_INVALID_NAME; /* Reject null name */ + } /* Create SFN in directory form */ for (si = 0; lfn[si] == ' '; si++) ; /* Remove leading spaces */ - if (si > 0 || lfn[si] == '.') cf |= NS_LOSS | NS_LFN; /* Is there any leading space or dot? */ - while (di > 0 && lfn[di - 1] != '.') di--; /* Find last dot (di<=si: no extension) */ + if (si > 0 || lfn[si] == '.') { + cf |= NS_LOSS | NS_LFN; /* Is there any leading space or dot? */ + } + while (di > 0 && lfn[di - 1] != '.') { + di--; /* Find last dot (di<=si: no extension) */ + } memset(dp->fn, ' ', 11); - i = b = 0; ni = 8; + i = b = 0; + ni = 8; for (;;) { wc = lfn[si++]; /* Get an LFN character */ - if (wc == 0) break; /* Break on end of the LFN */ + if (wc == 0) { + break; /* Break on end of the LFN */ + } if (wc == ' ' || (wc == '.' && si != di)) { /* Remove embedded spaces and dots */ cf |= NS_LOSS | NS_LFN; continue; @@ -2974,9 +3507,16 @@ static FRESULT create_name ( /* FR_OK: successful, FR_INVALID_NAME: could not cr cf |= NS_LOSS | NS_LFN; break; } - if (si != di) cf |= NS_LOSS | NS_LFN; /* Name body overflow? */ - if (si > di) break; /* No name extension? */ - si = di; i = 8; ni = 11; b <<= 2; /* Enter name extension */ + if (si != di) { + cf |= NS_LOSS | NS_LFN; /* Name body overflow? */ + } + if (si > di) { + break; /* No name extension? */ + } + si = di; + i = 8; + ni = 11; + b <<= 2; /* Enter name extension */ continue; } @@ -2985,13 +3525,18 @@ static FRESULT create_name ( /* FR_OK: successful, FR_INVALID_NAME: could not cr #if FF_CODE_PAGE == 0 if (ExCvt) { /* In SBCS cfg */ wc = ff_uni2oem(wc, CODEPAGE); /* Unicode ==> ANSI/OEM code */ - if (wc & 0x80) wc = ExCvt[wc & 0x7F]; /* Convert extended character to upper (SBCS) */ - } else { /* In DBCS cfg */ + if (wc & 0x80) { + wc = ExCvt[wc & 0x7F]; /* Convert extended character to upper (SBCS) */ + } + } + else { /* In DBCS cfg */ wc = ff_uni2oem(ff_wtoupper(wc), CODEPAGE); /* Unicode ==> Up-convert ==> ANSI/OEM code */ } #elif FF_CODE_PAGE < 900 /* In SBCS cfg */ wc = ff_uni2oem(wc, CODEPAGE); /* Unicode ==> ANSI/OEM code */ - if (wc & 0x80) wc = ExCvt[wc & 0x7F]; /* Convert extended character to upper (SBCS) */ + if (wc & 0x80) { + wc = ExCvt[wc & 0x7F]; /* Convert extended character to upper (SBCS) */ + } #else /* In DBCS cfg */ wc = ff_uni2oem(ff_wtoupper(wc), CODEPAGE); /* Unicode ==> Up-convert ==> ANSI/OEM code */ #endif @@ -3000,31 +3545,46 @@ static FRESULT create_name ( /* FR_OK: successful, FR_INVALID_NAME: could not cr if (wc >= 0x100) { /* Is this a DBC? */ if (i >= ni - 1) { /* Field overflow? */ cf |= NS_LOSS | NS_LFN; - i = ni; continue; /* Next field */ + i = ni; + continue; /* Next field */ } dp->fn[i++] = (BYTE)(wc >> 8); /* Put 1st byte */ - } else { /* SBC */ + } + else { /* SBC */ if (wc == 0 || strchr("+,;=[]", (int)wc)) { /* Replace illegal characters for SFN */ - wc = '_'; cf |= NS_LOSS | NS_LFN;/* Lossy conversion */ - } else { + wc = '_'; + cf |= NS_LOSS | NS_LFN;/* Lossy conversion */ + } + else { if (IsUpper(wc)) { /* ASCII upper case? */ b |= 2; } if (IsLower(wc)) { /* ASCII lower case? */ - b |= 1; wc -= 0x20; + b |= 1; + wc -= 0x20; } } } dp->fn[i++] = (BYTE)wc; } - if (dp->fn[0] == DDEM) dp->fn[0] = RDDEM; /* If the first character collides with DDEM, replace it with RDDEM */ + if (dp->fn[0] == DDEM) { + dp->fn[0] = RDDEM; /* If the first character collides with DDEM, replace it with RDDEM */ + } - if (ni == 8) b <<= 2; /* Shift capital flags if no extension */ - if ((b & 0x0C) == 0x0C || (b & 0x03) == 0x03) cf |= NS_LFN; /* LFN entry needs to be created if composite capitals */ + if (ni == 8) { + b <<= 2; /* Shift capital flags if no extension */ + } + if ((b & 0x0C) == 0x0C || (b & 0x03) == 0x03) { + cf |= NS_LFN; /* LFN entry needs to be created if composite capitals */ + } if (!(cf & NS_LFN)) { /* When LFN is in 8.3 format without extended character, NT flags are created */ - if (b & 0x01) cf |= NS_EXT; /* NT flag (Extension has small capital letters only) */ - if (b & 0x04) cf |= NS_BODY; /* NT flag (Body has small capital letters only) */ + if (b & 0x01) { + cf |= NS_EXT; /* NT flag (Extension has small capital letters only) */ + } + if (b & 0x04) { + cf |= NS_BODY; /* NT flag (Body has small capital letters only) */ + } } dp->fn[NSFLAG] = cf; /* SFN is created into dp->fn[] */ @@ -3039,17 +3599,23 @@ static FRESULT create_name ( /* FR_OK: successful, FR_INVALID_NAME: could not cr const char *p; /* Create file name in directory form */ - p = *path; sfn = dp->fn; + p = *path; + sfn = dp->fn; memset(sfn, ' ', 11); - si = i = 0; ni = 8; + si = i = 0; + ni = 8; #if FF_FS_RPATH != 0 if (p[si] == '.') { /* Is this a dot entry? */ for (;;) { c = (BYTE)p[si++]; - if (c != '.' || si >= 3) break; + if (c != '.' || si >= 3) { + break; + } sfn[i++] = c; } - if (!IsSeparator(c) && c > ' ') return FR_INVALID_NAME; + if (!IsSeparator(c) && c > ' ') { + return FR_INVALID_NAME; + } *path = p + si; /* Return pointer to the next segment */ sfn[NSFLAG] = (c <= ' ') ? NS_LAST | NS_DOT : NS_DOT; /* Set last segment flag if end of the path */ return FR_OK; @@ -3057,14 +3623,21 @@ static FRESULT create_name ( /* FR_OK: successful, FR_INVALID_NAME: could not cr #endif for (;;) { c = (BYTE)p[si++]; /* Get a byte */ - if (c <= ' ') break; /* Break if end of the path name */ + if (c <= ' ') { + break; /* Break if end of the path name */ + } if (IsSeparator(c)) { /* Break if a separator is found */ - while (IsSeparator(p[si])) si++; /* Skip duplicated separator if exist */ + while (IsSeparator(p[si])) { + si++; /* Skip duplicated separator if exist */ + } break; } if (c == '.' || i >= ni) { /* End of body or field overflow? */ - if (ni == 11 || c != '.') return FR_INVALID_NAME; /* Field overflow or invalid dot? */ - i = 8; ni = 11; /* Enter file extension field */ + if (ni == 11 || c != '.') { + return FR_INVALID_NAME; /* Field overflow or invalid dot? */ + } + i = 8; + ni = 11; /* Enter file extension field */ continue; } #if FF_CODE_PAGE == 0 @@ -3078,19 +3651,30 @@ static FRESULT create_name ( /* FR_OK: successful, FR_INVALID_NAME: could not cr #endif if (dbc_1st(c)) { /* Check if it is a DBC 1st byte */ d = (BYTE)p[si++]; /* Get 2nd byte */ - if (!dbc_2nd(d) || i >= ni - 1) return FR_INVALID_NAME; /* Reject invalid DBC */ + if (!dbc_2nd(d) || i >= ni - 1) { + return FR_INVALID_NAME; /* Reject invalid DBC */ + } sfn[i++] = c; sfn[i++] = d; - } else { /* SBC */ - if (strchr("*+,:;<=>[]|\"\?\x7F", (int)c)) return FR_INVALID_NAME; /* Reject illegal chrs for SFN */ - if (IsLower(c)) c -= 0x20; /* To upper */ + } + else { /* SBC */ + if (strchr("*+,:;<=>[]|\"\?\x7F", (int)c)) { + return FR_INVALID_NAME; /* Reject illegal chrs for SFN */ + } + if (IsLower(c)) { + c -= 0x20; /* To upper */ + } sfn[i++] = c; } } *path = &p[si]; /* Return pointer to the next segment */ - if (i == 0) return FR_INVALID_NAME; /* Reject nul string */ + if (i == 0) { + return FR_INVALID_NAME; /* Reject nul string */ + } - if (sfn[0] == DDEM) sfn[0] = RDDEM; /* If the first character collides with DDEM, replace it with RDDEM */ + if (sfn[0] == DDEM) { + sfn[0] = RDDEM; /* If the first character collides with DDEM, replace it with RDDEM */ + } sfn[NSFLAG] = (c <= ' ' || p[si] <= ' ') ? NS_LAST : 0; /* Set last segment flag if end of the path */ return FR_OK; @@ -3105,8 +3689,8 @@ static FRESULT create_name ( /* FR_OK: successful, FR_INVALID_NAME: could not cr /*-----------------------------------------------------------------------*/ static FRESULT follow_path ( /* FR_OK(0): successful, !=0: error code */ - DIR* dp, /* Directory object to return last directory and found object */ - const TCHAR* path /* Full-path string to find a file or directory */ + DIR *dp, /* Directory object to return last directory and found object */ + const TCHAR *path /* Full-path string to find a file or directory */ ) { FRESULT res = FR_DISK_ERR; @@ -3117,10 +3701,13 @@ static FRESULT follow_path ( /* FR_OK(0): successful, !=0: error code */ #if FF_FS_RPATH != 0 if (!IsSeparator(*path) && (FF_STR_VOLUME_ID != 2 || !IsTerminator(*path))) { /* Without heading separator */ dp->obj.sclust = fs->cdir; /* Start at the current directory */ - } else + } + else #endif { /* With heading separator */ - while (IsSeparator(*path)) path++; /* Strip separators */ + while (IsSeparator(*path)) { + path++; /* Strip separators */ + } dp->obj.sclust = 0; /* Start from the root directory */ } #if FF_FS_EXFAT @@ -3133,7 +3720,9 @@ static FRESULT follow_path ( /* FR_OK(0): successful, !=0: error code */ dp->obj.c_size = fs->cdc_size; dp->obj.c_ofs = fs->cdc_ofs; res = load_obj_xdir(&dj, &dp->obj); - if (res != FR_OK) return res; + if (res != FR_OK) { + return res; + } dp->obj.objsize = ld_dword(fs->dirbuf + XDIR_FileSize); dp->obj.stat = fs->dirbuf[XDIR_GenFlags] & 2; } @@ -3144,28 +3733,39 @@ static FRESULT follow_path ( /* FR_OK(0): successful, !=0: error code */ dp->fn[NSFLAG] = NS_NONAME; res = dir_sdi(dp, 0); - } else { /* Follow path */ + } + else { /* Follow path */ for (;;) { res = create_name(dp, &path); /* Get a segment name of the path */ - if (res != FR_OK) break; + if (res != FR_OK) { + break; + } res = dir_find(dp); /* Find an object with the segment name */ ns = dp->fn[NSFLAG]; if (res != FR_OK) { /* Failed to find the object */ if (res == FR_NO_FILE) { /* Object is not found */ if (FF_FS_RPATH && (ns & NS_DOT)) { /* If dot entry is not exist, stay there */ - if (!(ns & NS_LAST)) continue; /* Continue to follow if not last segment */ + if (!(ns & NS_LAST)) { + continue; /* Continue to follow if not last segment */ + } dp->fn[NSFLAG] = NS_NONAME; res = FR_OK; - } else { /* Could not find the object */ - if (!(ns & NS_LAST)) res = FR_NO_PATH; /* Adjust error code if not last segment */ + } + else { /* Could not find the object */ + if (!(ns & NS_LAST)) { + res = FR_NO_PATH; /* Adjust error code if not last segment */ + } } } break; } - if (ns & NS_LAST) break; /* Last segment matched. Function completed. */ + if (ns & NS_LAST) { + break; /* Last segment matched. Function completed. */ + } /* Get into the sub-directory */ if (!(dp->obj.attr & AM_DIR)) { /* It is not a sub-directory and cannot follow */ - res = FR_NO_PATH; break; + res = FR_NO_PATH; + break; } #if FF_FS_EXFAT if (fs->fs_type == FS_EXFAT) { /* Save containing directory information for next dir */ @@ -3173,7 +3773,8 @@ static FRESULT follow_path ( /* FR_OK(0): successful, !=0: error code */ dp->obj.c_size = ((DWORD)dp->obj.objsize & 0xFFFFFF00) | dp->obj.stat; dp->obj.c_ofs = dp->blk_ofs; init_alloc_info(fs, &dp->obj); /* Open next directory */ - } else + } + else #endif { dp->obj.sclust = ld_clust(fs, fs->win + dp->dptr % SS(fs)); /* Open next directory */ @@ -3192,7 +3793,7 @@ static FRESULT follow_path ( /* FR_OK(0): successful, !=0: error code */ /*-----------------------------------------------------------------------*/ static int get_ldnumber ( /* Returns logical drive number (-1:invalid drive number or null pointer) */ - const TCHAR** path /* Pointer to pointer to the path name */ + const TCHAR **path /* Pointer to pointer to the path name */ ) { const TCHAR *tp; @@ -3206,27 +3807,38 @@ static int get_ldnumber ( /* Returns logical drive number (-1:invalid drive numb #endif tt = tp = *path; - if (!tp) return vol; /* Invalid path name? */ + if (!tp) { + return vol; /* Invalid path name? */ + } do { /* Find a colon in the path */ tc = *tt++; - } while (!IsTerminator(tc) && tc != ':'); + } + while (!IsTerminator(tc) && tc != ':'); if (tc == ':') { /* DOS/Windows style volume ID? */ i = FF_VOLUMES; if (IsDigit(*tp) && tp + 2 == tt) { /* Is there a numeric volume ID + colon? */ - i = (int)*tp - '0'; /* Get the LD number */ + i = (int) * tp - '0'; /* Get the LD number */ } #if FF_STR_VOLUME_ID == 1 /* Arbitrary string is enabled */ else { i = 0; do { - sp = VolumeStr[i]; tp = *path; /* This string volume ID and path name */ + sp = VolumeStr[i]; + tp = *path; /* This string volume ID and path name */ do { /* Compare the volume ID with path name */ - c = *sp++; tc = *tp++; - if (IsLower(c)) c -= 0x20; - if (IsLower(tc)) tc -= 0x20; - } while (c && (TCHAR)c == tc); - } while ((c || tp != tt) && ++i < FF_VOLUMES); /* Repeat for each id until pattern match */ + c = *sp++; + tc = *tp++; + if (IsLower(c)) { + c -= 0x20; + } + if (IsLower(tc)) { + tc -= 0x20; + } + } + while (c && (TCHAR)c == tc); + } + while ((c || tp != tt) && ++i < FF_VOLUMES); /* Repeat for each id until pattern match */ } #endif if ((UINT)i < FF_VOLUMES) { /* If a volume ID is found, get the drive number and strip it */ @@ -3237,16 +3849,26 @@ static int get_ldnumber ( /* Returns logical drive number (-1:invalid drive numb } #if FF_STR_VOLUME_ID == 2 /* Unix style volume ID is enabled */ if (*tp == '/') { /* Is there a volume ID? */ - while (*(tp + 1) == '/') tp++; /* Skip duplicated separator */ + while (*(tp + 1) == '/') { + tp++; /* Skip duplicated separator */ + } i = 0; do { - tt = tp; sp = VolumeStr[i]; /* Path name and this string volume ID */ + tt = tp; + sp = VolumeStr[i]; /* Path name and this string volume ID */ do { /* Compare the volume ID with path name */ - c = *sp++; tc = *(++tt); - if (IsLower(c)) c -= 0x20; - if (IsLower(tc)) tc -= 0x20; - } while (c && (TCHAR)c == tc); - } while ((c || (tc != '/' && !IsTerminator(tc))) && ++i < FF_VOLUMES); /* Repeat for each ID until pattern match */ + c = *sp++; + tc = *(++tt); + if (IsLower(c)) { + c -= 0x20; + } + if (IsLower(tc)) { + tc -= 0x20; + } + } + while (c && (TCHAR)c == tc); + } + while ((c || (tc != '/' && !IsTerminator(tc))) && ++i < FF_VOLUMES); /* Repeat for each ID until pattern match */ if (i < FF_VOLUMES) { /* If a volume ID is found, get the drive number and strip it */ vol = i; /* Drive number */ *path = tt; /* Snip the drive prefix off */ @@ -3293,22 +3915,32 @@ static DWORD crc32 ( /* Returns next CRC value */ /* Check validity of GPT header */ static int test_gpt_header ( /* 0:Invalid, 1:Valid */ - const BYTE* gpth /* Pointer to the GPT header */ + const BYTE *gpth /* Pointer to the GPT header */ ) { UINT i; DWORD bcc, hlen; - if (memcmp(gpth + GPTH_Sign, "EFI PART" "\0\0\1", 12)) return 0; /* Check signature and version (1.0) */ + if (memcmp(gpth + GPTH_Sign, "EFI PART" "\0\0\1", 12)) { + return 0; /* Check signature and version (1.0) */ + } hlen = ld_dword(gpth + GPTH_Size); /* Check header size */ - if (hlen < 92 || hlen > FF_MIN_SS) return 0; + if (hlen < 92 || hlen > FF_MIN_SS) { + return 0; + } for (i = 0, bcc = 0xFFFFFFFF; i < hlen; i++) { /* Check header BCC */ bcc = crc32(bcc, i - GPTH_Bcc < 4 ? 0 : gpth[i]); } - if (~bcc != ld_dword(gpth + GPTH_Bcc)) return 0; - if (ld_dword(gpth + GPTH_PteSize) != SZ_GPTE) return 0; /* Table entry size (must be SZ_GPTE bytes) */ - if (ld_dword(gpth + GPTH_PtNum) > 128) return 0; /* Table size (must be 128 entries or less) */ + if (~bcc != ld_dword(gpth + GPTH_Bcc)) { + return 0; + } + if (ld_dword(gpth + GPTH_PteSize) != SZ_GPTE) { + return 0; /* Table entry size (must be SZ_GPTE bytes) */ + } + if (ld_dword(gpth + GPTH_PtNum) > 128) { + return 0; /* Table size (must be 128 entries or less) */ + } return 1; } @@ -3325,11 +3957,16 @@ static DWORD make_rand ( UINT r; - if (seed == 0) seed = 1; + if (seed == 0) { + seed = 1; + } do { - for (r = 0; r < 8; r++) seed = seed & 1 ? seed >> 1 ^ 0xA3000000 : seed >> 1; /* Shift 8 bits the 32-bit LFSR */ + for (r = 0; r < 8; r++) { + seed = seed & 1 ? seed >> 1 ^ 0xA3000000 : seed >> 1; /* Shift 8 bits the 32-bit LFSR */ + } *buff++ = (BYTE)seed; - } while (--n); + } + while (--n); return seed; } @@ -3344,8 +3981,9 @@ static DWORD make_rand ( /* Check what the sector is */ -static UINT check_fs ( /* 0:FAT/FAT32 VBR, 1:exFAT VBR, 2:Not FAT and valid BS, 3:Not FAT and invalid BS, 4:Disk error */ - FATFS* fs, /* Filesystem object */ +static UINT +check_fs ( /* 0:FAT/FAT32 VBR, 1:exFAT VBR, 2:Not FAT and valid BS, 3:Not FAT and invalid BS, 4:Disk error */ + FATFS *fs, /* Filesystem object */ LBA_t sect /* Sector to load and check if it is an FAT-VBR or not */ ) { @@ -3353,11 +3991,16 @@ static UINT check_fs ( /* 0:FAT/FAT32 VBR, 1:exFAT VBR, 2:Not FAT and valid BS, BYTE b; - fs->wflag = 0; fs->winsect = (LBA_t)0 - 1; /* Invaidate window */ - if (move_window(fs, sect) != FR_OK) return 4; /* Load the boot sector */ + fs->wflag = 0; + fs->winsect = (LBA_t)0 - 1; /* Invaidate window */ + if (move_window(fs, sect) != FR_OK) { + return 4; /* Load the boot sector */ + } sign = ld_word(fs->win + BS_55AA); #if FF_FS_EXFAT - if (sign == 0xAA55 && !memcmp(fs->win + BS_JmpBoot, "\xEB\x76\x90" "EXFAT ", 11)) return 1; /* It is an exFAT VBR */ + if (sign == 0xAA55 && !memcmp(fs->win + BS_JmpBoot, "\xEB\x76\x90" "EXFAT ", 11)) { + return 1; /* It is an exFAT VBR */ + } #endif b = fs->win[BS_JmpBoot]; if (b == 0xEB || b == 0xE9 || b == 0xE8) { /* Valid JumpBoot code? (short jump, near jump or near call) */ @@ -3368,13 +4011,14 @@ static UINT check_fs ( /* 0:FAT/FAT32 VBR, 1:exFAT VBR, 2:Not FAT and valid BS, w = ld_word(fs->win + BPB_BytsPerSec); b = fs->win[BPB_SecPerClus]; if ((w & (w - 1)) == 0 && w >= FF_MIN_SS && w <= FF_MAX_SS /* Properness of sector size (512-4096 and 2^n) */ - && b != 0 && (b & (b - 1)) == 0 /* Properness of cluster size (2^n) */ - && ld_word(fs->win + BPB_RsvdSecCnt) != 0 /* Properness of reserved sectors (MNBZ) */ - && (UINT)fs->win[BPB_NumFATs] - 1 <= 1 /* Properness of FATs (1 or 2) */ - && ld_word(fs->win + BPB_RootEntCnt) != 0 /* Properness of root dir entries (MNBZ) */ - && (ld_word(fs->win + BPB_TotSec16) >= 128 || ld_dword(fs->win + BPB_TotSec32) >= 0x10000) /* Properness of volume sectors (>=128) */ - && ld_word(fs->win + BPB_FATSz16) != 0) { /* Properness of FAT size (MNBZ) */ - return 0; /* It can be presumed an FAT VBR */ + && b != 0 && (b & (b - 1)) == 0 /* Properness of cluster size (2^n) */ + && ld_word(fs->win + BPB_RsvdSecCnt) != 0 /* Properness of reserved sectors (MNBZ) */ + && (UINT)fs->win[BPB_NumFATs] - 1 <= 1 /* Properness of FATs (1 or 2) */ + && ld_word(fs->win + BPB_RootEntCnt) != 0 /* Properness of root dir entries (MNBZ) */ + && (ld_word(fs->win + BPB_TotSec16) >= 128 + || ld_dword(fs->win + BPB_TotSec32) >= 0x10000) /* Properness of volume sectors (>=128) */ + && ld_word(fs->win + BPB_FATSz16) != 0) { /* Properness of FAT size (MNBZ) */ + return 0; /* It can be presumed an FAT VBR */ } } return sign == 0xAA55 ? 2 : 3; /* Not an FAT VBR (valid or invalid BS) */ @@ -3385,7 +4029,7 @@ static UINT check_fs ( /* 0:FAT/FAT32 VBR, 1:exFAT VBR, 2:Not FAT and valid BS, /* (It supports only generic partitioning rules, MBR, GPT and SFD) */ static UINT find_volume ( /* Returns BS status found in the hosting drive */ - FATFS* fs, /* Filesystem object */ + FATFS *fs, /* Filesystem object */ UINT part /* Partition to fined = 0:find as SFD and partitions, >0:forced partition number */ ) { @@ -3394,7 +4038,9 @@ static UINT find_volume ( /* Returns BS status found in the hosting drive */ fmt = check_fs(fs, 0); /* Load sector 0 and check if it is an FAT VBR as SFD format */ - if (fmt != 2 && (fmt >= 3 || part == 0)) return fmt; /* Returns if it is an FAT VBR as auto scan, not a BS or disk error */ + if (fmt != 2 && (fmt >= 3 || part == 0)) { + return fmt; /* Returns if it is an FAT VBR as auto scan, not a BS or disk error */ + } /* Sector 0 is not an FAT VBR or forced partition number wants a partition */ @@ -3403,31 +4049,44 @@ static UINT find_volume ( /* Returns BS status found in the hosting drive */ DWORD n_ent, v_ent, ofs; QWORD pt_lba; - if (move_window(fs, 1) != FR_OK) return 4; /* Load GPT header sector (next to MBR) */ - if (!test_gpt_header(fs->win)) return 3; /* Check if GPT header is valid */ + if (move_window(fs, 1) != FR_OK) { + return 4; /* Load GPT header sector (next to MBR) */ + } + if (!test_gpt_header(fs->win)) { + return 3; /* Check if GPT header is valid */ + } n_ent = ld_dword(fs->win + GPTH_PtNum); /* Number of entries */ pt_lba = ld_qword(fs->win + GPTH_PtOfs); /* Table location */ for (v_ent = i = 0; i < n_ent; i++) { /* Find FAT partition */ - if (move_window(fs, pt_lba + i * SZ_GPTE / SS(fs)) != FR_OK) return 4; /* PT sector */ + if (move_window(fs, pt_lba + i * SZ_GPTE / SS(fs)) != FR_OK) { + return 4; /* PT sector */ + } ofs = i * SZ_GPTE % SS(fs); /* Offset in the sector */ if (!memcmp(fs->win + ofs + GPTE_PtGuid, GUID_MS_Basic, 16)) { /* MS basic data partition? */ v_ent++; fmt = check_fs(fs, ld_qword(fs->win + ofs + GPTE_FstLba)); /* Load VBR and check status */ - if (part == 0 && fmt <= 1) return fmt; /* Auto search (valid FAT volume found first) */ - if (part != 0 && v_ent == part) return fmt; /* Forced partition order (regardless of it is valid or not) */ + if (part == 0 && fmt <= 1) { + return fmt; /* Auto search (valid FAT volume found first) */ + } + if (part != 0 && v_ent == part) { + return fmt; /* Forced partition order (regardless of it is valid or not) */ + } } } return 3; /* Not found */ } #endif - if (FF_MULTI_PARTITION && part > 4) return 3; /* MBR has 4 partitions max */ + if (FF_MULTI_PARTITION && part > 4) { + return 3; /* MBR has 4 partitions max */ + } for (i = 0; i < 4; i++) { /* Load partition offset in the MBR */ mbr_pt[i] = ld_dword(fs->win + MBR_Table + i * SZ_PTE + PTE_StLba); } i = part ? part - 1 : 0; /* Table index to find first */ do { /* Find an FAT volume */ fmt = mbr_pt[i] ? check_fs(fs, mbr_pt[i]) : 3; /* Check if the partition is FAT */ - } while (part == 0 && fmt >= 2 && ++i < 4); + } + while (part == 0 && fmt >= 2 && ++i < 4); return fmt; } @@ -3439,8 +4098,8 @@ static UINT find_volume ( /* Returns BS status found in the hosting drive */ /*-----------------------------------------------------------------------*/ static FRESULT mount_volume ( /* FR_OK(0): successful, !=0: an error occurred */ - const TCHAR** path, /* Pointer to pointer to the path name (drive number) */ - FATFS** rfs, /* Pointer to pointer to the found filesystem object */ + const TCHAR **path, /* Pointer to pointer to the path name (drive number) */ + FATFS **rfs, /* Pointer to pointer to the found filesystem object */ BYTE mode /* Desiered access mode to check write protection */ ) { @@ -3456,13 +4115,19 @@ static FRESULT mount_volume ( /* FR_OK(0): successful, !=0: an error occurred */ /* Get logical drive number */ *rfs = 0; vol = get_ldnumber(path); - if (vol < 0) return FR_INVALID_DRIVE; + if (vol < 0) { + return FR_INVALID_DRIVE; + } /* Check if the filesystem object is valid or not */ fs = FatFs[vol]; /* Get pointer to the filesystem object */ - if (!fs) return FR_NOT_ENABLED; /* Is the filesystem object available? */ + if (!fs) { + return FR_NOT_ENABLED; /* Is the filesystem object available? */ + } #if FF_FS_REENTRANT - if (!lock_volume(fs, 1)) return FR_TIMEOUT; /* Lock the volume, and system if needed */ + if (!lock_volume(fs, 1)) { + return FR_TIMEOUT; /* Lock the volume, and system if needed */ + } #endif *rfs = fs; /* Return pointer to the filesystem object */ @@ -3489,14 +4154,22 @@ static FRESULT mount_volume ( /* FR_OK(0): successful, !=0: an error occurred */ return FR_WRITE_PROTECTED; } #if FF_MAX_SS != FF_MIN_SS /* Get sector size (multiple sector size cfg only) */ - if (disk_ioctl(fs->pdrv, GET_SECTOR_SIZE, &SS(fs)) != RES_OK) return FR_DISK_ERR; - if (SS(fs) > FF_MAX_SS || SS(fs) < FF_MIN_SS || (SS(fs) & (SS(fs) - 1))) return FR_DISK_ERR; + if (disk_ioctl(fs->pdrv, GET_SECTOR_SIZE, &SS(fs)) != RES_OK) { + return FR_DISK_ERR; + } + if (SS(fs) > FF_MAX_SS || SS(fs) < FF_MIN_SS || (SS(fs) & (SS(fs) - 1))) { + return FR_DISK_ERR; + } #endif /* Find an FAT volume on the hosting drive */ fmt = find_volume(fs, LD2PT(vol)); - if (fmt == 4) return FR_DISK_ERR; /* An error occurred in the disk I/O layer */ - if (fmt >= 2) return FR_NO_FILESYSTEM; /* No FAT volume is found */ + if (fmt == 4) { + return FR_DISK_ERR; /* An error occurred in the disk I/O layer */ + } + if (fmt >= 2) { + return FR_NO_FILESYSTEM; /* No FAT volume is found */ + } bsect = fs->winsect; /* Volume offset in the hosting physical drive */ /* An FAT volume is found (bsect). Following code initializes the filesystem object */ @@ -3507,96 +4180,151 @@ static FRESULT mount_volume ( /* FR_OK(0): successful, !=0: an error occurred */ DWORD so, cv, bcl, i; for (i = BPB_ZeroedEx; i < BPB_ZeroedEx + 53 && fs->win[i] == 0; i++) ; /* Check zero filler */ - if (i < BPB_ZeroedEx + 53) return FR_NO_FILESYSTEM; + if (i < BPB_ZeroedEx + 53) { + return FR_NO_FILESYSTEM; + } - if (ld_word(fs->win + BPB_FSVerEx) != 0x100) return FR_NO_FILESYSTEM; /* Check exFAT version (must be version 1.0) */ + if (ld_word(fs->win + BPB_FSVerEx) != 0x100) { + return FR_NO_FILESYSTEM; /* Check exFAT version (must be version 1.0) */ + } if (1 << fs->win[BPB_BytsPerSecEx] != SS(fs)) { /* (BPB_BytsPerSecEx must be equal to the physical sector size) */ return FR_NO_FILESYSTEM; } maxlba = ld_qword(fs->win + BPB_TotSecEx) + bsect; /* Last LBA of the volume + 1 */ - if (!FF_LBA64 && maxlba >= 0x100000000) return FR_NO_FILESYSTEM; /* (It cannot be accessed in 32-bit LBA) */ + if (!FF_LBA64 && maxlba >= 0x100000000) { + return FR_NO_FILESYSTEM; /* (It cannot be accessed in 32-bit LBA) */ + } fs->fsize = ld_dword(fs->win + BPB_FatSzEx); /* Number of sectors per FAT */ fs->n_fats = fs->win[BPB_NumFATsEx]; /* Number of FATs */ - if (fs->n_fats != 1) return FR_NO_FILESYSTEM; /* (Supports only 1 FAT) */ + if (fs->n_fats != 1) { + return FR_NO_FILESYSTEM; /* (Supports only 1 FAT) */ + } fs->csize = 1 << fs->win[BPB_SecPerClusEx]; /* Cluster size */ - if (fs->csize == 0) return FR_NO_FILESYSTEM; /* (Must be 1..32768 sectors) */ + if (fs->csize == 0) { + return FR_NO_FILESYSTEM; /* (Must be 1..32768 sectors) */ + } nclst = ld_dword(fs->win + BPB_NumClusEx); /* Number of clusters */ - if (nclst > MAX_EXFAT) return FR_NO_FILESYSTEM; /* (Too many clusters) */ + if (nclst > MAX_EXFAT) { + return FR_NO_FILESYSTEM; /* (Too many clusters) */ + } fs->n_fatent = nclst + 2; /* Boundaries and Limits */ fs->volbase = bsect; fs->database = bsect + ld_dword(fs->win + BPB_DataOfsEx); fs->fatbase = bsect + ld_dword(fs->win + BPB_FatOfsEx); - if (maxlba < (QWORD)fs->database + nclst * fs->csize) return FR_NO_FILESYSTEM; /* (Volume size must not be smaller than the size required) */ + if (maxlba < (QWORD)fs->database + nclst * fs->csize) { + return FR_NO_FILESYSTEM; /* (Volume size must not be smaller than the size required) */ + } fs->dirbase = ld_dword(fs->win + BPB_RootClusEx); /* Get bitmap location and check if it is contiguous (implementation assumption) */ so = i = 0; for (;;) { /* Find the bitmap entry in the root directory (in only first cluster) */ if (i == 0) { - if (so >= fs->csize) return FR_NO_FILESYSTEM; /* Not found? */ - if (move_window(fs, clst2sect(fs, (DWORD)fs->dirbase) + so) != FR_OK) return FR_DISK_ERR; + if (so >= fs->csize) { + return FR_NO_FILESYSTEM; /* Not found? */ + } + if (move_window(fs, clst2sect(fs, (DWORD)fs->dirbase) + so) != FR_OK) { + return FR_DISK_ERR; + } so++; } - if (fs->win[i] == ET_BITMAP) break; /* Is it a bitmap entry? */ + if (fs->win[i] == ET_BITMAP) { + break; /* Is it a bitmap entry? */ + } i = (i + SZDIRE) % SS(fs); /* Next entry */ } bcl = ld_dword(fs->win + i + 20); /* Bitmap cluster */ - if (bcl < 2 || bcl >= fs->n_fatent) return FR_NO_FILESYSTEM; /* (Wrong cluster#) */ + if (bcl < 2 || bcl >= fs->n_fatent) { + return FR_NO_FILESYSTEM; /* (Wrong cluster#) */ + } fs->bitbase = fs->database + fs->csize * (bcl - 2); /* Bitmap sector */ for (;;) { /* Check if bitmap is contiguous */ - if (move_window(fs, fs->fatbase + bcl / (SS(fs) / 4)) != FR_OK) return FR_DISK_ERR; + if (move_window(fs, fs->fatbase + bcl / (SS(fs) / 4)) != FR_OK) { + return FR_DISK_ERR; + } cv = ld_dword(fs->win + bcl % (SS(fs) / 4) * 4); - if (cv == 0xFFFFFFFF) break; /* Last link? */ - if (cv != ++bcl) return FR_NO_FILESYSTEM; /* Fragmented bitmap? */ + if (cv == 0xFFFFFFFF) { + break; /* Last link? */ + } + if (cv != ++bcl) { + return FR_NO_FILESYSTEM; /* Fragmented bitmap? */ + } } #if !FF_FS_READONLY fs->last_clst = fs->free_clst = 0xFFFFFFFF; /* Initialize cluster allocation information */ #endif fmt = FS_EXFAT; /* FAT sub-type */ - } else + } + else #endif /* FF_FS_EXFAT */ { - if (ld_word(fs->win + BPB_BytsPerSec) != SS(fs)) return FR_NO_FILESYSTEM; /* (BPB_BytsPerSec must be equal to the physical sector size) */ + if (ld_word(fs->win + BPB_BytsPerSec) != SS(fs)) { + return FR_NO_FILESYSTEM; /* (BPB_BytsPerSec must be equal to the physical sector size) */ + } fasize = ld_word(fs->win + BPB_FATSz16); /* Number of sectors per FAT */ - if (fasize == 0) fasize = ld_dword(fs->win + BPB_FATSz32); + if (fasize == 0) { + fasize = ld_dword(fs->win + BPB_FATSz32); + } fs->fsize = fasize; fs->n_fats = fs->win[BPB_NumFATs]; /* Number of FATs */ - if (fs->n_fats != 1 && fs->n_fats != 2) return FR_NO_FILESYSTEM; /* (Must be 1 or 2) */ + if (fs->n_fats != 1 && fs->n_fats != 2) { + return FR_NO_FILESYSTEM; /* (Must be 1 or 2) */ + } fasize *= fs->n_fats; /* Number of sectors for FAT area */ fs->csize = fs->win[BPB_SecPerClus]; /* Cluster size */ - if (fs->csize == 0 || (fs->csize & (fs->csize - 1))) return FR_NO_FILESYSTEM; /* (Must be power of 2) */ + if (fs->csize == 0 || (fs->csize & (fs->csize - 1))) { + return FR_NO_FILESYSTEM; /* (Must be power of 2) */ + } fs->n_rootdir = ld_word(fs->win + BPB_RootEntCnt); /* Number of root directory entries */ - if (fs->n_rootdir % (SS(fs) / SZDIRE)) return FR_NO_FILESYSTEM; /* (Must be sector aligned) */ + if (fs->n_rootdir % (SS(fs) / SZDIRE)) { + return FR_NO_FILESYSTEM; /* (Must be sector aligned) */ + } tsect = ld_word(fs->win + BPB_TotSec16); /* Number of sectors on the volume */ - if (tsect == 0) tsect = ld_dword(fs->win + BPB_TotSec32); + if (tsect == 0) { + tsect = ld_dword(fs->win + BPB_TotSec32); + } nrsv = ld_word(fs->win + BPB_RsvdSecCnt); /* Number of reserved sectors */ - if (nrsv == 0) return FR_NO_FILESYSTEM; /* (Must not be 0) */ + if (nrsv == 0) { + return FR_NO_FILESYSTEM; /* (Must not be 0) */ + } /* Determine the FAT sub type */ sysect = nrsv + fasize + fs->n_rootdir / (SS(fs) / SZDIRE); /* RSV + FAT + DIR */ - if (tsect < sysect) return FR_NO_FILESYSTEM; /* (Invalid volume size) */ + if (tsect < sysect) { + return FR_NO_FILESYSTEM; /* (Invalid volume size) */ + } nclst = (tsect - sysect) / fs->csize; /* Number of clusters */ - if (nclst == 0) return FR_NO_FILESYSTEM; /* (Invalid volume size) */ + if (nclst == 0) { + return FR_NO_FILESYSTEM; /* (Invalid volume size) */ + } fmt = 0; - if (nclst <= MAX_FAT32) fmt = FS_FAT32; - if (nclst <= MAX_FAT16) fmt = FS_FAT16; - if (nclst <= MAX_FAT12) fmt = FS_FAT12; - if (fmt == 0) return FR_NO_FILESYSTEM; + if (nclst <= MAX_FAT32) { + fmt = FS_FAT32; + } + if (nclst <= MAX_FAT16) { + fmt = FS_FAT16; + } + if (nclst <= MAX_FAT12) { + fmt = FS_FAT12; + } + if (fmt == 0) { + return FR_NO_FILESYSTEM; + } /* Boundaries and Limits */ fs->n_fatent = nclst + 2; /* Number of FAT entries */ @@ -3604,17 +4332,26 @@ static FRESULT mount_volume ( /* FR_OK(0): successful, !=0: an error occurred */ fs->fatbase = bsect + nrsv; /* FAT start sector */ fs->database = bsect + sysect; /* Data start sector */ if (fmt == FS_FAT32) { - if (ld_word(fs->win + BPB_FSVer32) != 0) return FR_NO_FILESYSTEM; /* (Must be FAT32 revision 0.0) */ - if (fs->n_rootdir != 0) return FR_NO_FILESYSTEM; /* (BPB_RootEntCnt must be 0) */ + if (ld_word(fs->win + BPB_FSVer32) != 0) { + return FR_NO_FILESYSTEM; /* (Must be FAT32 revision 0.0) */ + } + if (fs->n_rootdir != 0) { + return FR_NO_FILESYSTEM; /* (BPB_RootEntCnt must be 0) */ + } fs->dirbase = ld_dword(fs->win + BPB_RootClus32); /* Root directory start cluster */ szbfat = fs->n_fatent * 4; /* (Needed FAT size) */ - } else { - if (fs->n_rootdir == 0) return FR_NO_FILESYSTEM; /* (BPB_RootEntCnt must not be 0) */ + } + else { + if (fs->n_rootdir == 0) { + return FR_NO_FILESYSTEM; /* (BPB_RootEntCnt must not be 0) */ + } fs->dirbase = fs->fatbase + fasize; /* Root directory start sector */ szbfat = (fmt == FS_FAT16) ? /* (Needed FAT size) */ - fs->n_fatent * 2 : fs->n_fatent * 3 / 2 + (fs->n_fatent & 1); + fs->n_fatent * 2 : fs->n_fatent * 3 / 2 + (fs->n_fatent & 1); + } + if (fs->fsize < (szbfat + (SS(fs) - 1)) / SS(fs)) { + return FR_NO_FILESYSTEM; /* (BPB_FATSz must not be less than the size needed) */ } - if (fs->fsize < (szbfat + (SS(fs) - 1)) / SS(fs)) return FR_NO_FILESYSTEM; /* (BPB_FATSz must not be less than the size needed) */ #if !FF_FS_READONLY /* Get FSInfo if available */ @@ -3622,14 +4359,12 @@ static FRESULT mount_volume ( /* FR_OK(0): successful, !=0: an error occurred */ fs->fsi_flag = 0x80; #if (FF_FS_NOFSINFO & 3) != 3 if (fmt == FS_FAT32 /* Allow to update FSInfo only if BPB_FSInfo32 == 1 */ - && ld_word(fs->win + BPB_FSInfo32) == 1 - && move_window(fs, bsect + 1) == FR_OK) - { + && ld_word(fs->win + BPB_FSInfo32) == 1 + && move_window(fs, bsect + 1) == FR_OK) { fs->fsi_flag = 0; if (ld_word(fs->win + BS_55AA) == 0xAA55 /* Load FSInfo data if available */ - && ld_dword(fs->win + FSI_LeadSig) == 0x41615252 - && ld_dword(fs->win + FSI_StrucSig) == 0x61417272) - { + && ld_dword(fs->win + FSI_LeadSig) == 0x41615252 + && ld_dword(fs->win + FSI_StrucSig) == 0x61417272) { #if (FF_FS_NOFSINFO & 1) == 0 fs->free_clst = ld_dword(fs->win + FSI_Free_Count); #endif @@ -3667,8 +4402,8 @@ static FRESULT mount_volume ( /* FR_OK(0): successful, !=0: an error occurred */ /*-----------------------------------------------------------------------*/ static FRESULT validate ( /* Returns FR_OK or FR_INVALID_OBJECT */ - FFOBJID* obj, /* Pointer to the FFOBJID, the 1st member in the FIL/DIR structure, to check validity */ - FATFS** rfs /* Pointer to pointer to the owner filesystem object to return */ + FFOBJID *obj, /* Pointer to the FFOBJID, the 1st member in the FIL/DIR structure, to check validity */ + FATFS **rfs /* Pointer to pointer to the owner filesystem object to return */ ) { FRESULT res = FR_INVALID_OBJECT; @@ -3679,10 +4414,12 @@ static FRESULT validate ( /* Returns FR_OK or FR_INVALID_OBJECT */ if (lock_volume(obj->fs, 0)) { /* Take a grant to access the volume */ if (!(disk_status(obj->fs->pdrv) & STA_NOINIT)) { /* Test if the hosting phsical drive is kept initialized */ res = FR_OK; - } else { + } + else { unlock_volume(obj->fs, FR_OK); /* Invalidated volume, abort to access */ } - } else { /* Could not take */ + } + else { /* Could not take */ res = FR_TIMEOUT; } #else @@ -3711,8 +4448,8 @@ static FRESULT validate ( /* Returns FR_OK or FR_INVALID_OBJECT */ /*-----------------------------------------------------------------------*/ FRESULT f_mount ( - FATFS* fs, /* Pointer to the filesystem object to be registered (NULL:unmount)*/ - const TCHAR* path, /* Logical drive number to be mounted/unmounted */ + FATFS *fs, /* Pointer to the filesystem object to be registered (NULL:unmount)*/ + const TCHAR *path, /* Logical drive number to be mounted/unmounted */ BYTE opt /* Mount option: 0=Do not mount (delayed mount), 1=Mount immediately */ ) { @@ -3724,7 +4461,9 @@ FRESULT f_mount ( /* Get volume ID (logical drive number) */ vol = get_ldnumber(&rp); - if (vol < 0) return FR_INVALID_DRIVE; + if (vol < 0) { + return FR_INVALID_DRIVE; + } cfs = FatFs[vol]; /* Pointer to the filesystem object of the volume */ if (cfs) { /* Unregister current filesystem object if regsitered */ @@ -3742,7 +4481,9 @@ FRESULT f_mount ( fs->pdrv = LD2PD(vol); /* Volume hosting physical drive */ #if FF_FS_REENTRANT /* Create a volume mutex */ fs->ldrv = (BYTE)vol; /* Owner volume ID */ - if (!ff_mutex_create(vol)) return FR_INT_ERR; + if (!ff_mutex_create(vol)) { + return FR_INT_ERR; + } #if FF_FS_LOCK if (SysLock == 0) { /* Create a system mutex if needed */ if (!ff_mutex_create(FF_VOLUMES)) { @@ -3757,7 +4498,9 @@ FRESULT f_mount ( FatFs[vol] = fs; /* Register new fs object */ } - if (opt == 0) return FR_OK; /* Do not mount now, it will be mounted in subsequent file functions */ + if (opt == 0) { + return FR_OK; /* Do not mount now, it will be mounted in subsequent file functions */ + } res = mount_volume(&path, &fs, 0); /* Force mounted the volume */ LEAVE_FF(fs, res); @@ -3771,8 +4514,8 @@ FRESULT f_mount ( /*-----------------------------------------------------------------------*/ FRESULT f_open ( - FIL* fp, /* Pointer to the blank file object */ - const TCHAR* path, /* Pointer to the file name */ + FIL *fp, /* Pointer to the blank file object */ + const TCHAR *path, /* Pointer to the file name */ BYTE mode /* Access mode and open mode flags */ ) { @@ -3787,10 +4530,13 @@ FRESULT f_open ( DEF_NAMBUF - if (!fp) return FR_INVALID_OBJECT; + if (!fp) { + return FR_INVALID_OBJECT; + } /* Get logical drive number */ - mode &= FF_FS_READONLY ? FA_READ : FA_READ | FA_WRITE | FA_CREATE_ALWAYS | FA_CREATE_NEW | FA_OPEN_ALWAYS | FA_OPEN_APPEND; + mode &= FF_FS_READONLY ? FA_READ : FA_READ | FA_WRITE | FA_CREATE_ALWAYS | FA_CREATE_NEW | FA_OPEN_ALWAYS | + FA_OPEN_APPEND; res = mount_volume(&path, &fs, mode); if (res == FR_OK) { dj.obj.fs = fs; @@ -3822,8 +4568,11 @@ FRESULT f_open ( else { /* Any object with the same name is already existing */ if (dj.obj.attr & (AM_RDO | AM_DIR)) { /* Cannot overwrite it (R/O or DIR) */ res = FR_DENIED; - } else { - if (mode & FA_CREATE_NEW) res = FR_EXIST; /* Cannot create as new file */ + } + else { + if (mode & FA_CREATE_NEW) { + res = FR_EXIST; /* Cannot create as new file */ + } } } if (res == FR_OK && (mode & FA_CREATE_ALWAYS)) { /* Truncate the file if overwrite mode */ @@ -3843,7 +4592,8 @@ FRESULT f_open ( res = remove_chain(&fp->obj, fp->obj.sclust, 0); fs->last_clst = fp->obj.sclust - 1; /* Reuse the cluster hole */ } - } else + } + else #endif { /* Set directory entry initial state */ @@ -3870,7 +4620,8 @@ FRESULT f_open ( if (res == FR_OK) { /* Is the object exsiting? */ if (dj.obj.attr & AM_DIR) { /* File open against a directory */ res = FR_NO_FILE; - } else { + } + else { if ((mode & FA_WRITE) && (dj.obj.attr & AM_RDO)) { /* Write mode open against R/O file */ res = FR_DENIED; } @@ -3878,19 +4629,24 @@ FRESULT f_open ( } } if (res == FR_OK) { - if (mode & FA_CREATE_ALWAYS) mode |= FA_MODIFIED; /* Set file change flag if created or overwritten */ + if (mode & FA_CREATE_ALWAYS) { + mode |= FA_MODIFIED; /* Set file change flag if created or overwritten */ + } fp->dir_sect = fs->winsect; /* Pointer to the directory entry */ fp->dir_ptr = dj.dir; #if FF_FS_LOCK fp->obj.lockid = inc_share(&dj, (mode & ~FA_READ) ? 1 : 0); /* Lock the file for this session */ - if (fp->obj.lockid == 0) res = FR_INT_ERR; + if (fp->obj.lockid == 0) { + res = FR_INT_ERR; + } #endif } #else /* R/O configuration */ if (res == FR_OK) { if (dj.fn[NSFLAG] & NS_NONAME) { /* Is it origin directory itself? */ res = FR_INVALID_NAME; - } else { + } + else { if (dj.obj.attr & AM_DIR) { /* Is it a directory? */ res = FR_NO_FILE; } @@ -3905,7 +4661,8 @@ FRESULT f_open ( fp->obj.c_size = ((DWORD)dj.obj.objsize & 0xFFFFFF00) | dj.obj.stat; fp->obj.c_ofs = dj.blk_ofs; init_alloc_info(fs, &fp->obj); - } else + } + else #endif { fp->obj.sclust = ld_clust(fs, dj.dir); /* Get object allocation info */ @@ -3930,23 +4687,32 @@ FRESULT f_open ( clst = fp->obj.sclust; /* Follow the cluster chain */ for (ofs = fp->obj.objsize; res == FR_OK && ofs > bcs; ofs -= bcs) { clst = get_fat(&fp->obj, clst); - if (clst <= 1) res = FR_INT_ERR; - if (clst == 0xFFFFFFFF) res = FR_DISK_ERR; + if (clst <= 1) { + res = FR_INT_ERR; + } + if (clst == 0xFFFFFFFF) { + res = FR_DISK_ERR; + } } fp->clust = clst; if (res == FR_OK && ofs % SS(fs)) { /* Fill sector buffer if not on the sector boundary */ sc = clst2sect(fs, clst); if (sc == 0) { res = FR_INT_ERR; - } else { + } + else { fp->sect = sc + (DWORD)(ofs / SS(fs)); #if !FF_FS_TINY - if (disk_read(fs->pdrv, fp->buf, fp->sect, 1) != RES_OK) res = FR_DISK_ERR; + if (disk_read(fs->pdrv, fp->buf, fp->sect, 1) != RES_OK) { + res = FR_DISK_ERR; + } #endif } } #if FF_FS_LOCK - if (res != FR_OK) dec_share(fp->obj.lockid); /* Decrement file open counter if seek failed */ + if (res != FR_OK) { + dec_share(fp->obj.lockid); /* Decrement file open counter if seek failed */ + } #endif } #endif @@ -3955,7 +4721,9 @@ FRESULT f_open ( FREE_NAMBUF(); } - if (res != FR_OK) fp->obj.fs = 0; /* Invalidate file object on error */ + if (res != FR_OK) { + fp->obj.fs = 0; /* Invalidate file object on error */ + } LEAVE_FF(fs, res); } @@ -3968,10 +4736,10 @@ FRESULT f_open ( /*-----------------------------------------------------------------------*/ FRESULT f_read ( - FIL* fp, /* Open file to be read */ - void* buff, /* Data buffer to store the read data */ + FIL *fp, /* Open file to be read */ + void *buff, /* Data buffer to store the read data */ UINT btr, /* Number of bytes to read */ - UINT* br /* Number of bytes read */ + UINT *br /* Number of bytes read */ ) { FRESULT res = FR_DISK_ERR; @@ -3980,15 +4748,21 @@ FRESULT f_read ( LBA_t sect; FSIZE_t remain; UINT rcnt, cc, csect; - BYTE *rbuff = (BYTE*)buff; + BYTE *rbuff = (BYTE *)buff; *br = 0; /* Clear read byte counter */ res = validate(&fp->obj, &fs); /* Check validity of the file object */ - if (res != FR_OK || (res = (FRESULT)fp->err) != FR_OK) LEAVE_FF(fs, res); /* Check validity */ - if (!(fp->flag & FA_READ)) LEAVE_FF(fs, FR_DENIED); /* Check access mode */ + if (res != FR_OK || (res = (FRESULT)fp->err) != FR_OK) { + LEAVE_FF(fs, res); /* Check validity */ + } + if (!(fp->flag & FA_READ)) { + LEAVE_FF(fs, FR_DENIED); /* Check access mode */ + } remain = fp->obj.objsize - fp->fptr; - if (btr > remain) btr = (UINT)remain; /* Truncate btr by remaining bytes */ + if (btr > remain) { + btr = (UINT)remain; /* Truncate btr by remaining bytes */ + } for ( ; btr > 0; btr -= rcnt, *br += rcnt, rbuff += rcnt, fp->fptr += rcnt) { /* Repeat until btr bytes read */ if (fp->fptr % SS(fs) == 0) { /* On the sector boundary? */ @@ -3996,29 +4770,39 @@ FRESULT f_read ( if (csect == 0) { /* On the cluster boundary? */ if (fp->fptr == 0) { /* On the top of the file? */ clst = fp->obj.sclust; /* Follow cluster chain from the origin */ - } else { /* Middle or end of the file */ + } + else { /* Middle or end of the file */ #if FF_USE_FASTSEEK if (fp->cltbl) { clst = clmt_clust(fp, fp->fptr); /* Get cluster# from the CLMT */ - } else + } + else #endif { clst = get_fat(&fp->obj, fp->clust); /* Follow cluster chain on the FAT */ } } - if (clst < 2) ABORT(fs, FR_INT_ERR); - if (clst == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR); + if (clst < 2) { + ABORT(fs, FR_INT_ERR); + } + if (clst == 0xFFFFFFFF) { + ABORT(fs, FR_DISK_ERR); + } fp->clust = clst; /* Update current cluster */ } sect = clst2sect(fs, fp->clust); /* Get current sector */ - if (sect == 0) ABORT(fs, FR_INT_ERR); + if (sect == 0) { + ABORT(fs, FR_INT_ERR); + } sect += csect; cc = btr / SS(fs); /* When remaining bytes >= sector size, */ if (cc > 0) { /* Read maximum contiguous sectors directly */ if (csect + cc > fs->csize) { /* Clip at cluster boundary */ cc = fs->csize - csect; } - if (disk_read(fs->pdrv, rbuff, sect, cc) != RES_OK) ABORT(fs, FR_DISK_ERR); + if (disk_read(fs->pdrv, rbuff, sect, cc) != RES_OK) { + ABORT(fs, FR_DISK_ERR); + } #if !FF_FS_READONLY && FF_FS_MINIMIZE <= 2 /* Replace one of the read sectors with cached data if it contains a dirty sector */ #if FF_FS_TINY if (fs->wflag && fs->winsect - sect < cc) { @@ -4037,19 +4821,27 @@ FRESULT f_read ( if (fp->sect != sect) { /* Load data sector if not in cache */ #if !FF_FS_READONLY if (fp->flag & FA_DIRTY) { /* Write-back dirty sector cache */ - if (disk_write(fs->pdrv, fp->buf, fp->sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR); + if (disk_write(fs->pdrv, fp->buf, fp->sect, 1) != RES_OK) { + ABORT(fs, FR_DISK_ERR); + } fp->flag &= (BYTE)~FA_DIRTY; } #endif - if (disk_read(fs->pdrv, fp->buf, sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR); /* Fill sector cache */ + if (disk_read(fs->pdrv, fp->buf, sect, 1) != RES_OK) { + ABORT(fs, FR_DISK_ERR); /* Fill sector cache */ + } } #endif fp->sect = sect; } rcnt = SS(fs) - (UINT)fp->fptr % SS(fs); /* Number of bytes remains in the sector */ - if (rcnt > btr) rcnt = btr; /* Clip it by btr if needed */ + if (rcnt > btr) { + rcnt = btr; /* Clip it by btr if needed */ + } #if FF_FS_TINY - if (move_window(fs, fp->sect) != FR_OK) ABORT(fs, FR_DISK_ERR); /* Move sector window */ + if (move_window(fs, fp->sect) != FR_OK) { + ABORT(fs, FR_DISK_ERR); /* Move sector window */ + } mem_cpy(rbuff, fs->win + fp->fptr % SS(fs), rcnt); /* Extract partial sector */ #else mem_cpy(rbuff, fp->buf + fp->fptr % SS(fs), rcnt); /* Extract partial sector */ @@ -4076,10 +4868,10 @@ FRESULT f_read ( /*-----------------------------------------------------------------------*/ FRESULT f_write ( - FIL* fp, /* Open file to be written */ - const void* buff, /* Data to be written */ + FIL *fp, /* Open file to be written */ + const void *buff, /* Data to be written */ UINT btw, /* Number of bytes to write */ - UINT* bw /* Number of bytes written */ + UINT *bw /* Number of bytes written */ ) { FRESULT res = FR_DISK_ERR; @@ -4087,20 +4879,26 @@ FRESULT f_write ( DWORD clst; LBA_t sect; UINT wcnt, cc, csect; - const BYTE *wbuff = (const BYTE*)buff; + const BYTE *wbuff = (const BYTE *)buff; *bw = 0; /* Clear write byte counter */ res = validate(&fp->obj, &fs); /* Check validity of the file object */ - if (res != FR_OK || (res = (FRESULT)fp->err) != FR_OK) LEAVE_FF(fs, res); /* Check validity */ - if (!(fp->flag & FA_WRITE)) LEAVE_FF(fs, FR_DENIED); /* Check access mode */ + if (res != FR_OK || (res = (FRESULT)fp->err) != FR_OK) { + LEAVE_FF(fs, res); /* Check validity */ + } + if (!(fp->flag & FA_WRITE)) { + LEAVE_FF(fs, FR_DENIED); /* Check access mode */ + } /* Check fptr wrap-around (file size cannot reach 4 GiB at FAT volume) */ if ((!FF_FS_EXFAT || fs->fs_type != FS_EXFAT) && (DWORD)(fp->fptr + btw) < (DWORD)fp->fptr) { btw = (UINT)(0xFFFFFFFF - (DWORD)fp->fptr); } - for ( ; btw > 0; btw -= wcnt, *bw += wcnt, wbuff += wcnt, fp->fptr += wcnt, fp->obj.objsize = (fp->fptr > fp->obj.objsize) ? fp->fptr : fp->obj.objsize) { /* Repeat until all data written */ + for ( ; btw > 0; + btw -= wcnt, *bw += wcnt, wbuff += wcnt, fp->fptr += wcnt, + fp->obj.objsize = (fp->fptr > fp->obj.objsize) ? fp->fptr : fp->obj.objsize) { /* Repeat until all data written */ if (fp->fptr % SS(fs) == 0) { /* On the sector boundary? */ csect = (UINT)(fp->fptr / SS(fs)) & (fs->csize - 1); /* Sector offset in the cluster */ if (csect == 0) { /* On the cluster boundary? */ @@ -4109,39 +4907,57 @@ FRESULT f_write ( if (clst == 0) { /* If no cluster is allocated, */ clst = create_chain(&fp->obj, 0); /* create a new cluster chain */ } - } else { /* On the middle or end of the file */ + } + else { /* On the middle or end of the file */ #if FF_USE_FASTSEEK if (fp->cltbl) { clst = clmt_clust(fp, fp->fptr); /* Get cluster# from the CLMT */ - } else + } + else #endif { clst = create_chain(&fp->obj, fp->clust); /* Follow or stretch cluster chain on the FAT */ } } - if (clst == 0) break; /* Could not allocate a new cluster (disk full) */ - if (clst == 1) ABORT(fs, FR_INT_ERR); - if (clst == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR); + if (clst == 0) { + break; /* Could not allocate a new cluster (disk full) */ + } + if (clst == 1) { + ABORT(fs, FR_INT_ERR); + } + if (clst == 0xFFFFFFFF) { + ABORT(fs, FR_DISK_ERR); + } fp->clust = clst; /* Update current cluster */ - if (fp->obj.sclust == 0) fp->obj.sclust = clst; /* Set start cluster if the first write */ + if (fp->obj.sclust == 0) { + fp->obj.sclust = clst; /* Set start cluster if the first write */ + } } #if FF_FS_TINY - if (fs->winsect == fp->sect && sync_window(fs) != FR_OK) ABORT(fs, FR_DISK_ERR); /* Write-back sector cache */ + if (fs->winsect == fp->sect && sync_window(fs) != FR_OK) { + ABORT(fs, FR_DISK_ERR); /* Write-back sector cache */ + } #else if (fp->flag & FA_DIRTY) { /* Write-back sector cache */ - if (disk_write(fs->pdrv, fp->buf, fp->sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR); + if (disk_write(fs->pdrv, fp->buf, fp->sect, 1) != RES_OK) { + ABORT(fs, FR_DISK_ERR); + } fp->flag &= (BYTE)~FA_DIRTY; } #endif sect = clst2sect(fs, fp->clust); /* Get current sector */ - if (sect == 0) ABORT(fs, FR_INT_ERR); + if (sect == 0) { + ABORT(fs, FR_INT_ERR); + } sect += csect; cc = btw / SS(fs); /* When remaining bytes >= sector size, */ if (cc > 0) { /* Write maximum contiguous sectors directly */ if (csect + cc > fs->csize) { /* Clip at cluster boundary */ cc = fs->csize - csect; } - if (disk_write(fs->pdrv, wbuff, sect, cc) != RES_OK) ABORT(fs, FR_DISK_ERR); + if (disk_write(fs->pdrv, wbuff, sect, cc) != RES_OK) { + ABORT(fs, FR_DISK_ERR); + } #if FF_FS_MINIMIZE <= 2 #if FF_FS_TINY if (fs->winsect - sect < cc) { /* Refill sector cache if it gets invalidated by the direct write */ @@ -4160,22 +4976,28 @@ FRESULT f_write ( } #if FF_FS_TINY if (fp->fptr >= fp->obj.objsize) { /* Avoid silly cache filling on the growing edge */ - if (sync_window(fs) != FR_OK) ABORT(fs, FR_DISK_ERR); + if (sync_window(fs) != FR_OK) { + ABORT(fs, FR_DISK_ERR); + } fs->winsect = sect; } #else if (fp->sect != sect && /* Fill sector cache with file data */ - fp->fptr < fp->obj.objsize && - disk_read(fs->pdrv, fp->buf, sect, 1) != RES_OK) { - ABORT(fs, FR_DISK_ERR); + fp->fptr < fp->obj.objsize && + disk_read(fs->pdrv, fp->buf, sect, 1) != RES_OK) { + ABORT(fs, FR_DISK_ERR); } #endif fp->sect = sect; } wcnt = SS(fs) - (UINT)fp->fptr % SS(fs); /* Number of bytes remains in the sector */ - if (wcnt > btw) wcnt = btw; /* Clip it by btw if needed */ + if (wcnt > btw) { + wcnt = btw; /* Clip it by btw if needed */ + } #if FF_FS_TINY - if (move_window(fs, fp->sect) != FR_OK) ABORT(fs, FR_DISK_ERR); /* Move sector window */ + if (move_window(fs, fp->sect) != FR_OK) { + ABORT(fs, FR_DISK_ERR); /* Move sector window */ + } mem_cpy(fs->win + fp->fptr % SS(fs), wbuff, wcnt); /* Fit data to the sector */ fs->wflag = 1; #else @@ -4197,7 +5019,7 @@ FRESULT f_write ( /*-----------------------------------------------------------------------*/ FRESULT f_sync ( - FIL* fp /* Open file to be synced */ + FIL *fp /* Open file to be synced */ ) { FRESULT res = FR_DISK_ERR; @@ -4211,7 +5033,9 @@ FRESULT f_sync ( if (fp->flag & FA_MODIFIED) { /* Is there any change to the file? */ #if !FF_FS_TINY if (fp->flag & FA_DIRTY) { /* Write-back cached data if needed */ - if (disk_write(fs->pdrv, fp->buf, fp->sect, 1) != RES_OK) LEAVE_FF(fs, FR_DISK_ERR); + if (disk_write(fs->pdrv, fp->buf, fp->sect, 1) != RES_OK) { + LEAVE_FF(fs, FR_DISK_ERR); + } fp->flag &= (BYTE)~FA_DIRTY; } #endif @@ -4246,7 +5070,8 @@ FRESULT f_sync ( } FREE_NAMBUF(); } - } else + } + else #endif { res = move_window(fs, fp->dir_sect); @@ -4278,7 +5103,7 @@ FRESULT f_sync ( /*-----------------------------------------------------------------------*/ FRESULT f_close ( - FIL* fp /* Open file to be closed */ + FIL *fp /* Open file to be closed */ ) { FRESULT res = FR_DISK_ERR; @@ -4293,7 +5118,9 @@ FRESULT f_close ( if (res == FR_OK) { #if FF_FS_LOCK res = dec_share(fp->obj.lockid); /* Decrement file open counter */ - if (res == FR_OK) fp->obj.fs = 0; /* Invalidate file object */ + if (res == FR_OK) { + fp->obj.fs = 0; /* Invalidate file object */ + } #else fp->obj.fs = 0; /* Invalidate file object */ #endif @@ -4314,7 +5141,7 @@ FRESULT f_close ( /*-----------------------------------------------------------------------*/ FRESULT f_chdrive ( - const TCHAR* path /* Drive number to set */ + const TCHAR *path /* Drive number to set */ ) { int vol; @@ -4322,7 +5149,9 @@ FRESULT f_chdrive ( /* Get logical drive number */ vol = get_ldnumber(&path); - if (vol < 0) return FR_INVALID_DRIVE; + if (vol < 0) { + return FR_INVALID_DRIVE; + } CurrVol = (BYTE)vol; /* Set it as current volume */ return FR_OK; @@ -4331,7 +5160,7 @@ FRESULT f_chdrive ( FRESULT f_chdir ( - const TCHAR* path /* Pointer to the directory path */ + const TCHAR *path /* Pointer to the directory path */ ) { #if FF_STR_VOLUME_ID == 2 @@ -4359,7 +5188,8 @@ FRESULT f_chdir ( fs->cdc_ofs = dj.obj.c_ofs; } #endif - } else { + } + else { if (dj.obj.attr & AM_DIR) { /* It is a sub-directory */ #if FF_FS_EXFAT if (fs->fs_type == FS_EXFAT) { @@ -4367,18 +5197,22 @@ FRESULT f_chdir ( fs->cdc_scl = dj.obj.sclust; /* Save containing directory information */ fs->cdc_size = ((DWORD)dj.obj.objsize & 0xFFFFFF00) | dj.obj.stat; fs->cdc_ofs = dj.blk_ofs; - } else + } + else #endif { fs->cdir = ld_clust(fs, dj.dir); /* Sub-directory cluster */ } - } else { + } + else { res = FR_NO_PATH; /* Reached but a file */ } } } FREE_NAMBUF(); - if (res == FR_NO_FILE) res = FR_NO_PATH; + if (res == FR_NO_FILE) { + res = FR_NO_PATH; + } #if FF_STR_VOLUME_ID == 2 /* Also current drive is changed if in Unix style volume ID */ if (res == FR_OK) { for (i = FF_VOLUMES - 1; i && fs != FatFs[i]; i--) ; /* Set current drive */ @@ -4393,7 +5227,7 @@ FRESULT f_chdir ( #if FF_FS_RPATH >= 2 FRESULT f_getcwd ( - TCHAR* buff, /* Pointer to the directory path */ + TCHAR *buff, /* Pointer to the directory path */ UINT len /* Size of buff in unit of TCHAR */ ) { @@ -4415,7 +5249,7 @@ FRESULT f_getcwd ( /* Get logical drive */ buff[0] = 0; /* Set null string to get current volume */ - res = mount_volume((const TCHAR**)&buff, &fs, 0); /* Get current volume */ + res = mount_volume((const TCHAR **)&buff, &fs, 0); /* Get current volume */ if (res == FR_OK) { dj.obj.fs = fs; INIT_NAMBUF(fs); @@ -4426,39 +5260,63 @@ FRESULT f_getcwd ( dj.obj.sclust = fs->cdir; /* Start to follow upper directory from current directory */ while ((ccl = dj.obj.sclust) != 0) { /* Repeat while current directory is a sub-directory */ res = dir_sdi(&dj, 1 * SZDIRE); /* Get parent directory */ - if (res != FR_OK) break; + if (res != FR_OK) { + break; + } res = move_window(fs, dj.sect); - if (res != FR_OK) break; + if (res != FR_OK) { + break; + } dj.obj.sclust = ld_clust(fs, dj.dir); /* Goto parent directory */ res = dir_sdi(&dj, 0); - if (res != FR_OK) break; + if (res != FR_OK) { + break; + } do { /* Find the entry links to the child directory */ res = DIR_READ_FILE(&dj); - if (res != FR_OK) break; - if (ccl == ld_clust(fs, dj.dir)) break; /* Found the entry */ + if (res != FR_OK) { + break; + } + if (ccl == ld_clust(fs, dj.dir)) { + break; /* Found the entry */ + } res = dir_next(&dj, 0); - } while (res == FR_OK); - if (res == FR_NO_FILE) res = FR_INT_ERR;/* It cannot be 'not found'. */ - if (res != FR_OK) break; + } + while (res == FR_OK); + if (res == FR_NO_FILE) { + res = FR_INT_ERR; /* It cannot be 'not found'. */ + } + if (res != FR_OK) { + break; + } get_fileinfo(&dj, &fno); /* Get the directory name and push it to the buffer */ for (n = 0; fno.fname[n]; n++) ; /* Name length */ if (i < n + 1) { /* Insufficient space to store the path name? */ - res = FR_NOT_ENOUGH_CORE; break; + res = FR_NOT_ENOUGH_CORE; + break; + } + while (n) { + buff[--i] = fno.fname[--n]; /* Stack the name */ } - while (n) buff[--i] = fno.fname[--n]; /* Stack the name */ buff[--i] = '/'; } } if (res == FR_OK) { - if (i == len) buff[--i] = '/'; /* Is it the root-directory? */ + if (i == len) { + buff[--i] = '/'; /* Is it the root-directory? */ + } #if FF_VOLUMES >= 2 /* Put drive prefix */ vl = 0; #if FF_STR_VOLUME_ID >= 1 /* String volume ID */ - for (n = 0, vp = (const char*)VolumeStr[CurrVol]; vp[n]; n++) ; + for (n = 0, vp = (const char *)VolumeStr[CurrVol]; vp[n]; n++) ; if (i >= n + 2) { - if (FF_STR_VOLUME_ID == 2) *tp++ = (TCHAR)'/'; + if (FF_STR_VOLUME_ID == 2) { + *tp++ = (TCHAR)'/'; + } for (vl = 0; vl < n; *tp++ = (TCHAR)vp[vl], vl++) ; - if (FF_STR_VOLUME_ID == 1) *tp++ = (TCHAR)':'; + if (FF_STR_VOLUME_ID == 1) { + *tp++ = (TCHAR)':'; + } vl++; } #else /* Numeric volume ID */ @@ -4468,13 +5326,16 @@ FRESULT f_getcwd ( vl = 2; } #endif - if (vl == 0) res = FR_NOT_ENOUGH_CORE; + if (vl == 0) { + res = FR_NOT_ENOUGH_CORE; + } #endif /* Add current directory path */ if (res == FR_OK) { do { /* Copy stacked path string */ *tp++ = buff[i++]; - } while (i < len); + } + while (i < len); } } FREE_NAMBUF(); @@ -4495,7 +5356,7 @@ FRESULT f_getcwd ( /*-----------------------------------------------------------------------*/ FRESULT f_lseek ( - FIL* fp, /* Pointer to the file object */ + FIL *fp, /* Pointer to the file object */ FSIZE_t ofs /* File pointer from top of file */ ) { @@ -4511,72 +5372,101 @@ FRESULT f_lseek ( #endif res = validate(&fp->obj, &fs); /* Check validity of the file object */ - if (res == FR_OK) res = (FRESULT)fp->err; + if (res == FR_OK) { + res = (FRESULT)fp->err; + } #if FF_FS_EXFAT && !FF_FS_READONLY if (res == FR_OK && fs->fs_type == FS_EXFAT) { res = fill_last_frag(&fp->obj, fp->clust, 0xFFFFFFFF); /* Fill last fragment on the FAT if needed */ } #endif - if (res != FR_OK) LEAVE_FF(fs, res); + if (res != FR_OK) { + LEAVE_FF(fs, res); + } #if FF_USE_FASTSEEK if (fp->cltbl) { /* Fast seek */ if (ofs == CREATE_LINKMAP) { /* Create CLMT */ tbl = fp->cltbl; - tlen = *tbl++; ulen = 2; /* Given table size and required table size */ + tlen = *tbl++; + ulen = 2; /* Given table size and required table size */ cl = fp->obj.sclust; /* Origin of the chain */ if (cl != 0) { do { /* Get a fragment */ - tcl = cl; ncl = 0; ulen += 2; /* Top, length and used items */ + tcl = cl; + ncl = 0; + ulen += 2; /* Top, length and used items */ do { - pcl = cl; ncl++; + pcl = cl; + ncl++; cl = get_fat(&fp->obj, cl); - if (cl <= 1) ABORT(fs, FR_INT_ERR); - if (cl == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR); - } while (cl == pcl + 1); - if (ulen <= tlen) { /* Store the length and top of the fragment */ - *tbl++ = ncl; *tbl++ = tcl; + if (cl <= 1) { + ABORT(fs, FR_INT_ERR); + } + if (cl == 0xFFFFFFFF) { + ABORT(fs, FR_DISK_ERR); + } } - } while (cl < fs->n_fatent); /* Repeat until end of chain */ + while (cl == pcl + 1); + if (ulen <= tlen) { /* Store the length and top of the fragment */ + *tbl++ = ncl; + *tbl++ = tcl; + } + } + while (cl < fs->n_fatent); /* Repeat until end of chain */ } *fp->cltbl = ulen; /* Number of items used */ if (ulen <= tlen) { *tbl = 0; /* Terminate table */ - } else { + } + else { res = FR_NOT_ENOUGH_CORE; /* Given table size is smaller than required */ } - } else { /* Fast seek */ - if (ofs > fp->obj.objsize) ofs = fp->obj.objsize; /* Clip offset at the file size */ + } + else { /* Fast seek */ + if (ofs > fp->obj.objsize) { + ofs = fp->obj.objsize; /* Clip offset at the file size */ + } fp->fptr = ofs; /* Set file pointer */ if (ofs > 0) { fp->clust = clmt_clust(fp, ofs - 1); dsc = clst2sect(fs, fp->clust); - if (dsc == 0) ABORT(fs, FR_INT_ERR); + if (dsc == 0) { + ABORT(fs, FR_INT_ERR); + } dsc += (DWORD)((ofs - 1) / SS(fs)) & (fs->csize - 1); if (fp->fptr % SS(fs) && dsc != fp->sect) { /* Refill sector cache if needed */ #if !FF_FS_TINY #if !FF_FS_READONLY if (fp->flag & FA_DIRTY) { /* Write-back dirty sector cache */ - if (disk_write(fs->pdrv, fp->buf, fp->sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR); + if (disk_write(fs->pdrv, fp->buf, fp->sect, 1) != RES_OK) { + ABORT(fs, FR_DISK_ERR); + } fp->flag &= (BYTE)~FA_DIRTY; } #endif - if (disk_read(fs->pdrv, fp->buf, dsc, 1) != RES_OK) ABORT(fs, FR_DISK_ERR); /* Load current sector */ + if (disk_read(fs->pdrv, fp->buf, dsc, 1) != RES_OK) { + ABORT(fs, FR_DISK_ERR); /* Load current sector */ + } #endif fp->sect = dsc; } } } - } else + } + else #endif - /* Normal Seek */ + /* Normal Seek */ { #if FF_FS_EXFAT - if (fs->fs_type != FS_EXFAT && ofs >= 0x100000000) ofs = 0xFFFFFFFF; /* Clip at 4 GiB - 1 if at FATxx */ + if (fs->fs_type != FS_EXFAT && ofs >= 0x100000000) { + ofs = 0xFFFFFFFF; /* Clip at 4 GiB - 1 if at FATxx */ + } #endif - if (ofs > fp->obj.objsize && (FF_FS_READONLY || !(fp->flag & FA_WRITE))) { /* In read-only mode, clip offset with the file size */ + if (ofs > fp->obj.objsize && (FF_FS_READONLY + || !(fp->flag & FA_WRITE))) { /* In read-only mode, clip offset with the file size */ ofs = fp->obj.objsize; } ifptr = fp->fptr; @@ -4584,17 +5474,22 @@ FRESULT f_lseek ( if (ofs > 0) { bcs = (DWORD)fs->csize * SS(fs); /* Cluster size (byte) */ if (ifptr > 0 && - (ofs - 1) / bcs >= (ifptr - 1) / bcs) { /* When seek to same or following cluster, */ + (ofs - 1) / bcs >= (ifptr - 1) / bcs) { /* When seek to same or following cluster, */ fp->fptr = (ifptr - 1) & ~(FSIZE_t)(bcs - 1); /* start from the current cluster */ ofs -= fp->fptr; clst = fp->clust; - } else { /* When seek to back cluster, */ + } + else { /* When seek to back cluster, */ clst = fp->obj.sclust; /* start from the first cluster */ #if !FF_FS_READONLY if (clst == 0) { /* If no cluster chain, create a new chain */ clst = create_chain(&fp->obj, 0); - if (clst == 1) ABORT(fs, FR_INT_ERR); - if (clst == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR); + if (clst == 1) { + ABORT(fs, FR_INT_ERR); + } + if (clst == 0xFFFFFFFF) { + ABORT(fs, FR_DISK_ERR); + } fp->obj.sclust = clst; } #endif @@ -4602,7 +5497,8 @@ FRESULT f_lseek ( } if (clst != 0) { while (ofs > bcs) { /* Cluster following loop */ - ofs -= bcs; fp->fptr += bcs; + ofs -= bcs; + fp->fptr += bcs; #if !FF_FS_READONLY if (fp->flag & FA_WRITE) { /* Check if in write mode or not */ if (FF_FS_EXFAT && fp->fptr > fp->obj.objsize) { /* No FAT chain object needs correct objsize to generate FAT value */ @@ -4611,21 +5507,29 @@ FRESULT f_lseek ( } clst = create_chain(&fp->obj, clst); /* Follow chain with forceed stretch */ if (clst == 0) { /* Clip file size in case of disk full */ - ofs = 0; break; + ofs = 0; + break; } - } else + } + else #endif { clst = get_fat(&fp->obj, clst); /* Follow cluster chain if not in write mode */ } - if (clst == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR); - if (clst <= 1 || clst >= fs->n_fatent) ABORT(fs, FR_INT_ERR); + if (clst == 0xFFFFFFFF) { + ABORT(fs, FR_DISK_ERR); + } + if (clst <= 1 || clst >= fs->n_fatent) { + ABORT(fs, FR_INT_ERR); + } fp->clust = clst; } fp->fptr += ofs; if (ofs % SS(fs)) { nsect = clst2sect(fs, clst); /* Current sector */ - if (nsect == 0) ABORT(fs, FR_INT_ERR); + if (nsect == 0) { + ABORT(fs, FR_INT_ERR); + } nsect += (DWORD)(ofs / SS(fs)); } } @@ -4638,11 +5542,15 @@ FRESULT f_lseek ( #if !FF_FS_TINY #if !FF_FS_READONLY if (fp->flag & FA_DIRTY) { /* Write-back dirty sector cache */ - if (disk_write(fs->pdrv, fp->buf, fp->sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR); + if (disk_write(fs->pdrv, fp->buf, fp->sect, 1) != RES_OK) { + ABORT(fs, FR_DISK_ERR); + } fp->flag &= (BYTE)~FA_DIRTY; } #endif - if (disk_read(fs->pdrv, fp->buf, nsect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR); /* Fill sector cache */ + if (disk_read(fs->pdrv, fp->buf, nsect, 1) != RES_OK) { + ABORT(fs, FR_DISK_ERR); /* Fill sector cache */ + } #endif fp->sect = nsect; } @@ -4659,8 +5567,8 @@ FRESULT f_lseek ( /*-----------------------------------------------------------------------*/ FRESULT f_opendir ( - DIR* dp, /* Pointer to directory object to create */ - const TCHAR* path /* Pointer to the directory path */ + DIR *dp, /* Pointer to directory object to create */ + const TCHAR *path /* Pointer to the directory path */ ) { FRESULT res = FR_DISK_ERR; @@ -4668,7 +5576,9 @@ FRESULT f_opendir ( DEF_NAMBUF - if (!dp) return FR_INVALID_OBJECT; + if (!dp) { + return FR_INVALID_OBJECT; + } /* Get logical drive */ res = mount_volume(&path, &fs, 0); @@ -4685,12 +5595,14 @@ FRESULT f_opendir ( dp->obj.c_size = ((DWORD)dp->obj.objsize & 0xFFFFFF00) | dp->obj.stat; dp->obj.c_ofs = dp->blk_ofs; init_alloc_info(fs, &dp->obj); /* Get object allocation info */ - } else + } + else #endif { dp->obj.sclust = ld_clust(fs, dp->dir); /* Get object allocation info */ } - } else { /* This object is a file */ + } + else { /* This object is a file */ res = FR_NO_PATH; } } @@ -4701,8 +5613,11 @@ FRESULT f_opendir ( if (res == FR_OK) { if (dp->obj.sclust != 0) { dp->obj.lockid = inc_share(dp, 0); /* Lock the sub directory */ - if (!dp->obj.lockid) res = FR_TOO_MANY_OPEN_FILES; - } else { + if (!dp->obj.lockid) { + res = FR_TOO_MANY_OPEN_FILES; + } + } + else { dp->obj.lockid = 0; /* Root directory need not to be locked */ } } @@ -4710,9 +5625,13 @@ FRESULT f_opendir ( } } FREE_NAMBUF(); - if (res == FR_NO_FILE) res = FR_NO_PATH; + if (res == FR_NO_FILE) { + res = FR_NO_PATH; + } + } + if (res != FR_OK) { + dp->obj.fs = 0; /* Invalidate the directory object if function failed */ } - if (res != FR_OK) dp->obj.fs = 0; /* Invalidate the directory object if function failed */ LEAVE_FF(fs, res); } @@ -4735,8 +5654,12 @@ FRESULT f_closedir ( res = validate(&dp->obj, &fs); /* Check validity of the file object */ if (res == FR_OK) { #if FF_FS_LOCK - if (dp->obj.lockid) res = dec_share(dp->obj.lockid); /* Decrement sub-directory open counter */ - if (res == FR_OK) dp->obj.fs = 0; /* Invalidate directory object */ + if (dp->obj.lockid) { + res = dec_share(dp->obj.lockid); /* Decrement sub-directory open counter */ + } + if (res == FR_OK) { + dp->obj.fs = 0; /* Invalidate directory object */ + } #else dp->obj.fs = 0; /* Invalidate directory object */ #endif @@ -4755,8 +5678,8 @@ FRESULT f_closedir ( /*-----------------------------------------------------------------------*/ FRESULT f_readdir ( - DIR* dp, /* Pointer to the open directory object */ - FILINFO* fno /* Pointer to file information to return */ + DIR *dp, /* Pointer to the open directory object */ + FILINFO *fno /* Pointer to file information to return */ ) { FRESULT res = FR_DISK_ERR; @@ -4768,14 +5691,19 @@ FRESULT f_readdir ( if (res == FR_OK) { if (!fno) { res = dir_sdi(dp, 0); /* Rewind the directory object */ - } else { + } + else { INIT_NAMBUF(fs); res = DIR_READ_FILE(dp); /* Read an item */ - if (res == FR_NO_FILE) res = FR_OK; /* Ignore end of directory */ + if (res == FR_NO_FILE) { + res = FR_OK; /* Ignore end of directory */ + } if (res == FR_OK) { /* A valid entry is found */ get_fileinfo(dp, fno); /* Get the object information */ res = dir_next(dp, 0); /* Increment index for next */ - if (res == FR_NO_FILE) res = FR_OK; /* Ignore end of directory now */ + if (res == FR_NO_FILE) { + res = FR_OK; /* Ignore end of directory now */ + } } FREE_NAMBUF(); } @@ -4791,8 +5719,8 @@ FRESULT f_readdir ( /*-----------------------------------------------------------------------*/ FRESULT f_findnext ( - DIR* dp, /* Pointer to the open directory object */ - FILINFO* fno /* Pointer to the file information structure */ + DIR *dp, /* Pointer to the open directory object */ + FILINFO *fno /* Pointer to the file information structure */ ) { FRESULT res = FR_DISK_ERR; @@ -4800,10 +5728,16 @@ FRESULT f_findnext ( for (;;) { res = f_readdir(dp, fno); /* Get a directory item */ - if (res != FR_OK || !fno || !fno->fname[0]) break; /* Terminate if any error or end of directory */ - if (pattern_match(dp->pat, fno->fname, 0, FIND_RECURS)) break; /* Test for the file name */ + if (res != FR_OK || !fno || !fno->fname[0]) { + break; /* Terminate if any error or end of directory */ + } + if (pattern_match(dp->pat, fno->fname, 0, FIND_RECURS)) { + break; /* Test for the file name */ + } #if FF_USE_LFN && FF_USE_FIND == 2 - if (pattern_match(dp->pat, fno->altname, 0, FIND_RECURS)) break; /* Test for alternative name if exist */ + if (pattern_match(dp->pat, fno->altname, 0, FIND_RECURS)) { + break; /* Test for alternative name if exist */ + } #endif } return res; @@ -4816,10 +5750,10 @@ FRESULT f_findnext ( /*-----------------------------------------------------------------------*/ FRESULT f_findfirst ( - DIR* dp, /* Pointer to the blank directory object */ - FILINFO* fno, /* Pointer to the file information structure */ - const TCHAR* path, /* Pointer to the directory to open */ - const TCHAR* pattern /* Pointer to the matching pattern */ + DIR *dp, /* Pointer to the blank directory object */ + FILINFO *fno, /* Pointer to the file information structure */ + const TCHAR *path, /* Pointer to the directory to open */ + const TCHAR *pattern /* Pointer to the matching pattern */ ) { FRESULT res = FR_DISK_ERR; @@ -4843,8 +5777,8 @@ FRESULT f_findfirst ( /*-----------------------------------------------------------------------*/ FRESULT f_stat ( - const TCHAR* path, /* Pointer to the file path */ - FILINFO* fno /* Pointer to file information to return */ + const TCHAR *path, /* Pointer to the file path */ + FILINFO *fno /* Pointer to file information to return */ ) { FRESULT res = FR_DISK_ERR; @@ -4860,8 +5794,11 @@ FRESULT f_stat ( if (res == FR_OK) { /* Follow completed */ if (dj.fn[NSFLAG] & NS_NONAME) { /* It is origin directory */ res = FR_INVALID_NAME; - } else { /* Found an object */ - if (fno) get_fileinfo(&dj, fno); + } + else { /* Found an object */ + if (fno) { + get_fileinfo(&dj, fno); + } } } FREE_NAMBUF(); @@ -4878,9 +5815,9 @@ FRESULT f_stat ( /*-----------------------------------------------------------------------*/ FRESULT f_getfree ( - const TCHAR* path, /* Logical drive number */ - DWORD* nclst, /* Pointer to a variable to return number of free clusters */ - FATFS** fatfs /* Pointer to return pointer to corresponding filesystem object */ + const TCHAR *path, /* Logical drive number */ + DWORD *nclst, /* Pointer to a variable to return number of free clusters */ + FATFS **fatfs /* Pointer to return pointer to corresponding filesystem object */ ) { FRESULT res = FR_DISK_ERR; @@ -4898,22 +5835,30 @@ FRESULT f_getfree ( /* If free_clst is valid, return it without full FAT scan */ if (fs->free_clst <= fs->n_fatent - 2) { *nclst = fs->free_clst; - } else { + } + else { /* Scan FAT to obtain number of free clusters */ nfree = 0; if (fs->fs_type == FS_FAT12) { /* FAT12: Scan bit field FAT entries */ - clst = 2; obj.fs = fs; + clst = 2; + obj.fs = fs; do { stat = get_fat(&obj, clst); if (stat == 0xFFFFFFFF) { - res = FR_DISK_ERR; break; + res = FR_DISK_ERR; + break; } if (stat == 1) { - res = FR_INT_ERR; break; + res = FR_INT_ERR; + break; } - if (stat == 0) nfree++; - } while (++clst < fs->n_fatent); - } else { + if (stat == 0) { + nfree++; + } + } + while (++clst < fs->n_fatent); + } + else { #if FF_FS_EXFAT if (fs->fs_type == FS_EXFAT) { /* exFAT: Scan allocation bitmap */ BYTE bm; @@ -4925,15 +5870,19 @@ FRESULT f_getfree ( do { /* Counts numbuer of bits with zero in the bitmap */ if (i == 0) { /* New sector? */ res = move_window(fs, sect++); - if (res != FR_OK) break; + if (res != FR_OK) { + break; + } } for (b = 8, bm = ~fs->win[i]; b && clst; b--, clst--) { nfree += bm & 1; bm >>= 1; } i = (i + 1) % SS(fs); - } while (clst); - } else + } + while (clst); + } + else #endif { /* FAT16/32: Scan WORD/DWORD FAT entries */ clst = fs->n_fatent; /* Number of entries */ @@ -4942,17 +5891,25 @@ FRESULT f_getfree ( do { /* Counts numbuer of entries with zero in the FAT */ if (i == 0) { /* New sector? */ res = move_window(fs, sect++); - if (res != FR_OK) break; + if (res != FR_OK) { + break; + } } if (fs->fs_type == FS_FAT16) { - if (ld_word(fs->win + i) == 0) nfree++; + if (ld_word(fs->win + i) == 0) { + nfree++; + } i += 2; - } else { - if ((ld_dword(fs->win + i) & 0x0FFFFFFF) == 0) nfree++; + } + else { + if ((ld_dword(fs->win + i) & 0x0FFFFFFF) == 0) { + nfree++; + } i += 4; } i %= SS(fs); - } while (--clst); + } + while (--clst); } } if (res == FR_OK) { /* Update parameters if succeeded */ @@ -4974,7 +5931,7 @@ FRESULT f_getfree ( /*-----------------------------------------------------------------------*/ FRESULT f_truncate ( - FIL* fp /* Pointer to the file object */ + FIL *fp /* Pointer to the file object */ ) { FRESULT res = FR_DISK_ERR; @@ -4983,18 +5940,27 @@ FRESULT f_truncate ( res = validate(&fp->obj, &fs); /* Check validity of the file object */ - if (res != FR_OK || (res = (FRESULT)fp->err) != FR_OK) LEAVE_FF(fs, res); - if (!(fp->flag & FA_WRITE)) LEAVE_FF(fs, FR_DENIED); /* Check access mode */ + if (res != FR_OK || (res = (FRESULT)fp->err) != FR_OK) { + LEAVE_FF(fs, res); + } + if (!(fp->flag & FA_WRITE)) { + LEAVE_FF(fs, FR_DENIED); /* Check access mode */ + } if (fp->fptr < fp->obj.objsize) { /* Process when fptr is not on the eof */ if (fp->fptr == 0) { /* When set file size to zero, remove entire cluster chain */ res = remove_chain(&fp->obj, fp->obj.sclust, 0); fp->obj.sclust = 0; - } else { /* When truncate a part of the file, remove remaining clusters */ + } + else { /* When truncate a part of the file, remove remaining clusters */ ncl = get_fat(&fp->obj, fp->clust); res = FR_OK; - if (ncl == 0xFFFFFFFF) res = FR_DISK_ERR; - if (ncl == 1) res = FR_INT_ERR; + if (ncl == 0xFFFFFFFF) { + res = FR_DISK_ERR; + } + if (ncl == 1) { + res = FR_INT_ERR; + } if (res == FR_OK && ncl < fs->n_fatent) { res = remove_chain(&fp->obj, ncl, fp->clust); } @@ -5005,12 +5971,15 @@ FRESULT f_truncate ( if (res == FR_OK && (fp->flag & FA_DIRTY)) { if (disk_write(fs->pdrv, fp->buf, fp->sect, 1) != RES_OK) { res = FR_DISK_ERR; - } else { + } + else { fp->flag &= (BYTE)~FA_DIRTY; } } #endif - if (res != FR_OK) ABORT(fs, res); + if (res != FR_OK) { + ABORT(fs, res); + } } LEAVE_FF(fs, res); @@ -5024,7 +5993,7 @@ FRESULT f_truncate ( /*-----------------------------------------------------------------------*/ FRESULT f_unlink ( - const TCHAR* path /* Pointer to the file or directory path */ + const TCHAR *path /* Pointer to the file or directory path */ ) { FRESULT res = FR_DISK_ERR; @@ -5047,12 +6016,15 @@ FRESULT f_unlink ( res = FR_INVALID_NAME; /* Cannot remove dot entry */ } #if FF_FS_LOCK - if (res == FR_OK) res = chk_share(&dj, 2); /* Check if it is an open object */ + if (res == FR_OK) { + res = chk_share(&dj, 2); /* Check if it is an open object */ + } #endif if (res == FR_OK) { /* The object is accessible */ if (dj.fn[NSFLAG] & NS_NONAME) { res = FR_INVALID_NAME; /* Cannot remove the origin directory */ - } else { + } + else { if (dj.obj.attr & AM_RDO) { res = FR_DENIED; /* Cannot remove R/O object */ } @@ -5063,7 +6035,8 @@ FRESULT f_unlink ( if (fs->fs_type == FS_EXFAT) { init_alloc_info(fs, &obj); dclst = obj.sclust; - } else + } + else #endif { dclst = ld_clust(fs, dj.dir); @@ -5072,7 +6045,8 @@ FRESULT f_unlink ( #if FF_FS_RPATH != 0 if (dclst == fs->cdir) { /* Is it the current directory? */ res = FR_DENIED; - } else + } + else #endif { sdj.obj.fs = fs; /* Open the sub-directory */ @@ -5086,8 +6060,12 @@ FRESULT f_unlink ( res = dir_sdi(&sdj, 0); if (res == FR_OK) { res = DIR_READ_FILE(&sdj); /* Test if the directory is empty */ - if (res == FR_OK) res = FR_DENIED; /* Not empty? */ - if (res == FR_NO_FILE) res = FR_OK; /* Empty? */ + if (res == FR_OK) { + res = FR_DENIED; /* Not empty? */ + } + if (res == FR_NO_FILE) { + res = FR_OK; /* Empty? */ + } } } } @@ -5101,7 +6079,9 @@ FRESULT f_unlink ( res = remove_chain(&dj.obj, dclst, 0); #endif } - if (res == FR_OK) res = sync_fs(fs); + if (res == FR_OK) { + res = sync_fs(fs); + } } } FREE_NAMBUF(); @@ -5118,7 +6098,7 @@ FRESULT f_unlink ( /*-----------------------------------------------------------------------*/ FRESULT f_mkdir ( - const TCHAR* path /* Pointer to the directory path */ + const TCHAR *path /* Pointer to the directory path */ ) { FRESULT res = FR_DISK_ERR; @@ -5134,7 +6114,9 @@ FRESULT f_mkdir ( dj.obj.fs = fs; INIT_NAMBUF(fs); res = follow_path(&dj, path); /* Follow the file path */ - if (res == FR_OK) res = FR_EXIST; /* Name collision? */ + if (res == FR_OK) { + res = FR_EXIST; /* Name collision? */ + } if (FF_FS_RPATH && res == FR_NO_FILE && (dj.fn[NSFLAG] & NS_DOT)) { /* Invalid name? */ res = FR_INVALID_NAME; } @@ -5142,9 +6124,15 @@ FRESULT f_mkdir ( sobj.fs = fs; /* New object id to create a new chain */ dcl = create_chain(&sobj, 0); /* Allocate a cluster for the new directory */ res = FR_OK; - if (dcl == 0) res = FR_DENIED; /* No space to allocate a new cluster? */ - if (dcl == 1) res = FR_INT_ERR; /* Any insanity? */ - if (dcl == 0xFFFFFFFF) res = FR_DISK_ERR; /* Disk error? */ + if (dcl == 0) { + res = FR_DENIED; /* No space to allocate a new cluster? */ + } + if (dcl == 1) { + res = FR_INT_ERR; /* Any insanity? */ + } + if (dcl == 0xFFFFFFFF) { + res = FR_DISK_ERR; /* Disk error? */ + } tm = GET_FATTIME(); if (res == FR_OK) { res = dir_clear(fs, dcl); /* Clean up the new table */ @@ -5156,7 +6144,8 @@ FRESULT f_mkdir ( st_dword(fs->win + DIR_ModTime, tm); st_clust(fs, fs->win, dcl); mem_cpy(fs->win + SZDIRE, fs->win, SZDIRE); /* Create ".." entry */ - fs->win[SZDIRE + 1] = '.'; pcl = dj.obj.sclust; + fs->win[SZDIRE + 1] = '.'; + pcl = dj.obj.sclust; st_clust(fs, fs->win + SZDIRE, pcl); fs->wflag = 1; } @@ -5173,7 +6162,8 @@ FRESULT f_mkdir ( fs->dirbuf[XDIR_GenFlags] = 3; /* Initialize the object flag */ fs->dirbuf[XDIR_Attr] = AM_DIR; /* Attribute */ res = store_xdir(&dj); - } else + } + else #endif { st_dword(dj.dir + DIR_ModTime, tm); /* Created time */ @@ -5184,7 +6174,8 @@ FRESULT f_mkdir ( if (res == FR_OK) { res = sync_fs(fs); } - } else { + } + else { (void)remove_chain(&dj.obj, dcl, 0); /* Could not register, remove cluster chain */ } } @@ -5202,8 +6193,8 @@ FRESULT f_mkdir ( /*-----------------------------------------------------------------------*/ FRESULT f_rename ( - const TCHAR* path_old, /* Pointer to the object name to be renamed */ - const TCHAR* path_new /* Pointer to the new name */ + const TCHAR *path_old, /* Pointer to the object name to be renamed */ + const TCHAR *path_new /* Pointer to the new name */ ) { FRESULT res = FR_DISK_ERR; @@ -5220,7 +6211,9 @@ FRESULT f_rename ( djo.obj.fs = fs; INIT_NAMBUF(fs); res = follow_path(&djo, path_old); /* Check old object */ - if (res == FR_OK && (djo.fn[NSFLAG] & (NS_DOT | NS_NONAME))) res = FR_INVALID_NAME; /* Check validity of name */ + if (res == FR_OK && (djo.fn[NSFLAG] & (NS_DOT | NS_NONAME))) { + res = FR_INVALID_NAME; /* Check validity of name */ + } #if FF_FS_LOCK if (res == FR_OK) { res = chk_share(&djo, 2); @@ -5241,17 +6234,22 @@ FRESULT f_rename ( if (res == FR_NO_FILE) { /* It is a valid path and no name collision */ res = dir_register(&djn); /* Register the new entry */ if (res == FR_OK) { - nf = fs->dirbuf[XDIR_NumSec]; nn = fs->dirbuf[XDIR_NumName]; + nf = fs->dirbuf[XDIR_NumSec]; + nn = fs->dirbuf[XDIR_NumName]; nh = ld_word(fs->dirbuf + XDIR_NameHash); mem_cpy(fs->dirbuf, buf, SZDIRE * 2); /* Restore 85+C0 entry */ - fs->dirbuf[XDIR_NumSec] = nf; fs->dirbuf[XDIR_NumName] = nn; + fs->dirbuf[XDIR_NumSec] = nf; + fs->dirbuf[XDIR_NumName] = nn; st_word(fs->dirbuf + XDIR_NameHash, nh); - if (!(fs->dirbuf[XDIR_Attr] & AM_DIR)) fs->dirbuf[XDIR_Attr] |= AM_ARC; /* Set archive attribute if it is a file */ -/* Start of critical section where an interruption can cause a cross-link */ + if (!(fs->dirbuf[XDIR_Attr] & AM_DIR)) { + fs->dirbuf[XDIR_Attr] |= AM_ARC; /* Set archive attribute if it is a file */ + } + /* Start of critical section where an interruption can cause a cross-link */ res = store_xdir(&djn); } } - } else + } + else #endif { /* At FAT/FAT32 volume */ mem_cpy(buf, djo.dir, SZDIRE); /* Save directory entry of the object */ @@ -5266,14 +6264,17 @@ FRESULT f_rename ( dir = djn.dir; /* Copy directory entry of the object except name */ mem_cpy(dir + 13, buf + 13, SZDIRE - 13); dir[DIR_Attr] = buf[DIR_Attr]; - if (!(dir[DIR_Attr] & AM_DIR)) dir[DIR_Attr] |= AM_ARC; /* Set archive attribute if it is a file */ + if (!(dir[DIR_Attr] & AM_DIR)) { + dir[DIR_Attr] |= AM_ARC; /* Set archive attribute if it is a file */ + } fs->wflag = 1; if ((dir[DIR_Attr] & AM_DIR) && djo.obj.sclust != djn.obj.sclust) { /* Update .. entry in the sub-directory if needed */ sect = clst2sect(fs, ld_clust(fs, dir)); if (sect == 0) { res = FR_INT_ERR; - } else { -/* Start of critical section where an interruption can cause a cross-link */ + } + else { + /* Start of critical section where an interruption can cause a cross-link */ res = move_window(fs, sect); dir = fs->win + SZDIRE * 1; /* Ptr to .. entry */ if (res == FR_OK && dir[1] == '.') { @@ -5291,7 +6292,7 @@ FRESULT f_rename ( res = sync_fs(fs); } } -/* End of the critical section */ + /* End of the critical section */ } FREE_NAMBUF(); } @@ -5312,7 +6313,7 @@ FRESULT f_rename ( /*-----------------------------------------------------------------------*/ FRESULT f_chmod ( - const TCHAR* path, /* Pointer to the file path */ + const TCHAR *path, /* Pointer to the file path */ BYTE attr, /* Attribute bits */ BYTE mask /* Attribute mask to change */ ) @@ -5328,14 +6329,17 @@ FRESULT f_chmod ( dj.obj.fs = fs; INIT_NAMBUF(fs); res = follow_path(&dj, path); /* Follow the file path */ - if (res == FR_OK && (dj.fn[NSFLAG] & (NS_DOT | NS_NONAME))) res = FR_INVALID_NAME; /* Check object validity */ + if (res == FR_OK && (dj.fn[NSFLAG] & (NS_DOT | NS_NONAME))) { + res = FR_INVALID_NAME; /* Check object validity */ + } if (res == FR_OK) { - mask &= AM_RDO|AM_HID|AM_SYS|AM_ARC; /* Valid attribute mask */ + mask &= AM_RDO | AM_HID | AM_SYS | AM_ARC; /* Valid attribute mask */ #if FF_FS_EXFAT if (fs->fs_type == FS_EXFAT) { fs->dirbuf[XDIR_Attr] = (attr & mask) | (fs->dirbuf[XDIR_Attr] & (BYTE)~mask); /* Apply attribute change */ res = store_xdir(&dj); - } else + } + else #endif { dj.dir[DIR_Attr] = (attr & mask) | (dj.dir[DIR_Attr] & (BYTE)~mask); /* Apply attribute change */ @@ -5359,8 +6363,8 @@ FRESULT f_chmod ( /*-----------------------------------------------------------------------*/ FRESULT f_utime ( - const TCHAR* path, /* Pointer to the file/directory name */ - const FILINFO* fno /* Pointer to the timestamp to be set */ + const TCHAR *path, /* Pointer to the file/directory name */ + const FILINFO *fno /* Pointer to the timestamp to be set */ ) { FRESULT res = FR_DISK_ERR; @@ -5374,13 +6378,16 @@ FRESULT f_utime ( dj.obj.fs = fs; INIT_NAMBUF(fs); res = follow_path(&dj, path); /* Follow the file path */ - if (res == FR_OK && (dj.fn[NSFLAG] & (NS_DOT | NS_NONAME))) res = FR_INVALID_NAME; /* Check object validity */ + if (res == FR_OK && (dj.fn[NSFLAG] & (NS_DOT | NS_NONAME))) { + res = FR_INVALID_NAME; /* Check object validity */ + } if (res == FR_OK) { #if FF_FS_EXFAT if (fs->fs_type == FS_EXFAT) { st_dword(fs->dirbuf + XDIR_ModTime, (DWORD)fno->fdate << 16 | fno->ftime); res = store_xdir(&dj); - } else + } + else #endif { st_dword(dj.dir + DIR_ModTime, (DWORD)fno->fdate << 16 | fno->ftime); @@ -5406,9 +6413,9 @@ FRESULT f_utime ( /*-----------------------------------------------------------------------*/ FRESULT f_getlabel ( - const TCHAR* path, /* Logical drive number */ - TCHAR* label, /* Buffer to store the volume label */ - DWORD* vsn /* Variable to store the volume serial number */ + const TCHAR *path, /* Logical drive number */ + TCHAR *label, /* Buffer to store the volume label */ + DWORD *vsn /* Variable to store the volume serial number */ ) { FRESULT res = FR_DISK_ERR; @@ -5422,7 +6429,8 @@ FRESULT f_getlabel ( /* Get volume label */ if (res == FR_OK && label) { - dj.obj.fs = fs; dj.obj.sclust = 0; /* Open root directory */ + dj.obj.fs = fs; + dj.obj.sclust = 0; /* Open root directory */ res = dir_sdi(&dj, 0); if (res == FR_OK) { res = DIR_READ_LABEL(&dj); /* Find a volume label entry */ @@ -5435,28 +6443,36 @@ FRESULT f_getlabel ( for (si = di = hs = 0; si < dj.dir[XDIR_NumLabel]; si++) { /* Extract volume label from 83 entry */ wc = ld_word(dj.dir + XDIR_Label + si * 2); if (hs == 0 && IsSurrogate(wc)) { /* Is the code a surrogate? */ - hs = wc; continue; + hs = wc; + continue; } nw = put_utf((DWORD)hs << 16 | wc, &label[di], 4); /* Store it in API encoding */ if (nw == 0) { /* Encode error? */ - di = 0; break; + di = 0; + break; } di += nw; hs = 0; } - if (hs != 0) di = 0; /* Broken surrogate pair? */ + if (hs != 0) { + di = 0; /* Broken surrogate pair? */ + } label[di] = 0; - } else + } + else #endif { si = di = 0; /* Extract volume label from AM_VOL entry */ while (si < 11) { wc = dj.dir[si++]; #if FF_USE_LFN && FF_LFN_UNICODE >= 1 /* Unicode output */ - if (dbc_1st((BYTE)wc) && si < 11) wc = wc << 8 | dj.dir[si++]; /* Is it a DBC? */ + if (dbc_1st((BYTE)wc) && si < 11) { + wc = wc << 8 | dj.dir[si++]; /* Is it a DBC? */ + } wc = ff_oem2uni(wc, CODEPAGE); /* Convert it into Unicode */ if (wc == 0) { /* Invalid char in current code page? */ - di = 0; break; + di = 0; + break; } di += put_utf(wc, &label[di], 4); /* Store it in Unicode */ #else /* ANSI/OEM output */ @@ -5465,8 +6481,11 @@ FRESULT f_getlabel ( } do { /* Truncate trailing spaces */ label[di] = 0; - if (di == 0) break; - } while (label[--di] == ' '); + if (di == 0) { + break; + } + } + while (label[--di] == ' '); } } } @@ -5481,16 +6500,16 @@ FRESULT f_getlabel ( res = move_window(fs, fs->volbase); if (res == FR_OK) { switch (fs->fs_type) { - case FS_EXFAT: - di = BPB_VolIDEx; - break; + case FS_EXFAT: + di = BPB_VolIDEx; + break; - case FS_FAT32: - di = BS_VolID32; - break; + case FS_FAT32: + di = BS_VolID32; + break; - default: - di = BS_VolID; + default: + di = BS_VolID; } *vsn = ld_dword(fs->win + di); } @@ -5507,7 +6526,7 @@ FRESULT f_getlabel ( /*-----------------------------------------------------------------------*/ FRESULT f_setlabel ( - const TCHAR* label /* Volume label to set with heading logical drive number */ + const TCHAR *label /* Volume label to set with heading logical drive number */ ) { FRESULT res = FR_DISK_ERR; @@ -5523,7 +6542,12 @@ FRESULT f_setlabel ( /* Get logical drive */ res = mount_volume(&label, &fs, FA_WRITE); - if (res != FR_OK) LEAVE_FF(fs, res); + if (res != FR_OK) { + LEAVE_FF(fs, res); + } +#if FF_STR_VOLUME_ID == 2 + for ( ; *label == '/'; label++) ; /* Snip the separators off */ +#endif #if FF_FS_EXFAT if (fs->fs_type == FS_EXFAT) { /* On the exFAT volume */ @@ -5534,16 +6558,20 @@ FRESULT f_setlabel ( if (dc >= 0x10000) { if (dc == 0xFFFFFFFF || di >= 10) { /* Wrong surrogate or buffer overflow */ dc = 0; - } else { - st_word(dirvn + di * 2, (WCHAR)(dc >> 16)); di++; + } + else { + st_word(dirvn + di * 2, (WCHAR)(dc >> 16)); + di++; } } if (dc == 0 || strchr(&badchr[7], (int)dc) || di >= 11) { /* Check validity of the volume label */ LEAVE_FF(fs, FR_INVALID_NAME); } - st_word(dirvn + di * 2, (WCHAR)dc); di++; + st_word(dirvn + di * 2, (WCHAR)dc); + di++; } - } else + } + else #endif { /* On the FAT/FAT32 volume */ memset(dirvn, ' ', 11); @@ -5553,27 +6581,43 @@ FRESULT f_setlabel ( dc = tchar2uni(&label); wc = (dc < 0x10000) ? ff_uni2oem(ff_wtoupper(dc), CODEPAGE) : 0; #else /* ANSI/OEM input */ - wc = (BYTE)*label++; - if (dbc_1st((BYTE)wc)) wc = dbc_2nd((BYTE)*label) ? wc << 8 | (BYTE)*label++ : 0; - if (IsLower(wc)) wc -= 0x20; /* To upper ASCII characters */ + wc = (BYTE) * label++; + if (dbc_1st((BYTE)wc)) { + wc = dbc_2nd((BYTE) * label) ? wc << 8 | (BYTE) * label++ : 0; + } + if (IsLower(wc)) { + wc -= 0x20; /* To upper ASCII characters */ + } #if FF_CODE_PAGE == 0 - if (ExCvt && wc >= 0x80) wc = ExCvt[wc - 0x80]; /* To upper extended characters (SBCS cfg) */ + if (ExCvt && wc >= 0x80) { + wc = ExCvt[wc - 0x80]; /* To upper extended characters (SBCS cfg) */ + } #elif FF_CODE_PAGE < 900 - if (wc >= 0x80) wc = ExCvt[wc - 0x80]; /* To upper extended characters (SBCS cfg) */ + if (wc >= 0x80) { + wc = ExCvt[wc - 0x80]; /* To upper extended characters (SBCS cfg) */ + } #endif #endif - if (wc == 0 || strchr(&badchr[0], (int)wc) || di >= (UINT)((wc >= 0x100) ? 10 : 11)) { /* Reject invalid characters for volume label */ + if (wc == 0 || strchr(&badchr[0], (int)wc) + || di >= (UINT)((wc >= 0x100) ? 10 : 11)) { /* Reject invalid characters for volume label */ LEAVE_FF(fs, FR_INVALID_NAME); } - if (wc >= 0x100) dirvn[di++] = (BYTE)(wc >> 8); + if (wc >= 0x100) { + dirvn[di++] = (BYTE)(wc >> 8); + } dirvn[di++] = (BYTE)wc; } - if (dirvn[0] == DDEM) LEAVE_FF(fs, FR_INVALID_NAME); /* Reject illegal name (heading DDEM) */ - while (di && dirvn[di - 1] == ' ') di--; /* Snip trailing spaces */ + if (dirvn[0] == DDEM) { + LEAVE_FF(fs, FR_INVALID_NAME); /* Reject illegal name (heading DDEM) */ + } + while (di && dirvn[di - 1] == ' ') { + di--; /* Snip trailing spaces */ + } } /* Set volume label */ - dj.obj.fs = fs; dj.obj.sclust = 0; /* Open root directory */ + dj.obj.fs = fs; + dj.obj.sclust = 0; /* Open root directory */ res = dir_sdi(&dj, 0); if (res == FR_OK) { res = DIR_READ_LABEL(&dj); /* Get volume label entry */ @@ -5581,16 +6625,19 @@ FRESULT f_setlabel ( if (FF_FS_EXFAT && fs->fs_type == FS_EXFAT) { dj.dir[XDIR_NumLabel] = (BYTE)di; /* Change the volume label */ mem_cpy(dj.dir + XDIR_Label, dirvn, 22); - } else { + } + else { if (di != 0) { mem_cpy(dj.dir, dirvn, 11); /* Change the volume label */ - } else { + } + else { dj.dir[DIR_Name] = DDEM; /* Remove the volume label */ } } fs->wflag = 1; res = sync_fs(fs); - } else { /* No volume label entry or an error */ + } + else { /* No volume label entry or an error */ if (res == FR_NO_FILE) { res = FR_OK; if (di != 0) { /* Create a volume label entry */ @@ -5601,7 +6648,8 @@ FRESULT f_setlabel ( dj.dir[XDIR_Type] = ET_VLABEL; /* Create volume label entry */ dj.dir[XDIR_NumLabel] = (BYTE)di; mem_cpy(dj.dir + XDIR_Label, dirvn, 22); - } else { + } + else { dj.dir[DIR_Attr] = AM_VOL; /* Create volume label entry */ mem_cpy(dj.dir, dirvn, 11); } @@ -5627,7 +6675,7 @@ FRESULT f_setlabel ( /*-----------------------------------------------------------------------*/ FRESULT f_expand ( - FIL* fp, /* Pointer to the file object */ + FIL *fp, /* Pointer to the file object */ FSIZE_t fsz, /* File size to be expanded to */ BYTE opt /* Operation mode 0:Find and prepare or 1:Find and allocate */ ) @@ -5638,59 +6686,87 @@ FRESULT f_expand ( res = validate(&fp->obj, &fs); /* Check validity of the file object */ - if (res != FR_OK || (res = (FRESULT)fp->err) != FR_OK) LEAVE_FF(fs, res); - if (fsz == 0 || fp->obj.objsize != 0 || !(fp->flag & FA_WRITE)) LEAVE_FF(fs, FR_DENIED); + if (res != FR_OK || (res = (FRESULT)fp->err) != FR_OK) { + LEAVE_FF(fs, res); + } + if (fsz == 0 || fp->obj.objsize != 0 || !(fp->flag & FA_WRITE)) { + LEAVE_FF(fs, FR_DENIED); + } #if FF_FS_EXFAT - if (fs->fs_type != FS_EXFAT && fsz >= 0x100000000) LEAVE_FF(fs, FR_DENIED); /* Check if in size limit */ + if (fs->fs_type != FS_EXFAT && fsz >= 0x100000000) { + LEAVE_FF(fs, FR_DENIED); /* Check if in size limit */ + } #endif n = (DWORD)fs->csize * SS(fs); /* Cluster size */ tcl = (DWORD)(fsz / n) + ((fsz & (n - 1)) ? 1 : 0); /* Number of clusters required */ - stcl = fs->last_clst; lclst = 0; - if (stcl < 2 || stcl >= fs->n_fatent) stcl = 2; + stcl = fs->last_clst; + lclst = 0; + if (stcl < 2 || stcl >= fs->n_fatent) { + stcl = 2; + } #if FF_FS_EXFAT if (fs->fs_type == FS_EXFAT) { scl = find_bitmap(fs, stcl, tcl); /* Find a contiguous cluster block */ - if (scl == 0) res = FR_DENIED; /* No contiguous cluster block was found */ - if (scl == 0xFFFFFFFF) res = FR_DISK_ERR; + if (scl == 0) { + res = FR_DENIED; /* No contiguous cluster block was found */ + } + if (scl == 0xFFFFFFFF) { + res = FR_DISK_ERR; + } if (res == FR_OK) { /* A contiguous free area is found */ if (opt) { /* Allocate it now */ res = change_bitmap(fs, scl, tcl, 1); /* Mark the cluster block 'in use' */ lclst = scl + tcl - 1; - } else { /* Set it as suggested point for next allocation */ + } + else { /* Set it as suggested point for next allocation */ lclst = scl - 1; } } - } else + } + else #endif { - scl = clst = stcl; ncl = 0; + scl = clst = stcl; + ncl = 0; for (;;) { /* Find a contiguous cluster block */ n = get_fat(&fp->obj, clst); - if (++clst >= fs->n_fatent) clst = 2; + if (++clst >= fs->n_fatent) { + clst = 2; + } if (n == 1) { - res = FR_INT_ERR; break; + res = FR_INT_ERR; + break; } if (n == 0xFFFFFFFF) { - res = FR_DISK_ERR; break; + res = FR_DISK_ERR; + break; } if (n == 0) { /* Is it a free cluster? */ - if (++ncl == tcl) break; /* Break if a contiguous cluster block is found */ - } else { - scl = clst; ncl = 0; /* Not a free cluster */ + if (++ncl == tcl) { + break; /* Break if a contiguous cluster block is found */ + } + } + else { + scl = clst; + ncl = 0; /* Not a free cluster */ } if (clst == stcl) { /* No contiguous cluster? */ - res = FR_DENIED; break; + res = FR_DENIED; + break; } } if (res == FR_OK) { /* A contiguous free area is found */ if (opt) { /* Allocate it now */ for (clst = scl, n = tcl; n; clst++, n--) { /* Create a cluster chain on the FAT */ res = put_fat(fs, clst, (n == 1) ? 0xFFFFFFFF : clst + 1); - if (res != FR_OK) break; + if (res != FR_OK) { + break; + } lclst = clst; } - } else { /* Set it as suggested point for next allocation */ + } + else { /* Set it as suggested point for next allocation */ lclst = scl - 1; } } @@ -5701,7 +6777,9 @@ FRESULT f_expand ( if (opt) { /* Is it allocated now? */ fp->obj.sclust = scl; /* Update object allocation information */ fp->obj.objsize = fsz; - if (FF_FS_EXFAT) fp->obj.stat = 2; /* Set status 'contiguous chain' */ + if (FF_FS_EXFAT) { + fp->obj.stat = 2; /* Set status 'contiguous chain' */ + } fp->flag |= FA_MODIFIED; if (fs->free_clst <= fs->n_fatent - 2) { /* Update FSINFO */ fs->free_clst -= tcl; @@ -5723,10 +6801,10 @@ FRESULT f_expand ( /*-----------------------------------------------------------------------*/ FRESULT f_forward ( - FIL* fp, /* Pointer to the file object */ - UINT (*func)(const BYTE*,UINT), /* Pointer to the streaming function */ + FIL *fp, /* Pointer to the file object */ + UINT (*func)(const BYTE *, UINT), /* Pointer to the streaming function */ UINT btf, /* Number of bytes to forward */ - UINT* bf /* Pointer to number of bytes forwarded */ + UINT *bf /* Pointer to number of bytes forwarded */ ) { FRESULT res = FR_DISK_ERR; @@ -5740,46 +6818,69 @@ FRESULT f_forward ( *bf = 0; /* Clear transfer byte counter */ res = validate(&fp->obj, &fs); /* Check validity of the file object */ - if (res != FR_OK || (res = (FRESULT)fp->err) != FR_OK) LEAVE_FF(fs, res); - if (!(fp->flag & FA_READ)) LEAVE_FF(fs, FR_DENIED); /* Check access mode */ + if (res != FR_OK || (res = (FRESULT)fp->err) != FR_OK) { + LEAVE_FF(fs, res); + } + if (!(fp->flag & FA_READ)) { + LEAVE_FF(fs, FR_DENIED); /* Check access mode */ + } remain = fp->obj.objsize - fp->fptr; - if (btf > remain) btf = (UINT)remain; /* Truncate btf by remaining bytes */ + if (btf > remain) { + btf = (UINT)remain; /* Truncate btf by remaining bytes */ + } - for ( ; btf > 0 && (*func)(0, 0); fp->fptr += rcnt, *bf += rcnt, btf -= rcnt) { /* Repeat until all data transferred or stream goes busy */ + for ( ; btf > 0 + && (*func)(0, 0); fp->fptr += rcnt, *bf += rcnt, btf -= rcnt) { /* Repeat until all data transferred or stream goes busy */ csect = (UINT)(fp->fptr / SS(fs) & (fs->csize - 1)); /* Sector offset in the cluster */ if (fp->fptr % SS(fs) == 0) { /* On the sector boundary? */ if (csect == 0) { /* On the cluster boundary? */ clst = (fp->fptr == 0) ? /* On the top of the file? */ - fp->obj.sclust : get_fat(&fp->obj, fp->clust); - if (clst <= 1) ABORT(fs, FR_INT_ERR); - if (clst == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR); + fp->obj.sclust : get_fat(&fp->obj, fp->clust); + if (clst <= 1) { + ABORT(fs, FR_INT_ERR); + } + if (clst == 0xFFFFFFFF) { + ABORT(fs, FR_DISK_ERR); + } fp->clust = clst; /* Update current cluster */ } } sect = clst2sect(fs, fp->clust); /* Get current data sector */ - if (sect == 0) ABORT(fs, FR_INT_ERR); + if (sect == 0) { + ABORT(fs, FR_INT_ERR); + } sect += csect; #if FF_FS_TINY - if (move_window(fs, sect) != FR_OK) ABORT(fs, FR_DISK_ERR); /* Move sector window to the file data */ + if (move_window(fs, sect) != FR_OK) { + ABORT(fs, FR_DISK_ERR); /* Move sector window to the file data */ + } dbuf = fs->win; #else if (fp->sect != sect) { /* Fill sector cache with file data */ #if !FF_FS_READONLY if (fp->flag & FA_DIRTY) { /* Write-back dirty sector cache */ - if (disk_write(fs->pdrv, fp->buf, fp->sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR); + if (disk_write(fs->pdrv, fp->buf, fp->sect, 1) != RES_OK) { + ABORT(fs, FR_DISK_ERR); + } fp->flag &= (BYTE)~FA_DIRTY; } #endif - if (disk_read(fs->pdrv, fp->buf, sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR); + if (disk_read(fs->pdrv, fp->buf, sect, 1) != RES_OK) { + ABORT(fs, FR_DISK_ERR); + } } dbuf = fp->buf; #endif fp->sect = sect; rcnt = SS(fs) - (UINT)fp->fptr % SS(fs); /* Number of bytes remains in the sector */ - if (rcnt > btf) rcnt = btf; /* Clip it by btr if needed */ + if (rcnt > btf) { + rcnt = btf; /* Clip it by btr if needed */ + } rcnt = (*func)(dbuf + ((UINT)fp->fptr % SS(fs)), rcnt); /* Forward the file data */ - if (rcnt == 0) ABORT(fs, FR_INT_ERR); + if (rcnt == 0) { + ABORT(fs, FR_INT_ERR); + } } LEAVE_FF(fs, FR_OK); @@ -5814,7 +6915,9 @@ static FRESULT create_partition ( BYTE hd, n_hd, sc, n_sc; /* Get physical drive size */ - if (disk_ioctl(drv, GET_SECTOR_COUNT, &sz_drv) != RES_OK) return FR_DISK_ERR; + if (disk_ioctl(drv, GET_SECTOR_COUNT, &sz_drv) != RES_OK) { + return FR_DISK_ERR; + } #if FF_LBA64 if (sz_drv >= FF_MIN_GPT) { /* Create partitions in GPT format */ @@ -5825,8 +6928,12 @@ static FRESULT create_partition ( static const BYTE gpt_mbr[16] = {0x00, 0x00, 0x02, 0x00, 0xEE, 0xFE, 0xFF, 0x00, 0x01, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF}; #if FF_MAX_SS != FF_MIN_SS - if (disk_ioctl(drv, GET_SECTOR_SIZE, &ss) != RES_OK) return FR_DISK_ERR; /* Get sector size */ - if (ss > FF_MAX_SS || ss < FF_MIN_SS || (ss & (ss - 1))) return FR_DISK_ERR; + if (disk_ioctl(drv, GET_SECTOR_SIZE, &ss) != RES_OK) { + return FR_DISK_ERR; /* Get sector size */ + } + if (ss > FF_MAX_SS || ss < FF_MIN_SS || (ss & (ss - 1))) { + return FR_DISK_ERR; + } #else ss = FF_MAX_SS; #endif @@ -5836,10 +6943,13 @@ static FRESULT create_partition ( top_bpt = sz_drv - sz_ptbl - 1; /* Backup partition table start sector */ nxt_alloc = 2 + sz_ptbl; /* First allocatable sector */ sz_pool = top_bpt - nxt_alloc; /* Size of allocatable area */ - bcc = 0xFFFFFFFF; sz_part = 1; + bcc = 0xFFFFFFFF; + sz_part = 1; pi = si = 0; /* partition table index, size table index */ do { - if (pi * SZ_GPTE % ss == 0) memset(buf, 0, ss); /* Clean the buffer if needed */ + if (pi * SZ_GPTE % ss == 0) { + memset(buf, 0, ss); /* Clean the buffer if needed */ + } if (sz_part != 0) { /* Is the size table not termintated? */ nxt_alloc = (nxt_alloc + align - 1) & ((QWORD)0 - align); /* Align partition start */ sz_part = plst[si++]; /* Get a partition size */ @@ -5861,10 +6971,15 @@ static FRESULT create_partition ( } if ((pi + 1) * SZ_GPTE % ss == 0) { /* Write the buffer if it is filled up */ for (i = 0; i < ss; bcc = crc32(bcc, buf[i++])) ; /* Calculate table check sum */ - if (disk_write(drv, buf, 2 + pi * SZ_GPTE / ss, 1) != RES_OK) return FR_DISK_ERR; /* Write to primary table */ - if (disk_write(drv, buf, top_bpt + pi * SZ_GPTE / ss, 1) != RES_OK) return FR_DISK_ERR; /* Write to secondary table */ + if (disk_write(drv, buf, 2 + pi * SZ_GPTE / ss, 1) != RES_OK) { + return FR_DISK_ERR; /* Write to primary table */ + } + if (disk_write(drv, buf, top_bpt + pi * SZ_GPTE / ss, 1) != RES_OK) { + return FR_DISK_ERR; /* Write to secondary table */ + } } - } while (++pi < GPT_ITEMS); + } + while (++pi < GPT_ITEMS); /* Create primary GPT header */ memset(buf, 0, ss); @@ -5878,40 +6993,55 @@ static FRESULT create_partition ( st_dword(buf + GPTH_PtNum, GPT_ITEMS); /* Number of table entries */ st_dword(buf + GPTH_PtOfs, 2); /* LBA of this table */ rnd = make_rand(rnd, buf + GPTH_DskGuid, 16); /* Disk GUID */ - for (i = 0, bcc= 0xFFFFFFFF; i < 92; bcc = crc32(bcc, buf[i++])) ; /* Calculate header check sum */ + for (i = 0, bcc = 0xFFFFFFFF; i < 92; bcc = crc32(bcc, buf[i++])) ; /* Calculate header check sum */ st_dword(buf + GPTH_Bcc, ~bcc); /* Header check sum */ - if (disk_write(drv, buf, 1, 1) != RES_OK) return FR_DISK_ERR; + if (disk_write(drv, buf, 1, 1) != RES_OK) { + return FR_DISK_ERR; + } /* Create secondary GPT header */ st_qword(buf + GPTH_CurLba, sz_drv - 1); /* LBA of this header */ st_qword(buf + GPTH_BakLba, 1); /* LBA of primary header */ st_qword(buf + GPTH_PtOfs, top_bpt); /* LBA of this table */ st_dword(buf + GPTH_Bcc, 0); - for (i = 0, bcc= 0xFFFFFFFF; i < 92; bcc = crc32(bcc, buf[i++])) ; /* Calculate header check sum */ + for (i = 0, bcc = 0xFFFFFFFF; i < 92; bcc = crc32(bcc, buf[i++])) ; /* Calculate header check sum */ st_dword(buf + GPTH_Bcc, ~bcc); /* Header check sum */ - if (disk_write(drv, buf, sz_drv - 1, 1) != RES_OK) return FR_DISK_ERR; + if (disk_write(drv, buf, sz_drv - 1, 1) != RES_OK) { + return FR_DISK_ERR; + } /* Create protective MBR */ memset(buf, 0, ss); mem_cpy(buf + MBR_Table, gpt_mbr, 16); /* Create a GPT partition */ st_word(buf + BS_55AA, 0xAA55); - if (disk_write(drv, buf, 0, 1) != RES_OK) return FR_DISK_ERR; + if (disk_write(drv, buf, 0, 1) != RES_OK) { + return FR_DISK_ERR; + } - } else + } + else #endif { /* Create partitions in MBR format */ sz_drv32 = (DWORD)sz_drv; n_sc = N_SEC_TRACK; /* Determine drive CHS without any consideration of the drive geometry */ for (n_hd = 8; n_hd != 0 && sz_drv32 / n_hd / n_sc > 1024; n_hd *= 2) ; - if (n_hd == 0) n_hd = 255; /* Number of heads needs to be <256 */ + if (n_hd == 0) { + n_hd = 255; /* Number of heads needs to be <256 */ + } memset(buf, 0, FF_MAX_SS); /* Clear MBR */ pte = buf + MBR_Table; /* Partition table in the MBR */ for (i = 0, nxt_alloc32 = n_sc; i < 4 && nxt_alloc32 != 0 && nxt_alloc32 < sz_drv32; i++, nxt_alloc32 += sz_part32) { sz_part32 = (DWORD)plst[i]; /* Get partition size */ - if (sz_part32 <= 100) sz_part32 = (sz_part32 == 100) ? sz_drv32 : sz_drv32 / 100 * sz_part32; /* Size in percentage? */ - if (nxt_alloc32 + sz_part32 > sz_drv32 || nxt_alloc32 + sz_part32 < nxt_alloc32) sz_part32 = sz_drv32 - nxt_alloc32; /* Clip at drive size */ - if (sz_part32 == 0) break; /* End of table or no sector to allocate? */ + if (sz_part32 <= 100) { + sz_part32 = (sz_part32 == 100) ? sz_drv32 : sz_drv32 / 100 * sz_part32; /* Size in percentage? */ + } + if (nxt_alloc32 + sz_part32 > sz_drv32 || nxt_alloc32 + sz_part32 < nxt_alloc32) { + sz_part32 = sz_drv32 - nxt_alloc32; /* Clip at drive size */ + } + if (sz_part32 == 0) { + break; /* End of table or no sector to allocate? */ + } st_dword(pte + PTE_StLba, nxt_alloc32); /* Start LBA */ st_dword(pte + PTE_SizLba, sz_part32); /* Number of sectors */ @@ -5935,7 +7065,9 @@ static FRESULT create_partition ( } st_word(buf + BS_55AA, 0xAA55); /* MBR signature */ - if (disk_write(drv, buf, 0, 1) != RES_OK) return FR_DISK_ERR; /* Write it to the MBR */ + if (disk_write(drv, buf, 0, 1) != RES_OK) { + return FR_DISK_ERR; /* Write it to the MBR */ + } } return FR_OK; @@ -5944,9 +7076,9 @@ static FRESULT create_partition ( FRESULT f_mkfs ( - const TCHAR* path, /* Logical drive number */ - const MKFS_PARM* opt, /* Format options */ - void* work, /* Pointer to working buffer (null: use len bytes of heap memory) */ + const TCHAR *path, /* Logical drive number */ + const MKFS_PARM *opt, /* Format options */ + void *work, /* Pointer to working buffer (null: use len bytes of heap memory) */ UINT len /* Size of working buffer [byte] */ ) { @@ -5969,24 +7101,42 @@ FRESULT f_mkfs ( /* Check mounted drive and clear work area */ vol = get_ldnumber(&path); /* Get target logical drive */ - if (vol < 0) return FR_INVALID_DRIVE; - if (FatFs[vol]) FatFs[vol]->fs_type = 0; /* Clear the fs object if mounted */ + if (vol < 0) { + return FR_INVALID_DRIVE; + } + if (FatFs[vol]) { + FatFs[vol]->fs_type = 0; /* Clear the fs object if mounted */ + } pdrv = LD2PD(vol); /* Hosting physical drive */ ipart = LD2PT(vol); /* Hosting partition (0:create as new, 1..:existing partition) */ /* Initialize the hosting physical drive */ ds = disk_initialize(pdrv); - if (ds & STA_NOINIT) return FR_NOT_READY; - if (ds & STA_PROTECT) return FR_WRITE_PROTECTED; + if (ds & STA_NOINIT) { + return FR_NOT_READY; + } + if (ds & STA_PROTECT) { + return FR_WRITE_PROTECTED; + } /* Get physical drive parameters (sz_drv, sz_blk and ss) */ - if (!opt) opt = &defopt; /* Use default parameter if it is not given */ + if (!opt) { + opt = &defopt; /* Use default parameter if it is not given */ + } sz_blk = opt->align; - if (sz_blk == 0) disk_ioctl(pdrv, GET_BLOCK_SIZE, &sz_blk); /* Block size from the paramter or lower layer */ - if (sz_blk == 0 || sz_blk > 0x8000 || (sz_blk & (sz_blk - 1))) sz_blk = 1; /* Use default if the block size is invalid */ + if (sz_blk == 0) { + disk_ioctl(pdrv, GET_BLOCK_SIZE, &sz_blk); /* Block size from the paramter or lower layer */ + } + if (sz_blk == 0 || sz_blk > 0x8000 || (sz_blk & (sz_blk - 1))) { + sz_blk = 1; /* Use default if the block size is invalid */ + } #if FF_MAX_SS != FF_MIN_SS - if (disk_ioctl(pdrv, GET_SECTOR_SIZE, &ss) != RES_OK) return FR_DISK_ERR; - if (ss > FF_MAX_SS || ss < FF_MIN_SS || (ss & (ss - 1))) return FR_DISK_ERR; + if (disk_ioctl(pdrv, GET_SECTOR_SIZE, &ss) != RES_OK) { + return FR_DISK_ERR; + } + if (ss > FF_MAX_SS || ss < FF_MIN_SS || (ss & (ss - 1))) { + return FR_DISK_ERR; + } #else ss = FF_MAX_SS; #endif @@ -6000,88 +7150,128 @@ FRESULT f_mkfs ( /* Get working buffer */ sz_buf = len / ss; /* Size of working buffer [sector] */ - if (sz_buf == 0) return FR_NOT_ENOUGH_CORE; - buf = (BYTE*)work; /* Working buffer */ + if (sz_buf == 0) { + return FR_NOT_ENOUGH_CORE; + } + buf = (BYTE *)work; /* Working buffer */ #if FF_USE_LFN == 3 - if (!buf) buf = ff_memalloc(sz_buf * ss); /* Use heap memory for working buffer */ + if (!buf) { + buf = ff_memalloc(sz_buf * ss); /* Use heap memory for working buffer */ + } #endif - if (!buf) return FR_NOT_ENOUGH_CORE; + if (!buf) { + return FR_NOT_ENOUGH_CORE; + } /* Determine where the volume to be located (b_vol, sz_vol) */ b_vol = sz_vol = 0; if (FF_MULTI_PARTITION && ipart != 0) { /* Is the volume associated with any specific partition? */ /* Get partition location from the existing partition table */ - if (disk_read(pdrv, buf, 0, 1) != RES_OK) LEAVE_MKFS(FR_DISK_ERR); /* Load MBR */ - if (ld_word(buf + BS_55AA) != 0xAA55) LEAVE_MKFS(FR_MKFS_ABORTED); /* Check if MBR is valid */ + if (disk_read(pdrv, buf, 0, 1) != RES_OK) { + LEAVE_MKFS(FR_DISK_ERR); /* Load MBR */ + } + if (ld_word(buf + BS_55AA) != 0xAA55) { + LEAVE_MKFS(FR_MKFS_ABORTED); /* Check if MBR is valid */ + } #if FF_LBA64 if (buf[MBR_Table + PTE_System] == 0xEE) { /* GPT protective MBR? */ DWORD n_ent, ofs; QWORD pt_lba; /* Get the partition location from GPT */ - if (disk_read(pdrv, buf, 1, 1) != RES_OK) LEAVE_MKFS(FR_DISK_ERR); /* Load GPT header sector (next to MBR) */ - if (!test_gpt_header(buf)) LEAVE_MKFS(FR_MKFS_ABORTED); /* Check if GPT header is valid */ + if (disk_read(pdrv, buf, 1, 1) != RES_OK) { + LEAVE_MKFS(FR_DISK_ERR); /* Load GPT header sector (next to MBR) */ + } + if (!test_gpt_header(buf)) { + LEAVE_MKFS(FR_MKFS_ABORTED); /* Check if GPT header is valid */ + } n_ent = ld_dword(buf + GPTH_PtNum); /* Number of entries */ pt_lba = ld_qword(buf + GPTH_PtOfs); /* Table start sector */ ofs = i = 0; while (n_ent) { /* Find MS Basic partition with order of ipart */ - if (ofs == 0 && disk_read(pdrv, buf, pt_lba++, 1) != RES_OK) LEAVE_MKFS(FR_DISK_ERR); /* Get PT sector */ + if (ofs == 0 && disk_read(pdrv, buf, pt_lba++, 1) != RES_OK) { + LEAVE_MKFS(FR_DISK_ERR); /* Get PT sector */ + } if (!memcmp(buf + ofs + GPTE_PtGuid, GUID_MS_Basic, 16) && ++i == ipart) { /* MS basic data partition? */ b_vol = ld_qword(buf + ofs + GPTE_FstLba); sz_vol = ld_qword(buf + ofs + GPTE_LstLba) - b_vol + 1; break; } - n_ent--; ofs = (ofs + SZ_GPTE) % ss; /* Next entry */ + n_ent--; + ofs = (ofs + SZ_GPTE) % ss; /* Next entry */ + } + if (n_ent == 0) { + LEAVE_MKFS(FR_MKFS_ABORTED); /* Partition not found */ } - if (n_ent == 0) LEAVE_MKFS(FR_MKFS_ABORTED); /* Partition not found */ fsopt |= 0x80; /* Partitioning is in GPT */ - } else + } + else #endif { /* Get the partition location from MBR partition table */ pte = buf + (MBR_Table + (ipart - 1) * SZ_PTE); - if (ipart > 4 || pte[PTE_System] == 0) LEAVE_MKFS(FR_MKFS_ABORTED); /* No partition? */ + if (ipart > 4 || pte[PTE_System] == 0) { + LEAVE_MKFS(FR_MKFS_ABORTED); /* No partition? */ + } b_vol = ld_dword(pte + PTE_StLba); /* Get volume start sector */ sz_vol = ld_dword(pte + PTE_SizLba); /* Get volume size */ } - } else { /* The volume is associated with a physical drive */ - if (disk_ioctl(pdrv, GET_SECTOR_COUNT, &sz_vol) != RES_OK) LEAVE_MKFS(FR_DISK_ERR); + } + else { /* The volume is associated with a physical drive */ + if (disk_ioctl(pdrv, GET_SECTOR_COUNT, &sz_vol) != RES_OK) { + LEAVE_MKFS(FR_DISK_ERR); + } if (!(fsopt & FM_SFD)) { /* To be partitioned? */ /* Create a single-partition on the drive in this function */ #if FF_LBA64 if (sz_vol >= FF_MIN_GPT) { /* Which partition type to create, MBR or GPT? */ fsopt |= 0x80; /* Partitioning is in GPT */ - b_vol = GPT_ALIGN / ss; sz_vol -= b_vol + GPT_ITEMS * SZ_GPTE / ss + 1; /* Estimated partition offset and size */ - } else + b_vol = GPT_ALIGN / ss; + sz_vol -= b_vol + GPT_ITEMS * SZ_GPTE / ss + 1; /* Estimated partition offset and size */ + } + else #endif { /* Partitioning is in MBR */ if (sz_vol > N_SEC_TRACK) { - b_vol = N_SEC_TRACK; sz_vol -= b_vol; /* Estimated partition offset and size */ + b_vol = N_SEC_TRACK; + sz_vol -= b_vol; /* Estimated partition offset and size */ } } } } - if (sz_vol < 128) LEAVE_MKFS(FR_MKFS_ABORTED); /* Check if volume size is >=128s */ + if (sz_vol < 128) { + LEAVE_MKFS(FR_MKFS_ABORTED); /* Check if volume size is >=128s */ + } /* Now start to create an FAT volume at b_vol and sz_vol */ do { /* Pre-determine the FAT type */ if (FF_FS_EXFAT && (fsopt & FM_EXFAT)) { /* exFAT possible? */ - if ((fsopt & FM_ANY) == FM_EXFAT || sz_vol >= 0x4000000 || sz_au > 128) { /* exFAT only, vol >= 64MS or sz_au > 128S ? */ - fsty = FS_EXFAT; break; + if ((fsopt & FM_ANY) == FM_EXFAT || sz_vol >= 0x4000000 + || sz_au > 128) { /* exFAT only, vol >= 64MS or sz_au > 128S ? */ + fsty = FS_EXFAT; + break; } } #if FF_LBA64 - if (sz_vol >= 0x100000000) LEAVE_MKFS(FR_MKFS_ABORTED); /* Too large volume for FAT/FAT32 */ + if (sz_vol >= 0x100000000) { + LEAVE_MKFS(FR_MKFS_ABORTED); /* Too large volume for FAT/FAT32 */ + } #endif - if (sz_au > 128) sz_au = 128; /* Invalid AU for FAT/FAT32? */ + if (sz_au > 128) { + sz_au = 128; /* Invalid AU for FAT/FAT32? */ + } if (fsopt & FM_FAT32) { /* FAT32 possible? */ if (!(fsopt & FM_FAT)) { /* no-FAT? */ - fsty = FS_FAT32; break; + fsty = FS_FAT32; + break; } } - if (!(fsopt & FM_FAT)) LEAVE_MKFS(FR_INVALID_PARAMETER); /* no-FAT? */ + if (!(fsopt & FM_FAT)) { + LEAVE_MKFS(FR_INVALID_PARAMETER); /* no-FAT? */ + } fsty = FS_FAT16; - } while (0); + } + while (0); vsn = (DWORD)sz_vol + GET_FATTIME(); /* VSN generated from current time and partitiion size */ @@ -6091,24 +7281,37 @@ FRESULT f_mkfs ( WCHAR ch, si; UINT j, st; - if (sz_vol < 0x1000) LEAVE_MKFS(FR_MKFS_ABORTED); /* Too small volume for exFAT? */ + if (sz_vol < 0x1000) { + LEAVE_MKFS(FR_MKFS_ABORTED); /* Too small volume for exFAT? */ + } #if FF_USE_TRIM - lba[0] = b_vol; lba[1] = b_vol + sz_vol - 1; /* Inform storage device that the volume area may be erased */ + lba[0] = b_vol; + lba[1] = b_vol + sz_vol - 1; /* Inform storage device that the volume area may be erased */ disk_ioctl(pdrv, CTRL_TRIM, lba); #endif /* Determine FAT location, data location and number of clusters */ if (sz_au == 0) { /* AU auto-selection */ sz_au = 8; - if (sz_vol >= 0x80000) sz_au = 64; /* >= 512Ks */ - if (sz_vol >= 0x4000000) sz_au = 256; /* >= 64Ms */ + if (sz_vol >= 0x80000) { + sz_au = 64; /* >= 512Ks */ + } + if (sz_vol >= 0x4000000) { + sz_au = 256; /* >= 64Ms */ + } } b_fat = b_vol + 32; /* FAT start at offset 32 */ sz_fat = (DWORD)((sz_vol / sz_au + 2) * 4 + ss - 1) / ss; /* Number of FAT sectors */ b_data = (b_fat + sz_fat + sz_blk - 1) & ~((LBA_t)sz_blk - 1); /* Align data area to the erase block boundary */ - if (b_data - b_vol >= sz_vol / 2) LEAVE_MKFS(FR_MKFS_ABORTED); /* Too small volume? */ + if (b_data - b_vol >= sz_vol / 2) { + LEAVE_MKFS(FR_MKFS_ABORTED); /* Too small volume? */ + } n_clst = (DWORD)((sz_vol - (b_data - b_vol)) / sz_au); /* Number of clusters */ - if (n_clst <16) LEAVE_MKFS(FR_MKFS_ABORTED); /* Too few clusters? */ - if (n_clst > MAX_EXFAT) LEAVE_MKFS(FR_MKFS_ABORTED); /* Too many clusters? */ + if (n_clst < 16) { + LEAVE_MKFS(FR_MKFS_ABORTED); /* Too few clusters? */ + } + if (n_clst > MAX_EXFAT) { + LEAVE_MKFS(FR_MKFS_ABORTED); /* Too many clusters? */ + } szb_bit = (n_clst + 7) / 8; /* Size of allocation bitmap */ clen[0] = (szb_bit + sz_au * ss - 1) / (sz_au * ss); /* Number of allocation bitmap clusters */ @@ -6116,74 +7319,112 @@ FRESULT f_mkfs ( /* Create a compressed up-case table */ sect = b_data + sz_au * clen[0]; /* Table start sector */ sum = 0; /* Table checksum to be stored in the 82 entry */ - st = 0; si = 0; i = 0; j = 0; szb_case = 0; + st = 0; + si = 0; + i = 0; + j = 0; + szb_case = 0; do { switch (st) { - case 0: - ch = (WCHAR)ff_wtoupper(si); /* Get an up-case char */ - if (ch != si) { - si++; break; /* Store the up-case char if exist */ - } - for (j = 1; (WCHAR)(si + j) && (WCHAR)(si + j) == ff_wtoupper((WCHAR)(si + j)); j++) ; /* Get run length of no-case block */ - if (j >= 128) { - ch = 0xFFFF; st = 2; break; /* Compress the no-case block if run is >= 128 chars */ - } - st = 1; /* Do not compress short run */ - ch = si++; /* Fill the short run */ - if (--j == 0) st = 0; - break; - case 1: - ch = si++; /* Fill the short run */ - if (--j == 0) st = 0; - break; + case 0: + ch = (WCHAR)ff_wtoupper(si); /* Get an up-case char */ + if (ch != si) { + si++; + break; /* Store the up-case char if exist */ + } + for (j = 1; (WCHAR)(si + j) + && (WCHAR)(si + j) == ff_wtoupper((WCHAR)(si + j)); j++) ; /* Get run length of no-case block */ + if (j >= 128) { + ch = 0xFFFF; + st = 2; + break; /* Compress the no-case block if run is >= 128 chars */ + } + st = 1; /* Do not compress short run */ + ch = si++; /* Fill the short run */ + if (--j == 0) { + st = 0; + } + break; + case 1: + ch = si++; /* Fill the short run */ + if (--j == 0) { + st = 0; + } + break; - default: - ch = (WCHAR)j; si += (WCHAR)j; /* Number of chars to skip */ - st = 0; + default: + ch = (WCHAR)j; + si += (WCHAR)j; /* Number of chars to skip */ + st = 0; } sum = xsum32(buf[i + 0] = (BYTE)ch, sum); /* Put it into the write buffer */ sum = xsum32(buf[i + 1] = (BYTE)(ch >> 8), sum); - i += 2; szb_case += 2; + i += 2; + szb_case += 2; if (si == 0 || i == sz_buf * ss) { /* Write buffered data when buffer full or end of process */ n = (i + ss - 1) / ss; - if (disk_write(pdrv, buf, sect, n) != RES_OK) LEAVE_MKFS(FR_DISK_ERR); - sect += n; i = 0; + if (disk_write(pdrv, buf, sect, n) != RES_OK) { + LEAVE_MKFS(FR_DISK_ERR); + } + sect += n; + i = 0; } - } while (si); + } + while (si); clen[1] = (szb_case + sz_au * ss - 1) / (sz_au * ss); /* Number of up-case table clusters */ clen[2] = 1; /* Number of root dir clusters */ /* Initialize the allocation bitmap */ - sect = b_data; nsect = (szb_bit + ss - 1) / ss; /* Start of bitmap and number of bitmap sectors */ + sect = b_data; + nsect = (szb_bit + ss - 1) / ss; /* Start of bitmap and number of bitmap sectors */ nbit = clen[0] + clen[1] + clen[2]; /* Number of clusters in-use by system (bitmap, up-case and root-dir) */ do { memset(buf, 0, sz_buf * ss); /* Initialize bitmap buffer */ for (i = 0; nbit != 0 && i / 8 < sz_buf * ss; buf[i / 8] |= 1 << (i % 8), i++, nbit--) ; /* Mark used clusters */ n = (nsect > sz_buf) ? sz_buf : nsect; /* Write the buffered data */ - if (disk_write(pdrv, buf, sect, n) != RES_OK) LEAVE_MKFS(FR_DISK_ERR); - sect += n; nsect -= n; - } while (nsect); + if (disk_write(pdrv, buf, sect, n) != RES_OK) { + LEAVE_MKFS(FR_DISK_ERR); + } + sect += n; + nsect -= n; + } + while (nsect); /* Initialize the FAT */ - sect = b_fat; nsect = sz_fat; /* Start of FAT and number of FAT sectors */ + sect = b_fat; + nsect = sz_fat; /* Start of FAT and number of FAT sectors */ j = nbit = clu = 0; do { - memset(buf, 0, sz_buf * ss); i = 0; /* Clear work area and reset write offset */ + memset(buf, 0, sz_buf * ss); + i = 0; /* Clear work area and reset write offset */ if (clu == 0) { /* Initialize FAT [0] and FAT[1] */ - st_dword(buf + i, 0xFFFFFFF8); i += 4; clu++; - st_dword(buf + i, 0xFFFFFFFF); i += 4; clu++; + st_dword(buf + i, 0xFFFFFFF8); + i += 4; + clu++; + st_dword(buf + i, 0xFFFFFFFF); + i += 4; + clu++; } do { /* Create chains of bitmap, up-case and root dir */ while (nbit != 0 && i < sz_buf * ss) { /* Create a chain */ st_dword(buf + i, (nbit > 1) ? clu + 1 : 0xFFFFFFFF); - i += 4; clu++; nbit--; + i += 4; + clu++; + nbit--; } - if (nbit == 0 && j < 3) nbit = clen[j++]; /* Get next chain length */ - } while (nbit != 0 && i < sz_buf * ss); + if (nbit == 0 && j < 3) { + nbit = clen[j++]; /* Get next chain length */ + } + } + while (nbit != 0 && i < sz_buf * ss); n = (nsect > sz_buf) ? sz_buf : nsect; /* Write the buffered data */ - if (disk_write(pdrv, buf, sect, n) != RES_OK) LEAVE_MKFS(FR_DISK_ERR); - sect += n; nsect -= n; - } while (nsect); + if (disk_write(pdrv, buf, sect, n) != RES_OK) { + LEAVE_MKFS(FR_DISK_ERR); + } + sect += n; + nsect -= n; + } + while (nsect); /* Initialize the root directory */ memset(buf, 0, sz_buf * ss); @@ -6195,13 +7436,18 @@ FRESULT f_mkfs ( st_dword(buf + SZDIRE * 2 + 4, sum); /* sum */ st_dword(buf + SZDIRE * 2 + 20, 2 + clen[0]); /* cluster */ st_dword(buf + SZDIRE * 2 + 24, szb_case); /* size */ - sect = b_data + sz_au * (clen[0] + clen[1]); nsect = sz_au; /* Start of the root directory and number of sectors */ + sect = b_data + sz_au * (clen[0] + clen[1]); + nsect = sz_au; /* Start of the root directory and number of sectors */ do { /* Fill root directory sectors */ n = (nsect > sz_buf) ? sz_buf : nsect; - if (disk_write(pdrv, buf, sect, n) != RES_OK) LEAVE_MKFS(FR_DISK_ERR); + if (disk_write(pdrv, buf, sect, n) != RES_OK) { + LEAVE_MKFS(FR_DISK_ERR); + } memset(buf, 0, ss); /* Rest of entries are filled with zero */ - sect += n; nsect -= n; - } while (nsect); + sect += n; + nsect -= n; + } + while (nsect); /* Create two set of the exFAT VBR blocks */ sect = b_vol; @@ -6225,28 +7471,41 @@ FRESULT f_mkfs ( st_word(buf + BS_BootCodeEx, 0xFEEB); /* Boot code (x86) */ st_word(buf + BS_55AA, 0xAA55); /* Signature (placed here regardless of sector size) */ for (i = sum = 0; i < ss; i++) { /* VBR checksum */ - if (i != BPB_VolFlagEx && i != BPB_VolFlagEx + 1 && i != BPB_PercInUseEx) sum = xsum32(buf[i], sum); + if (i != BPB_VolFlagEx && i != BPB_VolFlagEx + 1 && i != BPB_PercInUseEx) { + sum = xsum32(buf[i], sum); + } + } + if (disk_write(pdrv, buf, sect++, 1) != RES_OK) { + LEAVE_MKFS(FR_DISK_ERR); } - if (disk_write(pdrv, buf, sect++, 1) != RES_OK) LEAVE_MKFS(FR_DISK_ERR); /* Extended bootstrap record (+1..+8) */ memset(buf, 0, ss); st_word(buf + ss - 2, 0xAA55); /* Signature (placed at end of sector) */ for (j = 1; j < 9; j++) { for (i = 0; i < ss; sum = xsum32(buf[i++], sum)) ; /* VBR checksum */ - if (disk_write(pdrv, buf, sect++, 1) != RES_OK) LEAVE_MKFS(FR_DISK_ERR); + if (disk_write(pdrv, buf, sect++, 1) != RES_OK) { + LEAVE_MKFS(FR_DISK_ERR); + } } /* OEM/Reserved record (+9..+10) */ memset(buf, 0, ss); for ( ; j < 11; j++) { for (i = 0; i < ss; sum = xsum32(buf[i++], sum)) ; /* VBR checksum */ - if (disk_write(pdrv, buf, sect++, 1) != RES_OK) LEAVE_MKFS(FR_DISK_ERR); + if (disk_write(pdrv, buf, sect++, 1) != RES_OK) { + LEAVE_MKFS(FR_DISK_ERR); + } } /* Sum record (+11) */ - for (i = 0; i < ss; i += 4) st_dword(buf + i, sum); /* Fill with checksum value */ - if (disk_write(pdrv, buf, sect++, 1) != RES_OK) LEAVE_MKFS(FR_DISK_ERR); + for (i = 0; i < ss; i += 4) { + st_dword(buf + i, sum); /* Fill with checksum value */ + } + if (disk_write(pdrv, buf, sect++, 1) != RES_OK) { + LEAVE_MKFS(FR_DISK_ERR); + } } - } else + } + else #endif /* FF_FS_EXFAT */ { /* Create an FAT/FAT32 volume */ do { @@ -6261,8 +7520,11 @@ FRESULT f_mkfs ( sz_fat = (n_clst * 4 + 8 + ss - 1) / ss; /* FAT size [sector] */ sz_rsv = 32; /* Number of reserved sectors */ sz_dir = 0; /* No static directory */ - if (n_clst <= MAX_FAT16 || n_clst > MAX_FAT32) LEAVE_MKFS(FR_MKFS_ABORTED); - } else { /* FAT volume */ + if (n_clst <= MAX_FAT16 || n_clst > MAX_FAT32) { + LEAVE_MKFS(FR_MKFS_ABORTED); + } + } + else { /* FAT volume */ if (pau == 0) { /* au auto-selection */ n = (DWORD)sz_vol / 0x1000; /* Volume size in unit of 4KS */ for (i = 0, pau = 1; cst[i] && cst[i] <= n; i++, pau <<= 1) ; /* Get from table */ @@ -6270,7 +7532,8 @@ FRESULT f_mkfs ( n_clst = (DWORD)sz_vol / pau; if (n_clst > MAX_FAT12) { n = n_clst * 2 + 4; /* FAT size [byte] */ - } else { + } + else { fsty = FS_FAT12; n = (n_clst * 3 + 1) / 2 + 3; /* FAT size [byte] */ } @@ -6284,47 +7547,65 @@ FRESULT f_mkfs ( /* Align data area to erase block boundary (for flash memory media) */ n = (DWORD)(((b_data + sz_blk - 1) & ~(sz_blk - 1)) - b_data); /* Sectors to next nearest from current data base */ if (fsty == FS_FAT32) { /* FAT32: Move FAT */ - sz_rsv += n; b_fat += n; - } else { /* FAT: Expand FAT */ + sz_rsv += n; + b_fat += n; + } + else { /* FAT: Expand FAT */ if (n % n_fat) { /* Adjust fractional error if needed */ - n--; sz_rsv++; b_fat++; + n--; + sz_rsv++; + b_fat++; } sz_fat += n / n_fat; } /* Determine number of clusters and final check of validity of the FAT sub-type */ - if (sz_vol < b_data + pau * 16 - b_vol) LEAVE_MKFS(FR_MKFS_ABORTED); /* Too small volume? */ + if (sz_vol < b_data + pau * 16 - b_vol) { + LEAVE_MKFS(FR_MKFS_ABORTED); /* Too small volume? */ + } n_clst = ((DWORD)sz_vol - sz_rsv - sz_fat * n_fat - sz_dir) / pau; if (fsty == FS_FAT32) { if (n_clst <= MAX_FAT16) { /* Too few clusters for FAT32? */ - if (sz_au == 0 && (sz_au = pau / 2) != 0) continue; /* Adjust cluster size and retry */ + if (sz_au == 0 && (sz_au = pau / 2) != 0) { + continue; /* Adjust cluster size and retry */ + } LEAVE_MKFS(FR_MKFS_ABORTED); } } if (fsty == FS_FAT16) { if (n_clst > MAX_FAT16) { /* Too many clusters for FAT16 */ if (sz_au == 0 && (pau * 2) <= 64) { - sz_au = pau * 2; continue; /* Adjust cluster size and retry */ + sz_au = pau * 2; + continue; /* Adjust cluster size and retry */ } if ((fsopt & FM_FAT32)) { - fsty = FS_FAT32; continue; /* Switch type to FAT32 and retry */ + fsty = FS_FAT32; + continue; /* Switch type to FAT32 and retry */ + } + if (sz_au == 0 && (sz_au = pau * 2) <= 128) { + continue; /* Adjust cluster size and retry */ } - if (sz_au == 0 && (sz_au = pau * 2) <= 128) continue; /* Adjust cluster size and retry */ LEAVE_MKFS(FR_MKFS_ABORTED); } if (n_clst <= MAX_FAT12) { /* Too few clusters for FAT16 */ - if (sz_au == 0 && (sz_au = pau * 2) <= 128) continue; /* Adjust cluster size and retry */ + if (sz_au == 0 && (sz_au = pau * 2) <= 128) { + continue; /* Adjust cluster size and retry */ + } LEAVE_MKFS(FR_MKFS_ABORTED); } } - if (fsty == FS_FAT12 && n_clst > MAX_FAT12) LEAVE_MKFS(FR_MKFS_ABORTED); /* Too many clusters for FAT12 */ + if (fsty == FS_FAT12 && n_clst > MAX_FAT12) { + LEAVE_MKFS(FR_MKFS_ABORTED); /* Too many clusters for FAT12 */ + } /* Ok, it is the valid cluster configuration */ break; - } while (1); + } + while (1); #if FF_USE_TRIM - lba[0] = b_vol; lba[1] = b_vol + sz_vol - 1; /* Inform storage device that the volume area may be erased */ + lba[0] = b_vol; + lba[1] = b_vol + sz_vol - 1; /* Inform storage device that the volume area may be erased */ disk_ioctl(pdrv, CTRL_TRIM, lba); #endif /* Create FAT VBR */ @@ -6337,7 +7618,8 @@ FRESULT f_mkfs ( st_word(buf + BPB_RootEntCnt, (WORD)((fsty == FS_FAT32) ? 0 : n_root)); /* Number of root directory entries */ if (sz_vol < 0x10000) { st_word(buf + BPB_TotSec16, (WORD)sz_vol); /* Volume size in 16-bit LBA */ - } else { + } + else { st_dword(buf + BPB_TotSec32, (DWORD)sz_vol); /* Volume size in 32-bit LBA */ } buf[BPB_Media] = 0xF8; /* Media descriptor byte */ @@ -6353,7 +7635,8 @@ FRESULT f_mkfs ( buf[BS_DrvNum32] = 0x80; /* Drive number (for int13) */ buf[BS_BootSig32] = 0x29; /* Extended boot signature */ mem_cpy(buf + BS_VolLab32, "NO NAME " "FAT32 ", 19); /* Volume label, FAT signature */ - } else { + } + else { st_dword(buf + BS_VolID, vsn); /* VSN */ st_word(buf + BPB_FATSz16, (WORD)sz_fat); /* FAT size [sector] */ buf[BS_DrvNum] = 0x80; /* Drive number (for int13) */ @@ -6361,7 +7644,9 @@ FRESULT f_mkfs ( mem_cpy(buf + BS_VolLab, "NO NAME " "FAT ", 19); /* Volume label, FAT signature */ } st_word(buf + BS_55AA, 0xAA55); /* Signature (offset is fixed here regardless of sector size) */ - if (disk_write(pdrv, buf, b_vol, 1) != RES_OK) LEAVE_MKFS(FR_DISK_ERR); /* Write it to the VBR sector */ + if (disk_write(pdrv, buf, b_vol, 1) != RES_OK) { + LEAVE_MKFS(FR_DISK_ERR); /* Write it to the VBR sector */ + } /* Create FSINFO record if needed */ if (fsty == FS_FAT32) { @@ -6384,25 +7669,34 @@ FRESULT f_mkfs ( st_dword(buf + 0, 0xFFFFFFF8); /* FAT[0] */ st_dword(buf + 4, 0xFFFFFFFF); /* FAT[1] */ st_dword(buf + 8, 0x0FFFFFFF); /* FAT[2] (root directory) */ - } else { + } + else { st_dword(buf + 0, (fsty == FS_FAT12) ? 0xFFFFF8 : 0xFFFFFFF8); /* FAT[0] and FAT[1] */ } nsect = sz_fat; /* Number of FAT sectors */ do { /* Fill FAT sectors */ n = (nsect > sz_buf) ? sz_buf : nsect; - if (disk_write(pdrv, buf, sect, (UINT)n) != RES_OK) LEAVE_MKFS(FR_DISK_ERR); + if (disk_write(pdrv, buf, sect, (UINT)n) != RES_OK) { + LEAVE_MKFS(FR_DISK_ERR); + } memset(buf, 0, ss); /* Rest of FAT all are cleared */ - sect += n; nsect -= n; - } while (nsect); + sect += n; + nsect -= n; + } + while (nsect); } /* Initialize root directory (fill with zero) */ nsect = (fsty == FS_FAT32) ? pau : sz_dir; /* Number of root directory sectors */ do { n = (nsect > sz_buf) ? sz_buf : nsect; - if (disk_write(pdrv, buf, sect, (UINT)n) != RES_OK) LEAVE_MKFS(FR_DISK_ERR); - sect += n; nsect -= n; - } while (nsect); + if (disk_write(pdrv, buf, sect, (UINT)n) != RES_OK) { + LEAVE_MKFS(FR_DISK_ERR); + } + sect += n; + nsect -= n; + } + while (nsect); } /* A FAT volume has been created here */ @@ -6410,13 +7704,17 @@ FRESULT f_mkfs ( /* Determine system ID in the MBR partition table */ if (FF_FS_EXFAT && fsty == FS_EXFAT) { sys = 0x07; /* exFAT */ - } else if (fsty == FS_FAT32) { + } + else if (fsty == FS_FAT32) { sys = 0x0C; /* FAT32X */ - } else if (sz_vol >= 0x10000) { + } + else if (sz_vol >= 0x10000) { sys = 0x06; /* FAT12/16 (large) */ - } else if (fsty == FS_FAT16) { + } + else if (fsty == FS_FAT16) { sys = 0x04; /* FAT16 */ - } else { + } + else { sys = 0x01; /* FAT12 */ } @@ -6424,19 +7722,29 @@ FRESULT f_mkfs ( if (FF_MULTI_PARTITION && ipart != 0) { /* Volume is in the existing partition */ if (!FF_LBA64 || !(fsopt & 0x80)) { /* Is the partition in MBR? */ /* Update system ID in the partition table */ - if (disk_read(pdrv, buf, 0, 1) != RES_OK) LEAVE_MKFS(FR_DISK_ERR); /* Read the MBR */ + if (disk_read(pdrv, buf, 0, 1) != RES_OK) { + LEAVE_MKFS(FR_DISK_ERR); /* Read the MBR */ + } buf[MBR_Table + (ipart - 1) * SZ_PTE + PTE_System] = sys; /* Set system ID */ - if (disk_write(pdrv, buf, 0, 1) != RES_OK) LEAVE_MKFS(FR_DISK_ERR); /* Write it back to the MBR */ + if (disk_write(pdrv, buf, 0, 1) != RES_OK) { + LEAVE_MKFS(FR_DISK_ERR); /* Write it back to the MBR */ + } } - } else { /* Volume as a new single partition */ + } + else { /* Volume as a new single partition */ if (!(fsopt & FM_SFD)) { /* Create partition table if not in SFD format */ - lba[0] = sz_vol; lba[1] = 0; + lba[0] = sz_vol; + lba[1] = 0; res = create_partition(pdrv, lba, sys, buf); - if (res != FR_OK) LEAVE_MKFS(res); + if (res != FR_OK) { + LEAVE_MKFS(res); + } } } - if (disk_ioctl(pdrv, CTRL_SYNC, 0) != RES_OK) LEAVE_MKFS(FR_DISK_ERR); + if (disk_ioctl(pdrv, CTRL_SYNC, 0) != RES_OK) { + LEAVE_MKFS(FR_DISK_ERR); + } LEAVE_MKFS(FR_OK); } @@ -6452,25 +7760,34 @@ FRESULT f_mkfs ( FRESULT f_fdisk ( BYTE pdrv, /* Physical drive number */ const LBA_t ptbl[], /* Pointer to the size table for each partitions */ - void* work /* Pointer to the working buffer (null: use heap memory) */ + void *work /* Pointer to the working buffer (null: use heap memory) */ ) { - BYTE *buf = (BYTE*)work; + BYTE *buf = (BYTE *)work; DSTATUS stat; FRESULT res = FR_DISK_ERR; /* Initialize the physical drive */ stat = disk_initialize(pdrv); - if (stat & STA_NOINIT) return FR_NOT_READY; - if (stat & STA_PROTECT) return FR_WRITE_PROTECTED; + if (stat & STA_NOINIT) { + return FR_NOT_READY; + } + if (stat & STA_PROTECT) { + return FR_WRITE_PROTECTED; + } #if FF_USE_LFN == 3 - if (!buf) buf = ff_memalloc(FF_MAX_SS); /* Use heap memory for working buffer */ + if (!buf) { + buf = ff_memalloc(FF_MAX_SS); /* Use heap memory for working buffer */ + } #endif - if (!buf) return FR_NOT_ENOUGH_CORE; + if (!buf) { + return FR_NOT_ENOUGH_CORE; + } - res = create_partition(pdrv, ptbl, 0x07, buf); /* Create partitions (system ID is temporary setting and determined by f_mkfs) */ + res = create_partition(pdrv, ptbl, 0x07, + buf); /* Create partitions (system ID is temporary setting and determined by f_mkfs) */ LEAVE_MKFS(res); } @@ -6489,10 +7806,10 @@ FRESULT f_fdisk ( /* Get a String from the File */ /*-----------------------------------------------------------------------*/ -TCHAR* f_gets ( - TCHAR* buff, /* Pointer to the buffer to store read string */ +TCHAR *f_gets ( + TCHAR *buff, /* Pointer to the buffer to store read string */ int len, /* Size of string buffer (items) */ - FIL* fp /* Pointer to the file object */ + FIL *fp /* Pointer to the file object */ ) { int nc = 0; @@ -6509,84 +7826,129 @@ TCHAR* f_gets ( #if FF_USE_LFN && FF_LFN_UNICODE /* With code conversion (Unicode API) */ /* Make a room for the character and terminator */ - if (FF_LFN_UNICODE == 1) len -= (FF_STRF_ENCODE == 0) ? 1 : 2; - if (FF_LFN_UNICODE == 2) len -= (FF_STRF_ENCODE == 0) ? 3 : 4; - if (FF_LFN_UNICODE == 3) len -= 1; + if (FF_LFN_UNICODE == 1) { + len -= (FF_STRF_ENCODE == 0) ? 1 : 2; + } + if (FF_LFN_UNICODE == 2) { + len -= (FF_STRF_ENCODE == 0) ? 3 : 4; + } + if (FF_LFN_UNICODE == 3) { + len -= 1; + } while (nc < len) { #if FF_STRF_ENCODE == 0 /* Read a character in ANSI/OEM */ f_read(fp, s, 1, &rc); /* Get a code unit */ - if (rc != 1) break; /* EOF? */ + if (rc != 1) { + break; /* EOF? */ + } wc = s[0]; if (dbc_1st((BYTE)wc)) { /* DBC 1st byte? */ f_read(fp, s, 1, &rc); /* Get 2nd byte */ - if (rc != 1 || !dbc_2nd(s[0])) continue; /* Wrong code? */ + if (rc != 1 || !dbc_2nd(s[0])) { + continue; /* Wrong code? */ + } wc = wc << 8 | s[0]; } dc = ff_oem2uni(wc, CODEPAGE); /* Convert ANSI/OEM into Unicode */ - if (dc == 0) continue; /* Conversion error? */ + if (dc == 0) { + continue; /* Conversion error? */ + } #elif FF_STRF_ENCODE == 1 || FF_STRF_ENCODE == 2 /* Read a character in UTF-16LE/BE */ f_read(fp, s, 2, &rc); /* Get a code unit */ - if (rc != 2) break; /* EOF? */ + if (rc != 2) { + break; /* EOF? */ + } dc = (FF_STRF_ENCODE == 1) ? ld_word(s) : s[0] << 8 | s[1]; - if (IsSurrogateL(dc)) continue; /* Broken surrogate pair? */ + if (IsSurrogateL(dc)) { + continue; /* Broken surrogate pair? */ + } if (IsSurrogateH(dc)) { /* High surrogate? */ f_read(fp, s, 2, &rc); /* Get low surrogate */ - if (rc != 2) break; /* EOF? */ + if (rc != 2) { + break; /* EOF? */ + } wc = (FF_STRF_ENCODE == 1) ? ld_word(s) : s[0] << 8 | s[1]; - if (!IsSurrogateL(wc)) continue; /* Broken surrogate pair? */ + if (!IsSurrogateL(wc)) { + continue; /* Broken surrogate pair? */ + } dc = ((dc & 0x3FF) + 0x40) << 10 | (wc & 0x3FF); /* Merge surrogate pair */ } #else /* Read a character in UTF-8 */ f_read(fp, s, 1, &rc); /* Get a code unit */ - if (rc != 1) break; /* EOF? */ + if (rc != 1) { + break; /* EOF? */ + } dc = s[0]; if (dc >= 0x80) { /* Multi-byte sequence? */ ct = 0; if ((dc & 0xE0) == 0xC0) { /* 2-byte sequence? */ - dc &= 0x1F; ct = 1; + dc &= 0x1F; + ct = 1; } if ((dc & 0xF0) == 0xE0) { /* 3-byte sequence? */ - dc &= 0x0F; ct = 2; + dc &= 0x0F; + ct = 2; } if ((dc & 0xF8) == 0xF0) { /* 4-byte sequence? */ - dc &= 0x07; ct = 3; + dc &= 0x07; + ct = 3; + } + if (ct == 0) { + continue; } - if (ct == 0) continue; f_read(fp, s, ct, &rc); /* Get trailing bytes */ - if (rc != ct) break; + if (rc != ct) { + break; + } rc = 0; do { /* Merge the byte sequence */ - if ((s[rc] & 0xC0) != 0x80) break; + if ((s[rc] & 0xC0) != 0x80) { + break; + } dc = dc << 6 | (s[rc] & 0x3F); - } while (++rc < ct); - if (rc != ct || dc < 0x80 || IsSurrogate(dc) || dc >= 0x110000) continue; /* Wrong encoding? */ + } + while (++rc < ct); + if (rc != ct || dc < 0x80 || IsSurrogate(dc) || dc >= 0x110000) { + continue; /* Wrong encoding? */ + } } #endif /* A code point is avaialble in dc to be output */ - if (FF_USE_STRFUNC == 2 && dc == '\r') continue; /* Strip \r off if needed */ + if (FF_USE_STRFUNC == 2 && dc == '\r') { + continue; /* Strip \r off if needed */ + } #if FF_LFN_UNICODE == 1 || FF_LFN_UNICODE == 3 /* Output it in UTF-16/32 encoding */ if (FF_LFN_UNICODE == 1 && dc >= 0x10000) { /* Out of BMP at UTF-16? */ - *p++ = (TCHAR)(0xD800 | ((dc >> 10) - 0x40)); nc++; /* Make and output high surrogate */ + *p++ = (TCHAR)(0xD800 | ((dc >> 10) - 0x40)); + nc++; /* Make and output high surrogate */ dc = 0xDC00 | (dc & 0x3FF); /* Make low surrogate */ } - *p++ = (TCHAR)dc; nc++; - if (dc == '\n') break; /* End of line? */ + *p++ = (TCHAR)dc; + nc++; + if (dc == '\n') { + break; /* End of line? */ + } #elif FF_LFN_UNICODE == 2 /* Output it in UTF-8 encoding */ if (dc < 0x80) { /* Single byte? */ *p++ = (TCHAR)dc; nc++; - if (dc == '\n') break; /* End of line? */ - } else if (dc < 0x800) { /* 2-byte sequence? */ + if (dc == '\n') { + break; /* End of line? */ + } + } + else if (dc < 0x800) { /* 2-byte sequence? */ *p++ = (TCHAR)(0xC0 | (dc >> 6 & 0x1F)); *p++ = (TCHAR)(0x80 | (dc >> 0 & 0x3F)); nc += 2; - } else if (dc < 0x10000) { /* 3-byte sequence? */ + } + else if (dc < 0x10000) { /* 3-byte sequence? */ *p++ = (TCHAR)(0xE0 | (dc >> 12 & 0x0F)); *p++ = (TCHAR)(0x80 | (dc >> 6 & 0x3F)); *p++ = (TCHAR)(0x80 | (dc >> 0 & 0x3F)); nc += 3; - } else { /* 4-byte sequence */ + } + else { /* 4-byte sequence */ *p++ = (TCHAR)(0xF0 | (dc >> 18 & 0x07)); *p++ = (TCHAR)(0x80 | (dc >> 12 & 0x3F)); *p++ = (TCHAR)(0x80 | (dc >> 6 & 0x3F)); @@ -6600,11 +7962,18 @@ TCHAR* f_gets ( len -= 1; /* Make a room for the terminator */ while (nc < len) { f_read(fp, s, 1, &rc); /* Get a byte */ - if (rc != 1) break; /* EOF? */ + if (rc != 1) { + break; /* EOF? */ + } dc = s[0]; - if (FF_USE_STRFUNC == 2 && dc == '\r') continue; - *p++ = (TCHAR)dc; nc++; - if (dc == '\n') break; + if (FF_USE_STRFUNC == 2 && dc == '\r') { + continue; + } + *p++ = (TCHAR)dc; + nc++; + if (dc == '\n') { + break; + } } #endif @@ -6641,7 +8010,7 @@ typedef struct { /* Buffered file write with code conversion */ -static void putc_bfd (putbuff* pb, TCHAR c) +static void putc_bfd (putbuff *pb, TCHAR c) { UINT n; int i, nc; @@ -6649,7 +8018,7 @@ static void putc_bfd (putbuff* pb, TCHAR c) WCHAR hs, wc; #if FF_LFN_UNICODE == 2 DWORD dc; - const TCHAR* tp; + const TCHAR *tp; #endif #endif @@ -6658,50 +8027,76 @@ static void putc_bfd (putbuff* pb, TCHAR c) } i = pb->idx; /* Write index of pb->buf[] */ - if (i < 0) return; /* In write error? */ + if (i < 0) { + return; /* In write error? */ + } nc = pb->nchr; /* Write unit counter */ #if FF_USE_LFN && FF_LFN_UNICODE #if FF_LFN_UNICODE == 1 /* UTF-16 input */ if (IsSurrogateH(c)) { /* Is this a high-surrogate? */ - pb->hs = c; return; /* Save it for next */ + pb->hs = c; + return; /* Save it for next */ } - hs = pb->hs; pb->hs = 0; + hs = pb->hs; + pb->hs = 0; if (hs != 0) { /* Is there a leading high-surrogate? */ - if (!IsSurrogateL(c)) hs = 0; /* Discard high-surrogate if not a surrogate pair */ - } else { - if (IsSurrogateL(c)) return; /* Discard stray low-surrogate */ + if (!IsSurrogateL(c)) { + hs = 0; /* Discard high-surrogate if not a surrogate pair */ + } + } + else { + if (IsSurrogateL(c)) { + return; /* Discard stray low-surrogate */ + } } wc = c; #elif FF_LFN_UNICODE == 2 /* UTF-8 input */ for (;;) { if (pb->ct == 0) { /* Out of multi-byte sequence? */ pb->bs[pb->wi = 0] = (BYTE)c; /* Save 1st byte */ - if ((BYTE)c < 0x80) break; /* Single byte code? */ - if (((BYTE)c & 0xE0) == 0xC0) pb->ct = 1; /* 2-byte sequence? */ - if (((BYTE)c & 0xF0) == 0xE0) pb->ct = 2; /* 3-byte sequence? */ - if (((BYTE)c & 0xF8) == 0xF0) pb->ct = 3; /* 4-byte sequence? */ + if ((BYTE)c < 0x80) { + break; /* Single byte code? */ + } + if (((BYTE)c & 0xE0) == 0xC0) { + pb->ct = 1; /* 2-byte sequence? */ + } + if (((BYTE)c & 0xF0) == 0xE0) { + pb->ct = 2; /* 3-byte sequence? */ + } + if (((BYTE)c & 0xF8) == 0xF0) { + pb->ct = 3; /* 4-byte sequence? */ + } return; /* Wrong leading byte (discard it) */ - } else { /* In the multi-byte sequence */ + } + else { /* In the multi-byte sequence */ if (((BYTE)c & 0xC0) != 0x80) { /* Broken sequence? */ - pb->ct = 0; continue; /* Discard the sequense */ + pb->ct = 0; + continue; /* Discard the sequense */ } pb->bs[++pb->wi] = (BYTE)c; /* Save the trailing byte */ - if (--pb->ct == 0) break; /* End of the sequence? */ + if (--pb->ct == 0) { + break; /* End of the sequence? */ + } return; } } - tp = (const TCHAR*)pb->bs; + tp = (const TCHAR *)pb->bs; dc = tchar2uni(&tp); /* UTF-8 ==> UTF-16 */ - if (dc == 0xFFFFFFFF) return; /* Wrong code? */ + if (dc == 0xFFFFFFFF) { + return; /* Wrong code? */ + } hs = (WCHAR)(dc >> 16); wc = (WCHAR)dc; #elif FF_LFN_UNICODE == 3 /* UTF-32 input */ - if (IsSurrogate(c) || c >= 0x110000) return; /* Discard invalid code */ + if (IsSurrogate(c) || c >= 0x110000) { + return; /* Discard invalid code */ + } if (c >= 0x10000) { /* Out of BMP? */ hs = (WCHAR)(0xD800 | ((c >> 10) - 0x40)); /* Make high surrogate */ wc = 0xDC00 | (c & 0x3FF); /* Make low surrogate */ - } else { + } + else { hs = 0; wc = (WCHAR)c; } @@ -6732,14 +8127,17 @@ static void putc_bfd (putbuff* pb, TCHAR c) pb->buf[i++] = (BYTE)(0x80 | (hs >> 2 & 0x3F)); pb->buf[i++] = (BYTE)(0x80 | (hs & 3) << 4 | (wc >> 6 & 0x0F)); pb->buf[i++] = (BYTE)(0x80 | (wc & 0x3F)); - } else { + } + else { if (wc < 0x80) { /* Single byte? */ pb->buf[i++] = (BYTE)wc; - } else { + } + else { if (wc < 0x800) { /* 2-byte sequence? */ nc += 1; pb->buf[i++] = (BYTE)(0xC0 | wc >> 6); - } else { /* 3-byte sequence */ + } + else { /* 3-byte sequence */ nc += 2; pb->buf[i++] = (BYTE)(0xE0 | wc >> 12); pb->buf[i++] = (BYTE)(0x80 | (wc >> 6 & 0x3F)); @@ -6748,11 +8146,16 @@ static void putc_bfd (putbuff* pb, TCHAR c) } } #else /* Write a code point in ANSI/OEM */ - if (hs != 0) return; + if (hs != 0) { + return; + } wc = ff_uni2oem(wc, CODEPAGE); /* UTF-16 ==> ANSI/OEM */ - if (wc == 0) return; + if (wc == 0) { + return; + } if (wc >= 0x100) { - pb->buf[i++] = (BYTE)(wc >> 8); nc++; + pb->buf[i++] = (BYTE)(wc >> 8); + nc++; } pb->buf[i++] = (BYTE)wc; #endif @@ -6772,20 +8175,22 @@ static void putc_bfd (putbuff* pb, TCHAR c) /* Flush remaining characters in the buffer */ -static int putc_flush (putbuff* pb) +static int putc_flush (putbuff *pb) { UINT nw; if ( pb->idx >= 0 /* Flush buffered characters to the file */ - && f_write(pb->fp, pb->buf, (UINT)pb->idx, &nw) == FR_OK - && (UINT)pb->idx == nw) return pb->nchr; + && f_write(pb->fp, pb->buf, (UINT)pb->idx, &nw) == FR_OK + && (UINT)pb->idx == nw) { + return pb->nchr; + } return -1; } /* Initialize write buffer */ -static void putc_init (putbuff* pb, FIL* fp) +static void putc_init (putbuff *pb, FIL *fp) { memset(pb, 0, sizeof (putbuff)); pb->fp = fp; @@ -6795,7 +8200,7 @@ static void putc_init (putbuff* pb, FIL* fp) int f_putc ( TCHAR c, /* A character to be output */ - FIL* fp /* Pointer to the file object */ + FIL *fp /* Pointer to the file object */ ) { putbuff pb; @@ -6814,15 +8219,17 @@ int f_putc ( /*-----------------------------------------------------------------------*/ int f_puts ( - const TCHAR* str, /* Pointer to the string to be output */ - FIL* fp /* Pointer to the file object */ + const TCHAR *str, /* Pointer to the string to be output */ + FIL *fp /* Pointer to the file object */ ) { putbuff pb; putc_init(&pb, fp); - while (*str) putc_bfd(&pb, *str++); /* Put the string */ + while (*str) { + putc_bfd(&pb, *str++); /* Put the string */ + } return putc_flush(&pb); } @@ -6841,16 +8248,22 @@ static int ilog10 (double n) /* Calculate log10(n) in integer output */ while (n >= 10) { /* Decimate digit in right shift */ if (n >= 100000) { - n /= 100000; rv += 5; - } else { - n /= 10; rv++; + n /= 100000; + rv += 5; + } + else { + n /= 10; + rv++; } } while (n < 1) { /* Decimate digit in left shift */ if (n < 0.00001) { - n *= 100000; rv -= 5; - } else { - n *= 10; rv--; + n *= 100000; + rv -= 5; + } + else { + n *= 10; + rv--; } } return rv; @@ -6863,16 +8276,22 @@ static double i10x (int n) /* Calculate 10^n in integer input */ while (n > 0) { /* Left shift */ if (n >= 5) { - rv *= 100000; n -= 5; - } else { - rv *= 10; n--; + rv *= 100000; + n -= 5; + } + else { + rv *= 10; + n--; } } while (n < 0) { /* Right shift */ if (n <= -5) { - rv /= 100000; n += 5; - } else { - rv /= 10; n++; + rv /= 100000; + n += 5; + } + else { + rv /= 10; + n++; } } return rv; @@ -6880,7 +8299,7 @@ static double i10x (int n) /* Calculate 10^n in integer input */ static void ftoa ( - char* buf, /* Buffer to output the floating point string */ + char *buf, /* Buffer to output the floating point string */ double val, /* Value to output */ int prec, /* Number of fractional digits */ TCHAR fmt /* Notation */ @@ -6896,47 +8315,69 @@ static void ftoa ( if (isnan(val)) { /* Not a number? */ er = "NaN"; - } else { - if (prec < 0) prec = 6; /* Default precision? (6 fractional digits) */ + } + else { + if (prec < 0) { + prec = 6; /* Default precision? (6 fractional digits) */ + } if (val < 0) { /* Negative? */ - val = 0 - val; sign = '-'; - } else { + val = 0 - val; + sign = '-'; + } + else { sign = '+'; } if (isinf(val)) { /* Infinite? */ er = "INF"; - } else { + } + else { if (fmt == 'f') { /* Decimal notation? */ val += i10x(0 - prec) / 2; /* Round (nearest) */ m = ilog10(val); - if (m < 0) m = 0; - if (m + prec + 3 >= SZ_NUM_BUF) er = "OV"; /* Buffer overflow? */ - } else { /* E notation */ + if (m < 0) { + m = 0; + } + if (m + prec + 3 >= SZ_NUM_BUF) { + er = "OV"; /* Buffer overflow? */ + } + } + else { /* E notation */ if (val != 0) { /* Not a true zero? */ val += i10x(ilog10(val) - prec) / 2; /* Round (nearest) */ e = ilog10(val); if (e > 99 || prec + 7 >= SZ_NUM_BUF) { /* Buffer overflow or E > +99? */ er = "OV"; - } else { - if (e < -99) e = -99; + } + else { + if (e < -99) { + e = -99; + } val /= i10x(e); /* Normalize */ } } } } if (!er) { /* Not error condition */ - if (sign == '-') *buf++ = sign; /* Add a - if negative value */ + if (sign == '-') { + *buf++ = sign; /* Add a - if negative value */ + } do { /* Put decimal number */ - if (m == -1) *buf++ = ds; /* Insert a decimal separator when get into fractional part */ + if (m == -1) { + *buf++ = ds; /* Insert a decimal separator when get into fractional part */ + } w = i10x(m); /* Snip the highest digit d */ - d = (int)(val / w); val -= d * w; + d = (int)(val / w); + val -= d * w; *buf++ = (char)('0' + d); /* Put the digit */ - } while (--m >= -prec); /* Output all digits specified by prec */ + } + while (--m >= -prec); /* Output all digits specified by prec */ if (fmt != 'f') { /* Put exponent if needed */ *buf++ = (char)fmt; if (e < 0) { - e = 0 - e; *buf++ = '-'; - } else { + e = 0 - e; + *buf++ = '-'; + } + else { *buf++ = '+'; } *buf++ = (char)('0' + e / 10); @@ -6945,10 +8386,13 @@ static void ftoa ( } } if (er) { /* Error condition */ - if (sign) *buf++ = sign; /* Add sign if needed */ + if (sign) { + *buf++ = sign; /* Add sign if needed */ + } do { /* Put error symbol */ *buf++ = *er++; - } while (*er); + } + while (*er); } *buf = 0; /* Term */ } @@ -6957,8 +8401,8 @@ static void ftoa ( int f_printf ( - FIL* fp, /* Pointer to the file object */ - const TCHAR* fmt, /* Pointer to the format string */ + FIL *fp, /* Pointer to the file object */ + const TCHAR *fmt, /* Pointer to the format string */ ... /* Optional arguments... */ ) { @@ -6983,22 +8427,30 @@ int f_printf ( for (;;) { tc = *fmt++; - if (tc == 0) break; /* End of format string */ + if (tc == 0) { + break; /* End of format string */ + } if (tc != '%') { /* Not an escape character (pass-through) */ putc_bfd(&pb, tc); continue; } - f = w = 0; pad = ' '; prec = -1; /* Initialize parms */ + f = w = 0; + pad = ' '; + prec = -1; /* Initialize parms */ tc = *fmt++; if (tc == '0') { /* Flag: '0' padded */ - pad = '0'; tc = *fmt++; - } else if (tc == '-') { /* Flag: Left aligned */ - f = 2; tc = *fmt++; + pad = '0'; + tc = *fmt++; + } + else if (tc == '-') { /* Flag: Left aligned */ + f = 2; + tc = *fmt++; } if (tc == '*') { /* Minimum width from an argument */ w = va_arg(arp, int); tc = *fmt++; - } else { + } + else { while (IsDigit(tc)) { /* Minimum width */ w = w * 10 + tc - '0'; tc = *fmt++; @@ -7009,7 +8461,8 @@ int f_printf ( if (tc == '*') { /* Precision from an argument */ prec = va_arg(arp, int); tc = *fmt++; - } else { + } + else { prec = 0; while (IsDigit(tc)) { /* Precision */ prec = prec * 10 + tc - '0'; @@ -7018,92 +8471,127 @@ int f_printf ( } } if (tc == 'l') { /* Size: long int */ - f |= 4; tc = *fmt++; + f |= 4; + tc = *fmt++; #if FF_PRINT_LLI && FF_INTDEF == 2 if (tc == 'l') { /* Size: long long int */ - f |= 8; tc = *fmt++; + f |= 8; + tc = *fmt++; } #endif } - if (tc == 0) break; /* End of format string */ + if (tc == 0) { + break; /* End of format string */ + } switch (tc) { /* Atgument type is... */ - case 'b': /* Unsigned binary */ - r = 2; break; + case 'b': /* Unsigned binary */ + r = 2; + break; - case 'o': /* Unsigned octal */ - r = 8; break; + case 'o': /* Unsigned octal */ + r = 8; + break; - case 'd': /* Signed decimal */ - case 'u': /* Unsigned decimal */ - r = 10; break; + case 'd': /* Signed decimal */ + case 'u': /* Unsigned decimal */ + r = 10; + break; - case 'x': /* Unsigned hexadecimal (lower case) */ - case 'X': /* Unsigned hexadecimal (upper case) */ - r = 16; break; + case 'x': /* Unsigned hexadecimal (lower case) */ + case 'X': /* Unsigned hexadecimal (upper case) */ + r = 16; + break; - case 'c': /* Character */ - putc_bfd(&pb, (TCHAR)va_arg(arp, int)); - continue; + case 'c': /* Character */ + putc_bfd(&pb, (TCHAR)va_arg(arp, int)); + continue; - case 's': /* String */ - tp = va_arg(arp, TCHAR*); /* Get a pointer argument */ - if (!tp) tp = &nul; /* Null ptr generates a null string */ - for (j = 0; tp[j]; j++) ; /* j = tcslen(tp) */ - if (prec >= 0 && j > (UINT)prec) j = prec; /* Limited length of string body */ - for ( ; !(f & 2) && j < w; j++) putc_bfd(&pb, pad); /* Left pads */ - while (*tp && prec--) putc_bfd(&pb, *tp++); /* Body */ - while (j++ < w) putc_bfd(&pb, ' '); /* Right pads */ - continue; + case 's': /* String */ + tp = va_arg(arp, TCHAR *); /* Get a pointer argument */ + if (!tp) { + tp = &nul; /* Null ptr generates a null string */ + } + for (j = 0; tp[j]; j++) ; /* j = tcslen(tp) */ + if (prec >= 0 && j > (UINT)prec) { + j = prec; /* Limited length of string body */ + } + for ( ; !(f & 2) && j < w; j++) { + putc_bfd(&pb, pad); /* Left pads */ + } + while (*tp && prec--) { + putc_bfd(&pb, *tp++); /* Body */ + } + while (j++ < w) { + putc_bfd(&pb, ' '); /* Right pads */ + } + continue; #if FF_PRINT_FLOAT && FF_INTDEF == 2 - case 'f': /* Floating point (decimal) */ - case 'e': /* Floating point (e) */ - case 'E': /* Floating point (E) */ - ftoa(str, va_arg(arp, double), prec, tc); /* Make a floating point string */ - for (j = strlen(str); !(f & 2) && j < w; j++) putc_bfd(&pb, pad); /* Left pads */ - for (i = 0; str[i]; putc_bfd(&pb, str[i++])) ; /* Body */ - while (j++ < w) putc_bfd(&pb, ' '); /* Right pads */ - continue; + case 'f': /* Floating point (decimal) */ + case 'e': /* Floating point (e) */ + case 'E': /* Floating point (E) */ + ftoa(str, va_arg(arp, double), prec, tc); /* Make a floating point string */ + for (j = strlen(str); !(f & 2) && j < w; j++) { + putc_bfd(&pb, pad); /* Left pads */ + } + for (i = 0; str[i]; putc_bfd(&pb, str[i++])) ; /* Body */ + while (j++ < w) { + putc_bfd(&pb, ' '); /* Right pads */ + } + continue; #endif - default: /* Unknown type (pass-through) */ - putc_bfd(&pb, tc); continue; + default: /* Unknown type (pass-through) */ + putc_bfd(&pb, tc); + continue; } /* Get an integer argument and put it in numeral */ #if FF_PRINT_LLI && FF_INTDEF == 2 if (f & 8) { /* long long argument? */ v = (QWORD)va_arg(arp, long long); - } else if (f & 4) { /* long argument? */ + } + else if (f & 4) { /* long argument? */ v = (tc == 'd') ? (QWORD)(long long)va_arg(arp, long) : (QWORD)va_arg(arp, unsigned long); - } else { /* int/short/char argument */ + } + else { /* int/short/char argument */ v = (tc == 'd') ? (QWORD)(long long)va_arg(arp, int) : (QWORD)va_arg(arp, unsigned int); } if (tc == 'd' && (v & 0x8000000000000000)) { /* Negative value? */ - v = 0 - v; f |= 1; + v = 0 - v; + f |= 1; } #else if (f & 4) { /* long argument? */ v = (DWORD)va_arg(arp, long); - } else { /* int/short/char argument */ + } + else { /* int/short/char argument */ v = (tc == 'd') ? (DWORD)(long)va_arg(arp, int) : (DWORD)va_arg(arp, unsigned int); } if (tc == 'd' && (v & 0x80000000)) { /* Negative value? */ - v = 0 - v; f |= 1; + v = 0 - v; + f |= 1; } #endif i = 0; do { /* Make an integer number string */ - d = (char)(v % r); v /= r; - if (d > 9) d += (tc == 'x') ? 0x27 : 0x07; + d = (char)(v % r); + v /= r; + if (d > 9) { + d += (tc == 'x') ? 0x27 : 0x07; + } str[i++] = d + '0'; - } while (v && i < SZ_NUM_BUF); - if (f & 1) str[i++] = '-'; /* Sign */ + } + while (v && i < SZ_NUM_BUF); + if (f & 1) { + str[i++] = '-'; /* Sign */ + } /* Write it */ for (j = i; !(f & 2) && j < w; j++) { /* Left pads */ putc_bfd(&pb, pad); } do { /* Body */ putc_bfd(&pb, (TCHAR)str[--i]); - } while (i); + } + while (i); while (j++ < w) { /* Right pads */ putc_bfd(&pb, ' '); } @@ -7134,13 +8622,16 @@ FRESULT f_setcp ( for (i = 0; validcp[i] != 0 && validcp[i] != cp; i++) ; /* Find the code page */ - if (validcp[i] != cp) return FR_INVALID_PARAMETER; /* Not found? */ + if (validcp[i] != cp) { + return FR_INVALID_PARAMETER; /* Not found? */ + } CodePage = cp; if (cp >= 900) { /* DBCS */ ExCvt = 0; DbcTbl = tables[i]; - } else { /* SBCS */ + } + else { /* SBCS */ ExCvt = tables[i]; DbcTbl = 0; } diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/xilffs/src/include/diskio.h b/bsp_z7/ps7_cortexa9_0/libsrc/xilffs/src/include/diskio.h index 1c2b4a4..acfa0f0 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/xilffs/src/include/diskio.h +++ b/bsp_z7/ps7_cortexa9_0/libsrc/xilffs/src/include/diskio.h @@ -9,8 +9,8 @@ extern "C" { #endif -#define USE_WRITE 1 /* 1: Enable disk_write function */ -#define USE_IOCTL 1 /* 1: Enable disk_ioctl function */ +#define USE_WRITE 1 /**< 1: Enable disk_write function */ +#define USE_IOCTL 1 /**< 1: Enable disk_ioctl function */ #include "ff.h" #include "xil_types.h" @@ -20,11 +20,11 @@ typedef BYTE DSTATUS; /* Results of Disk Functions */ typedef enum { - RES_OK = 0, /* 0: Successful */ - RES_ERROR, /* 1: R/W Error */ - RES_WRPRT, /* 2: Write Protected */ - RES_NOTRDY, /* 3: Not Ready */ - RES_PARERR /* 4: Invalid Parameter */ + RES_OK = 0, /**< 0: Successful */ + RES_ERROR, /**< 1: R/W Error */ + RES_WRPRT, /**< 2: Write Protected */ + RES_NOTRDY, /**< 3: Not Ready */ + RES_PARERR /**< 4: Invalid Parameter */ } DRESULT; @@ -41,40 +41,40 @@ DRESULT disk_ioctl (BYTE pdrv, BYTE cmd, void* buff); /* Disk Status Bits (DSTATUS) */ -#define STA_NOINIT 0x01U /* Drive not initialized */ -#define STA_NODISK 0x02U /* No medium in the drive */ -#define STA_PROTECT 0x04U /* Write protected */ +#define STA_NOINIT 0x01U /**< Drive not initialized */ +#define STA_NODISK 0x02U /**< No medium in the drive */ +#define STA_PROTECT 0x04U /**< Write protected */ /* Command code for disk_ioctrl fucntion */ /* Generic command (Used by FatFs) */ -#define CTRL_SYNC 0U /* Complete pending write process (needed at FF_FS_READONLY == 0) */ -#define GET_SECTOR_COUNT 1U /* Get media size (needed at FF_USE_MKFS == 1) */ -#define GET_SECTOR_SIZE 2U /* Get sector size (needed at FF_MAX_SS != FF_MIN_SS) */ -#define GET_BLOCK_SIZE 3U /* Get erase block size (needed at FF_USE_MKFS == 1) */ -#define CTRL_TRIM 4U /* Inform device that the data on the block of sectors is no longer used (needed at FF_USE_TRIM == 1) */ +#define CTRL_SYNC 0U /**< Complete pending write process (needed at FF_FS_READONLY == 0) */ +#define GET_SECTOR_COUNT 1U /**< Get media size (needed at FF_USE_MKFS == 1) */ +#define GET_SECTOR_SIZE 2U /**< Get sector size (needed at FF_MAX_SS != FF_MIN_SS) */ +#define GET_BLOCK_SIZE 3U /**< Get erase block size (needed at FF_USE_MKFS == 1) */ +#define CTRL_TRIM 4U /**< Inform device that the data on the block of sectors is no longer used (needed at FF_USE_TRIM == 1) */ /* Generic command (Not used by FatFs) */ -#define CTRL_POWER 5U /* Get/Set power status */ -#define CTRL_LOCK 6U /* Lock/Unlock media removal */ -#define CTRL_EJECT 7U /* Eject media */ -#define CTRL_FORMAT 8U /* Create physical format on the media */ +#define CTRL_POWER 5U /**< Get/Set power status */ +#define CTRL_LOCK 6U /**< Lock/Unlock media removal */ +#define CTRL_EJECT 7U /**< Eject media */ +#define CTRL_FORMAT 8U /**< Create physical format on the media */ /* MMC/SDC specific ioctl command */ -#define MMC_GET_TYPE 10U /* Get card type */ -#define MMC_GET_CSD 11U /* Get CSD */ -#define MMC_GET_CID 12U /* Get CID */ -#define MMC_GET_OCR 13U /* Get OCR */ -#define MMC_GET_SDSTAT 14U /* Get SD status */ -#define ISDIO_READ 55 /* Read data form SD iSDIO register */ -#define ISDIO_WRITE 56 /* Write data to SD iSDIO register */ -#define ISDIO_MRITE 57 /* Masked write data to SD iSDIO register */ +#define MMC_GET_TYPE 10U /**< Get card type */ +#define MMC_GET_CSD 11U /**< Get CSD */ +#define MMC_GET_CID 12U /**< Get CID */ +#define MMC_GET_OCR 13U /**< Get OCR */ +#define MMC_GET_SDSTAT 14U /**< Get SD status */ +#define ISDIO_READ 55 /**< Read data form SD iSDIO register */ +#define ISDIO_WRITE 56 /**< Write data to SD iSDIO register */ +#define ISDIO_MRITE 57 /**< Masked write data to SD iSDIO register */ /* ATA/CF specific ioctl command */ -#define ATA_GET_REV 20U /* Get F/W revision */ -#define ATA_GET_MODEL 21U /* Get model name */ -#define ATA_GET_SN 22U /* Get serial number */ +#define ATA_GET_REV 20U /**< Get F/W revision */ +#define ATA_GET_MODEL 21U /**< Get model name */ +#define ATA_GET_SN 22U /**< Get serial number */ #ifdef __cplusplus } diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/xilffs/src/include/ff.h b/bsp_z7/ps7_cortexa9_0/libsrc/xilffs/src/include/ff.h index 6f522f9..0a0e086 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/xilffs/src/include/ff.h +++ b/bsp_z7/ps7_cortexa9_0/libsrc/xilffs/src/include/ff.h @@ -26,8 +26,8 @@ extern "C" { #endif -#include "xil_types.h" #include "ffconf.h" /* FatFs configuration options */ +#include "xilffs.h" #if FF_DEFINED != FFCONF_DEF #error Wrong configuration file (ffconf.h). @@ -355,7 +355,7 @@ int f_puts (const TCHAR* str, FIL* cp); /* Put a string to the file */ int f_printf (FIL* fp, const TCHAR* str, ...); /* Put a formatted string to the file */ TCHAR* f_gets (TCHAR* buff, int len, FIL* fp); /* Get a string from the file */ -/* Some API fucntions are implemented as macro */ +/* Some API functions are implemented as macro */ #define f_eof(fp) ((int)((fp)->fptr == (fp)->obj.objsize)) #define f_error(fp) ((fp)->err) diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/xilffs/src/include/ffconf.h b/bsp_z7/ps7_cortexa9_0/libsrc/xilffs/src/include/ffconf.h index 007d807..5a1bbe3 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/xilffs/src/include/ffconf.h +++ b/bsp_z7/ps7_cortexa9_0/libsrc/xilffs/src/include/ffconf.h @@ -8,7 +8,11 @@ extern "C" { #endif +#ifdef SDT +#include "xilffs_config.h" +#else #include "xparameters.h" +#endif /*---------------------------------------------------------------------------/ / Function Configurations @@ -34,7 +38,7 @@ extern "C" { / 2: f_opendir(), f_readdir() and f_closedir() are removed in addition to 1. / 3: f_lseek() function is removed in addition to 2. */ - +#ifdef FILE_SYSTEM_USE_STRFUNC #if FILE_SYSTEM_USE_STRFUNC == 0 #define FF_USE_STRFUNC 0 /* 0:Disable */ #elif FILE_SYSTEM_USE_STRFUNC == 1 @@ -42,6 +46,9 @@ extern "C" { #elif FILE_SYSTEM_USE_STRFUNC == 2 #define FF_USE_STRFUNC 2 /* 2:Enable */ #endif +#else +#define FF_USE_STRFUNC 0 /* 0:Disable */ +#endif /* This option switches string functions, f_gets(), f_putc(), f_puts() and f_printf(). / / 0: Disable string functions. @@ -87,7 +94,6 @@ extern "C" { /* This option switches f_forward() function. (0:Disable or 1:Enable) */ -#define FF_USE_STRFUNC 0 #define FF_PRINT_LLI 1 #define FF_PRINT_FLOAT 1 #define FF_STRF_ENCODE 3 @@ -187,7 +193,7 @@ extern "C" { / the file names to read. The maximum possible length of the read file name depends / on character encoding. When LFN is not enabled, these options have no effect. */ - +#ifdef FILE_SYSTEM_SET_FS_RPATH #if FILE_SYSTEM_SET_FS_RPATH == 0 #define FF_FS_RPATH 0U #elif FILE_SYSTEM_SET_FS_RPATH == 1 @@ -195,6 +201,9 @@ extern "C" { #elif FILE_SYSTEM_SET_FS_RPATH == 2 #define FF_FS_RPATH 2U #endif +#else +#define FF_FS_RPATH 0U +#endif /* This option configures support for relative path. / / 0: Disable relative path and remove related functions. diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/xilffs/src/include/xilffs.h b/bsp_z7/ps7_cortexa9_0/libsrc/xilffs/src/include/xilffs.h new file mode 100644 index 0000000..dd51f5b --- /dev/null +++ b/bsp_z7/ps7_cortexa9_0/libsrc/xilffs/src/include/xilffs.h @@ -0,0 +1,67 @@ +/****************************************************************************** +* Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** + * + * @file xilffs.h + * @addtogroup xilffs Overview + * @{ + * @details + * + * This file contains declarations specific to AMD's unique requirements and + * functionalities for xilffs. + * + * 
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date        Changes
+ * ----- ---- -------- -------------------------------------------------------
+ * 5.2   ht   10/10/23    Added code for versioning of library.
+ *
+ *
+ * + *@note + *****************************************************************************/ +#ifndef XILFFS_H +#define XILFFS_H + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ +#include "xil_util.h" +#include "xil_io.h" +#include "xil_types.h" + +/************************** Constant Definitions *****************************/ +/* Library version info */ +#define XILFFS_MAJOR_VERSION 5U +#define XILFFS_MINOR_VERSION 2U + +/****************** Macros (Inline Functions) Definitions *********************/ + +/*****************************************************************************/ +/** + * + * @brief This function returns the version number of xilffs library. + * + * @return 32-bit version number + * +******************************************************************************/ +static __attribute__((always_inline)) INLINE +u32 Xilffs_GetLibVersion(void) +{ + return (XIL_BUILD_VERSION(XILFFS_MAJOR_VERSION, XILFFS_MINOR_VERSION)); +} + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* XILFFS_H */ diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/xilffs/src/xilffs.cmake b/bsp_z7/ps7_cortexa9_0/libsrc/xilffs/src/xilffs.cmake new file mode 100644 index 0000000..3a5fff7 --- /dev/null +++ b/bsp_z7/ps7_cortexa9_0/libsrc/xilffs/src/xilffs.cmake @@ -0,0 +1,93 @@ +# Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved. +# SPDX-License-Identifier: MIT +cmake_minimum_required(VERSION 3.3) + +SET(XILFFS_fs_interface 1 CACHE STRING "Enables file system with selected interface. Enter 1 for SD. Enter 2 for RAM") +SET_PROPERTY(CACHE XILFFS_fs_interface PROPERTY STRINGS 1 2) +option(XILFFS_read_only "Enables the file system in Read_Only mode if true. ZynqMP fsbl will set this to true" OFF) +option(XILFFS_enable_exfat "0:Disable exFAT, 1:Enable exFAT(Also Enables LFN)" OFF) +SET(XILFFS_use_lfn 0 CACHE STRING "Enables the Long File Name(LFN) support if non-zero. Disabled by default: 0, LFN with static working buffer: 1, Dynamic working buffer: 2 (on stack) or 3 (on heap)") +SET_PROPERTY(CACHE XILFFS_use_lfn PROPERTY STRINGS 0 1 2 3) +option(XILFFS_use_mkfs "Disable(0) or Enable(1) f_mkfs function. ZynqMP fsbl will set this to false" ON) +option(XILFFS_use_trim "Disable(0) or Enable(1) TRIM function. ZynqMP fsbl will set this to false" OFF) +option(XILFFS_enable_multi_partition "0:Single partition, 1:Enable multiple partition" OFF) +SET(XILFFS_num_logical_vol 2 CACHE STRING "Number of volumes (logical drives, from 1 to 10) to be used.") +SET(XILFFS_use_strfunc 0 CACHE STRING "Enables the string functions (valid values 0 to 2).") +SET_PROPERTY(CACHE XILFFS_use_strfunc PROPERTY STRINGS 0 1 2) +SET(XILFFS_set_fs_rpath 0 CACHE STRING "Configures relative path feature (valid values 0 to 2).") +SET_PROPERTY(CACHE XILFFS_set_fs_rpath PROPERTY STRINGS 0 1 2) +option(XILFFS_word_access "Enables word access for misaligned memory access platform" ON) +option(XILFFS_use_chmod "Enables use of CHMOD functionality for changing attributes (valid only with read_only set to false)" OFF) + +SET(XILFFS_ramfs_size 3145728 CACHE STRING "RAM FS size") +SET(XILFFS_ramfs_start_addr CACHE STRING "RAM FS start address") + +if (${XILFFS_fs_interface} EQUAL 2) + set(FILE_SYSTEM_INTERFACE_RAM " ") + set(RAMFS_SIZE ${XILFFS_ramfs_size}) + if(${XILFFS_ramfs_start_addr}) + set(RAMFS_START_ADDR ${XILFFS_ramfs_start_addr}) + else() + set(RAMFS_START_ADDR 0x10000000) + endif() +endif() + +if (${XILFFS_fs_interface} EQUAL 1) + set(FILE_SYSTEM_INTERFACE_SD " ") +endif() + +if (${XILFFS_fs_interface}) + if (${XILFFS_read_only}) + set(FILE_SYSTEM_READ_ONLY " ") + endif() + if (${XILFFS_enable_exfat}) + set(XILFFS_use_lfn 1) + set(FILE_SYSTEM_FS_EXFAT " ") + endif() + if (${XILFFS_use_lfn} GREATER 0) + set(FILE_SYSTEM_USE_LFN ${XILFFS_use_lfn}) + endif() + if (${XILFFS_use_mkfs}) + set(FILE_SYSTEM_USE_MKFS " ") + endif() + if (${XILFFS_enable_multi_partition}) + set(FILE_SYSTEM_MULTI_PARTITION " ") + endif() + if (${XILFFS_use_trim}) + set(FILE_SYSTEM_USE_TRIM " ") + endif() + if (${XILFFS_use_chmod}) + if (${XILFFS_read_only}) + message("WARNING : Cannot Enable CHMOD in read only mode\n") + message("WARNING : File System supports only up to 10 logical drives Setting back the num of vol to 10\n") + else() + set(FILE_SYSTEM_USE_CHMOD " ") + endif() + endif() + + if (${XILFFS_num_logical_vol}) + if (${XILFFS_num_logical_vol} GREATER 10) + message("WARNING : File System supports only up to 10 logical drives Setting back the num of vol to 10\n") + set(FILE_SYSTEM_NUM_LOGIC_VOL 10) + else() + set(FILE_SYSTEM_NUM_LOGIC_VOL ${XILFFS_num_logical_vol}) + endif() + endif() + if (${XILFFS_use_strfunc}) + set(FILE_SYSTEM_USE_STRFUNC ${XILFFS_use_strfunc}) + endif() + if (${XILFFS_set_fs_rpath}) + set(FILE_SYSTEM_SET_FS_RPATH ${XILFFS_set_fs_rpath}) + endif() + + if((NOT "${CMAKE_SYSTEM_PROCESSOR}" STREQUAL "microblaze") AND + (NOT "${CMAKE_SYSTEM_PROCESSOR}" STREQUAL "microblaze_riscv") AND + (NOT "${CMAKE_SYSTEM_PROCESSOR}" STREQUAL "microblazeel") AND + (NOT "${CMAKE_SYSTEM_PROCESSOR}" STREQUAL "plm_microblaze") AND + (NOT "${CMAKE_SYSTEM_PROCESSOR}" STREQUAL "pmu_microblaze") AND + (${XILFFS_word_access})) + set(FILE_SYSTEM_WORD_ACCESS " ") + endif() + +endif() +configure_file(${CMAKE_CURRENT_SOURCE_DIR}/xilffs_config.h.in ${CMAKE_BINARY_DIR}/include/xilffs_config.h) diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/xilffs/src/xilffs_config.h.in b/bsp_z7/ps7_cortexa9_0/libsrc/xilffs/src/xilffs_config.h.in new file mode 100644 index 0000000..a8dd518 --- /dev/null +++ b/bsp_z7/ps7_cortexa9_0/libsrc/xilffs/src/xilffs_config.h.in @@ -0,0 +1,30 @@ +/****************************************************************************** +* Copyright (c) 2023 - 2024 Advanced Micro Devices, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ +#ifndef XILFFS_CONFIG_H +#define XILFFS_CONFIG_H + +#include "xparameters.h" + +#if (defined XPAR_XSDPS_0_BASEADDR) +#cmakedefine FILE_SYSTEM_INTERFACE_SD @FILE_SYSTEM_INTERFACE_SD@ +#endif + +#cmakedefine FILE_SYSTEM_INTERFACE_RAM @FILE_SYSTEM_INTERFACE_RAM@ +#cmakedefine RAMFS_SIZE @RAMFS_SIZE@ +#cmakedefine RAMFS_START_ADDR @RAMFS_START_ADDR@ + +#cmakedefine FILE_SYSTEM_READ_ONLY @FILE_SYSTEM_READ_ONLY@ +#cmakedefine FILE_SYSTEM_FS_EXFAT @FILE_SYSTEM_FS_EXFAT@ +#cmakedefine FILE_SYSTEM_USE_LFN @FILE_SYSTEM_USE_LFN@ +#cmakedefine FILE_SYSTEM_USE_MKFS @FILE_SYSTEM_USE_MKFS@ +#cmakedefine FILE_SYSTEM_USE_TRIM @FILE_SYSTEM_USE_TRIM@ +#cmakedefine FILE_SYSTEM_MULTI_PARTITION @FILE_SYSTEM_MULTI_PARTITION@ +#cmakedefine FILE_SYSTEM_USE_CHMOD @FILE_SYSTEM_USE_CHMOD@ +#cmakedefine FILE_SYSTEM_NUM_LOGIC_VOL @FILE_SYSTEM_NUM_LOGIC_VOL@ +#cmakedefine FILE_SYSTEM_WORD_ACCESS @FILE_SYSTEM_WORD_ACCESS@ +#cmakedefine FILE_SYSTEM_USE_STRFUNC @FILE_SYSTEM_USE_STRFUNC@ +#cmakedefine FILE_SYSTEM_SET_FS_RPATH @FILE_SYSTEM_SET_FS_RPATH@ + +#endif /* XILFFS_CONFIG_H */ diff --git a/bsp_z7/ps7_cortexa9_0/libsrc/xilrsa/data/xilrsa.mld b/bsp_z7/ps7_cortexa9_0/libsrc/xilrsa/data/xilrsa.mld index cdf6b33..8ff8f4b 100644 --- a/bsp_z7/ps7_cortexa9_0/libsrc/xilrsa/data/xilrsa.mld +++ b/bsp_z7/ps7_cortexa9_0/libsrc/xilrsa/data/xilrsa.mld @@ -1,5 +1,6 @@ ############################################################################### # Copyright (c) 2014 - 2020 Xilinx, Inc. All rights reserved. +# Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved. # SPDX-License-Identifier: MIT # # Modification History @@ -22,6 +23,6 @@ BEGIN LIBRARY xilrsa OPTION SUPPORTED_PERIPHERALS = (ps7_cortexa9); OPTION APP_LINKER_FLAGS = "-Wl,--start-group,-lrsa,-lxil,-lgcc,-lc,--end-group"; OPTION desc = "Xilinx RSA Library to access RSA and SHA software algorithms on Zynq "; - OPTION VERSION = 1.6; + OPTION VERSION = 1.8; OPTION NAME = xilrsa; END LIBRARY