diff --git a/CHANGELOG.md b/CHANGELOG.md index 0c7a1e2..2d46aff 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -8,6 +8,10 @@ and this project adheres to [Semantic Versioning](http://semver.org/). ## [unreleased] +## [v0.2.1] + +- README tweaks + ## [v0.2.0] ### Added diff --git a/Cargo.toml b/Cargo.toml index ecbf2fb..7f786b3 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -1,6 +1,6 @@ [package] name = "max116xx-10bit" -version = "0.2.0" +version = "0.2.1" authors = ["Robin Mueller "] edition = "2021" description = "Driver crate for the MAX116xx 10-bit ADC devices" diff --git a/README.md b/README.md index a8452c7..9e9ad30 100644 --- a/README.md +++ b/README.md @@ -9,13 +9,8 @@ This is a platform agnostic Rust driver for the MAX11618-MAX11621, MAX11624 and [ADC devices](https://www.maximintegrated.com/en/products/analog/data-converters/analog-to-digital-converters/MAX11619.html) which uses the [`embedded-hal`](https://github.com/rust-embedded/embedded-hal) traits. -This driver implements basic operations to read raw ADC values: - -- Read ADC values using the SPI clock as an external clock -- Read ADC values using the End-Of-Conversion (EOC) pin - -Currently, the driver only supports operation without a wake-up delay and the EOC read -functionality is still limited. Pull requests to improve this are welcome. +This driver supports most required features but the CNVST pin support is still limited because +the test development board did not have the pin connected. Pull requests to improve this are welcome. # Usage @@ -25,6 +20,6 @@ the appropriate device. The crate uses basic type-level support to prevent using the ADC in a wrong way. The type-level support defaults to an externally clocked device with no wake-up delay. -This crate was tested using the Vorago REB1 development board. You can find an example application -[here](https://egit.irs.uni-stuttgart.de/rust/vorago-reb1/src/branch/main/src/max11619.rs) -and [here](https://egit.irs.uni-stuttgart.de/rust/vorago-reb1/src/branch/main/examples/max11619-adc.rs). +This crate was tested using the Vorago REB1 development board. You can find the example +application [here](https://egit.irs.uni-stuttgart.de/rust/vorago-reb1/src/branch/main/examples/max11619-adc.rs) +using a [thin abstraction layer](https://egit.irs.uni-stuttgart.de/rust/vorago-reb1/src/branch/main/src/max11619.rs)