diff --git a/.gitignore b/.gitignore
index 91f35d4..6a5b49d 100644
--- a/.gitignore
+++ b/.gitignore
@@ -1,5 +1,6 @@
target/
+output.log
/Cargo.lock
output.log
diff --git a/README.md b/README.md
index c20b996..b1e76c9 100644
--- a/README.md
+++ b/README.md
@@ -1,4 +1,4 @@
-
+
[![sat-rs website](https://img.shields.io/badge/sat--rs-website-darkgreen?style=flat)](https://absatsw.irs.uni-stuttgart.de/projects/sat-rs/)
[![sat-rs book](https://img.shields.io/badge/sat--rs-book-darkgreen?style=flat)](https://absatsw.irs.uni-stuttgart.de/projects/sat-rs/book/)
@@ -8,17 +8,27 @@
sat-rs
=========
-This is the repository of the sat-rs framework. Its primary goal is to provide re-usable components
+This is the repository of the sat-rs library. Its primary goal is to provide re-usable components
to write on-board software for remote systems like rovers or satellites. It is specifically written
for the special requirements for these systems. You can find an overview of the project and the
link to the [more high-level sat-rs book](https://absatsw.irs.uni-stuttgart.de/projects/sat-rs/)
at the [IRS software projects website](https://absatsw.irs.uni-stuttgart.de/projects/sat-rs/).
+This is early-stage software. Important features are missing. New releases
+with breaking changes are released regularly, with all changes documented inside respective
+changelog files. You should only use this library if your are willing to work in this
+environment.
+
A lot of the architecture and general design considerations are based on the
[FSFW](https://egit.irs.uni-stuttgart.de/fsfw/fsfw) C++ framework which has flight heritage
through the 2 missions [FLP](https://www.irs.uni-stuttgart.de/en/research/satellitetechnology-and-instruments/smallsatelliteprogram/flying-laptop/)
and [EIVE](https://www.irs.uni-stuttgart.de/en/research/satellitetechnology-and-instruments/smallsatelliteprogram/EIVE/).
+This framework is in the early stages of development. Important features are missing. New releases
+with breaking changes are released regularly, with all changes documented inside respective
+changelog files. You should only use this framework if your are willing to work in this
+environment.
+
# Overview
This project currently contains following crates:
@@ -35,7 +45,7 @@ This project currently contains following crates:
* [`satrs-mib`](https://egit.irs.uni-stuttgart.de/rust/sat-rs/src/branch/main/satrs-mib):
Components to build a mission information base from the on-board software directly.
* [`satrs-example-stm32f3-disco`](https://egit.irs.uni-stuttgart.de/rust/sat-rs/src/branch/main/satrs-example-stm32f3-disco):
- Example of a simple example on-board software using sat-rs components on a bare-metal system
+ Example of a simple example using low-level sat-rs components on a bare-metal system
with constrained resources.
Each project has its own `CHANGELOG.md`.
diff --git a/coverage.py b/coverage.py
index 3b1c3c4..c932d9a 100755
--- a/coverage.py
+++ b/coverage.py
@@ -47,7 +47,7 @@ def main():
parser.add_argument(
"-p",
"--package",
- choices=["satrs", "satrs-minisim"],
+ choices=["satrs", "satrs-minisim", "satrs-example"],
default="satrs",
help="Choose project to generate coverage for",
)
diff --git a/misc/satrs-logo-v2.png b/misc/satrs-logo-v2.png
new file mode 100644
index 0000000..76859f8
Binary files /dev/null and b/misc/satrs-logo-v2.png differ
diff --git a/satrs-book/src/actions.md b/satrs-book/src/actions.md
index 0e092d9..bed9fdb 100644
--- a/satrs-book/src/actions.md
+++ b/satrs-book/src/actions.md
@@ -15,7 +15,7 @@ action commanding could look like.
2. Target ID and Action String based. The target ID is the same as in the first proposal, but
the unique action is identified by a string.
-The framework provides an `ActionRequest` abstraction to model both of these cases.
+The library provides an `ActionRequest` abstraction to model both of these cases.
## Commanding with ECSS PUS 8
diff --git a/satrs-book/src/communication.md b/satrs-book/src/communication.md
index 9e7a4ac..f102f6b 100644
--- a/satrs-book/src/communication.md
+++ b/satrs-book/src/communication.md
@@ -20,7 +20,7 @@ components.
1. [UDP TMTC Server](https://docs.rs/satrs/latest/satrs/hal/host/udp_server/index.html).
UDP is already packet based which makes it an excellent fit for exchanging space packets.
2. [TCP TMTC Server Components](https://docs.rs/satrs/latest/satrs/hal/std/tcp_server/index.html).
- TCP is a stream based protocol, so the framework provides building blocks to parse telemetry
+ TCP is a stream based protocol, so the library provides building blocks to parse telemetry
from an arbitrary bytestream. Two concrete implementations are provided:
- [TCP spacepackets server](https://docs.rs/satrs/latest/satrs/hal/std/tcp_server/struct.TcpSpacepacketsServer.html)
to parse tightly packed CCSDS Spacepackets.
diff --git a/satrs-book/src/design.md b/satrs-book/src/design.md
index 9ec7317..ef14250 100644
--- a/satrs-book/src/design.md
+++ b/satrs-book/src/design.md
@@ -1,13 +1,14 @@
-# Framework Design
+# Library Design
Satellites and space systems in general are complex systems with a wide range of requirements for
-both the hardware and the software. Consequently, the general design of the framework is centered
+both the hardware and the software. Consequently, the general design of the library is centered
around many light-weight components which try to impose as few restrictions as possible on how to
-solve certain problems.
+solve certain problems. This is also the reason why sat-rs is explicitely called a library
+instead of a framework.
There are still a lot of common patterns and architectures across these systems where guidance
of how to solve a problem and a common structure would still be extremely useful to avoid pitfalls
-which were already solved and to avoid boilerplate code. This framework tries to provide this
+which were already solved and to avoid boilerplate code. This library tries to provide this
structure and guidance the following way:
1. Providing this book which explains the architecture and design patterns in respect to common
@@ -18,7 +19,7 @@ structure and guidance the following way:
3. Providing a good test suite. This includes both unittests and integration tests. The integration
tests can also serve as smaller usage examples than the large `satrs-example` application.
-This framework has special support for standards used in the space industry. This especially
+This library has special support for standards used in the space industry. This especially
includes standards provided by Consultative Committee for Space Data Systems (CCSDS) and European
Cooperation for Space Standardization (ECSS). It does not enforce using any of those standards,
but it is always recommended to use some sort of standard for interoperability.
@@ -30,10 +31,10 @@ Flying Laptop Project by the University of Stuttgart with Airbus Defence and Spa
It has flight heritage through the 2 mssions [FLP](https://www.irs.uni-stuttgart.de/en/research/satellitetechnology-and-instruments/smallsatelliteprogram/flying-laptop/)
and [EIVE](https://www.irs.uni-stuttgart.de/en/research/satellitetechnology-and-instruments/smallsatelliteprogram/EIVE/).
Therefore, a lot of the design concepts were ported more or less unchanged to the `sat-rs`
-framework.
+library.
FLP is a medium-size small satellite with a higher budget and longer development time than EIVE,
which allowed to build a highly reliable system while EIVE is a smaller 6U+ cubesat which had a
-shorter development cycle and was built using cheaper COTS components. This framework also tries
+shorter development cycle and was built using cheaper COTS components. This library also tries
to accumulate the knowledge of developing the OBSW and operating the satellite for both these
different systems and provide a solution for a wider range of small satellite systems.
diff --git a/satrs-book/src/example.md b/satrs-book/src/example.md
index 12fec83..4e1f590 100644
--- a/satrs-book/src/example.md
+++ b/satrs-book/src/example.md
@@ -1,6 +1,6 @@
# sat-rs Example Application
-The `sat-rs` framework includes a monolithic example application which can be found inside
+The `sat-rs` library includes a monolithic example application which can be found inside
the [`satrs-example`](https://egit.irs.uni-stuttgart.de/rust/sat-rs/src/branch/main/satrs-example)
subdirectory of the repository. The primary purpose of this example application is to show how
the various components of the sat-rs framework could be used as part of a larger on-board
diff --git a/satrs-book/src/introduction.md b/satrs-book/src/introduction.md
index f448441..babd8ca 100644
--- a/satrs-book/src/introduction.md
+++ b/satrs-book/src/introduction.md
@@ -1,7 +1,7 @@
The sat-rs book
======
-This book is the primary information resource for the [sat-rs framework](https://egit.irs.uni-stuttgart.de/rust/sat-rs)
+This book is the primary information resource for the [sat-rs library](https://egit.irs.uni-stuttgart.de/rust/sat-rs)
in addition to the regular API documentation. It contains the following resources:
1. Architecture informations and consideration which would exceeds the scope of the regular API.
@@ -12,10 +12,15 @@ in addition to the regular API documentation. It contains the following resource
# Introduction
-The primary goal of the sat-rs framework is to provide re-usable components
+The primary goal of the sat-rs library is to provide re-usable components
to write on-board software for remote systems like rovers or satellites. It is specifically written
for the special requirements for these systems.
+It should be noted that sat-rs is early-stage software. Important features are missing. New releases
+with breaking changes are released regularly, with all changes documented inside respective
+changelog files. You should only use this library if your are willing to work in this
+environment.
+
A lot of the architecture and general design considerations are based on the
[FSFW](https://egit.irs.uni-stuttgart.de/fsfw/fsfw) C++ framework which has flight heritage
through the 2 missions [FLP](https://www.irs.uni-stuttgart.de/en/research/satellitetechnology-and-instruments/smallsatelliteprogram/flying-laptop/)
diff --git a/satrs-example-stm32f3-disco/.cargo/def_config.toml b/satrs-example-stm32f3-disco/.cargo/def_config.toml
index 4150986..4598c09 100644
--- a/satrs-example-stm32f3-disco/.cargo/def_config.toml
+++ b/satrs-example-stm32f3-disco/.cargo/def_config.toml
@@ -5,11 +5,17 @@
# runner = "arm-none-eabi-gdb -q -x openocd.gdb"
# runner = "gdb-multiarch -q -x openocd.gdb"
# runner = "gdb -q -x openocd.gdb"
-# runner = "probe-run --chip STM32F303VCTx --connect-under-reset"
+runner = "probe-rs run --chip STM32F303VCTx"
rustflags = [
+ "-C", "linker=flip-link",
# LLD (shipped with the Rust toolchain) is used as the default linker
"-C", "link-arg=-Tlink.x",
+ "-C", "link-arg=-Tdefmt.x",
+
+ # This is needed if your flash or ram addresses are not aligned to 0x10000 in memory.x
+ # See https://github.com/rust-embedded/cortex-m-quickstart/pull/95
+ "-C", "link-arg=--nmagic",
# if you run into problems with LLD switch to the GNU linker by commenting out
# this line
@@ -26,3 +32,6 @@ rustflags = [
[build]
# comment out the following line if you intend to run unit tests on host machine
target = "thumbv7em-none-eabihf" # Cortex-M4F and Cortex-M7F (with FPU)
+
+[env]
+DEFMT_LOG = "info"
\ No newline at end of file
diff --git a/satrs-example-stm32f3-disco/Cargo.lock b/satrs-example-stm32f3-disco/Cargo.lock
index 9043d7a..fffb020 100644
--- a/satrs-example-stm32f3-disco/Cargo.lock
+++ b/satrs-example-stm32f3-disco/Cargo.lock
@@ -22,9 +22,9 @@ dependencies = [
[[package]]
name = "autocfg"
-version = "1.1.0"
+version = "1.2.0"
source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "d468802bab17cbc0cc575e9b053f41e72aa36bfa6b7f55e3529ffa43161b97fa"
+checksum = "f1fdabc7756949593fe60f30ec81974b613357de856987752631dea1e3394c80"
[[package]]
name = "bare-metal"
@@ -88,19 +88,13 @@ checksum = "baf1de4339761588bc0619e3cbc0120ee582ebb74b53b4efbf79117bd2da40fd"
[[package]]
name = "chrono"
-version = "0.4.35"
+version = "0.4.37"
source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "8eaf5903dcbc0a39312feb77df2ff4c76387d591b9fc7b04a238dcf8bb62639a"
+checksum = "8a0d04d43504c61aa6c7531f1871dd0d418d91130162063b789da00fd7057a5e"
dependencies = [
"num-traits",
]
-[[package]]
-name = "cobs"
-version = "0.2.3"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "67ba02a97a2bd10f4b59b25c7973101c79642302776489e030cd13cdab09ed15"
-
[[package]]
name = "cobs"
version = "0.2.3"
@@ -139,6 +133,15 @@ dependencies = [
"syn 1.0.109",
]
+[[package]]
+name = "cortex-m-semihosting"
+version = "0.5.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "c23234600452033cc77e4b761e740e02d2c4168e11dbf36ab14a0f58973592b0"
+dependencies = [
+ "cortex-m",
+]
+
[[package]]
name = "crc"
version = "3.0.1"
@@ -180,7 +183,7 @@ dependencies = [
"ident_case",
"proc-macro2",
"quote",
- "syn 2.0.53",
+ "syn 2.0.58",
]
[[package]]
@@ -191,7 +194,72 @@ checksum = "a668eda54683121533a393014d8692171709ff57a7d61f187b6e782719f8933f"
dependencies = [
"darling_core",
"quote",
- "syn 2.0.53",
+ "syn 2.0.58",
+]
+
+[[package]]
+name = "defmt"
+version = "0.3.6"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "3939552907426de152b3c2c6f51ed53f98f448babd26f28694c95f5906194595"
+dependencies = [
+ "bitflags",
+ "defmt-macros",
+]
+
+[[package]]
+name = "defmt-brtt"
+version = "0.1.1"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "c2f0ac3635d0c89d12b8101fcb44a7625f5f030a1c0491124b74467eb5a58a78"
+dependencies = [
+ "critical-section",
+ "defmt",
+]
+
+[[package]]
+name = "defmt-macros"
+version = "0.3.7"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "18bdc7a7b92ac413e19e95240e75d3a73a8d8e78aa24a594c22cbb4d44b4bbda"
+dependencies = [
+ "defmt-parser",
+ "proc-macro-error",
+ "proc-macro2",
+ "quote",
+ "syn 2.0.58",
+]
+
+[[package]]
+name = "defmt-parser"
+version = "0.3.4"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "ff4a5fefe330e8d7f31b16a318f9ce81000d8e35e69b93eae154d16d2278f70f"
+dependencies = [
+ "thiserror",
+]
+
+[[package]]
+name = "defmt-test"
+version = "0.3.2"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "290966e8c38f94b11884877242de876280d0eab934900e9642d58868e77c5df1"
+dependencies = [
+ "cortex-m-rt",
+ "cortex-m-semihosting",
+ "defmt",
+ "defmt-test-macros",
+]
+
+[[package]]
+name = "defmt-test-macros"
+version = "0.3.1"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "984bc6eca246389726ac2826acc2488ca0fe5fcd6b8d9b48797021951d76a125"
+dependencies = [
+ "proc-macro2",
+ "quote",
+ "syn 2.0.58",
]
[[package]]
@@ -257,7 +325,7 @@ dependencies = [
"darling",
"proc-macro2",
"quote",
- "syn 2.0.53",
+ "syn 2.0.58",
]
[[package]]
@@ -371,21 +439,6 @@ dependencies = [
"hashbrown",
]
-[[package]]
-name = "itm_logger"
-version = "0.1.3-alpha.0"
-source = "git+https://github.com/robamu/itm_logger.rs.git?branch=all_features#83ee7a6c57f525a70d0cc5bb7e65826d0ce938a0"
-dependencies = [
- "cortex-m",
- "log",
-]
-
-[[package]]
-name = "log"
-version = "0.4.21"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "90ed8c1e510134f979dbc4f070f87d4313098b704861a105fe34231c70a3901c"
-
[[package]]
name = "lsm303dlhc"
version = "0.2.0"
@@ -500,16 +553,17 @@ checksum = "681030a937600a36906c185595136d26abfebb4aa9c65701cefcaf8578bb982b"
dependencies = [
"proc-macro2",
"quote",
- "syn 2.0.53",
+ "syn 2.0.58",
]
[[package]]
-name = "panic-itm"
-version = "0.4.2"
+name = "panic-probe"
+version = "0.3.1"
source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "3d577d97d1b31268087b6dddf2470e6794ef5eee87d9dca7fcd0481695391a4c"
+checksum = "aa6fa5645ef5a760cd340eaa92af9c1ce131c8c09e7f8926d8a24b59d26652b9"
dependencies = [
"cortex-m",
+ "defmt",
]
[[package]]
@@ -520,9 +574,9 @@ checksum = "de3145af08024dea9fa9914f381a17b8fc6034dfb00f3a84013f7ff43f29ed4c"
[[package]]
name = "pin-project-lite"
-version = "0.2.13"
+version = "0.2.14"
source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "8afb450f006bf6385ca15ef45d71d2288452bc3683ce2e2cacc0d18e4be60b58"
+checksum = "bda66fc9667c18cb2758a2ac84d1167245054bcf85d5d1aaa6923f45801bdd02"
[[package]]
name = "pin-utils"
@@ -574,9 +628,9 @@ dependencies = [
[[package]]
name = "rtcc"
-version = "0.3.1"
+version = "0.3.2"
source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "f4fbd0d5bed2b76e27a7ef872568b34072c1af94c277cd52c17a89d54673b3fe"
+checksum = "95973c3a0274adc4f3c5b70d2b5b85618d6de9559a6737d3293ecae9a2fc0839"
dependencies = [
"chrono",
]
@@ -620,7 +674,7 @@ dependencies = [
"proc-macro-error",
"proc-macro2",
"quote",
- "syn 2.0.53",
+ "syn 2.0.58",
]
[[package]]
@@ -669,10 +723,8 @@ dependencies = [
[[package]]
name = "satrs"
version = "0.2.0-rc.0"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "c8cb19cba46a45047ff0879ebfbf9d6ae1c5b2e0e38b2e08760b10a441d4dae6"
dependencies = [
- "cobs 0.2.3 (registry+https://github.com/rust-lang/crates.io-index)",
+ "cobs",
"crc",
"delegate",
"num-traits",
@@ -687,14 +739,17 @@ dependencies = [
name = "satrs-example-stm32f3-disco"
version = "0.1.0"
dependencies = [
- "cobs 0.2.3 (git+https://github.com/robamu/cobs.rs.git?branch=all_features)",
+ "cobs",
"cortex-m",
"cortex-m-rt",
+ "cortex-m-semihosting",
+ "defmt",
+ "defmt-brtt",
+ "defmt-test",
"embedded-hal 0.2.7",
"enumset",
"heapless",
- "itm_logger",
- "panic-itm",
+ "panic-probe",
"rtic",
"rtic-monotonics",
"satrs",
@@ -704,9 +759,7 @@ dependencies = [
[[package]]
name = "satrs-shared"
-version = "0.1.2"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "75a402ba556a7f5eef707035b45e64a3259b09674311e98697f3dd0508a1bf51"
+version = "0.1.3"
dependencies = [
"spacepackets",
]
@@ -746,12 +799,12 @@ checksum = "3c5e1a9a646d36c3599cd173a41282daf47c44583ad367b8e6837255952e5c67"
[[package]]
name = "spacepackets"
-version = "0.10.0"
+version = "0.11.0-rc.2"
source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "28246ae2451af240c3e3ff3c51363c7b6ad565ca6aa9bad23b8c725687c485e1"
+checksum = "c2cfd5f9a4c7f10714d21f9bc61f2d176cb7ae092cdd687e7ade2d4e6f7d7125"
dependencies = [
- "chrono",
"crc",
+ "defmt",
"delegate",
"num-traits",
"num_enum",
@@ -846,15 +899,35 @@ dependencies = [
[[package]]
name = "syn"
-version = "2.0.53"
+version = "2.0.58"
source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "7383cd0e49fff4b6b90ca5670bfd3e9d6a733b3f90c686605aa7eec8c4996032"
+checksum = "44cfb93f38070beee36b3fef7d4f5a16f27751d94b187b666a5cc5e9b0d30687"
dependencies = [
"proc-macro2",
"quote",
"unicode-ident",
]
+[[package]]
+name = "thiserror"
+version = "1.0.58"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "03468839009160513471e86a034bb2c5c0e4baae3b43f79ffc55c4a5427b3297"
+dependencies = [
+ "thiserror-impl",
+]
+
+[[package]]
+name = "thiserror-impl"
+version = "1.0.58"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "c61f3ba182994efc43764a46c018c347bc492c79f024e705f46567b418f6d4f7"
+dependencies = [
+ "proc-macro2",
+ "quote",
+ "syn 2.0.58",
+]
+
[[package]]
name = "typenum"
version = "1.17.0"
@@ -918,5 +991,5 @@ checksum = "9ce1b18ccd8e73a9321186f97e46f9f04b778851177567b1975109d26a08d2a6"
dependencies = [
"proc-macro2",
"quote",
- "syn 2.0.53",
+ "syn 2.0.58",
]
diff --git a/satrs-example-stm32f3-disco/Cargo.toml b/satrs-example-stm32f3-disco/Cargo.toml
index 4337919..c149dd4 100644
--- a/satrs-example-stm32f3-disco/Cargo.toml
+++ b/satrs-example-stm32f3-disco/Cargo.toml
@@ -2,13 +2,18 @@
name = "satrs-example-stm32f3-disco"
version = "0.1.0"
edition = "2021"
+default-run = "satrs-example-stm32f3-disco"
# See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html
[dependencies]
cortex-m = { version = "0.7", features = ["critical-section-single-core"] }
cortex-m-rt = "0.7"
+defmt = "0.3"
+defmt-brtt = { version = "0.1", default-features = false, features = ["rtt"] }
+panic-probe = { version = "0.3", features = ["print-defmt"] }
embedded-hal = "0.2.7"
+cortex-m-semihosting = "0.5.0"
enumset = "1"
heapless = "0.8"
@@ -25,14 +30,6 @@ git = "https://github.com/robamu/cobs.rs.git"
branch = "all_features"
default-features = false
-[dependencies.panic-itm]
-version = "0.4"
-
-[dependencies.itm_logger]
-git = "https://github.com/robamu/itm_logger.rs.git"
-branch = "all_features"
-version = "0.1.3-alpha.0"
-
[dependencies.stm32f3xx-hal]
git = "https://github.com/robamu/stm32f3xx-hal"
version = "0.11.0-alpha.0"
@@ -49,17 +46,38 @@ branch = "complete-dma-update-hal"
# path = "../stm32f3-discovery"
[dependencies.satrs]
-# git = "https://egit.irs.uni-stuttgart.de/rust/satrs-core.git"
-version = "0.2.0-rc.0"
+path = "../satrs"
default-features = false
+features = ["defmt"]
-# this lets you use `cargo fix`!
-# [[bin]]
-# name = "stm32f3-blinky"
-# test = false
-# bench = false
+[dev-dependencies]
+defmt-test = "0.3"
+# cargo test
+[profile.test]
+codegen-units = 1
+debug = 2
+debug-assertions = true # <-
+incremental = false
+opt-level = "s" # <-
+overflow-checks = true # <-
+
+# cargo build/run --release
[profile.release]
-codegen-units = 1 # better optimizations
-debug = true # symbols are nice and they don't increase the size on Flash
-lto = true # better optimizations
+codegen-units = 1
+debug = 2
+debug-assertions = false # <-
+incremental = false
+lto = 'fat'
+opt-level = "s" # <-
+overflow-checks = false # <-
+
+# cargo test --release
+[profile.bench]
+codegen-units = 1
+debug = 2
+debug-assertions = false # <-
+incremental = false
+lto = 'fat'
+opt-level = "s" # <-
+overflow-checks = false # <-
diff --git a/satrs-example-stm32f3-disco/README.md b/satrs-example-stm32f3-disco/README.md
index 9d502fa..090faea 100644
--- a/satrs-example-stm32f3-disco/README.md
+++ b/satrs-example-stm32f3-disco/README.md
@@ -2,26 +2,24 @@ sat-rs example for the STM32F3-Discovery board
=======
This example application shows how the [sat-rs framework](https://egit.irs.uni-stuttgart.de/rust/satrs-launchpad)
-can be used on an embedded target. It also shows how a relatively simple OBSW could be built when no
-standard runtime is available. It uses [RTIC](https://rtic.rs/1/book/en/) as the concurrency
-framework.
+can be used on an embedded target.
+It also shows how a relatively simple OBSW could be built when no standard runtime is available.
+It uses [RTIC](https://rtic.rs/1/book/en/) as the concurrency framework and the
+[defmt](https://defmt.ferrous-systems.com/) framework for logging.
The STM32F3-Discovery device was picked because it is a cheap Cortex-M4 based device which is also
used by the [Rust Embedded Book](https://docs.rust-embedded.org/book/intro/hardware.html) and the
[Rust Discovery](https://docs.rust-embedded.org/discovery/f3discovery/) book as an introduction
to embedded Rust.
-If you would like to access the ITM log output, you need to connect the PB3 pin to the CN3 pin
-of the SWD header like [shown here](https://docs.rust-embedded.org/discovery/f3discovery/06-hello-world/index.html).
-
## Pre-Requisites
Make sure the following tools are installed:
-1. `openocd`: This is the debug server used to debug the STM32F3. You can install this from
- [`xPacks`](https://xpack.github.io/dev-tools/openocd/install/). You can also use the one provided
- by a STM32Cube installation.
-2. A debugger like `arm-none-eabi-gdb` or `gdb-multiarch`.
+1. [`probe-rs`](https://probe.rs/): Application used to flash and debug the MCU.
+2. Optional and recommended: [VS Code](https://code.visualstudio.com/) with
+ [probe-rs plugin](https://marketplace.visualstudio.com/items?itemName=probe-rs.probe-rs-debugger)
+ for debugging.
## Preparing Rust and the repository
@@ -52,23 +50,19 @@ you can simply build the application with
cargo build
```
-## Flashing and Debugging from the command line
+## Flashing from the command line
-Make sure you have `openocd` and `itmdump` installed first.
+You can flash the application from the command line using `probe-rs`:
-1. Configure a runner inside your `.cargo/config.toml` file by uncommenting an appropriate line
- depending on the application you want to use for debugging
-2. Start `openocd` inside the project folder. This will start `openocd` with the provided
- `openocd.cfg` configuration file.
-3. Use `cargo run` to flash and debug the application in your terminal
-4. Use `itmdump -F -f itm.txt` to print the logs received from the STM32F3 device. Please note
- that the PB3 and CN3 pin of the SWD header need to be connected for this to work.
+```sh
+probe-rs run --chip STM32F303VCTx
+```
## Debugging with VS Code
The STM32F3-Discovery comes with an on-board ST-Link so all that is required to flash and debug
-the board is a Mini-USB cable. The code in this repository was debugged using `openocd`
-and the VS Code [`Cortex-Debug` plugin](https://marketplace.visualstudio.com/items?itemName=marus25.cortex-debug).
+the board is a Mini-USB cable. The code in this repository was debugged using [`probe-rs`](https://probe.rs/docs/tools/debuggerA)
+and the VS Code [`probe-rs` plugin](https://marketplace.visualstudio.com/items?itemName=probe-rs.probe-rs-debugger).
Make sure to install this plugin first.
Sample configuration files are provided inside the `vscode` folder.
@@ -80,19 +74,11 @@ to automatically rebuild and flash your application.
The `tasks.json` and `launch.json` files are generic and you can use them immediately by opening
the folder in VS code or adding it to a workspace.
-If you would like to use a custom GDB application, you can specify the gdb binary in the following
-configuration variables in your `settings.json`:
-
-- `"cortex-debug.gdbPath"`
-- `"cortex-debug.gdbPath.linux"`
-- `"cortex-debug.gdbPath.windows"`
-- `"cortex-debug.gdbPath.osx"`
-
## Commanding with Python
When the SW is running on the Discovery board, you can command the MCU via a serial interface,
using COBS encoded PUS packets.
-
+
It is recommended to use a virtual environment to do this. To set up one in the command line,
you can use `python3 -m venv venv` on Unix systems or `py -m venv venv` on Windows systems.
After doing this, you can check the [venv tutorial](https://docs.python.org/3/tutorial/venv.html)
@@ -111,3 +97,18 @@ A default configuration file for the python application is provided and can be u
```sh
cp def_tmtc_conf.json tmtc_conf.json
```
+
+After that, you can for example send a ping to the MCU using the following command
+
+```sh
+./main.py -p /ping
+```
+
+You can configure the blinky frequency using
+
+```sh
+./main.py -p /change_blink_freq
+```
+
+All these commands will package a PUS telecommand which will be sent to the MCU using the COBS
+format as the packet framing format.
diff --git a/satrs-example-stm32f3-disco/STM32F303.svd b/satrs-example-stm32f3-disco/STM32F303.svd
new file mode 100644
index 0000000..63fb761
--- /dev/null
+++ b/satrs-example-stm32f3-disco/STM32F303.svd
@@ -0,0 +1,38601 @@
+
+
+
+ STM32F303
+ 1.8
+ STM32F303
+
+ CM4
+ r1p0
+ little
+ true
+ true
+ 3
+ false
+
+ 8
+ 32
+ 0x20
+ 0x0
+ 0xFFFFFFFF
+
+
+ GPIOA
+ General-purpose I/Os
+ GPIO
+ 0x48000000
+
+ 0x0
+ 0x400
+ registers
+
+
+
+ MODER
+ MODER
+ GPIO port mode register
+ 0x0
+ 0x20
+ read-write
+ 0x28000000
+
+
+ MODER15
+ Port x configuration bits (y =
+ 0..15)
+ 30
+ 2
+
+
+ MODER14
+ Port x configuration bits (y =
+ 0..15)
+ 28
+ 2
+
+
+ MODER13
+ Port x configuration bits (y =
+ 0..15)
+ 26
+ 2
+
+
+ MODER12
+ Port x configuration bits (y =
+ 0..15)
+ 24
+ 2
+
+
+ MODER11
+ Port x configuration bits (y =
+ 0..15)
+ 22
+ 2
+
+
+ MODER10
+ Port x configuration bits (y =
+ 0..15)
+ 20
+ 2
+
+
+ MODER9
+ Port x configuration bits (y =
+ 0..15)
+ 18
+ 2
+
+
+ MODER8
+ Port x configuration bits (y =
+ 0..15)
+ 16
+ 2
+
+
+ MODER7
+ Port x configuration bits (y =
+ 0..15)
+ 14
+ 2
+
+
+ MODER6
+ Port x configuration bits (y =
+ 0..15)
+ 12
+ 2
+
+
+ MODER5
+ Port x configuration bits (y =
+ 0..15)
+ 10
+ 2
+
+
+ MODER4
+ Port x configuration bits (y =
+ 0..15)
+ 8
+ 2
+
+
+ MODER3
+ Port x configuration bits (y =
+ 0..15)
+ 6
+ 2
+
+
+ MODER2
+ Port x configuration bits (y =
+ 0..15)
+ 4
+ 2
+
+
+ MODER1
+ Port x configuration bits (y =
+ 0..15)
+ 2
+ 2
+
+
+ MODER0
+ Port x configuration bits (y =
+ 0..15)
+ 0
+ 2
+
+
+
+
+ OTYPER
+ OTYPER
+ GPIO port output type register
+ 0x4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ OT15
+ Port x configuration bits (y =
+ 0..15)
+ 15
+ 1
+
+
+ OT14
+ Port x configuration bits (y =
+ 0..15)
+ 14
+ 1
+
+
+ OT13
+ Port x configuration bits (y =
+ 0..15)
+ 13
+ 1
+
+
+ OT12
+ Port x configuration bits (y =
+ 0..15)
+ 12
+ 1
+
+
+ OT11
+ Port x configuration bits (y =
+ 0..15)
+ 11
+ 1
+
+
+ OT10
+ Port x configuration bits (y =
+ 0..15)
+ 10
+ 1
+
+
+ OT9
+ Port x configuration bits (y =
+ 0..15)
+ 9
+ 1
+
+
+ OT8
+ Port x configuration bits (y =
+ 0..15)
+ 8
+ 1
+
+
+ OT7
+ Port x configuration bits (y =
+ 0..15)
+ 7
+ 1
+
+
+ OT6
+ Port x configuration bits (y =
+ 0..15)
+ 6
+ 1
+
+
+ OT5
+ Port x configuration bits (y =
+ 0..15)
+ 5
+ 1
+
+
+ OT4
+ Port x configuration bits (y =
+ 0..15)
+ 4
+ 1
+
+
+ OT3
+ Port x configuration bits (y =
+ 0..15)
+ 3
+ 1
+
+
+ OT2
+ Port x configuration bits (y =
+ 0..15)
+ 2
+ 1
+
+
+ OT1
+ Port x configuration bits (y =
+ 0..15)
+ 1
+ 1
+
+
+ OT0
+ Port x configuration bits (y =
+ 0..15)
+ 0
+ 1
+
+
+
+
+ OSPEEDR
+ OSPEEDR
+ GPIO port output speed
+ register
+ 0x8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ OSPEEDR15
+ Port x configuration bits (y =
+ 0..15)
+ 30
+ 2
+
+
+ OSPEEDR14
+ Port x configuration bits (y =
+ 0..15)
+ 28
+ 2
+
+
+ OSPEEDR13
+ Port x configuration bits (y =
+ 0..15)
+ 26
+ 2
+
+
+ OSPEEDR12
+ Port x configuration bits (y =
+ 0..15)
+ 24
+ 2
+
+
+ OSPEEDR11
+ Port x configuration bits (y =
+ 0..15)
+ 22
+ 2
+
+
+ OSPEEDR10
+ Port x configuration bits (y =
+ 0..15)
+ 20
+ 2
+
+
+ OSPEEDR9
+ Port x configuration bits (y =
+ 0..15)
+ 18
+ 2
+
+
+ OSPEEDR8
+ Port x configuration bits (y =
+ 0..15)
+ 16
+ 2
+
+
+ OSPEEDR7
+ Port x configuration bits (y =
+ 0..15)
+ 14
+ 2
+
+
+ OSPEEDR6
+ Port x configuration bits (y =
+ 0..15)
+ 12
+ 2
+
+
+ OSPEEDR5
+ Port x configuration bits (y =
+ 0..15)
+ 10
+ 2
+
+
+ OSPEEDR4
+ Port x configuration bits (y =
+ 0..15)
+ 8
+ 2
+
+
+ OSPEEDR3
+ Port x configuration bits (y =
+ 0..15)
+ 6
+ 2
+
+
+ OSPEEDR2
+ Port x configuration bits (y =
+ 0..15)
+ 4
+ 2
+
+
+ OSPEEDR1
+ Port x configuration bits (y =
+ 0..15)
+ 2
+ 2
+
+
+ OSPEEDR0
+ Port x configuration bits (y =
+ 0..15)
+ 0
+ 2
+
+
+
+
+ PUPDR
+ PUPDR
+ GPIO port pull-up/pull-down
+ register
+ 0xC
+ 0x20
+ read-write
+ 0x24000000
+
+
+ PUPDR15
+ Port x configuration bits (y =
+ 0..15)
+ 30
+ 2
+
+
+ PUPDR14
+ Port x configuration bits (y =
+ 0..15)
+ 28
+ 2
+
+
+ PUPDR13
+ Port x configuration bits (y =
+ 0..15)
+ 26
+ 2
+
+
+ PUPDR12
+ Port x configuration bits (y =
+ 0..15)
+ 24
+ 2
+
+
+ PUPDR11
+ Port x configuration bits (y =
+ 0..15)
+ 22
+ 2
+
+
+ PUPDR10
+ Port x configuration bits (y =
+ 0..15)
+ 20
+ 2
+
+
+ PUPDR9
+ Port x configuration bits (y =
+ 0..15)
+ 18
+ 2
+
+
+ PUPDR8
+ Port x configuration bits (y =
+ 0..15)
+ 16
+ 2
+
+
+ PUPDR7
+ Port x configuration bits (y =
+ 0..15)
+ 14
+ 2
+
+
+ PUPDR6
+ Port x configuration bits (y =
+ 0..15)
+ 12
+ 2
+
+
+ PUPDR5
+ Port x configuration bits (y =
+ 0..15)
+ 10
+ 2
+
+
+ PUPDR4
+ Port x configuration bits (y =
+ 0..15)
+ 8
+ 2
+
+
+ PUPDR3
+ Port x configuration bits (y =
+ 0..15)
+ 6
+ 2
+
+
+ PUPDR2
+ Port x configuration bits (y =
+ 0..15)
+ 4
+ 2
+
+
+ PUPDR1
+ Port x configuration bits (y =
+ 0..15)
+ 2
+ 2
+
+
+ PUPDR0
+ Port x configuration bits (y =
+ 0..15)
+ 0
+ 2
+
+
+
+
+ IDR
+ IDR
+ GPIO port input data register
+ 0x10
+ 0x20
+ read-only
+ 0x00000000
+
+
+ IDR15
+ Port input data (y =
+ 0..15)
+ 15
+ 1
+
+
+ IDR14
+ Port input data (y =
+ 0..15)
+ 14
+ 1
+
+
+ IDR13
+ Port input data (y =
+ 0..15)
+ 13
+ 1
+
+
+ IDR12
+ Port input data (y =
+ 0..15)
+ 12
+ 1
+
+
+ IDR11
+ Port input data (y =
+ 0..15)
+ 11
+ 1
+
+
+ IDR10
+ Port input data (y =
+ 0..15)
+ 10
+ 1
+
+
+ IDR9
+ Port input data (y =
+ 0..15)
+ 9
+ 1
+
+
+ IDR8
+ Port input data (y =
+ 0..15)
+ 8
+ 1
+
+
+ IDR7
+ Port input data (y =
+ 0..15)
+ 7
+ 1
+
+
+ IDR6
+ Port input data (y =
+ 0..15)
+ 6
+ 1
+
+
+ IDR5
+ Port input data (y =
+ 0..15)
+ 5
+ 1
+
+
+ IDR4
+ Port input data (y =
+ 0..15)
+ 4
+ 1
+
+
+ IDR3
+ Port input data (y =
+ 0..15)
+ 3
+ 1
+
+
+ IDR2
+ Port input data (y =
+ 0..15)
+ 2
+ 1
+
+
+ IDR1
+ Port input data (y =
+ 0..15)
+ 1
+ 1
+
+
+ IDR0
+ Port input data (y =
+ 0..15)
+ 0
+ 1
+
+
+
+
+ ODR
+ ODR
+ GPIO port output data register
+ 0x14
+ 0x20
+ read-write
+ 0x00000000
+
+
+ ODR15
+ Port output data (y =
+ 0..15)
+ 15
+ 1
+
+
+ ODR14
+ Port output data (y =
+ 0..15)
+ 14
+ 1
+
+
+ ODR13
+ Port output data (y =
+ 0..15)
+ 13
+ 1
+
+
+ ODR12
+ Port output data (y =
+ 0..15)
+ 12
+ 1
+
+
+ ODR11
+ Port output data (y =
+ 0..15)
+ 11
+ 1
+
+
+ ODR10
+ Port output data (y =
+ 0..15)
+ 10
+ 1
+
+
+ ODR9
+ Port output data (y =
+ 0..15)
+ 9
+ 1
+
+
+ ODR8
+ Port output data (y =
+ 0..15)
+ 8
+ 1
+
+
+ ODR7
+ Port output data (y =
+ 0..15)
+ 7
+ 1
+
+
+ ODR6
+ Port output data (y =
+ 0..15)
+ 6
+ 1
+
+
+ ODR5
+ Port output data (y =
+ 0..15)
+ 5
+ 1
+
+
+ ODR4
+ Port output data (y =
+ 0..15)
+ 4
+ 1
+
+
+ ODR3
+ Port output data (y =
+ 0..15)
+ 3
+ 1
+
+
+ ODR2
+ Port output data (y =
+ 0..15)
+ 2
+ 1
+
+
+ ODR1
+ Port output data (y =
+ 0..15)
+ 1
+ 1
+
+
+ ODR0
+ Port output data (y =
+ 0..15)
+ 0
+ 1
+
+
+
+
+ BSRR
+ BSRR
+ GPIO port bit set/reset
+ register
+ 0x18
+ 0x20
+ write-only
+ 0x00000000
+
+
+ BR15
+ Port x reset bit y (y =
+ 0..15)
+ 31
+ 1
+
+
+ BR14
+ Port x reset bit y (y =
+ 0..15)
+ 30
+ 1
+
+
+ BR13
+ Port x reset bit y (y =
+ 0..15)
+ 29
+ 1
+
+
+ BR12
+ Port x reset bit y (y =
+ 0..15)
+ 28
+ 1
+
+
+ BR11
+ Port x reset bit y (y =
+ 0..15)
+ 27
+ 1
+
+
+ BR10
+ Port x reset bit y (y =
+ 0..15)
+ 26
+ 1
+
+
+ BR9
+ Port x reset bit y (y =
+ 0..15)
+ 25
+ 1
+
+
+ BR8
+ Port x reset bit y (y =
+ 0..15)
+ 24
+ 1
+
+
+ BR7
+ Port x reset bit y (y =
+ 0..15)
+ 23
+ 1
+
+
+ BR6
+ Port x reset bit y (y =
+ 0..15)
+ 22
+ 1
+
+
+ BR5
+ Port x reset bit y (y =
+ 0..15)
+ 21
+ 1
+
+
+ BR4
+ Port x reset bit y (y =
+ 0..15)
+ 20
+ 1
+
+
+ BR3
+ Port x reset bit y (y =
+ 0..15)
+ 19
+ 1
+
+
+ BR2
+ Port x reset bit y (y =
+ 0..15)
+ 18
+ 1
+
+
+ BR1
+ Port x reset bit y (y =
+ 0..15)
+ 17
+ 1
+
+
+ BR0
+ Port x set bit y (y=
+ 0..15)
+ 16
+ 1
+
+
+ BS15
+ Port x set bit y (y=
+ 0..15)
+ 15
+ 1
+
+
+ BS14
+ Port x set bit y (y=
+ 0..15)
+ 14
+ 1
+
+
+ BS13
+ Port x set bit y (y=
+ 0..15)
+ 13
+ 1
+
+
+ BS12
+ Port x set bit y (y=
+ 0..15)
+ 12
+ 1
+
+
+ BS11
+ Port x set bit y (y=
+ 0..15)
+ 11
+ 1
+
+
+ BS10
+ Port x set bit y (y=
+ 0..15)
+ 10
+ 1
+
+
+ BS9
+ Port x set bit y (y=
+ 0..15)
+ 9
+ 1
+
+
+ BS8
+ Port x set bit y (y=
+ 0..15)
+ 8
+ 1
+
+
+ BS7
+ Port x set bit y (y=
+ 0..15)
+ 7
+ 1
+
+
+ BS6
+ Port x set bit y (y=
+ 0..15)
+ 6
+ 1
+
+
+ BS5
+ Port x set bit y (y=
+ 0..15)
+ 5
+ 1
+
+
+ BS4
+ Port x set bit y (y=
+ 0..15)
+ 4
+ 1
+
+
+ BS3
+ Port x set bit y (y=
+ 0..15)
+ 3
+ 1
+
+
+ BS2
+ Port x set bit y (y=
+ 0..15)
+ 2
+ 1
+
+
+ BS1
+ Port x set bit y (y=
+ 0..15)
+ 1
+ 1
+
+
+ BS0
+ Port x set bit y (y=
+ 0..15)
+ 0
+ 1
+
+
+
+
+ LCKR
+ LCKR
+ GPIO port configuration lock
+ register
+ 0x1C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ LCKK
+ Lok Key
+ 16
+ 1
+
+
+ LCK15
+ Port x lock bit y (y=
+ 0..15)
+ 15
+ 1
+
+
+ LCK14
+ Port x lock bit y (y=
+ 0..15)
+ 14
+ 1
+
+
+ LCK13
+ Port x lock bit y (y=
+ 0..15)
+ 13
+ 1
+
+
+ LCK12
+ Port x lock bit y (y=
+ 0..15)
+ 12
+ 1
+
+
+ LCK11
+ Port x lock bit y (y=
+ 0..15)
+ 11
+ 1
+
+
+ LCK10
+ Port x lock bit y (y=
+ 0..15)
+ 10
+ 1
+
+
+ LCK9
+ Port x lock bit y (y=
+ 0..15)
+ 9
+ 1
+
+
+ LCK8
+ Port x lock bit y (y=
+ 0..15)
+ 8
+ 1
+
+
+ LCK7
+ Port x lock bit y (y=
+ 0..15)
+ 7
+ 1
+
+
+ LCK6
+ Port x lock bit y (y=
+ 0..15)
+ 6
+ 1
+
+
+ LCK5
+ Port x lock bit y (y=
+ 0..15)
+ 5
+ 1
+
+
+ LCK4
+ Port x lock bit y (y=
+ 0..15)
+ 4
+ 1
+
+
+ LCK3
+ Port x lock bit y (y=
+ 0..15)
+ 3
+ 1
+
+
+ LCK2
+ Port x lock bit y (y=
+ 0..15)
+ 2
+ 1
+
+
+ LCK1
+ Port x lock bit y (y=
+ 0..15)
+ 1
+ 1
+
+
+ LCK0
+ Port x lock bit y (y=
+ 0..15)
+ 0
+ 1
+
+
+
+
+ AFRL
+ AFRL
+ GPIO alternate function low
+ register
+ 0x20
+ 0x20
+ read-write
+ 0x00000000
+
+
+ AFRL7
+ Alternate function selection for port x
+ bit y (y = 0..7)
+ 28
+ 4
+
+
+ AFRL6
+ Alternate function selection for port x
+ bit y (y = 0..7)
+ 24
+ 4
+
+
+ AFRL5
+ Alternate function selection for port x
+ bit y (y = 0..7)
+ 20
+ 4
+
+
+ AFRL4
+ Alternate function selection for port x
+ bit y (y = 0..7)
+ 16
+ 4
+
+
+ AFRL3
+ Alternate function selection for port x
+ bit y (y = 0..7)
+ 12
+ 4
+
+
+ AFRL2
+ Alternate function selection for port x
+ bit y (y = 0..7)
+ 8
+ 4
+
+
+ AFRL1
+ Alternate function selection for port x
+ bit y (y = 0..7)
+ 4
+ 4
+
+
+ AFRL0
+ Alternate function selection for port x
+ bit y (y = 0..7)
+ 0
+ 4
+
+
+
+
+ AFRH
+ AFRH
+ GPIO alternate function high
+ register
+ 0x24
+ 0x20
+ read-write
+ 0x00000000
+
+
+ AFRH15
+ Alternate function selection for port x
+ bit y (y = 8..15)
+ 28
+ 4
+
+
+ AFRH14
+ Alternate function selection for port x
+ bit y (y = 8..15)
+ 24
+ 4
+
+
+ AFRH13
+ Alternate function selection for port x
+ bit y (y = 8..15)
+ 20
+ 4
+
+
+ AFRH12
+ Alternate function selection for port x
+ bit y (y = 8..15)
+ 16
+ 4
+
+
+ AFRH11
+ Alternate function selection for port x
+ bit y (y = 8..15)
+ 12
+ 4
+
+
+ AFRH10
+ Alternate function selection for port x
+ bit y (y = 8..15)
+ 8
+ 4
+
+
+ AFRH9
+ Alternate function selection for port x
+ bit y (y = 8..15)
+ 4
+ 4
+
+
+ AFRH8
+ Alternate function selection for port x
+ bit y (y = 8..15)
+ 0
+ 4
+
+
+
+
+ BRR
+ BRR
+ Port bit reset register
+ 0x28
+ 0x20
+ write-only
+ 0x00000000
+
+
+ BR0
+ Port x Reset bit y
+ 0
+ 1
+
+
+ BR1
+ Port x Reset bit y
+ 1
+ 1
+
+
+ BR2
+ Port x Reset bit y
+ 2
+ 1
+
+
+ BR3
+ Port x Reset bit y
+ 3
+ 1
+
+
+ BR4
+ Port x Reset bit y
+ 4
+ 1
+
+
+ BR5
+ Port x Reset bit y
+ 5
+ 1
+
+
+ BR6
+ Port x Reset bit y
+ 6
+ 1
+
+
+ BR7
+ Port x Reset bit y
+ 7
+ 1
+
+
+ BR8
+ Port x Reset bit y
+ 8
+ 1
+
+
+ BR9
+ Port x Reset bit y
+ 9
+ 1
+
+
+ BR10
+ Port x Reset bit y
+ 10
+ 1
+
+
+ BR11
+ Port x Reset bit y
+ 11
+ 1
+
+
+ BR12
+ Port x Reset bit y
+ 12
+ 1
+
+
+ BR13
+ Port x Reset bit y
+ 13
+ 1
+
+
+ BR14
+ Port x Reset bit y
+ 14
+ 1
+
+
+ BR15
+ Port x Reset bit y
+ 15
+ 1
+
+
+
+
+
+
+ GPIOB
+ General-purpose I/Os
+ GPIO
+ 0x48000400
+
+ 0x0
+ 0x400
+ registers
+
+
+
+ MODER
+ MODER
+ GPIO port mode register
+ 0x0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MODER15
+ Port x configuration bits (y =
+ 0..15)
+ 30
+ 2
+
+
+ MODER14
+ Port x configuration bits (y =
+ 0..15)
+ 28
+ 2
+
+
+ MODER13
+ Port x configuration bits (y =
+ 0..15)
+ 26
+ 2
+
+
+ MODER12
+ Port x configuration bits (y =
+ 0..15)
+ 24
+ 2
+
+
+ MODER11
+ Port x configuration bits (y =
+ 0..15)
+ 22
+ 2
+
+
+ MODER10
+ Port x configuration bits (y =
+ 0..15)
+ 20
+ 2
+
+
+ MODER9
+ Port x configuration bits (y =
+ 0..15)
+ 18
+ 2
+
+
+ MODER8
+ Port x configuration bits (y =
+ 0..15)
+ 16
+ 2
+
+
+ MODER7
+ Port x configuration bits (y =
+ 0..15)
+ 14
+ 2
+
+
+ MODER6
+ Port x configuration bits (y =
+ 0..15)
+ 12
+ 2
+
+
+ MODER5
+ Port x configuration bits (y =
+ 0..15)
+ 10
+ 2
+
+
+ MODER4
+ Port x configuration bits (y =
+ 0..15)
+ 8
+ 2
+
+
+ MODER3
+ Port x configuration bits (y =
+ 0..15)
+ 6
+ 2
+
+
+ MODER2
+ Port x configuration bits (y =
+ 0..15)
+ 4
+ 2
+
+
+ MODER1
+ Port x configuration bits (y =
+ 0..15)
+ 2
+ 2
+
+
+ MODER0
+ Port x configuration bits (y =
+ 0..15)
+ 0
+ 2
+
+
+
+
+ OTYPER
+ OTYPER
+ GPIO port output type register
+ 0x4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ OT15
+ Port x configuration bit
+ 15
+ 15
+ 1
+
+
+ OT14
+ Port x configuration bit
+ 14
+ 14
+ 1
+
+
+ OT13
+ Port x configuration bit
+ 13
+ 13
+ 1
+
+
+ OT12
+ Port x configuration bit
+ 12
+ 12
+ 1
+
+
+ OT11
+ Port x configuration bit
+ 11
+ 11
+ 1
+
+
+ OT10
+ Port x configuration bit
+ 10
+ 10
+ 1
+
+
+ OT9
+ Port x configuration bit 9
+ 9
+ 1
+
+
+ OT8
+ Port x configuration bit 8
+ 8
+ 1
+
+
+ OT7
+ Port x configuration bit 7
+ 7
+ 1
+
+
+ OT6
+ Port x configuration bit 6
+ 6
+ 1
+
+
+ OT5
+ Port x configuration bit 5
+ 5
+ 1
+
+
+ OT4
+ Port x configuration bit 4
+ 4
+ 1
+
+
+ OT3
+ Port x configuration bit 3
+ 3
+ 1
+
+
+ OT2
+ Port x configuration bit 2
+ 2
+ 1
+
+
+ OT1
+ Port x configuration bit 1
+ 1
+ 1
+
+
+ OT0
+ Port x configuration bit 0
+ 0
+ 1
+
+
+
+
+ OSPEEDR
+ OSPEEDR
+ GPIO port output speed
+ register
+ 0x8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ OSPEEDR15
+ Port x configuration bits (y =
+ 0..15)
+ 30
+ 2
+
+
+ OSPEEDR14
+ Port x configuration bits (y =
+ 0..15)
+ 28
+ 2
+
+
+ OSPEEDR13
+ Port x configuration bits (y =
+ 0..15)
+ 26
+ 2
+
+
+ OSPEEDR12
+ Port x configuration bits (y =
+ 0..15)
+ 24
+ 2
+
+
+ OSPEEDR11
+ Port x configuration bits (y =
+ 0..15)
+ 22
+ 2
+
+
+ OSPEEDR10
+ Port x configuration bits (y =
+ 0..15)
+ 20
+ 2
+
+
+ OSPEEDR9
+ Port x configuration bits (y =
+ 0..15)
+ 18
+ 2
+
+
+ OSPEEDR8
+ Port x configuration bits (y =
+ 0..15)
+ 16
+ 2
+
+
+ OSPEEDR7
+ Port x configuration bits (y =
+ 0..15)
+ 14
+ 2
+
+
+ OSPEEDR6
+ Port x configuration bits (y =
+ 0..15)
+ 12
+ 2
+
+
+ OSPEEDR5
+ Port x configuration bits (y =
+ 0..15)
+ 10
+ 2
+
+
+ OSPEEDR4
+ Port x configuration bits (y =
+ 0..15)
+ 8
+ 2
+
+
+ OSPEEDR3
+ Port x configuration bits (y =
+ 0..15)
+ 6
+ 2
+
+
+ OSPEEDR2
+ Port x configuration bits (y =
+ 0..15)
+ 4
+ 2
+
+
+ OSPEEDR1
+ Port x configuration bits (y =
+ 0..15)
+ 2
+ 2
+
+
+ OSPEEDR0
+ Port x configuration bits (y =
+ 0..15)
+ 0
+ 2
+
+
+
+
+ PUPDR
+ PUPDR
+ GPIO port pull-up/pull-down
+ register
+ 0xC
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PUPDR15
+ Port x configuration bits (y =
+ 0..15)
+ 30
+ 2
+
+
+ PUPDR14
+ Port x configuration bits (y =
+ 0..15)
+ 28
+ 2
+
+
+ PUPDR13
+ Port x configuration bits (y =
+ 0..15)
+ 26
+ 2
+
+
+ PUPDR12
+ Port x configuration bits (y =
+ 0..15)
+ 24
+ 2
+
+
+ PUPDR11
+ Port x configuration bits (y =
+ 0..15)
+ 22
+ 2
+
+
+ PUPDR10
+ Port x configuration bits (y =
+ 0..15)
+ 20
+ 2
+
+
+ PUPDR9
+ Port x configuration bits (y =
+ 0..15)
+ 18
+ 2
+
+
+ PUPDR8
+ Port x configuration bits (y =
+ 0..15)
+ 16
+ 2
+
+
+ PUPDR7
+ Port x configuration bits (y =
+ 0..15)
+ 14
+ 2
+
+
+ PUPDR6
+ Port x configuration bits (y =
+ 0..15)
+ 12
+ 2
+
+
+ PUPDR5
+ Port x configuration bits (y =
+ 0..15)
+ 10
+ 2
+
+
+ PUPDR4
+ Port x configuration bits (y =
+ 0..15)
+ 8
+ 2
+
+
+ PUPDR3
+ Port x configuration bits (y =
+ 0..15)
+ 6
+ 2
+
+
+ PUPDR2
+ Port x configuration bits (y =
+ 0..15)
+ 4
+ 2
+
+
+ PUPDR1
+ Port x configuration bits (y =
+ 0..15)
+ 2
+ 2
+
+
+ PUPDR0
+ Port x configuration bits (y =
+ 0..15)
+ 0
+ 2
+
+
+
+
+ IDR
+ IDR
+ GPIO port input data register
+ 0x10
+ 0x20
+ read-only
+ 0x00000000
+
+
+ IDR15
+ Port input data (y =
+ 0..15)
+ 15
+ 1
+
+
+ IDR14
+ Port input data (y =
+ 0..15)
+ 14
+ 1
+
+
+ IDR13
+ Port input data (y =
+ 0..15)
+ 13
+ 1
+
+
+ IDR12
+ Port input data (y =
+ 0..15)
+ 12
+ 1
+
+
+ IDR11
+ Port input data (y =
+ 0..15)
+ 11
+ 1
+
+
+ IDR10
+ Port input data (y =
+ 0..15)
+ 10
+ 1
+
+
+ IDR9
+ Port input data (y =
+ 0..15)
+ 9
+ 1
+
+
+ IDR8
+ Port input data (y =
+ 0..15)
+ 8
+ 1
+
+
+ IDR7
+ Port input data (y =
+ 0..15)
+ 7
+ 1
+
+
+ IDR6
+ Port input data (y =
+ 0..15)
+ 6
+ 1
+
+
+ IDR5
+ Port input data (y =
+ 0..15)
+ 5
+ 1
+
+
+ IDR4
+ Port input data (y =
+ 0..15)
+ 4
+ 1
+
+
+ IDR3
+ Port input data (y =
+ 0..15)
+ 3
+ 1
+
+
+ IDR2
+ Port input data (y =
+ 0..15)
+ 2
+ 1
+
+
+ IDR1
+ Port input data (y =
+ 0..15)
+ 1
+ 1
+
+
+ IDR0
+ Port input data (y =
+ 0..15)
+ 0
+ 1
+
+
+
+
+ ODR
+ ODR
+ GPIO port output data register
+ 0x14
+ 0x20
+ read-write
+ 0x00000000
+
+
+ ODR15
+ Port output data (y =
+ 0..15)
+ 15
+ 1
+
+
+ ODR14
+ Port output data (y =
+ 0..15)
+ 14
+ 1
+
+
+ ODR13
+ Port output data (y =
+ 0..15)
+ 13
+ 1
+
+
+ ODR12
+ Port output data (y =
+ 0..15)
+ 12
+ 1
+
+
+ ODR11
+ Port output data (y =
+ 0..15)
+ 11
+ 1
+
+
+ ODR10
+ Port output data (y =
+ 0..15)
+ 10
+ 1
+
+
+ ODR9
+ Port output data (y =
+ 0..15)
+ 9
+ 1
+
+
+ ODR8
+ Port output data (y =
+ 0..15)
+ 8
+ 1
+
+
+ ODR7
+ Port output data (y =
+ 0..15)
+ 7
+ 1
+
+
+ ODR6
+ Port output data (y =
+ 0..15)
+ 6
+ 1
+
+
+ ODR5
+ Port output data (y =
+ 0..15)
+ 5
+ 1
+
+
+ ODR4
+ Port output data (y =
+ 0..15)
+ 4
+ 1
+
+
+ ODR3
+ Port output data (y =
+ 0..15)
+ 3
+ 1
+
+
+ ODR2
+ Port output data (y =
+ 0..15)
+ 2
+ 1
+
+
+ ODR1
+ Port output data (y =
+ 0..15)
+ 1
+ 1
+
+
+ ODR0
+ Port output data (y =
+ 0..15)
+ 0
+ 1
+
+
+
+
+ BSRR
+ BSRR
+ GPIO port bit set/reset
+ register
+ 0x18
+ 0x20
+ write-only
+ 0x00000000
+
+
+ BR15
+ Port x reset bit y (y =
+ 0..15)
+ 31
+ 1
+
+
+ BR14
+ Port x reset bit y (y =
+ 0..15)
+ 30
+ 1
+
+
+ BR13
+ Port x reset bit y (y =
+ 0..15)
+ 29
+ 1
+
+
+ BR12
+ Port x reset bit y (y =
+ 0..15)
+ 28
+ 1
+
+
+ BR11
+ Port x reset bit y (y =
+ 0..15)
+ 27
+ 1
+
+
+ BR10
+ Port x reset bit y (y =
+ 0..15)
+ 26
+ 1
+
+
+ BR9
+ Port x reset bit y (y =
+ 0..15)
+ 25
+ 1
+
+
+ BR8
+ Port x reset bit y (y =
+ 0..15)
+ 24
+ 1
+
+
+ BR7
+ Port x reset bit y (y =
+ 0..15)
+ 23
+ 1
+
+
+ BR6
+ Port x reset bit y (y =
+ 0..15)
+ 22
+ 1
+
+
+ BR5
+ Port x reset bit y (y =
+ 0..15)
+ 21
+ 1
+
+
+ BR4
+ Port x reset bit y (y =
+ 0..15)
+ 20
+ 1
+
+
+ BR3
+ Port x reset bit y (y =
+ 0..15)
+ 19
+ 1
+
+
+ BR2
+ Port x reset bit y (y =
+ 0..15)
+ 18
+ 1
+
+
+ BR1
+ Port x reset bit y (y =
+ 0..15)
+ 17
+ 1
+
+
+ BR0
+ Port x set bit y (y=
+ 0..15)
+ 16
+ 1
+
+
+ BS15
+ Port x set bit y (y=
+ 0..15)
+ 15
+ 1
+
+
+ BS14
+ Port x set bit y (y=
+ 0..15)
+ 14
+ 1
+
+
+ BS13
+ Port x set bit y (y=
+ 0..15)
+ 13
+ 1
+
+
+ BS12
+ Port x set bit y (y=
+ 0..15)
+ 12
+ 1
+
+
+ BS11
+ Port x set bit y (y=
+ 0..15)
+ 11
+ 1
+
+
+ BS10
+ Port x set bit y (y=
+ 0..15)
+ 10
+ 1
+
+
+ BS9
+ Port x set bit y (y=
+ 0..15)
+ 9
+ 1
+
+
+ BS8
+ Port x set bit y (y=
+ 0..15)
+ 8
+ 1
+
+
+ BS7
+ Port x set bit y (y=
+ 0..15)
+ 7
+ 1
+
+
+ BS6
+ Port x set bit y (y=
+ 0..15)
+ 6
+ 1
+
+
+ BS5
+ Port x set bit y (y=
+ 0..15)
+ 5
+ 1
+
+
+ BS4
+ Port x set bit y (y=
+ 0..15)
+ 4
+ 1
+
+
+ BS3
+ Port x set bit y (y=
+ 0..15)
+ 3
+ 1
+
+
+ BS2
+ Port x set bit y (y=
+ 0..15)
+ 2
+ 1
+
+
+ BS1
+ Port x set bit y (y=
+ 0..15)
+ 1
+ 1
+
+
+ BS0
+ Port x set bit y (y=
+ 0..15)
+ 0
+ 1
+
+
+
+
+ LCKR
+ LCKR
+ GPIO port configuration lock
+ register
+ 0x1C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ LCKK
+ Lok Key
+ 16
+ 1
+
+
+ LCK15
+ Port x lock bit y (y=
+ 0..15)
+ 15
+ 1
+
+
+ LCK14
+ Port x lock bit y (y=
+ 0..15)
+ 14
+ 1
+
+
+ LCK13
+ Port x lock bit y (y=
+ 0..15)
+ 13
+ 1
+
+
+ LCK12
+ Port x lock bit y (y=
+ 0..15)
+ 12
+ 1
+
+
+ LCK11
+ Port x lock bit y (y=
+ 0..15)
+ 11
+ 1
+
+
+ LCK10
+ Port x lock bit y (y=
+ 0..15)
+ 10
+ 1
+
+
+ LCK9
+ Port x lock bit y (y=
+ 0..15)
+ 9
+ 1
+
+
+ LCK8
+ Port x lock bit y (y=
+ 0..15)
+ 8
+ 1
+
+
+ LCK7
+ Port x lock bit y (y=
+ 0..15)
+ 7
+ 1
+
+
+ LCK6
+ Port x lock bit y (y=
+ 0..15)
+ 6
+ 1
+
+
+ LCK5
+ Port x lock bit y (y=
+ 0..15)
+ 5
+ 1
+
+
+ LCK4
+ Port x lock bit y (y=
+ 0..15)
+ 4
+ 1
+
+
+ LCK3
+ Port x lock bit y (y=
+ 0..15)
+ 3
+ 1
+
+
+ LCK2
+ Port x lock bit y (y=
+ 0..15)
+ 2
+ 1
+
+
+ LCK1
+ Port x lock bit y (y=
+ 0..15)
+ 1
+ 1
+
+
+ LCK0
+ Port x lock bit y (y=
+ 0..15)
+ 0
+ 1
+
+
+
+
+ AFRL
+ AFRL
+ GPIO alternate function low
+ register
+ 0x20
+ 0x20
+ read-write
+ 0x00000000
+
+
+ AFRL7
+ Alternate function selection for port x
+ bit y (y = 0..7)
+ 28
+ 4
+
+
+ AFRL6
+ Alternate function selection for port x
+ bit y (y = 0..7)
+ 24
+ 4
+
+
+ AFRL5
+ Alternate function selection for port x
+ bit y (y = 0..7)
+ 20
+ 4
+
+
+ AFRL4
+ Alternate function selection for port x
+ bit y (y = 0..7)
+ 16
+ 4
+
+
+ AFRL3
+ Alternate function selection for port x
+ bit y (y = 0..7)
+ 12
+ 4
+
+
+ AFRL2
+ Alternate function selection for port x
+ bit y (y = 0..7)
+ 8
+ 4
+
+
+ AFRL1
+ Alternate function selection for port x
+ bit y (y = 0..7)
+ 4
+ 4
+
+
+ AFRL0
+ Alternate function selection for port x
+ bit y (y = 0..7)
+ 0
+ 4
+
+
+
+
+ AFRH
+ AFRH
+ GPIO alternate function high
+ register
+ 0x24
+ 0x20
+ read-write
+ 0x00000000
+
+
+ AFRH15
+ Alternate function selection for port x
+ bit y (y = 8..15)
+ 28
+ 4
+
+
+ AFRH14
+ Alternate function selection for port x
+ bit y (y = 8..15)
+ 24
+ 4
+
+
+ AFRH13
+ Alternate function selection for port x
+ bit y (y = 8..15)
+ 20
+ 4
+
+
+ AFRH12
+ Alternate function selection for port x
+ bit y (y = 8..15)
+ 16
+ 4
+
+
+ AFRH11
+ Alternate function selection for port x
+ bit y (y = 8..15)
+ 12
+ 4
+
+
+ AFRH10
+ Alternate function selection for port x
+ bit y (y = 8..15)
+ 8
+ 4
+
+
+ AFRH9
+ Alternate function selection for port x
+ bit y (y = 8..15)
+ 4
+ 4
+
+
+ AFRH8
+ Alternate function selection for port x
+ bit y (y = 8..15)
+ 0
+ 4
+
+
+
+
+ BRR
+ BRR
+ Port bit reset register
+ 0x28
+ 0x20
+ write-only
+ 0x00000000
+
+
+ BR0
+ Port x Reset bit y
+ 0
+ 1
+
+
+ BR1
+ Port x Reset bit y
+ 1
+ 1
+
+
+ BR2
+ Port x Reset bit y
+ 2
+ 1
+
+
+ BR3
+ Port x Reset bit y
+ 3
+ 1
+
+
+ BR4
+ Port x Reset bit y
+ 4
+ 1
+
+
+ BR5
+ Port x Reset bit y
+ 5
+ 1
+
+
+ BR6
+ Port x Reset bit y
+ 6
+ 1
+
+
+ BR7
+ Port x Reset bit y
+ 7
+ 1
+
+
+ BR8
+ Port x Reset bit y
+ 8
+ 1
+
+
+ BR9
+ Port x Reset bit y
+ 9
+ 1
+
+
+ BR10
+ Port x Reset bit y
+ 10
+ 1
+
+
+ BR11
+ Port x Reset bit y
+ 11
+ 1
+
+
+ BR12
+ Port x Reset bit y
+ 12
+ 1
+
+
+ BR13
+ Port x Reset bit y
+ 13
+ 1
+
+
+ BR14
+ Port x Reset bit y
+ 14
+ 1
+
+
+ BR15
+ Port x Reset bit y
+ 15
+ 1
+
+
+
+
+
+
+ GPIOC
+ 0x48000800
+
+
+ GPIOD
+ 0x48000C00
+
+
+ GPIOE
+ 0x48001000
+
+
+ GPIOF
+ 0x48001400
+
+
+ GPIOG
+ 0x48001800
+
+
+ GPIOH
+ 0x48001C00
+
+
+ TSC
+ Touch sensing controller
+ TSC
+ 0x40024000
+
+ 0x0
+ 0x400
+ registers
+
+
+
+ CR
+ CR
+ control register
+ 0x0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CTPH
+ Charge transfer pulse high
+ 28
+ 4
+
+
+ CTPL
+ Charge transfer pulse low
+ 24
+ 4
+
+
+ SSD
+ Spread spectrum deviation
+ 17
+ 7
+
+
+ SSE
+ Spread spectrum enable
+ 16
+ 1
+
+
+ SSPSC
+ Spread spectrum prescaler
+ 15
+ 1
+
+
+ PGPSC
+ pulse generator prescaler
+ 12
+ 3
+
+
+ MCV
+ Max count value
+ 5
+ 3
+
+
+ IODEF
+ I/O Default mode
+ 4
+ 1
+
+
+ SYNCPOL
+ Synchronization pin
+ polarity
+ 3
+ 1
+
+
+ AM
+ Acquisition mode
+ 2
+ 1
+
+
+ START
+ Start a new acquisition
+ 1
+ 1
+
+
+ TSCE
+ Touch sensing controller
+ enable
+ 0
+ 1
+
+
+
+
+ IER
+ IER
+ interrupt enable register
+ 0x4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MCEIE
+ Max count error interrupt
+ enable
+ 1
+ 1
+
+
+ EOAIE
+ End of acquisition interrupt
+ enable
+ 0
+ 1
+
+
+
+
+ ICR
+ ICR
+ interrupt clear register
+ 0x8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MCEIC
+ Max count error interrupt
+ clear
+ 1
+ 1
+
+
+ EOAIC
+ End of acquisition interrupt
+ clear
+ 0
+ 1
+
+
+
+
+ ISR
+ ISR
+ interrupt status register
+ 0xC
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MCEF
+ Max count error flag
+ 1
+ 1
+
+
+ EOAF
+ End of acquisition flag
+ 0
+ 1
+
+
+
+
+ IOHCR
+ IOHCR
+ I/O hysteresis control
+ register
+ 0x10
+ 0x20
+ read-write
+ 0xFFFFFFFF
+
+
+ G1_IO1
+ G1_IO1 Schmitt trigger hysteresis
+ mode
+ 0
+ 1
+
+
+ G1_IO2
+ G1_IO2 Schmitt trigger hysteresis
+ mode
+ 1
+ 1
+
+
+ G1_IO3
+ G1_IO3 Schmitt trigger hysteresis
+ mode
+ 2
+ 1
+
+
+ G1_IO4
+ G1_IO4 Schmitt trigger hysteresis
+ mode
+ 3
+ 1
+
+
+ G2_IO1
+ G2_IO1 Schmitt trigger hysteresis
+ mode
+ 4
+ 1
+
+
+ G2_IO2
+ G2_IO2 Schmitt trigger hysteresis
+ mode
+ 5
+ 1
+
+
+ G2_IO3
+ G2_IO3 Schmitt trigger hysteresis
+ mode
+ 6
+ 1
+
+
+ G2_IO4
+ G2_IO4 Schmitt trigger hysteresis
+ mode
+ 7
+ 1
+
+
+ G3_IO1
+ G3_IO1 Schmitt trigger hysteresis
+ mode
+ 8
+ 1
+
+
+ G3_IO2
+ G3_IO2 Schmitt trigger hysteresis
+ mode
+ 9
+ 1
+
+
+ G3_IO3
+ G3_IO3 Schmitt trigger hysteresis
+ mode
+ 10
+ 1
+
+
+ G3_IO4
+ G3_IO4 Schmitt trigger hysteresis
+ mode
+ 11
+ 1
+
+
+ G4_IO1
+ G4_IO1 Schmitt trigger hysteresis
+ mode
+ 12
+ 1
+
+
+ G4_IO2
+ G4_IO2 Schmitt trigger hysteresis
+ mode
+ 13
+ 1
+
+
+ G4_IO3
+ G4_IO3 Schmitt trigger hysteresis
+ mode
+ 14
+ 1
+
+
+ G4_IO4
+ G4_IO4 Schmitt trigger hysteresis
+ mode
+ 15
+ 1
+
+
+ G5_IO1
+ G5_IO1 Schmitt trigger hysteresis
+ mode
+ 16
+ 1
+
+
+ G5_IO2
+ G5_IO2 Schmitt trigger hysteresis
+ mode
+ 17
+ 1
+
+
+ G5_IO3
+ G5_IO3 Schmitt trigger hysteresis
+ mode
+ 18
+ 1
+
+
+ G5_IO4
+ G5_IO4 Schmitt trigger hysteresis
+ mode
+ 19
+ 1
+
+
+ G6_IO1
+ G6_IO1 Schmitt trigger hysteresis
+ mode
+ 20
+ 1
+
+
+ G6_IO2
+ G6_IO2 Schmitt trigger hysteresis
+ mode
+ 21
+ 1
+
+
+ G6_IO3
+ G6_IO3 Schmitt trigger hysteresis
+ mode
+ 22
+ 1
+
+
+ G6_IO4
+ G6_IO4 Schmitt trigger hysteresis
+ mode
+ 23
+ 1
+
+
+ G7_IO1
+ G7_IO1 Schmitt trigger hysteresis
+ mode
+ 24
+ 1
+
+
+ G7_IO2
+ G7_IO2 Schmitt trigger hysteresis
+ mode
+ 25
+ 1
+
+
+ G7_IO3
+ G7_IO3 Schmitt trigger hysteresis
+ mode
+ 26
+ 1
+
+
+ G7_IO4
+ G7_IO4 Schmitt trigger hysteresis
+ mode
+ 27
+ 1
+
+
+ G8_IO1
+ G8_IO1 Schmitt trigger hysteresis
+ mode
+ 28
+ 1
+
+
+ G8_IO2
+ G8_IO2 Schmitt trigger hysteresis
+ mode
+ 29
+ 1
+
+
+ G8_IO3
+ G8_IO3 Schmitt trigger hysteresis
+ mode
+ 30
+ 1
+
+
+ G8_IO4
+ G8_IO4 Schmitt trigger hysteresis
+ mode
+ 31
+ 1
+
+
+
+
+ IOASCR
+ IOASCR
+ I/O analog switch control
+ register
+ 0x18
+ 0x20
+ read-write
+ 0x00000000
+
+
+ G1_IO1
+ G1_IO1 analog switch
+ enable
+ 0
+ 1
+
+
+ G1_IO2
+ G1_IO2 analog switch
+ enable
+ 1
+ 1
+
+
+ G1_IO3
+ G1_IO3 analog switch
+ enable
+ 2
+ 1
+
+
+ G1_IO4
+ G1_IO4 analog switch
+ enable
+ 3
+ 1
+
+
+ G2_IO1
+ G2_IO1 analog switch
+ enable
+ 4
+ 1
+
+
+ G2_IO2
+ G2_IO2 analog switch
+ enable
+ 5
+ 1
+
+
+ G2_IO3
+ G2_IO3 analog switch
+ enable
+ 6
+ 1
+
+
+ G2_IO4
+ G2_IO4 analog switch
+ enable
+ 7
+ 1
+
+
+ G3_IO1
+ G3_IO1 analog switch
+ enable
+ 8
+ 1
+
+
+ G3_IO2
+ G3_IO2 analog switch
+ enable
+ 9
+ 1
+
+
+ G3_IO3
+ G3_IO3 analog switch
+ enable
+ 10
+ 1
+
+
+ G3_IO4
+ G3_IO4 analog switch
+ enable
+ 11
+ 1
+
+
+ G4_IO1
+ G4_IO1 analog switch
+ enable
+ 12
+ 1
+
+
+ G4_IO2
+ G4_IO2 analog switch
+ enable
+ 13
+ 1
+
+
+ G4_IO3
+ G4_IO3 analog switch
+ enable
+ 14
+ 1
+
+
+ G4_IO4
+ G4_IO4 analog switch
+ enable
+ 15
+ 1
+
+
+ G5_IO1
+ G5_IO1 analog switch
+ enable
+ 16
+ 1
+
+
+ G5_IO2
+ G5_IO2 analog switch
+ enable
+ 17
+ 1
+
+
+ G5_IO3
+ G5_IO3 analog switch
+ enable
+ 18
+ 1
+
+
+ G5_IO4
+ G5_IO4 analog switch
+ enable
+ 19
+ 1
+
+
+ G6_IO1
+ G6_IO1 analog switch
+ enable
+ 20
+ 1
+
+
+ G6_IO2
+ G6_IO2 analog switch
+ enable
+ 21
+ 1
+
+
+ G6_IO3
+ G6_IO3 analog switch
+ enable
+ 22
+ 1
+
+
+ G6_IO4
+ G6_IO4 analog switch
+ enable
+ 23
+ 1
+
+
+ G7_IO1
+ G7_IO1 analog switch
+ enable
+ 24
+ 1
+
+
+ G7_IO2
+ G7_IO2 analog switch
+ enable
+ 25
+ 1
+
+
+ G7_IO3
+ G7_IO3 analog switch
+ enable
+ 26
+ 1
+
+
+ G7_IO4
+ G7_IO4 analog switch
+ enable
+ 27
+ 1
+
+
+ G8_IO1
+ G8_IO1 analog switch
+ enable
+ 28
+ 1
+
+
+ G8_IO2
+ G8_IO2 analog switch
+ enable
+ 29
+ 1
+
+
+ G8_IO3
+ G8_IO3 analog switch
+ enable
+ 30
+ 1
+
+
+ G8_IO4
+ G8_IO4 analog switch
+ enable
+ 31
+ 1
+
+
+
+
+ IOSCR
+ IOSCR
+ I/O sampling control register
+ 0x20
+ 0x20
+ read-write
+ 0x00000000
+
+
+ G1_IO1
+ G1_IO1 sampling mode
+ 0
+ 1
+
+
+ G1_IO2
+ G1_IO2 sampling mode
+ 1
+ 1
+
+
+ G1_IO3
+ G1_IO3 sampling mode
+ 2
+ 1
+
+
+ G1_IO4
+ G1_IO4 sampling mode
+ 3
+ 1
+
+
+ G2_IO1
+ G2_IO1 sampling mode
+ 4
+ 1
+
+
+ G2_IO2
+ G2_IO2 sampling mode
+ 5
+ 1
+
+
+ G2_IO3
+ G2_IO3 sampling mode
+ 6
+ 1
+
+
+ G2_IO4
+ G2_IO4 sampling mode
+ 7
+ 1
+
+
+ G3_IO1
+ G3_IO1 sampling mode
+ 8
+ 1
+
+
+ G3_IO2
+ G3_IO2 sampling mode
+ 9
+ 1
+
+
+ G3_IO3
+ G3_IO3 sampling mode
+ 10
+ 1
+
+
+ G3_IO4
+ G3_IO4 sampling mode
+ 11
+ 1
+
+
+ G4_IO1
+ G4_IO1 sampling mode
+ 12
+ 1
+
+
+ G4_IO2
+ G4_IO2 sampling mode
+ 13
+ 1
+
+
+ G4_IO3
+ G4_IO3 sampling mode
+ 14
+ 1
+
+
+ G4_IO4
+ G4_IO4 sampling mode
+ 15
+ 1
+
+
+ G5_IO1
+ G5_IO1 sampling mode
+ 16
+ 1
+
+
+ G5_IO2
+ G5_IO2 sampling mode
+ 17
+ 1
+
+
+ G5_IO3
+ G5_IO3 sampling mode
+ 18
+ 1
+
+
+ G5_IO4
+ G5_IO4 sampling mode
+ 19
+ 1
+
+
+ G6_IO1
+ G6_IO1 sampling mode
+ 20
+ 1
+
+
+ G6_IO2
+ G6_IO2 sampling mode
+ 21
+ 1
+
+
+ G6_IO3
+ G6_IO3 sampling mode
+ 22
+ 1
+
+
+ G6_IO4
+ G6_IO4 sampling mode
+ 23
+ 1
+
+
+ G7_IO1
+ G7_IO1 sampling mode
+ 24
+ 1
+
+
+ G7_IO2
+ G7_IO2 sampling mode
+ 25
+ 1
+
+
+ G7_IO3
+ G7_IO3 sampling mode
+ 26
+ 1
+
+
+ G7_IO4
+ G7_IO4 sampling mode
+ 27
+ 1
+
+
+ G8_IO1
+ G8_IO1 sampling mode
+ 28
+ 1
+
+
+ G8_IO2
+ G8_IO2 sampling mode
+ 29
+ 1
+
+
+ G8_IO3
+ G8_IO3 sampling mode
+ 30
+ 1
+
+
+ G8_IO4
+ G8_IO4 sampling mode
+ 31
+ 1
+
+
+
+
+ IOCCR
+ IOCCR
+ I/O channel control register
+ 0x28
+ 0x20
+ read-write
+ 0x00000000
+
+
+ G1_IO1
+ G1_IO1 channel mode
+ 0
+ 1
+
+
+ G1_IO2
+ G1_IO2 channel mode
+ 1
+ 1
+
+
+ G1_IO3
+ G1_IO3 channel mode
+ 2
+ 1
+
+
+ G1_IO4
+ G1_IO4 channel mode
+ 3
+ 1
+
+
+ G2_IO1
+ G2_IO1 channel mode
+ 4
+ 1
+
+
+ G2_IO2
+ G2_IO2 channel mode
+ 5
+ 1
+
+
+ G2_IO3
+ G2_IO3 channel mode
+ 6
+ 1
+
+
+ G2_IO4
+ G2_IO4 channel mode
+ 7
+ 1
+
+
+ G3_IO1
+ G3_IO1 channel mode
+ 8
+ 1
+
+
+ G3_IO2
+ G3_IO2 channel mode
+ 9
+ 1
+
+
+ G3_IO3
+ G3_IO3 channel mode
+ 10
+ 1
+
+
+ G3_IO4
+ G3_IO4 channel mode
+ 11
+ 1
+
+
+ G4_IO1
+ G4_IO1 channel mode
+ 12
+ 1
+
+
+ G4_IO2
+ G4_IO2 channel mode
+ 13
+ 1
+
+
+ G4_IO3
+ G4_IO3 channel mode
+ 14
+ 1
+
+
+ G4_IO4
+ G4_IO4 channel mode
+ 15
+ 1
+
+
+ G5_IO1
+ G5_IO1 channel mode
+ 16
+ 1
+
+
+ G5_IO2
+ G5_IO2 channel mode
+ 17
+ 1
+
+
+ G5_IO3
+ G5_IO3 channel mode
+ 18
+ 1
+
+
+ G5_IO4
+ G5_IO4 channel mode
+ 19
+ 1
+
+
+ G6_IO1
+ G6_IO1 channel mode
+ 20
+ 1
+
+
+ G6_IO2
+ G6_IO2 channel mode
+ 21
+ 1
+
+
+ G6_IO3
+ G6_IO3 channel mode
+ 22
+ 1
+
+
+ G6_IO4
+ G6_IO4 channel mode
+ 23
+ 1
+
+
+ G7_IO1
+ G7_IO1 channel mode
+ 24
+ 1
+
+
+ G7_IO2
+ G7_IO2 channel mode
+ 25
+ 1
+
+
+ G7_IO3
+ G7_IO3 channel mode
+ 26
+ 1
+
+
+ G7_IO4
+ G7_IO4 channel mode
+ 27
+ 1
+
+
+ G8_IO1
+ G8_IO1 channel mode
+ 28
+ 1
+
+
+ G8_IO2
+ G8_IO2 channel mode
+ 29
+ 1
+
+
+ G8_IO3
+ G8_IO3 channel mode
+ 30
+ 1
+
+
+ G8_IO4
+ G8_IO4 channel mode
+ 31
+ 1
+
+
+
+
+ IOGCSR
+ IOGCSR
+ I/O group control status
+ register
+ 0x30
+ 0x20
+ 0x00000000
+
+
+ G8S
+ Analog I/O group x status
+ 23
+ 1
+ read-write
+
+
+ G7S
+ Analog I/O group x status
+ 22
+ 1
+ read-write
+
+
+ G6S
+ Analog I/O group x status
+ 21
+ 1
+ read-only
+
+
+ G5S
+ Analog I/O group x status
+ 20
+ 1
+ read-only
+
+
+ G4S
+ Analog I/O group x status
+ 19
+ 1
+ read-only
+
+
+ G3S
+ Analog I/O group x status
+ 18
+ 1
+ read-only
+
+
+ G2S
+ Analog I/O group x status
+ 17
+ 1
+ read-only
+
+
+ G1S
+ Analog I/O group x status
+ 16
+ 1
+ read-only
+
+
+ G8E
+ Analog I/O group x enable
+ 7
+ 1
+ read-write
+
+
+ G7E
+ Analog I/O group x enable
+ 6
+ 1
+ read-write
+
+
+ G6E
+ Analog I/O group x enable
+ 5
+ 1
+ read-write
+
+
+ G5E
+ Analog I/O group x enable
+ 4
+ 1
+ read-write
+
+
+ G4E
+ Analog I/O group x enable
+ 3
+ 1
+ read-write
+
+
+ G3E
+ Analog I/O group x enable
+ 2
+ 1
+ read-write
+
+
+ G2E
+ Analog I/O group x enable
+ 1
+ 1
+ read-write
+
+
+ G1E
+ Analog I/O group x enable
+ 0
+ 1
+ read-write
+
+
+
+
+ IOG1CR
+ IOG1CR
+ I/O group x counter register
+ 0x34
+ 0x20
+ read-only
+ 0x00000000
+
+
+ CNT
+ Counter value
+ 0
+ 14
+
+
+
+
+ IOG2CR
+ IOG2CR
+ I/O group x counter register
+ 0x38
+ 0x20
+ read-only
+ 0x00000000
+
+
+ CNT
+ Counter value
+ 0
+ 14
+
+
+
+
+ IOG3CR
+ IOG3CR
+ I/O group x counter register
+ 0x3C
+ 0x20
+ read-only
+ 0x00000000
+
+
+ CNT
+ Counter value
+ 0
+ 14
+
+
+
+
+ IOG4CR
+ IOG4CR
+ I/O group x counter register
+ 0x40
+ 0x20
+ read-only
+ 0x00000000
+
+
+ CNT
+ Counter value
+ 0
+ 14
+
+
+
+
+ IOG5CR
+ IOG5CR
+ I/O group x counter register
+ 0x44
+ 0x20
+ read-only
+ 0x00000000
+
+
+ CNT
+ Counter value
+ 0
+ 14
+
+
+
+
+ IOG6CR
+ IOG6CR
+ I/O group x counter register
+ 0x48
+ 0x20
+ read-only
+ 0x00000000
+
+
+ CNT
+ Counter value
+ 0
+ 14
+
+
+
+
+ IOG7CR
+ IOG7CR
+ I/O group x counter register
+ 0x4C
+ 0x20
+ read-only
+ 0x00000000
+
+
+ CNT
+ Counter value
+ 0
+ 14
+
+
+
+
+ IOG8CR
+ IOG8CR
+ I/O group x counter register
+ 0x50
+ 0x20
+ read-only
+ 0x00000000
+
+
+ CNT
+ Counter value
+ 0
+ 14
+
+
+
+
+
+
+ CRC
+ cyclic redundancy check calculation
+ unit
+ CRC
+ 0x40023000
+
+ 0x0
+ 0x400
+ registers
+
+
+
+ DR
+ DR
+ Data register
+ 0x0
+ 0x20
+ read-write
+ 0xFFFFFFFF
+
+
+ DR
+ Data register bits
+ 0
+ 32
+
+
+
+
+ IDR
+ IDR
+ Independent data register
+ 0x4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ IDR
+ General-purpose 8-bit data register
+ bits
+ 0
+ 8
+
+
+
+
+ CR
+ CR
+ Control register
+ 0x8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ RESET
+ reset bit
+ 0
+ 1
+
+
+ POLYSIZE
+ Polynomial size
+ 3
+ 2
+
+
+ REV_IN
+ Reverse input data
+ 5
+ 2
+
+
+ REV_OUT
+ Reverse output data
+ 7
+ 1
+
+
+
+
+ INIT
+ INIT
+ Initial CRC value
+ 0x10
+ 0x20
+ read-write
+ 0xFFFFFFFF
+
+
+ INIT
+ Programmable initial CRC
+ value
+ 0
+ 32
+
+
+
+
+ POL
+ POL
+ CRC polynomial
+ 0x14
+ 0x20
+ read-write
+ 0x04C11DB7
+
+
+ POL
+ Programmable polynomial
+ 0
+ 32
+
+
+
+
+
+
+ Flash
+ Flash
+ Flash
+ 0x40022000
+
+ 0x0
+ 0x400
+ registers
+
+
+ FLASH
+ Flash global interrupt
+ 4
+
+
+
+ ACR
+ ACR
+ Flash access control register
+ 0x0
+ 0x20
+ 0x00000030
+
+
+ LATENCY
+ LATENCY
+ 0
+ 3
+ read-write
+
+
+ PRFTBE
+ PRFTBE
+ 4
+ 1
+ read-write
+
+
+ PRFTBS
+ PRFTBS
+ 5
+ 1
+ read-only
+
+
+
+
+ KEYR
+ KEYR
+ Flash key register
+ 0x4
+ 0x20
+ write-only
+ 0x00000000
+
+
+ FKEYR
+ Flash Key
+ 0
+ 32
+
+
+
+
+ OPTKEYR
+ OPTKEYR
+ Flash option key register
+ 0x8
+ 0x20
+ write-only
+ 0x00000000
+
+
+ OPTKEYR
+ Option byte key
+ 0
+ 32
+
+
+
+
+ SR
+ SR
+ Flash status register
+ 0xC
+ 0x20
+ 0x00000000
+
+
+ EOP
+ End of operation
+ 5
+ 1
+ read-write
+
+
+ WRPRT
+ Write protection error
+ 4
+ 1
+ read-write
+
+
+ PGERR
+ Programming error
+ 2
+ 1
+ read-write
+
+
+ BSY
+ Busy
+ 0
+ 1
+ read-only
+
+
+
+
+ CR
+ CR
+ Flash control register
+ 0x10
+ 0x20
+ read-write
+ 0x00000080
+
+
+ FORCE_OPTLOAD
+ Force option byte loading
+ 13
+ 1
+
+
+ EOPIE
+ End of operation interrupt
+ enable
+ 12
+ 1
+
+
+ ERRIE
+ Error interrupt enable
+ 10
+ 1
+
+
+ OPTWRE
+ Option bytes write enable
+ 9
+ 1
+
+
+ LOCK
+ Lock
+ 7
+ 1
+
+
+ STRT
+ Start
+ 6
+ 1
+
+
+ OPTER
+ Option byte erase
+ 5
+ 1
+
+
+ OPTPG
+ Option byte programming
+ 4
+ 1
+
+
+ MER
+ Mass erase
+ 2
+ 1
+
+
+ PER
+ Page erase
+ 1
+ 1
+
+
+ PG
+ Programming
+ 0
+ 1
+
+
+
+
+ AR
+ AR
+ Flash address register
+ 0x14
+ 0x20
+ write-only
+ 0x00000000
+
+
+ FAR
+ Flash address
+ 0
+ 32
+
+
+
+
+ OBR
+ OBR
+ Option byte register
+ 0x1C
+ 0x20
+ read-only
+ 0xFFFFFF02
+
+
+ OPTERR
+ Option byte error
+ 0
+ 1
+
+
+ LEVEL1_PROT
+ Level 1 protection status
+ 1
+ 1
+
+
+ LEVEL2_PROT
+ Level 2 protection status
+ 2
+ 1
+
+
+ WDG_SW
+ WDG_SW
+ 8
+ 1
+
+
+ nRST_STOP
+ nRST_STOP
+ 9
+ 1
+
+
+ nRST_STDBY
+ nRST_STDBY
+ 10
+ 1
+
+
+ BOOT1
+ BOOT1
+ 12
+ 1
+
+
+ VDDA_MONITOR
+ VDDA_MONITOR
+ 13
+ 1
+
+
+ SRAM_PARITY_CHECK
+ SRAM_PARITY_CHECK
+ 14
+ 1
+
+
+ Data0
+ Data0
+ 16
+ 8
+
+
+ Data1
+ Data1
+ 24
+ 8
+
+
+
+
+ WRPR
+ WRPR
+ Write protection register
+ 0x20
+ 0x20
+ read-only
+ 0xFFFFFFFF
+
+
+ WRP
+ Write protect
+ 0
+ 32
+
+
+
+
+
+
+ RCC
+ Reset and clock control
+ RCC
+ 0x40021000
+
+ 0x0
+ 0x400
+ registers
+
+
+ RCC
+ RCC global interrupt
+ 5
+
+
+
+ CR
+ CR
+ Clock control register
+ 0x0
+ 0x20
+ 0x00000083
+
+
+ HSION
+ Internal High Speed clock
+ enable
+ 0
+ 1
+ read-write
+
+
+ HSIRDY
+ Internal High Speed clock ready
+ flag
+ 1
+ 1
+ read-only
+
+
+ HSITRIM
+ Internal High Speed clock
+ trimming
+ 3
+ 5
+ read-write
+
+
+ HSICAL
+ Internal High Speed clock
+ Calibration
+ 8
+ 8
+ read-only
+
+
+ HSEON
+ External High Speed clock
+ enable
+ 16
+ 1
+ read-write
+
+
+ HSERDY
+ External High Speed clock ready
+ flag
+ 17
+ 1
+ read-only
+
+
+ HSEBYP
+ External High Speed clock
+ Bypass
+ 18
+ 1
+ read-write
+
+
+ CSSON
+ Clock Security System
+ enable
+ 19
+ 1
+ read-write
+
+
+ PLLON
+ PLL enable
+ 24
+ 1
+ read-write
+
+
+ PLLRDY
+ PLL clock ready flag
+ 25
+ 1
+ read-only
+
+
+
+
+ CFGR
+ CFGR
+ Clock configuration register
+ (RCC_CFGR)
+ 0x4
+ 0x20
+ 0x00000000
+
+
+ SW
+ System clock Switch
+ 0
+ 2
+ read-write
+
+
+ SWS
+ System Clock Switch Status
+ 2
+ 2
+ read-only
+
+
+ HPRE
+ AHB prescaler
+ 4
+ 4
+ read-write
+
+
+ PPRE1
+ APB Low speed prescaler
+ (APB1)
+ 8
+ 3
+ read-write
+
+
+ PPRE2
+ APB high speed prescaler
+ (APB2)
+ 11
+ 3
+ read-write
+
+
+ PLLSRC
+ PLL entry clock source
+ 15
+ 2
+ read-write
+
+
+ PLLXTPRE
+ HSE divider for PLL entry
+ 17
+ 1
+ read-write
+
+
+ PLLMUL
+ PLL Multiplication Factor
+ 18
+ 4
+ read-write
+
+
+ USBPRES
+ USB prescaler
+ 22
+ 1
+ read-write
+
+
+ MCO
+ Microcontroller clock
+ output
+ 24
+ 3
+ read-write
+
+
+ MCOF
+ Microcontroller Clock Output
+ Flag
+ 28
+ 1
+ read-only
+
+
+ I2SSRC
+ I2S external clock source
+ selection
+ 23
+ 1
+ read-write
+
+
+
+
+ CIR
+ CIR
+ Clock interrupt register
+ (RCC_CIR)
+ 0x8
+ 0x20
+ 0x00000000
+
+
+ LSIRDYF
+ LSI Ready Interrupt flag
+ 0
+ 1
+ read-only
+
+
+ LSERDYF
+ LSE Ready Interrupt flag
+ 1
+ 1
+ read-only
+
+
+ HSIRDYF
+ HSI Ready Interrupt flag
+ 2
+ 1
+ read-only
+
+
+ HSERDYF
+ HSE Ready Interrupt flag
+ 3
+ 1
+ read-only
+
+
+ PLLRDYF
+ PLL Ready Interrupt flag
+ 4
+ 1
+ read-only
+
+
+ CSSF
+ Clock Security System Interrupt
+ flag
+ 7
+ 1
+ read-only
+
+
+ LSIRDYIE
+ LSI Ready Interrupt Enable
+ 8
+ 1
+ read-write
+
+
+ LSERDYIE
+ LSE Ready Interrupt Enable
+ 9
+ 1
+ read-write
+
+
+ HSIRDYIE
+ HSI Ready Interrupt Enable
+ 10
+ 1
+ read-write
+
+
+ HSERDYIE
+ HSE Ready Interrupt Enable
+ 11
+ 1
+ read-write
+
+
+ PLLRDYIE
+ PLL Ready Interrupt Enable
+ 12
+ 1
+ read-write
+
+
+ LSIRDYC
+ LSI Ready Interrupt Clear
+ 16
+ 1
+ write-only
+
+
+ LSERDYC
+ LSE Ready Interrupt Clear
+ 17
+ 1
+ write-only
+
+
+ HSIRDYC
+ HSI Ready Interrupt Clear
+ 18
+ 1
+ write-only
+
+
+ HSERDYC
+ HSE Ready Interrupt Clear
+ 19
+ 1
+ write-only
+
+
+ PLLRDYC
+ PLL Ready Interrupt Clear
+ 20
+ 1
+ write-only
+
+
+ CSSC
+ Clock security system interrupt
+ clear
+ 23
+ 1
+ write-only
+
+
+
+
+ APB2RSTR
+ APB2RSTR
+ APB2 peripheral reset register
+ (RCC_APB2RSTR)
+ 0xC
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SYSCFGRST
+ SYSCFG and COMP reset
+ 0
+ 1
+
+
+ TIM1RST
+ TIM1 timer reset
+ 11
+ 1
+
+
+ SPI1RST
+ SPI 1 reset
+ 12
+ 1
+
+
+ TIM8RST
+ TIM8 timer reset
+ 13
+ 1
+
+
+ USART1RST
+ USART1 reset
+ 14
+ 1
+
+
+ TIM15RST
+ TIM15 timer reset
+ 16
+ 1
+
+
+ TIM16RST
+ TIM16 timer reset
+ 17
+ 1
+
+
+ TIM17RST
+ TIM17 timer reset
+ 18
+ 1
+
+
+
+
+ APB1RSTR
+ APB1RSTR
+ APB1 peripheral reset register
+ (RCC_APB1RSTR)
+ 0x10
+ 0x20
+ read-write
+ 0x00000000
+
+
+ TIM2RST
+ Timer 2 reset
+ 0
+ 1
+
+
+ TIM3RST
+ Timer 3 reset
+ 1
+ 1
+
+
+ TIM4RST
+ Timer 14 reset
+ 2
+ 1
+
+
+ TIM6RST
+ Timer 6 reset
+ 4
+ 1
+
+
+ TIM7RST
+ Timer 7 reset
+ 5
+ 1
+
+
+ WWDGRST
+ Window watchdog reset
+ 11
+ 1
+
+
+ SPI2RST
+ SPI2 reset
+ 14
+ 1
+
+
+ SPI3RST
+ SPI3 reset
+ 15
+ 1
+
+
+ USART2RST
+ USART 2 reset
+ 17
+ 1
+
+
+ USART3RST
+ USART3 reset
+ 18
+ 1
+
+
+ UART4RST
+ UART 4 reset
+ 19
+ 1
+
+
+ UART5RST
+ UART 5 reset
+ 20
+ 1
+
+
+ I2C1RST
+ I2C1 reset
+ 21
+ 1
+
+
+ I2C2RST
+ I2C2 reset
+ 22
+ 1
+
+
+ USBRST
+ USB reset
+ 23
+ 1
+
+
+ CANRST
+ CAN reset
+ 25
+ 1
+
+
+ PWRRST
+ Power interface reset
+ 28
+ 1
+
+
+ DACRST
+ DAC interface reset
+ 29
+ 1
+
+
+ I2C3RST
+ I2C3 reset
+ 30
+ 1
+
+
+
+
+ AHBENR
+ AHBENR
+ AHB Peripheral Clock enable register
+ (RCC_AHBENR)
+ 0x14
+ 0x20
+ read-write
+ 0x00000014
+
+
+ DMAEN
+ DMA1 clock enable
+ 0
+ 1
+
+
+ DMA2EN
+ DMA2 clock enable
+ 1
+ 1
+
+
+ SRAMEN
+ SRAM interface clock
+ enable
+ 2
+ 1
+
+
+ FLITFEN
+ FLITF clock enable
+ 4
+ 1
+
+
+ FMCEN
+ FMC clock enable
+ 5
+ 1
+
+
+ CRCEN
+ CRC clock enable
+ 6
+ 1
+
+
+ IOPHEN
+ IO port H clock enable
+ 16
+ 1
+
+
+ IOPAEN
+ I/O port A clock enable
+ 17
+ 1
+
+
+ IOPBEN
+ I/O port B clock enable
+ 18
+ 1
+
+
+ IOPCEN
+ I/O port C clock enable
+ 19
+ 1
+
+
+ IOPDEN
+ I/O port D clock enable
+ 20
+ 1
+
+
+ IOPEEN
+ I/O port E clock enable
+ 21
+ 1
+
+
+ IOPFEN
+ I/O port F clock enable
+ 22
+ 1
+
+
+ IOPGEN
+ I/O port G clock enable
+ 23
+ 1
+
+
+ TSCEN
+ Touch sensing controller clock
+ enable
+ 24
+ 1
+
+
+ ADC12EN
+ ADC1 and ADC2 clock enable
+ 28
+ 1
+
+
+ ADC34EN
+ ADC3 and ADC4 clock enable
+ 29
+ 1
+
+
+
+
+ APB2ENR
+ APB2ENR
+ APB2 peripheral clock enable register
+ (RCC_APB2ENR)
+ 0x18
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SYSCFGEN
+ SYSCFG clock enable
+ 0
+ 1
+
+
+ TIM1EN
+ TIM1 Timer clock enable
+ 11
+ 1
+
+
+ SPI1EN
+ SPI 1 clock enable
+ 12
+ 1
+
+
+ TIM8EN
+ TIM8 Timer clock enable
+ 13
+ 1
+
+
+ USART1EN
+ USART1 clock enable
+ 14
+ 1
+
+
+ TIM15EN
+ TIM15 timer clock enable
+ 16
+ 1
+
+
+ TIM16EN
+ TIM16 timer clock enable
+ 17
+ 1
+
+
+ TIM17EN
+ TIM17 timer clock enable
+ 18
+ 1
+
+
+
+
+ APB1ENR
+ APB1ENR
+ APB1 peripheral clock enable register
+ (RCC_APB1ENR)
+ 0x1C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ TIM2EN
+ Timer 2 clock enable
+ 0
+ 1
+
+
+ TIM3EN
+ Timer 3 clock enable
+ 1
+ 1
+
+
+ TIM4EN
+ Timer 4 clock enable
+ 2
+ 1
+
+
+ TIM6EN
+ Timer 6 clock enable
+ 4
+ 1
+
+
+ TIM7EN
+ Timer 7 clock enable
+ 5
+ 1
+
+
+ WWDGEN
+ Window watchdog clock
+ enable
+ 11
+ 1
+
+
+ SPI2EN
+ SPI 2 clock enable
+ 14
+ 1
+
+
+ SPI3EN
+ SPI 3 clock enable
+ 15
+ 1
+
+
+ USART2EN
+ USART 2 clock enable
+ 17
+ 1
+
+
+ USART3EN
+ USART 3 clock enable
+ 18
+ 1
+
+
+ USART4EN
+ USART 4 clock enable
+ 19
+ 1
+
+
+ USART5EN
+ USART 5 clock enable
+ 20
+ 1
+
+
+ I2C1EN
+ I2C 1 clock enable
+ 21
+ 1
+
+
+ I2C2EN
+ I2C 2 clock enable
+ 22
+ 1
+
+
+ USBEN
+ USB clock enable
+ 23
+ 1
+
+
+ CANEN
+ CAN clock enable
+ 25
+ 1
+
+
+ DAC2EN
+ DAC2 interface clock
+ enable
+ 26
+ 1
+
+
+ PWREN
+ Power interface clock
+ enable
+ 28
+ 1
+
+
+ DACEN
+ DAC interface clock enable
+ 29
+ 1
+
+
+ I2C3EN
+ I2C3 clock enable
+ 30
+ 1
+
+
+
+
+ BDCR
+ BDCR
+ Backup domain control register
+ (RCC_BDCR)
+ 0x20
+ 0x20
+ 0x00000000
+
+
+ LSEON
+ External Low Speed oscillator
+ enable
+ 0
+ 1
+ read-write
+
+
+ LSERDY
+ External Low Speed oscillator
+ ready
+ 1
+ 1
+ read-only
+
+
+ LSEBYP
+ External Low Speed oscillator
+ bypass
+ 2
+ 1
+ read-write
+
+
+ LSEDRV
+ LSE oscillator drive
+ capability
+ 3
+ 2
+ read-write
+
+
+ RTCSEL
+ RTC clock source selection
+ 8
+ 2
+ read-write
+
+
+ RTCEN
+ RTC clock enable
+ 15
+ 1
+ read-write
+
+
+ BDRST
+ Backup domain software
+ reset
+ 16
+ 1
+ read-write
+
+
+
+
+ CSR
+ CSR
+ Control/status register
+ (RCC_CSR)
+ 0x24
+ 0x20
+ 0x0C000000
+
+
+ LSION
+ Internal low speed oscillator
+ enable
+ 0
+ 1
+ read-write
+
+
+ LSIRDY
+ Internal low speed oscillator
+ ready
+ 1
+ 1
+ read-only
+
+
+ RMVF
+ Remove reset flag
+ 24
+ 1
+ read-write
+
+
+ OBLRSTF
+ Option byte loader reset
+ flag
+ 25
+ 1
+ read-write
+
+
+ PINRSTF
+ PIN reset flag
+ 26
+ 1
+ read-write
+
+
+ PORRSTF
+ POR/PDR reset flag
+ 27
+ 1
+ read-write
+
+
+ SFTRSTF
+ Software reset flag
+ 28
+ 1
+ read-write
+
+
+ IWDGRSTF
+ Independent watchdog reset
+ flag
+ 29
+ 1
+ read-write
+
+
+ WWDGRSTF
+ Window watchdog reset flag
+ 30
+ 1
+ read-write
+
+
+ LPWRRSTF
+ Low-power reset flag
+ 31
+ 1
+ read-write
+
+
+
+
+ AHBRSTR
+ AHBRSTR
+ AHB peripheral reset register
+ 0x28
+ 0x20
+ read-write
+ 0x00000000
+
+
+ FMCRST
+ FMC reset
+ 5
+ 1
+
+
+ IOPHRST
+ I/O port H reset
+ 16
+ 1
+
+
+ IOPARST
+ I/O port A reset
+ 17
+ 1
+
+
+ IOPBRST
+ I/O port B reset
+ 18
+ 1
+
+
+ IOPCRST
+ I/O port C reset
+ 19
+ 1
+
+
+ IOPDRST
+ I/O port D reset
+ 20
+ 1
+
+
+ IOPERST
+ I/O port E reset
+ 21
+ 1
+
+
+ IOPFRST
+ I/O port F reset
+ 22
+ 1
+
+
+ IOPGRST
+ Touch sensing controller
+ reset
+ 23
+ 1
+
+
+ TSCRST
+ Touch sensing controller
+ reset
+ 24
+ 1
+
+
+ ADC12RST
+ ADC1 and ADC2 reset
+ 28
+ 1
+
+
+ ADC34RST
+ ADC3 and ADC4 reset
+ 29
+ 1
+
+
+
+
+ CFGR2
+ CFGR2
+ Clock configuration register 2
+ 0x2C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PREDIV
+ PREDIV division factor
+ 0
+ 4
+
+
+ ADC12PRES
+ ADC1 and ADC2 prescaler
+ 4
+ 5
+
+
+ ADC34PRES
+ ADC3 and ADC4 prescaler
+ 9
+ 5
+
+
+
+
+ CFGR3
+ CFGR3
+ Clock configuration register 3
+ 0x30
+ 0x20
+ read-write
+ 0x00000000
+
+
+ USART1SW
+ USART1 clock source
+ selection
+ 0
+ 2
+
+
+ I2C1SW
+ I2C1 clock source
+ selection
+ 4
+ 1
+
+
+ I2C2SW
+ I2C2 clock source
+ selection
+ 5
+ 1
+
+
+ I2C3SW
+ I2C3 clock source
+ selection
+ 6
+ 1
+
+
+ USART2SW
+ USART2 clock source
+ selection
+ 16
+ 2
+
+
+ USART3SW
+ USART3 clock source
+ selection
+ 18
+ 2
+
+
+ TIM1SW
+ Timer1 clock source
+ selection
+ 8
+ 1
+
+
+ TIM8SW
+ Timer8 clock source
+ selection
+ 9
+ 1
+
+
+ UART4SW
+ UART4 clock source
+ selection
+ 20
+ 2
+
+
+ UART5SW
+ UART5 clock source
+ selection
+ 22
+ 2
+
+
+
+
+
+
+ DMA1
+ DMA controller 1
+ DMA
+ 0x40020000
+
+ 0x0
+ 0x400
+ registers
+
+
+ DMA1_CH1
+ DMA1 channel 1 interrupt
+ 11
+
+
+ DMA1_CH2
+ DMA1 channel 2 interrupt
+ 12
+
+
+ DMA1_CH3
+ DMA1 channel 3 interrupt
+ 13
+
+
+ DMA1_CH4
+ DMA1 channel 4 interrupt
+ 14
+
+
+ DMA1_CH5
+ DMA1 channel 5 interrupt
+ 15
+
+
+ DMA1_CH6
+ DMA1 channel 6 interrupt
+ 16
+
+
+ DMA1_CH7
+ DMA1 channel 7interrupt
+ 17
+
+
+
+ ISR
+ ISR
+ DMA interrupt status register
+ (DMA_ISR)
+ 0x0
+ 0x20
+ read-only
+ 0x00000000
+
+
+ GIF1
+ Channel 1 Global interrupt
+ flag
+ 0
+ 1
+
+
+ TCIF1
+ Channel 1 Transfer Complete
+ flag
+ 1
+ 1
+
+
+ HTIF1
+ Channel 1 Half Transfer Complete
+ flag
+ 2
+ 1
+
+
+ TEIF1
+ Channel 1 Transfer Error
+ flag
+ 3
+ 1
+
+
+ GIF2
+ Channel 2 Global interrupt
+ flag
+ 4
+ 1
+
+
+ TCIF2
+ Channel 2 Transfer Complete
+ flag
+ 5
+ 1
+
+
+ HTIF2
+ Channel 2 Half Transfer Complete
+ flag
+ 6
+ 1
+
+
+ TEIF2
+ Channel 2 Transfer Error
+ flag
+ 7
+ 1
+
+
+ GIF3
+ Channel 3 Global interrupt
+ flag
+ 8
+ 1
+
+
+ TCIF3
+ Channel 3 Transfer Complete
+ flag
+ 9
+ 1
+
+
+ HTIF3
+ Channel 3 Half Transfer Complete
+ flag
+ 10
+ 1
+
+
+ TEIF3
+ Channel 3 Transfer Error
+ flag
+ 11
+ 1
+
+
+ GIF4
+ Channel 4 Global interrupt
+ flag
+ 12
+ 1
+
+
+ TCIF4
+ Channel 4 Transfer Complete
+ flag
+ 13
+ 1
+
+
+ HTIF4
+ Channel 4 Half Transfer Complete
+ flag
+ 14
+ 1
+
+
+ TEIF4
+ Channel 4 Transfer Error
+ flag
+ 15
+ 1
+
+
+ GIF5
+ Channel 5 Global interrupt
+ flag
+ 16
+ 1
+
+
+ TCIF5
+ Channel 5 Transfer Complete
+ flag
+ 17
+ 1
+
+
+ HTIF5
+ Channel 5 Half Transfer Complete
+ flag
+ 18
+ 1
+
+
+ TEIF5
+ Channel 5 Transfer Error
+ flag
+ 19
+ 1
+
+
+ GIF6
+ Channel 6 Global interrupt
+ flag
+ 20
+ 1
+
+
+ TCIF6
+ Channel 6 Transfer Complete
+ flag
+ 21
+ 1
+
+
+ HTIF6
+ Channel 6 Half Transfer Complete
+ flag
+ 22
+ 1
+
+
+ TEIF6
+ Channel 6 Transfer Error
+ flag
+ 23
+ 1
+
+
+ GIF7
+ Channel 7 Global interrupt
+ flag
+ 24
+ 1
+
+
+ TCIF7
+ Channel 7 Transfer Complete
+ flag
+ 25
+ 1
+
+
+ HTIF7
+ Channel 7 Half Transfer Complete
+ flag
+ 26
+ 1
+
+
+ TEIF7
+ Channel 7 Transfer Error
+ flag
+ 27
+ 1
+
+
+
+
+ IFCR
+ IFCR
+ DMA interrupt flag clear register
+ (DMA_IFCR)
+ 0x4
+ 0x20
+ write-only
+ 0x00000000
+
+
+ CGIF1
+ Channel 1 Global interrupt
+ clear
+ 0
+ 1
+
+
+ CTCIF1
+ Channel 1 Transfer Complete
+ clear
+ 1
+ 1
+
+
+ CHTIF1
+ Channel 1 Half Transfer
+ clear
+ 2
+ 1
+
+
+ CTEIF1
+ Channel 1 Transfer Error
+ clear
+ 3
+ 1
+
+
+ CGIF2
+ Channel 2 Global interrupt
+ clear
+ 4
+ 1
+
+
+ CTCIF2
+ Channel 2 Transfer Complete
+ clear
+ 5
+ 1
+
+
+ CHTIF2
+ Channel 2 Half Transfer
+ clear
+ 6
+ 1
+
+
+ CTEIF2
+ Channel 2 Transfer Error
+ clear
+ 7
+ 1
+
+
+ CGIF3
+ Channel 3 Global interrupt
+ clear
+ 8
+ 1
+
+
+ CTCIF3
+ Channel 3 Transfer Complete
+ clear
+ 9
+ 1
+
+
+ CHTIF3
+ Channel 3 Half Transfer
+ clear
+ 10
+ 1
+
+
+ CTEIF3
+ Channel 3 Transfer Error
+ clear
+ 11
+ 1
+
+
+ CGIF4
+ Channel 4 Global interrupt
+ clear
+ 12
+ 1
+
+
+ CTCIF4
+ Channel 4 Transfer Complete
+ clear
+ 13
+ 1
+
+
+ CHTIF4
+ Channel 4 Half Transfer
+ clear
+ 14
+ 1
+
+
+ CTEIF4
+ Channel 4 Transfer Error
+ clear
+ 15
+ 1
+
+
+ CGIF5
+ Channel 5 Global interrupt
+ clear
+ 16
+ 1
+
+
+ CTCIF5
+ Channel 5 Transfer Complete
+ clear
+ 17
+ 1
+
+
+ CHTIF5
+ Channel 5 Half Transfer
+ clear
+ 18
+ 1
+
+
+ CTEIF5
+ Channel 5 Transfer Error
+ clear
+ 19
+ 1
+
+
+ CGIF6
+ Channel 6 Global interrupt
+ clear
+ 20
+ 1
+
+
+ CTCIF6
+ Channel 6 Transfer Complete
+ clear
+ 21
+ 1
+
+
+ CHTIF6
+ Channel 6 Half Transfer
+ clear
+ 22
+ 1
+
+
+ CTEIF6
+ Channel 6 Transfer Error
+ clear
+ 23
+ 1
+
+
+ CGIF7
+ Channel 7 Global interrupt
+ clear
+ 24
+ 1
+
+
+ CTCIF7
+ Channel 7 Transfer Complete
+ clear
+ 25
+ 1
+
+
+ CHTIF7
+ Channel 7 Half Transfer
+ clear
+ 26
+ 1
+
+
+ CTEIF7
+ Channel 7 Transfer Error
+ clear
+ 27
+ 1
+
+
+
+
+ CCR1
+ CCR1
+ DMA channel configuration register
+ (DMA_CCR)
+ 0x8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ EN
+ Channel enable
+ 0
+ 1
+
+
+ TCIE
+ Transfer complete interrupt
+ enable
+ 1
+ 1
+
+
+ HTIE
+ Half Transfer interrupt
+ enable
+ 2
+ 1
+
+
+ TEIE
+ Transfer error interrupt
+ enable
+ 3
+ 1
+
+
+ DIR
+ Data transfer direction
+ 4
+ 1
+
+
+ CIRC
+ Circular mode
+ 5
+ 1
+
+
+ PINC
+ Peripheral increment mode
+ 6
+ 1
+
+
+ MINC
+ Memory increment mode
+ 7
+ 1
+
+
+ PSIZE
+ Peripheral size
+ 8
+ 2
+
+
+ MSIZE
+ Memory size
+ 10
+ 2
+
+
+ PL
+ Channel Priority level
+ 12
+ 2
+
+
+ MEM2MEM
+ Memory to memory mode
+ 14
+ 1
+
+
+
+
+ CNDTR1
+ CNDTR1
+ DMA channel 1 number of data
+ register
+ 0xC
+ 0x20
+ read-write
+ 0x00000000
+
+
+ NDT
+ Number of data to transfer
+ 0
+ 16
+
+
+
+
+ CPAR1
+ CPAR1
+ DMA channel 1 peripheral address
+ register
+ 0x10
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PA
+ Peripheral address
+ 0
+ 32
+
+
+
+
+ CMAR1
+ CMAR1
+ DMA channel 1 memory address
+ register
+ 0x14
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MA
+ Memory address
+ 0
+ 32
+
+
+
+
+ CCR2
+ CCR2
+ DMA channel configuration register
+ (DMA_CCR)
+ 0x1C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ EN
+ Channel enable
+ 0
+ 1
+
+
+ TCIE
+ Transfer complete interrupt
+ enable
+ 1
+ 1
+
+
+ HTIE
+ Half Transfer interrupt
+ enable
+ 2
+ 1
+
+
+ TEIE
+ Transfer error interrupt
+ enable
+ 3
+ 1
+
+
+ DIR
+ Data transfer direction
+ 4
+ 1
+
+
+ CIRC
+ Circular mode
+ 5
+ 1
+
+
+ PINC
+ Peripheral increment mode
+ 6
+ 1
+
+
+ MINC
+ Memory increment mode
+ 7
+ 1
+
+
+ PSIZE
+ Peripheral size
+ 8
+ 2
+
+
+ MSIZE
+ Memory size
+ 10
+ 2
+
+
+ PL
+ Channel Priority level
+ 12
+ 2
+
+
+ MEM2MEM
+ Memory to memory mode
+ 14
+ 1
+
+
+
+
+ CNDTR2
+ CNDTR2
+ DMA channel 2 number of data
+ register
+ 0x20
+ 0x20
+ read-write
+ 0x00000000
+
+
+ NDT
+ Number of data to transfer
+ 0
+ 16
+
+
+
+
+ CPAR2
+ CPAR2
+ DMA channel 2 peripheral address
+ register
+ 0x24
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PA
+ Peripheral address
+ 0
+ 32
+
+
+
+
+ CMAR2
+ CMAR2
+ DMA channel 2 memory address
+ register
+ 0x28
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MA
+ Memory address
+ 0
+ 32
+
+
+
+
+ CCR3
+ CCR3
+ DMA channel configuration register
+ (DMA_CCR)
+ 0x30
+ 0x20
+ read-write
+ 0x00000000
+
+
+ EN
+ Channel enable
+ 0
+ 1
+
+
+ TCIE
+ Transfer complete interrupt
+ enable
+ 1
+ 1
+
+
+ HTIE
+ Half Transfer interrupt
+ enable
+ 2
+ 1
+
+
+ TEIE
+ Transfer error interrupt
+ enable
+ 3
+ 1
+
+
+ DIR
+ Data transfer direction
+ 4
+ 1
+
+
+ CIRC
+ Circular mode
+ 5
+ 1
+
+
+ PINC
+ Peripheral increment mode
+ 6
+ 1
+
+
+ MINC
+ Memory increment mode
+ 7
+ 1
+
+
+ PSIZE
+ Peripheral size
+ 8
+ 2
+
+
+ MSIZE
+ Memory size
+ 10
+ 2
+
+
+ PL
+ Channel Priority level
+ 12
+ 2
+
+
+ MEM2MEM
+ Memory to memory mode
+ 14
+ 1
+
+
+
+
+ CNDTR3
+ CNDTR3
+ DMA channel 3 number of data
+ register
+ 0x34
+ 0x20
+ read-write
+ 0x00000000
+
+
+ NDT
+ Number of data to transfer
+ 0
+ 16
+
+
+
+
+ CPAR3
+ CPAR3
+ DMA channel 3 peripheral address
+ register
+ 0x38
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PA
+ Peripheral address
+ 0
+ 32
+
+
+
+
+ CMAR3
+ CMAR3
+ DMA channel 3 memory address
+ register
+ 0x3C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MA
+ Memory address
+ 0
+ 32
+
+
+
+
+ CCR4
+ CCR4
+ DMA channel configuration register
+ (DMA_CCR)
+ 0x44
+ 0x20
+ read-write
+ 0x00000000
+
+
+ EN
+ Channel enable
+ 0
+ 1
+
+
+ TCIE
+ Transfer complete interrupt
+ enable
+ 1
+ 1
+
+
+ HTIE
+ Half Transfer interrupt
+ enable
+ 2
+ 1
+
+
+ TEIE
+ Transfer error interrupt
+ enable
+ 3
+ 1
+
+
+ DIR
+ Data transfer direction
+ 4
+ 1
+
+
+ CIRC
+ Circular mode
+ 5
+ 1
+
+
+ PINC
+ Peripheral increment mode
+ 6
+ 1
+
+
+ MINC
+ Memory increment mode
+ 7
+ 1
+
+
+ PSIZE
+ Peripheral size
+ 8
+ 2
+
+
+ MSIZE
+ Memory size
+ 10
+ 2
+
+
+ PL
+ Channel Priority level
+ 12
+ 2
+
+
+ MEM2MEM
+ Memory to memory mode
+ 14
+ 1
+
+
+
+
+ CNDTR4
+ CNDTR4
+ DMA channel 4 number of data
+ register
+ 0x48
+ 0x20
+ read-write
+ 0x00000000
+
+
+ NDT
+ Number of data to transfer
+ 0
+ 16
+
+
+
+
+ CPAR4
+ CPAR4
+ DMA channel 4 peripheral address
+ register
+ 0x4C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PA
+ Peripheral address
+ 0
+ 32
+
+
+
+
+ CMAR4
+ CMAR4
+ DMA channel 4 memory address
+ register
+ 0x50
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MA
+ Memory address
+ 0
+ 32
+
+
+
+
+ CCR5
+ CCR5
+ DMA channel configuration register
+ (DMA_CCR)
+ 0x58
+ 0x20
+ read-write
+ 0x00000000
+
+
+ EN
+ Channel enable
+ 0
+ 1
+
+
+ TCIE
+ Transfer complete interrupt
+ enable
+ 1
+ 1
+
+
+ HTIE
+ Half Transfer interrupt
+ enable
+ 2
+ 1
+
+
+ TEIE
+ Transfer error interrupt
+ enable
+ 3
+ 1
+
+
+ DIR
+ Data transfer direction
+ 4
+ 1
+
+
+ CIRC
+ Circular mode
+ 5
+ 1
+
+
+ PINC
+ Peripheral increment mode
+ 6
+ 1
+
+
+ MINC
+ Memory increment mode
+ 7
+ 1
+
+
+ PSIZE
+ Peripheral size
+ 8
+ 2
+
+
+ MSIZE
+ Memory size
+ 10
+ 2
+
+
+ PL
+ Channel Priority level
+ 12
+ 2
+
+
+ MEM2MEM
+ Memory to memory mode
+ 14
+ 1
+
+
+
+
+ CNDTR5
+ CNDTR5
+ DMA channel 5 number of data
+ register
+ 0x5C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ NDT
+ Number of data to transfer
+ 0
+ 16
+
+
+
+
+ CPAR5
+ CPAR5
+ DMA channel 5 peripheral address
+ register
+ 0x60
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PA
+ Peripheral address
+ 0
+ 32
+
+
+
+
+ CMAR5
+ CMAR5
+ DMA channel 5 memory address
+ register
+ 0x64
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MA
+ Memory address
+ 0
+ 32
+
+
+
+
+ CCR6
+ CCR6
+ DMA channel configuration register
+ (DMA_CCR)
+ 0x6C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ EN
+ Channel enable
+ 0
+ 1
+
+
+ TCIE
+ Transfer complete interrupt
+ enable
+ 1
+ 1
+
+
+ HTIE
+ Half Transfer interrupt
+ enable
+ 2
+ 1
+
+
+ TEIE
+ Transfer error interrupt
+ enable
+ 3
+ 1
+
+
+ DIR
+ Data transfer direction
+ 4
+ 1
+
+
+ CIRC
+ Circular mode
+ 5
+ 1
+
+
+ PINC
+ Peripheral increment mode
+ 6
+ 1
+
+
+ MINC
+ Memory increment mode
+ 7
+ 1
+
+
+ PSIZE
+ Peripheral size
+ 8
+ 2
+
+
+ MSIZE
+ Memory size
+ 10
+ 2
+
+
+ PL
+ Channel Priority level
+ 12
+ 2
+
+
+ MEM2MEM
+ Memory to memory mode
+ 14
+ 1
+
+
+
+
+ CNDTR6
+ CNDTR6
+ DMA channel 6 number of data
+ register
+ 0x70
+ 0x20
+ read-write
+ 0x00000000
+
+
+ NDT
+ Number of data to transfer
+ 0
+ 16
+
+
+
+
+ CPAR6
+ CPAR6
+ DMA channel 6 peripheral address
+ register
+ 0x74
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PA
+ Peripheral address
+ 0
+ 32
+
+
+
+
+ CMAR6
+ CMAR6
+ DMA channel 6 memory address
+ register
+ 0x78
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MA
+ Memory address
+ 0
+ 32
+
+
+
+
+ CCR7
+ CCR7
+ DMA channel configuration register
+ (DMA_CCR)
+ 0x80
+ 0x20
+ read-write
+ 0x00000000
+
+
+ EN
+ Channel enable
+ 0
+ 1
+
+
+ TCIE
+ Transfer complete interrupt
+ enable
+ 1
+ 1
+
+
+ HTIE
+ Half Transfer interrupt
+ enable
+ 2
+ 1
+
+
+ TEIE
+ Transfer error interrupt
+ enable
+ 3
+ 1
+
+
+ DIR
+ Data transfer direction
+ 4
+ 1
+
+
+ CIRC
+ Circular mode
+ 5
+ 1
+
+
+ PINC
+ Peripheral increment mode
+ 6
+ 1
+
+
+ MINC
+ Memory increment mode
+ 7
+ 1
+
+
+ PSIZE
+ Peripheral size
+ 8
+ 2
+
+
+ MSIZE
+ Memory size
+ 10
+ 2
+
+
+ PL
+ Channel Priority level
+ 12
+ 2
+
+
+ MEM2MEM
+ Memory to memory mode
+ 14
+ 1
+
+
+
+
+ CNDTR7
+ CNDTR7
+ DMA channel 7 number of data
+ register
+ 0x84
+ 0x20
+ read-write
+ 0x00000000
+
+
+ NDT
+ Number of data to transfer
+ 0
+ 16
+
+
+
+
+ CPAR7
+ CPAR7
+ DMA channel 7 peripheral address
+ register
+ 0x88
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PA
+ Peripheral address
+ 0
+ 32
+
+
+
+
+ CMAR7
+ CMAR7
+ DMA channel 7 memory address
+ register
+ 0x8C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MA
+ Memory address
+ 0
+ 32
+
+
+
+
+
+
+ DMA2
+ 0x40020400
+
+ DMA2_CH1
+ DMA2 channel1 global interrupt
+ 56
+
+
+ DMA2_CH2
+ DMA2 channel2 global interrupt
+ 57
+
+
+ DMA2_CH3
+ DMA2 channel3 global interrupt
+ 58
+
+
+ DMA2_CH4
+ DMA2 channel4 global interrupt
+ 59
+
+
+ DMA2_CH5
+ DMA2 channel5 global interrupt
+ 60
+
+
+
+ TIM2
+ General purpose timer
+ TIMs
+ 0x40000000
+
+ 0x0
+ 0x400
+ registers
+
+
+ TIM2
+ TIM2 global interrupt
+ 28
+
+
+
+ CR1
+ CR1
+ control register 1
+ 0x0
+ 0x20
+ read-write
+ 0x0000
+
+
+ CEN
+ Counter enable
+ 0
+ 1
+
+
+ UDIS
+ Update disable
+ 1
+ 1
+
+
+ URS
+ Update request source
+ 2
+ 1
+
+
+ OPM
+ One-pulse mode
+ 3
+ 1
+
+
+ DIR
+ Direction
+ 4
+ 1
+
+
+ CMS
+ Center-aligned mode
+ selection
+ 5
+ 2
+
+
+ ARPE
+ Auto-reload preload enable
+ 7
+ 1
+
+
+ CKD
+ Clock division
+ 8
+ 2
+
+
+ UIFREMAP
+ UIF status bit remapping
+ 11
+ 1
+
+
+
+
+ CR2
+ CR2
+ control register 2
+ 0x4
+ 0x20
+ read-write
+ 0x0000
+
+
+ TI1S
+ TI1 selection
+ 7
+ 1
+
+
+ MMS
+ Master mode selection
+ 4
+ 3
+
+
+ CCDS
+ Capture/compare DMA
+ selection
+ 3
+ 1
+
+
+
+
+ SMCR
+ SMCR
+ slave mode control register
+ 0x8
+ 0x20
+ read-write
+ 0x0000
+
+
+ SMS
+ Slave mode selection
+ 0
+ 3
+
+
+ OCCS
+ OCREF clear selection
+ 3
+ 1
+
+
+ TS
+ Trigger selection
+ 4
+ 3
+
+
+ MSM
+ Master/Slave mode
+ 7
+ 1
+
+
+ ETF
+ External trigger filter
+ 8
+ 4
+
+
+ ETPS
+ External trigger prescaler
+ 12
+ 2
+
+
+ ECE
+ External clock enable
+ 14
+ 1
+
+
+ ETP
+ External trigger polarity
+ 15
+ 1
+
+
+ SMS_3
+ Slave mode selection bit3
+ 16
+ 1
+
+
+
+
+ DIER
+ DIER
+ DMA/Interrupt enable register
+ 0xC
+ 0x20
+ read-write
+ 0x0000
+
+
+ TDE
+ Trigger DMA request enable
+ 14
+ 1
+
+
+ CC4DE
+ Capture/Compare 4 DMA request
+ enable
+ 12
+ 1
+
+
+ CC3DE
+ Capture/Compare 3 DMA request
+ enable
+ 11
+ 1
+
+
+ CC2DE
+ Capture/Compare 2 DMA request
+ enable
+ 10
+ 1
+
+
+ CC1DE
+ Capture/Compare 1 DMA request
+ enable
+ 9
+ 1
+
+
+ UDE
+ Update DMA request enable
+ 8
+ 1
+
+
+ TIE
+ Trigger interrupt enable
+ 6
+ 1
+
+
+ CC4IE
+ Capture/Compare 4 interrupt
+ enable
+ 4
+ 1
+
+
+ CC3IE
+ Capture/Compare 3 interrupt
+ enable
+ 3
+ 1
+
+
+ CC2IE
+ Capture/Compare 2 interrupt
+ enable
+ 2
+ 1
+
+
+ CC1IE
+ Capture/Compare 1 interrupt
+ enable
+ 1
+ 1
+
+
+ UIE
+ Update interrupt enable
+ 0
+ 1
+
+
+
+
+ SR
+ SR
+ status register
+ 0x10
+ 0x20
+ read-write
+ 0x0000
+
+
+ CC4OF
+ Capture/Compare 4 overcapture
+ flag
+ 12
+ 1
+
+
+ CC3OF
+ Capture/Compare 3 overcapture
+ flag
+ 11
+ 1
+
+
+ CC2OF
+ Capture/compare 2 overcapture
+ flag
+ 10
+ 1
+
+
+ CC1OF
+ Capture/Compare 1 overcapture
+ flag
+ 9
+ 1
+
+
+ TIF
+ Trigger interrupt flag
+ 6
+ 1
+
+
+ CC4IF
+ Capture/Compare 4 interrupt
+ flag
+ 4
+ 1
+
+
+ CC3IF
+ Capture/Compare 3 interrupt
+ flag
+ 3
+ 1
+
+
+ CC2IF
+ Capture/Compare 2 interrupt
+ flag
+ 2
+ 1
+
+
+ CC1IF
+ Capture/compare 1 interrupt
+ flag
+ 1
+ 1
+
+
+ UIF
+ Update interrupt flag
+ 0
+ 1
+
+
+
+
+ EGR
+ EGR
+ event generation register
+ 0x14
+ 0x20
+ write-only
+ 0x0000
+
+
+ TG
+ Trigger generation
+ 6
+ 1
+
+
+ CC4G
+ Capture/compare 4
+ generation
+ 4
+ 1
+
+
+ CC3G
+ Capture/compare 3
+ generation
+ 3
+ 1
+
+
+ CC2G
+ Capture/compare 2
+ generation
+ 2
+ 1
+
+
+ CC1G
+ Capture/compare 1
+ generation
+ 1
+ 1
+
+
+ UG
+ Update generation
+ 0
+ 1
+
+
+
+
+ CCMR1_Output
+ CCMR1_Output
+ capture/compare mode register 1 (output
+ mode)
+ 0x18
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CC1S
+ Capture/Compare 1
+ selection
+ 0
+ 2
+
+
+ OC1FE
+ Output compare 1 fast
+ enable
+ 2
+ 1
+
+
+ OC1PE
+ Output compare 1 preload
+ enable
+ 3
+ 1
+
+
+ OC1M
+ Output compare 1 mode
+ 4
+ 3
+
+
+ OC1CE
+ Output compare 1 clear
+ enable
+ 7
+ 1
+
+
+ CC2S
+ Capture/Compare 2
+ selection
+ 8
+ 2
+
+
+ OC2FE
+ Output compare 2 fast
+ enable
+ 10
+ 1
+
+
+ OC2PE
+ Output compare 2 preload
+ enable
+ 11
+ 1
+
+
+ OC2M
+ Output compare 2 mode
+ 12
+ 3
+
+
+ OC2CE
+ Output compare 2 clear
+ enable
+ 15
+ 1
+
+
+ OC1M_3
+ Output compare 1 mode bit
+ 3
+ 16
+ 1
+
+
+ OC2M_3
+ Output compare 2 mode bit
+ 3
+ 24
+ 1
+
+
+
+
+ CCMR1_Input
+ CCMR1_Input
+ capture/compare mode register 1 (input
+ mode)
+ CCMR1_Output
+ 0x18
+ 0x20
+ read-write
+ 0x00000000
+
+
+ IC2F
+ Input capture 2 filter
+ 12
+ 4
+
+
+ IC2PSC
+ Input capture 2 prescaler
+ 10
+ 2
+
+
+ CC2S
+ Capture/compare 2
+ selection
+ 8
+ 2
+
+
+ IC1F
+ Input capture 1 filter
+ 4
+ 4
+
+
+ IC1PSC
+ Input capture 1 prescaler
+ 2
+ 2
+
+
+ CC1S
+ Capture/Compare 1
+ selection
+ 0
+ 2
+
+
+
+
+ CCMR2_Output
+ CCMR2_Output
+ capture/compare mode register 2 (output
+ mode)
+ 0x1C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CC3S
+ Capture/Compare 3
+ selection
+ 0
+ 2
+
+
+ OC3FE
+ Output compare 3 fast
+ enable
+ 2
+ 1
+
+
+ OC3PE
+ Output compare 3 preload
+ enable
+ 3
+ 1
+
+
+ OC3M
+ Output compare 3 mode
+ 4
+ 3
+
+
+ OC3CE
+ Output compare 3 clear
+ enable
+ 7
+ 1
+
+
+ CC4S
+ Capture/Compare 4
+ selection
+ 8
+ 2
+
+
+ OC4FE
+ Output compare 4 fast
+ enable
+ 10
+ 1
+
+
+ OC4PE
+ Output compare 4 preload
+ enable
+ 11
+ 1
+
+
+ OC4M
+ Output compare 4 mode
+ 12
+ 3
+
+
+ O24CE
+ Output compare 4 clear
+ enable
+ 15
+ 1
+
+
+ OC3M_3
+ Output compare 3 mode bit3
+ 16
+ 1
+
+
+ OC4M_3
+ Output compare 4 mode bit3
+ 24
+ 1
+
+
+
+
+ CCMR2_Input
+ CCMR2_Input
+ capture/compare mode register 2 (input
+ mode)
+ CCMR2_Output
+ 0x1C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ IC4F
+ Input capture 4 filter
+ 12
+ 4
+
+
+ IC4PSC
+ Input capture 4 prescaler
+ 10
+ 2
+
+
+ CC4S
+ Capture/Compare 4
+ selection
+ 8
+ 2
+
+
+ IC3F
+ Input capture 3 filter
+ 4
+ 4
+
+
+ IC3PSC
+ Input capture 3 prescaler
+ 2
+ 2
+
+
+ CC3S
+ Capture/Compare 3
+ selection
+ 0
+ 2
+
+
+
+
+ CCER
+ CCER
+ capture/compare enable
+ register
+ 0x20
+ 0x20
+ read-write
+ 0x0000
+
+
+ CC1E
+ Capture/Compare 1 output
+ enable
+ 0
+ 1
+
+
+ CC1P
+ Capture/Compare 1 output
+ Polarity
+ 1
+ 1
+
+
+ CC1NP
+ Capture/Compare 1 output
+ Polarity
+ 3
+ 1
+
+
+ CC2E
+ Capture/Compare 2 output
+ enable
+ 4
+ 1
+
+
+ CC2P
+ Capture/Compare 2 output
+ Polarity
+ 5
+ 1
+
+
+ CC2NP
+ Capture/Compare 2 output
+ Polarity
+ 7
+ 1
+
+
+ CC3E
+ Capture/Compare 3 output
+ enable
+ 8
+ 1
+
+
+ CC3P
+ Capture/Compare 3 output
+ Polarity
+ 9
+ 1
+
+
+ CC3NP
+ Capture/Compare 3 output
+ Polarity
+ 11
+ 1
+
+
+ CC4E
+ Capture/Compare 4 output
+ enable
+ 12
+ 1
+
+
+ CC4P
+ Capture/Compare 3 output
+ Polarity
+ 13
+ 1
+
+
+ CC4NP
+ Capture/Compare 3 output
+ Polarity
+ 15
+ 1
+
+
+
+
+ CNT
+ CNT
+ counter
+ 0x24
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CNTL
+ Low counter value
+ 0
+ 16
+
+
+ CNTH
+ High counter value
+ 16
+ 15
+
+
+ CNT_or_UIFCPY
+ if IUFREMAP=0 than CNT with read write
+ access else UIFCPY with read only
+ access
+ 31
+ 1
+
+
+
+
+ PSC
+ PSC
+ prescaler
+ 0x28
+ 0x20
+ read-write
+ 0x0000
+
+
+ PSC
+ Prescaler value
+ 0
+ 16
+
+
+
+
+ ARR
+ ARR
+ auto-reload register
+ 0x2C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ ARRL
+ Low Auto-reload value
+ 0
+ 16
+
+
+ ARRH
+ High Auto-reload value
+ 16
+ 16
+
+
+
+
+ CCR1
+ CCR1
+ capture/compare register 1
+ 0x34
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CCR1L
+ Low Capture/Compare 1
+ value
+ 0
+ 16
+
+
+ CCR1H
+ High Capture/Compare 1 value (on
+ TIM2)
+ 16
+ 16
+
+
+
+
+ CCR2
+ CCR2
+ capture/compare register 2
+ 0x38
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CCR2L
+ Low Capture/Compare 2
+ value
+ 0
+ 16
+
+
+ CCR2H
+ High Capture/Compare 2 value (on
+ TIM2)
+ 16
+ 16
+
+
+
+
+ CCR3
+ CCR3
+ capture/compare register 3
+ 0x3C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CCR3L
+ Low Capture/Compare value
+ 0
+ 16
+
+
+ CCR3H
+ High Capture/Compare value (on
+ TIM2)
+ 16
+ 16
+
+
+
+
+ CCR4
+ CCR4
+ capture/compare register 4
+ 0x40
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CCR4L
+ Low Capture/Compare value
+ 0
+ 16
+
+
+ CCR4H
+ High Capture/Compare value (on
+ TIM2)
+ 16
+ 16
+
+
+
+
+ DCR
+ DCR
+ DMA control register
+ 0x48
+ 0x20
+ read-write
+ 0x0000
+
+
+ DBL
+ DMA burst length
+ 8
+ 5
+
+
+ DBA
+ DMA base address
+ 0
+ 5
+
+
+
+
+ DMAR
+ DMAR
+ DMA address for full transfer
+ 0x4C
+ 0x20
+ read-write
+ 0x0000
+
+
+ DMAB
+ DMA register for burst
+ accesses
+ 0
+ 16
+
+
+
+
+
+
+ TIM3
+ 0x40000400
+
+ TIM3
+ TIM3 global interrupt
+ 29
+
+
+
+ TIM4
+ 0x40000800
+
+ TIM4
+ TIM4 global interrupt
+ 30
+
+
+
+ TIM15
+ General purpose timers
+ TIMs
+ 0x40014000
+
+ 0x0
+ 0x400
+ registers
+
+
+
+ CR1
+ CR1
+ control register 1
+ 0x0
+ 0x20
+ read-write
+ 0x0000
+
+
+ CEN
+ Counter enable
+ 0
+ 1
+
+
+ UDIS
+ Update disable
+ 1
+ 1
+
+
+ URS
+ Update request source
+ 2
+ 1
+
+
+ OPM
+ One-pulse mode
+ 3
+ 1
+
+
+ ARPE
+ Auto-reload preload enable
+ 7
+ 1
+
+
+ CKD
+ Clock division
+ 8
+ 2
+
+
+ UIFREMAP
+ UIF status bit remapping
+ 11
+ 1
+
+
+
+
+ CR2
+ CR2
+ control register 2
+ 0x4
+ 0x20
+ read-write
+ 0x0000
+
+
+ CCPC
+ Capture/compare preloaded
+ control
+ 0
+ 1
+
+
+ CCUS
+ Capture/compare control update
+ selection
+ 2
+ 1
+
+
+ CCDS
+ Capture/compare DMA
+ selection
+ 3
+ 1
+
+
+ MMS
+ Master mode selection
+ 4
+ 3
+
+
+ TI1S
+ TI1 selection
+ 7
+ 1
+
+
+ OIS1
+ Output Idle state 1
+ 8
+ 1
+
+
+ OIS1N
+ Output Idle state 1
+ 9
+ 1
+
+
+ OIS2
+ Output Idle state 2
+ 10
+ 1
+
+
+
+
+ SMCR
+ SMCR
+ slave mode control register
+ 0x8
+ 0x20
+ read-write
+ 0x0000
+
+
+ SMS
+ Slave mode selection
+ 0
+ 3
+
+
+ TS
+ Trigger selection
+ 4
+ 3
+
+
+ MSM
+ Master/Slave mode
+ 7
+ 1
+
+
+ SMS_3
+ Slave mode selection bit 3
+ 16
+ 1
+
+
+
+
+ DIER
+ DIER
+ DMA/Interrupt enable register
+ 0xC
+ 0x20
+ read-write
+ 0x0000
+
+
+ UIE
+ Update interrupt enable
+ 0
+ 1
+
+
+ CC1IE
+ Capture/Compare 1 interrupt
+ enable
+ 1
+ 1
+
+
+ CC2IE
+ Capture/Compare 2 interrupt
+ enable
+ 2
+ 1
+
+
+ COMIE
+ COM interrupt enable
+ 5
+ 1
+
+
+ TIE
+ Trigger interrupt enable
+ 6
+ 1
+
+
+ BIE
+ Break interrupt enable
+ 7
+ 1
+
+
+ UDE
+ Update DMA request enable
+ 8
+ 1
+
+
+ CC1DE
+ Capture/Compare 1 DMA request
+ enable
+ 9
+ 1
+
+
+ CC2DE
+ Capture/Compare 2 DMA request
+ enable
+ 10
+ 1
+
+
+ COMDE
+ COM DMA request enable
+ 13
+ 1
+
+
+ TDE
+ Trigger DMA request enable
+ 14
+ 1
+
+
+
+
+ SR
+ SR
+ status register
+ 0x10
+ 0x20
+ read-write
+ 0x0000
+
+
+ CC2OF
+ Capture/compare 2 overcapture
+ flag
+ 10
+ 1
+
+
+ CC1OF
+ Capture/Compare 1 overcapture
+ flag
+ 9
+ 1
+
+
+ BIF
+ Break interrupt flag
+ 7
+ 1
+
+
+ TIF
+ Trigger interrupt flag
+ 6
+ 1
+
+
+ COMIF
+ COM interrupt flag
+ 5
+ 1
+
+
+ CC2IF
+ Capture/Compare 2 interrupt
+ flag
+ 2
+ 1
+
+
+ CC1IF
+ Capture/compare 1 interrupt
+ flag
+ 1
+ 1
+
+
+ UIF
+ Update interrupt flag
+ 0
+ 1
+
+
+
+
+ EGR
+ EGR
+ event generation register
+ 0x14
+ 0x20
+ write-only
+ 0x0000
+
+
+ BG
+ Break generation
+ 7
+ 1
+
+
+ TG
+ Trigger generation
+ 6
+ 1
+
+
+ COMG
+ Capture/Compare control update
+ generation
+ 5
+ 1
+
+
+ CC2G
+ Capture/compare 2
+ generation
+ 2
+ 1
+
+
+ CC1G
+ Capture/compare 1
+ generation
+ 1
+ 1
+
+
+ UG
+ Update generation
+ 0
+ 1
+
+
+
+
+ CCMR1_Output
+ CCMR1_Output
+ capture/compare mode register (output
+ mode)
+ 0x18
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CC1S
+ Capture/Compare 1
+ selection
+ 0
+ 2
+
+
+ OC1FE
+ Output Compare 1 fast
+ enable
+ 2
+ 1
+
+
+ OC1PE
+ Output Compare 1 preload
+ enable
+ 3
+ 1
+
+
+ OC1M
+ Output Compare 1 mode
+ 4
+ 3
+
+
+ CC2S
+ Capture/Compare 2
+ selection
+ 8
+ 2
+
+
+ OC2FE
+ Output Compare 2 fast
+ enable
+ 10
+ 1
+
+
+ OC2PE
+ Output Compare 2 preload
+ enable
+ 11
+ 1
+
+
+ OC2M
+ Output Compare 2 mode
+ 12
+ 3
+
+
+ OC1M_3
+ Output Compare 1 mode bit
+ 3
+ 16
+ 1
+
+
+ OC2M_3
+ Output Compare 2 mode bit
+ 3
+ 24
+ 1
+
+
+
+
+ CCMR1_Input
+ CCMR1_Input
+ capture/compare mode register 1 (input
+ mode)
+ CCMR1_Output
+ 0x18
+ 0x20
+ read-write
+ 0x00000000
+
+
+ IC2F
+ Input capture 2 filter
+ 12
+ 4
+
+
+ IC2PSC
+ Input capture 2 prescaler
+ 10
+ 2
+
+
+ CC2S
+ Capture/Compare 2
+ selection
+ 8
+ 2
+
+
+ IC1F
+ Input capture 1 filter
+ 4
+ 4
+
+
+ IC1PSC
+ Input capture 1 prescaler
+ 2
+ 2
+
+
+ CC1S
+ Capture/Compare 1
+ selection
+ 0
+ 2
+
+
+
+
+ CCER
+ CCER
+ capture/compare enable
+ register
+ 0x20
+ 0x20
+ read-write
+ 0x0000
+
+
+ CC2NP
+ Capture/Compare 2 output
+ Polarity
+ 7
+ 1
+
+
+ CC2P
+ Capture/Compare 2 output
+ Polarity
+ 5
+ 1
+
+
+ CC2E
+ Capture/Compare 2 output
+ enable
+ 4
+ 1
+
+
+ CC1NP
+ Capture/Compare 1 output
+ Polarity
+ 3
+ 1
+
+
+ CC1NE
+ Capture/Compare 1 complementary output
+ enable
+ 2
+ 1
+
+
+ CC1P
+ Capture/Compare 1 output
+ Polarity
+ 1
+ 1
+
+
+ CC1E
+ Capture/Compare 1 output
+ enable
+ 0
+ 1
+
+
+
+
+ CNT
+ CNT
+ counter
+ 0x24
+ 0x20
+ 0x00000000
+
+
+ CNT
+ counter value
+ 0
+ 16
+ read-write
+
+
+ UIFCPY
+ UIF copy
+ 31
+ 1
+ read-only
+
+
+
+
+ PSC
+ PSC
+ prescaler
+ 0x28
+ 0x20
+ read-write
+ 0x0000
+
+
+ PSC
+ Prescaler value
+ 0
+ 16
+
+
+
+
+ ARR
+ ARR
+ auto-reload register
+ 0x2C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ ARR
+ Auto-reload value
+ 0
+ 16
+
+
+
+
+ RCR
+ RCR
+ repetition counter register
+ 0x30
+ 0x20
+ read-write
+ 0x0000
+
+
+ REP
+ Repetition counter value
+ 0
+ 8
+
+
+
+
+ CCR1
+ CCR1
+ capture/compare register 1
+ 0x34
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CCR1
+ Capture/Compare 1 value
+ 0
+ 16
+
+
+
+
+ CCR2
+ CCR2
+ capture/compare register 2
+ 0x38
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CCR2
+ Capture/Compare 2 value
+ 0
+ 16
+
+
+
+
+ BDTR
+ BDTR
+ break and dead-time register
+ 0x44
+ 0x20
+ read-write
+ 0x0000
+
+
+ MOE
+ Main output enable
+ 15
+ 1
+
+
+ AOE
+ Automatic output enable
+ 14
+ 1
+
+
+ BKP
+ Break polarity
+ 13
+ 1
+
+
+ BKE
+ Break enable
+ 12
+ 1
+
+
+ OSSR
+ Off-state selection for Run
+ mode
+ 11
+ 1
+
+
+ OSSI
+ Off-state selection for Idle
+ mode
+ 10
+ 1
+
+
+ LOCK
+ Lock configuration
+ 8
+ 2
+
+
+ DTG
+ Dead-time generator setup
+ 0
+ 8
+
+
+ BKF
+ Break filter
+ 16
+ 4
+
+
+
+
+ DCR
+ DCR
+ DMA control register
+ 0x48
+ 0x20
+ read-write
+ 0x0000
+
+
+ DBL
+ DMA burst length
+ 8
+ 5
+
+
+ DBA
+ DMA base address
+ 0
+ 5
+
+
+
+
+ DMAR
+ DMAR
+ DMA address for full transfer
+ 0x4C
+ 0x20
+ read-write
+ 0x0000
+
+
+ DMAB
+ DMA register for burst
+ accesses
+ 0
+ 16
+
+
+
+
+
+
+ TIM16
+ General-purpose-timers
+ TIMs
+ 0x40014400
+
+ 0x0
+ 0x400
+ registers
+
+
+
+ CR1
+ CR1
+ control register 1
+ 0x0
+ 0x20
+ read-write
+ 0x0000
+
+
+ CEN
+ Counter enable
+ 0
+ 1
+
+
+ UDIS
+ Update disable
+ 1
+ 1
+
+
+ URS
+ Update request source
+ 2
+ 1
+
+
+ OPM
+ One-pulse mode
+ 3
+ 1
+
+
+ ARPE
+ Auto-reload preload enable
+ 7
+ 1
+
+
+ CKD
+ Clock division
+ 8
+ 2
+
+
+ UIFREMAP
+ UIF status bit remapping
+ 11
+ 1
+
+
+
+
+ CR2
+ CR2
+ control register 2
+ 0x4
+ 0x20
+ read-write
+ 0x0000
+
+
+ OIS1N
+ Output Idle state 1
+ 9
+ 1
+
+
+ OIS1
+ Output Idle state 1
+ 8
+ 1
+
+
+ CCDS
+ Capture/compare DMA
+ selection
+ 3
+ 1
+
+
+ CCUS
+ Capture/compare control update
+ selection
+ 2
+ 1
+
+
+ CCPC
+ Capture/compare preloaded
+ control
+ 0
+ 1
+
+
+
+
+ DIER
+ DIER
+ DMA/Interrupt enable register
+ 0xC
+ 0x20
+ read-write
+ 0x0000
+
+
+ UIE
+ Update interrupt enable
+ 0
+ 1
+
+
+ CC1IE
+ Capture/Compare 1 interrupt
+ enable
+ 1
+ 1
+
+
+ COMIE
+ COM interrupt enable
+ 5
+ 1
+
+
+ TIE
+ Trigger interrupt enable
+ 6
+ 1
+
+
+ BIE
+ Break interrupt enable
+ 7
+ 1
+
+
+ UDE
+ Update DMA request enable
+ 8
+ 1
+
+
+ CC1DE
+ Capture/Compare 1 DMA request
+ enable
+ 9
+ 1
+
+
+ COMDE
+ COM DMA request enable
+ 13
+ 1
+
+
+ TDE
+ Trigger DMA request enable
+ 14
+ 1
+
+
+
+
+ SR
+ SR
+ status register
+ 0x10
+ 0x20
+ read-write
+ 0x0000
+
+
+ CC1OF
+ Capture/Compare 1 overcapture
+ flag
+ 9
+ 1
+
+
+ BIF
+ Break interrupt flag
+ 7
+ 1
+
+
+ TIF
+ Trigger interrupt flag
+ 6
+ 1
+
+
+ COMIF
+ COM interrupt flag
+ 5
+ 1
+
+
+ CC1IF
+ Capture/compare 1 interrupt
+ flag
+ 1
+ 1
+
+
+ UIF
+ Update interrupt flag
+ 0
+ 1
+
+
+
+
+ EGR
+ EGR
+ event generation register
+ 0x14
+ 0x20
+ write-only
+ 0x0000
+
+
+ BG
+ Break generation
+ 7
+ 1
+
+
+ TG
+ Trigger generation
+ 6
+ 1
+
+
+ COMG
+ Capture/Compare control update
+ generation
+ 5
+ 1
+
+
+ CC1G
+ Capture/compare 1
+ generation
+ 1
+ 1
+
+
+ UG
+ Update generation
+ 0
+ 1
+
+
+
+
+ CCMR1_Output
+ CCMR1_Output
+ capture/compare mode register (output
+ mode)
+ 0x18
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CC1S
+ Capture/Compare 1
+ selection
+ 0
+ 2
+
+
+ OC1FE
+ Output Compare 1 fast
+ enable
+ 2
+ 1
+
+
+ OC1PE
+ Output Compare 1 preload
+ enable
+ 3
+ 1
+
+
+ OC1M
+ Output Compare 1 mode
+ 4
+ 3
+
+
+ OC1M_3
+ Output Compare 1 mode
+ 16
+ 1
+
+
+
+
+ CCMR1_Input
+ CCMR1_Input
+ capture/compare mode register 1 (input
+ mode)
+ CCMR1_Output
+ 0x18
+ 0x20
+ read-write
+ 0x00000000
+
+
+ IC1F
+ Input capture 1 filter
+ 4
+ 4
+
+
+ IC1PSC
+ Input capture 1 prescaler
+ 2
+ 2
+
+
+ CC1S
+ Capture/Compare 1
+ selection
+ 0
+ 2
+
+
+
+
+ CCER
+ CCER
+ capture/compare enable
+ register
+ 0x20
+ 0x20
+ read-write
+ 0x0000
+
+
+ CC1NP
+ Capture/Compare 1 output
+ Polarity
+ 3
+ 1
+
+
+ CC1NE
+ Capture/Compare 1 complementary output
+ enable
+ 2
+ 1
+
+
+ CC1P
+ Capture/Compare 1 output
+ Polarity
+ 1
+ 1
+
+
+ CC1E
+ Capture/Compare 1 output
+ enable
+ 0
+ 1
+
+
+
+
+ CNT
+ CNT
+ counter
+ 0x24
+ 0x20
+ 0x00000000
+
+
+ CNT
+ counter value
+ 0
+ 16
+ read-write
+
+
+ UIFCPY
+ UIF Copy
+ 31
+ 1
+ read-only
+
+
+
+
+ PSC
+ PSC
+ prescaler
+ 0x28
+ 0x20
+ read-write
+ 0x0000
+
+
+ PSC
+ Prescaler value
+ 0
+ 16
+
+
+
+
+ ARR
+ ARR
+ auto-reload register
+ 0x2C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ ARR
+ Auto-reload value
+ 0
+ 16
+
+
+
+
+ RCR
+ RCR
+ repetition counter register
+ 0x30
+ 0x20
+ read-write
+ 0x0000
+
+
+ REP
+ Repetition counter value
+ 0
+ 8
+
+
+
+
+ CCR1
+ CCR1
+ capture/compare register 1
+ 0x34
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CCR1
+ Capture/Compare 1 value
+ 0
+ 16
+
+
+
+
+ BDTR
+ BDTR
+ break and dead-time register
+ 0x44
+ 0x20
+ read-write
+ 0x0000
+
+
+ DTG
+ Dead-time generator setup
+ 0
+ 8
+
+
+ LOCK
+ Lock configuration
+ 8
+ 2
+
+
+ OSSI
+ Off-state selection for Idle
+ mode
+ 10
+ 1
+
+
+ OSSR
+ Off-state selection for Run
+ mode
+ 11
+ 1
+
+
+ BKE
+ Break enable
+ 12
+ 1
+
+
+ BKP
+ Break polarity
+ 13
+ 1
+
+
+ AOE
+ Automatic output enable
+ 14
+ 1
+
+
+ MOE
+ Main output enable
+ 15
+ 1
+
+
+ BKF
+ Break filter
+ 16
+ 4
+
+
+
+
+ DCR
+ DCR
+ DMA control register
+ 0x48
+ 0x20
+ read-write
+ 0x0000
+
+
+ DBL
+ DMA burst length
+ 8
+ 5
+
+
+ DBA
+ DMA base address
+ 0
+ 5
+
+
+
+
+ DMAR
+ DMAR
+ DMA address for full transfer
+ 0x4C
+ 0x20
+ read-write
+ 0x0000
+
+
+ DMAB
+ DMA register for burst
+ accesses
+ 0
+ 16
+
+
+
+
+ OR
+ OR
+ option register
+ 0x50
+ 0x20
+ read-write
+ 0x0000
+
+
+
+
+ TIM17
+ General purpose timer
+ TIMs
+ 0x40014800
+
+ 0x0
+ 0x400
+ registers
+
+
+
+ CR1
+ CR1
+ control register 1
+ 0x0
+ 0x20
+ read-write
+ 0x0000
+
+
+ CEN
+ Counter enable
+ 0
+ 1
+
+
+ UDIS
+ Update disable
+ 1
+ 1
+
+
+ URS
+ Update request source
+ 2
+ 1
+
+
+ OPM
+ One-pulse mode
+ 3
+ 1
+
+
+ ARPE
+ Auto-reload preload enable
+ 7
+ 1
+
+
+ CKD
+ Clock division
+ 8
+ 2
+
+
+ UIFREMAP
+ UIF status bit remapping
+ 11
+ 1
+
+
+
+
+ CR2
+ CR2
+ control register 2
+ 0x4
+ 0x20
+ read-write
+ 0x0000
+
+
+ OIS1N
+ Output Idle state 1
+ 9
+ 1
+
+
+ OIS1
+ Output Idle state 1
+ 8
+ 1
+
+
+ CCDS
+ Capture/compare DMA
+ selection
+ 3
+ 1
+
+
+ CCUS
+ Capture/compare control update
+ selection
+ 2
+ 1
+
+
+ CCPC
+ Capture/compare preloaded
+ control
+ 0
+ 1
+
+
+
+
+ DIER
+ DIER
+ DMA/Interrupt enable register
+ 0xC
+ 0x20
+ read-write
+ 0x0000
+
+
+ UIE
+ Update interrupt enable
+ 0
+ 1
+
+
+ CC1IE
+ Capture/Compare 1 interrupt
+ enable
+ 1
+ 1
+
+
+ COMIE
+ COM interrupt enable
+ 5
+ 1
+
+
+ TIE
+ Trigger interrupt enable
+ 6
+ 1
+
+
+ BIE
+ Break interrupt enable
+ 7
+ 1
+
+
+ UDE
+ Update DMA request enable
+ 8
+ 1
+
+
+ CC1DE
+ Capture/Compare 1 DMA request
+ enable
+ 9
+ 1
+
+
+ COMDE
+ COM DMA request enable
+ 13
+ 1
+
+
+ TDE
+ Trigger DMA request enable
+ 14
+ 1
+
+
+
+
+ SR
+ SR
+ status register
+ 0x10
+ 0x20
+ read-write
+ 0x0000
+
+
+ CC1OF
+ Capture/Compare 1 overcapture
+ flag
+ 9
+ 1
+
+
+ BIF
+ Break interrupt flag
+ 7
+ 1
+
+
+ TIF
+ Trigger interrupt flag
+ 6
+ 1
+
+
+ COMIF
+ COM interrupt flag
+ 5
+ 1
+
+
+ CC1IF
+ Capture/compare 1 interrupt
+ flag
+ 1
+ 1
+
+
+ UIF
+ Update interrupt flag
+ 0
+ 1
+
+
+
+
+ EGR
+ EGR
+ event generation register
+ 0x14
+ 0x20
+ write-only
+ 0x0000
+
+
+ BG
+ Break generation
+ 7
+ 1
+
+
+ TG
+ Trigger generation
+ 6
+ 1
+
+
+ COMG
+ Capture/Compare control update
+ generation
+ 5
+ 1
+
+
+ CC1G
+ Capture/compare 1
+ generation
+ 1
+ 1
+
+
+ UG
+ Update generation
+ 0
+ 1
+
+
+
+
+ CCMR1_Output
+ CCMR1_Output
+ capture/compare mode register (output
+ mode)
+ 0x18
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CC1S
+ Capture/Compare 1
+ selection
+ 0
+ 2
+
+
+ OC1FE
+ Output Compare 1 fast
+ enable
+ 2
+ 1
+
+
+ OC1PE
+ Output Compare 1 preload
+ enable
+ 3
+ 1
+
+
+ OC1M
+ Output Compare 1 mode
+ 4
+ 3
+
+
+ OC1M_3
+ Output Compare 1 mode
+ 16
+ 1
+
+
+
+
+ CCMR1_Input
+ CCMR1_Input
+ capture/compare mode register 1 (input
+ mode)
+ CCMR1_Output
+ 0x18
+ 0x20
+ read-write
+ 0x00000000
+
+
+ IC1F
+ Input capture 1 filter
+ 4
+ 4
+
+
+ IC1PSC
+ Input capture 1 prescaler
+ 2
+ 2
+
+
+ CC1S
+ Capture/Compare 1
+ selection
+ 0
+ 2
+
+
+
+
+ CCER
+ CCER
+ capture/compare enable
+ register
+ 0x20
+ 0x20
+ read-write
+ 0x0000
+
+
+ CC1NP
+ Capture/Compare 1 output
+ Polarity
+ 3
+ 1
+
+
+ CC1NE
+ Capture/Compare 1 complementary output
+ enable
+ 2
+ 1
+
+
+ CC1P
+ Capture/Compare 1 output
+ Polarity
+ 1
+ 1
+
+
+ CC1E
+ Capture/Compare 1 output
+ enable
+ 0
+ 1
+
+
+
+
+ CNT
+ CNT
+ counter
+ 0x24
+ 0x20
+ 0x00000000
+
+
+ CNT
+ counter value
+ 0
+ 16
+ read-write
+
+
+ UIFCPY
+ UIF Copy
+ 31
+ 1
+ read-only
+
+
+
+
+ PSC
+ PSC
+ prescaler
+ 0x28
+ 0x20
+ read-write
+ 0x0000
+
+
+ PSC
+ Prescaler value
+ 0
+ 16
+
+
+
+
+ ARR
+ ARR
+ auto-reload register
+ 0x2C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ ARR
+ Auto-reload value
+ 0
+ 16
+
+
+
+
+ RCR
+ RCR
+ repetition counter register
+ 0x30
+ 0x20
+ read-write
+ 0x0000
+
+
+ REP
+ Repetition counter value
+ 0
+ 8
+
+
+
+
+ CCR1
+ CCR1
+ capture/compare register 1
+ 0x34
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CCR1
+ Capture/Compare 1 value
+ 0
+ 16
+
+
+
+
+ BDTR
+ BDTR
+ break and dead-time register
+ 0x44
+ 0x20
+ read-write
+ 0x0000
+
+
+ DTG
+ Dead-time generator setup
+ 0
+ 8
+
+
+ LOCK
+ Lock configuration
+ 8
+ 2
+
+
+ OSSI
+ Off-state selection for Idle
+ mode
+ 10
+ 1
+
+
+ OSSR
+ Off-state selection for Run
+ mode
+ 11
+ 1
+
+
+ BKE
+ Break enable
+ 12
+ 1
+
+
+ BKP
+ Break polarity
+ 13
+ 1
+
+
+ AOE
+ Automatic output enable
+ 14
+ 1
+
+
+ MOE
+ Main output enable
+ 15
+ 1
+
+
+ BKF
+ Break filter
+ 16
+ 4
+
+
+
+
+ DCR
+ DCR
+ DMA control register
+ 0x48
+ 0x20
+ read-write
+ 0x0000
+
+
+ DBL
+ DMA burst length
+ 8
+ 5
+
+
+ DBA
+ DMA base address
+ 0
+ 5
+
+
+
+
+ DMAR
+ DMAR
+ DMA address for full transfer
+ 0x4C
+ 0x20
+ read-write
+ 0x0000
+
+
+ DMAB
+ DMA register for burst
+ accesses
+ 0
+ 16
+
+
+
+
+
+
+ USART1
+ Universal synchronous asynchronous receiver
+ transmitter
+ USART
+ 0x40013800
+
+ 0x0
+ 0x400
+ registers
+
+
+ USART1_EXTI25
+ USART1 global interrupt and EXTI Line 25
+ interrupt
+ 37
+
+
+
+ CR1
+ CR1
+ Control register 1
+ 0x0
+ 0x20
+ read-write
+ 0x0000
+
+
+ EOBIE
+ End of Block interrupt
+ enable
+ 27
+ 1
+
+
+ RTOIE
+ Receiver timeout interrupt
+ enable
+ 26
+ 1
+
+
+ DEAT
+ Driver Enable assertion
+ time
+ 21
+ 5
+
+
+ DEDT
+ Driver Enable deassertion
+ time
+ 16
+ 5
+
+
+ OVER8
+ Oversampling mode
+ 15
+ 1
+
+
+ CMIE
+ Character match interrupt
+ enable
+ 14
+ 1
+
+
+ MME
+ Mute mode enable
+ 13
+ 1
+
+
+ M
+ Word length
+ 12
+ 1
+
+
+ WAKE
+ Receiver wakeup method
+ 11
+ 1
+
+
+ PCE
+ Parity control enable
+ 10
+ 1
+
+
+ PS
+ Parity selection
+ 9
+ 1
+
+
+ PEIE
+ PE interrupt enable
+ 8
+ 1
+
+
+ TXEIE
+ interrupt enable
+ 7
+ 1
+
+
+ TCIE
+ Transmission complete interrupt
+ enable
+ 6
+ 1
+
+
+ RXNEIE
+ RXNE interrupt enable
+ 5
+ 1
+
+
+ IDLEIE
+ IDLE interrupt enable
+ 4
+ 1
+
+
+ TE
+ Transmitter enable
+ 3
+ 1
+
+
+ RE
+ Receiver enable
+ 2
+ 1
+
+
+ UESM
+ USART enable in Stop mode
+ 1
+ 1
+
+
+ UE
+ USART enable
+ 0
+ 1
+
+
+
+
+ CR2
+ CR2
+ Control register 2
+ 0x4
+ 0x20
+ read-write
+ 0x0000
+
+
+ ADD4
+ Address of the USART node
+ 28
+ 4
+
+
+ ADD0
+ Address of the USART node
+ 24
+ 4
+
+
+ RTOEN
+ Receiver timeout enable
+ 23
+ 1
+
+
+ ABRMOD
+ Auto baud rate mode
+ 21
+ 2
+
+
+ ABREN
+ Auto baud rate enable
+ 20
+ 1
+
+
+ MSBFIRST
+ Most significant bit first
+ 19
+ 1
+
+
+ DATAINV
+ Binary data inversion
+ 18
+ 1
+
+
+ TXINV
+ TX pin active level
+ inversion
+ 17
+ 1
+
+
+ RXINV
+ RX pin active level
+ inversion
+ 16
+ 1
+
+
+ SWAP
+ Swap TX/RX pins
+ 15
+ 1
+
+
+ LINEN
+ LIN mode enable
+ 14
+ 1
+
+
+ STOP
+ STOP bits
+ 12
+ 2
+
+
+ CLKEN
+ Clock enable
+ 11
+ 1
+
+
+ CPOL
+ Clock polarity
+ 10
+ 1
+
+
+ CPHA
+ Clock phase
+ 9
+ 1
+
+
+ LBCL
+ Last bit clock pulse
+ 8
+ 1
+
+
+ LBDIE
+ LIN break detection interrupt
+ enable
+ 6
+ 1
+
+
+ LBDL
+ LIN break detection length
+ 5
+ 1
+
+
+ ADDM7
+ 7-bit Address Detection/4-bit Address
+ Detection
+ 4
+ 1
+
+
+
+
+ CR3
+ CR3
+ Control register 3
+ 0x8
+ 0x20
+ read-write
+ 0x0000
+
+
+ WUFIE
+ Wakeup from Stop mode interrupt
+ enable
+ 22
+ 1
+
+
+ WUS
+ Wakeup from Stop mode interrupt flag
+ selection
+ 20
+ 2
+
+
+ SCARCNT
+ Smartcard auto-retry count
+ 17
+ 3
+
+
+ DEP
+ Driver enable polarity
+ selection
+ 15
+ 1
+
+
+ DEM
+ Driver enable mode
+ 14
+ 1
+
+
+ DDRE
+ DMA Disable on Reception
+ Error
+ 13
+ 1
+
+
+ OVRDIS
+ Overrun Disable
+ 12
+ 1
+
+
+ ONEBIT
+ One sample bit method
+ enable
+ 11
+ 1
+
+
+ CTSIE
+ CTS interrupt enable
+ 10
+ 1
+
+
+ CTSE
+ CTS enable
+ 9
+ 1
+
+
+ RTSE
+ RTS enable
+ 8
+ 1
+
+
+ DMAT
+ DMA enable transmitter
+ 7
+ 1
+
+
+ DMAR
+ DMA enable receiver
+ 6
+ 1
+
+
+ SCEN
+ Smartcard mode enable
+ 5
+ 1
+
+
+ NACK
+ Smartcard NACK enable
+ 4
+ 1
+
+
+ HDSEL
+ Half-duplex selection
+ 3
+ 1
+
+
+ IRLP
+ IrDA low-power
+ 2
+ 1
+
+
+ IREN
+ IrDA mode enable
+ 1
+ 1
+
+
+ EIE
+ Error interrupt enable
+ 0
+ 1
+
+
+
+
+ BRR
+ BRR
+ Baud rate register
+ 0xC
+ 0x20
+ read-write
+ 0x0000
+
+
+ DIV_Mantissa
+ mantissa of USARTDIV
+ 4
+ 12
+
+
+ DIV_Fraction
+ fraction of USARTDIV
+ 0
+ 4
+
+
+
+
+ GTPR
+ GTPR
+ Guard time and prescaler
+ register
+ 0x10
+ 0x20
+ read-write
+ 0x0000
+
+
+ GT
+ Guard time value
+ 8
+ 8
+
+
+ PSC
+ Prescaler value
+ 0
+ 8
+
+
+
+
+ RTOR
+ RTOR
+ Receiver timeout register
+ 0x14
+ 0x20
+ read-write
+ 0x0000
+
+
+ BLEN
+ Block Length
+ 24
+ 8
+
+
+ RTO
+ Receiver timeout value
+ 0
+ 24
+
+
+
+
+ RQR
+ RQR
+ Request register
+ 0x18
+ 0x20
+ read-write
+ 0x0000
+
+
+ TXFRQ
+ Transmit data flush
+ request
+ 4
+ 1
+
+
+ RXFRQ
+ Receive data flush request
+ 3
+ 1
+
+
+ MMRQ
+ Mute mode request
+ 2
+ 1
+
+
+ SBKRQ
+ Send break request
+ 1
+ 1
+
+
+ ABRRQ
+ Auto baud rate request
+ 0
+ 1
+
+
+
+
+ ISR
+ ISR
+ Interrupt & status
+ register
+ 0x1C
+ 0x20
+ read-only
+ 0x00C0
+
+
+ REACK
+ Receive enable acknowledge
+ flag
+ 22
+ 1
+
+
+ TEACK
+ Transmit enable acknowledge
+ flag
+ 21
+ 1
+
+
+ WUF
+ Wakeup from Stop mode flag
+ 20
+ 1
+
+
+ RWU
+ Receiver wakeup from Mute
+ mode
+ 19
+ 1
+
+
+ SBKF
+ Send break flag
+ 18
+ 1
+
+
+ CMF
+ character match flag
+ 17
+ 1
+
+
+ BUSY
+ Busy flag
+ 16
+ 1
+
+
+ ABRF
+ Auto baud rate flag
+ 15
+ 1
+
+
+ ABRE
+ Auto baud rate error
+ 14
+ 1
+
+
+ EOBF
+ End of block flag
+ 12
+ 1
+
+
+ RTOF
+ Receiver timeout
+ 11
+ 1
+
+
+ CTS
+ CTS flag
+ 10
+ 1
+
+
+ CTSIF
+ CTS interrupt flag
+ 9
+ 1
+
+
+ LBDF
+ LIN break detection flag
+ 8
+ 1
+
+
+ TXE
+ Transmit data register
+ empty
+ 7
+ 1
+
+
+ TC
+ Transmission complete
+ 6
+ 1
+
+
+ RXNE
+ Read data register not
+ empty
+ 5
+ 1
+
+
+ IDLE
+ Idle line detected
+ 4
+ 1
+
+
+ ORE
+ Overrun error
+ 3
+ 1
+
+
+ NF
+ Noise detected flag
+ 2
+ 1
+
+
+ FE
+ Framing error
+ 1
+ 1
+
+
+ PE
+ Parity error
+ 0
+ 1
+
+
+
+
+ ICR
+ ICR
+ Interrupt flag clear register
+ 0x20
+ 0x20
+ read-write
+ 0x0000
+
+
+ WUCF
+ Wakeup from Stop mode clear
+ flag
+ 20
+ 1
+
+
+ CMCF
+ Character match clear flag
+ 17
+ 1
+
+
+ EOBCF
+ End of timeout clear flag
+ 12
+ 1
+
+
+ RTOCF
+ Receiver timeout clear
+ flag
+ 11
+ 1
+
+
+ CTSCF
+ CTS clear flag
+ 9
+ 1
+
+
+ LBDCF
+ LIN break detection clear
+ flag
+ 8
+ 1
+
+
+ TCCF
+ Transmission complete clear
+ flag
+ 6
+ 1
+
+
+ IDLECF
+ Idle line detected clear
+ flag
+ 4
+ 1
+
+
+ ORECF
+ Overrun error clear flag
+ 3
+ 1
+
+
+ NCF
+ Noise detected clear flag
+ 2
+ 1
+
+
+ FECF
+ Framing error clear flag
+ 1
+ 1
+
+
+ PECF
+ Parity error clear flag
+ 0
+ 1
+
+
+
+
+ RDR
+ RDR
+ Receive data register
+ 0x24
+ 0x20
+ read-only
+ 0x0000
+
+
+ RDR
+ Receive data value
+ 0
+ 9
+
+
+
+
+ TDR
+ TDR
+ Transmit data register
+ 0x28
+ 0x20
+ read-write
+ 0x0000
+
+
+ TDR
+ Transmit data value
+ 0
+ 9
+
+
+
+
+
+
+ USART2
+ 0x40004400
+
+ USART2_EXTI26
+ USART2 global interrupt and EXTI Line 26
+ interrupt
+ 38
+
+
+
+ USART3
+ 0x40004800
+
+ USART3_EXTI28
+ USART3 global interrupt and EXTI Line 28
+ interrupt
+ 39
+
+
+
+ UART4
+ 0x40004C00
+
+ UART4_EXTI34
+ UART4 global and EXTI Line 34
+ interrupts
+ 52
+
+
+
+ UART5
+ 0x40005000
+
+ UART5_EXTI35
+ UART5 global and EXTI Line 35
+ interrupts
+ 53
+
+
+
+ SPI1
+ Serial peripheral interface/Inter-IC
+ sound
+ SPI
+ 0x40013000
+
+ 0x0
+ 0x400
+ registers
+
+
+ SPI1
+ SPI1 global interrupt
+ 35
+
+
+
+ CR1
+ CR1
+ control register 1
+ 0x0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ BIDIMODE
+ Bidirectional data mode
+ enable
+ 15
+ 1
+
+
+ BIDIOE
+ Output enable in bidirectional
+ mode
+ 14
+ 1
+
+
+ CRCEN
+ Hardware CRC calculation
+ enable
+ 13
+ 1
+
+
+ CRCNEXT
+ CRC transfer next
+ 12
+ 1
+
+
+ CRCL
+ CRC length
+ 11
+ 1
+
+
+ RXONLY
+ Receive only
+ 10
+ 1
+
+
+ SSM
+ Software slave management
+ 9
+ 1
+
+
+ SSI
+ Internal slave select
+ 8
+ 1
+
+
+ LSBFIRST
+ Frame format
+ 7
+ 1
+
+
+ SPE
+ SPI enable
+ 6
+ 1
+
+
+ BR
+ Baud rate control
+ 3
+ 3
+
+
+ MSTR
+ Master selection
+ 2
+ 1
+
+
+ CPOL
+ Clock polarity
+ 1
+ 1
+
+
+ CPHA
+ Clock phase
+ 0
+ 1
+
+
+
+
+ CR2
+ CR2
+ control register 2
+ 0x4
+ 0x20
+ read-write
+ 0x00000700
+
+
+ RXDMAEN
+ Rx buffer DMA enable
+ 0
+ 1
+
+
+ TXDMAEN
+ Tx buffer DMA enable
+ 1
+ 1
+
+
+ SSOE
+ SS output enable
+ 2
+ 1
+
+
+ NSSP
+ NSS pulse management
+ 3
+ 1
+
+
+ FRF
+ Frame format
+ 4
+ 1
+
+
+ ERRIE
+ Error interrupt enable
+ 5
+ 1
+
+
+ RXNEIE
+ RX buffer not empty interrupt
+ enable
+ 6
+ 1
+
+
+ TXEIE
+ Tx buffer empty interrupt
+ enable
+ 7
+ 1
+
+
+ DS
+ Data size
+ 8
+ 4
+
+
+ FRXTH
+ FIFO reception threshold
+ 12
+ 1
+
+
+ LDMA_RX
+ Last DMA transfer for
+ reception
+ 13
+ 1
+
+
+ LDMA_TX
+ Last DMA transfer for
+ transmission
+ 14
+ 1
+
+
+
+
+ SR
+ SR
+ status register
+ 0x8
+ 0x20
+ 0x00000002
+
+
+ RXNE
+ Receive buffer not empty
+ 0
+ 1
+ read-only
+
+
+ TXE
+ Transmit buffer empty
+ 1
+ 1
+ read-only
+
+
+ CHSIDE
+ Channel side
+ 2
+ 1
+ read-only
+
+
+ UDR
+ Underrun flag
+ 3
+ 1
+ read-only
+
+
+ CRCERR
+ CRC error flag
+ 4
+ 1
+ read-write
+
+
+ MODF
+ Mode fault
+ 5
+ 1
+ read-only
+
+
+ OVR
+ Overrun flag
+ 6
+ 1
+ read-only
+
+
+ BSY
+ Busy flag
+ 7
+ 1
+ read-only
+
+
+ TIFRFE
+ TI frame format error
+ 8
+ 1
+ read-only
+
+
+ FRLVL
+ FIFO reception level
+ 9
+ 2
+ read-only
+
+
+ FTLVL
+ FIFO transmission level
+ 11
+ 2
+ read-only
+
+
+
+
+ DR
+ DR
+ data register
+ 0xC
+ 0x20
+ read-write
+ 0x00000000
+
+
+ DR
+ Data register
+ 0
+ 16
+
+
+
+
+ CRCPR
+ CRCPR
+ CRC polynomial register
+ 0x10
+ 0x20
+ read-write
+ 0x00000007
+
+
+ CRCPOLY
+ CRC polynomial register
+ 0
+ 16
+
+
+
+
+ RXCRCR
+ RXCRCR
+ RX CRC register
+ 0x14
+ 0x20
+ read-only
+ 0x00000000
+
+
+ RxCRC
+ Rx CRC register
+ 0
+ 16
+
+
+
+
+ TXCRCR
+ TXCRCR
+ TX CRC register
+ 0x18
+ 0x20
+ read-only
+ 0x00000000
+
+
+ TxCRC
+ Tx CRC register
+ 0
+ 16
+
+
+
+
+ I2SCFGR
+ I2SCFGR
+ I2S configuration register
+ 0x1C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ I2SMOD
+ I2S mode selection
+ 11
+ 1
+
+
+ I2SE
+ I2S Enable
+ 10
+ 1
+
+
+ I2SCFG
+ I2S configuration mode
+ 8
+ 2
+
+
+ PCMSYNC
+ PCM frame synchronization
+ 7
+ 1
+
+
+ I2SSTD
+ I2S standard selection
+ 4
+ 2
+
+
+ CKPOL
+ Steady state clock
+ polarity
+ 3
+ 1
+
+
+ DATLEN
+ Data length to be
+ transferred
+ 1
+ 2
+
+
+ CHLEN
+ Channel length (number of bits per audio
+ channel)
+ 0
+ 1
+
+
+
+
+ I2SPR
+ I2SPR
+ I2S prescaler register
+ 0x20
+ 0x20
+ read-write
+ 0x00000010
+
+
+ MCKOE
+ Master clock output enable
+ 9
+ 1
+
+
+ ODD
+ Odd factor for the
+ prescaler
+ 8
+ 1
+
+
+ I2SDIV
+ I2S Linear prescaler
+ 0
+ 8
+
+
+
+
+
+
+ SPI2
+ 0x40003800
+
+ SPI2
+ SPI2 global interrupt
+ 36
+
+
+
+ SPI3
+ 0x40003C00
+
+ SPI3
+ SPI3 global interrupt
+ 51
+
+
+
+ SPI4
+ 0x40013C00
+
+ SPI4
+ SPI4 Global interrupt
+ 84
+
+
+
+ I2S2ext
+ Serial peripheral interface/Inter-IC
+ sound
+ SPI
+ 0x40003400
+
+ 0x0
+ 0x400
+ registers
+
+
+
+ CR1
+ CR1
+ control register 1
+ 0x0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ BIDIMODE
+ Bidirectional data mode
+ enable
+ 15
+ 1
+
+
+ BIDIOE
+ Output enable in bidirectional
+ mode
+ 14
+ 1
+
+
+ CRCEN
+ Hardware CRC calculation
+ enable
+ 13
+ 1
+
+
+ CRCNEXT
+ CRC transfer next
+ 12
+ 1
+
+
+ CRCL
+ CRC length
+ 11
+ 1
+
+
+ RXONLY
+ Receive only
+ 10
+ 1
+
+
+ SSM
+ Software slave management
+ 9
+ 1
+
+
+ SSI
+ Internal slave select
+ 8
+ 1
+
+
+ LSBFIRST
+ Frame format
+ 7
+ 1
+
+
+ SPE
+ SPI enable
+ 6
+ 1
+
+
+ BR
+ Baud rate control
+ 3
+ 3
+
+
+ MSTR
+ Master selection
+ 2
+ 1
+
+
+ CPOL
+ Clock polarity
+ 1
+ 1
+
+
+ CPHA
+ Clock phase
+ 0
+ 1
+
+
+
+
+ CR2
+ CR2
+ control register 2
+ 0x4
+ 0x20
+ read-write
+ 0x00000700
+
+
+ RXDMAEN
+ Rx buffer DMA enable
+ 0
+ 1
+
+
+ TXDMAEN
+ Tx buffer DMA enable
+ 1
+ 1
+
+
+ SSOE
+ SS output enable
+ 2
+ 1
+
+
+ NSSP
+ NSS pulse management
+ 3
+ 1
+
+
+ FRF
+ Frame format
+ 4
+ 1
+
+
+ ERRIE
+ Error interrupt enable
+ 5
+ 1
+
+
+ RXNEIE
+ RX buffer not empty interrupt
+ enable
+ 6
+ 1
+
+
+ TXEIE
+ Tx buffer empty interrupt
+ enable
+ 7
+ 1
+
+
+ DS
+ Data size
+ 8
+ 4
+
+
+ FRXTH
+ FIFO reception threshold
+ 12
+ 1
+
+
+ LDMA_RX
+ Last DMA transfer for
+ reception
+ 13
+ 1
+
+
+ LDMA_TX
+ Last DMA transfer for
+ transmission
+ 14
+ 1
+
+
+
+
+ SR
+ SR
+ status register
+ 0x8
+ 0x20
+ 0x00000002
+
+
+ RXNE
+ Receive buffer not empty
+ 0
+ 1
+ read-only
+
+
+ TXE
+ Transmit buffer empty
+ 1
+ 1
+ read-only
+
+
+ CHSIDE
+ Channel side
+ 2
+ 1
+ read-only
+
+
+ UDR
+ Underrun flag
+ 3
+ 1
+ read-only
+
+
+ CRCERR
+ CRC error flag
+ 4
+ 1
+ read-write
+
+
+ MODF
+ Mode fault
+ 5
+ 1
+ read-only
+
+
+ OVR
+ Overrun flag
+ 6
+ 1
+ read-only
+
+
+ BSY
+ Busy flag
+ 7
+ 1
+ read-only
+
+
+ TIFRFE
+ TI frame format error
+ 8
+ 1
+ read-only
+
+
+ FRLVL
+ FIFO reception level
+ 9
+ 2
+ read-only
+
+
+ FTLVL
+ FIFO transmission level
+ 11
+ 2
+ read-only
+
+
+
+
+ DR
+ DR
+ data register
+ 0xC
+ 0x20
+ read-write
+ 0x00000000
+
+
+ DR
+ Data register
+ 0
+ 16
+
+
+
+
+ CRCPR
+ CRCPR
+ CRC polynomial register
+ 0x10
+ 0x20
+ read-write
+ 0x00000007
+
+
+ CRCPOLY
+ CRC polynomial register
+ 0
+ 16
+
+
+
+
+ RXCRCR
+ RXCRCR
+ RX CRC register
+ 0x14
+ 0x20
+ read-only
+ 0x00000000
+
+
+ RxCRC
+ Rx CRC register
+ 0
+ 16
+
+
+
+
+ TXCRCR
+ TXCRCR
+ TX CRC register
+ 0x18
+ 0x20
+ read-only
+ 0x00000000
+
+
+ TxCRC
+ Tx CRC register
+ 0
+ 16
+
+
+
+
+ I2SCFGR
+ I2SCFGR
+ I2S configuration register
+ 0x1C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ I2SMOD
+ I2S mode selection
+ 11
+ 1
+
+
+ I2SE
+ I2S Enable
+ 10
+ 1
+
+
+ I2SCFG
+ I2S configuration mode
+ 8
+ 2
+
+
+ PCMSYNC
+ PCM frame synchronization
+ 7
+ 1
+
+
+ I2SSTD
+ I2S standard selection
+ 4
+ 2
+
+
+ CKPOL
+ Steady state clock
+ polarity
+ 3
+ 1
+
+
+ DATLEN
+ Data length to be
+ transferred
+ 1
+ 2
+
+
+ CHLEN
+ Channel length (number of bits per audio
+ channel)
+ 0
+ 1
+
+
+
+
+ I2SPR
+ I2SPR
+ I2S prescaler register
+ 0x20
+ 0x20
+ read-write
+ 0x00000002
+
+
+ MCKOE
+ Master clock output enable
+ 9
+ 1
+
+
+ ODD
+ Odd factor for the
+ prescaler
+ 8
+ 1
+
+
+ I2SDIV
+ I2S Linear prescaler
+ 0
+ 8
+
+
+
+
+
+
+ I2S3ext
+ 0x40004000
+
+
+ EXTI
+ External interrupt/event
+ controller
+ EXTI
+ 0x40010400
+
+ 0x0
+ 0x400
+ registers
+
+
+ TAMP_STAMP
+ Tamper and TimeStamp interrupts
+ 2
+
+
+ EXTI0
+ EXTI Line0 interrupt
+ 6
+
+
+ EXTI1
+ EXTI Line3 interrupt
+ 7
+
+
+ EXTI2_TSC
+ EXTI Line2 and Touch sensing
+ interrupts
+ 8
+
+
+ EXTI3
+ EXTI Line3 interrupt
+ 9
+
+
+ EXTI4
+ EXTI Line4 interrupt
+ 10
+
+
+ EXTI9_5
+ EXTI Line5 to Line9 interrupts
+ 23
+
+
+ EXTI15_10
+ EXTI Line15 to Line10 interrupts
+ 40
+
+
+ USB_WKUP_EXTI
+ USB wakeup from Suspend and EXTI Line
+ 18
+ 76
+
+
+
+ IMR1
+ IMR1
+ Interrupt mask register
+ 0x0
+ 0x20
+ read-write
+ 0x1F800000
+
+
+ MR0
+ Interrupt Mask on line 0
+ 0
+ 1
+
+
+ MR1
+ Interrupt Mask on line 1
+ 1
+ 1
+
+
+ MR2
+ Interrupt Mask on line 2
+ 2
+ 1
+
+
+ MR3
+ Interrupt Mask on line 3
+ 3
+ 1
+
+
+ MR4
+ Interrupt Mask on line 4
+ 4
+ 1
+
+
+ MR5
+ Interrupt Mask on line 5
+ 5
+ 1
+
+
+ MR6
+ Interrupt Mask on line 6
+ 6
+ 1
+
+
+ MR7
+ Interrupt Mask on line 7
+ 7
+ 1
+
+
+ MR8
+ Interrupt Mask on line 8
+ 8
+ 1
+
+
+ MR9
+ Interrupt Mask on line 9
+ 9
+ 1
+
+
+ MR10
+ Interrupt Mask on line 10
+ 10
+ 1
+
+
+ MR11
+ Interrupt Mask on line 11
+ 11
+ 1
+
+
+ MR12
+ Interrupt Mask on line 12
+ 12
+ 1
+
+
+ MR13
+ Interrupt Mask on line 13
+ 13
+ 1
+
+
+ MR14
+ Interrupt Mask on line 14
+ 14
+ 1
+
+
+ MR15
+ Interrupt Mask on line 15
+ 15
+ 1
+
+
+ MR16
+ Interrupt Mask on line 16
+ 16
+ 1
+
+
+ MR17
+ Interrupt Mask on line 17
+ 17
+ 1
+
+
+ MR18
+ Interrupt Mask on line 18
+ 18
+ 1
+
+
+ MR19
+ Interrupt Mask on line 19
+ 19
+ 1
+
+
+ MR20
+ Interrupt Mask on line 20
+ 20
+ 1
+
+
+ MR21
+ Interrupt Mask on line 21
+ 21
+ 1
+
+
+ MR22
+ Interrupt Mask on line 22
+ 22
+ 1
+
+
+ MR23
+ Interrupt Mask on line 23
+ 23
+ 1
+
+
+ MR24
+ Interrupt Mask on line 24
+ 24
+ 1
+
+
+ MR25
+ Interrupt Mask on line 25
+ 25
+ 1
+
+
+ MR26
+ Interrupt Mask on line 26
+ 26
+ 1
+
+
+ MR27
+ Interrupt Mask on line 27
+ 27
+ 1
+
+
+ MR28
+ Interrupt Mask on line 28
+ 28
+ 1
+
+
+ MR29
+ Interrupt Mask on line 29
+ 29
+ 1
+
+
+ MR30
+ Interrupt Mask on line 30
+ 30
+ 1
+
+
+ MR31
+ Interrupt Mask on line 31
+ 31
+ 1
+
+
+
+
+ EMR1
+ EMR1
+ Event mask register
+ 0x4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MR0
+ Event Mask on line 0
+ 0
+ 1
+
+
+ MR1
+ Event Mask on line 1
+ 1
+ 1
+
+
+ MR2
+ Event Mask on line 2
+ 2
+ 1
+
+
+ MR3
+ Event Mask on line 3
+ 3
+ 1
+
+
+ MR4
+ Event Mask on line 4
+ 4
+ 1
+
+
+ MR5
+ Event Mask on line 5
+ 5
+ 1
+
+
+ MR6
+ Event Mask on line 6
+ 6
+ 1
+
+
+ MR7
+ Event Mask on line 7
+ 7
+ 1
+
+
+ MR8
+ Event Mask on line 8
+ 8
+ 1
+
+
+ MR9
+ Event Mask on line 9
+ 9
+ 1
+
+
+ MR10
+ Event Mask on line 10
+ 10
+ 1
+
+
+ MR11
+ Event Mask on line 11
+ 11
+ 1
+
+
+ MR12
+ Event Mask on line 12
+ 12
+ 1
+
+
+ MR13
+ Event Mask on line 13
+ 13
+ 1
+
+
+ MR14
+ Event Mask on line 14
+ 14
+ 1
+
+
+ MR15
+ Event Mask on line 15
+ 15
+ 1
+
+
+ MR16
+ Event Mask on line 16
+ 16
+ 1
+
+
+ MR17
+ Event Mask on line 17
+ 17
+ 1
+
+
+ MR18
+ Event Mask on line 18
+ 18
+ 1
+
+
+ MR19
+ Event Mask on line 19
+ 19
+ 1
+
+
+ MR20
+ Event Mask on line 20
+ 20
+ 1
+
+
+ MR21
+ Event Mask on line 21
+ 21
+ 1
+
+
+ MR22
+ Event Mask on line 22
+ 22
+ 1
+
+
+ MR23
+ Event Mask on line 23
+ 23
+ 1
+
+
+ MR24
+ Event Mask on line 24
+ 24
+ 1
+
+
+ MR25
+ Event Mask on line 25
+ 25
+ 1
+
+
+ MR26
+ Event Mask on line 26
+ 26
+ 1
+
+
+ MR27
+ Event Mask on line 27
+ 27
+ 1
+
+
+ MR28
+ Event Mask on line 28
+ 28
+ 1
+
+
+ MR29
+ Event Mask on line 29
+ 29
+ 1
+
+
+ MR30
+ Event Mask on line 30
+ 30
+ 1
+
+
+ MR31
+ Event Mask on line 31
+ 31
+ 1
+
+
+
+
+ RTSR1
+ RTSR1
+ Rising Trigger selection
+ register
+ 0x8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ TR0
+ Rising trigger event configuration of
+ line 0
+ 0
+ 1
+
+
+ TR1
+ Rising trigger event configuration of
+ line 1
+ 1
+ 1
+
+
+ TR2
+ Rising trigger event configuration of
+ line 2
+ 2
+ 1
+
+
+ TR3
+ Rising trigger event configuration of
+ line 3
+ 3
+ 1
+
+
+ TR4
+ Rising trigger event configuration of
+ line 4
+ 4
+ 1
+
+
+ TR5
+ Rising trigger event configuration of
+ line 5
+ 5
+ 1
+
+
+ TR6
+ Rising trigger event configuration of
+ line 6
+ 6
+ 1
+
+
+ TR7
+ Rising trigger event configuration of
+ line 7
+ 7
+ 1
+
+
+ TR8
+ Rising trigger event configuration of
+ line 8
+ 8
+ 1
+
+
+ TR9
+ Rising trigger event configuration of
+ line 9
+ 9
+ 1
+
+
+ TR10
+ Rising trigger event configuration of
+ line 10
+ 10
+ 1
+
+
+ TR11
+ Rising trigger event configuration of
+ line 11
+ 11
+ 1
+
+
+ TR12
+ Rising trigger event configuration of
+ line 12
+ 12
+ 1
+
+
+ TR13
+ Rising trigger event configuration of
+ line 13
+ 13
+ 1
+
+
+ TR14
+ Rising trigger event configuration of
+ line 14
+ 14
+ 1
+
+
+ TR15
+ Rising trigger event configuration of
+ line 15
+ 15
+ 1
+
+
+ TR16
+ Rising trigger event configuration of
+ line 16
+ 16
+ 1
+
+
+ TR17
+ Rising trigger event configuration of
+ line 17
+ 17
+ 1
+
+
+ TR18
+ Rising trigger event configuration of
+ line 18
+ 18
+ 1
+
+
+ TR19
+ Rising trigger event configuration of
+ line 19
+ 19
+ 1
+
+
+ TR20
+ Rising trigger event configuration of
+ line 20
+ 20
+ 1
+
+
+ TR21
+ Rising trigger event configuration of
+ line 21
+ 21
+ 1
+
+
+ TR22
+ Rising trigger event configuration of
+ line 22
+ 22
+ 1
+
+
+ TR29
+ Rising trigger event configuration of
+ line 29
+ 29
+ 1
+
+
+ TR30
+ Rising trigger event configuration of
+ line 30
+ 30
+ 1
+
+
+ TR31
+ Rising trigger event configuration of
+ line 31
+ 31
+ 1
+
+
+
+
+ FTSR1
+ FTSR1
+ Falling Trigger selection
+ register
+ 0xC
+ 0x20
+ read-write
+ 0x00000000
+
+
+ TR0
+ Falling trigger event configuration of
+ line 0
+ 0
+ 1
+
+
+ TR1
+ Falling trigger event configuration of
+ line 1
+ 1
+ 1
+
+
+ TR2
+ Falling trigger event configuration of
+ line 2
+ 2
+ 1
+
+
+ TR3
+ Falling trigger event configuration of
+ line 3
+ 3
+ 1
+
+
+ TR4
+ Falling trigger event configuration of
+ line 4
+ 4
+ 1
+
+
+ TR5
+ Falling trigger event configuration of
+ line 5
+ 5
+ 1
+
+
+ TR6
+ Falling trigger event configuration of
+ line 6
+ 6
+ 1
+
+
+ TR7
+ Falling trigger event configuration of
+ line 7
+ 7
+ 1
+
+
+ TR8
+ Falling trigger event configuration of
+ line 8
+ 8
+ 1
+
+
+ TR9
+ Falling trigger event configuration of
+ line 9
+ 9
+ 1
+
+
+ TR10
+ Falling trigger event configuration of
+ line 10
+ 10
+ 1
+
+
+ TR11
+ Falling trigger event configuration of
+ line 11
+ 11
+ 1
+
+
+ TR12
+ Falling trigger event configuration of
+ line 12
+ 12
+ 1
+
+
+ TR13
+ Falling trigger event configuration of
+ line 13
+ 13
+ 1
+
+
+ TR14
+ Falling trigger event configuration of
+ line 14
+ 14
+ 1
+
+
+ TR15
+ Falling trigger event configuration of
+ line 15
+ 15
+ 1
+
+
+ TR16
+ Falling trigger event configuration of
+ line 16
+ 16
+ 1
+
+
+ TR17
+ Falling trigger event configuration of
+ line 17
+ 17
+ 1
+
+
+ TR18
+ Falling trigger event configuration of
+ line 18
+ 18
+ 1
+
+
+ TR19
+ Falling trigger event configuration of
+ line 19
+ 19
+ 1
+
+
+ TR20
+ Falling trigger event configuration of
+ line 20
+ 20
+ 1
+
+
+ TR21
+ Falling trigger event configuration of
+ line 21
+ 21
+ 1
+
+
+ TR22
+ Falling trigger event configuration of
+ line 22
+ 22
+ 1
+
+
+ TR29
+ Falling trigger event configuration of
+ line 29
+ 29
+ 1
+
+
+ TR30
+ Falling trigger event configuration of
+ line 30.
+ 30
+ 1
+
+
+ TR31
+ Falling trigger event configuration of
+ line 31
+ 31
+ 1
+
+
+
+
+ SWIER1
+ SWIER1
+ Software interrupt event
+ register
+ 0x10
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SWIER0
+ Software Interrupt on line
+ 0
+ 0
+ 1
+
+
+ SWIER1
+ Software Interrupt on line
+ 1
+ 1
+ 1
+
+
+ SWIER2
+ Software Interrupt on line
+ 2
+ 2
+ 1
+
+
+ SWIER3
+ Software Interrupt on line
+ 3
+ 3
+ 1
+
+
+ SWIER4
+ Software Interrupt on line
+ 4
+ 4
+ 1
+
+
+ SWIER5
+ Software Interrupt on line
+ 5
+ 5
+ 1
+
+
+ SWIER6
+ Software Interrupt on line
+ 6
+ 6
+ 1
+
+
+ SWIER7
+ Software Interrupt on line
+ 7
+ 7
+ 1
+
+
+ SWIER8
+ Software Interrupt on line
+ 8
+ 8
+ 1
+
+
+ SWIER9
+ Software Interrupt on line
+ 9
+ 9
+ 1
+
+
+ SWIER10
+ Software Interrupt on line
+ 10
+ 10
+ 1
+
+
+ SWIER11
+ Software Interrupt on line
+ 11
+ 11
+ 1
+
+
+ SWIER12
+ Software Interrupt on line
+ 12
+ 12
+ 1
+
+
+ SWIER13
+ Software Interrupt on line
+ 13
+ 13
+ 1
+
+
+ SWIER14
+ Software Interrupt on line
+ 14
+ 14
+ 1
+
+
+ SWIER15
+ Software Interrupt on line
+ 15
+ 15
+ 1
+
+
+ SWIER16
+ Software Interrupt on line
+ 16
+ 16
+ 1
+
+
+ SWIER17
+ Software Interrupt on line
+ 17
+ 17
+ 1
+
+
+ SWIER18
+ Software Interrupt on line
+ 18
+ 18
+ 1
+
+
+ SWIER19
+ Software Interrupt on line
+ 19
+ 19
+ 1
+
+
+ SWIER20
+ Software Interrupt on line
+ 20
+ 20
+ 1
+
+
+ SWIER21
+ Software Interrupt on line
+ 21
+ 21
+ 1
+
+
+ SWIER22
+ Software Interrupt on line
+ 22
+ 22
+ 1
+
+
+ SWIER29
+ Software Interrupt on line
+ 29
+ 29
+ 1
+
+
+ SWIER30
+ Software Interrupt on line
+ 309
+ 30
+ 1
+
+
+ SWIER31
+ Software Interrupt on line
+ 319
+ 31
+ 1
+
+
+
+
+ PR1
+ PR1
+ Pending register
+ 0x14
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PR0
+ Pending bit 0
+ 0
+ 1
+
+
+ PR1
+ Pending bit 1
+ 1
+ 1
+
+
+ PR2
+ Pending bit 2
+ 2
+ 1
+
+
+ PR3
+ Pending bit 3
+ 3
+ 1
+
+
+ PR4
+ Pending bit 4
+ 4
+ 1
+
+
+ PR5
+ Pending bit 5
+ 5
+ 1
+
+
+ PR6
+ Pending bit 6
+ 6
+ 1
+
+
+ PR7
+ Pending bit 7
+ 7
+ 1
+
+
+ PR8
+ Pending bit 8
+ 8
+ 1
+
+
+ PR9
+ Pending bit 9
+ 9
+ 1
+
+
+ PR10
+ Pending bit 10
+ 10
+ 1
+
+
+ PR11
+ Pending bit 11
+ 11
+ 1
+
+
+ PR12
+ Pending bit 12
+ 12
+ 1
+
+
+ PR13
+ Pending bit 13
+ 13
+ 1
+
+
+ PR14
+ Pending bit 14
+ 14
+ 1
+
+
+ PR15
+ Pending bit 15
+ 15
+ 1
+
+
+ PR16
+ Pending bit 16
+ 16
+ 1
+
+
+ PR17
+ Pending bit 17
+ 17
+ 1
+
+
+ PR18
+ Pending bit 18
+ 18
+ 1
+
+
+ PR19
+ Pending bit 19
+ 19
+ 1
+
+
+ PR20
+ Pending bit 20
+ 20
+ 1
+
+
+ PR21
+ Pending bit 21
+ 21
+ 1
+
+
+ PR22
+ Pending bit 22
+ 22
+ 1
+
+
+ PR29
+ Pending bit 29
+ 29
+ 1
+
+
+ PR30
+ Pending bit 30
+ 30
+ 1
+
+
+ PR31
+ Pending bit 31
+ 31
+ 1
+
+
+
+
+ IMR2
+ IMR2
+ Interrupt mask register
+ 0x18
+ 0x20
+ read-write
+ 0xFFFFFFFC
+
+
+ MR32
+ Interrupt Mask on external/internal line
+ 32
+ 0
+ 1
+
+
+ MR33
+ Interrupt Mask on external/internal line
+ 33
+ 1
+ 1
+
+
+ MR34
+ Interrupt Mask on external/internal line
+ 34
+ 2
+ 1
+
+
+ MR35
+ Interrupt Mask on external/internal line
+ 35
+ 3
+ 1
+
+
+
+
+ EMR2
+ EMR2
+ Event mask register
+ 0x1C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MR32
+ Event mask on external/internal line
+ 32
+ 0
+ 1
+
+
+ MR33
+ Event mask on external/internal line
+ 33
+ 1
+ 1
+
+
+ MR34
+ Event mask on external/internal line
+ 34
+ 2
+ 1
+
+
+ MR35
+ Event mask on external/internal line
+ 35
+ 3
+ 1
+
+
+
+
+ RTSR2
+ RTSR2
+ Rising Trigger selection
+ register
+ 0x20
+ 0x20
+ read-write
+ 0x00000000
+
+
+ TR32
+ Rising trigger event configuration bit
+ of line 32
+ 0
+ 1
+
+
+ TR33
+ Rising trigger event configuration bit
+ of line 33
+ 1
+ 1
+
+
+
+
+ FTSR2
+ FTSR2
+ Falling Trigger selection
+ register
+ 0x24
+ 0x20
+ read-write
+ 0x00000000
+
+
+ TR32
+ Falling trigger event configuration bit
+ of line 32
+ 0
+ 1
+
+
+ TR33
+ Falling trigger event configuration bit
+ of line 33
+ 1
+ 1
+
+
+
+
+ SWIER2
+ SWIER2
+ Software interrupt event
+ register
+ 0x28
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SWIER32
+ Software interrupt on line
+ 32
+ 0
+ 1
+
+
+ SWIER33
+ Software interrupt on line
+ 33
+ 1
+ 1
+
+
+
+
+ PR2
+ PR2
+ Pending register
+ 0x2C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PR32
+ Pending bit on line 32
+ 0
+ 1
+
+
+ PR33
+ Pending bit on line 33
+ 1
+ 1
+
+
+
+
+
+
+ PWR
+ Power control
+ PWR
+ 0x40007000
+
+ 0x0
+ 0x400
+ registers
+
+
+ PVD
+ PVD through EXTI line detection
+ interrupt
+ 1
+
+
+
+ CR
+ CR
+ power control register
+ 0x0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ LPDS
+ Low-power deep sleep
+ 0
+ 1
+
+
+ PDDS
+ Power down deepsleep
+ 1
+ 1
+
+
+ CWUF
+ Clear wakeup flag
+ 2
+ 1
+
+
+ CSBF
+ Clear standby flag
+ 3
+ 1
+
+
+ PVDE
+ Power voltage detector
+ enable
+ 4
+ 1
+
+
+ PLS
+ PVD level selection
+ 5
+ 3
+
+
+ DBP
+ Disable backup domain write
+ protection
+ 8
+ 1
+
+
+
+
+ CSR
+ CSR
+ power control/status register
+ 0x4
+ 0x20
+ 0x00000000
+
+
+ WUF
+ Wakeup flag
+ 0
+ 1
+ read-only
+
+
+ SBF
+ Standby flag
+ 1
+ 1
+ read-only
+
+
+ PVDO
+ PVD output
+ 2
+ 1
+ read-only
+
+
+ EWUP1
+ Enable WKUP1 pin
+ 8
+ 1
+ read-write
+
+
+ EWUP2
+ Enable WKUP2 pin
+ 9
+ 1
+ read-write
+
+
+
+
+
+
+ CAN
+ Controller area network
+ CAN
+ 0x40006400
+
+ 0x0
+ 0x400
+ registers
+
+
+ USB_HP_CAN_TX
+ USB High Priority/CAN_TX
+ interrupts
+ 19
+
+
+ USB_LP_CAN_RX0
+ USB Low Priority/CAN_RX0
+ interrupts
+ 20
+
+
+ CAN_RX1
+ CAN_RX1 interrupt
+ 21
+
+
+ CAN_SCE
+ CAN_SCE interrupt
+ 22
+
+
+
+ MCR
+ MCR
+ master control register
+ 0x0
+ 0x20
+ read-write
+ 0x00010002
+
+
+ DBF
+ DBF
+ 16
+ 1
+
+
+ RESET
+ RESET
+ 15
+ 1
+
+
+ TTCM
+ TTCM
+ 7
+ 1
+
+
+ ABOM
+ ABOM
+ 6
+ 1
+
+
+ AWUM
+ AWUM
+ 5
+ 1
+
+
+ NART
+ NART
+ 4
+ 1
+
+
+ RFLM
+ RFLM
+ 3
+ 1
+
+
+ TXFP
+ TXFP
+ 2
+ 1
+
+
+ SLEEP
+ SLEEP
+ 1
+ 1
+
+
+ INRQ
+ INRQ
+ 0
+ 1
+
+
+
+
+ MSR
+ MSR
+ master status register
+ 0x4
+ 0x20
+ 0x00000C02
+
+
+ RX
+ RX
+ 11
+ 1
+ read-only
+
+
+ SAMP
+ SAMP
+ 10
+ 1
+ read-only
+
+
+ RXM
+ RXM
+ 9
+ 1
+ read-only
+
+
+ TXM
+ TXM
+ 8
+ 1
+ read-only
+
+
+ SLAKI
+ SLAKI
+ 4
+ 1
+ read-write
+
+
+ WKUI
+ WKUI
+ 3
+ 1
+ read-write
+
+
+ ERRI
+ ERRI
+ 2
+ 1
+ read-write
+
+
+ SLAK
+ SLAK
+ 1
+ 1
+ read-only
+
+
+ INAK
+ INAK
+ 0
+ 1
+ read-only
+
+
+
+
+ TSR
+ TSR
+ transmit status register
+ 0x8
+ 0x20
+ 0x1C000000
+
+
+ LOW2
+ Lowest priority flag for mailbox
+ 2
+ 31
+ 1
+ read-only
+
+
+ LOW1
+ Lowest priority flag for mailbox
+ 1
+ 30
+ 1
+ read-only
+
+
+ LOW0
+ Lowest priority flag for mailbox
+ 0
+ 29
+ 1
+ read-only
+
+
+ TME2
+ Lowest priority flag for mailbox
+ 2
+ 28
+ 1
+ read-only
+
+
+ TME1
+ Lowest priority flag for mailbox
+ 1
+ 27
+ 1
+ read-only
+
+
+ TME0
+ Lowest priority flag for mailbox
+ 0
+ 26
+ 1
+ read-only
+
+
+ CODE
+ CODE
+ 24
+ 2
+ read-only
+
+
+ ABRQ2
+ ABRQ2
+ 23
+ 1
+ read-write
+
+
+ TERR2
+ TERR2
+ 19
+ 1
+ read-write
+
+
+ ALST2
+ ALST2
+ 18
+ 1
+ read-write
+
+
+ TXOK2
+ TXOK2
+ 17
+ 1
+ read-write
+
+
+ RQCP2
+ RQCP2
+ 16
+ 1
+ read-write
+
+
+ ABRQ1
+ ABRQ1
+ 15
+ 1
+ read-write
+
+
+ TERR1
+ TERR1
+ 11
+ 1
+ read-write
+
+
+ ALST1
+ ALST1
+ 10
+ 1
+ read-write
+
+
+ TXOK1
+ TXOK1
+ 9
+ 1
+ read-write
+
+
+ RQCP1
+ RQCP1
+ 8
+ 1
+ read-write
+
+
+ ABRQ0
+ ABRQ0
+ 7
+ 1
+ read-write
+
+
+ TERR0
+ TERR0
+ 3
+ 1
+ read-write
+
+
+ ALST0
+ ALST0
+ 2
+ 1
+ read-write
+
+
+ TXOK0
+ TXOK0
+ 1
+ 1
+ read-write
+
+
+ RQCP0
+ RQCP0
+ 0
+ 1
+ read-write
+
+
+
+
+ RF0R
+ RF0R
+ receive FIFO 0 register
+ 0xC
+ 0x20
+ 0x00000000
+
+
+ RFOM0
+ RFOM0
+ 5
+ 1
+ read-write
+
+
+ FOVR0
+ FOVR0
+ 4
+ 1
+ read-write
+
+
+ FULL0
+ FULL0
+ 3
+ 1
+ read-write
+
+
+ FMP0
+ FMP0
+ 0
+ 2
+ read-only
+
+
+
+
+ RF1R
+ RF1R
+ receive FIFO 1 register
+ 0x10
+ 0x20
+ 0x00000000
+
+
+ RFOM1
+ RFOM1
+ 5
+ 1
+ read-write
+
+
+ FOVR1
+ FOVR1
+ 4
+ 1
+ read-write
+
+
+ FULL1
+ FULL1
+ 3
+ 1
+ read-write
+
+
+ FMP1
+ FMP1
+ 0
+ 2
+ read-only
+
+
+
+
+ IER
+ IER
+ interrupt enable register
+ 0x14
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SLKIE
+ SLKIE
+ 17
+ 1
+
+
+ WKUIE
+ WKUIE
+ 16
+ 1
+
+
+ ERRIE
+ ERRIE
+ 15
+ 1
+
+
+ LECIE
+ LECIE
+ 11
+ 1
+
+
+ BOFIE
+ BOFIE
+ 10
+ 1
+
+
+ EPVIE
+ EPVIE
+ 9
+ 1
+
+
+ EWGIE
+ EWGIE
+ 8
+ 1
+
+
+ FOVIE1
+ FOVIE1
+ 6
+ 1
+
+
+ FFIE1
+ FFIE1
+ 5
+ 1
+
+
+ FMPIE1
+ FMPIE1
+ 4
+ 1
+
+
+ FOVIE0
+ FOVIE0
+ 3
+ 1
+
+
+ FFIE0
+ FFIE0
+ 2
+ 1
+
+
+ FMPIE0
+ FMPIE0
+ 1
+ 1
+
+
+ TMEIE
+ TMEIE
+ 0
+ 1
+
+
+
+
+ ESR
+ ESR
+ error status register
+ 0x18
+ 0x20
+ 0x00000000
+
+
+ REC
+ REC
+ 24
+ 8
+ read-only
+
+
+ TEC
+ TEC
+ 16
+ 8
+ read-only
+
+
+ LEC
+ LEC
+ 4
+ 3
+ read-write
+
+
+ BOFF
+ BOFF
+ 2
+ 1
+ read-only
+
+
+ EPVF
+ EPVF
+ 1
+ 1
+ read-only
+
+
+ EWGF
+ EWGF
+ 0
+ 1
+ read-only
+
+
+
+
+ BTR
+ BTR
+ bit timing register
+ 0x1C
+ 0x20
+ read-write
+ 0x01230000
+
+
+ SILM
+ SILM
+ 31
+ 1
+
+
+ LBKM
+ LBKM
+ 30
+ 1
+
+
+ SJW
+ SJW
+ 24
+ 2
+
+
+ TS2
+ TS2
+ 20
+ 3
+
+
+ TS1
+ TS1
+ 16
+ 4
+
+
+ BRP
+ BRP
+ 0
+ 10
+
+
+
+
+ TI0R
+ TI0R
+ TX mailbox identifier register
+ 0x180
+ 0x20
+ read-write
+ 0x00000000
+
+
+ STID
+ STID
+ 21
+ 11
+
+
+ EXID
+ EXID
+ 3
+ 18
+
+
+ IDE
+ IDE
+ 2
+ 1
+
+
+ RTR
+ RTR
+ 1
+ 1
+
+
+ TXRQ
+ TXRQ
+ 0
+ 1
+
+
+
+
+ TDT0R
+ TDT0R
+ mailbox data length control and time stamp
+ register
+ 0x184
+ 0x20
+ read-write
+ 0x00000000
+
+
+ TIME
+ TIME
+ 16
+ 16
+
+
+ TGT
+ TGT
+ 8
+ 1
+
+
+ DLC
+ DLC
+ 0
+ 4
+
+
+
+
+ TDL0R
+ TDL0R
+ mailbox data low register
+ 0x188
+ 0x20
+ read-write
+ 0x00000000
+
+
+ DATA3
+ DATA3
+ 24
+ 8
+
+
+ DATA2
+ DATA2
+ 16
+ 8
+
+
+ DATA1
+ DATA1
+ 8
+ 8
+
+
+ DATA0
+ DATA0
+ 0
+ 8
+
+
+
+
+ TDH0R
+ TDH0R
+ mailbox data high register
+ 0x18C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ DATA7
+ DATA7
+ 24
+ 8
+
+
+ DATA6
+ DATA6
+ 16
+ 8
+
+
+ DATA5
+ DATA5
+ 8
+ 8
+
+
+ DATA4
+ DATA4
+ 0
+ 8
+
+
+
+
+ TI1R
+ TI1R
+ TX mailbox identifier register
+ 0x190
+ 0x20
+ read-write
+ 0x00000000
+
+
+ STID
+ STID
+ 21
+ 11
+
+
+ EXID
+ EXID
+ 3
+ 18
+
+
+ IDE
+ IDE
+ 2
+ 1
+
+
+ RTR
+ RTR
+ 1
+ 1
+
+
+ TXRQ
+ TXRQ
+ 0
+ 1
+
+
+
+
+ TDT1R
+ TDT1R
+ mailbox data length control and time stamp
+ register
+ 0x194
+ 0x20
+ read-write
+ 0x00000000
+
+
+ TIME
+ TIME
+ 16
+ 16
+
+
+ TGT
+ TGT
+ 8
+ 1
+
+
+ DLC
+ DLC
+ 0
+ 4
+
+
+
+
+ TDL1R
+ TDL1R
+ mailbox data low register
+ 0x198
+ 0x20
+ read-write
+ 0x00000000
+
+
+ DATA3
+ DATA3
+ 24
+ 8
+
+
+ DATA2
+ DATA2
+ 16
+ 8
+
+
+ DATA1
+ DATA1
+ 8
+ 8
+
+
+ DATA0
+ DATA0
+ 0
+ 8
+
+
+
+
+ TDH1R
+ TDH1R
+ mailbox data high register
+ 0x19C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ DATA7
+ DATA7
+ 24
+ 8
+
+
+ DATA6
+ DATA6
+ 16
+ 8
+
+
+ DATA5
+ DATA5
+ 8
+ 8
+
+
+ DATA4
+ DATA4
+ 0
+ 8
+
+
+
+
+ TI2R
+ TI2R
+ TX mailbox identifier register
+ 0x1A0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ STID
+ STID
+ 21
+ 11
+
+
+ EXID
+ EXID
+ 3
+ 18
+
+
+ IDE
+ IDE
+ 2
+ 1
+
+
+ RTR
+ RTR
+ 1
+ 1
+
+
+ TXRQ
+ TXRQ
+ 0
+ 1
+
+
+
+
+ TDT2R
+ TDT2R
+ mailbox data length control and time stamp
+ register
+ 0x1A4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ TIME
+ TIME
+ 16
+ 16
+
+
+ TGT
+ TGT
+ 8
+ 1
+
+
+ DLC
+ DLC
+ 0
+ 4
+
+
+
+
+ TDL2R
+ TDL2R
+ mailbox data low register
+ 0x1A8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ DATA3
+ DATA3
+ 24
+ 8
+
+
+ DATA2
+ DATA2
+ 16
+ 8
+
+
+ DATA1
+ DATA1
+ 8
+ 8
+
+
+ DATA0
+ DATA0
+ 0
+ 8
+
+
+
+
+ TDH2R
+ TDH2R
+ mailbox data high register
+ 0x1AC
+ 0x20
+ read-write
+ 0x00000000
+
+
+ DATA7
+ DATA7
+ 24
+ 8
+
+
+ DATA6
+ DATA6
+ 16
+ 8
+
+
+ DATA5
+ DATA5
+ 8
+ 8
+
+
+ DATA4
+ DATA4
+ 0
+ 8
+
+
+
+
+ RI0R
+ RI0R
+ receive FIFO mailbox identifier
+ register
+ 0x1B0
+ 0x20
+ read-only
+ 0x00000000
+
+
+ STID
+ STID
+ 21
+ 11
+
+
+ EXID
+ EXID
+ 3
+ 18
+
+
+ IDE
+ IDE
+ 2
+ 1
+
+
+ RTR
+ RTR
+ 1
+ 1
+
+
+
+
+ RDT0R
+ RDT0R
+ receive FIFO mailbox data length control and
+ time stamp register
+ 0x1B4
+ 0x20
+ read-only
+ 0x00000000
+
+
+ TIME
+ TIME
+ 16
+ 16
+
+
+ FMI
+ FMI
+ 8
+ 8
+
+
+ DLC
+ DLC
+ 0
+ 4
+
+
+
+
+ RDL0R
+ RDL0R
+ receive FIFO mailbox data low
+ register
+ 0x1B8
+ 0x20
+ read-only
+ 0x00000000
+
+
+ DATA3
+ DATA3
+ 24
+ 8
+
+
+ DATA2
+ DATA2
+ 16
+ 8
+
+
+ DATA1
+ DATA1
+ 8
+ 8
+
+
+ DATA0
+ DATA0
+ 0
+ 8
+
+
+
+
+ RDH0R
+ RDH0R
+ receive FIFO mailbox data high
+ register
+ 0x1BC
+ 0x20
+ read-only
+ 0x00000000
+
+
+ DATA7
+ DATA7
+ 24
+ 8
+
+
+ DATA6
+ DATA6
+ 16
+ 8
+
+
+ DATA5
+ DATA5
+ 8
+ 8
+
+
+ DATA4
+ DATA4
+ 0
+ 8
+
+
+
+
+ RI1R
+ RI1R
+ receive FIFO mailbox identifier
+ register
+ 0x1C0
+ 0x20
+ read-only
+ 0x00000000
+
+
+ STID
+ STID
+ 21
+ 11
+
+
+ EXID
+ EXID
+ 3
+ 18
+
+
+ IDE
+ IDE
+ 2
+ 1
+
+
+ RTR
+ RTR
+ 1
+ 1
+
+
+
+
+ RDT1R
+ RDT1R
+ receive FIFO mailbox data length control and
+ time stamp register
+ 0x1C4
+ 0x20
+ read-only
+ 0x00000000
+
+
+ TIME
+ TIME
+ 16
+ 16
+
+
+ FMI
+ FMI
+ 8
+ 8
+
+
+ DLC
+ DLC
+ 0
+ 4
+
+
+
+
+ RDL1R
+ RDL1R
+ receive FIFO mailbox data low
+ register
+ 0x1C8
+ 0x20
+ read-only
+ 0x00000000
+
+
+ DATA3
+ DATA3
+ 24
+ 8
+
+
+ DATA2
+ DATA2
+ 16
+ 8
+
+
+ DATA1
+ DATA1
+ 8
+ 8
+
+
+ DATA0
+ DATA0
+ 0
+ 8
+
+
+
+
+ RDH1R
+ RDH1R
+ receive FIFO mailbox data high
+ register
+ 0x1CC
+ 0x20
+ read-only
+ 0x00000000
+
+
+ DATA7
+ DATA7
+ 24
+ 8
+
+
+ DATA6
+ DATA6
+ 16
+ 8
+
+
+ DATA5
+ DATA5
+ 8
+ 8
+
+
+ DATA4
+ DATA4
+ 0
+ 8
+
+
+
+
+ FMR
+ FMR
+ filter master register
+ 0x200
+ 0x20
+ read-write
+ 0x2A1C0E01
+
+
+ CAN2SB
+ CAN2 start bank
+ 8
+ 6
+
+
+ FINIT
+ Filter init mode
+ 0
+ 1
+
+
+
+
+ FM1R
+ FM1R
+ filter mode register
+ 0x204
+ 0x20
+ read-write
+ 0x00000000
+
+
+ FBM0
+ Filter mode
+ 0
+ 1
+
+
+ FBM1
+ Filter mode
+ 1
+ 1
+
+
+ FBM2
+ Filter mode
+ 2
+ 1
+
+
+ FBM3
+ Filter mode
+ 3
+ 1
+
+
+ FBM4
+ Filter mode
+ 4
+ 1
+
+
+ FBM5
+ Filter mode
+ 5
+ 1
+
+
+ FBM6
+ Filter mode
+ 6
+ 1
+
+
+ FBM7
+ Filter mode
+ 7
+ 1
+
+
+ FBM8
+ Filter mode
+ 8
+ 1
+
+
+ FBM9
+ Filter mode
+ 9
+ 1
+
+
+ FBM10
+ Filter mode
+ 10
+ 1
+
+
+ FBM11
+ Filter mode
+ 11
+ 1
+
+
+ FBM12
+ Filter mode
+ 12
+ 1
+
+
+ FBM13
+ Filter mode
+ 13
+ 1
+
+
+ FBM14
+ Filter mode
+ 14
+ 1
+
+
+ FBM15
+ Filter mode
+ 15
+ 1
+
+
+ FBM16
+ Filter mode
+ 16
+ 1
+
+
+ FBM17
+ Filter mode
+ 17
+ 1
+
+
+ FBM18
+ Filter mode
+ 18
+ 1
+
+
+ FBM19
+ Filter mode
+ 19
+ 1
+
+
+ FBM20
+ Filter mode
+ 20
+ 1
+
+
+ FBM21
+ Filter mode
+ 21
+ 1
+
+
+ FBM22
+ Filter mode
+ 22
+ 1
+
+
+ FBM23
+ Filter mode
+ 23
+ 1
+
+
+ FBM24
+ Filter mode
+ 24
+ 1
+
+
+ FBM25
+ Filter mode
+ 25
+ 1
+
+
+ FBM26
+ Filter mode
+ 26
+ 1
+
+
+ FBM27
+ Filter mode
+ 27
+ 1
+
+
+
+
+ FS1R
+ FS1R
+ filter scale register
+ 0x20C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ FSC0
+ Filter scale configuration
+ 0
+ 1
+
+
+ FSC1
+ Filter scale configuration
+ 1
+ 1
+
+
+ FSC2
+ Filter scale configuration
+ 2
+ 1
+
+
+ FSC3
+ Filter scale configuration
+ 3
+ 1
+
+
+ FSC4
+ Filter scale configuration
+ 4
+ 1
+
+
+ FSC5
+ Filter scale configuration
+ 5
+ 1
+
+
+ FSC6
+ Filter scale configuration
+ 6
+ 1
+
+
+ FSC7
+ Filter scale configuration
+ 7
+ 1
+
+
+ FSC8
+ Filter scale configuration
+ 8
+ 1
+
+
+ FSC9
+ Filter scale configuration
+ 9
+ 1
+
+
+ FSC10
+ Filter scale configuration
+ 10
+ 1
+
+
+ FSC11
+ Filter scale configuration
+ 11
+ 1
+
+
+ FSC12
+ Filter scale configuration
+ 12
+ 1
+
+
+ FSC13
+ Filter scale configuration
+ 13
+ 1
+
+
+ FSC14
+ Filter scale configuration
+ 14
+ 1
+
+
+ FSC15
+ Filter scale configuration
+ 15
+ 1
+
+
+ FSC16
+ Filter scale configuration
+ 16
+ 1
+
+
+ FSC17
+ Filter scale configuration
+ 17
+ 1
+
+
+ FSC18
+ Filter scale configuration
+ 18
+ 1
+
+
+ FSC19
+ Filter scale configuration
+ 19
+ 1
+
+
+ FSC20
+ Filter scale configuration
+ 20
+ 1
+
+
+ FSC21
+ Filter scale configuration
+ 21
+ 1
+
+
+ FSC22
+ Filter scale configuration
+ 22
+ 1
+
+
+ FSC23
+ Filter scale configuration
+ 23
+ 1
+
+
+ FSC24
+ Filter scale configuration
+ 24
+ 1
+
+
+ FSC25
+ Filter scale configuration
+ 25
+ 1
+
+
+ FSC26
+ Filter scale configuration
+ 26
+ 1
+
+
+ FSC27
+ Filter scale configuration
+ 27
+ 1
+
+
+
+
+ FFA1R
+ FFA1R
+ filter FIFO assignment
+ register
+ 0x214
+ 0x20
+ read-write
+ 0x00000000
+
+
+ FFA0
+ Filter FIFO assignment for filter
+ 0
+ 0
+ 1
+
+
+ FFA1
+ Filter FIFO assignment for filter
+ 1
+ 1
+ 1
+
+
+ FFA2
+ Filter FIFO assignment for filter
+ 2
+ 2
+ 1
+
+
+ FFA3
+ Filter FIFO assignment for filter
+ 3
+ 3
+ 1
+
+
+ FFA4
+ Filter FIFO assignment for filter
+ 4
+ 4
+ 1
+
+
+ FFA5
+ Filter FIFO assignment for filter
+ 5
+ 5
+ 1
+
+
+ FFA6
+ Filter FIFO assignment for filter
+ 6
+ 6
+ 1
+
+
+ FFA7
+ Filter FIFO assignment for filter
+ 7
+ 7
+ 1
+
+
+ FFA8
+ Filter FIFO assignment for filter
+ 8
+ 8
+ 1
+
+
+ FFA9
+ Filter FIFO assignment for filter
+ 9
+ 9
+ 1
+
+
+ FFA10
+ Filter FIFO assignment for filter
+ 10
+ 10
+ 1
+
+
+ FFA11
+ Filter FIFO assignment for filter
+ 11
+ 11
+ 1
+
+
+ FFA12
+ Filter FIFO assignment for filter
+ 12
+ 12
+ 1
+
+
+ FFA13
+ Filter FIFO assignment for filter
+ 13
+ 13
+ 1
+
+
+ FFA14
+ Filter FIFO assignment for filter
+ 14
+ 14
+ 1
+
+
+ FFA15
+ Filter FIFO assignment for filter
+ 15
+ 15
+ 1
+
+
+ FFA16
+ Filter FIFO assignment for filter
+ 16
+ 16
+ 1
+
+
+ FFA17
+ Filter FIFO assignment for filter
+ 17
+ 17
+ 1
+
+
+ FFA18
+ Filter FIFO assignment for filter
+ 18
+ 18
+ 1
+
+
+ FFA19
+ Filter FIFO assignment for filter
+ 19
+ 19
+ 1
+
+
+ FFA20
+ Filter FIFO assignment for filter
+ 20
+ 20
+ 1
+
+
+ FFA21
+ Filter FIFO assignment for filter
+ 21
+ 21
+ 1
+
+
+ FFA22
+ Filter FIFO assignment for filter
+ 22
+ 22
+ 1
+
+
+ FFA23
+ Filter FIFO assignment for filter
+ 23
+ 23
+ 1
+
+
+ FFA24
+ Filter FIFO assignment for filter
+ 24
+ 24
+ 1
+
+
+ FFA25
+ Filter FIFO assignment for filter
+ 25
+ 25
+ 1
+
+
+ FFA26
+ Filter FIFO assignment for filter
+ 26
+ 26
+ 1
+
+
+ FFA27
+ Filter FIFO assignment for filter
+ 27
+ 27
+ 1
+
+
+
+
+ FA1R
+ FA1R
+ CAN filter activation register
+ 0x21C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ FACT0
+ Filter active
+ 0
+ 1
+
+
+ FACT1
+ Filter active
+ 1
+ 1
+
+
+ FACT2
+ Filter active
+ 2
+ 1
+
+
+ FACT3
+ Filter active
+ 3
+ 1
+
+
+ FACT4
+ Filter active
+ 4
+ 1
+
+
+ FACT5
+ Filter active
+ 5
+ 1
+
+
+ FACT6
+ Filter active
+ 6
+ 1
+
+
+ FACT7
+ Filter active
+ 7
+ 1
+
+
+ FACT8
+ Filter active
+ 8
+ 1
+
+
+ FACT9
+ Filter active
+ 9
+ 1
+
+
+ FACT10
+ Filter active
+ 10
+ 1
+
+
+ FACT11
+ Filter active
+ 11
+ 1
+
+
+ FACT12
+ Filter active
+ 12
+ 1
+
+
+ FACT13
+ Filter active
+ 13
+ 1
+
+
+ FACT14
+ Filter active
+ 14
+ 1
+
+
+ FACT15
+ Filter active
+ 15
+ 1
+
+
+ FACT16
+ Filter active
+ 16
+ 1
+
+
+ FACT17
+ Filter active
+ 17
+ 1
+
+
+ FACT18
+ Filter active
+ 18
+ 1
+
+
+ FACT19
+ Filter active
+ 19
+ 1
+
+
+ FACT20
+ Filter active
+ 20
+ 1
+
+
+ FACT21
+ Filter active
+ 21
+ 1
+
+
+ FACT22
+ Filter active
+ 22
+ 1
+
+
+ FACT23
+ Filter active
+ 23
+ 1
+
+
+ FACT24
+ Filter active
+ 24
+ 1
+
+
+ FACT25
+ Filter active
+ 25
+ 1
+
+
+ FACT26
+ Filter active
+ 26
+ 1
+
+
+ FACT27
+ Filter active
+ 27
+ 1
+
+
+
+
+ F0R1
+ F0R1
+ Filter bank 0 register 1
+ 0x240
+ 0x20
+ read-write
+ 0x00000000
+
+
+ FB0
+ Filter bits
+ 0
+ 1
+
+
+ FB1
+ Filter bits
+ 1
+ 1
+
+
+ FB2
+ Filter bits
+ 2
+ 1
+
+
+ FB3
+ Filter bits
+ 3
+ 1
+
+
+ FB4
+ Filter bits
+ 4
+ 1
+
+
+ FB5
+ Filter bits
+ 5
+ 1
+
+
+ FB6
+ Filter bits
+ 6
+ 1
+
+
+ FB7
+ Filter bits
+ 7
+ 1
+
+
+ FB8
+ Filter bits
+ 8
+ 1
+
+
+ FB9
+ Filter bits
+ 9
+ 1
+
+
+ FB10
+ Filter bits
+ 10
+ 1
+
+
+ FB11
+ Filter bits
+ 11
+ 1
+
+
+ FB12
+ Filter bits
+ 12
+ 1
+
+
+ FB13
+ Filter bits
+ 13
+ 1
+
+
+ FB14
+ Filter bits
+ 14
+ 1
+
+
+ FB15
+ Filter bits
+ 15
+ 1
+
+
+ FB16
+ Filter bits
+ 16
+ 1
+
+
+ FB17
+ Filter bits
+ 17
+ 1
+
+
+ FB18
+ Filter bits
+ 18
+ 1
+
+
+ FB19
+ Filter bits
+ 19
+ 1
+
+
+ FB20
+ Filter bits
+ 20
+ 1
+
+
+ FB21
+ Filter bits
+ 21
+ 1
+
+
+ FB22
+ Filter bits
+ 22
+ 1
+
+
+ FB23
+ Filter bits
+ 23
+ 1
+
+
+ FB24
+ Filter bits
+ 24
+ 1
+
+
+ FB25
+ Filter bits
+ 25
+ 1
+
+
+ FB26
+ Filter bits
+ 26
+ 1
+
+
+ FB27
+ Filter bits
+ 27
+ 1
+
+
+ FB28
+ Filter bits
+ 28
+ 1
+
+
+ FB29
+ Filter bits
+ 29
+ 1
+
+
+ FB30
+ Filter bits
+ 30
+ 1
+
+
+ FB31
+ Filter bits
+ 31
+ 1
+
+
+
+
+ F0R2
+ F0R2
+ Filter bank 0 register 2
+ 0x244
+ 0x20
+ read-write
+ 0x00000000
+
+
+ FB0
+ Filter bits
+ 0
+ 1
+
+
+ FB1
+ Filter bits
+ 1
+ 1
+
+
+ FB2
+ Filter bits
+ 2
+ 1
+
+
+ FB3
+ Filter bits
+ 3
+ 1
+
+
+ FB4
+ Filter bits
+ 4
+ 1
+
+
+ FB5
+ Filter bits
+ 5
+ 1
+
+
+ FB6
+ Filter bits
+ 6
+ 1
+
+
+ FB7
+ Filter bits
+ 7
+ 1
+
+
+ FB8
+ Filter bits
+ 8
+ 1
+
+
+ FB9
+ Filter bits
+ 9
+ 1
+
+
+ FB10
+ Filter bits
+ 10
+ 1
+
+
+ FB11
+ Filter bits
+ 11
+ 1
+
+
+ FB12
+ Filter bits
+ 12
+ 1
+
+
+ FB13
+ Filter bits
+ 13
+ 1
+
+
+ FB14
+ Filter bits
+ 14
+ 1
+
+
+ FB15
+ Filter bits
+ 15
+ 1
+
+
+ FB16
+ Filter bits
+ 16
+ 1
+
+
+ FB17
+ Filter bits
+ 17
+ 1
+
+
+ FB18
+ Filter bits
+ 18
+ 1
+
+
+ FB19
+ Filter bits
+ 19
+ 1
+
+
+ FB20
+ Filter bits
+ 20
+ 1
+
+
+ FB21
+ Filter bits
+ 21
+ 1
+
+
+ FB22
+ Filter bits
+ 22
+ 1
+
+
+ FB23
+ Filter bits
+ 23
+ 1
+
+
+ FB24
+ Filter bits
+ 24
+ 1
+
+
+ FB25
+ Filter bits
+ 25
+ 1
+
+
+ FB26
+ Filter bits
+ 26
+ 1
+
+
+ FB27
+ Filter bits
+ 27
+ 1
+
+
+ FB28
+ Filter bits
+ 28
+ 1
+
+
+ FB29
+ Filter bits
+ 29
+ 1
+
+
+ FB30
+ Filter bits
+ 30
+ 1
+
+
+ FB31
+ Filter bits
+ 31
+ 1
+
+
+
+
+ F1R1
+ F1R1
+ Filter bank 1 register 1
+ 0x248
+ 0x20
+ read-write
+ 0x00000000
+
+
+ FB0
+ Filter bits
+ 0
+ 1
+
+
+ FB1
+ Filter bits
+ 1
+ 1
+
+
+ FB2
+ Filter bits
+ 2
+ 1
+
+
+ FB3
+ Filter bits
+ 3
+ 1
+
+
+ FB4
+ Filter bits
+ 4
+ 1
+
+
+ FB5
+ Filter bits
+ 5
+ 1
+
+
+ FB6
+ Filter bits
+ 6
+ 1
+
+
+ FB7
+ Filter bits
+ 7
+ 1
+
+
+ FB8
+ Filter bits
+ 8
+ 1
+
+
+ FB9
+ Filter bits
+ 9
+ 1
+
+
+ FB10
+ Filter bits
+ 10
+ 1
+
+
+ FB11
+ Filter bits
+ 11
+ 1
+
+
+ FB12
+ Filter bits
+ 12
+ 1
+
+
+ FB13
+ Filter bits
+ 13
+ 1
+
+
+ FB14
+ Filter bits
+ 14
+ 1
+
+
+ FB15
+ Filter bits
+ 15
+ 1
+
+
+ FB16
+ Filter bits
+ 16
+ 1
+
+
+ FB17
+ Filter bits
+ 17
+ 1
+
+
+ FB18
+ Filter bits
+ 18
+ 1
+
+
+ FB19
+ Filter bits
+ 19
+ 1
+
+
+ FB20
+ Filter bits
+ 20
+ 1
+
+
+ FB21
+ Filter bits
+ 21
+ 1
+
+
+ FB22
+ Filter bits
+ 22
+ 1
+
+
+ FB23
+ Filter bits
+ 23
+ 1
+
+
+ FB24
+ Filter bits
+ 24
+ 1
+
+
+ FB25
+ Filter bits
+ 25
+ 1
+
+
+ FB26
+ Filter bits
+ 26
+ 1
+
+
+ FB27
+ Filter bits
+ 27
+ 1
+
+
+ FB28
+ Filter bits
+ 28
+ 1
+
+
+ FB29
+ Filter bits
+ 29
+ 1
+
+
+ FB30
+ Filter bits
+ 30
+ 1
+
+
+ FB31
+ Filter bits
+ 31
+ 1
+
+
+
+
+ F1R2
+ F1R2
+ Filter bank 1 register 2
+ 0x24C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ FB0
+ Filter bits
+ 0
+ 1
+
+
+ FB1
+ Filter bits
+ 1
+ 1
+
+
+ FB2
+ Filter bits
+ 2
+ 1
+
+
+ FB3
+ Filter bits
+ 3
+ 1
+
+
+ FB4
+ Filter bits
+ 4
+ 1
+
+
+ FB5
+ Filter bits
+ 5
+ 1
+
+
+ FB6
+ Filter bits
+ 6
+ 1
+
+
+ FB7
+ Filter bits
+ 7
+ 1
+
+
+ FB8
+ Filter bits
+ 8
+ 1
+
+
+ FB9
+ Filter bits
+ 9
+ 1
+
+
+ FB10
+ Filter bits
+ 10
+ 1
+
+
+ FB11
+ Filter bits
+ 11
+ 1
+
+
+ FB12
+ Filter bits
+ 12
+ 1
+
+
+ FB13
+ Filter bits
+ 13
+ 1
+
+
+ FB14
+ Filter bits
+ 14
+ 1
+
+
+ FB15
+ Filter bits
+ 15
+ 1
+
+
+ FB16
+ Filter bits
+ 16
+ 1
+
+
+ FB17
+ Filter bits
+ 17
+ 1
+
+
+ FB18
+ Filter bits
+ 18
+ 1
+
+
+ FB19
+ Filter bits
+ 19
+ 1
+
+
+ FB20
+ Filter bits
+ 20
+ 1
+
+
+ FB21
+ Filter bits
+ 21
+ 1
+
+
+ FB22
+ Filter bits
+ 22
+ 1
+
+
+ FB23
+ Filter bits
+ 23
+ 1
+
+
+ FB24
+ Filter bits
+ 24
+ 1
+
+
+ FB25
+ Filter bits
+ 25
+ 1
+
+
+ FB26
+ Filter bits
+ 26
+ 1
+
+
+ FB27
+ Filter bits
+ 27
+ 1
+
+
+ FB28
+ Filter bits
+ 28
+ 1
+
+
+ FB29
+ Filter bits
+ 29
+ 1
+
+
+ FB30
+ Filter bits
+ 30
+ 1
+
+
+ FB31
+ Filter bits
+ 31
+ 1
+
+
+
+
+ F2R1
+ F2R1
+ Filter bank 2 register 1
+ 0x250
+ 0x20
+ read-write
+ 0x00000000
+
+
+ FB0
+ Filter bits
+ 0
+ 1
+
+
+ FB1
+ Filter bits
+ 1
+ 1
+
+
+ FB2
+ Filter bits
+ 2
+ 1
+
+
+ FB3
+ Filter bits
+ 3
+ 1
+
+
+ FB4
+ Filter bits
+ 4
+ 1
+
+
+ FB5
+ Filter bits
+ 5
+ 1
+
+
+ FB6
+ Filter bits
+ 6
+ 1
+
+
+ FB7
+ Filter bits
+ 7
+ 1
+
+
+ FB8
+ Filter bits
+ 8
+ 1
+
+
+ FB9
+ Filter bits
+ 9
+ 1
+
+
+ FB10
+ Filter bits
+ 10
+ 1
+
+
+ FB11
+ Filter bits
+ 11
+ 1
+
+
+ FB12
+ Filter bits
+ 12
+ 1
+
+
+ FB13
+ Filter bits
+ 13
+ 1
+
+
+ FB14
+ Filter bits
+ 14
+ 1
+
+
+ FB15
+ Filter bits
+ 15
+ 1
+
+
+ FB16
+ Filter bits
+ 16
+ 1
+
+
+ FB17
+ Filter bits
+ 17
+ 1
+
+
+ FB18
+ Filter bits
+ 18
+ 1
+
+
+ FB19
+ Filter bits
+ 19
+ 1
+
+
+ FB20
+ Filter bits
+ 20
+ 1
+
+
+ FB21
+ Filter bits
+ 21
+ 1
+
+
+ FB22
+ Filter bits
+ 22
+ 1
+
+
+ FB23
+ Filter bits
+ 23
+ 1
+
+
+ FB24
+ Filter bits
+ 24
+ 1
+
+
+ FB25
+ Filter bits
+ 25
+ 1
+
+
+ FB26
+ Filter bits
+ 26
+ 1
+
+
+ FB27
+ Filter bits
+ 27
+ 1
+
+
+ FB28
+ Filter bits
+ 28
+ 1
+
+
+ FB29
+ Filter bits
+ 29
+ 1
+
+
+ FB30
+ Filter bits
+ 30
+ 1
+
+
+ FB31
+ Filter bits
+ 31
+ 1
+
+
+
+
+ F2R2
+ F2R2
+ Filter bank 2 register 2
+ 0x254
+ 0x20
+ read-write
+ 0x00000000
+
+
+ FB0
+ Filter bits
+ 0
+ 1
+
+
+ FB1
+ Filter bits
+ 1
+ 1
+
+
+ FB2
+ Filter bits
+ 2
+ 1
+
+
+ FB3
+ Filter bits
+ 3
+ 1
+
+
+ FB4
+ Filter bits
+ 4
+ 1
+
+
+ FB5
+ Filter bits
+ 5
+ 1
+
+
+ FB6
+ Filter bits
+ 6
+ 1
+
+
+ FB7
+ Filter bits
+ 7
+ 1
+
+
+ FB8
+ Filter bits
+ 8
+ 1
+
+
+ FB9
+ Filter bits
+ 9
+ 1
+
+
+ FB10
+ Filter bits
+ 10
+ 1
+
+
+ FB11
+ Filter bits
+ 11
+ 1
+
+
+ FB12
+ Filter bits
+ 12
+ 1
+
+
+ FB13
+ Filter bits
+ 13
+ 1
+
+
+ FB14
+ Filter bits
+ 14
+ 1
+
+
+ FB15
+ Filter bits
+ 15
+ 1
+
+
+ FB16
+ Filter bits
+ 16
+ 1
+
+
+ FB17
+ Filter bits
+ 17
+ 1
+
+
+ FB18
+ Filter bits
+ 18
+ 1
+
+
+ FB19
+ Filter bits
+ 19
+ 1
+
+
+ FB20
+ Filter bits
+ 20
+ 1
+
+
+ FB21
+ Filter bits
+ 21
+ 1
+
+
+ FB22
+ Filter bits
+ 22
+ 1
+
+
+ FB23
+ Filter bits
+ 23
+ 1
+
+
+ FB24
+ Filter bits
+ 24
+ 1
+
+
+ FB25
+ Filter bits
+ 25
+ 1
+
+
+ FB26
+ Filter bits
+ 26
+ 1
+
+
+ FB27
+ Filter bits
+ 27
+ 1
+
+
+ FB28
+ Filter bits
+ 28
+ 1
+
+
+ FB29
+ Filter bits
+ 29
+ 1
+
+
+ FB30
+ Filter bits
+ 30
+ 1
+
+
+ FB31
+ Filter bits
+ 31
+ 1
+
+
+
+
+ F3R1
+ F3R1
+ Filter bank 3 register 1
+ 0x258
+ 0x20
+ read-write
+ 0x00000000
+
+
+ FB0
+ Filter bits
+ 0
+ 1
+
+
+ FB1
+ Filter bits
+ 1
+ 1
+
+
+ FB2
+ Filter bits
+ 2
+ 1
+
+
+ FB3
+ Filter bits
+ 3
+ 1
+
+
+ FB4
+ Filter bits
+ 4
+ 1
+
+
+ FB5
+ Filter bits
+ 5
+ 1
+
+
+ FB6
+ Filter bits
+ 6
+ 1
+
+
+ FB7
+ Filter bits
+ 7
+ 1
+
+
+ FB8
+ Filter bits
+ 8
+ 1
+
+
+ FB9
+ Filter bits
+ 9
+ 1
+
+
+ FB10
+ Filter bits
+ 10
+ 1
+
+
+ FB11
+ Filter bits
+ 11
+ 1
+
+
+ FB12
+ Filter bits
+ 12
+ 1
+
+
+ FB13
+ Filter bits
+ 13
+ 1
+
+
+ FB14
+ Filter bits
+ 14
+ 1
+
+
+ FB15
+ Filter bits
+ 15
+ 1
+
+
+ FB16
+ Filter bits
+ 16
+ 1
+
+
+ FB17
+ Filter bits
+ 17
+ 1
+
+
+ FB18
+ Filter bits
+ 18
+ 1
+
+
+ FB19
+ Filter bits
+ 19
+ 1
+
+
+ FB20
+ Filter bits
+ 20
+ 1
+
+
+ FB21
+ Filter bits
+ 21
+ 1
+
+
+ FB22
+ Filter bits
+ 22
+ 1
+
+
+ FB23
+ Filter bits
+ 23
+ 1
+
+
+ FB24
+ Filter bits
+ 24
+ 1
+
+
+ FB25
+ Filter bits
+ 25
+ 1
+
+
+ FB26
+ Filter bits
+ 26
+ 1
+
+
+ FB27
+ Filter bits
+ 27
+ 1
+
+
+ FB28
+ Filter bits
+ 28
+ 1
+
+
+ FB29
+ Filter bits
+ 29
+ 1
+
+
+ FB30
+ Filter bits
+ 30
+ 1
+
+
+ FB31
+ Filter bits
+ 31
+ 1
+
+
+
+
+ F3R2
+ F3R2
+ Filter bank 3 register 2
+ 0x25C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ FB0
+ Filter bits
+ 0
+ 1
+
+
+ FB1
+ Filter bits
+ 1
+ 1
+
+
+ FB2
+ Filter bits
+ 2
+ 1
+
+
+ FB3
+ Filter bits
+ 3
+ 1
+
+
+ FB4
+ Filter bits
+ 4
+ 1
+
+
+ FB5
+ Filter bits
+ 5
+ 1
+
+
+ FB6
+ Filter bits
+ 6
+ 1
+
+
+ FB7
+ Filter bits
+ 7
+ 1
+
+
+ FB8
+ Filter bits
+ 8
+ 1
+
+
+ FB9
+ Filter bits
+ 9
+ 1
+
+
+ FB10
+ Filter bits
+ 10
+ 1
+
+
+ FB11
+ Filter bits
+ 11
+ 1
+
+
+ FB12
+ Filter bits
+ 12
+ 1
+
+
+ FB13
+ Filter bits
+ 13
+ 1
+
+
+ FB14
+ Filter bits
+ 14
+ 1
+
+
+ FB15
+ Filter bits
+ 15
+ 1
+
+
+ FB16
+ Filter bits
+ 16
+ 1
+
+
+ FB17
+ Filter bits
+ 17
+ 1
+
+
+ FB18
+ Filter bits
+ 18
+ 1
+
+
+ FB19
+ Filter bits
+ 19
+ 1
+
+
+ FB20
+ Filter bits
+ 20
+ 1
+
+
+ FB21
+ Filter bits
+ 21
+ 1
+
+
+ FB22
+ Filter bits
+ 22
+ 1
+
+
+ FB23
+ Filter bits
+ 23
+ 1
+
+
+ FB24
+ Filter bits
+ 24
+ 1
+
+
+ FB25
+ Filter bits
+ 25
+ 1
+
+
+ FB26
+ Filter bits
+ 26
+ 1
+
+
+ FB27
+ Filter bits
+ 27
+ 1
+
+
+ FB28
+ Filter bits
+ 28
+ 1
+
+
+ FB29
+ Filter bits
+ 29
+ 1
+
+
+ FB30
+ Filter bits
+ 30
+ 1
+
+
+ FB31
+ Filter bits
+ 31
+ 1
+
+
+
+
+ F4R1
+ F4R1
+ Filter bank 4 register 1
+ 0x260
+ 0x20
+ read-write
+ 0x00000000
+
+
+ FB0
+ Filter bits
+ 0
+ 1
+
+
+ FB1
+ Filter bits
+ 1
+ 1
+
+
+ FB2
+ Filter bits
+ 2
+ 1
+
+
+ FB3
+ Filter bits
+ 3
+ 1
+
+
+ FB4
+ Filter bits
+ 4
+ 1
+
+
+ FB5
+ Filter bits
+ 5
+ 1
+
+
+ FB6
+ Filter bits
+ 6
+ 1
+
+
+ FB7
+ Filter bits
+ 7
+ 1
+
+
+ FB8
+ Filter bits
+ 8
+ 1
+
+
+ FB9
+ Filter bits
+ 9
+ 1
+
+
+ FB10
+ Filter bits
+ 10
+ 1
+
+
+ FB11
+ Filter bits
+ 11
+ 1
+
+
+ FB12
+ Filter bits
+ 12
+ 1
+
+
+ FB13
+ Filter bits
+ 13
+ 1
+
+
+ FB14
+ Filter bits
+ 14
+ 1
+
+
+ FB15
+ Filter bits
+ 15
+ 1
+
+
+ FB16
+ Filter bits
+ 16
+ 1
+
+
+ FB17
+ Filter bits
+ 17
+ 1
+
+
+ FB18
+ Filter bits
+ 18
+ 1
+
+
+ FB19
+ Filter bits
+ 19
+ 1
+
+
+ FB20
+ Filter bits
+ 20
+ 1
+
+
+ FB21
+ Filter bits
+ 21
+ 1
+
+
+ FB22
+ Filter bits
+ 22
+ 1
+
+
+ FB23
+ Filter bits
+ 23
+ 1
+
+
+ FB24
+ Filter bits
+ 24
+ 1
+
+
+ FB25
+ Filter bits
+ 25
+ 1
+
+
+ FB26
+ Filter bits
+ 26
+ 1
+
+
+ FB27
+ Filter bits
+ 27
+ 1
+
+
+ FB28
+ Filter bits
+ 28
+ 1
+
+
+ FB29
+ Filter bits
+ 29
+ 1
+
+
+ FB30
+ Filter bits
+ 30
+ 1
+
+
+ FB31
+ Filter bits
+ 31
+ 1
+
+
+
+
+ F4R2
+ F4R2
+ Filter bank 4 register 2
+ 0x264
+ 0x20
+ read-write
+ 0x00000000
+
+
+ FB0
+ Filter bits
+ 0
+ 1
+
+
+ FB1
+ Filter bits
+ 1
+ 1
+
+
+ FB2
+ Filter bits
+ 2
+ 1
+
+
+ FB3
+ Filter bits
+ 3
+ 1
+
+
+ FB4
+ Filter bits
+ 4
+ 1
+
+
+ FB5
+ Filter bits
+ 5
+ 1
+
+
+ FB6
+ Filter bits
+ 6
+ 1
+
+
+ FB7
+ Filter bits
+ 7
+ 1
+
+
+ FB8
+ Filter bits
+ 8
+ 1
+
+
+ FB9
+ Filter bits
+ 9
+ 1
+
+
+ FB10
+ Filter bits
+ 10
+ 1
+
+
+ FB11
+ Filter bits
+ 11
+ 1
+
+
+ FB12
+ Filter bits
+ 12
+ 1
+
+
+ FB13
+ Filter bits
+ 13
+ 1
+
+
+ FB14
+ Filter bits
+ 14
+ 1
+
+
+ FB15
+ Filter bits
+ 15
+ 1
+
+
+ FB16
+ Filter bits
+ 16
+ 1
+
+
+ FB17
+ Filter bits
+ 17
+ 1
+
+
+ FB18
+ Filter bits
+ 18
+ 1
+
+
+ FB19
+ Filter bits
+ 19
+ 1
+
+
+ FB20
+ Filter bits
+ 20
+ 1
+
+
+ FB21
+ Filter bits
+ 21
+ 1
+
+
+ FB22
+ Filter bits
+ 22
+ 1
+
+
+ FB23
+ Filter bits
+ 23
+ 1
+
+
+ FB24
+ Filter bits
+ 24
+ 1
+
+
+ FB25
+ Filter bits
+ 25
+ 1
+
+
+ FB26
+ Filter bits
+ 26
+ 1
+
+
+ FB27
+ Filter bits
+ 27
+ 1
+
+
+ FB28
+ Filter bits
+ 28
+ 1
+
+
+ FB29
+ Filter bits
+ 29
+ 1
+
+
+ FB30
+ Filter bits
+ 30
+ 1
+
+
+ FB31
+ Filter bits
+ 31
+ 1
+
+
+
+
+ F5R1
+ F5R1
+ Filter bank 5 register 1
+ 0x268
+ 0x20
+ read-write
+ 0x00000000
+
+
+ FB0
+ Filter bits
+ 0
+ 1
+
+
+ FB1
+ Filter bits
+ 1
+ 1
+
+
+ FB2
+ Filter bits
+ 2
+ 1
+
+
+ FB3
+ Filter bits
+ 3
+ 1
+
+
+ FB4
+ Filter bits
+ 4
+ 1
+
+
+ FB5
+ Filter bits
+ 5
+ 1
+
+
+ FB6
+ Filter bits
+ 6
+ 1
+
+
+ FB7
+ Filter bits
+ 7
+ 1
+
+
+ FB8
+ Filter bits
+ 8
+ 1
+
+
+ FB9
+ Filter bits
+ 9
+ 1
+
+
+ FB10
+ Filter bits
+ 10
+ 1
+
+
+ FB11
+ Filter bits
+ 11
+ 1
+
+
+ FB12
+ Filter bits
+ 12
+ 1
+
+
+ FB13
+ Filter bits
+ 13
+ 1
+
+
+ FB14
+ Filter bits
+ 14
+ 1
+
+
+ FB15
+ Filter bits
+ 15
+ 1
+
+
+ FB16
+ Filter bits
+ 16
+ 1
+
+
+ FB17
+ Filter bits
+ 17
+ 1
+
+
+ FB18
+ Filter bits
+ 18
+ 1
+
+
+ FB19
+ Filter bits
+ 19
+ 1
+
+
+ FB20
+ Filter bits
+ 20
+ 1
+
+
+ FB21
+ Filter bits
+ 21
+ 1
+
+
+ FB22
+ Filter bits
+ 22
+ 1
+
+
+ FB23
+ Filter bits
+ 23
+ 1
+
+
+ FB24
+ Filter bits
+ 24
+ 1
+
+
+ FB25
+ Filter bits
+ 25
+ 1
+
+
+ FB26
+ Filter bits
+ 26
+ 1
+
+
+ FB27
+ Filter bits
+ 27
+ 1
+
+
+ FB28
+ Filter bits
+ 28
+ 1
+
+
+ FB29
+ Filter bits
+ 29
+ 1
+
+
+ FB30
+ Filter bits
+ 30
+ 1
+
+
+ FB31
+ Filter bits
+ 31
+ 1
+
+
+
+
+ F5R2
+ F5R2
+ Filter bank 5 register 2
+ 0x26C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ FB0
+ Filter bits
+ 0
+ 1
+
+
+ FB1
+ Filter bits
+ 1
+ 1
+
+
+ FB2
+ Filter bits
+ 2
+ 1
+
+
+ FB3
+ Filter bits
+ 3
+ 1
+
+
+ FB4
+ Filter bits
+ 4
+ 1
+
+
+ FB5
+ Filter bits
+ 5
+ 1
+
+
+ FB6
+ Filter bits
+ 6
+ 1
+
+
+ FB7
+ Filter bits
+ 7
+ 1
+
+
+ FB8
+ Filter bits
+ 8
+ 1
+
+
+ FB9
+ Filter bits
+ 9
+ 1
+
+
+ FB10
+ Filter bits
+ 10
+ 1
+
+
+ FB11
+ Filter bits
+ 11
+ 1
+
+
+ FB12
+ Filter bits
+ 12
+ 1
+
+
+ FB13
+ Filter bits
+ 13
+ 1
+
+
+ FB14
+ Filter bits
+ 14
+ 1
+
+
+ FB15
+ Filter bits
+ 15
+ 1
+
+
+ FB16
+ Filter bits
+ 16
+ 1
+
+
+ FB17
+ Filter bits
+ 17
+ 1
+
+
+ FB18
+ Filter bits
+ 18
+ 1
+
+
+ FB19
+ Filter bits
+ 19
+ 1
+
+
+ FB20
+ Filter bits
+ 20
+ 1
+
+
+ FB21
+ Filter bits
+ 21
+ 1
+
+
+ FB22
+ Filter bits
+ 22
+ 1
+
+
+ FB23
+ Filter bits
+ 23
+ 1
+
+
+ FB24
+ Filter bits
+ 24
+ 1
+
+
+ FB25
+ Filter bits
+ 25
+ 1
+
+
+ FB26
+ Filter bits
+ 26
+ 1
+
+
+ FB27
+ Filter bits
+ 27
+ 1
+
+
+ FB28
+ Filter bits
+ 28
+ 1
+
+
+ FB29
+ Filter bits
+ 29
+ 1
+
+
+ FB30
+ Filter bits
+ 30
+ 1
+
+
+ FB31
+ Filter bits
+ 31
+ 1
+
+
+
+
+ F6R1
+ F6R1
+ Filter bank 6 register 1
+ 0x270
+ 0x20
+ read-write
+ 0x00000000
+
+
+ FB0
+ Filter bits
+ 0
+ 1
+
+
+ FB1
+ Filter bits
+ 1
+ 1
+
+
+ FB2
+ Filter bits
+ 2
+ 1
+
+
+ FB3
+ Filter bits
+ 3
+ 1
+
+
+ FB4
+ Filter bits
+ 4
+ 1
+
+
+ FB5
+ Filter bits
+ 5
+ 1
+
+
+ FB6
+ Filter bits
+ 6
+ 1
+
+
+ FB7
+ Filter bits
+ 7
+ 1
+
+
+ FB8
+ Filter bits
+ 8
+ 1
+
+
+ FB9
+ Filter bits
+ 9
+ 1
+
+
+ FB10
+ Filter bits
+ 10
+ 1
+
+
+ FB11
+ Filter bits
+ 11
+ 1
+
+
+ FB12
+ Filter bits
+ 12
+ 1
+
+
+ FB13
+ Filter bits
+ 13
+ 1
+
+
+ FB14
+ Filter bits
+ 14
+ 1
+
+
+ FB15
+ Filter bits
+ 15
+ 1
+
+
+ FB16
+ Filter bits
+ 16
+ 1
+
+
+ FB17
+ Filter bits
+ 17
+ 1
+
+
+ FB18
+ Filter bits
+ 18
+ 1
+
+
+ FB19
+ Filter bits
+ 19
+ 1
+
+
+ FB20
+ Filter bits
+ 20
+ 1
+
+
+ FB21
+ Filter bits
+ 21
+ 1
+
+
+ FB22
+ Filter bits
+ 22
+ 1
+
+
+ FB23
+ Filter bits
+ 23
+ 1
+
+
+ FB24
+ Filter bits
+ 24
+ 1
+
+
+ FB25
+ Filter bits
+ 25
+ 1
+
+
+ FB26
+ Filter bits
+ 26
+ 1
+
+
+ FB27
+ Filter bits
+ 27
+ 1
+
+
+ FB28
+ Filter bits
+ 28
+ 1
+
+
+ FB29
+ Filter bits
+ 29
+ 1
+
+
+ FB30
+ Filter bits
+ 30
+ 1
+
+
+ FB31
+ Filter bits
+ 31
+ 1
+
+
+
+
+ F6R2
+ F6R2
+ Filter bank 6 register 2
+ 0x274
+ 0x20
+ read-write
+ 0x00000000
+
+
+ FB0
+ Filter bits
+ 0
+ 1
+
+
+ FB1
+ Filter bits
+ 1
+ 1
+
+
+ FB2
+ Filter bits
+ 2
+ 1
+
+
+ FB3
+ Filter bits
+ 3
+ 1
+
+
+ FB4
+ Filter bits
+ 4
+ 1
+
+
+ FB5
+ Filter bits
+ 5
+ 1
+
+
+ FB6
+ Filter bits
+ 6
+ 1
+
+
+ FB7
+ Filter bits
+ 7
+ 1
+
+
+ FB8
+ Filter bits
+ 8
+ 1
+
+
+ FB9
+ Filter bits
+ 9
+ 1
+
+
+ FB10
+ Filter bits
+ 10
+ 1
+
+
+ FB11
+ Filter bits
+ 11
+ 1
+
+
+ FB12
+ Filter bits
+ 12
+ 1
+
+
+ FB13
+ Filter bits
+ 13
+ 1
+
+
+ FB14
+ Filter bits
+ 14
+ 1
+
+
+ FB15
+ Filter bits
+ 15
+ 1
+
+
+ FB16
+ Filter bits
+ 16
+ 1
+
+
+ FB17
+ Filter bits
+ 17
+ 1
+
+
+ FB18
+ Filter bits
+ 18
+ 1
+
+
+ FB19
+ Filter bits
+ 19
+ 1
+
+
+ FB20
+ Filter bits
+ 20
+ 1
+
+
+ FB21
+ Filter bits
+ 21
+ 1
+
+
+ FB22
+ Filter bits
+ 22
+ 1
+
+
+ FB23
+ Filter bits
+ 23
+ 1
+
+
+ FB24
+ Filter bits
+ 24
+ 1
+
+
+ FB25
+ Filter bits
+ 25
+ 1
+
+
+ FB26
+ Filter bits
+ 26
+ 1
+
+
+ FB27
+ Filter bits
+ 27
+ 1
+
+
+ FB28
+ Filter bits
+ 28
+ 1
+
+
+ FB29
+ Filter bits
+ 29
+ 1
+
+
+ FB30
+ Filter bits
+ 30
+ 1
+
+
+ FB31
+ Filter bits
+ 31
+ 1
+
+
+
+
+ F7R1
+ F7R1
+ Filter bank 7 register 1
+ 0x278
+ 0x20
+ read-write
+ 0x00000000
+
+
+ FB0
+ Filter bits
+ 0
+ 1
+
+
+ FB1
+ Filter bits
+ 1
+ 1
+
+
+ FB2
+ Filter bits
+ 2
+ 1
+
+
+ FB3
+ Filter bits
+ 3
+ 1
+
+
+ FB4
+ Filter bits
+ 4
+ 1
+
+
+ FB5
+ Filter bits
+ 5
+ 1
+
+
+ FB6
+ Filter bits
+ 6
+ 1
+
+
+ FB7
+ Filter bits
+ 7
+ 1
+
+
+ FB8
+ Filter bits
+ 8
+ 1
+
+
+ FB9
+ Filter bits
+ 9
+ 1
+
+
+ FB10
+ Filter bits
+ 10
+ 1
+
+
+ FB11
+ Filter bits
+ 11
+ 1
+
+
+ FB12
+ Filter bits
+ 12
+ 1
+
+
+ FB13
+ Filter bits
+ 13
+ 1
+
+
+ FB14
+ Filter bits
+ 14
+ 1
+
+
+ FB15
+ Filter bits
+ 15
+ 1
+
+
+ FB16
+ Filter bits
+ 16
+ 1
+
+
+ FB17
+ Filter bits
+ 17
+ 1
+
+
+ FB18
+ Filter bits
+ 18
+ 1
+
+
+ FB19
+ Filter bits
+ 19
+ 1
+
+
+ FB20
+ Filter bits
+ 20
+ 1
+
+
+ FB21
+ Filter bits
+ 21
+ 1
+
+
+ FB22
+ Filter bits
+ 22
+ 1
+
+
+ FB23
+ Filter bits
+ 23
+ 1
+
+
+ FB24
+ Filter bits
+ 24
+ 1
+
+
+ FB25
+ Filter bits
+ 25
+ 1
+
+
+ FB26
+ Filter bits
+ 26
+ 1
+
+
+ FB27
+ Filter bits
+ 27
+ 1
+
+
+ FB28
+ Filter bits
+ 28
+ 1
+
+
+ FB29
+ Filter bits
+ 29
+ 1
+
+
+ FB30
+ Filter bits
+ 30
+ 1
+
+
+ FB31
+ Filter bits
+ 31
+ 1
+
+
+
+
+ F7R2
+ F7R2
+ Filter bank 7 register 2
+ 0x27C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ FB0
+ Filter bits
+ 0
+ 1
+
+
+ FB1
+ Filter bits
+ 1
+ 1
+
+
+ FB2
+ Filter bits
+ 2
+ 1
+
+
+ FB3
+ Filter bits
+ 3
+ 1
+
+
+ FB4
+ Filter bits
+ 4
+ 1
+
+
+ FB5
+ Filter bits
+ 5
+ 1
+
+
+ FB6
+ Filter bits
+ 6
+ 1
+
+
+ FB7
+ Filter bits
+ 7
+ 1
+
+
+ FB8
+ Filter bits
+ 8
+ 1
+
+
+ FB9
+ Filter bits
+ 9
+ 1
+
+
+ FB10
+ Filter bits
+ 10
+ 1
+
+
+ FB11
+ Filter bits
+ 11
+ 1
+
+
+ FB12
+ Filter bits
+ 12
+ 1
+
+
+ FB13
+ Filter bits
+ 13
+ 1
+
+
+ FB14
+ Filter bits
+ 14
+ 1
+
+
+ FB15
+ Filter bits
+ 15
+ 1
+
+
+ FB16
+ Filter bits
+ 16
+ 1
+
+
+ FB17
+ Filter bits
+ 17
+ 1
+
+
+ FB18
+ Filter bits
+ 18
+ 1
+
+
+ FB19
+ Filter bits
+ 19
+ 1
+
+
+ FB20
+ Filter bits
+ 20
+ 1
+
+
+ FB21
+ Filter bits
+ 21
+ 1
+
+
+ FB22
+ Filter bits
+ 22
+ 1
+
+
+ FB23
+ Filter bits
+ 23
+ 1
+
+
+ FB24
+ Filter bits
+ 24
+ 1
+
+
+ FB25
+ Filter bits
+ 25
+ 1
+
+
+ FB26
+ Filter bits
+ 26
+ 1
+
+
+ FB27
+ Filter bits
+ 27
+ 1
+
+
+ FB28
+ Filter bits
+ 28
+ 1
+
+
+ FB29
+ Filter bits
+ 29
+ 1
+
+
+ FB30
+ Filter bits
+ 30
+ 1
+
+
+ FB31
+ Filter bits
+ 31
+ 1
+
+
+
+
+ F8R1
+ F8R1
+ Filter bank 8 register 1
+ 0x280
+ 0x20
+ read-write
+ 0x00000000
+
+
+ FB0
+ Filter bits
+ 0
+ 1
+
+
+ FB1
+ Filter bits
+ 1
+ 1
+
+
+ FB2
+ Filter bits
+ 2
+ 1
+
+
+ FB3
+ Filter bits
+ 3
+ 1
+
+
+ FB4
+ Filter bits
+ 4
+ 1
+
+
+ FB5
+ Filter bits
+ 5
+ 1
+
+
+ FB6
+ Filter bits
+ 6
+ 1
+
+
+ FB7
+ Filter bits
+ 7
+ 1
+
+
+ FB8
+ Filter bits
+ 8
+ 1
+
+
+ FB9
+ Filter bits
+ 9
+ 1
+
+
+ FB10
+ Filter bits
+ 10
+ 1
+
+
+ FB11
+ Filter bits
+ 11
+ 1
+
+
+ FB12
+ Filter bits
+ 12
+ 1
+
+
+ FB13
+ Filter bits
+ 13
+ 1
+
+
+ FB14
+ Filter bits
+ 14
+ 1
+
+
+ FB15
+ Filter bits
+ 15
+ 1
+
+
+ FB16
+ Filter bits
+ 16
+ 1
+
+
+ FB17
+ Filter bits
+ 17
+ 1
+
+
+ FB18
+ Filter bits
+ 18
+ 1
+
+
+ FB19
+ Filter bits
+ 19
+ 1
+
+
+ FB20
+ Filter bits
+ 20
+ 1
+
+
+ FB21
+ Filter bits
+ 21
+ 1
+
+
+ FB22
+ Filter bits
+ 22
+ 1
+
+
+ FB23
+ Filter bits
+ 23
+ 1
+
+
+ FB24
+ Filter bits
+ 24
+ 1
+
+
+ FB25
+ Filter bits
+ 25
+ 1
+
+
+ FB26
+ Filter bits
+ 26
+ 1
+
+
+ FB27
+ Filter bits
+ 27
+ 1
+
+
+ FB28
+ Filter bits
+ 28
+ 1
+
+
+ FB29
+ Filter bits
+ 29
+ 1
+
+
+ FB30
+ Filter bits
+ 30
+ 1
+
+
+ FB31
+ Filter bits
+ 31
+ 1
+
+
+
+
+ F8R2
+ F8R2
+ Filter bank 8 register 2
+ 0x284
+ 0x20
+ read-write
+ 0x00000000
+
+
+ FB0
+ Filter bits
+ 0
+ 1
+
+
+ FB1
+ Filter bits
+ 1
+ 1
+
+
+ FB2
+ Filter bits
+ 2
+ 1
+
+
+ FB3
+ Filter bits
+ 3
+ 1
+
+
+ FB4
+ Filter bits
+ 4
+ 1
+
+
+ FB5
+ Filter bits
+ 5
+ 1
+
+
+ FB6
+ Filter bits
+ 6
+ 1
+
+
+ FB7
+ Filter bits
+ 7
+ 1
+
+
+ FB8
+ Filter bits
+ 8
+ 1
+
+
+ FB9
+ Filter bits
+ 9
+ 1
+
+
+ FB10
+ Filter bits
+ 10
+ 1
+
+
+ FB11
+ Filter bits
+ 11
+ 1
+
+
+ FB12
+ Filter bits
+ 12
+ 1
+
+
+ FB13
+ Filter bits
+ 13
+ 1
+
+
+ FB14
+ Filter bits
+ 14
+ 1
+
+
+ FB15
+ Filter bits
+ 15
+ 1
+
+
+ FB16
+ Filter bits
+ 16
+ 1
+
+
+ FB17
+ Filter bits
+ 17
+ 1
+
+
+ FB18
+ Filter bits
+ 18
+ 1
+
+
+ FB19
+ Filter bits
+ 19
+ 1
+
+
+ FB20
+ Filter bits
+ 20
+ 1
+
+
+ FB21
+ Filter bits
+ 21
+ 1
+
+
+ FB22
+ Filter bits
+ 22
+ 1
+
+
+ FB23
+ Filter bits
+ 23
+ 1
+
+
+ FB24
+ Filter bits
+ 24
+ 1
+
+
+ FB25
+ Filter bits
+ 25
+ 1
+
+
+ FB26
+ Filter bits
+ 26
+ 1
+
+
+ FB27
+ Filter bits
+ 27
+ 1
+
+
+ FB28
+ Filter bits
+ 28
+ 1
+
+
+ FB29
+ Filter bits
+ 29
+ 1
+
+
+ FB30
+ Filter bits
+ 30
+ 1
+
+
+ FB31
+ Filter bits
+ 31
+ 1
+
+
+
+
+ F9R1
+ F9R1
+ Filter bank 9 register 1
+ 0x288
+ 0x20
+ read-write
+ 0x00000000
+
+
+ FB0
+ Filter bits
+ 0
+ 1
+
+
+ FB1
+ Filter bits
+ 1
+ 1
+
+
+ FB2
+ Filter bits
+ 2
+ 1
+
+
+ FB3
+ Filter bits
+ 3
+ 1
+
+
+ FB4
+ Filter bits
+ 4
+ 1
+
+
+ FB5
+ Filter bits
+ 5
+ 1
+
+
+ FB6
+ Filter bits
+ 6
+ 1
+
+
+ FB7
+ Filter bits
+ 7
+ 1
+
+
+ FB8
+ Filter bits
+ 8
+ 1
+
+
+ FB9
+ Filter bits
+ 9
+ 1
+
+
+ FB10
+ Filter bits
+ 10
+ 1
+
+
+ FB11
+ Filter bits
+ 11
+ 1
+
+
+ FB12
+ Filter bits
+ 12
+ 1
+
+
+ FB13
+ Filter bits
+ 13
+ 1
+
+
+ FB14
+ Filter bits
+ 14
+ 1
+
+
+ FB15
+ Filter bits
+ 15
+ 1
+
+
+ FB16
+ Filter bits
+ 16
+ 1
+
+
+ FB17
+ Filter bits
+ 17
+ 1
+
+
+ FB18
+ Filter bits
+ 18
+ 1
+
+
+ FB19
+ Filter bits
+ 19
+ 1
+
+
+ FB20
+ Filter bits
+ 20
+ 1
+
+
+ FB21
+ Filter bits
+ 21
+ 1
+
+
+ FB22
+ Filter bits
+ 22
+ 1
+
+
+ FB23
+ Filter bits
+ 23
+ 1
+
+
+ FB24
+ Filter bits
+ 24
+ 1
+
+
+ FB25
+ Filter bits
+ 25
+ 1
+
+
+ FB26
+ Filter bits
+ 26
+ 1
+
+
+ FB27
+ Filter bits
+ 27
+ 1
+
+
+ FB28
+ Filter bits
+ 28
+ 1
+
+
+ FB29
+ Filter bits
+ 29
+ 1
+
+
+ FB30
+ Filter bits
+ 30
+ 1
+
+
+ FB31
+ Filter bits
+ 31
+ 1
+
+
+
+
+ F9R2
+ F9R2
+ Filter bank 9 register 2
+ 0x28C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ FB0
+ Filter bits
+ 0
+ 1
+
+
+ FB1
+ Filter bits
+ 1
+ 1
+
+
+ FB2
+ Filter bits
+ 2
+ 1
+
+
+ FB3
+ Filter bits
+ 3
+ 1
+
+
+ FB4
+ Filter bits
+ 4
+ 1
+
+
+ FB5
+ Filter bits
+ 5
+ 1
+
+
+ FB6
+ Filter bits
+ 6
+ 1
+
+
+ FB7
+ Filter bits
+ 7
+ 1
+
+
+ FB8
+ Filter bits
+ 8
+ 1
+
+
+ FB9
+ Filter bits
+ 9
+ 1
+
+
+ FB10
+ Filter bits
+ 10
+ 1
+
+
+ FB11
+ Filter bits
+ 11
+ 1
+
+
+ FB12
+ Filter bits
+ 12
+ 1
+
+
+ FB13
+ Filter bits
+ 13
+ 1
+
+
+ FB14
+ Filter bits
+ 14
+ 1
+
+
+ FB15
+ Filter bits
+ 15
+ 1
+
+
+ FB16
+ Filter bits
+ 16
+ 1
+
+
+ FB17
+ Filter bits
+ 17
+ 1
+
+
+ FB18
+ Filter bits
+ 18
+ 1
+
+
+ FB19
+ Filter bits
+ 19
+ 1
+
+
+ FB20
+ Filter bits
+ 20
+ 1
+
+
+ FB21
+ Filter bits
+ 21
+ 1
+
+
+ FB22
+ Filter bits
+ 22
+ 1
+
+
+ FB23
+ Filter bits
+ 23
+ 1
+
+
+ FB24
+ Filter bits
+ 24
+ 1
+
+
+ FB25
+ Filter bits
+ 25
+ 1
+
+
+ FB26
+ Filter bits
+ 26
+ 1
+
+
+ FB27
+ Filter bits
+ 27
+ 1
+
+
+ FB28
+ Filter bits
+ 28
+ 1
+
+
+ FB29
+ Filter bits
+ 29
+ 1
+
+
+ FB30
+ Filter bits
+ 30
+ 1
+
+
+ FB31
+ Filter bits
+ 31
+ 1
+
+
+
+
+ F10R1
+ F10R1
+ Filter bank 10 register 1
+ 0x290
+ 0x20
+ read-write
+ 0x00000000
+
+
+ FB0
+ Filter bits
+ 0
+ 1
+
+
+ FB1
+ Filter bits
+ 1
+ 1
+
+
+ FB2
+ Filter bits
+ 2
+ 1
+
+
+ FB3
+ Filter bits
+ 3
+ 1
+
+
+ FB4
+ Filter bits
+ 4
+ 1
+
+
+ FB5
+ Filter bits
+ 5
+ 1
+
+
+ FB6
+ Filter bits
+ 6
+ 1
+
+
+ FB7
+ Filter bits
+ 7
+ 1
+
+
+ FB8
+ Filter bits
+ 8
+ 1
+
+
+ FB9
+ Filter bits
+ 9
+ 1
+
+
+ FB10
+ Filter bits
+ 10
+ 1
+
+
+ FB11
+ Filter bits
+ 11
+ 1
+
+
+ FB12
+ Filter bits
+ 12
+ 1
+
+
+ FB13
+ Filter bits
+ 13
+ 1
+
+
+ FB14
+ Filter bits
+ 14
+ 1
+
+
+ FB15
+ Filter bits
+ 15
+ 1
+
+
+ FB16
+ Filter bits
+ 16
+ 1
+
+
+ FB17
+ Filter bits
+ 17
+ 1
+
+
+ FB18
+ Filter bits
+ 18
+ 1
+
+
+ FB19
+ Filter bits
+ 19
+ 1
+
+
+ FB20
+ Filter bits
+ 20
+ 1
+
+
+ FB21
+ Filter bits
+ 21
+ 1
+
+
+ FB22
+ Filter bits
+ 22
+ 1
+
+
+ FB23
+ Filter bits
+ 23
+ 1
+
+
+ FB24
+ Filter bits
+ 24
+ 1
+
+
+ FB25
+ Filter bits
+ 25
+ 1
+
+
+ FB26
+ Filter bits
+ 26
+ 1
+
+
+ FB27
+ Filter bits
+ 27
+ 1
+
+
+ FB28
+ Filter bits
+ 28
+ 1
+
+
+ FB29
+ Filter bits
+ 29
+ 1
+
+
+ FB30
+ Filter bits
+ 30
+ 1
+
+
+ FB31
+ Filter bits
+ 31
+ 1
+
+
+
+
+ F10R2
+ F10R2
+ Filter bank 10 register 2
+ 0x294
+ 0x20
+ read-write
+ 0x00000000
+
+
+ FB0
+ Filter bits
+ 0
+ 1
+
+
+ FB1
+ Filter bits
+ 1
+ 1
+
+
+ FB2
+ Filter bits
+ 2
+ 1
+
+
+ FB3
+ Filter bits
+ 3
+ 1
+
+
+ FB4
+ Filter bits
+ 4
+ 1
+
+
+ FB5
+ Filter bits
+ 5
+ 1
+
+
+ FB6
+ Filter bits
+ 6
+ 1
+
+
+ FB7
+ Filter bits
+ 7
+ 1
+
+
+ FB8
+ Filter bits
+ 8
+ 1
+
+
+ FB9
+ Filter bits
+ 9
+ 1
+
+
+ FB10
+ Filter bits
+ 10
+ 1
+
+
+ FB11
+ Filter bits
+ 11
+ 1
+
+
+ FB12
+ Filter bits
+ 12
+ 1
+
+
+ FB13
+ Filter bits
+ 13
+ 1
+
+
+ FB14
+ Filter bits
+ 14
+ 1
+
+
+ FB15
+ Filter bits
+ 15
+ 1
+
+
+ FB16
+ Filter bits
+ 16
+ 1
+
+
+ FB17
+ Filter bits
+ 17
+ 1
+
+
+ FB18
+ Filter bits
+ 18
+ 1
+
+
+ FB19
+ Filter bits
+ 19
+ 1
+
+
+ FB20
+ Filter bits
+ 20
+ 1
+
+
+ FB21
+ Filter bits
+ 21
+ 1
+
+
+ FB22
+ Filter bits
+ 22
+ 1
+
+
+ FB23
+ Filter bits
+ 23
+ 1
+
+
+ FB24
+ Filter bits
+ 24
+ 1
+
+
+ FB25
+ Filter bits
+ 25
+ 1
+
+
+ FB26
+ Filter bits
+ 26
+ 1
+
+
+ FB27
+ Filter bits
+ 27
+ 1
+
+
+ FB28
+ Filter bits
+ 28
+ 1
+
+
+ FB29
+ Filter bits
+ 29
+ 1
+
+
+ FB30
+ Filter bits
+ 30
+ 1
+
+
+ FB31
+ Filter bits
+ 31
+ 1
+
+
+
+
+ F11R1
+ F11R1
+ Filter bank 11 register 1
+ 0x298
+ 0x20
+ read-write
+ 0x00000000
+
+
+ FB0
+ Filter bits
+ 0
+ 1
+
+
+ FB1
+ Filter bits
+ 1
+ 1
+
+
+ FB2
+ Filter bits
+ 2
+ 1
+
+
+ FB3
+ Filter bits
+ 3
+ 1
+
+
+ FB4
+ Filter bits
+ 4
+ 1
+
+
+ FB5
+ Filter bits
+ 5
+ 1
+
+
+ FB6
+ Filter bits
+ 6
+ 1
+
+
+ FB7
+ Filter bits
+ 7
+ 1
+
+
+ FB8
+ Filter bits
+ 8
+ 1
+
+
+ FB9
+ Filter bits
+ 9
+ 1
+
+
+ FB10
+ Filter bits
+ 10
+ 1
+
+
+ FB11
+ Filter bits
+ 11
+ 1
+
+
+ FB12
+ Filter bits
+ 12
+ 1
+
+
+ FB13
+ Filter bits
+ 13
+ 1
+
+
+ FB14
+ Filter bits
+ 14
+ 1
+
+
+ FB15
+ Filter bits
+ 15
+ 1
+
+
+ FB16
+ Filter bits
+ 16
+ 1
+
+
+ FB17
+ Filter bits
+ 17
+ 1
+
+
+ FB18
+ Filter bits
+ 18
+ 1
+
+
+ FB19
+ Filter bits
+ 19
+ 1
+
+
+ FB20
+ Filter bits
+ 20
+ 1
+
+
+ FB21
+ Filter bits
+ 21
+ 1
+
+
+ FB22
+ Filter bits
+ 22
+ 1
+
+
+ FB23
+ Filter bits
+ 23
+ 1
+
+
+ FB24
+ Filter bits
+ 24
+ 1
+
+
+ FB25
+ Filter bits
+ 25
+ 1
+
+
+ FB26
+ Filter bits
+ 26
+ 1
+
+
+ FB27
+ Filter bits
+ 27
+ 1
+
+
+ FB28
+ Filter bits
+ 28
+ 1
+
+
+ FB29
+ Filter bits
+ 29
+ 1
+
+
+ FB30
+ Filter bits
+ 30
+ 1
+
+
+ FB31
+ Filter bits
+ 31
+ 1
+
+
+
+
+ F11R2
+ F11R2
+ Filter bank 11 register 2
+ 0x29C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ FB0
+ Filter bits
+ 0
+ 1
+
+
+ FB1
+ Filter bits
+ 1
+ 1
+
+
+ FB2
+ Filter bits
+ 2
+ 1
+
+
+ FB3
+ Filter bits
+ 3
+ 1
+
+
+ FB4
+ Filter bits
+ 4
+ 1
+
+
+ FB5
+ Filter bits
+ 5
+ 1
+
+
+ FB6
+ Filter bits
+ 6
+ 1
+
+
+ FB7
+ Filter bits
+ 7
+ 1
+
+
+ FB8
+ Filter bits
+ 8
+ 1
+
+
+ FB9
+ Filter bits
+ 9
+ 1
+
+
+ FB10
+ Filter bits
+ 10
+ 1
+
+
+ FB11
+ Filter bits
+ 11
+ 1
+
+
+ FB12
+ Filter bits
+ 12
+ 1
+
+
+ FB13
+ Filter bits
+ 13
+ 1
+
+
+ FB14
+ Filter bits
+ 14
+ 1
+
+
+ FB15
+ Filter bits
+ 15
+ 1
+
+
+ FB16
+ Filter bits
+ 16
+ 1
+
+
+ FB17
+ Filter bits
+ 17
+ 1
+
+
+ FB18
+ Filter bits
+ 18
+ 1
+
+
+ FB19
+ Filter bits
+ 19
+ 1
+
+
+ FB20
+ Filter bits
+ 20
+ 1
+
+
+ FB21
+ Filter bits
+ 21
+ 1
+
+
+ FB22
+ Filter bits
+ 22
+ 1
+
+
+ FB23
+ Filter bits
+ 23
+ 1
+
+
+ FB24
+ Filter bits
+ 24
+ 1
+
+
+ FB25
+ Filter bits
+ 25
+ 1
+
+
+ FB26
+ Filter bits
+ 26
+ 1
+
+
+ FB27
+ Filter bits
+ 27
+ 1
+
+
+ FB28
+ Filter bits
+ 28
+ 1
+
+
+ FB29
+ Filter bits
+ 29
+ 1
+
+
+ FB30
+ Filter bits
+ 30
+ 1
+
+
+ FB31
+ Filter bits
+ 31
+ 1
+
+
+
+
+ F12R1
+ F12R1
+ Filter bank 4 register 1
+ 0x2A0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ FB0
+ Filter bits
+ 0
+ 1
+
+
+ FB1
+ Filter bits
+ 1
+ 1
+
+
+ FB2
+ Filter bits
+ 2
+ 1
+
+
+ FB3
+ Filter bits
+ 3
+ 1
+
+
+ FB4
+ Filter bits
+ 4
+ 1
+
+
+ FB5
+ Filter bits
+ 5
+ 1
+
+
+ FB6
+ Filter bits
+ 6
+ 1
+
+
+ FB7
+ Filter bits
+ 7
+ 1
+
+
+ FB8
+ Filter bits
+ 8
+ 1
+
+
+ FB9
+ Filter bits
+ 9
+ 1
+
+
+ FB10
+ Filter bits
+ 10
+ 1
+
+
+ FB11
+ Filter bits
+ 11
+ 1
+
+
+ FB12
+ Filter bits
+ 12
+ 1
+
+
+ FB13
+ Filter bits
+ 13
+ 1
+
+
+ FB14
+ Filter bits
+ 14
+ 1
+
+
+ FB15
+ Filter bits
+ 15
+ 1
+
+
+ FB16
+ Filter bits
+ 16
+ 1
+
+
+ FB17
+ Filter bits
+ 17
+ 1
+
+
+ FB18
+ Filter bits
+ 18
+ 1
+
+
+ FB19
+ Filter bits
+ 19
+ 1
+
+
+ FB20
+ Filter bits
+ 20
+ 1
+
+
+ FB21
+ Filter bits
+ 21
+ 1
+
+
+ FB22
+ Filter bits
+ 22
+ 1
+
+
+ FB23
+ Filter bits
+ 23
+ 1
+
+
+ FB24
+ Filter bits
+ 24
+ 1
+
+
+ FB25
+ Filter bits
+ 25
+ 1
+
+
+ FB26
+ Filter bits
+ 26
+ 1
+
+
+ FB27
+ Filter bits
+ 27
+ 1
+
+
+ FB28
+ Filter bits
+ 28
+ 1
+
+
+ FB29
+ Filter bits
+ 29
+ 1
+
+
+ FB30
+ Filter bits
+ 30
+ 1
+
+
+ FB31
+ Filter bits
+ 31
+ 1
+
+
+
+
+ F12R2
+ F12R2
+ Filter bank 12 register 2
+ 0x2A4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ FB0
+ Filter bits
+ 0
+ 1
+
+
+ FB1
+ Filter bits
+ 1
+ 1
+
+
+ FB2
+ Filter bits
+ 2
+ 1
+
+
+ FB3
+ Filter bits
+ 3
+ 1
+
+
+ FB4
+ Filter bits
+ 4
+ 1
+
+
+ FB5
+ Filter bits
+ 5
+ 1
+
+
+ FB6
+ Filter bits
+ 6
+ 1
+
+
+ FB7
+ Filter bits
+ 7
+ 1
+
+
+ FB8
+ Filter bits
+ 8
+ 1
+
+
+ FB9
+ Filter bits
+ 9
+ 1
+
+
+ FB10
+ Filter bits
+ 10
+ 1
+
+
+ FB11
+ Filter bits
+ 11
+ 1
+
+
+ FB12
+ Filter bits
+ 12
+ 1
+
+
+ FB13
+ Filter bits
+ 13
+ 1
+
+
+ FB14
+ Filter bits
+ 14
+ 1
+
+
+ FB15
+ Filter bits
+ 15
+ 1
+
+
+ FB16
+ Filter bits
+ 16
+ 1
+
+
+ FB17
+ Filter bits
+ 17
+ 1
+
+
+ FB18
+ Filter bits
+ 18
+ 1
+
+
+ FB19
+ Filter bits
+ 19
+ 1
+
+
+ FB20
+ Filter bits
+ 20
+ 1
+
+
+ FB21
+ Filter bits
+ 21
+ 1
+
+
+ FB22
+ Filter bits
+ 22
+ 1
+
+
+ FB23
+ Filter bits
+ 23
+ 1
+
+
+ FB24
+ Filter bits
+ 24
+ 1
+
+
+ FB25
+ Filter bits
+ 25
+ 1
+
+
+ FB26
+ Filter bits
+ 26
+ 1
+
+
+ FB27
+ Filter bits
+ 27
+ 1
+
+
+ FB28
+ Filter bits
+ 28
+ 1
+
+
+ FB29
+ Filter bits
+ 29
+ 1
+
+
+ FB30
+ Filter bits
+ 30
+ 1
+
+
+ FB31
+ Filter bits
+ 31
+ 1
+
+
+
+
+ F13R1
+ F13R1
+ Filter bank 13 register 1
+ 0x2A8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ FB0
+ Filter bits
+ 0
+ 1
+
+
+ FB1
+ Filter bits
+ 1
+ 1
+
+
+ FB2
+ Filter bits
+ 2
+ 1
+
+
+ FB3
+ Filter bits
+ 3
+ 1
+
+
+ FB4
+ Filter bits
+ 4
+ 1
+
+
+ FB5
+ Filter bits
+ 5
+ 1
+
+
+ FB6
+ Filter bits
+ 6
+ 1
+
+
+ FB7
+ Filter bits
+ 7
+ 1
+
+
+ FB8
+ Filter bits
+ 8
+ 1
+
+
+ FB9
+ Filter bits
+ 9
+ 1
+
+
+ FB10
+ Filter bits
+ 10
+ 1
+
+
+ FB11
+ Filter bits
+ 11
+ 1
+
+
+ FB12
+ Filter bits
+ 12
+ 1
+
+
+ FB13
+ Filter bits
+ 13
+ 1
+
+
+ FB14
+ Filter bits
+ 14
+ 1
+
+
+ FB15
+ Filter bits
+ 15
+ 1
+
+
+ FB16
+ Filter bits
+ 16
+ 1
+
+
+ FB17
+ Filter bits
+ 17
+ 1
+
+
+ FB18
+ Filter bits
+ 18
+ 1
+
+
+ FB19
+ Filter bits
+ 19
+ 1
+
+
+ FB20
+ Filter bits
+ 20
+ 1
+
+
+ FB21
+ Filter bits
+ 21
+ 1
+
+
+ FB22
+ Filter bits
+ 22
+ 1
+
+
+ FB23
+ Filter bits
+ 23
+ 1
+
+
+ FB24
+ Filter bits
+ 24
+ 1
+
+
+ FB25
+ Filter bits
+ 25
+ 1
+
+
+ FB26
+ Filter bits
+ 26
+ 1
+
+
+ FB27
+ Filter bits
+ 27
+ 1
+
+
+ FB28
+ Filter bits
+ 28
+ 1
+
+
+ FB29
+ Filter bits
+ 29
+ 1
+
+
+ FB30
+ Filter bits
+ 30
+ 1
+
+
+ FB31
+ Filter bits
+ 31
+ 1
+
+
+
+
+ F13R2
+ F13R2
+ Filter bank 13 register 2
+ 0x2AC
+ 0x20
+ read-write
+ 0x00000000
+
+
+ FB0
+ Filter bits
+ 0
+ 1
+
+
+ FB1
+ Filter bits
+ 1
+ 1
+
+
+ FB2
+ Filter bits
+ 2
+ 1
+
+
+ FB3
+ Filter bits
+ 3
+ 1
+
+
+ FB4
+ Filter bits
+ 4
+ 1
+
+
+ FB5
+ Filter bits
+ 5
+ 1
+
+
+ FB6
+ Filter bits
+ 6
+ 1
+
+
+ FB7
+ Filter bits
+ 7
+ 1
+
+
+ FB8
+ Filter bits
+ 8
+ 1
+
+
+ FB9
+ Filter bits
+ 9
+ 1
+
+
+ FB10
+ Filter bits
+ 10
+ 1
+
+
+ FB11
+ Filter bits
+ 11
+ 1
+
+
+ FB12
+ Filter bits
+ 12
+ 1
+
+
+ FB13
+ Filter bits
+ 13
+ 1
+
+
+ FB14
+ Filter bits
+ 14
+ 1
+
+
+ FB15
+ Filter bits
+ 15
+ 1
+
+
+ FB16
+ Filter bits
+ 16
+ 1
+
+
+ FB17
+ Filter bits
+ 17
+ 1
+
+
+ FB18
+ Filter bits
+ 18
+ 1
+
+
+ FB19
+ Filter bits
+ 19
+ 1
+
+
+ FB20
+ Filter bits
+ 20
+ 1
+
+
+ FB21
+ Filter bits
+ 21
+ 1
+
+
+ FB22
+ Filter bits
+ 22
+ 1
+
+
+ FB23
+ Filter bits
+ 23
+ 1
+
+
+ FB24
+ Filter bits
+ 24
+ 1
+
+
+ FB25
+ Filter bits
+ 25
+ 1
+
+
+ FB26
+ Filter bits
+ 26
+ 1
+
+
+ FB27
+ Filter bits
+ 27
+ 1
+
+
+ FB28
+ Filter bits
+ 28
+ 1
+
+
+ FB29
+ Filter bits
+ 29
+ 1
+
+
+ FB30
+ Filter bits
+ 30
+ 1
+
+
+ FB31
+ Filter bits
+ 31
+ 1
+
+
+
+
+ F14R1
+ F14R1
+ Filter bank 14 register 1
+ 0x2B0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ FB0
+ Filter bits
+ 0
+ 1
+
+
+ FB1
+ Filter bits
+ 1
+ 1
+
+
+ FB2
+ Filter bits
+ 2
+ 1
+
+
+ FB3
+ Filter bits
+ 3
+ 1
+
+
+ FB4
+ Filter bits
+ 4
+ 1
+
+
+ FB5
+ Filter bits
+ 5
+ 1
+
+
+ FB6
+ Filter bits
+ 6
+ 1
+
+
+ FB7
+ Filter bits
+ 7
+ 1
+
+
+ FB8
+ Filter bits
+ 8
+ 1
+
+
+ FB9
+ Filter bits
+ 9
+ 1
+
+
+ FB10
+ Filter bits
+ 10
+ 1
+
+
+ FB11
+ Filter bits
+ 11
+ 1
+
+
+ FB12
+ Filter bits
+ 12
+ 1
+
+
+ FB13
+ Filter bits
+ 13
+ 1
+
+
+ FB14
+ Filter bits
+ 14
+ 1
+
+
+ FB15
+ Filter bits
+ 15
+ 1
+
+
+ FB16
+ Filter bits
+ 16
+ 1
+
+
+ FB17
+ Filter bits
+ 17
+ 1
+
+
+ FB18
+ Filter bits
+ 18
+ 1
+
+
+ FB19
+ Filter bits
+ 19
+ 1
+
+
+ FB20
+ Filter bits
+ 20
+ 1
+
+
+ FB21
+ Filter bits
+ 21
+ 1
+
+
+ FB22
+ Filter bits
+ 22
+ 1
+
+
+ FB23
+ Filter bits
+ 23
+ 1
+
+
+ FB24
+ Filter bits
+ 24
+ 1
+
+
+ FB25
+ Filter bits
+ 25
+ 1
+
+
+ FB26
+ Filter bits
+ 26
+ 1
+
+
+ FB27
+ Filter bits
+ 27
+ 1
+
+
+ FB28
+ Filter bits
+ 28
+ 1
+
+
+ FB29
+ Filter bits
+ 29
+ 1
+
+
+ FB30
+ Filter bits
+ 30
+ 1
+
+
+ FB31
+ Filter bits
+ 31
+ 1
+
+
+
+
+ F14R2
+ F14R2
+ Filter bank 14 register 2
+ 0x2B4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ FB0
+ Filter bits
+ 0
+ 1
+
+
+ FB1
+ Filter bits
+ 1
+ 1
+
+
+ FB2
+ Filter bits
+ 2
+ 1
+
+
+ FB3
+ Filter bits
+ 3
+ 1
+
+
+ FB4
+ Filter bits
+ 4
+ 1
+
+
+ FB5
+ Filter bits
+ 5
+ 1
+
+
+ FB6
+ Filter bits
+ 6
+ 1
+
+
+ FB7
+ Filter bits
+ 7
+ 1
+
+
+ FB8
+ Filter bits
+ 8
+ 1
+
+
+ FB9
+ Filter bits
+ 9
+ 1
+
+
+ FB10
+ Filter bits
+ 10
+ 1
+
+
+ FB11
+ Filter bits
+ 11
+ 1
+
+
+ FB12
+ Filter bits
+ 12
+ 1
+
+
+ FB13
+ Filter bits
+ 13
+ 1
+
+
+ FB14
+ Filter bits
+ 14
+ 1
+
+
+ FB15
+ Filter bits
+ 15
+ 1
+
+
+ FB16
+ Filter bits
+ 16
+ 1
+
+
+ FB17
+ Filter bits
+ 17
+ 1
+
+
+ FB18
+ Filter bits
+ 18
+ 1
+
+
+ FB19
+ Filter bits
+ 19
+ 1
+
+
+ FB20
+ Filter bits
+ 20
+ 1
+
+
+ FB21
+ Filter bits
+ 21
+ 1
+
+
+ FB22
+ Filter bits
+ 22
+ 1
+
+
+ FB23
+ Filter bits
+ 23
+ 1
+
+
+ FB24
+ Filter bits
+ 24
+ 1
+
+
+ FB25
+ Filter bits
+ 25
+ 1
+
+
+ FB26
+ Filter bits
+ 26
+ 1
+
+
+ FB27
+ Filter bits
+ 27
+ 1
+
+
+ FB28
+ Filter bits
+ 28
+ 1
+
+
+ FB29
+ Filter bits
+ 29
+ 1
+
+
+ FB30
+ Filter bits
+ 30
+ 1
+
+
+ FB31
+ Filter bits
+ 31
+ 1
+
+
+
+
+ F15R1
+ F15R1
+ Filter bank 15 register 1
+ 0x2B8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ FB0
+ Filter bits
+ 0
+ 1
+
+
+ FB1
+ Filter bits
+ 1
+ 1
+
+
+ FB2
+ Filter bits
+ 2
+ 1
+
+
+ FB3
+ Filter bits
+ 3
+ 1
+
+
+ FB4
+ Filter bits
+ 4
+ 1
+
+
+ FB5
+ Filter bits
+ 5
+ 1
+
+
+ FB6
+ Filter bits
+ 6
+ 1
+
+
+ FB7
+ Filter bits
+ 7
+ 1
+
+
+ FB8
+ Filter bits
+ 8
+ 1
+
+
+ FB9
+ Filter bits
+ 9
+ 1
+
+
+ FB10
+ Filter bits
+ 10
+ 1
+
+
+ FB11
+ Filter bits
+ 11
+ 1
+
+
+ FB12
+ Filter bits
+ 12
+ 1
+
+
+ FB13
+ Filter bits
+ 13
+ 1
+
+
+ FB14
+ Filter bits
+ 14
+ 1
+
+
+ FB15
+ Filter bits
+ 15
+ 1
+
+
+ FB16
+ Filter bits
+ 16
+ 1
+
+
+ FB17
+ Filter bits
+ 17
+ 1
+
+
+ FB18
+ Filter bits
+ 18
+ 1
+
+
+ FB19
+ Filter bits
+ 19
+ 1
+
+
+ FB20
+ Filter bits
+ 20
+ 1
+
+
+ FB21
+ Filter bits
+ 21
+ 1
+
+
+ FB22
+ Filter bits
+ 22
+ 1
+
+
+ FB23
+ Filter bits
+ 23
+ 1
+
+
+ FB24
+ Filter bits
+ 24
+ 1
+
+
+ FB25
+ Filter bits
+ 25
+ 1
+
+
+ FB26
+ Filter bits
+ 26
+ 1
+
+
+ FB27
+ Filter bits
+ 27
+ 1
+
+
+ FB28
+ Filter bits
+ 28
+ 1
+
+
+ FB29
+ Filter bits
+ 29
+ 1
+
+
+ FB30
+ Filter bits
+ 30
+ 1
+
+
+ FB31
+ Filter bits
+ 31
+ 1
+
+
+
+
+ F15R2
+ F15R2
+ Filter bank 15 register 2
+ 0x2BC
+ 0x20
+ read-write
+ 0x00000000
+
+
+ FB0
+ Filter bits
+ 0
+ 1
+
+
+ FB1
+ Filter bits
+ 1
+ 1
+
+
+ FB2
+ Filter bits
+ 2
+ 1
+
+
+ FB3
+ Filter bits
+ 3
+ 1
+
+
+ FB4
+ Filter bits
+ 4
+ 1
+
+
+ FB5
+ Filter bits
+ 5
+ 1
+
+
+ FB6
+ Filter bits
+ 6
+ 1
+
+
+ FB7
+ Filter bits
+ 7
+ 1
+
+
+ FB8
+ Filter bits
+ 8
+ 1
+
+
+ FB9
+ Filter bits
+ 9
+ 1
+
+
+ FB10
+ Filter bits
+ 10
+ 1
+
+
+ FB11
+ Filter bits
+ 11
+ 1
+
+
+ FB12
+ Filter bits
+ 12
+ 1
+
+
+ FB13
+ Filter bits
+ 13
+ 1
+
+
+ FB14
+ Filter bits
+ 14
+ 1
+
+
+ FB15
+ Filter bits
+ 15
+ 1
+
+
+ FB16
+ Filter bits
+ 16
+ 1
+
+
+ FB17
+ Filter bits
+ 17
+ 1
+
+
+ FB18
+ Filter bits
+ 18
+ 1
+
+
+ FB19
+ Filter bits
+ 19
+ 1
+
+
+ FB20
+ Filter bits
+ 20
+ 1
+
+
+ FB21
+ Filter bits
+ 21
+ 1
+
+
+ FB22
+ Filter bits
+ 22
+ 1
+
+
+ FB23
+ Filter bits
+ 23
+ 1
+
+
+ FB24
+ Filter bits
+ 24
+ 1
+
+
+ FB25
+ Filter bits
+ 25
+ 1
+
+
+ FB26
+ Filter bits
+ 26
+ 1
+
+
+ FB27
+ Filter bits
+ 27
+ 1
+
+
+ FB28
+ Filter bits
+ 28
+ 1
+
+
+ FB29
+ Filter bits
+ 29
+ 1
+
+
+ FB30
+ Filter bits
+ 30
+ 1
+
+
+ FB31
+ Filter bits
+ 31
+ 1
+
+
+
+
+ F16R1
+ F16R1
+ Filter bank 16 register 1
+ 0x2C0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ FB0
+ Filter bits
+ 0
+ 1
+
+
+ FB1
+ Filter bits
+ 1
+ 1
+
+
+ FB2
+ Filter bits
+ 2
+ 1
+
+
+ FB3
+ Filter bits
+ 3
+ 1
+
+
+ FB4
+ Filter bits
+ 4
+ 1
+
+
+ FB5
+ Filter bits
+ 5
+ 1
+
+
+ FB6
+ Filter bits
+ 6
+ 1
+
+
+ FB7
+ Filter bits
+ 7
+ 1
+
+
+ FB8
+ Filter bits
+ 8
+ 1
+
+
+ FB9
+ Filter bits
+ 9
+ 1
+
+
+ FB10
+ Filter bits
+ 10
+ 1
+
+
+ FB11
+ Filter bits
+ 11
+ 1
+
+
+ FB12
+ Filter bits
+ 12
+ 1
+
+
+ FB13
+ Filter bits
+ 13
+ 1
+
+
+ FB14
+ Filter bits
+ 14
+ 1
+
+
+ FB15
+ Filter bits
+ 15
+ 1
+
+
+ FB16
+ Filter bits
+ 16
+ 1
+
+
+ FB17
+ Filter bits
+ 17
+ 1
+
+
+ FB18
+ Filter bits
+ 18
+ 1
+
+
+ FB19
+ Filter bits
+ 19
+ 1
+
+
+ FB20
+ Filter bits
+ 20
+ 1
+
+
+ FB21
+ Filter bits
+ 21
+ 1
+
+
+ FB22
+ Filter bits
+ 22
+ 1
+
+
+ FB23
+ Filter bits
+ 23
+ 1
+
+
+ FB24
+ Filter bits
+ 24
+ 1
+
+
+ FB25
+ Filter bits
+ 25
+ 1
+
+
+ FB26
+ Filter bits
+ 26
+ 1
+
+
+ FB27
+ Filter bits
+ 27
+ 1
+
+
+ FB28
+ Filter bits
+ 28
+ 1
+
+
+ FB29
+ Filter bits
+ 29
+ 1
+
+
+ FB30
+ Filter bits
+ 30
+ 1
+
+
+ FB31
+ Filter bits
+ 31
+ 1
+
+
+
+
+ F16R2
+ F16R2
+ Filter bank 16 register 2
+ 0x2C4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ FB0
+ Filter bits
+ 0
+ 1
+
+
+ FB1
+ Filter bits
+ 1
+ 1
+
+
+ FB2
+ Filter bits
+ 2
+ 1
+
+
+ FB3
+ Filter bits
+ 3
+ 1
+
+
+ FB4
+ Filter bits
+ 4
+ 1
+
+
+ FB5
+ Filter bits
+ 5
+ 1
+
+
+ FB6
+ Filter bits
+ 6
+ 1
+
+
+ FB7
+ Filter bits
+ 7
+ 1
+
+
+ FB8
+ Filter bits
+ 8
+ 1
+
+
+ FB9
+ Filter bits
+ 9
+ 1
+
+
+ FB10
+ Filter bits
+ 10
+ 1
+
+
+ FB11
+ Filter bits
+ 11
+ 1
+
+
+ FB12
+ Filter bits
+ 12
+ 1
+
+
+ FB13
+ Filter bits
+ 13
+ 1
+
+
+ FB14
+ Filter bits
+ 14
+ 1
+
+
+ FB15
+ Filter bits
+ 15
+ 1
+
+
+ FB16
+ Filter bits
+ 16
+ 1
+
+
+ FB17
+ Filter bits
+ 17
+ 1
+
+
+ FB18
+ Filter bits
+ 18
+ 1
+
+
+ FB19
+ Filter bits
+ 19
+ 1
+
+
+ FB20
+ Filter bits
+ 20
+ 1
+
+
+ FB21
+ Filter bits
+ 21
+ 1
+
+
+ FB22
+ Filter bits
+ 22
+ 1
+
+
+ FB23
+ Filter bits
+ 23
+ 1
+
+
+ FB24
+ Filter bits
+ 24
+ 1
+
+
+ FB25
+ Filter bits
+ 25
+ 1
+
+
+ FB26
+ Filter bits
+ 26
+ 1
+
+
+ FB27
+ Filter bits
+ 27
+ 1
+
+
+ FB28
+ Filter bits
+ 28
+ 1
+
+
+ FB29
+ Filter bits
+ 29
+ 1
+
+
+ FB30
+ Filter bits
+ 30
+ 1
+
+
+ FB31
+ Filter bits
+ 31
+ 1
+
+
+
+
+ F17R1
+ F17R1
+ Filter bank 17 register 1
+ 0x2C8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ FB0
+ Filter bits
+ 0
+ 1
+
+
+ FB1
+ Filter bits
+ 1
+ 1
+
+
+ FB2
+ Filter bits
+ 2
+ 1
+
+
+ FB3
+ Filter bits
+ 3
+ 1
+
+
+ FB4
+ Filter bits
+ 4
+ 1
+
+
+ FB5
+ Filter bits
+ 5
+ 1
+
+
+ FB6
+ Filter bits
+ 6
+ 1
+
+
+ FB7
+ Filter bits
+ 7
+ 1
+
+
+ FB8
+ Filter bits
+ 8
+ 1
+
+
+ FB9
+ Filter bits
+ 9
+ 1
+
+
+ FB10
+ Filter bits
+ 10
+ 1
+
+
+ FB11
+ Filter bits
+ 11
+ 1
+
+
+ FB12
+ Filter bits
+ 12
+ 1
+
+
+ FB13
+ Filter bits
+ 13
+ 1
+
+
+ FB14
+ Filter bits
+ 14
+ 1
+
+
+ FB15
+ Filter bits
+ 15
+ 1
+
+
+ FB16
+ Filter bits
+ 16
+ 1
+
+
+ FB17
+ Filter bits
+ 17
+ 1
+
+
+ FB18
+ Filter bits
+ 18
+ 1
+
+
+ FB19
+ Filter bits
+ 19
+ 1
+
+
+ FB20
+ Filter bits
+ 20
+ 1
+
+
+ FB21
+ Filter bits
+ 21
+ 1
+
+
+ FB22
+ Filter bits
+ 22
+ 1
+
+
+ FB23
+ Filter bits
+ 23
+ 1
+
+
+ FB24
+ Filter bits
+ 24
+ 1
+
+
+ FB25
+ Filter bits
+ 25
+ 1
+
+
+ FB26
+ Filter bits
+ 26
+ 1
+
+
+ FB27
+ Filter bits
+ 27
+ 1
+
+
+ FB28
+ Filter bits
+ 28
+ 1
+
+
+ FB29
+ Filter bits
+ 29
+ 1
+
+
+ FB30
+ Filter bits
+ 30
+ 1
+
+
+ FB31
+ Filter bits
+ 31
+ 1
+
+
+
+
+ F17R2
+ F17R2
+ Filter bank 17 register 2
+ 0x2CC
+ 0x20
+ read-write
+ 0x00000000
+
+
+ FB0
+ Filter bits
+ 0
+ 1
+
+
+ FB1
+ Filter bits
+ 1
+ 1
+
+
+ FB2
+ Filter bits
+ 2
+ 1
+
+
+ FB3
+ Filter bits
+ 3
+ 1
+
+
+ FB4
+ Filter bits
+ 4
+ 1
+
+
+ FB5
+ Filter bits
+ 5
+ 1
+
+
+ FB6
+ Filter bits
+ 6
+ 1
+
+
+ FB7
+ Filter bits
+ 7
+ 1
+
+
+ FB8
+ Filter bits
+ 8
+ 1
+
+
+ FB9
+ Filter bits
+ 9
+ 1
+
+
+ FB10
+ Filter bits
+ 10
+ 1
+
+
+ FB11
+ Filter bits
+ 11
+ 1
+
+
+ FB12
+ Filter bits
+ 12
+ 1
+
+
+ FB13
+ Filter bits
+ 13
+ 1
+
+
+ FB14
+ Filter bits
+ 14
+ 1
+
+
+ FB15
+ Filter bits
+ 15
+ 1
+
+
+ FB16
+ Filter bits
+ 16
+ 1
+
+
+ FB17
+ Filter bits
+ 17
+ 1
+
+
+ FB18
+ Filter bits
+ 18
+ 1
+
+
+ FB19
+ Filter bits
+ 19
+ 1
+
+
+ FB20
+ Filter bits
+ 20
+ 1
+
+
+ FB21
+ Filter bits
+ 21
+ 1
+
+
+ FB22
+ Filter bits
+ 22
+ 1
+
+
+ FB23
+ Filter bits
+ 23
+ 1
+
+
+ FB24
+ Filter bits
+ 24
+ 1
+
+
+ FB25
+ Filter bits
+ 25
+ 1
+
+
+ FB26
+ Filter bits
+ 26
+ 1
+
+
+ FB27
+ Filter bits
+ 27
+ 1
+
+
+ FB28
+ Filter bits
+ 28
+ 1
+
+
+ FB29
+ Filter bits
+ 29
+ 1
+
+
+ FB30
+ Filter bits
+ 30
+ 1
+
+
+ FB31
+ Filter bits
+ 31
+ 1
+
+
+
+
+ F18R1
+ F18R1
+ Filter bank 18 register 1
+ 0x2D0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ FB0
+ Filter bits
+ 0
+ 1
+
+
+ FB1
+ Filter bits
+ 1
+ 1
+
+
+ FB2
+ Filter bits
+ 2
+ 1
+
+
+ FB3
+ Filter bits
+ 3
+ 1
+
+
+ FB4
+ Filter bits
+ 4
+ 1
+
+
+ FB5
+ Filter bits
+ 5
+ 1
+
+
+ FB6
+ Filter bits
+ 6
+ 1
+
+
+ FB7
+ Filter bits
+ 7
+ 1
+
+
+ FB8
+ Filter bits
+ 8
+ 1
+
+
+ FB9
+ Filter bits
+ 9
+ 1
+
+
+ FB10
+ Filter bits
+ 10
+ 1
+
+
+ FB11
+ Filter bits
+ 11
+ 1
+
+
+ FB12
+ Filter bits
+ 12
+ 1
+
+
+ FB13
+ Filter bits
+ 13
+ 1
+
+
+ FB14
+ Filter bits
+ 14
+ 1
+
+
+ FB15
+ Filter bits
+ 15
+ 1
+
+
+ FB16
+ Filter bits
+ 16
+ 1
+
+
+ FB17
+ Filter bits
+ 17
+ 1
+
+
+ FB18
+ Filter bits
+ 18
+ 1
+
+
+ FB19
+ Filter bits
+ 19
+ 1
+
+
+ FB20
+ Filter bits
+ 20
+ 1
+
+
+ FB21
+ Filter bits
+ 21
+ 1
+
+
+ FB22
+ Filter bits
+ 22
+ 1
+
+
+ FB23
+ Filter bits
+ 23
+ 1
+
+
+ FB24
+ Filter bits
+ 24
+ 1
+
+
+ FB25
+ Filter bits
+ 25
+ 1
+
+
+ FB26
+ Filter bits
+ 26
+ 1
+
+
+ FB27
+ Filter bits
+ 27
+ 1
+
+
+ FB28
+ Filter bits
+ 28
+ 1
+
+
+ FB29
+ Filter bits
+ 29
+ 1
+
+
+ FB30
+ Filter bits
+ 30
+ 1
+
+
+ FB31
+ Filter bits
+ 31
+ 1
+
+
+
+
+ F18R2
+ F18R2
+ Filter bank 18 register 2
+ 0x2D4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ FB0
+ Filter bits
+ 0
+ 1
+
+
+ FB1
+ Filter bits
+ 1
+ 1
+
+
+ FB2
+ Filter bits
+ 2
+ 1
+
+
+ FB3
+ Filter bits
+ 3
+ 1
+
+
+ FB4
+ Filter bits
+ 4
+ 1
+
+
+ FB5
+ Filter bits
+ 5
+ 1
+
+
+ FB6
+ Filter bits
+ 6
+ 1
+
+
+ FB7
+ Filter bits
+ 7
+ 1
+
+
+ FB8
+ Filter bits
+ 8
+ 1
+
+
+ FB9
+ Filter bits
+ 9
+ 1
+
+
+ FB10
+ Filter bits
+ 10
+ 1
+
+
+ FB11
+ Filter bits
+ 11
+ 1
+
+
+ FB12
+ Filter bits
+ 12
+ 1
+
+
+ FB13
+ Filter bits
+ 13
+ 1
+
+
+ FB14
+ Filter bits
+ 14
+ 1
+
+
+ FB15
+ Filter bits
+ 15
+ 1
+
+
+ FB16
+ Filter bits
+ 16
+ 1
+
+
+ FB17
+ Filter bits
+ 17
+ 1
+
+
+ FB18
+ Filter bits
+ 18
+ 1
+
+
+ FB19
+ Filter bits
+ 19
+ 1
+
+
+ FB20
+ Filter bits
+ 20
+ 1
+
+
+ FB21
+ Filter bits
+ 21
+ 1
+
+
+ FB22
+ Filter bits
+ 22
+ 1
+
+
+ FB23
+ Filter bits
+ 23
+ 1
+
+
+ FB24
+ Filter bits
+ 24
+ 1
+
+
+ FB25
+ Filter bits
+ 25
+ 1
+
+
+ FB26
+ Filter bits
+ 26
+ 1
+
+
+ FB27
+ Filter bits
+ 27
+ 1
+
+
+ FB28
+ Filter bits
+ 28
+ 1
+
+
+ FB29
+ Filter bits
+ 29
+ 1
+
+
+ FB30
+ Filter bits
+ 30
+ 1
+
+
+ FB31
+ Filter bits
+ 31
+ 1
+
+
+
+
+ F19R1
+ F19R1
+ Filter bank 19 register 1
+ 0x2D8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ FB0
+ Filter bits
+ 0
+ 1
+
+
+ FB1
+ Filter bits
+ 1
+ 1
+
+
+ FB2
+ Filter bits
+ 2
+ 1
+
+
+ FB3
+ Filter bits
+ 3
+ 1
+
+
+ FB4
+ Filter bits
+ 4
+ 1
+
+
+ FB5
+ Filter bits
+ 5
+ 1
+
+
+ FB6
+ Filter bits
+ 6
+ 1
+
+
+ FB7
+ Filter bits
+ 7
+ 1
+
+
+ FB8
+ Filter bits
+ 8
+ 1
+
+
+ FB9
+ Filter bits
+ 9
+ 1
+
+
+ FB10
+ Filter bits
+ 10
+ 1
+
+
+ FB11
+ Filter bits
+ 11
+ 1
+
+
+ FB12
+ Filter bits
+ 12
+ 1
+
+
+ FB13
+ Filter bits
+ 13
+ 1
+
+
+ FB14
+ Filter bits
+ 14
+ 1
+
+
+ FB15
+ Filter bits
+ 15
+ 1
+
+
+ FB16
+ Filter bits
+ 16
+ 1
+
+
+ FB17
+ Filter bits
+ 17
+ 1
+
+
+ FB18
+ Filter bits
+ 18
+ 1
+
+
+ FB19
+ Filter bits
+ 19
+ 1
+
+
+ FB20
+ Filter bits
+ 20
+ 1
+
+
+ FB21
+ Filter bits
+ 21
+ 1
+
+
+ FB22
+ Filter bits
+ 22
+ 1
+
+
+ FB23
+ Filter bits
+ 23
+ 1
+
+
+ FB24
+ Filter bits
+ 24
+ 1
+
+
+ FB25
+ Filter bits
+ 25
+ 1
+
+
+ FB26
+ Filter bits
+ 26
+ 1
+
+
+ FB27
+ Filter bits
+ 27
+ 1
+
+
+ FB28
+ Filter bits
+ 28
+ 1
+
+
+ FB29
+ Filter bits
+ 29
+ 1
+
+
+ FB30
+ Filter bits
+ 30
+ 1
+
+
+ FB31
+ Filter bits
+ 31
+ 1
+
+
+
+
+ F19R2
+ F19R2
+ Filter bank 19 register 2
+ 0x2DC
+ 0x20
+ read-write
+ 0x00000000
+
+
+ FB0
+ Filter bits
+ 0
+ 1
+
+
+ FB1
+ Filter bits
+ 1
+ 1
+
+
+ FB2
+ Filter bits
+ 2
+ 1
+
+
+ FB3
+ Filter bits
+ 3
+ 1
+
+
+ FB4
+ Filter bits
+ 4
+ 1
+
+
+ FB5
+ Filter bits
+ 5
+ 1
+
+
+ FB6
+ Filter bits
+ 6
+ 1
+
+
+ FB7
+ Filter bits
+ 7
+ 1
+
+
+ FB8
+ Filter bits
+ 8
+ 1
+
+
+ FB9
+ Filter bits
+ 9
+ 1
+
+
+ FB10
+ Filter bits
+ 10
+ 1
+
+
+ FB11
+ Filter bits
+ 11
+ 1
+
+
+ FB12
+ Filter bits
+ 12
+ 1
+
+
+ FB13
+ Filter bits
+ 13
+ 1
+
+
+ FB14
+ Filter bits
+ 14
+ 1
+
+
+ FB15
+ Filter bits
+ 15
+ 1
+
+
+ FB16
+ Filter bits
+ 16
+ 1
+
+
+ FB17
+ Filter bits
+ 17
+ 1
+
+
+ FB18
+ Filter bits
+ 18
+ 1
+
+
+ FB19
+ Filter bits
+ 19
+ 1
+
+
+ FB20
+ Filter bits
+ 20
+ 1
+
+
+ FB21
+ Filter bits
+ 21
+ 1
+
+
+ FB22
+ Filter bits
+ 22
+ 1
+
+
+ FB23
+ Filter bits
+ 23
+ 1
+
+
+ FB24
+ Filter bits
+ 24
+ 1
+
+
+ FB25
+ Filter bits
+ 25
+ 1
+
+
+ FB26
+ Filter bits
+ 26
+ 1
+
+
+ FB27
+ Filter bits
+ 27
+ 1
+
+
+ FB28
+ Filter bits
+ 28
+ 1
+
+
+ FB29
+ Filter bits
+ 29
+ 1
+
+
+ FB30
+ Filter bits
+ 30
+ 1
+
+
+ FB31
+ Filter bits
+ 31
+ 1
+
+
+
+
+ F20R1
+ F20R1
+ Filter bank 20 register 1
+ 0x2E0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ FB0
+ Filter bits
+ 0
+ 1
+
+
+ FB1
+ Filter bits
+ 1
+ 1
+
+
+ FB2
+ Filter bits
+ 2
+ 1
+
+
+ FB3
+ Filter bits
+ 3
+ 1
+
+
+ FB4
+ Filter bits
+ 4
+ 1
+
+
+ FB5
+ Filter bits
+ 5
+ 1
+
+
+ FB6
+ Filter bits
+ 6
+ 1
+
+
+ FB7
+ Filter bits
+ 7
+ 1
+
+
+ FB8
+ Filter bits
+ 8
+ 1
+
+
+ FB9
+ Filter bits
+ 9
+ 1
+
+
+ FB10
+ Filter bits
+ 10
+ 1
+
+
+ FB11
+ Filter bits
+ 11
+ 1
+
+
+ FB12
+ Filter bits
+ 12
+ 1
+
+
+ FB13
+ Filter bits
+ 13
+ 1
+
+
+ FB14
+ Filter bits
+ 14
+ 1
+
+
+ FB15
+ Filter bits
+ 15
+ 1
+
+
+ FB16
+ Filter bits
+ 16
+ 1
+
+
+ FB17
+ Filter bits
+ 17
+ 1
+
+
+ FB18
+ Filter bits
+ 18
+ 1
+
+
+ FB19
+ Filter bits
+ 19
+ 1
+
+
+ FB20
+ Filter bits
+ 20
+ 1
+
+
+ FB21
+ Filter bits
+ 21
+ 1
+
+
+ FB22
+ Filter bits
+ 22
+ 1
+
+
+ FB23
+ Filter bits
+ 23
+ 1
+
+
+ FB24
+ Filter bits
+ 24
+ 1
+
+
+ FB25
+ Filter bits
+ 25
+ 1
+
+
+ FB26
+ Filter bits
+ 26
+ 1
+
+
+ FB27
+ Filter bits
+ 27
+ 1
+
+
+ FB28
+ Filter bits
+ 28
+ 1
+
+
+ FB29
+ Filter bits
+ 29
+ 1
+
+
+ FB30
+ Filter bits
+ 30
+ 1
+
+
+ FB31
+ Filter bits
+ 31
+ 1
+
+
+
+
+ F20R2
+ F20R2
+ Filter bank 20 register 2
+ 0x2E4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ FB0
+ Filter bits
+ 0
+ 1
+
+
+ FB1
+ Filter bits
+ 1
+ 1
+
+
+ FB2
+ Filter bits
+ 2
+ 1
+
+
+ FB3
+ Filter bits
+ 3
+ 1
+
+
+ FB4
+ Filter bits
+ 4
+ 1
+
+
+ FB5
+ Filter bits
+ 5
+ 1
+
+
+ FB6
+ Filter bits
+ 6
+ 1
+
+
+ FB7
+ Filter bits
+ 7
+ 1
+
+
+ FB8
+ Filter bits
+ 8
+ 1
+
+
+ FB9
+ Filter bits
+ 9
+ 1
+
+
+ FB10
+ Filter bits
+ 10
+ 1
+
+
+ FB11
+ Filter bits
+ 11
+ 1
+
+
+ FB12
+ Filter bits
+ 12
+ 1
+
+
+ FB13
+ Filter bits
+ 13
+ 1
+
+
+ FB14
+ Filter bits
+ 14
+ 1
+
+
+ FB15
+ Filter bits
+ 15
+ 1
+
+
+ FB16
+ Filter bits
+ 16
+ 1
+
+
+ FB17
+ Filter bits
+ 17
+ 1
+
+
+ FB18
+ Filter bits
+ 18
+ 1
+
+
+ FB19
+ Filter bits
+ 19
+ 1
+
+
+ FB20
+ Filter bits
+ 20
+ 1
+
+
+ FB21
+ Filter bits
+ 21
+ 1
+
+
+ FB22
+ Filter bits
+ 22
+ 1
+
+
+ FB23
+ Filter bits
+ 23
+ 1
+
+
+ FB24
+ Filter bits
+ 24
+ 1
+
+
+ FB25
+ Filter bits
+ 25
+ 1
+
+
+ FB26
+ Filter bits
+ 26
+ 1
+
+
+ FB27
+ Filter bits
+ 27
+ 1
+
+
+ FB28
+ Filter bits
+ 28
+ 1
+
+
+ FB29
+ Filter bits
+ 29
+ 1
+
+
+ FB30
+ Filter bits
+ 30
+ 1
+
+
+ FB31
+ Filter bits
+ 31
+ 1
+
+
+
+
+ F21R1
+ F21R1
+ Filter bank 21 register 1
+ 0x2E8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ FB0
+ Filter bits
+ 0
+ 1
+
+
+ FB1
+ Filter bits
+ 1
+ 1
+
+
+ FB2
+ Filter bits
+ 2
+ 1
+
+
+ FB3
+ Filter bits
+ 3
+ 1
+
+
+ FB4
+ Filter bits
+ 4
+ 1
+
+
+ FB5
+ Filter bits
+ 5
+ 1
+
+
+ FB6
+ Filter bits
+ 6
+ 1
+
+
+ FB7
+ Filter bits
+ 7
+ 1
+
+
+ FB8
+ Filter bits
+ 8
+ 1
+
+
+ FB9
+ Filter bits
+ 9
+ 1
+
+
+ FB10
+ Filter bits
+ 10
+ 1
+
+
+ FB11
+ Filter bits
+ 11
+ 1
+
+
+ FB12
+ Filter bits
+ 12
+ 1
+
+
+ FB13
+ Filter bits
+ 13
+ 1
+
+
+ FB14
+ Filter bits
+ 14
+ 1
+
+
+ FB15
+ Filter bits
+ 15
+ 1
+
+
+ FB16
+ Filter bits
+ 16
+ 1
+
+
+ FB17
+ Filter bits
+ 17
+ 1
+
+
+ FB18
+ Filter bits
+ 18
+ 1
+
+
+ FB19
+ Filter bits
+ 19
+ 1
+
+
+ FB20
+ Filter bits
+ 20
+ 1
+
+
+ FB21
+ Filter bits
+ 21
+ 1
+
+
+ FB22
+ Filter bits
+ 22
+ 1
+
+
+ FB23
+ Filter bits
+ 23
+ 1
+
+
+ FB24
+ Filter bits
+ 24
+ 1
+
+
+ FB25
+ Filter bits
+ 25
+ 1
+
+
+ FB26
+ Filter bits
+ 26
+ 1
+
+
+ FB27
+ Filter bits
+ 27
+ 1
+
+
+ FB28
+ Filter bits
+ 28
+ 1
+
+
+ FB29
+ Filter bits
+ 29
+ 1
+
+
+ FB30
+ Filter bits
+ 30
+ 1
+
+
+ FB31
+ Filter bits
+ 31
+ 1
+
+
+
+
+ F21R2
+ F21R2
+ Filter bank 21 register 2
+ 0x2EC
+ 0x20
+ read-write
+ 0x00000000
+
+
+ FB0
+ Filter bits
+ 0
+ 1
+
+
+ FB1
+ Filter bits
+ 1
+ 1
+
+
+ FB2
+ Filter bits
+ 2
+ 1
+
+
+ FB3
+ Filter bits
+ 3
+ 1
+
+
+ FB4
+ Filter bits
+ 4
+ 1
+
+
+ FB5
+ Filter bits
+ 5
+ 1
+
+
+ FB6
+ Filter bits
+ 6
+ 1
+
+
+ FB7
+ Filter bits
+ 7
+ 1
+
+
+ FB8
+ Filter bits
+ 8
+ 1
+
+
+ FB9
+ Filter bits
+ 9
+ 1
+
+
+ FB10
+ Filter bits
+ 10
+ 1
+
+
+ FB11
+ Filter bits
+ 11
+ 1
+
+
+ FB12
+ Filter bits
+ 12
+ 1
+
+
+ FB13
+ Filter bits
+ 13
+ 1
+
+
+ FB14
+ Filter bits
+ 14
+ 1
+
+
+ FB15
+ Filter bits
+ 15
+ 1
+
+
+ FB16
+ Filter bits
+ 16
+ 1
+
+
+ FB17
+ Filter bits
+ 17
+ 1
+
+
+ FB18
+ Filter bits
+ 18
+ 1
+
+
+ FB19
+ Filter bits
+ 19
+ 1
+
+
+ FB20
+ Filter bits
+ 20
+ 1
+
+
+ FB21
+ Filter bits
+ 21
+ 1
+
+
+ FB22
+ Filter bits
+ 22
+ 1
+
+
+ FB23
+ Filter bits
+ 23
+ 1
+
+
+ FB24
+ Filter bits
+ 24
+ 1
+
+
+ FB25
+ Filter bits
+ 25
+ 1
+
+
+ FB26
+ Filter bits
+ 26
+ 1
+
+
+ FB27
+ Filter bits
+ 27
+ 1
+
+
+ FB28
+ Filter bits
+ 28
+ 1
+
+
+ FB29
+ Filter bits
+ 29
+ 1
+
+
+ FB30
+ Filter bits
+ 30
+ 1
+
+
+ FB31
+ Filter bits
+ 31
+ 1
+
+
+
+
+ F22R1
+ F22R1
+ Filter bank 22 register 1
+ 0x2F0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ FB0
+ Filter bits
+ 0
+ 1
+
+
+ FB1
+ Filter bits
+ 1
+ 1
+
+
+ FB2
+ Filter bits
+ 2
+ 1
+
+
+ FB3
+ Filter bits
+ 3
+ 1
+
+
+ FB4
+ Filter bits
+ 4
+ 1
+
+
+ FB5
+ Filter bits
+ 5
+ 1
+
+
+ FB6
+ Filter bits
+ 6
+ 1
+
+
+ FB7
+ Filter bits
+ 7
+ 1
+
+
+ FB8
+ Filter bits
+ 8
+ 1
+
+
+ FB9
+ Filter bits
+ 9
+ 1
+
+
+ FB10
+ Filter bits
+ 10
+ 1
+
+
+ FB11
+ Filter bits
+ 11
+ 1
+
+
+ FB12
+ Filter bits
+ 12
+ 1
+
+
+ FB13
+ Filter bits
+ 13
+ 1
+
+
+ FB14
+ Filter bits
+ 14
+ 1
+
+
+ FB15
+ Filter bits
+ 15
+ 1
+
+
+ FB16
+ Filter bits
+ 16
+ 1
+
+
+ FB17
+ Filter bits
+ 17
+ 1
+
+
+ FB18
+ Filter bits
+ 18
+ 1
+
+
+ FB19
+ Filter bits
+ 19
+ 1
+
+
+ FB20
+ Filter bits
+ 20
+ 1
+
+
+ FB21
+ Filter bits
+ 21
+ 1
+
+
+ FB22
+ Filter bits
+ 22
+ 1
+
+
+ FB23
+ Filter bits
+ 23
+ 1
+
+
+ FB24
+ Filter bits
+ 24
+ 1
+
+
+ FB25
+ Filter bits
+ 25
+ 1
+
+
+ FB26
+ Filter bits
+ 26
+ 1
+
+
+ FB27
+ Filter bits
+ 27
+ 1
+
+
+ FB28
+ Filter bits
+ 28
+ 1
+
+
+ FB29
+ Filter bits
+ 29
+ 1
+
+
+ FB30
+ Filter bits
+ 30
+ 1
+
+
+ FB31
+ Filter bits
+ 31
+ 1
+
+
+
+
+ F22R2
+ F22R2
+ Filter bank 22 register 2
+ 0x2F4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ FB0
+ Filter bits
+ 0
+ 1
+
+
+ FB1
+ Filter bits
+ 1
+ 1
+
+
+ FB2
+ Filter bits
+ 2
+ 1
+
+
+ FB3
+ Filter bits
+ 3
+ 1
+
+
+ FB4
+ Filter bits
+ 4
+ 1
+
+
+ FB5
+ Filter bits
+ 5
+ 1
+
+
+ FB6
+ Filter bits
+ 6
+ 1
+
+
+ FB7
+ Filter bits
+ 7
+ 1
+
+
+ FB8
+ Filter bits
+ 8
+ 1
+
+
+ FB9
+ Filter bits
+ 9
+ 1
+
+
+ FB10
+ Filter bits
+ 10
+ 1
+
+
+ FB11
+ Filter bits
+ 11
+ 1
+
+
+ FB12
+ Filter bits
+ 12
+ 1
+
+
+ FB13
+ Filter bits
+ 13
+ 1
+
+
+ FB14
+ Filter bits
+ 14
+ 1
+
+
+ FB15
+ Filter bits
+ 15
+ 1
+
+
+ FB16
+ Filter bits
+ 16
+ 1
+
+
+ FB17
+ Filter bits
+ 17
+ 1
+
+
+ FB18
+ Filter bits
+ 18
+ 1
+
+
+ FB19
+ Filter bits
+ 19
+ 1
+
+
+ FB20
+ Filter bits
+ 20
+ 1
+
+
+ FB21
+ Filter bits
+ 21
+ 1
+
+
+ FB22
+ Filter bits
+ 22
+ 1
+
+
+ FB23
+ Filter bits
+ 23
+ 1
+
+
+ FB24
+ Filter bits
+ 24
+ 1
+
+
+ FB25
+ Filter bits
+ 25
+ 1
+
+
+ FB26
+ Filter bits
+ 26
+ 1
+
+
+ FB27
+ Filter bits
+ 27
+ 1
+
+
+ FB28
+ Filter bits
+ 28
+ 1
+
+
+ FB29
+ Filter bits
+ 29
+ 1
+
+
+ FB30
+ Filter bits
+ 30
+ 1
+
+
+ FB31
+ Filter bits
+ 31
+ 1
+
+
+
+
+ F23R1
+ F23R1
+ Filter bank 23 register 1
+ 0x2F8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ FB0
+ Filter bits
+ 0
+ 1
+
+
+ FB1
+ Filter bits
+ 1
+ 1
+
+
+ FB2
+ Filter bits
+ 2
+ 1
+
+
+ FB3
+ Filter bits
+ 3
+ 1
+
+
+ FB4
+ Filter bits
+ 4
+ 1
+
+
+ FB5
+ Filter bits
+ 5
+ 1
+
+
+ FB6
+ Filter bits
+ 6
+ 1
+
+
+ FB7
+ Filter bits
+ 7
+ 1
+
+
+ FB8
+ Filter bits
+ 8
+ 1
+
+
+ FB9
+ Filter bits
+ 9
+ 1
+
+
+ FB10
+ Filter bits
+ 10
+ 1
+
+
+ FB11
+ Filter bits
+ 11
+ 1
+
+
+ FB12
+ Filter bits
+ 12
+ 1
+
+
+ FB13
+ Filter bits
+ 13
+ 1
+
+
+ FB14
+ Filter bits
+ 14
+ 1
+
+
+ FB15
+ Filter bits
+ 15
+ 1
+
+
+ FB16
+ Filter bits
+ 16
+ 1
+
+
+ FB17
+ Filter bits
+ 17
+ 1
+
+
+ FB18
+ Filter bits
+ 18
+ 1
+
+
+ FB19
+ Filter bits
+ 19
+ 1
+
+
+ FB20
+ Filter bits
+ 20
+ 1
+
+
+ FB21
+ Filter bits
+ 21
+ 1
+
+
+ FB22
+ Filter bits
+ 22
+ 1
+
+
+ FB23
+ Filter bits
+ 23
+ 1
+
+
+ FB24
+ Filter bits
+ 24
+ 1
+
+
+ FB25
+ Filter bits
+ 25
+ 1
+
+
+ FB26
+ Filter bits
+ 26
+ 1
+
+
+ FB27
+ Filter bits
+ 27
+ 1
+
+
+ FB28
+ Filter bits
+ 28
+ 1
+
+
+ FB29
+ Filter bits
+ 29
+ 1
+
+
+ FB30
+ Filter bits
+ 30
+ 1
+
+
+ FB31
+ Filter bits
+ 31
+ 1
+
+
+
+
+ F23R2
+ F23R2
+ Filter bank 23 register 2
+ 0x2FC
+ 0x20
+ read-write
+ 0x00000000
+
+
+ FB0
+ Filter bits
+ 0
+ 1
+
+
+ FB1
+ Filter bits
+ 1
+ 1
+
+
+ FB2
+ Filter bits
+ 2
+ 1
+
+
+ FB3
+ Filter bits
+ 3
+ 1
+
+
+ FB4
+ Filter bits
+ 4
+ 1
+
+
+ FB5
+ Filter bits
+ 5
+ 1
+
+
+ FB6
+ Filter bits
+ 6
+ 1
+
+
+ FB7
+ Filter bits
+ 7
+ 1
+
+
+ FB8
+ Filter bits
+ 8
+ 1
+
+
+ FB9
+ Filter bits
+ 9
+ 1
+
+
+ FB10
+ Filter bits
+ 10
+ 1
+
+
+ FB11
+ Filter bits
+ 11
+ 1
+
+
+ FB12
+ Filter bits
+ 12
+ 1
+
+
+ FB13
+ Filter bits
+ 13
+ 1
+
+
+ FB14
+ Filter bits
+ 14
+ 1
+
+
+ FB15
+ Filter bits
+ 15
+ 1
+
+
+ FB16
+ Filter bits
+ 16
+ 1
+
+
+ FB17
+ Filter bits
+ 17
+ 1
+
+
+ FB18
+ Filter bits
+ 18
+ 1
+
+
+ FB19
+ Filter bits
+ 19
+ 1
+
+
+ FB20
+ Filter bits
+ 20
+ 1
+
+
+ FB21
+ Filter bits
+ 21
+ 1
+
+
+ FB22
+ Filter bits
+ 22
+ 1
+
+
+ FB23
+ Filter bits
+ 23
+ 1
+
+
+ FB24
+ Filter bits
+ 24
+ 1
+
+
+ FB25
+ Filter bits
+ 25
+ 1
+
+
+ FB26
+ Filter bits
+ 26
+ 1
+
+
+ FB27
+ Filter bits
+ 27
+ 1
+
+
+ FB28
+ Filter bits
+ 28
+ 1
+
+
+ FB29
+ Filter bits
+ 29
+ 1
+
+
+ FB30
+ Filter bits
+ 30
+ 1
+
+
+ FB31
+ Filter bits
+ 31
+ 1
+
+
+
+
+ F24R1
+ F24R1
+ Filter bank 24 register 1
+ 0x300
+ 0x20
+ read-write
+ 0x00000000
+
+
+ FB0
+ Filter bits
+ 0
+ 1
+
+
+ FB1
+ Filter bits
+ 1
+ 1
+
+
+ FB2
+ Filter bits
+ 2
+ 1
+
+
+ FB3
+ Filter bits
+ 3
+ 1
+
+
+ FB4
+ Filter bits
+ 4
+ 1
+
+
+ FB5
+ Filter bits
+ 5
+ 1
+
+
+ FB6
+ Filter bits
+ 6
+ 1
+
+
+ FB7
+ Filter bits
+ 7
+ 1
+
+
+ FB8
+ Filter bits
+ 8
+ 1
+
+
+ FB9
+ Filter bits
+ 9
+ 1
+
+
+ FB10
+ Filter bits
+ 10
+ 1
+
+
+ FB11
+ Filter bits
+ 11
+ 1
+
+
+ FB12
+ Filter bits
+ 12
+ 1
+
+
+ FB13
+ Filter bits
+ 13
+ 1
+
+
+ FB14
+ Filter bits
+ 14
+ 1
+
+
+ FB15
+ Filter bits
+ 15
+ 1
+
+
+ FB16
+ Filter bits
+ 16
+ 1
+
+
+ FB17
+ Filter bits
+ 17
+ 1
+
+
+ FB18
+ Filter bits
+ 18
+ 1
+
+
+ FB19
+ Filter bits
+ 19
+ 1
+
+
+ FB20
+ Filter bits
+ 20
+ 1
+
+
+ FB21
+ Filter bits
+ 21
+ 1
+
+
+ FB22
+ Filter bits
+ 22
+ 1
+
+
+ FB23
+ Filter bits
+ 23
+ 1
+
+
+ FB24
+ Filter bits
+ 24
+ 1
+
+
+ FB25
+ Filter bits
+ 25
+ 1
+
+
+ FB26
+ Filter bits
+ 26
+ 1
+
+
+ FB27
+ Filter bits
+ 27
+ 1
+
+
+ FB28
+ Filter bits
+ 28
+ 1
+
+
+ FB29
+ Filter bits
+ 29
+ 1
+
+
+ FB30
+ Filter bits
+ 30
+ 1
+
+
+ FB31
+ Filter bits
+ 31
+ 1
+
+
+
+
+ F24R2
+ F24R2
+ Filter bank 24 register 2
+ 0x304
+ 0x20
+ read-write
+ 0x00000000
+
+
+ FB0
+ Filter bits
+ 0
+ 1
+
+
+ FB1
+ Filter bits
+ 1
+ 1
+
+
+ FB2
+ Filter bits
+ 2
+ 1
+
+
+ FB3
+ Filter bits
+ 3
+ 1
+
+
+ FB4
+ Filter bits
+ 4
+ 1
+
+
+ FB5
+ Filter bits
+ 5
+ 1
+
+
+ FB6
+ Filter bits
+ 6
+ 1
+
+
+ FB7
+ Filter bits
+ 7
+ 1
+
+
+ FB8
+ Filter bits
+ 8
+ 1
+
+
+ FB9
+ Filter bits
+ 9
+ 1
+
+
+ FB10
+ Filter bits
+ 10
+ 1
+
+
+ FB11
+ Filter bits
+ 11
+ 1
+
+
+ FB12
+ Filter bits
+ 12
+ 1
+
+
+ FB13
+ Filter bits
+ 13
+ 1
+
+
+ FB14
+ Filter bits
+ 14
+ 1
+
+
+ FB15
+ Filter bits
+ 15
+ 1
+
+
+ FB16
+ Filter bits
+ 16
+ 1
+
+
+ FB17
+ Filter bits
+ 17
+ 1
+
+
+ FB18
+ Filter bits
+ 18
+ 1
+
+
+ FB19
+ Filter bits
+ 19
+ 1
+
+
+ FB20
+ Filter bits
+ 20
+ 1
+
+
+ FB21
+ Filter bits
+ 21
+ 1
+
+
+ FB22
+ Filter bits
+ 22
+ 1
+
+
+ FB23
+ Filter bits
+ 23
+ 1
+
+
+ FB24
+ Filter bits
+ 24
+ 1
+
+
+ FB25
+ Filter bits
+ 25
+ 1
+
+
+ FB26
+ Filter bits
+ 26
+ 1
+
+
+ FB27
+ Filter bits
+ 27
+ 1
+
+
+ FB28
+ Filter bits
+ 28
+ 1
+
+
+ FB29
+ Filter bits
+ 29
+ 1
+
+
+ FB30
+ Filter bits
+ 30
+ 1
+
+
+ FB31
+ Filter bits
+ 31
+ 1
+
+
+
+
+ F25R1
+ F25R1
+ Filter bank 25 register 1
+ 0x308
+ 0x20
+ read-write
+ 0x00000000
+
+
+ FB0
+ Filter bits
+ 0
+ 1
+
+
+ FB1
+ Filter bits
+ 1
+ 1
+
+
+ FB2
+ Filter bits
+ 2
+ 1
+
+
+ FB3
+ Filter bits
+ 3
+ 1
+
+
+ FB4
+ Filter bits
+ 4
+ 1
+
+
+ FB5
+ Filter bits
+ 5
+ 1
+
+
+ FB6
+ Filter bits
+ 6
+ 1
+
+
+ FB7
+ Filter bits
+ 7
+ 1
+
+
+ FB8
+ Filter bits
+ 8
+ 1
+
+
+ FB9
+ Filter bits
+ 9
+ 1
+
+
+ FB10
+ Filter bits
+ 10
+ 1
+
+
+ FB11
+ Filter bits
+ 11
+ 1
+
+
+ FB12
+ Filter bits
+ 12
+ 1
+
+
+ FB13
+ Filter bits
+ 13
+ 1
+
+
+ FB14
+ Filter bits
+ 14
+ 1
+
+
+ FB15
+ Filter bits
+ 15
+ 1
+
+
+ FB16
+ Filter bits
+ 16
+ 1
+
+
+ FB17
+ Filter bits
+ 17
+ 1
+
+
+ FB18
+ Filter bits
+ 18
+ 1
+
+
+ FB19
+ Filter bits
+ 19
+ 1
+
+
+ FB20
+ Filter bits
+ 20
+ 1
+
+
+ FB21
+ Filter bits
+ 21
+ 1
+
+
+ FB22
+ Filter bits
+ 22
+ 1
+
+
+ FB23
+ Filter bits
+ 23
+ 1
+
+
+ FB24
+ Filter bits
+ 24
+ 1
+
+
+ FB25
+ Filter bits
+ 25
+ 1
+
+
+ FB26
+ Filter bits
+ 26
+ 1
+
+
+ FB27
+ Filter bits
+ 27
+ 1
+
+
+ FB28
+ Filter bits
+ 28
+ 1
+
+
+ FB29
+ Filter bits
+ 29
+ 1
+
+
+ FB30
+ Filter bits
+ 30
+ 1
+
+
+ FB31
+ Filter bits
+ 31
+ 1
+
+
+
+
+ F25R2
+ F25R2
+ Filter bank 25 register 2
+ 0x30C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ FB0
+ Filter bits
+ 0
+ 1
+
+
+ FB1
+ Filter bits
+ 1
+ 1
+
+
+ FB2
+ Filter bits
+ 2
+ 1
+
+
+ FB3
+ Filter bits
+ 3
+ 1
+
+
+ FB4
+ Filter bits
+ 4
+ 1
+
+
+ FB5
+ Filter bits
+ 5
+ 1
+
+
+ FB6
+ Filter bits
+ 6
+ 1
+
+
+ FB7
+ Filter bits
+ 7
+ 1
+
+
+ FB8
+ Filter bits
+ 8
+ 1
+
+
+ FB9
+ Filter bits
+ 9
+ 1
+
+
+ FB10
+ Filter bits
+ 10
+ 1
+
+
+ FB11
+ Filter bits
+ 11
+ 1
+
+
+ FB12
+ Filter bits
+ 12
+ 1
+
+
+ FB13
+ Filter bits
+ 13
+ 1
+
+
+ FB14
+ Filter bits
+ 14
+ 1
+
+
+ FB15
+ Filter bits
+ 15
+ 1
+
+
+ FB16
+ Filter bits
+ 16
+ 1
+
+
+ FB17
+ Filter bits
+ 17
+ 1
+
+
+ FB18
+ Filter bits
+ 18
+ 1
+
+
+ FB19
+ Filter bits
+ 19
+ 1
+
+
+ FB20
+ Filter bits
+ 20
+ 1
+
+
+ FB21
+ Filter bits
+ 21
+ 1
+
+
+ FB22
+ Filter bits
+ 22
+ 1
+
+
+ FB23
+ Filter bits
+ 23
+ 1
+
+
+ FB24
+ Filter bits
+ 24
+ 1
+
+
+ FB25
+ Filter bits
+ 25
+ 1
+
+
+ FB26
+ Filter bits
+ 26
+ 1
+
+
+ FB27
+ Filter bits
+ 27
+ 1
+
+
+ FB28
+ Filter bits
+ 28
+ 1
+
+
+ FB29
+ Filter bits
+ 29
+ 1
+
+
+ FB30
+ Filter bits
+ 30
+ 1
+
+
+ FB31
+ Filter bits
+ 31
+ 1
+
+
+
+
+ F26R1
+ F26R1
+ Filter bank 26 register 1
+ 0x310
+ 0x20
+ read-write
+ 0x00000000
+
+
+ FB0
+ Filter bits
+ 0
+ 1
+
+
+ FB1
+ Filter bits
+ 1
+ 1
+
+
+ FB2
+ Filter bits
+ 2
+ 1
+
+
+ FB3
+ Filter bits
+ 3
+ 1
+
+
+ FB4
+ Filter bits
+ 4
+ 1
+
+
+ FB5
+ Filter bits
+ 5
+ 1
+
+
+ FB6
+ Filter bits
+ 6
+ 1
+
+
+ FB7
+ Filter bits
+ 7
+ 1
+
+
+ FB8
+ Filter bits
+ 8
+ 1
+
+
+ FB9
+ Filter bits
+ 9
+ 1
+
+
+ FB10
+ Filter bits
+ 10
+ 1
+
+
+ FB11
+ Filter bits
+ 11
+ 1
+
+
+ FB12
+ Filter bits
+ 12
+ 1
+
+
+ FB13
+ Filter bits
+ 13
+ 1
+
+
+ FB14
+ Filter bits
+ 14
+ 1
+
+
+ FB15
+ Filter bits
+ 15
+ 1
+
+
+ FB16
+ Filter bits
+ 16
+ 1
+
+
+ FB17
+ Filter bits
+ 17
+ 1
+
+
+ FB18
+ Filter bits
+ 18
+ 1
+
+
+ FB19
+ Filter bits
+ 19
+ 1
+
+
+ FB20
+ Filter bits
+ 20
+ 1
+
+
+ FB21
+ Filter bits
+ 21
+ 1
+
+
+ FB22
+ Filter bits
+ 22
+ 1
+
+
+ FB23
+ Filter bits
+ 23
+ 1
+
+
+ FB24
+ Filter bits
+ 24
+ 1
+
+
+ FB25
+ Filter bits
+ 25
+ 1
+
+
+ FB26
+ Filter bits
+ 26
+ 1
+
+
+ FB27
+ Filter bits
+ 27
+ 1
+
+
+ FB28
+ Filter bits
+ 28
+ 1
+
+
+ FB29
+ Filter bits
+ 29
+ 1
+
+
+ FB30
+ Filter bits
+ 30
+ 1
+
+
+ FB31
+ Filter bits
+ 31
+ 1
+
+
+
+
+ F26R2
+ F26R2
+ Filter bank 26 register 2
+ 0x314
+ 0x20
+ read-write
+ 0x00000000
+
+
+ FB0
+ Filter bits
+ 0
+ 1
+
+
+ FB1
+ Filter bits
+ 1
+ 1
+
+
+ FB2
+ Filter bits
+ 2
+ 1
+
+
+ FB3
+ Filter bits
+ 3
+ 1
+
+
+ FB4
+ Filter bits
+ 4
+ 1
+
+
+ FB5
+ Filter bits
+ 5
+ 1
+
+
+ FB6
+ Filter bits
+ 6
+ 1
+
+
+ FB7
+ Filter bits
+ 7
+ 1
+
+
+ FB8
+ Filter bits
+ 8
+ 1
+
+
+ FB9
+ Filter bits
+ 9
+ 1
+
+
+ FB10
+ Filter bits
+ 10
+ 1
+
+
+ FB11
+ Filter bits
+ 11
+ 1
+
+
+ FB12
+ Filter bits
+ 12
+ 1
+
+
+ FB13
+ Filter bits
+ 13
+ 1
+
+
+ FB14
+ Filter bits
+ 14
+ 1
+
+
+ FB15
+ Filter bits
+ 15
+ 1
+
+
+ FB16
+ Filter bits
+ 16
+ 1
+
+
+ FB17
+ Filter bits
+ 17
+ 1
+
+
+ FB18
+ Filter bits
+ 18
+ 1
+
+
+ FB19
+ Filter bits
+ 19
+ 1
+
+
+ FB20
+ Filter bits
+ 20
+ 1
+
+
+ FB21
+ Filter bits
+ 21
+ 1
+
+
+ FB22
+ Filter bits
+ 22
+ 1
+
+
+ FB23
+ Filter bits
+ 23
+ 1
+
+
+ FB24
+ Filter bits
+ 24
+ 1
+
+
+ FB25
+ Filter bits
+ 25
+ 1
+
+
+ FB26
+ Filter bits
+ 26
+ 1
+
+
+ FB27
+ Filter bits
+ 27
+ 1
+
+
+ FB28
+ Filter bits
+ 28
+ 1
+
+
+ FB29
+ Filter bits
+ 29
+ 1
+
+
+ FB30
+ Filter bits
+ 30
+ 1
+
+
+ FB31
+ Filter bits
+ 31
+ 1
+
+
+
+
+ F27R1
+ F27R1
+ Filter bank 27 register 1
+ 0x318
+ 0x20
+ read-write
+ 0x00000000
+
+
+ FB0
+ Filter bits
+ 0
+ 1
+
+
+ FB1
+ Filter bits
+ 1
+ 1
+
+
+ FB2
+ Filter bits
+ 2
+ 1
+
+
+ FB3
+ Filter bits
+ 3
+ 1
+
+
+ FB4
+ Filter bits
+ 4
+ 1
+
+
+ FB5
+ Filter bits
+ 5
+ 1
+
+
+ FB6
+ Filter bits
+ 6
+ 1
+
+
+ FB7
+ Filter bits
+ 7
+ 1
+
+
+ FB8
+ Filter bits
+ 8
+ 1
+
+
+ FB9
+ Filter bits
+ 9
+ 1
+
+
+ FB10
+ Filter bits
+ 10
+ 1
+
+
+ FB11
+ Filter bits
+ 11
+ 1
+
+
+ FB12
+ Filter bits
+ 12
+ 1
+
+
+ FB13
+ Filter bits
+ 13
+ 1
+
+
+ FB14
+ Filter bits
+ 14
+ 1
+
+
+ FB15
+ Filter bits
+ 15
+ 1
+
+
+ FB16
+ Filter bits
+ 16
+ 1
+
+
+ FB17
+ Filter bits
+ 17
+ 1
+
+
+ FB18
+ Filter bits
+ 18
+ 1
+
+
+ FB19
+ Filter bits
+ 19
+ 1
+
+
+ FB20
+ Filter bits
+ 20
+ 1
+
+
+ FB21
+ Filter bits
+ 21
+ 1
+
+
+ FB22
+ Filter bits
+ 22
+ 1
+
+
+ FB23
+ Filter bits
+ 23
+ 1
+
+
+ FB24
+ Filter bits
+ 24
+ 1
+
+
+ FB25
+ Filter bits
+ 25
+ 1
+
+
+ FB26
+ Filter bits
+ 26
+ 1
+
+
+ FB27
+ Filter bits
+ 27
+ 1
+
+
+ FB28
+ Filter bits
+ 28
+ 1
+
+
+ FB29
+ Filter bits
+ 29
+ 1
+
+
+ FB30
+ Filter bits
+ 30
+ 1
+
+
+ FB31
+ Filter bits
+ 31
+ 1
+
+
+
+
+ F27R2
+ F27R2
+ Filter bank 27 register 2
+ 0x31C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ FB0
+ Filter bits
+ 0
+ 1
+
+
+ FB1
+ Filter bits
+ 1
+ 1
+
+
+ FB2
+ Filter bits
+ 2
+ 1
+
+
+ FB3
+ Filter bits
+ 3
+ 1
+
+
+ FB4
+ Filter bits
+ 4
+ 1
+
+
+ FB5
+ Filter bits
+ 5
+ 1
+
+
+ FB6
+ Filter bits
+ 6
+ 1
+
+
+ FB7
+ Filter bits
+ 7
+ 1
+
+
+ FB8
+ Filter bits
+ 8
+ 1
+
+
+ FB9
+ Filter bits
+ 9
+ 1
+
+
+ FB10
+ Filter bits
+ 10
+ 1
+
+
+ FB11
+ Filter bits
+ 11
+ 1
+
+
+ FB12
+ Filter bits
+ 12
+ 1
+
+
+ FB13
+ Filter bits
+ 13
+ 1
+
+
+ FB14
+ Filter bits
+ 14
+ 1
+
+
+ FB15
+ Filter bits
+ 15
+ 1
+
+
+ FB16
+ Filter bits
+ 16
+ 1
+
+
+ FB17
+ Filter bits
+ 17
+ 1
+
+
+ FB18
+ Filter bits
+ 18
+ 1
+
+
+ FB19
+ Filter bits
+ 19
+ 1
+
+
+ FB20
+ Filter bits
+ 20
+ 1
+
+
+ FB21
+ Filter bits
+ 21
+ 1
+
+
+ FB22
+ Filter bits
+ 22
+ 1
+
+
+ FB23
+ Filter bits
+ 23
+ 1
+
+
+ FB24
+ Filter bits
+ 24
+ 1
+
+
+ FB25
+ Filter bits
+ 25
+ 1
+
+
+ FB26
+ Filter bits
+ 26
+ 1
+
+
+ FB27
+ Filter bits
+ 27
+ 1
+
+
+ FB28
+ Filter bits
+ 28
+ 1
+
+
+ FB29
+ Filter bits
+ 29
+ 1
+
+
+ FB30
+ Filter bits
+ 30
+ 1
+
+
+ FB31
+ Filter bits
+ 31
+ 1
+
+
+
+
+
+
+ USB_FS
+ Universal serial bus full-speed device
+ interface
+ USB_FS
+ 0x40005C00
+
+ 0x0
+ 0x400
+ registers
+
+
+ USB_WKUP
+ USB wakeup from Suspend
+ 42
+
+
+ USB_HP
+ USB High priority interrupt
+ 74
+
+
+ USB_LP
+ USB Low priority interrupt
+ 75
+
+
+
+ USB_EP0R
+ USB_EP0R
+ endpoint 0 register
+ 0x0
+ 0x20
+ 0x00000000
+
+
+ EA
+ Endpoint address
+ 0
+ 4
+ read-write
+
+
+ STAT_TX
+ Status bits, for transmission
+ transfers
+ 4
+ 2
+ read-write
+
+
+ DTOG_TX
+ Data Toggle, for transmission
+ transfers
+ 6
+ 1
+ read-write
+
+
+ CTR_TX
+ Correct Transfer for
+ transmission
+ 7
+ 1
+ read-write
+
+
+ EP_KIND
+ Endpoint kind
+ 8
+ 1
+ read-write
+
+
+ EP_TYPE
+ Endpoint type
+ 9
+ 2
+ read-write
+
+
+ SETUP
+ Setup transaction
+ completed
+ 11
+ 1
+ read-only
+
+
+ STAT_RX
+ Status bits, for reception
+ transfers
+ 12
+ 2
+ read-write
+
+
+ DTOG_RX
+ Data Toggle, for reception
+ transfers
+ 14
+ 1
+ read-write
+
+
+ CTR_RX
+ Correct transfer for
+ reception
+ 15
+ 1
+ read-write
+
+
+
+
+ USB_EP1R
+ USB_EP1R
+ endpoint 1 register
+ 0x4
+ 0x20
+ 0x00000000
+
+
+ EA
+ Endpoint address
+ 0
+ 4
+ read-write
+
+
+ STAT_TX
+ Status bits, for transmission
+ transfers
+ 4
+ 2
+ read-write
+
+
+ DTOG_TX
+ Data Toggle, for transmission
+ transfers
+ 6
+ 1
+ read-write
+
+
+ CTR_TX
+ Correct Transfer for
+ transmission
+ 7
+ 1
+ read-write
+
+
+ EP_KIND
+ Endpoint kind
+ 8
+ 1
+ read-write
+
+
+ EP_TYPE
+ Endpoint type
+ 9
+ 2
+ read-write
+
+
+ SETUP
+ Setup transaction
+ completed
+ 11
+ 1
+ read-only
+
+
+ STAT_RX
+ Status bits, for reception
+ transfers
+ 12
+ 2
+ read-write
+
+
+ DTOG_RX
+ Data Toggle, for reception
+ transfers
+ 14
+ 1
+ read-write
+
+
+ CTR_RX
+ Correct transfer for
+ reception
+ 15
+ 1
+ read-write
+
+
+
+
+ USB_EP2R
+ USB_EP2R
+ endpoint 2 register
+ 0x8
+ 0x20
+ 0x00000000
+
+
+ EA
+ Endpoint address
+ 0
+ 4
+ read-write
+
+
+ STAT_TX
+ Status bits, for transmission
+ transfers
+ 4
+ 2
+ read-write
+
+
+ DTOG_TX
+ Data Toggle, for transmission
+ transfers
+ 6
+ 1
+ read-write
+
+
+ CTR_TX
+ Correct Transfer for
+ transmission
+ 7
+ 1
+ read-write
+
+
+ EP_KIND
+ Endpoint kind
+ 8
+ 1
+ read-write
+
+
+ EP_TYPE
+ Endpoint type
+ 9
+ 2
+ read-write
+
+
+ SETUP
+ Setup transaction
+ completed
+ 11
+ 1
+ read-only
+
+
+ STAT_RX
+ Status bits, for reception
+ transfers
+ 12
+ 2
+ read-write
+
+
+ DTOG_RX
+ Data Toggle, for reception
+ transfers
+ 14
+ 1
+ read-write
+
+
+ CTR_RX
+ Correct transfer for
+ reception
+ 15
+ 1
+ read-write
+
+
+
+
+ USB_EP3R
+ USB_EP3R
+ endpoint 3 register
+ 0xC
+ 0x20
+ 0x00000000
+
+
+ EA
+ Endpoint address
+ 0
+ 4
+ read-write
+
+
+ STAT_TX
+ Status bits, for transmission
+ transfers
+ 4
+ 2
+ read-write
+
+
+ DTOG_TX
+ Data Toggle, for transmission
+ transfers
+ 6
+ 1
+ read-write
+
+
+ CTR_TX
+ Correct Transfer for
+ transmission
+ 7
+ 1
+ read-write
+
+
+ EP_KIND
+ Endpoint kind
+ 8
+ 1
+ read-write
+
+
+ EP_TYPE
+ Endpoint type
+ 9
+ 2
+ read-write
+
+
+ SETUP
+ Setup transaction
+ completed
+ 11
+ 1
+ read-only
+
+
+ STAT_RX
+ Status bits, for reception
+ transfers
+ 12
+ 2
+ read-write
+
+
+ DTOG_RX
+ Data Toggle, for reception
+ transfers
+ 14
+ 1
+ read-write
+
+
+ CTR_RX
+ Correct transfer for
+ reception
+ 15
+ 1
+ read-write
+
+
+
+
+ USB_EP4R
+ USB_EP4R
+ endpoint 4 register
+ 0x10
+ 0x20
+ 0x00000000
+
+
+ EA
+ Endpoint address
+ 0
+ 4
+ read-write
+
+
+ STAT_TX
+ Status bits, for transmission
+ transfers
+ 4
+ 2
+ read-write
+
+
+ DTOG_TX
+ Data Toggle, for transmission
+ transfers
+ 6
+ 1
+ read-write
+
+
+ CTR_TX
+ Correct Transfer for
+ transmission
+ 7
+ 1
+ read-write
+
+
+ EP_KIND
+ Endpoint kind
+ 8
+ 1
+ read-write
+
+
+ EP_TYPE
+ Endpoint type
+ 9
+ 2
+ read-write
+
+
+ SETUP
+ Setup transaction
+ completed
+ 11
+ 1
+ read-only
+
+
+ STAT_RX
+ Status bits, for reception
+ transfers
+ 12
+ 2
+ read-write
+
+
+ DTOG_RX
+ Data Toggle, for reception
+ transfers
+ 14
+ 1
+ read-write
+
+
+ CTR_RX
+ Correct transfer for
+ reception
+ 15
+ 1
+ read-write
+
+
+
+
+ USB_EP5R
+ USB_EP5R
+ endpoint 5 register
+ 0x14
+ 0x20
+ 0x00000000
+
+
+ EA
+ Endpoint address
+ 0
+ 4
+ read-write
+
+
+ STAT_TX
+ Status bits, for transmission
+ transfers
+ 4
+ 2
+ read-write
+
+
+ DTOG_TX
+ Data Toggle, for transmission
+ transfers
+ 6
+ 1
+ read-write
+
+
+ CTR_TX
+ Correct Transfer for
+ transmission
+ 7
+ 1
+ read-write
+
+
+ EP_KIND
+ Endpoint kind
+ 8
+ 1
+ read-write
+
+
+ EP_TYPE
+ Endpoint type
+ 9
+ 2
+ read-write
+
+
+ SETUP
+ Setup transaction
+ completed
+ 11
+ 1
+ read-only
+
+
+ STAT_RX
+ Status bits, for reception
+ transfers
+ 12
+ 2
+ read-write
+
+
+ DTOG_RX
+ Data Toggle, for reception
+ transfers
+ 14
+ 1
+ read-write
+
+
+ CTR_RX
+ Correct transfer for
+ reception
+ 15
+ 1
+ read-write
+
+
+
+
+ USB_EP6R
+ USB_EP6R
+ endpoint 6 register
+ 0x18
+ 0x20
+ 0x00000000
+
+
+ EA
+ Endpoint address
+ 0
+ 4
+ read-write
+
+
+ STAT_TX
+ Status bits, for transmission
+ transfers
+ 4
+ 2
+ read-write
+
+
+ DTOG_TX
+ Data Toggle, for transmission
+ transfers
+ 6
+ 1
+ read-write
+
+
+ CTR_TX
+ Correct Transfer for
+ transmission
+ 7
+ 1
+ read-write
+
+
+ EP_KIND
+ Endpoint kind
+ 8
+ 1
+ read-write
+
+
+ EP_TYPE
+ Endpoint type
+ 9
+ 2
+ read-write
+
+
+ SETUP
+ Setup transaction
+ completed
+ 11
+ 1
+ read-only
+
+
+ STAT_RX
+ Status bits, for reception
+ transfers
+ 12
+ 2
+ read-write
+
+
+ DTOG_RX
+ Data Toggle, for reception
+ transfers
+ 14
+ 1
+ read-write
+
+
+ CTR_RX
+ Correct transfer for
+ reception
+ 15
+ 1
+ read-write
+
+
+
+
+ USB_EP7R
+ USB_EP7R
+ endpoint 7 register
+ 0x1C
+ 0x20
+ 0x00000000
+
+
+ EA
+ Endpoint address
+ 0
+ 4
+ read-write
+
+
+ STAT_TX
+ Status bits, for transmission
+ transfers
+ 4
+ 2
+ read-write
+
+
+ DTOG_TX
+ Data Toggle, for transmission
+ transfers
+ 6
+ 1
+ read-write
+
+
+ CTR_TX
+ Correct Transfer for
+ transmission
+ 7
+ 1
+ read-write
+
+
+ EP_KIND
+ Endpoint kind
+ 8
+ 1
+ read-write
+
+
+ EP_TYPE
+ Endpoint type
+ 9
+ 2
+ read-write
+
+
+ SETUP
+ Setup transaction
+ completed
+ 11
+ 1
+ read-only
+
+
+ STAT_RX
+ Status bits, for reception
+ transfers
+ 12
+ 2
+ read-write
+
+
+ DTOG_RX
+ Data Toggle, for reception
+ transfers
+ 14
+ 1
+ read-write
+
+
+ CTR_RX
+ Correct transfer for
+ reception
+ 15
+ 1
+ read-write
+
+
+
+
+ USB_CNTR
+ USB_CNTR
+ control register
+ 0x40
+ 0x20
+ read-write
+ 0x00000003
+
+
+ FRES
+ Force USB Reset
+ 0
+ 1
+
+
+ PDWN
+ Power down
+ 1
+ 1
+
+
+ LPMODE
+ Low-power mode
+ 2
+ 1
+
+
+ FSUSP
+ Force suspend
+ 3
+ 1
+
+
+ RESUME
+ Resume request
+ 4
+ 1
+
+
+ ESOFM
+ Expected start of frame interrupt
+ mask
+ 8
+ 1
+
+
+ SOFM
+ Start of frame interrupt
+ mask
+ 9
+ 1
+
+
+ RESETM
+ USB reset interrupt mask
+ 10
+ 1
+
+
+ SUSPM
+ Suspend mode interrupt
+ mask
+ 11
+ 1
+
+
+ WKUPM
+ Wakeup interrupt mask
+ 12
+ 1
+
+
+ ERRM
+ Error interrupt mask
+ 13
+ 1
+
+
+ PMAOVRM
+ Packet memory area over / underrun
+ interrupt mask
+ 14
+ 1
+
+
+ CTRM
+ Correct transfer interrupt
+ mask
+ 15
+ 1
+
+
+
+
+ ISTR
+ ISTR
+ interrupt status register
+ 0x44
+ 0x20
+ 0x00000000
+
+
+ EP_ID
+ Endpoint Identifier
+ 0
+ 4
+ read-only
+
+
+ DIR
+ Direction of transaction
+ 4
+ 1
+ read-only
+
+
+ ESOF
+ Expected start frame
+ 8
+ 1
+ read-write
+
+
+ SOF
+ start of frame
+ 9
+ 1
+ read-write
+
+
+ RESET
+ reset request
+ 10
+ 1
+ read-write
+
+
+ SUSP
+ Suspend mode request
+ 11
+ 1
+ read-write
+
+
+ WKUP
+ Wakeup
+ 12
+ 1
+ read-write
+
+
+ ERR
+ Error
+ 13
+ 1
+ read-write
+
+
+ PMAOVR
+ Packet memory area over /
+ underrun
+ 14
+ 1
+ read-write
+
+
+ CTR
+ Correct transfer
+ 15
+ 1
+ read-only
+
+
+
+
+ FNR
+ FNR
+ frame number register
+ 0x48
+ 0x20
+ read-only
+ 0x0000
+
+
+ FN
+ Frame number
+ 0
+ 11
+
+
+ LSOF
+ Lost SOF
+ 11
+ 2
+
+
+ LCK
+ Locked
+ 13
+ 1
+
+
+ RXDM
+ Receive data - line status
+ 14
+ 1
+
+
+ RXDP
+ Receive data + line status
+ 15
+ 1
+
+
+
+
+ DADDR
+ DADDR
+ device address
+ 0x4C
+ 0x20
+ read-write
+ 0x0000
+
+
+ ADD
+ Device address
+ 0
+ 1
+
+
+ ADD1
+ Device address
+ 1
+ 1
+
+
+ ADD2
+ Device address
+ 2
+ 1
+
+
+ ADD3
+ Device address
+ 3
+ 1
+
+
+ ADD4
+ Device address
+ 4
+ 1
+
+
+ ADD5
+ Device address
+ 5
+ 1
+
+
+ ADD6
+ Device address
+ 6
+ 1
+
+
+ EF
+ Enable function
+ 7
+ 1
+
+
+
+
+ BTABLE
+ BTABLE
+ Buffer table address
+ 0x50
+ 0x20
+ read-write
+ 0x0000
+
+
+ BTABLE
+ Buffer table
+ 3
+ 13
+
+
+
+
+
+
+ I2C1
+ Inter-integrated circuit
+ I2C
+ 0x40005400
+
+ 0x0
+ 0x400
+ registers
+
+
+ I2C1_EV_EXTI23
+ I2C1 event interrupt and EXTI Line23
+ interrupt
+ 31
+
+
+ I2C1_EV_EXTI23
+ I2C1 event interrupt and EXTI Line23
+ interrupt
+ 31
+
+
+ I2C1_ER
+ I2C1 error interrupt
+ 32
+
+
+
+ CR1
+ CR1
+ Control register 1
+ 0x0
+ 0x20
+ 0x00000000
+
+
+ PE
+ Peripheral enable
+ 0
+ 1
+ read-write
+
+
+ TXIE
+ TX Interrupt enable
+ 1
+ 1
+ read-write
+
+
+ RXIE
+ RX Interrupt enable
+ 2
+ 1
+ read-write
+
+
+ ADDRIE
+ Address match interrupt enable (slave
+ only)
+ 3
+ 1
+ read-write
+
+
+ NACKIE
+ Not acknowledge received interrupt
+ enable
+ 4
+ 1
+ read-write
+
+
+ STOPIE
+ STOP detection Interrupt
+ enable
+ 5
+ 1
+ read-write
+
+
+ TCIE
+ Transfer Complete interrupt
+ enable
+ 6
+ 1
+ read-write
+
+
+ ERRIE
+ Error interrupts enable
+ 7
+ 1
+ read-write
+
+
+ DNF
+ Digital noise filter
+ 8
+ 4
+ read-write
+
+
+ ANFOFF
+ Analog noise filter OFF
+ 12
+ 1
+ read-write
+
+
+ SWRST
+ Software reset
+ 13
+ 1
+ write-only
+
+
+ TXDMAEN
+ DMA transmission requests
+ enable
+ 14
+ 1
+ read-write
+
+
+ RXDMAEN
+ DMA reception requests
+ enable
+ 15
+ 1
+ read-write
+
+
+ SBC
+ Slave byte control
+ 16
+ 1
+ read-write
+
+
+ NOSTRETCH
+ Clock stretching disable
+ 17
+ 1
+ read-write
+
+
+ WUPEN
+ Wakeup from STOP enable
+ 18
+ 1
+ read-write
+
+
+ GCEN
+ General call enable
+ 19
+ 1
+ read-write
+
+
+ SMBHEN
+ SMBus Host address enable
+ 20
+ 1
+ read-write
+
+
+ SMBDEN
+ SMBus Device Default address
+ enable
+ 21
+ 1
+ read-write
+
+
+ ALERTEN
+ SMBUS alert enable
+ 22
+ 1
+ read-write
+
+
+ PECEN
+ PEC enable
+ 23
+ 1
+ read-write
+
+
+
+
+ CR2
+ CR2
+ Control register 2
+ 0x4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PECBYTE
+ Packet error checking byte
+ 26
+ 1
+
+
+ AUTOEND
+ Automatic end mode (master
+ mode)
+ 25
+ 1
+
+
+ RELOAD
+ NBYTES reload mode
+ 24
+ 1
+
+
+ NBYTES
+ Number of bytes
+ 16
+ 8
+
+
+ NACK
+ NACK generation (slave
+ mode)
+ 15
+ 1
+
+
+ STOP
+ Stop generation (master
+ mode)
+ 14
+ 1
+
+
+ START
+ Start generation
+ 13
+ 1
+
+
+ HEAD10R
+ 10-bit address header only read
+ direction (master receiver mode)
+ 12
+ 1
+
+
+ ADD10
+ 10-bit addressing mode (master
+ mode)
+ 11
+ 1
+
+
+ RD_WRN
+ Transfer direction (master
+ mode)
+ 10
+ 1
+
+
+ SADD8
+ Slave address bit 9:8 (master
+ mode)
+ 8
+ 2
+
+
+ SADD1
+ Slave address bit 7:1 (master
+ mode)
+ 1
+ 7
+
+
+ SADD0
+ Slave address bit 0 (master
+ mode)
+ 0
+ 1
+
+
+
+
+ OAR1
+ OAR1
+ Own address register 1
+ 0x8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ OA1_0
+ Interface address
+ 0
+ 1
+
+
+ OA1_1
+ Interface address
+ 1
+ 7
+
+
+ OA1_8
+ Interface address
+ 8
+ 2
+
+
+ OA1MODE
+ Own Address 1 10-bit mode
+ 10
+ 1
+
+
+ OA1EN
+ Own Address 1 enable
+ 15
+ 1
+
+
+
+
+ OAR2
+ OAR2
+ Own address register 2
+ 0xC
+ 0x20
+ read-write
+ 0x00000000
+
+
+ OA2
+ Interface address
+ 1
+ 7
+
+
+ OA2MSK
+ Own Address 2 masks
+ 8
+ 3
+
+
+ OA2EN
+ Own Address 2 enable
+ 15
+ 1
+
+
+
+
+ TIMINGR
+ TIMINGR
+ Timing register
+ 0x10
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SCLL
+ SCL low period (master
+ mode)
+ 0
+ 8
+
+
+ SCLH
+ SCL high period (master
+ mode)
+ 8
+ 8
+
+
+ SDADEL
+ Data hold time
+ 16
+ 4
+
+
+ SCLDEL
+ Data setup time
+ 20
+ 4
+
+
+ PRESC
+ Timing prescaler
+ 28
+ 4
+
+
+
+
+ TIMEOUTR
+ TIMEOUTR
+ Status register 1
+ 0x14
+ 0x20
+ read-write
+ 0x00000000
+
+
+ TIMEOUTA
+ Bus timeout A
+ 0
+ 12
+
+
+ TIDLE
+ Idle clock timeout
+ detection
+ 12
+ 1
+
+
+ TIMOUTEN
+ Clock timeout enable
+ 15
+ 1
+
+
+ TIMEOUTB
+ Bus timeout B
+ 16
+ 12
+
+
+ TEXTEN
+ Extended clock timeout
+ enable
+ 31
+ 1
+
+
+
+
+ ISR
+ ISR
+ Interrupt and Status register
+ 0x18
+ 0x20
+ 0x00000001
+
+
+ ADDCODE
+ Address match code (Slave
+ mode)
+ 17
+ 7
+ read-only
+
+
+ DIR
+ Transfer direction (Slave
+ mode)
+ 16
+ 1
+ read-only
+
+
+ BUSY
+ Bus busy
+ 15
+ 1
+ read-only
+
+
+ ALERT
+ SMBus alert
+ 13
+ 1
+ read-only
+
+
+ TIMEOUT
+ Timeout or t_low detection
+ flag
+ 12
+ 1
+ read-only
+
+
+ PECERR
+ PEC Error in reception
+ 11
+ 1
+ read-only
+
+
+ OVR
+ Overrun/Underrun (slave
+ mode)
+ 10
+ 1
+ read-only
+
+
+ ARLO
+ Arbitration lost
+ 9
+ 1
+ read-only
+
+
+ BERR
+ Bus error
+ 8
+ 1
+ read-only
+
+
+ TCR
+ Transfer Complete Reload
+ 7
+ 1
+ read-only
+
+
+ TC
+ Transfer Complete (master
+ mode)
+ 6
+ 1
+ read-only
+
+
+ STOPF
+ Stop detection flag
+ 5
+ 1
+ read-only
+
+
+ NACKF
+ Not acknowledge received
+ flag
+ 4
+ 1
+ read-only
+
+
+ ADDR
+ Address matched (slave
+ mode)
+ 3
+ 1
+ read-only
+
+
+ RXNE
+ Receive data register not empty
+ (receivers)
+ 2
+ 1
+ read-only
+
+
+ TXIS
+ Transmit interrupt status
+ (transmitters)
+ 1
+ 1
+ read-write
+
+
+ TXE
+ Transmit data register empty
+ (transmitters)
+ 0
+ 1
+ read-write
+
+
+
+
+ ICR
+ ICR
+ Interrupt clear register
+ 0x1C
+ 0x20
+ write-only
+ 0x00000000
+
+
+ ALERTCF
+ Alert flag clear
+ 13
+ 1
+
+
+ TIMOUTCF
+ Timeout detection flag
+ clear
+ 12
+ 1
+
+
+ PECCF
+ PEC Error flag clear
+ 11
+ 1
+
+
+ OVRCF
+ Overrun/Underrun flag
+ clear
+ 10
+ 1
+
+
+ ARLOCF
+ Arbitration lost flag
+ clear
+ 9
+ 1
+
+
+ BERRCF
+ Bus error flag clear
+ 8
+ 1
+
+
+ STOPCF
+ Stop detection flag clear
+ 5
+ 1
+
+
+ NACKCF
+ Not Acknowledge flag clear
+ 4
+ 1
+
+
+ ADDRCF
+ Address Matched flag clear
+ 3
+ 1
+
+
+
+
+ PECR
+ PECR
+ PEC register
+ 0x20
+ 0x20
+ read-only
+ 0x00000000
+
+
+ PEC
+ Packet error checking
+ register
+ 0
+ 8
+
+
+
+
+ RXDR
+ RXDR
+ Receive data register
+ 0x24
+ 0x20
+ read-only
+ 0x00000000
+
+
+ RXDATA
+ 8-bit receive data
+ 0
+ 8
+
+
+
+
+ TXDR
+ TXDR
+ Transmit data register
+ 0x28
+ 0x20
+ read-write
+ 0x00000000
+
+
+ TXDATA
+ 8-bit transmit data
+ 0
+ 8
+
+
+
+
+
+
+ I2C2
+ 0x40005800
+
+ I2C2_EV_EXTI24
+ I2C2 event interrupt & EXTI Line24
+ interrupt
+ 33
+
+
+ I2C2_ER
+ I2C2 error interrupt
+ 34
+
+
+
+ I2C3
+ 0x40007800
+
+ I2C3_EV
+ I2C3 Event interrupt
+ 72
+
+
+ I2C3_ER
+ I2C3 Error interrupt
+ 73
+
+
+
+ IWDG
+ Independent watchdog
+ IWDG
+ 0x40003000
+
+ 0x0
+ 0x400
+ registers
+
+
+
+ KR
+ KR
+ Key register
+ 0x0
+ 0x20
+ write-only
+ 0x00000000
+
+
+ KEY
+ Key value
+ 0
+ 16
+
+
+
+
+ PR
+ PR
+ Prescaler register
+ 0x4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PR
+ Prescaler divider
+ 0
+ 3
+
+
+
+
+ RLR
+ RLR
+ Reload register
+ 0x8
+ 0x20
+ read-write
+ 0x00000FFF
+
+
+ RL
+ Watchdog counter reload
+ value
+ 0
+ 12
+
+
+
+
+ SR
+ SR
+ Status register
+ 0xC
+ 0x20
+ read-only
+ 0x00000000
+
+
+ PVU
+ Watchdog prescaler value
+ update
+ 0
+ 1
+
+
+ RVU
+ Watchdog counter reload value
+ update
+ 1
+ 1
+
+
+ WVU
+ Watchdog counter window value
+ update
+ 2
+ 1
+
+
+
+
+ WINR
+ WINR
+ Window register
+ 0x10
+ 0x20
+ read-write
+ 0x00000FFF
+
+
+ WIN
+ Watchdog counter window
+ value
+ 0
+ 12
+
+
+
+
+
+
+ WWDG
+ Window watchdog
+ WWDG
+ 0x40002C00
+
+ 0x0
+ 0x400
+ registers
+
+
+ WWDG
+ Window Watchdog interrupt
+ 0
+
+
+
+ CR
+ CR
+ Control register
+ 0x0
+ 0x20
+ read-write
+ 0x0000007F
+
+
+ T
+ 7-bit counter
+ 0
+ 7
+
+
+ WDGA
+ Activation bit
+ 7
+ 1
+
+
+
+
+ CFR
+ CFR
+ Configuration register
+ 0x4
+ 0x20
+ read-write
+ 0x0000007F
+
+
+ EWI
+ Early wakeup interrupt
+ 9
+ 1
+
+
+ WDGTB
+ Timer base
+ 7
+ 2
+
+
+ W
+ 7-bit window value
+ 0
+ 7
+
+
+
+
+ SR
+ SR
+ Status register
+ 0x8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ EWIF
+ Early wakeup interrupt
+ flag
+ 0
+ 1
+
+
+
+
+
+
+ RTC
+ Real-time clock
+ RTC
+ 0x40002800
+
+ 0x0
+ 0x400
+ registers
+
+
+ RTC_WKUP
+ RTC Wakeup interrupt through the EXTI
+ line
+ 3
+
+
+ RTCAlarm
+ RTC alarm interrupt
+ 41
+
+
+
+ TR
+ TR
+ time register
+ 0x0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PM
+ AM/PM notation
+ 22
+ 1
+
+
+ HT
+ Hour tens in BCD format
+ 20
+ 2
+
+
+ HU
+ Hour units in BCD format
+ 16
+ 4
+
+
+ MNT
+ Minute tens in BCD format
+ 12
+ 3
+
+
+ MNU
+ Minute units in BCD format
+ 8
+ 4
+
+
+ ST
+ Second tens in BCD format
+ 4
+ 3
+
+
+ SU
+ Second units in BCD format
+ 0
+ 4
+
+
+
+
+ DR
+ DR
+ date register
+ 0x4
+ 0x20
+ read-write
+ 0x00002101
+
+
+ YT
+ Year tens in BCD format
+ 20
+ 4
+
+
+ YU
+ Year units in BCD format
+ 16
+ 4
+
+
+ WDU
+ Week day units
+ 13
+ 3
+
+
+ MT
+ Month tens in BCD format
+ 12
+ 1
+
+
+ MU
+ Month units in BCD format
+ 8
+ 4
+
+
+ DT
+ Date tens in BCD format
+ 4
+ 2
+
+
+ DU
+ Date units in BCD format
+ 0
+ 4
+
+
+
+
+ CR
+ CR
+ control register
+ 0x8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ WCKSEL
+ Wakeup clock selection
+ 0
+ 3
+
+
+ TSEDGE
+ Time-stamp event active
+ edge
+ 3
+ 1
+
+
+ REFCKON
+ Reference clock detection enable (50 or
+ 60 Hz)
+ 4
+ 1
+
+
+ BYPSHAD
+ Bypass the shadow
+ registers
+ 5
+ 1
+
+
+ FMT
+ Hour format
+ 6
+ 1
+
+
+ ALRAE
+ Alarm A enable
+ 8
+ 1
+
+
+ ALRBE
+ Alarm B enable
+ 9
+ 1
+
+
+ WUTE
+ Wakeup timer enable
+ 10
+ 1
+
+
+ TSE
+ Time stamp enable
+ 11
+ 1
+
+
+ ALRAIE
+ Alarm A interrupt enable
+ 12
+ 1
+
+
+ ALRBIE
+ Alarm B interrupt enable
+ 13
+ 1
+
+
+ WUTIE
+ Wakeup timer interrupt
+ enable
+ 14
+ 1
+
+
+ TSIE
+ Time-stamp interrupt
+ enable
+ 15
+ 1
+
+
+ ADD1H
+ Add 1 hour (summer time
+ change)
+ 16
+ 1
+
+
+ SUB1H
+ Subtract 1 hour (winter time
+ change)
+ 17
+ 1
+
+
+ BKP
+ Backup
+ 18
+ 1
+
+
+ COSEL
+ Calibration output
+ selection
+ 19
+ 1
+
+
+ POL
+ Output polarity
+ 20
+ 1
+
+
+ OSEL
+ Output selection
+ 21
+ 2
+
+
+ COE
+ Calibration output enable
+ 23
+ 1
+
+
+
+
+ ISR
+ ISR
+ initialization and status
+ register
+ 0xC
+ 0x20
+ 0x00000007
+
+
+ ALRAWF
+ Alarm A write flag
+ 0
+ 1
+ read-only
+
+
+ ALRBWF
+ Alarm B write flag
+ 1
+ 1
+ read-only
+
+
+ WUTWF
+ Wakeup timer write flag
+ 2
+ 1
+ read-only
+
+
+ SHPF
+ Shift operation pending
+ 3
+ 1
+ read-write
+
+
+ INITS
+ Initialization status flag
+ 4
+ 1
+ read-only
+
+
+ RSF
+ Registers synchronization
+ flag
+ 5
+ 1
+ read-write
+
+
+ INITF
+ Initialization flag
+ 6
+ 1
+ read-only
+
+
+ INIT
+ Initialization mode
+ 7
+ 1
+ read-write
+
+
+ ALRAF
+ Alarm A flag
+ 8
+ 1
+ read-write
+
+
+ ALRBF
+ Alarm B flag
+ 9
+ 1
+ read-write
+
+
+ WUTF
+ Wakeup timer flag
+ 10
+ 1
+ read-write
+
+
+ TSF
+ Time-stamp flag
+ 11
+ 1
+ read-write
+
+
+ TSOVF
+ Time-stamp overflow flag
+ 12
+ 1
+ read-write
+
+
+ TAMP1F
+ Tamper detection flag
+ 13
+ 1
+ read-write
+
+
+ TAMP2F
+ RTC_TAMP2 detection flag
+ 14
+ 1
+ read-write
+
+
+ TAMP3F
+ RTC_TAMP3 detection flag
+ 15
+ 1
+ read-write
+
+
+ RECALPF
+ Recalibration pending Flag
+ 16
+ 1
+ read-only
+
+
+
+
+ PRER
+ PRER
+ prescaler register
+ 0x10
+ 0x20
+ read-write
+ 0x007F00FF
+
+
+ PREDIV_A
+ Asynchronous prescaler
+ factor
+ 16
+ 7
+
+
+ PREDIV_S
+ Synchronous prescaler
+ factor
+ 0
+ 15
+
+
+
+
+ WUTR
+ WUTR
+ wakeup timer register
+ 0x14
+ 0x20
+ read-write
+ 0x0000FFFF
+
+
+ WUT
+ Wakeup auto-reload value
+ bits
+ 0
+ 16
+
+
+
+
+ ALRMAR
+ ALRMAR
+ alarm A register
+ 0x1C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MSK4
+ Alarm A date mask
+ 31
+ 1
+
+
+ WDSEL
+ Week day selection
+ 30
+ 1
+
+
+ DT
+ Date tens in BCD format
+ 28
+ 2
+
+
+ DU
+ Date units or day in BCD
+ format
+ 24
+ 4
+
+
+ MSK3
+ Alarm A hours mask
+ 23
+ 1
+
+
+ PM
+ AM/PM notation
+ 22
+ 1
+
+
+ HT
+ Hour tens in BCD format
+ 20
+ 2
+
+
+ HU
+ Hour units in BCD format
+ 16
+ 4
+
+
+ MSK2
+ Alarm A minutes mask
+ 15
+ 1
+
+
+ MNT
+ Minute tens in BCD format
+ 12
+ 3
+
+
+ MNU
+ Minute units in BCD format
+ 8
+ 4
+
+
+ MSK1
+ Alarm A seconds mask
+ 7
+ 1
+
+
+ ST
+ Second tens in BCD format
+ 4
+ 3
+
+
+ SU
+ Second units in BCD format
+ 0
+ 4
+
+
+
+
+ ALRMBR
+ ALRMBR
+ alarm B register
+ 0x20
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MSK4
+ Alarm B date mask
+ 31
+ 1
+
+
+ WDSEL
+ Week day selection
+ 30
+ 1
+
+
+ DT
+ Date tens in BCD format
+ 28
+ 2
+
+
+ DU
+ Date units or day in BCD
+ format
+ 24
+ 4
+
+
+ MSK3
+ Alarm B hours mask
+ 23
+ 1
+
+
+ PM
+ AM/PM notation
+ 22
+ 1
+
+
+ HT
+ Hour tens in BCD format
+ 20
+ 2
+
+
+ HU
+ Hour units in BCD format
+ 16
+ 4
+
+
+ MSK2
+ Alarm B minutes mask
+ 15
+ 1
+
+
+ MNT
+ Minute tens in BCD format
+ 12
+ 3
+
+
+ MNU
+ Minute units in BCD format
+ 8
+ 4
+
+
+ MSK1
+ Alarm B seconds mask
+ 7
+ 1
+
+
+ ST
+ Second tens in BCD format
+ 4
+ 3
+
+
+ SU
+ Second units in BCD format
+ 0
+ 4
+
+
+
+
+ WPR
+ WPR
+ write protection register
+ 0x24
+ 0x20
+ write-only
+ 0x00000000
+
+
+ KEY
+ Write protection key
+ 0
+ 8
+
+
+
+
+ SSR
+ SSR
+ sub second register
+ 0x28
+ 0x20
+ read-only
+ 0x00000000
+
+
+ SS
+ Sub second value
+ 0
+ 16
+
+
+
+
+ SHIFTR
+ SHIFTR
+ shift control register
+ 0x2C
+ 0x20
+ write-only
+ 0x00000000
+
+
+ ADD1S
+ Add one second
+ 31
+ 1
+
+
+ SUBFS
+ Subtract a fraction of a
+ second
+ 0
+ 15
+
+
+
+
+ TSTR
+ TSTR
+ time stamp time register
+ 0x30
+ 0x20
+ read-only
+ 0x00000000
+
+
+ SU
+ Second units in BCD format
+ 0
+ 4
+
+
+ ST
+ Second tens in BCD format
+ 4
+ 3
+
+
+ MNU
+ Minute units in BCD format
+ 8
+ 4
+
+
+ MNT
+ Minute tens in BCD format
+ 12
+ 3
+
+
+ HU
+ Hour units in BCD format
+ 16
+ 4
+
+
+ HT
+ Hour tens in BCD format
+ 20
+ 2
+
+
+ PM
+ AM/PM notation
+ 22
+ 1
+
+
+
+
+ TSDR
+ TSDR
+ time stamp date register
+ 0x34
+ 0x20
+ read-only
+ 0x00000000
+
+
+ WDU
+ Week day units
+ 13
+ 3
+
+
+ MT
+ Month tens in BCD format
+ 12
+ 1
+
+
+ MU
+ Month units in BCD format
+ 8
+ 4
+
+
+ DT
+ Date tens in BCD format
+ 4
+ 2
+
+
+ DU
+ Date units in BCD format
+ 0
+ 4
+
+
+
+
+ TSSSR
+ TSSSR
+ timestamp sub second register
+ 0x38
+ 0x20
+ read-only
+ 0x00000000
+
+
+ SS
+ Sub second value
+ 0
+ 16
+
+
+
+
+ CALR
+ CALR
+ calibration register
+ 0x3C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CALP
+ Increase frequency of RTC by 488.5
+ ppm
+ 15
+ 1
+
+
+ CALW8
+ Use an 8-second calibration cycle
+ period
+ 14
+ 1
+
+
+ CALW16
+ Use a 16-second calibration cycle
+ period
+ 13
+ 1
+
+
+ CALM
+ Calibration minus
+ 0
+ 9
+
+
+
+
+ TAFCR
+ TAFCR
+ tamper and alternate function configuration
+ register
+ 0x40
+ 0x20
+ read-write
+ 0x00000000
+
+
+ TAMP1E
+ Tamper 1 detection enable
+ 0
+ 1
+
+
+ TAMP1TRG
+ Active level for tamper 1
+ 1
+ 1
+
+
+ TAMPIE
+ Tamper interrupt enable
+ 2
+ 1
+
+
+ TAMP2E
+ Tamper 2 detection enable
+ 3
+ 1
+
+
+ TAMP2TRG
+ Active level for tamper 2
+ 4
+ 1
+
+
+ TAMP3E
+ Tamper 3 detection enable
+ 5
+ 1
+
+
+ TAMP3TRG
+ Active level for tamper 3
+ 6
+ 1
+
+
+ TAMPTS
+ Activate timestamp on tamper detection
+ event
+ 7
+ 1
+
+
+ TAMPFREQ
+ Tamper sampling frequency
+ 8
+ 3
+
+
+ TAMPFLT
+ Tamper filter count
+ 11
+ 2
+
+
+ TAMPPRCH
+ Tamper precharge duration
+ 13
+ 2
+
+
+ TAMPPUDIS
+ TAMPER pull-up disable
+ 15
+ 1
+
+
+ PC13VALUE
+ PC13 value
+ 18
+ 1
+
+
+ PC13MODE
+ PC13 mode
+ 19
+ 1
+
+
+ PC14VALUE
+ PC14 value
+ 20
+ 1
+
+
+ PC14MODE
+ PC 14 mode
+ 21
+ 1
+
+
+ PC15VALUE
+ PC15 value
+ 22
+ 1
+
+
+ PC15MODE
+ PC15 mode
+ 23
+ 1
+
+
+
+
+ ALRMASSR
+ ALRMASSR
+ alarm A sub second register
+ 0x44
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MASKSS
+ Mask the most-significant bits starting
+ at this bit
+ 24
+ 4
+
+
+ SS
+ Sub seconds value
+ 0
+ 15
+
+
+
+
+ ALRMBSSR
+ ALRMBSSR
+ alarm B sub second register
+ 0x48
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MASKSS
+ Mask the most-significant bits starting
+ at this bit
+ 24
+ 4
+
+
+ SS
+ Sub seconds value
+ 0
+ 15
+
+
+
+
+ BKP0R
+ BKP0R
+ backup register
+ 0x50
+ 0x20
+ read-write
+ 0x00000000
+
+
+ BKP
+ BKP
+ 0
+ 32
+
+
+
+
+ BKP1R
+ BKP1R
+ backup register
+ 0x54
+ 0x20
+ read-write
+ 0x00000000
+
+
+ BKP
+ BKP
+ 0
+ 32
+
+
+
+
+ BKP2R
+ BKP2R
+ backup register
+ 0x58
+ 0x20
+ read-write
+ 0x00000000
+
+
+ BKP
+ BKP
+ 0
+ 32
+
+
+
+
+ BKP3R
+ BKP3R
+ backup register
+ 0x5C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ BKP
+ BKP
+ 0
+ 32
+
+
+
+
+ BKP4R
+ BKP4R
+ backup register
+ 0x60
+ 0x20
+ read-write
+ 0x00000000
+
+
+ BKP
+ BKP
+ 0
+ 32
+
+
+
+
+ BKP5R
+ BKP5R
+ backup register
+ 0x64
+ 0x20
+ read-write
+ 0x00000000
+
+
+ BKP
+ BKP
+ 0
+ 32
+
+
+
+
+ BKP6R
+ BKP6R
+ backup register
+ 0x68
+ 0x20
+ read-write
+ 0x00000000
+
+
+ BKP
+ BKP
+ 0
+ 32
+
+
+
+
+ BKP7R
+ BKP7R
+ backup register
+ 0x6C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ BKP
+ BKP
+ 0
+ 32
+
+
+
+
+ BKP8R
+ BKP8R
+ backup register
+ 0x70
+ 0x20
+ read-write
+ 0x00000000
+
+
+ BKP
+ BKP
+ 0
+ 32
+
+
+
+
+ BKP9R
+ BKP9R
+ backup register
+ 0x74
+ 0x20
+ read-write
+ 0x00000000
+
+
+ BKP
+ BKP
+ 0
+ 32
+
+
+
+
+ BKP10R
+ BKP10R
+ backup register
+ 0x78
+ 0x20
+ read-write
+ 0x00000000
+
+
+ BKP
+ BKP
+ 0
+ 32
+
+
+
+
+ BKP11R
+ BKP11R
+ backup register
+ 0x7C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ BKP
+ BKP
+ 0
+ 32
+
+
+
+
+ BKP12R
+ BKP12R
+ backup register
+ 0x80
+ 0x20
+ read-write
+ 0x00000000
+
+
+ BKP
+ BKP
+ 0
+ 32
+
+
+
+
+ BKP13R
+ BKP13R
+ backup register
+ 0x84
+ 0x20
+ read-write
+ 0x00000000
+
+
+ BKP
+ BKP
+ 0
+ 32
+
+
+
+
+ BKP14R
+ BKP14R
+ backup register
+ 0x88
+ 0x20
+ read-write
+ 0x00000000
+
+
+ BKP
+ BKP
+ 0
+ 32
+
+
+
+
+ BKP15R
+ BKP15R
+ backup register
+ 0x8C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ BKP
+ BKP
+ 0
+ 32
+
+
+
+
+ BKP16R
+ BKP16R
+ backup register
+ 0x90
+ 0x20
+ read-write
+ 0x00000000
+
+
+ BKP
+ BKP
+ 0
+ 32
+
+
+
+
+ BKP17R
+ BKP17R
+ backup register
+ 0x94
+ 0x20
+ read-write
+ 0x00000000
+
+
+ BKP
+ BKP
+ 0
+ 32
+
+
+
+
+ BKP18R
+ BKP18R
+ backup register
+ 0x98
+ 0x20
+ read-write
+ 0x00000000
+
+
+ BKP
+ BKP
+ 0
+ 32
+
+
+
+
+ BKP19R
+ BKP19R
+ backup register
+ 0x9C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ BKP
+ BKP
+ 0
+ 32
+
+
+
+
+ BKP20R
+ BKP20R
+ backup register
+ 0xA0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ BKP
+ BKP
+ 0
+ 32
+
+
+
+
+ BKP21R
+ BKP21R
+ backup register
+ 0xA4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ BKP
+ BKP
+ 0
+ 32
+
+
+
+
+ BKP22R
+ BKP22R
+ backup register
+ 0xA8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ BKP
+ BKP
+ 0
+ 32
+
+
+
+
+ BKP23R
+ BKP23R
+ backup register
+ 0xAC
+ 0x20
+ read-write
+ 0x00000000
+
+
+ BKP
+ BKP
+ 0
+ 32
+
+
+
+
+ BKP24R
+ BKP24R
+ backup register
+ 0xB0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ BKP
+ BKP
+ 0
+ 32
+
+
+
+
+ BKP25R
+ BKP25R
+ backup register
+ 0xB4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ BKP
+ BKP
+ 0
+ 32
+
+
+
+
+ BKP26R
+ BKP26R
+ backup register
+ 0xB8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ BKP
+ BKP
+ 0
+ 32
+
+
+
+
+ BKP27R
+ BKP27R
+ backup register
+ 0xBC
+ 0x20
+ read-write
+ 0x00000000
+
+
+ BKP
+ BKP
+ 0
+ 32
+
+
+
+
+ BKP28R
+ BKP28R
+ backup register
+ 0xC0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ BKP
+ BKP
+ 0
+ 32
+
+
+
+
+ BKP29R
+ BKP29R
+ backup register
+ 0xC4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ BKP
+ BKP
+ 0
+ 32
+
+
+
+
+ BKP30R
+ BKP30R
+ backup register
+ 0xC8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ BKP
+ BKP
+ 0
+ 32
+
+
+
+
+ BKP31R
+ BKP31R
+ backup register
+ 0xCC
+ 0x20
+ read-write
+ 0x00000000
+
+
+ BKP
+ BKP
+ 0
+ 32
+
+
+
+
+
+
+ TIM6
+ Basic timers
+ TIMs
+ 0x40001000
+
+ 0x0
+ 0x400
+ registers
+
+
+ TIM6_DACUNDER
+ TIM6 global and DAC12 underrun
+ interrupts
+ 54
+
+
+
+ CR1
+ CR1
+ control register 1
+ 0x0
+ 0x20
+ read-write
+ 0x0000
+
+
+ CEN
+ Counter enable
+ 0
+ 1
+
+
+ UDIS
+ Update disable
+ 1
+ 1
+
+
+ URS
+ Update request source
+ 2
+ 1
+
+
+ OPM
+ One-pulse mode
+ 3
+ 1
+
+
+ ARPE
+ Auto-reload preload enable
+ 7
+ 1
+
+
+ UIFREMAP
+ UIF status bit remapping
+ 11
+ 1
+
+
+
+
+ CR2
+ CR2
+ control register 2
+ 0x4
+ 0x20
+ read-write
+ 0x0000
+
+
+ MMS
+ Master mode selection
+ 4
+ 3
+
+
+
+
+ DIER
+ DIER
+ DMA/Interrupt enable register
+ 0xC
+ 0x20
+ read-write
+ 0x0000
+
+
+ UDE
+ Update DMA request enable
+ 8
+ 1
+
+
+ UIE
+ Update interrupt enable
+ 0
+ 1
+
+
+
+
+ SR
+ SR
+ status register
+ 0x10
+ 0x20
+ read-write
+ 0x0000
+
+
+ UIF
+ Update interrupt flag
+ 0
+ 1
+
+
+
+
+ EGR
+ EGR
+ event generation register
+ 0x14
+ 0x20
+ write-only
+ 0x0000
+
+
+ UG
+ Update generation
+ 0
+ 1
+
+
+
+
+ CNT
+ CNT
+ counter
+ 0x24
+ 0x20
+ 0x00000000
+
+
+ CNT
+ Low counter value
+ 0
+ 16
+ read-write
+
+
+ UIFCPY
+ UIF Copy
+ 31
+ 1
+ read-only
+
+
+
+
+ PSC
+ PSC
+ prescaler
+ 0x28
+ 0x20
+ read-write
+ 0x0000
+
+
+ PSC
+ Prescaler value
+ 0
+ 16
+
+
+
+
+ ARR
+ ARR
+ auto-reload register
+ 0x2C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ ARR
+ Low Auto-reload value
+ 0
+ 16
+
+
+
+
+
+
+ TIM7
+ 0x40001400
+
+ TIM7
+ TIM7 global interrupt
+ 55
+
+
+
+ DAC
+ Digital-to-analog converter
+ DAC
+ 0x40007400
+
+ 0x0
+ 0x400
+ registers
+
+
+
+ CR
+ CR
+ control register
+ 0x0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ DMAUDRIE2
+ DAC channel2 DMA underrun interrupt
+ enable
+ 29
+ 1
+
+
+ DMAEN2
+ DAC channel2 DMA enable
+ 28
+ 1
+
+
+ MAMP2
+ DAC channel2 mask/amplitude
+ selector
+ 24
+ 4
+
+
+ WAVE2
+ DAC channel2 noise/triangle wave
+ generation enable
+ 22
+ 2
+
+
+ TSEL2
+ DAC channel2 trigger
+ selection
+ 19
+ 3
+
+
+ TEN2
+ DAC channel2 trigger
+ enable
+ 18
+ 1
+
+
+ BOFF2
+ DAC channel2 output buffer
+ disable
+ 17
+ 1
+
+
+ EN2
+ DAC channel2 enable
+ 16
+ 1
+
+
+ DMAUDRIE1
+ DAC channel1 DMA Underrun Interrupt
+ enable
+ 13
+ 1
+
+
+ DMAEN1
+ DAC channel1 DMA enable
+ 12
+ 1
+
+
+ MAMP1
+ DAC channel1 mask/amplitude
+ selector
+ 8
+ 4
+
+
+ WAVE1
+ DAC channel1 noise/triangle wave
+ generation enable
+ 6
+ 2
+
+
+ TSEL1
+ DAC channel1 trigger
+ selection
+ 3
+ 3
+
+
+ TEN1
+ DAC channel1 trigger
+ enable
+ 2
+ 1
+
+
+ BOFF1
+ DAC channel1 output buffer
+ disable
+ 1
+ 1
+
+
+ EN1
+ DAC channel1 enable
+ 0
+ 1
+
+
+
+
+ SWTRIGR
+ SWTRIGR
+ software trigger register
+ 0x4
+ 0x20
+ write-only
+ 0x00000000
+
+
+ SWTRIG2
+ DAC channel2 software
+ trigger
+ 1
+ 1
+
+
+ SWTRIG1
+ DAC channel1 software
+ trigger
+ 0
+ 1
+
+
+
+
+ DHR12R1
+ DHR12R1
+ channel1 12-bit right-aligned data holding
+ register
+ 0x8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ DACC1DHR
+ DAC channel1 12-bit right-aligned
+ data
+ 0
+ 12
+
+
+
+
+ DHR12L1
+ DHR12L1
+ channel1 12-bit left aligned data holding
+ register
+ 0xC
+ 0x20
+ read-write
+ 0x00000000
+
+
+ DACC1DHR
+ DAC channel1 12-bit left-aligned
+ data
+ 4
+ 12
+
+
+
+
+ DHR8R1
+ DHR8R1
+ channel1 8-bit right aligned data holding
+ register
+ 0x10
+ 0x20
+ read-write
+ 0x00000000
+
+
+ DACC1DHR
+ DAC channel1 8-bit right-aligned
+ data
+ 0
+ 8
+
+
+
+
+ DHR12R2
+ DHR12R2
+ channel2 12-bit right aligned data holding
+ register
+ 0x14
+ 0x20
+ read-write
+ 0x00000000
+
+
+ DACC2DHR
+ DAC channel2 12-bit right-aligned
+ data
+ 0
+ 12
+
+
+
+
+ DHR12L2
+ DHR12L2
+ channel2 12-bit left aligned data holding
+ register
+ 0x18
+ 0x20
+ read-write
+ 0x00000000
+
+
+ DACC2DHR
+ DAC channel2 12-bit left-aligned
+ data
+ 4
+ 12
+
+
+
+
+ DHR8R2
+ DHR8R2
+ channel2 8-bit right-aligned data holding
+ register
+ 0x1C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ DACC2DHR
+ DAC channel2 8-bit right-aligned
+ data
+ 0
+ 8
+
+
+
+
+ DHR12RD
+ DHR12RD
+ Dual DAC 12-bit right-aligned data holding
+ register
+ 0x20
+ 0x20
+ read-write
+ 0x00000000
+
+
+ DACC2DHR
+ DAC channel2 12-bit right-aligned
+ data
+ 16
+ 12
+
+
+ DACC1DHR
+ DAC channel1 12-bit right-aligned
+ data
+ 0
+ 12
+
+
+
+
+ DHR12LD
+ DHR12LD
+ DUAL DAC 12-bit left aligned data holding
+ register
+ 0x24
+ 0x20
+ read-write
+ 0x00000000
+
+
+ DACC2DHR
+ DAC channel2 12-bit left-aligned
+ data
+ 20
+ 12
+
+
+ DACC1DHR
+ DAC channel1 12-bit left-aligned
+ data
+ 4
+ 12
+
+
+
+
+ DHR8RD
+ DHR8RD
+ DUAL DAC 8-bit right aligned data holding
+ register
+ 0x28
+ 0x20
+ read-write
+ 0x00000000
+
+
+ DACC2DHR
+ DAC channel2 8-bit right-aligned
+ data
+ 8
+ 8
+
+
+ DACC1DHR
+ DAC channel1 8-bit right-aligned
+ data
+ 0
+ 8
+
+
+
+
+ DOR1
+ DOR1
+ channel1 data output register
+ 0x2C
+ 0x20
+ read-only
+ 0x00000000
+
+
+ DACC1DOR
+ DAC channel1 data output
+ 0
+ 12
+
+
+
+
+ DOR2
+ DOR2
+ channel2 data output register
+ 0x30
+ 0x20
+ read-only
+ 0x00000000
+
+
+ DACC2DOR
+ DAC channel2 data output
+ 0
+ 12
+
+
+
+
+ SR
+ SR
+ status register
+ 0x34
+ 0x20
+ read-write
+ 0x00000000
+
+
+ DMAUDR2
+ DAC channel2 DMA underrun
+ flag
+ 29
+ 1
+
+
+ DMAUDR1
+ DAC channel1 DMA underrun
+ flag
+ 13
+ 1
+
+
+
+
+
+
+ DBGMCU
+ Debug support
+ DBGMCU
+ 0xE0042000
+
+ 0x0
+ 0x400
+ registers
+
+
+
+ IDCODE
+ IDCODE
+ MCU Device ID Code Register
+ 0x0
+ 0x20
+ read-only
+ 0x0
+
+
+ DEV_ID
+ Device Identifier
+ 0
+ 12
+
+
+ REV_ID
+ Revision Identifier
+ 16
+ 16
+
+
+
+
+ CR
+ CR
+ Debug MCU Configuration
+ Register
+ 0x4
+ 0x20
+ read-write
+ 0x0
+
+
+ DBG_SLEEP
+ Debug Sleep mode
+ 0
+ 1
+
+
+ DBG_STOP
+ Debug Stop Mode
+ 1
+ 1
+
+
+ DBG_STANDBY
+ Debug Standby Mode
+ 2
+ 1
+
+
+ TRACE_IOEN
+ Trace pin assignment
+ control
+ 5
+ 1
+
+
+ TRACE_MODE
+ Trace pin assignment
+ control
+ 6
+ 2
+
+
+
+
+ APB1FZ
+ APB1FZ
+ APB Low Freeze Register
+ 0x8
+ 0x20
+ read-write
+ 0x0
+
+
+ DBG_TIM2_STOP
+ Debug Timer 2 stopped when Core is
+ halted
+ 0
+ 1
+
+
+ DBG_TIM3_STOP
+ Debug Timer 3 stopped when Core is
+ halted
+ 1
+ 1
+
+
+ DBG_TIM4_STOP
+ Debug Timer 4 stopped when Core is
+ halted
+ 2
+ 1
+
+
+ DBG_TIM5_STOP
+ Debug Timer 5 stopped when Core is
+ halted
+ 3
+ 1
+
+
+ DBG_TIM6_STOP
+ Debug Timer 6 stopped when Core is
+ halted
+ 4
+ 1
+
+
+ DBG_TIM7_STOP
+ Debug Timer 7 stopped when Core is
+ halted
+ 5
+ 1
+
+
+ DBG_TIM12_STOP
+ Debug Timer 12 stopped when Core is
+ halted
+ 6
+ 1
+
+
+ DBG_TIM13_STOP
+ Debug Timer 13 stopped when Core is
+ halted
+ 7
+ 1
+
+
+ DBG_TIMER14_STOP
+ Debug Timer 14 stopped when Core is
+ halted
+ 8
+ 1
+
+
+ DBG_TIM18_STOP
+ Debug Timer 18 stopped when Core is
+ halted
+ 9
+ 1
+
+
+ DBG_RTC_STOP
+ Debug RTC stopped when Core is
+ halted
+ 10
+ 1
+
+
+ DBG_WWDG_STOP
+ Debug Window Wachdog stopped when Core
+ is halted
+ 11
+ 1
+
+
+ DBG_IWDG_STOP
+ Debug Independent Wachdog stopped when
+ Core is halted
+ 12
+ 1
+
+
+ I2C1_SMBUS_TIMEOUT
+ SMBUS timeout mode stopped when Core is
+ halted
+ 21
+ 1
+
+
+ I2C2_SMBUS_TIMEOUT
+ SMBUS timeout mode stopped when Core is
+ halted
+ 22
+ 1
+
+
+ DBG_CAN_STOP
+ Debug CAN stopped when core is
+ halted
+ 25
+ 1
+
+
+
+
+ APB2FZ
+ APB2FZ
+ APB High Freeze Register
+ 0xC
+ 0x20
+ read-write
+ 0x0
+
+
+ DBG_TIM15_STOP
+ Debug Timer 15 stopped when Core is
+ halted
+ 2
+ 1
+
+
+ DBG_TIM16_STOP
+ Debug Timer 16 stopped when Core is
+ halted
+ 3
+ 1
+
+
+ DBG_TIM17_STO
+ Debug Timer 17 stopped when Core is
+ halted
+ 4
+ 1
+
+
+ DBG_TIM19_STOP
+ Debug Timer 19 stopped when Core is
+ halted
+ 5
+ 1
+
+
+
+
+
+
+ TIM1
+ Advanced timer
+ TIMs
+ 0x40012C00
+
+ 0x0
+ 0x400
+ registers
+
+
+ TIM1_BRK_TIM15
+ TIM1 Break/TIM15 global
+ interruts
+ 24
+
+
+ TIM1_UP_TIM16
+ TIM1 Update/TIM16 global
+ interrupts
+ 25
+
+
+ TIM1_TRG_COM_TIM17
+ TIM1 trigger and commutation/TIM17
+ interrupts
+ 26
+
+
+
+ CR1
+ CR1
+ control register 1
+ 0x0
+ 0x20
+ read-write
+ 0x0000
+
+
+ CEN
+ Counter enable
+ 0
+ 1
+
+
+ UDIS
+ Update disable
+ 1
+ 1
+
+
+ URS
+ Update request source
+ 2
+ 1
+
+
+ OPM
+ One-pulse mode
+ 3
+ 1
+
+
+ DIR
+ Direction
+ 4
+ 1
+
+
+ CMS
+ Center-aligned mode
+ selection
+ 5
+ 2
+
+
+ ARPE
+ Auto-reload preload enable
+ 7
+ 1
+
+
+ CKD
+ Clock division
+ 8
+ 2
+
+
+ UIFREMAP
+ UIF status bit remapping
+ 11
+ 1
+
+
+
+
+ CR2
+ CR2
+ control register 2
+ 0x4
+ 0x20
+ read-write
+ 0x0000
+
+
+ CCPC
+ Capture/compare preloaded
+ control
+ 0
+ 1
+
+
+ CCUS
+ Capture/compare control update
+ selection
+ 2
+ 1
+
+
+ CCDS
+ Capture/compare DMA
+ selection
+ 3
+ 1
+
+
+ MMS
+ Master mode selection
+ 4
+ 3
+
+
+ TI1S
+ TI1 selection
+ 7
+ 1
+
+
+ OIS1
+ Output Idle state 1
+ 8
+ 1
+
+
+ OIS1N
+ Output Idle state 1
+ 9
+ 1
+
+
+ OIS2
+ Output Idle state 2
+ 10
+ 1
+
+
+ OIS2N
+ Output Idle state 2
+ 11
+ 1
+
+
+ OIS3
+ Output Idle state 3
+ 12
+ 1
+
+
+ OIS3N
+ Output Idle state 3
+ 13
+ 1
+
+
+ OIS4
+ Output Idle state 4
+ 14
+ 1
+
+
+ OIS5
+ Output Idle state 5
+ 16
+ 1
+
+
+ OIS6
+ Output Idle state 6
+ 18
+ 1
+
+
+ MMS2
+ Master mode selection 2
+ 20
+ 4
+
+
+
+
+ SMCR
+ SMCR
+ slave mode control register
+ 0x8
+ 0x20
+ read-write
+ 0x0000
+
+
+ SMS
+ Slave mode selection
+ 0
+ 3
+
+
+ OCCS
+ OCREF clear selection
+ 3
+ 1
+
+
+ TS
+ Trigger selection
+ 4
+ 3
+
+
+ MSM
+ Master/Slave mode
+ 7
+ 1
+
+
+ ETF
+ External trigger filter
+ 8
+ 4
+
+
+ ETPS
+ External trigger prescaler
+ 12
+ 2
+
+
+ ECE
+ External clock enable
+ 14
+ 1
+
+
+ ETP
+ External trigger polarity
+ 15
+ 1
+
+
+ SMS3
+ Slave mode selection bit 3
+ 16
+ 1
+
+
+
+
+ DIER
+ DIER
+ DMA/Interrupt enable register
+ 0xC
+ 0x20
+ read-write
+ 0x0000
+
+
+ TDE
+ Trigger DMA request enable
+ 14
+ 1
+
+
+ COMDE
+ COM DMA request enable
+ 13
+ 1
+
+
+ CC4DE
+ Capture/Compare 4 DMA request
+ enable
+ 12
+ 1
+
+
+ CC3DE
+ Capture/Compare 3 DMA request
+ enable
+ 11
+ 1
+
+
+ CC2DE
+ Capture/Compare 2 DMA request
+ enable
+ 10
+ 1
+
+
+ CC1DE
+ Capture/Compare 1 DMA request
+ enable
+ 9
+ 1
+
+
+ UDE
+ Update DMA request enable
+ 8
+ 1
+
+
+ BIE
+ Break interrupt enable
+ 7
+ 1
+
+
+ TIE
+ Trigger interrupt enable
+ 6
+ 1
+
+
+ COMIE
+ COM interrupt enable
+ 5
+ 1
+
+
+ CC4IE
+ Capture/Compare 4 interrupt
+ enable
+ 4
+ 1
+
+
+ CC3IE
+ Capture/Compare 3 interrupt
+ enable
+ 3
+ 1
+
+
+ CC2IE
+ Capture/Compare 2 interrupt
+ enable
+ 2
+ 1
+
+
+ CC1IE
+ Capture/Compare 1 interrupt
+ enable
+ 1
+ 1
+
+
+ UIE
+ Update interrupt enable
+ 0
+ 1
+
+
+
+
+ SR
+ SR
+ status register
+ 0x10
+ 0x20
+ read-write
+ 0x0000
+
+
+ UIF
+ Update interrupt flag
+ 0
+ 1
+
+
+ CC1IF
+ Capture/compare 1 interrupt
+ flag
+ 1
+ 1
+
+
+ CC2IF
+ Capture/Compare 2 interrupt
+ flag
+ 2
+ 1
+
+
+ CC3IF
+ Capture/Compare 3 interrupt
+ flag
+ 3
+ 1
+
+
+ CC4IF
+ Capture/Compare 4 interrupt
+ flag
+ 4
+ 1
+
+
+ COMIF
+ COM interrupt flag
+ 5
+ 1
+
+
+ TIF
+ Trigger interrupt flag
+ 6
+ 1
+
+
+ BIF
+ Break interrupt flag
+ 7
+ 1
+
+
+ B2IF
+ Break 2 interrupt flag
+ 8
+ 1
+
+
+ CC1OF
+ Capture/Compare 1 overcapture
+ flag
+ 9
+ 1
+
+
+ CC2OF
+ Capture/compare 2 overcapture
+ flag
+ 10
+ 1
+
+
+ CC3OF
+ Capture/Compare 3 overcapture
+ flag
+ 11
+ 1
+
+
+ CC4OF
+ Capture/Compare 4 overcapture
+ flag
+ 12
+ 1
+
+
+ C5IF
+ Capture/Compare 5 interrupt
+ flag
+ 16
+ 1
+
+
+ C6IF
+ Capture/Compare 6 interrupt
+ flag
+ 17
+ 1
+
+
+
+
+ EGR
+ EGR
+ event generation register
+ 0x14
+ 0x20
+ write-only
+ 0x0000
+
+
+ UG
+ Update generation
+ 0
+ 1
+
+
+ CC1G
+ Capture/compare 1
+ generation
+ 1
+ 1
+
+
+ CC2G
+ Capture/compare 2
+ generation
+ 2
+ 1
+
+
+ CC3G
+ Capture/compare 3
+ generation
+ 3
+ 1
+
+
+ CC4G
+ Capture/compare 4
+ generation
+ 4
+ 1
+
+
+ COMG
+ Capture/Compare control update
+ generation
+ 5
+ 1
+
+
+ TG
+ Trigger generation
+ 6
+ 1
+
+
+ BG
+ Break generation
+ 7
+ 1
+
+
+ B2G
+ Break 2 generation
+ 8
+ 1
+
+
+
+
+ CCMR1_Output
+ CCMR1_Output
+ capture/compare mode register (output
+ mode)
+ 0x18
+ 0x20
+ read-write
+ 0x00000000
+
+
+ OC2CE
+ Output Compare 2 clear
+ enable
+ 15
+ 1
+
+
+ OC2M
+ Output Compare 2 mode
+ 12
+ 3
+
+
+ OC2PE
+ Output Compare 2 preload
+ enable
+ 11
+ 1
+
+
+ OC2FE
+ Output Compare 2 fast
+ enable
+ 10
+ 1
+
+
+ CC2S
+ Capture/Compare 2
+ selection
+ 8
+ 2
+
+
+ OC1CE
+ Output Compare 1 clear
+ enable
+ 7
+ 1
+
+
+ OC1M
+ Output Compare 1 mode
+ 4
+ 3
+
+
+ OC1PE
+ Output Compare 1 preload
+ enable
+ 3
+ 1
+
+
+ OC1FE
+ Output Compare 1 fast
+ enable
+ 2
+ 1
+
+
+ CC1S
+ Capture/Compare 1
+ selection
+ 0
+ 2
+
+
+ OC1M_3
+ Output Compare 1 mode bit
+ 3
+ 16
+ 1
+
+
+ OC2M_3
+ Output Compare 2 mode bit
+ 3
+ 24
+ 1
+
+
+
+
+ CCMR1_Input
+ CCMR1_Input
+ capture/compare mode register 1 (input
+ mode)
+ CCMR1_Output
+ 0x18
+ 0x20
+ read-write
+ 0x00000000
+
+
+ IC2F
+ Input capture 2 filter
+ 12
+ 4
+
+
+ IC2PCS
+ Input capture 2 prescaler
+ 10
+ 2
+
+
+ CC2S
+ Capture/Compare 2
+ selection
+ 8
+ 2
+
+
+ IC1F
+ Input capture 1 filter
+ 4
+ 4
+
+
+ IC1PCS
+ Input capture 1 prescaler
+ 2
+ 2
+
+
+ CC1S
+ Capture/Compare 1
+ selection
+ 0
+ 2
+
+
+
+
+ CCMR2_Output
+ CCMR2_Output
+ capture/compare mode register (output
+ mode)
+ 0x1C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ OC4CE
+ Output compare 4 clear
+ enable
+ 15
+ 1
+
+
+ OC4M
+ Output compare 4 mode
+ 12
+ 3
+
+
+ OC4PE
+ Output compare 4 preload
+ enable
+ 11
+ 1
+
+
+ OC4FE
+ Output compare 4 fast
+ enable
+ 10
+ 1
+
+
+ CC4S
+ Capture/Compare 4
+ selection
+ 8
+ 2
+
+
+ OC3CE
+ Output compare 3 clear
+ enable
+ 7
+ 1
+
+
+ OC3M
+ Output compare 3 mode
+ 4
+ 3
+
+
+ OC3PE
+ Output compare 3 preload
+ enable
+ 3
+ 1
+
+
+ OC3FE
+ Output compare 3 fast
+ enable
+ 2
+ 1
+
+
+ CC3S
+ Capture/Compare 3
+ selection
+ 0
+ 2
+
+
+ OC3M_3
+ Output Compare 3 mode bit
+ 3
+ 16
+ 1
+
+
+ OC4M_3
+ Output Compare 4 mode bit
+ 3
+ 24
+ 1
+
+
+
+
+ CCMR2_Input
+ CCMR2_Input
+ capture/compare mode register 2 (input
+ mode)
+ CCMR2_Output
+ 0x1C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ IC4F
+ Input capture 4 filter
+ 12
+ 4
+
+
+ IC4PSC
+ Input capture 4 prescaler
+ 10
+ 2
+
+
+ CC4S
+ Capture/Compare 4
+ selection
+ 8
+ 2
+
+
+ IC3F
+ Input capture 3 filter
+ 4
+ 4
+
+
+ IC3PSC
+ Input capture 3 prescaler
+ 2
+ 2
+
+
+ CC3S
+ Capture/compare 3
+ selection
+ 0
+ 2
+
+
+
+
+ CCER
+ CCER
+ capture/compare enable
+ register
+ 0x20
+ 0x20
+ read-write
+ 0x0000
+
+
+ CC1E
+ Capture/Compare 1 output
+ enable
+ 0
+ 1
+
+
+ CC1P
+ Capture/Compare 1 output
+ Polarity
+ 1
+ 1
+
+
+ CC1NE
+ Capture/Compare 1 complementary output
+ enable
+ 2
+ 1
+
+
+ CC1NP
+ Capture/Compare 1 output
+ Polarity
+ 3
+ 1
+
+
+ CC2E
+ Capture/Compare 2 output
+ enable
+ 4
+ 1
+
+
+ CC2P
+ Capture/Compare 2 output
+ Polarity
+ 5
+ 1
+
+
+ CC2NE
+ Capture/Compare 2 complementary output
+ enable
+ 6
+ 1
+
+
+ CC2NP
+ Capture/Compare 2 output
+ Polarity
+ 7
+ 1
+
+
+ CC3E
+ Capture/Compare 3 output
+ enable
+ 8
+ 1
+
+
+ CC3P
+ Capture/Compare 3 output
+ Polarity
+ 9
+ 1
+
+
+ CC3NE
+ Capture/Compare 3 complementary output
+ enable
+ 10
+ 1
+
+
+ CC3NP
+ Capture/Compare 3 output
+ Polarity
+ 11
+ 1
+
+
+ CC4E
+ Capture/Compare 4 output
+ enable
+ 12
+ 1
+
+
+ CC4P
+ Capture/Compare 3 output
+ Polarity
+ 13
+ 1
+
+
+ CC4NP
+ Capture/Compare 4 output
+ Polarity
+ 15
+ 1
+
+
+ CC5E
+ Capture/Compare 5 output
+ enable
+ 16
+ 1
+
+
+ CC5P
+ Capture/Compare 5 output
+ Polarity
+ 17
+ 1
+
+
+ CC6E
+ Capture/Compare 6 output
+ enable
+ 20
+ 1
+
+
+ CC6P
+ Capture/Compare 6 output
+ Polarity
+ 21
+ 1
+
+
+
+
+ CNT
+ CNT
+ counter
+ 0x24
+ 0x20
+ 0x00000000
+
+
+ CNT
+ counter value
+ 0
+ 16
+ read-write
+
+
+ UIFCPY
+ UIF copy
+ 31
+ 1
+ read-only
+
+
+
+
+ PSC
+ PSC
+ prescaler
+ 0x28
+ 0x20
+ read-write
+ 0x0000
+
+
+ PSC
+ Prescaler value
+ 0
+ 16
+
+
+
+
+ ARR
+ ARR
+ auto-reload register
+ 0x2C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ ARR
+ Auto-reload value
+ 0
+ 16
+
+
+
+
+ RCR
+ RCR
+ repetition counter register
+ 0x30
+ 0x20
+ read-write
+ 0x0000
+
+
+ REP
+ Repetition counter value
+ 0
+ 16
+
+
+
+
+ CCR1
+ CCR1
+ capture/compare register 1
+ 0x34
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CCR1
+ Capture/Compare 1 value
+ 0
+ 16
+
+
+
+
+ CCR2
+ CCR2
+ capture/compare register 2
+ 0x38
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CCR2
+ Capture/Compare 2 value
+ 0
+ 16
+
+
+
+
+ CCR3
+ CCR3
+ capture/compare register 3
+ 0x3C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CCR3
+ Capture/Compare 3 value
+ 0
+ 16
+
+
+
+
+ CCR4
+ CCR4
+ capture/compare register 4
+ 0x40
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CCR4
+ Capture/Compare 3 value
+ 0
+ 16
+
+
+
+
+ BDTR
+ BDTR
+ break and dead-time register
+ 0x44
+ 0x20
+ read-write
+ 0x00000000
+
+
+ DTG
+ Dead-time generator setup
+ 0
+ 8
+
+
+ LOCK
+ Lock configuration
+ 8
+ 2
+
+
+ OSSI
+ Off-state selection for Idle
+ mode
+ 10
+ 1
+
+
+ OSSR
+ Off-state selection for Run
+ mode
+ 11
+ 1
+
+
+ BKE
+ Break enable
+ 12
+ 1
+
+
+ BKP
+ Break polarity
+ 13
+ 1
+
+
+ AOE
+ Automatic output enable
+ 14
+ 1
+
+
+ MOE
+ Main output enable
+ 15
+ 1
+
+
+ BKF
+ Break filter
+ 16
+ 4
+
+
+ BK2F
+ Break 2 filter
+ 20
+ 4
+
+
+ BK2E
+ Break 2 enable
+ 24
+ 1
+
+
+ BK2P
+ Break 2 polarity
+ 25
+ 1
+
+
+
+
+ DCR
+ DCR
+ DMA control register
+ 0x48
+ 0x20
+ read-write
+ 0x00000000
+
+
+ DBL
+ DMA burst length
+ 8
+ 5
+
+
+ DBA
+ DMA base address
+ 0
+ 5
+
+
+
+
+ DMAR
+ DMAR
+ DMA address for full transfer
+ 0x4C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ DMAB
+ DMA register for burst
+ accesses
+ 0
+ 16
+
+
+
+
+ CCMR3_Output
+ CCMR3_Output
+ capture/compare mode register 3 (output
+ mode)
+ 0x54
+ 0x20
+ read-write
+ 0x00000000
+
+
+ OC5FE
+ Output compare 5 fast
+ enable
+ 2
+ 1
+
+
+ OC5PE
+ Output compare 5 preload
+ enable
+ 3
+ 1
+
+
+ OC5M
+ Output compare 5 mode
+ 4
+ 3
+
+
+ OC5CE
+ Output compare 5 clear
+ enable
+ 7
+ 1
+
+
+ OC6FE
+ Output compare 6 fast
+ enable
+ 10
+ 1
+
+
+ OC6PE
+ Output compare 6 preload
+ enable
+ 11
+ 1
+
+
+ OC6M
+ Output compare 6 mode
+ 12
+ 3
+
+
+ OC6CE
+ Output compare 6 clear
+ enable
+ 15
+ 1
+
+
+ OC5M_3
+ Outout Compare 5 mode bit
+ 3
+ 16
+ 1
+
+
+ OC6M_3
+ Outout Compare 6 mode bit
+ 3
+ 24
+ 1
+
+
+
+
+ CCR5
+ CCR5
+ capture/compare register 5
+ 0x58
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CCR5
+ Capture/Compare 5 value
+ 0
+ 16
+
+
+ GC5C1
+ Group Channel 5 and Channel
+ 1
+ 29
+ 1
+
+
+ GC5C2
+ Group Channel 5 and Channel
+ 2
+ 30
+ 1
+
+
+ GC5C3
+ Group Channel 5 and Channel
+ 3
+ 31
+ 1
+
+
+
+
+ CCR6
+ CCR6
+ capture/compare register 6
+ 0x5C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CCR6
+ Capture/Compare 6 value
+ 0
+ 16
+
+
+
+
+ OR
+ OR
+ option registers
+ 0x60
+ 0x20
+ read-write
+ 0x00000000
+
+
+ TIM1_ETR_ADC1_RMP
+ TIM1_ETR_ADC1 remapping
+ capability
+ 0
+ 2
+
+
+ TIM1_ETR_ADC4_RMP
+ TIM1_ETR_ADC4 remapping
+ capability
+ 2
+ 2
+
+
+
+
+
+
+ TIM20
+ 0x40015000
+
+ TIM1_CC
+ TIM1 capture compare interrupt
+ 27
+
+
+ TIM20_BRK
+ TIM20 Break interrupt
+ 77
+
+
+ TIM20_UP
+ TIM20 Upgrade interrupt
+ 78
+
+
+ TIM20_TRG_COM
+ TIM20 Trigger and Commutation
+ interrupt
+ 79
+
+
+ TIM20_CC
+ TIM20 Capture Compare interrupt
+ 80
+
+
+
+ TIM8
+ Advanced-timers
+ TIMs
+ 0x40013400
+
+ 0x0
+ 0x400
+ registers
+
+
+ TIM8_BRK
+ TIM8 break interrupt
+ 43
+
+
+ TIM8_UP
+ TIM8 update interrupt
+ 44
+
+
+ TIM8_TRG_COM
+ TIM8 Trigger and commutation
+ interrupts
+ 45
+
+
+ TIM8_CC
+ TIM8 capture compare interrupt
+ 46
+
+
+
+ CR1
+ CR1
+ control register 1
+ 0x0
+ 0x20
+ read-write
+ 0x0000
+
+
+ CEN
+ Counter enable
+ 0
+ 1
+
+
+ UDIS
+ Update disable
+ 1
+ 1
+
+
+ URS
+ Update request source
+ 2
+ 1
+
+
+ OPM
+ One-pulse mode
+ 3
+ 1
+
+
+ DIR
+ Direction
+ 4
+ 1
+
+
+ CMS
+ Center-aligned mode
+ selection
+ 5
+ 2
+
+
+ ARPE
+ Auto-reload preload enable
+ 7
+ 1
+
+
+ CKD
+ Clock division
+ 8
+ 2
+
+
+ UIFREMAP
+ UIF status bit remapping
+ 11
+ 1
+
+
+
+
+ CR2
+ CR2
+ control register 2
+ 0x4
+ 0x20
+ read-write
+ 0x0000
+
+
+ CCPC
+ Capture/compare preloaded
+ control
+ 0
+ 1
+
+
+ CCUS
+ Capture/compare control update
+ selection
+ 2
+ 1
+
+
+ CCDS
+ Capture/compare DMA
+ selection
+ 3
+ 1
+
+
+ MMS
+ Master mode selection
+ 4
+ 3
+
+
+ TI1S
+ TI1 selection
+ 7
+ 1
+
+
+ OIS1
+ Output Idle state 1
+ 8
+ 1
+
+
+ OIS1N
+ Output Idle state 1
+ 9
+ 1
+
+
+ OIS2
+ Output Idle state 2
+ 10
+ 1
+
+
+ OIS2N
+ Output Idle state 2
+ 11
+ 1
+
+
+ OIS3
+ Output Idle state 3
+ 12
+ 1
+
+
+ OIS3N
+ Output Idle state 3
+ 13
+ 1
+
+
+ OIS4
+ Output Idle state 4
+ 14
+ 1
+
+
+ OIS5
+ Output Idle state 5
+ 16
+ 1
+
+
+ OIS6
+ Output Idle state 6
+ 18
+ 1
+
+
+ MMS2
+ Master mode selection 2
+ 20
+ 4
+
+
+
+
+ SMCR
+ SMCR
+ slave mode control register
+ 0x8
+ 0x20
+ read-write
+ 0x0000
+
+
+ SMS
+ Slave mode selection
+ 0
+ 3
+
+
+ OCCS
+ OCREF clear selection
+ 3
+ 1
+
+
+ TS
+ Trigger selection
+ 4
+ 3
+
+
+ MSM
+ Master/Slave mode
+ 7
+ 1
+
+
+ ETF
+ External trigger filter
+ 8
+ 4
+
+
+ ETPS
+ External trigger prescaler
+ 12
+ 2
+
+
+ ECE
+ External clock enable
+ 14
+ 1
+
+
+ ETP
+ External trigger polarity
+ 15
+ 1
+
+
+ SMS3
+ Slave mode selection bit 3
+ 16
+ 1
+
+
+
+
+ DIER
+ DIER
+ DMA/Interrupt enable register
+ 0xC
+ 0x20
+ read-write
+ 0x0000
+
+
+ TDE
+ Trigger DMA request enable
+ 14
+ 1
+
+
+ COMDE
+ COM DMA request enable
+ 13
+ 1
+
+
+ CC4DE
+ Capture/Compare 4 DMA request
+ enable
+ 12
+ 1
+
+
+ CC3DE
+ Capture/Compare 3 DMA request
+ enable
+ 11
+ 1
+
+
+ CC2DE
+ Capture/Compare 2 DMA request
+ enable
+ 10
+ 1
+
+
+ CC1DE
+ Capture/Compare 1 DMA request
+ enable
+ 9
+ 1
+
+
+ UDE
+ Update DMA request enable
+ 8
+ 1
+
+
+ BIE
+ Break interrupt enable
+ 7
+ 1
+
+
+ TIE
+ Trigger interrupt enable
+ 6
+ 1
+
+
+ COMIE
+ COM interrupt enable
+ 5
+ 1
+
+
+ CC4IE
+ Capture/Compare 4 interrupt
+ enable
+ 4
+ 1
+
+
+ CC3IE
+ Capture/Compare 3 interrupt
+ enable
+ 3
+ 1
+
+
+ CC2IE
+ Capture/Compare 2 interrupt
+ enable
+ 2
+ 1
+
+
+ CC1IE
+ Capture/Compare 1 interrupt
+ enable
+ 1
+ 1
+
+
+ UIE
+ Update interrupt enable
+ 0
+ 1
+
+
+
+
+ SR
+ SR
+ status register
+ 0x10
+ 0x20
+ read-write
+ 0x0000
+
+
+ UIF
+ Update interrupt flag
+ 0
+ 1
+
+
+ CC1IF
+ Capture/compare 1 interrupt
+ flag
+ 1
+ 1
+
+
+ CC2IF
+ Capture/Compare 2 interrupt
+ flag
+ 2
+ 1
+
+
+ CC3IF
+ Capture/Compare 3 interrupt
+ flag
+ 3
+ 1
+
+
+ CC4IF
+ Capture/Compare 4 interrupt
+ flag
+ 4
+ 1
+
+
+ COMIF
+ COM interrupt flag
+ 5
+ 1
+
+
+ TIF
+ Trigger interrupt flag
+ 6
+ 1
+
+
+ BIF
+ Break interrupt flag
+ 7
+ 1
+
+
+ B2IF
+ Break 2 interrupt flag
+ 8
+ 1
+
+
+ CC1OF
+ Capture/Compare 1 overcapture
+ flag
+ 9
+ 1
+
+
+ CC2OF
+ Capture/compare 2 overcapture
+ flag
+ 10
+ 1
+
+
+ CC3OF
+ Capture/Compare 3 overcapture
+ flag
+ 11
+ 1
+
+
+ CC4OF
+ Capture/Compare 4 overcapture
+ flag
+ 12
+ 1
+
+
+ C5IF
+ Capture/Compare 5 interrupt
+ flag
+ 16
+ 1
+
+
+ C6IF
+ Capture/Compare 6 interrupt
+ flag
+ 17
+ 1
+
+
+
+
+ EGR
+ EGR
+ event generation register
+ 0x14
+ 0x20
+ write-only
+ 0x0000
+
+
+ UG
+ Update generation
+ 0
+ 1
+
+
+ CC1G
+ Capture/compare 1
+ generation
+ 1
+ 1
+
+
+ CC2G
+ Capture/compare 2
+ generation
+ 2
+ 1
+
+
+ CC3G
+ Capture/compare 3
+ generation
+ 3
+ 1
+
+
+ CC4G
+ Capture/compare 4
+ generation
+ 4
+ 1
+
+
+ COMG
+ Capture/Compare control update
+ generation
+ 5
+ 1
+
+
+ TG
+ Trigger generation
+ 6
+ 1
+
+
+ BG
+ Break generation
+ 7
+ 1
+
+
+ B2G
+ Break 2 generation
+ 8
+ 1
+
+
+
+
+ CCMR1_Output
+ CCMR1_Output
+ capture/compare mode register (output
+ mode)
+ 0x18
+ 0x20
+ read-write
+ 0x00000000
+
+
+ OC2CE
+ Output Compare 2 clear
+ enable
+ 15
+ 1
+
+
+ OC2M
+ Output Compare 2 mode
+ 12
+ 3
+
+
+ OC2PE
+ Output Compare 2 preload
+ enable
+ 11
+ 1
+
+
+ OC2FE
+ Output Compare 2 fast
+ enable
+ 10
+ 1
+
+
+ CC2S
+ Capture/Compare 2
+ selection
+ 8
+ 2
+
+
+ OC1CE
+ Output Compare 1 clear
+ enable
+ 7
+ 1
+
+
+ OC1M
+ Output Compare 1 mode
+ 4
+ 3
+
+
+ OC1PE
+ Output Compare 1 preload
+ enable
+ 3
+ 1
+
+
+ OC1FE
+ Output Compare 1 fast
+ enable
+ 2
+ 1
+
+
+ CC1S
+ Capture/Compare 1
+ selection
+ 0
+ 2
+
+
+ OC1M_3
+ Output Compare 1 mode bit
+ 3
+ 16
+ 1
+
+
+ OC2M_3
+ Output Compare 2 mode bit
+ 3
+ 24
+ 1
+
+
+
+
+ CCMR1_Input
+ CCMR1_Input
+ capture/compare mode register 1 (input
+ mode)
+ CCMR1_Output
+ 0x18
+ 0x20
+ read-write
+ 0x00000000
+
+
+ IC2F
+ Input capture 2 filter
+ 12
+ 4
+
+
+ IC2PCS
+ Input capture 2 prescaler
+ 10
+ 2
+
+
+ CC2S
+ Capture/Compare 2
+ selection
+ 8
+ 2
+
+
+ IC1F
+ Input capture 1 filter
+ 4
+ 4
+
+
+ IC1PCS
+ Input capture 1 prescaler
+ 2
+ 2
+
+
+ CC1S
+ Capture/Compare 1
+ selection
+ 0
+ 2
+
+
+
+
+ CCMR2_Output
+ CCMR2_Output
+ capture/compare mode register (output
+ mode)
+ 0x1C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ OC4CE
+ Output compare 4 clear
+ enable
+ 15
+ 1
+
+
+ OC4M
+ Output compare 4 mode
+ 12
+ 3
+
+
+ OC4PE
+ Output compare 4 preload
+ enable
+ 11
+ 1
+
+
+ OC4FE
+ Output compare 4 fast
+ enable
+ 10
+ 1
+
+
+ CC4S
+ Capture/Compare 4
+ selection
+ 8
+ 2
+
+
+ OC3CE
+ Output compare 3 clear
+ enable
+ 7
+ 1
+
+
+ OC3M
+ Output compare 3 mode
+ 4
+ 3
+
+
+ OC3PE
+ Output compare 3 preload
+ enable
+ 3
+ 1
+
+
+ OC3FE
+ Output compare 3 fast
+ enable
+ 2
+ 1
+
+
+ CC3S
+ Capture/Compare 3
+ selection
+ 0
+ 2
+
+
+ OC3M_3
+ Output Compare 3 mode bit
+ 3
+ 16
+ 1
+
+
+ OC4M_3
+ Output Compare 4 mode bit
+ 3
+ 24
+ 1
+
+
+
+
+ CCMR2_Input
+ CCMR2_Input
+ capture/compare mode register 2 (input
+ mode)
+ CCMR2_Output
+ 0x1C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ IC4F
+ Input capture 4 filter
+ 12
+ 4
+
+
+ IC4PSC
+ Input capture 4 prescaler
+ 10
+ 2
+
+
+ CC4S
+ Capture/Compare 4
+ selection
+ 8
+ 2
+
+
+ IC3F
+ Input capture 3 filter
+ 4
+ 4
+
+
+ IC3PSC
+ Input capture 3 prescaler
+ 2
+ 2
+
+
+ CC3S
+ Capture/compare 3
+ selection
+ 0
+ 2
+
+
+
+
+ CCER
+ CCER
+ capture/compare enable
+ register
+ 0x20
+ 0x20
+ read-write
+ 0x0000
+
+
+ CC1E
+ Capture/Compare 1 output
+ enable
+ 0
+ 1
+
+
+ CC1P
+ Capture/Compare 1 output
+ Polarity
+ 1
+ 1
+
+
+ CC1NE
+ Capture/Compare 1 complementary output
+ enable
+ 2
+ 1
+
+
+ CC1NP
+ Capture/Compare 1 output
+ Polarity
+ 3
+ 1
+
+
+ CC2E
+ Capture/Compare 2 output
+ enable
+ 4
+ 1
+
+
+ CC2P
+ Capture/Compare 2 output
+ Polarity
+ 5
+ 1
+
+
+ CC2NE
+ Capture/Compare 2 complementary output
+ enable
+ 6
+ 1
+
+
+ CC2NP
+ Capture/Compare 2 output
+ Polarity
+ 7
+ 1
+
+
+ CC3E
+ Capture/Compare 3 output
+ enable
+ 8
+ 1
+
+
+ CC3P
+ Capture/Compare 3 output
+ Polarity
+ 9
+ 1
+
+
+ CC3NE
+ Capture/Compare 3 complementary output
+ enable
+ 10
+ 1
+
+
+ CC3NP
+ Capture/Compare 3 output
+ Polarity
+ 11
+ 1
+
+
+ CC4E
+ Capture/Compare 4 output
+ enable
+ 12
+ 1
+
+
+ CC4P
+ Capture/Compare 3 output
+ Polarity
+ 13
+ 1
+
+
+ CC4NP
+ Capture/Compare 4 output
+ Polarity
+ 15
+ 1
+
+
+ CC5E
+ Capture/Compare 5 output
+ enable
+ 16
+ 1
+
+
+ CC5P
+ Capture/Compare 5 output
+ Polarity
+ 17
+ 1
+
+
+ CC6E
+ Capture/Compare 6 output
+ enable
+ 20
+ 1
+
+
+ CC6P
+ Capture/Compare 6 output
+ Polarity
+ 21
+ 1
+
+
+
+
+ CNT
+ CNT
+ counter
+ 0x24
+ 0x20
+ 0x00000000
+
+
+ CNT
+ counter value
+ 0
+ 16
+ read-write
+
+
+ UIFCPY
+ UIF copy
+ 31
+ 1
+ read-only
+
+
+
+
+ PSC
+ PSC
+ prescaler
+ 0x28
+ 0x20
+ read-write
+ 0x0000
+
+
+ PSC
+ Prescaler value
+ 0
+ 16
+
+
+
+
+ ARR
+ ARR
+ auto-reload register
+ 0x2C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ ARR
+ Auto-reload value
+ 0
+ 16
+
+
+
+
+ RCR
+ RCR
+ repetition counter register
+ 0x30
+ 0x20
+ read-write
+ 0x0000
+
+
+ REP
+ Repetition counter value
+ 0
+ 16
+
+
+
+
+ CCR1
+ CCR1
+ capture/compare register 1
+ 0x34
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CCR1
+ Capture/Compare 1 value
+ 0
+ 16
+
+
+
+
+ CCR2
+ CCR2
+ capture/compare register 2
+ 0x38
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CCR2
+ Capture/Compare 2 value
+ 0
+ 16
+
+
+
+
+ CCR3
+ CCR3
+ capture/compare register 3
+ 0x3C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CCR3
+ Capture/Compare 3 value
+ 0
+ 16
+
+
+
+
+ CCR4
+ CCR4
+ capture/compare register 4
+ 0x40
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CCR4
+ Capture/Compare 3 value
+ 0
+ 16
+
+
+
+
+ BDTR
+ BDTR
+ break and dead-time register
+ 0x44
+ 0x20
+ read-write
+ 0x00000000
+
+
+ DTG
+ Dead-time generator setup
+ 0
+ 8
+
+
+ LOCK
+ Lock configuration
+ 8
+ 2
+
+
+ OSSI
+ Off-state selection for Idle
+ mode
+ 10
+ 1
+
+
+ OSSR
+ Off-state selection for Run
+ mode
+ 11
+ 1
+
+
+ BKE
+ Break enable
+ 12
+ 1
+
+
+ BKP
+ Break polarity
+ 13
+ 1
+
+
+ AOE
+ Automatic output enable
+ 14
+ 1
+
+
+ MOE
+ Main output enable
+ 15
+ 1
+
+
+ BKF
+ Break filter
+ 16
+ 4
+
+
+ BK2F
+ Break 2 filter
+ 20
+ 4
+
+
+ BK2E
+ Break 2 enable
+ 24
+ 1
+
+
+ BK2P
+ Break 2 polarity
+ 25
+ 1
+
+
+
+
+ DCR
+ DCR
+ DMA control register
+ 0x48
+ 0x20
+ read-write
+ 0x00000000
+
+
+ DBL
+ DMA burst length
+ 8
+ 5
+
+
+ DBA
+ DMA base address
+ 0
+ 5
+
+
+
+
+ DMAR
+ DMAR
+ DMA address for full transfer
+ 0x4C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ DMAB
+ DMA register for burst
+ accesses
+ 0
+ 16
+
+
+
+
+ CCMR3_Output
+ CCMR3_Output
+ capture/compare mode register 3 (output
+ mode)
+ 0x54
+ 0x20
+ read-write
+ 0x00000000
+
+
+ OC5FE
+ Output compare 5 fast
+ enable
+ 2
+ 1
+
+
+ OC5PE
+ Output compare 5 preload
+ enable
+ 3
+ 1
+
+
+ OC5M
+ Output compare 5 mode
+ 4
+ 3
+
+
+ OC5CE
+ Output compare 5 clear
+ enable
+ 7
+ 1
+
+
+ OC6FE
+ Output compare 6 fast
+ enable
+ 10
+ 1
+
+
+ OC6PE
+ Output compare 6 preload
+ enable
+ 11
+ 1
+
+
+ OC6M
+ Output compare 6 mode
+ 12
+ 3
+
+
+ OC6CE
+ Output compare 6 clear
+ enable
+ 15
+ 1
+
+
+ OC5M_3
+ Outout Compare 5 mode bit
+ 3
+ 16
+ 1
+
+
+ OC6M_3
+ Outout Compare 6 mode bit
+ 3
+ 24
+ 1
+
+
+
+
+ CCR5
+ CCR5
+ capture/compare register 5
+ 0x58
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CCR5
+ Capture/Compare 5 value
+ 0
+ 16
+
+
+ GC5C1
+ Group Channel 5 and Channel
+ 1
+ 29
+ 1
+
+
+ GC5C2
+ Group Channel 5 and Channel
+ 2
+ 30
+ 1
+
+
+ GC5C3
+ Group Channel 5 and Channel
+ 3
+ 31
+ 1
+
+
+
+
+ CCR6
+ CCR6
+ capture/compare register 6
+ 0x5C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CCR6
+ Capture/Compare 6 value
+ 0
+ 16
+
+
+
+
+ OR
+ OR
+ option registers
+ 0x60
+ 0x20
+ read-write
+ 0x00000000
+
+
+ TIM8_ETR_ADC2_RMP
+ TIM8_ETR_ADC2 remapping
+ capability
+ 0
+ 2
+
+
+ TIM8_ETR_ADC3_RMP
+ TIM8_ETR_ADC3 remapping
+ capability
+ 2
+ 2
+
+
+
+
+
+
+ ADC1
+ Analog-to-Digital Converter
+ ADC
+ 0x50000000
+
+ 0x0
+ 0x100
+ registers
+
+
+
+ ISR
+ ISR
+ interrupt and status register
+ 0x0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ JQOVF
+ JQOVF
+ 10
+ 1
+
+
+ AWD3
+ AWD3
+ 9
+ 1
+
+
+ AWD2
+ AWD2
+ 8
+ 1
+
+
+ AWD1
+ AWD1
+ 7
+ 1
+
+
+ JEOS
+ JEOS
+ 6
+ 1
+
+
+ JEOC
+ JEOC
+ 5
+ 1
+
+
+ OVR
+ OVR
+ 4
+ 1
+
+
+ EOS
+ EOS
+ 3
+ 1
+
+
+ EOC
+ EOC
+ 2
+ 1
+
+
+ EOSMP
+ EOSMP
+ 1
+ 1
+
+
+ ADRDY
+ ADRDY
+ 0
+ 1
+
+
+
+
+ IER
+ IER
+ interrupt enable register
+ 0x4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ JQOVFIE
+ JQOVFIE
+ 10
+ 1
+
+
+ AWD3IE
+ AWD3IE
+ 9
+ 1
+
+
+ AWD2IE
+ AWD2IE
+ 8
+ 1
+
+
+ AWD1IE
+ AWD1IE
+ 7
+ 1
+
+
+ JEOSIE
+ JEOSIE
+ 6
+ 1
+
+
+ JEOCIE
+ JEOCIE
+ 5
+ 1
+
+
+ OVRIE
+ OVRIE
+ 4
+ 1
+
+
+ EOSIE
+ EOSIE
+ 3
+ 1
+
+
+ EOCIE
+ EOCIE
+ 2
+ 1
+
+
+ EOSMPIE
+ EOSMPIE
+ 1
+ 1
+
+
+ ADRDYIE
+ ADRDYIE
+ 0
+ 1
+
+
+
+
+ CR
+ CR
+ control register
+ 0x8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ ADCAL
+ ADCAL
+ 31
+ 1
+
+
+ ADCALDIF
+ ADCALDIF
+ 30
+ 1
+
+
+ ADVREGEN
+ ADVREGEN
+ 28
+ 2
+
+
+ JADSTP
+ JADSTP
+ 5
+ 1
+
+
+ ADSTP
+ ADSTP
+ 4
+ 1
+
+
+ JADSTART
+ JADSTART
+ 3
+ 1
+
+
+ ADSTART
+ ADSTART
+ 2
+ 1
+
+
+ ADDIS
+ ADDIS
+ 1
+ 1
+
+
+ ADEN
+ ADEN
+ 0
+ 1
+
+
+
+
+ CFGR
+ CFGR
+ configuration register
+ 0xC
+ 0x20
+ read-write
+ 0x00000000
+
+
+ AWDCH1CH
+ AWDCH1CH
+ 26
+ 5
+
+
+ JAUTO
+ JAUTO
+ 25
+ 1
+
+
+ JAWD1EN
+ JAWD1EN
+ 24
+ 1
+
+
+ AWD1EN
+ AWD1EN
+ 23
+ 1
+
+
+ AWD1SGL
+ AWD1SGL
+ 22
+ 1
+
+
+ JQM
+ JQM
+ 21
+ 1
+
+
+ JDISCEN
+ JDISCEN
+ 20
+ 1
+
+
+ DISCNUM
+ DISCNUM
+ 17
+ 3
+
+
+ DISCEN
+ DISCEN
+ 16
+ 1
+
+
+ AUTDLY
+ AUTDLY
+ 14
+ 1
+
+
+ CONT
+ CONT
+ 13
+ 1
+
+
+ OVRMOD
+ OVRMOD
+ 12
+ 1
+
+
+ EXTEN
+ EXTEN
+ 10
+ 2
+
+
+ EXTSEL
+ EXTSEL
+ 6
+ 4
+
+
+ ALIGN
+ ALIGN
+ 5
+ 1
+
+
+ RES
+ RES
+ 3
+ 2
+
+
+ DMACFG
+ DMACFG
+ 1
+ 1
+
+
+ DMAEN
+ DMAEN
+ 0
+ 1
+
+
+
+
+ SMPR1
+ SMPR1
+ sample time register 1
+ 0x14
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SMP9
+ SMP9
+ 27
+ 3
+
+
+ SMP8
+ SMP8
+ 24
+ 3
+
+
+ SMP7
+ SMP7
+ 21
+ 3
+
+
+ SMP6
+ SMP6
+ 18
+ 3
+
+
+ SMP5
+ SMP5
+ 15
+ 3
+
+
+ SMP4
+ SMP4
+ 12
+ 3
+
+
+ SMP3
+ SMP3
+ 9
+ 3
+
+
+ SMP2
+ SMP2
+ 6
+ 3
+
+
+ SMP1
+ SMP1
+ 3
+ 3
+
+
+
+
+ SMPR2
+ SMPR2
+ sample time register 2
+ 0x18
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SMP18
+ SMP18
+ 24
+ 3
+
+
+ SMP17
+ SMP17
+ 21
+ 3
+
+
+ SMP16
+ SMP16
+ 18
+ 3
+
+
+ SMP15
+ SMP15
+ 15
+ 3
+
+
+ SMP14
+ SMP14
+ 12
+ 3
+
+
+ SMP13
+ SMP13
+ 9
+ 3
+
+
+ SMP12
+ SMP12
+ 6
+ 3
+
+
+ SMP11
+ SMP11
+ 3
+ 3
+
+
+ SMP10
+ SMP10
+ 0
+ 3
+
+
+
+
+ TR1
+ TR1
+ watchdog threshold register 1
+ 0x20
+ 0x20
+ read-write
+ 0x0FFF0000
+
+
+ HT1
+ HT1
+ 16
+ 12
+
+
+ LT1
+ LT1
+ 0
+ 12
+
+
+
+
+ TR2
+ TR2
+ watchdog threshold register
+ 0x24
+ 0x20
+ read-write
+ 0x0FFF0000
+
+
+ HT2
+ HT2
+ 16
+ 8
+
+
+ LT2
+ LT2
+ 0
+ 8
+
+
+
+
+ TR3
+ TR3
+ watchdog threshold register 3
+ 0x28
+ 0x20
+ read-write
+ 0x0FFF0000
+
+
+ HT3
+ HT3
+ 16
+ 8
+
+
+ LT3
+ LT3
+ 0
+ 8
+
+
+
+
+ SQR1
+ SQR1
+ regular sequence register 1
+ 0x30
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SQ4
+ SQ4
+ 24
+ 5
+
+
+ SQ3
+ SQ3
+ 18
+ 5
+
+
+ SQ2
+ SQ2
+ 12
+ 5
+
+
+ SQ1
+ SQ1
+ 6
+ 5
+
+
+ L3
+ L3
+ 0
+ 4
+
+
+
+
+ SQR2
+ SQR2
+ regular sequence register 2
+ 0x34
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SQ9
+ SQ9
+ 24
+ 5
+
+
+ SQ8
+ SQ8
+ 18
+ 5
+
+
+ SQ7
+ SQ7
+ 12
+ 5
+
+
+ SQ6
+ SQ6
+ 6
+ 5
+
+
+ SQ5
+ SQ5
+ 0
+ 5
+
+
+
+
+ SQR3
+ SQR3
+ regular sequence register 3
+ 0x38
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SQ14
+ SQ14
+ 24
+ 5
+
+
+ SQ13
+ SQ13
+ 18
+ 5
+
+
+ SQ12
+ SQ12
+ 12
+ 5
+
+
+ SQ11
+ SQ11
+ 6
+ 5
+
+
+ SQ10
+ SQ10
+ 0
+ 5
+
+
+
+
+ SQR4
+ SQR4
+ regular sequence register 4
+ 0x3C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SQ16
+ SQ16
+ 6
+ 5
+
+
+ SQ15
+ SQ15
+ 0
+ 5
+
+
+
+
+ DR
+ DR
+ regular Data Register
+ 0x40
+ 0x20
+ read-only
+ 0x00000000
+
+
+ regularDATA
+ regularDATA
+ 0
+ 16
+
+
+
+
+ JSQR
+ JSQR
+ injected sequence register
+ 0x4C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ JSQ4
+ JSQ4
+ 26
+ 5
+
+
+ JSQ3
+ JSQ3
+ 20
+ 5
+
+
+ JSQ2
+ JSQ2
+ 14
+ 5
+
+
+ JSQ1
+ JSQ1
+ 8
+ 5
+
+
+ JEXTEN
+ JEXTEN
+ 6
+ 2
+
+
+ JEXTSEL
+ JEXTSEL
+ 2
+ 4
+
+
+ JL
+ JL
+ 0
+ 2
+
+
+
+
+ OFR1
+ OFR1
+ offset register 1
+ 0x60
+ 0x20
+ read-write
+ 0x00000000
+
+
+ OFFSET1_EN
+ OFFSET1_EN
+ 31
+ 1
+
+
+ OFFSET1_CH
+ OFFSET1_CH
+ 26
+ 5
+
+
+ OFFSET1
+ OFFSET1
+ 0
+ 12
+
+
+
+
+ OFR2
+ OFR2
+ offset register 2
+ 0x64
+ 0x20
+ read-write
+ 0x00000000
+
+
+ OFFSET2_EN
+ OFFSET2_EN
+ 31
+ 1
+
+
+ OFFSET2_CH
+ OFFSET2_CH
+ 26
+ 5
+
+
+ OFFSET2
+ OFFSET2
+ 0
+ 12
+
+
+
+
+ OFR3
+ OFR3
+ offset register 3
+ 0x68
+ 0x20
+ read-write
+ 0x00000000
+
+
+ OFFSET3_EN
+ OFFSET3_EN
+ 31
+ 1
+
+
+ OFFSET3_CH
+ OFFSET3_CH
+ 26
+ 5
+
+
+ OFFSET3
+ OFFSET3
+ 0
+ 12
+
+
+
+
+ OFR4
+ OFR4
+ offset register 4
+ 0x6C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ OFFSET4_EN
+ OFFSET4_EN
+ 31
+ 1
+
+
+ OFFSET4_CH
+ OFFSET4_CH
+ 26
+ 5
+
+
+ OFFSET4
+ OFFSET4
+ 0
+ 12
+
+
+
+
+ JDR1
+ JDR1
+ injected data register 1
+ 0x80
+ 0x20
+ read-only
+ 0x00000000
+
+
+ JDATA1
+ JDATA1
+ 0
+ 16
+
+
+
+
+ JDR2
+ JDR2
+ injected data register 2
+ 0x84
+ 0x20
+ read-only
+ 0x00000000
+
+
+ JDATA2
+ JDATA2
+ 0
+ 16
+
+
+
+
+ JDR3
+ JDR3
+ injected data register 3
+ 0x88
+ 0x20
+ read-only
+ 0x00000000
+
+
+ JDATA3
+ JDATA3
+ 0
+ 16
+
+
+
+
+ JDR4
+ JDR4
+ injected data register 4
+ 0x8C
+ 0x20
+ read-only
+ 0x00000000
+
+
+ JDATA4
+ JDATA4
+ 0
+ 16
+
+
+
+
+ AWD2CR
+ AWD2CR
+ Analog Watchdog 2 Configuration
+ Register
+ 0xA0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ AWD2CH
+ AWD2CH
+ 1
+ 18
+
+
+
+
+ AWD3CR
+ AWD3CR
+ Analog Watchdog 3 Configuration
+ Register
+ 0xA4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ AWD3CH
+ AWD3CH
+ 1
+ 18
+
+
+
+
+ DIFSEL
+ DIFSEL
+ Differential Mode Selection Register
+ 2
+ 0xB0
+ 0x20
+ 0x00000000
+
+
+ DIFSEL_1_15
+ Differential mode for channels 15 to
+ 1
+ 1
+ 15
+ read-write
+
+
+ DIFSEL_16_18
+ Differential mode for channels 18 to
+ 16
+ 16
+ 3
+ read-only
+
+
+
+
+ CALFACT
+ CALFACT
+ Calibration Factors
+ 0xB4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CALFACT_D
+ CALFACT_D
+ 16
+ 7
+
+
+ CALFACT_S
+ CALFACT_S
+ 0
+ 7
+
+
+
+
+
+
+ ADC2
+ 0x50000100
+
+
+ ADC3
+ 0x50000400
+
+ ADC3
+ ADC3 global interrupt
+ 47
+
+
+
+ ADC4
+ 0x50000500
+
+ ADC4
+ ADC4 global interrupt
+ 61
+
+
+
+ ADC1_2
+ Analog-to-Digital Converter
+ ADC
+ 0x50000300
+
+ 0x0
+ 0x10
+ registers
+
+
+ ADC1_2
+ ADC1 and ADC2 global interrupt
+ 18
+
+
+
+ CSR
+ CSR
+ ADC Common status register
+ 0x0
+ 0x20
+ read-only
+ 0x00000000
+
+
+ ADDRDY_MST
+ ADDRDY_MST
+ 0
+ 1
+
+
+ EOSMP_MST
+ EOSMP_MST
+ 1
+ 1
+
+
+ EOC_MST
+ EOC_MST
+ 2
+ 1
+
+
+ EOS_MST
+ EOS_MST
+ 3
+ 1
+
+
+ OVR_MST
+ OVR_MST
+ 4
+ 1
+
+
+ JEOC_MST
+ JEOC_MST
+ 5
+ 1
+
+
+ JEOS_MST
+ JEOS_MST
+ 6
+ 1
+
+
+ AWD1_MST
+ AWD1_MST
+ 7
+ 1
+
+
+ AWD2_MST
+ AWD2_MST
+ 8
+ 1
+
+
+ AWD3_MST
+ AWD3_MST
+ 9
+ 1
+
+
+ JQOVF_MST
+ JQOVF_MST
+ 10
+ 1
+
+
+ ADRDY_SLV
+ ADRDY_SLV
+ 16
+ 1
+
+
+ EOSMP_SLV
+ EOSMP_SLV
+ 17
+ 1
+
+
+ EOC_SLV
+ End of regular conversion of the slave
+ ADC
+ 18
+ 1
+
+
+ EOS_SLV
+ End of regular sequence flag of the
+ slave ADC
+ 19
+ 1
+
+
+ OVR_SLV
+ Overrun flag of the slave
+ ADC
+ 20
+ 1
+
+
+ JEOC_SLV
+ End of injected conversion flag of the
+ slave ADC
+ 21
+ 1
+
+
+ JEOS_SLV
+ End of injected sequence flag of the
+ slave ADC
+ 22
+ 1
+
+
+ AWD1_SLV
+ Analog watchdog 1 flag of the slave
+ ADC
+ 23
+ 1
+
+
+ AWD2_SLV
+ Analog watchdog 2 flag of the slave
+ ADC
+ 24
+ 1
+
+
+ AWD3_SLV
+ Analog watchdog 3 flag of the slave
+ ADC
+ 25
+ 1
+
+
+ JQOVF_SLV
+ Injected Context Queue Overflow flag of
+ the slave ADC
+ 26
+ 1
+
+
+
+
+ CCR
+ CCR
+ ADC common control register
+ 0x8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MULT
+ Multi ADC mode selection
+ 0
+ 5
+
+
+ DELAY
+ Delay between 2 sampling
+ phases
+ 8
+ 4
+
+
+ DMACFG
+ DMA configuration (for multi-ADC
+ mode)
+ 13
+ 1
+
+
+ MDMA
+ Direct memory access mode for multi ADC
+ mode
+ 14
+ 2
+
+
+ CKMODE
+ ADC clock mode
+ 16
+ 2
+
+
+ VREFEN
+ VREFINT enable
+ 22
+ 1
+
+
+ TSEN
+ Temperature sensor enable
+ 23
+ 1
+
+
+ VBATEN
+ VBAT enable
+ 24
+ 1
+
+
+
+
+ CDR
+ CDR
+ ADC common regular data register for dual
+ and triple modes
+ 0xC
+ 0x20
+ read-only
+ 0x00000000
+
+
+ RDATA_SLV
+ Regular data of the slave
+ ADC
+ 16
+ 16
+
+
+ RDATA_MST
+ Regular data of the master
+ ADC
+ 0
+ 16
+
+
+
+
+
+
+ ADC3_4
+ 0x50000700
+
+
+ SYSCFG_COMP_OPAMP
+ System configuration controller _Comparator and
+ Operational amplifier
+ SYSCFG_COMP_OPAMP
+ 0x40010000
+
+ 0x0
+ 0x400
+ registers
+
+
+ COMP123
+ COMP1 & COMP2 & COMP3 interrupts
+ combined with EXTI Lines 21, 22 and 29
+ interrupts
+ 64
+
+
+ COMP456
+ COMP4 & COMP5 & COMP6 interrupts
+ combined with EXTI Lines 30, 31 and 32
+ interrupts
+ 65
+
+
+ COMP7
+ COMP7 interrupt combined with EXTI Line 33
+ interrupt
+ 66
+
+
+
+ SYSCFG_CFGR1
+ SYSCFG_CFGR1
+ configuration register 1
+ 0x0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MEM_MODE
+ Memory mapping selection
+ bits
+ 0
+ 2
+
+
+ USB_IT_RMP
+ USB interrupt remap
+ 5
+ 1
+
+
+ TIM1_ITR_RMP
+ Timer 1 ITR3 selection
+ 6
+ 1
+
+
+ DAC_TRIG_RMP
+ DAC trigger remap (when TSEL =
+ 001)
+ 7
+ 1
+
+
+ ADC24_DMA_RMP
+ ADC24 DMA remapping bit
+ 8
+ 1
+
+
+ TIM16_DMA_RMP
+ TIM16 DMA request remapping
+ bit
+ 11
+ 1
+
+
+ TIM17_DMA_RMP
+ TIM17 DMA request remapping
+ bit
+ 12
+ 1
+
+
+ TIM6_DAC1_DMA_RMP
+ TIM6 and DAC1 DMA request remapping
+ bit
+ 13
+ 1
+
+
+ TIM7_DAC2_DMA_RMP
+ TIM7 and DAC2 DMA request remapping
+ bit
+ 14
+ 1
+
+
+ I2C_PB6_FM
+ Fast Mode Plus (FM+) driving capability
+ activation bits.
+ 16
+ 1
+
+
+ I2C_PB7_FM
+ Fast Mode Plus (FM+) driving capability
+ activation bits.
+ 17
+ 1
+
+
+ I2C_PB8_FM
+ Fast Mode Plus (FM+) driving capability
+ activation bits.
+ 18
+ 1
+
+
+ I2C_PB9_FM
+ Fast Mode Plus (FM+) driving capability
+ activation bits.
+ 19
+ 1
+
+
+ I2C1_FM
+ I2C1 Fast Mode Plus
+ 20
+ 1
+
+
+ I2C2_FM
+ I2C2 Fast Mode Plus
+ 21
+ 1
+
+
+ ENCODER_MODE
+ Encoder mode
+ 22
+ 2
+
+
+ FPU_IT
+ Interrupt enable bits from
+ FPU
+ 26
+ 6
+
+
+
+
+ SYSCFG_EXTICR1
+ SYSCFG_EXTICR1
+ external interrupt configuration register
+ 1
+ 0x8
+ 0x20
+ read-write
+ 0x0000
+
+
+ EXTI3
+ EXTI 3 configuration bits
+ 12
+ 4
+
+
+ EXTI2
+ EXTI 2 configuration bits
+ 8
+ 4
+
+
+ EXTI1
+ EXTI 1 configuration bits
+ 4
+ 4
+
+
+ EXTI0
+ EXTI 0 configuration bits
+ 0
+ 4
+
+
+
+
+ SYSCFG_EXTICR2
+ SYSCFG_EXTICR2
+ external interrupt configuration register
+ 2
+ 0xC
+ 0x20
+ read-write
+ 0x0000
+
+
+ EXTI7
+ EXTI 7 configuration bits
+ 12
+ 4
+
+
+ EXTI6
+ EXTI 6 configuration bits
+ 8
+ 4
+
+
+ EXTI5
+ EXTI 5 configuration bits
+ 4
+ 4
+
+
+ EXTI4
+ EXTI 4 configuration bits
+ 0
+ 4
+
+
+
+
+ SYSCFG_EXTICR3
+ SYSCFG_EXTICR3
+ external interrupt configuration register
+ 3
+ 0x10
+ 0x20
+ read-write
+ 0x0000
+
+
+ EXTI11
+ EXTI 11 configuration bits
+ 12
+ 4
+
+
+ EXTI10
+ EXTI 10 configuration bits
+ 8
+ 4
+
+
+ EXTI9
+ EXTI 9 configuration bits
+ 4
+ 4
+
+
+ EXTI8
+ EXTI 8 configuration bits
+ 0
+ 4
+
+
+
+
+ SYSCFG_EXTICR4
+ SYSCFG_EXTICR4
+ external interrupt configuration register
+ 4
+ 0x14
+ 0x20
+ read-write
+ 0x0000
+
+
+ EXTI15
+ EXTI 15 configuration bits
+ 12
+ 4
+
+
+ EXTI14
+ EXTI 14 configuration bits
+ 8
+ 4
+
+
+ EXTI13
+ EXTI 13 configuration bits
+ 4
+ 4
+
+
+ EXTI12
+ EXTI 12 configuration bits
+ 0
+ 4
+
+
+
+
+ SYSCFG_CFGR2
+ SYSCFG_CFGR2
+ configuration register 2
+ 0x18
+ 0x20
+ read-write
+ 0x0000
+
+
+ LOCUP_LOCK
+ Cortex-M0 LOCKUP bit enable
+ bit
+ 0
+ 1
+
+
+ SRAM_PARITY_LOCK
+ SRAM parity lock bit
+ 1
+ 1
+
+
+ PVD_LOCK
+ PVD lock enable bit
+ 2
+ 1
+
+
+ BYP_ADD_PAR
+ Bypass address bit 29 in parity
+ calculation
+ 4
+ 1
+
+
+ SRAM_PEF
+ SRAM parity flag
+ 8
+ 1
+
+
+
+
+ SYSCFG_RCR
+ SYSCFG_RCR
+ CCM SRAM protection register
+ 0x4
+ 0x20
+ read-write
+ 0x0000
+
+
+ PAGE0_WP
+ CCM SRAM page write protection
+ bit
+ 0
+ 1
+
+
+ PAGE1_WP
+ CCM SRAM page write protection
+ bit
+ 1
+ 1
+
+
+ PAGE2_WP
+ CCM SRAM page write protection
+ bit
+ 2
+ 1
+
+
+ PAGE3_WP
+ CCM SRAM page write protection
+ bit
+ 3
+ 1
+
+
+ PAGE4_WP
+ CCM SRAM page write protection
+ bit
+ 4
+ 1
+
+
+ PAGE5_WP
+ CCM SRAM page write protection
+ bit
+ 5
+ 1
+
+
+ PAGE6_WP
+ CCM SRAM page write protection
+ bit
+ 6
+ 1
+
+
+ PAGE7_WP
+ CCM SRAM page write protection
+ bit
+ 7
+ 1
+
+
+
+
+ COMP1_CSR
+ COMP1_CSR
+ control and status register
+ 0x1C
+ 0x20
+ 0x0000
+
+
+ COMP1EN
+ Comparator 1 enable
+ 0
+ 1
+ read-write
+
+
+ COMP1_INP_DAC
+ COMP1_INP_DAC
+ 1
+ 1
+ read-write
+
+
+ COMP1MODE
+ Comparator 1 mode
+ 2
+ 2
+ read-write
+
+
+ COMP1INSEL
+ Comparator 1 inverting input
+ selection
+ 4
+ 3
+ read-write
+
+
+ COMP1_OUT_SEL
+ Comparator 1 output
+ selection
+ 10
+ 4
+ read-write
+
+
+ COMP1POL
+ Comparator 1 output
+ polarity
+ 15
+ 1
+ read-write
+
+
+ COMP1HYST
+ Comparator 1 hysteresis
+ 16
+ 2
+ read-write
+
+
+ COMP1_BLANKING
+ Comparator 1 blanking
+ source
+ 18
+ 3
+ read-write
+
+
+ COMP1OUT
+ Comparator 1 output
+ 30
+ 1
+ read-only
+
+
+ COMP1LOCK
+ Comparator 1 lock
+ 31
+ 1
+ read-write
+
+
+
+
+ COMP2_CSR
+ COMP2_CSR
+ control and status register
+ 0x20
+ 0x20
+ read-write
+ 0x0000
+
+
+ COMP2EN
+ Comparator 2 enable
+ 0
+ 1
+
+
+ COMP2MODE
+ Comparator 2 mode
+ 2
+ 2
+
+
+ COMP2INSEL
+ Comparator 2 inverting input
+ selection
+ 4
+ 3
+
+
+ COMP2INPSEL
+ Comparator 2 non inverted input
+ selection
+ 7
+ 1
+
+
+ COMP2INMSEL
+ Comparator 1inverting input
+ selection
+ 9
+ 1
+
+
+ COMP2_OUT_SEL
+ Comparator 2 output
+ selection
+ 10
+ 4
+
+
+ COMP2POL
+ Comparator 2 output
+ polarity
+ 15
+ 1
+
+
+ COMP2HYST
+ Comparator 2 hysteresis
+ 16
+ 2
+
+
+ COMP2_BLANKING
+ Comparator 2 blanking
+ source
+ 18
+ 3
+
+
+ COMP2LOCK
+ Comparator 2 lock
+ 31
+ 1
+
+
+ COMP2OUT
+ Comparator 2 output
+ 30
+ 1
+
+
+
+
+ COMP3_CSR
+ COMP3_CSR
+ control and status register
+ 0x24
+ 0x20
+ 0x0000
+
+
+ COMP3EN
+ Comparator 3 enable
+ 0
+ 1
+ read-write
+
+
+ COMP3MODE
+ Comparator 3 mode
+ 2
+ 2
+ read-write
+
+
+ COMP3INSEL
+ Comparator 3 inverting input
+ selection
+ 4
+ 3
+ read-write
+
+
+ COMP3INPSEL
+ Comparator 3 non inverted input
+ selection
+ 7
+ 1
+ read-write
+
+
+ COMP3_OUT_SEL
+ Comparator 3 output
+ selection
+ 10
+ 4
+ read-write
+
+
+ COMP3POL
+ Comparator 3 output
+ polarity
+ 15
+ 1
+ read-write
+
+
+ COMP3HYST
+ Comparator 3 hysteresis
+ 16
+ 2
+ read-write
+
+
+ COMP3_BLANKING
+ Comparator 3 blanking
+ source
+ 18
+ 3
+ read-write
+
+
+ COMP3OUT
+ Comparator 3 output
+ 30
+ 1
+ read-only
+
+
+ COMP3LOCK
+ Comparator 3 lock
+ 31
+ 1
+ read-write
+
+
+
+
+ COMP4_CSR
+ COMP4_CSR
+ control and status register
+ 0x28
+ 0x20
+ 0x0000
+
+
+ COMP4EN
+ Comparator 4 enable
+ 0
+ 1
+ read-write
+
+
+ COMP4MODE
+ Comparator 4 mode
+ 2
+ 2
+ read-write
+
+
+ COMP4INSEL
+ Comparator 4 inverting input
+ selection
+ 4
+ 3
+ read-write
+
+
+ COMP4INPSEL
+ Comparator 4 non inverted input
+ selection
+ 7
+ 1
+ read-write
+
+
+ COM4WINMODE
+ Comparator 4 window mode
+ 9
+ 1
+ read-write
+
+
+ COMP4_OUT_SEL
+ Comparator 4 output
+ selection
+ 10
+ 4
+ read-write
+
+
+ COMP4POL
+ Comparator 4 output
+ polarity
+ 15
+ 1
+ read-write
+
+
+ COMP4HYST
+ Comparator 4 hysteresis
+ 16
+ 2
+ read-write
+
+
+ COMP4_BLANKING
+ Comparator 4 blanking
+ source
+ 18
+ 3
+ read-write
+
+
+ COMP4OUT
+ Comparator 4 output
+ 30
+ 1
+ read-only
+
+
+ COMP4LOCK
+ Comparator 4 lock
+ 31
+ 1
+ read-write
+
+
+
+
+ COMP5_CSR
+ COMP5_CSR
+ control and status register
+ 0x2C
+ 0x20
+ 0x0000
+
+
+ COMP5EN
+ Comparator 5 enable
+ 0
+ 1
+ read-write
+
+
+ COMP5MODE
+ Comparator 5 mode
+ 2
+ 2
+ read-write
+
+
+ COMP5INSEL
+ Comparator 5 inverting input
+ selection
+ 4
+ 3
+ read-write
+
+
+ COMP5INPSEL
+ Comparator 5 non inverted input
+ selection
+ 7
+ 1
+ read-write
+
+
+ COMP5_OUT_SEL
+ Comparator 5 output
+ selection
+ 10
+ 4
+ read-write
+
+
+ COMP5POL
+ Comparator 5 output
+ polarity
+ 15
+ 1
+ read-write
+
+
+ COMP5HYST
+ Comparator 5 hysteresis
+ 16
+ 2
+ read-write
+
+
+ COMP5_BLANKING
+ Comparator 5 blanking
+ source
+ 18
+ 3
+ read-write
+
+
+ COMP5OUT
+ Comparator51 output
+ 30
+ 1
+ read-only
+
+
+ COMP5LOCK
+ Comparator 5 lock
+ 31
+ 1
+ read-write
+
+
+
+
+ COMP6_CSR
+ COMP6_CSR
+ control and status register
+ 0x30
+ 0x20
+ 0x0000
+
+
+ COMP6EN
+ Comparator 6 enable
+ 0
+ 1
+ read-write
+
+
+ COMP6MODE
+ Comparator 6 mode
+ 2
+ 2
+ read-write
+
+
+ COMP6INSEL
+ Comparator 6 inverting input
+ selection
+ 4
+ 3
+ read-write
+
+
+ COMP6INPSEL
+ Comparator 6 non inverted input
+ selection
+ 7
+ 1
+ read-write
+
+
+ COM6WINMODE
+ Comparator 6 window mode
+ 9
+ 1
+ read-write
+
+
+ COMP6_OUT_SEL
+ Comparator 6 output
+ selection
+ 10
+ 4
+ read-write
+
+
+ COMP6POL
+ Comparator 6 output
+ polarity
+ 15
+ 1
+ read-write
+
+
+ COMP6HYST
+ Comparator 6 hysteresis
+ 16
+ 2
+ read-write
+
+
+ COMP6_BLANKING
+ Comparator 6 blanking
+ source
+ 18
+ 3
+ read-write
+
+
+ COMP6OUT
+ Comparator 6 output
+ 30
+ 1
+ read-only
+
+
+ COMP6LOCK
+ Comparator 6 lock
+ 31
+ 1
+ read-write
+
+
+
+
+ COMP7_CSR
+ COMP7_CSR
+ control and status register
+ 0x34
+ 0x20
+ 0x0000
+
+
+ COMP7EN
+ Comparator 7 enable
+ 0
+ 1
+ read-write
+
+
+ COMP7MODE
+ Comparator 7 mode
+ 2
+ 2
+ read-write
+
+
+ COMP7INSEL
+ Comparator 7 inverting input
+ selection
+ 4
+ 3
+ read-write
+
+
+ COMP7INPSEL
+ Comparator 7 non inverted input
+ selection
+ 7
+ 1
+ read-write
+
+
+ COMP7_OUT_SEL
+ Comparator 7 output
+ selection
+ 10
+ 4
+ read-write
+
+
+ COMP7POL
+ Comparator 7 output
+ polarity
+ 15
+ 1
+ read-write
+
+
+ COMP7HYST
+ Comparator 7 hysteresis
+ 16
+ 2
+ read-write
+
+
+ COMP7_BLANKING
+ Comparator 7 blanking
+ source
+ 18
+ 3
+ read-write
+
+
+ COMP7OUT
+ Comparator 7 output
+ 30
+ 1
+ read-only
+
+
+ COMP7LOCK
+ Comparator 7 lock
+ 31
+ 1
+ read-write
+
+
+
+
+ OPAMP1_CSR
+ OPAMP1_CSR
+ control register
+ 0x38
+ 0x20
+ 0x0000
+
+
+ OPAMP1_EN
+ OPAMP1 enable
+ 0
+ 1
+ read-write
+
+
+ FORCE_VP
+ FORCE_VP
+ 1
+ 1
+ read-write
+
+
+ VP_SEL
+ OPAMP1 Non inverting input
+ selection
+ 2
+ 2
+ read-write
+
+
+ VM_SEL
+ OPAMP1 inverting input
+ selection
+ 5
+ 2
+ read-write
+
+
+ TCM_EN
+ Timer controlled Mux mode
+ enable
+ 7
+ 1
+ read-write
+
+
+ VMS_SEL
+ OPAMP1 inverting input secondary
+ selection
+ 8
+ 1
+ read-write
+
+
+ VPS_SEL
+ OPAMP1 Non inverting input secondary
+ selection
+ 9
+ 2
+ read-write
+
+
+ CALON
+ Calibration mode enable
+ 11
+ 1
+ read-write
+
+
+ CALSEL
+ Calibration selection
+ 12
+ 2
+ read-write
+
+
+ PGA_GAIN
+ Gain in PGA mode
+ 14
+ 4
+ read-write
+
+
+ USER_TRIM
+ User trimming enable
+ 18
+ 1
+ read-write
+
+
+ TRIMOFFSETP
+ Offset trimming value
+ (PMOS)
+ 19
+ 5
+ read-write
+
+
+ TRIMOFFSETN
+ Offset trimming value
+ (NMOS)
+ 24
+ 5
+ read-write
+
+
+ TSTREF
+ TSTREF
+ 29
+ 1
+ read-write
+
+
+ OUTCAL
+ OPAMP 1 ouput status flag
+ 30
+ 1
+ read-only
+
+
+ LOCK
+ OPAMP 1 lock
+ 31
+ 1
+ read-write
+
+
+
+
+ OPAMP2_CSR
+ OPAMP2_CSR
+ control register
+ 0x3C
+ 0x20
+ 0x0000
+
+
+ OPAMP2EN
+ OPAMP2 enable
+ 0
+ 1
+ read-write
+
+
+ FORCE_VP
+ FORCE_VP
+ 1
+ 1
+ read-write
+
+
+ VP_SEL
+ OPAMP2 Non inverting input
+ selection
+ 2
+ 2
+ read-write
+
+
+ VM_SEL
+ OPAMP2 inverting input
+ selection
+ 5
+ 2
+ read-write
+
+
+ TCM_EN
+ Timer controlled Mux mode
+ enable
+ 7
+ 1
+ read-write
+
+
+ VMS_SEL
+ OPAMP2 inverting input secondary
+ selection
+ 8
+ 1
+ read-write
+
+
+ VPS_SEL
+ OPAMP2 Non inverting input secondary
+ selection
+ 9
+ 2
+ read-write
+
+
+ CALON
+ Calibration mode enable
+ 11
+ 1
+ read-write
+
+
+ CALSEL
+ Calibration selection
+ 12
+ 2
+ read-write
+
+
+ PGA_GAIN
+ Gain in PGA mode
+ 14
+ 4
+ read-write
+
+
+ USER_TRIM
+ User trimming enable
+ 18
+ 1
+ read-write
+
+
+ TRIMOFFSETP
+ Offset trimming value
+ (PMOS)
+ 19
+ 5
+ read-write
+
+
+ TRIMOFFSETN
+ Offset trimming value
+ (NMOS)
+ 24
+ 5
+ read-write
+
+
+ TSTREF
+ TSTREF
+ 29
+ 1
+ read-write
+
+
+ OUTCAL
+ OPAMP 2 ouput status flag
+ 30
+ 1
+ read-only
+
+
+ LOCK
+ OPAMP 2 lock
+ 31
+ 1
+ read-write
+
+
+
+
+ OPAMP3_CSR
+ OPAMP3_CSR
+ control register
+ 0x40
+ 0x20
+ 0x0000
+
+
+ OPAMP3EN
+ OPAMP3 enable
+ 0
+ 1
+ read-write
+
+
+ FORCE_VP
+ FORCE_VP
+ 1
+ 1
+ read-write
+
+
+ VP_SEL
+ OPAMP3 Non inverting input
+ selection
+ 2
+ 2
+ read-write
+
+
+ VM_SEL
+ OPAMP3 inverting input
+ selection
+ 5
+ 2
+ read-write
+
+
+ TCM_EN
+ Timer controlled Mux mode
+ enable
+ 7
+ 1
+ read-write
+
+
+ VMS_SEL
+ OPAMP3 inverting input secondary
+ selection
+ 8
+ 1
+ read-write
+
+
+ VPS_SEL
+ OPAMP3 Non inverting input secondary
+ selection
+ 9
+ 2
+ read-write
+
+
+ CALON
+ Calibration mode enable
+ 11
+ 1
+ read-write
+
+
+ CALSEL
+ Calibration selection
+ 12
+ 2
+ read-write
+
+
+ PGA_GAIN
+ Gain in PGA mode
+ 14
+ 4
+ read-write
+
+
+ USER_TRIM
+ User trimming enable
+ 18
+ 1
+ read-write
+
+
+ TRIMOFFSETP
+ Offset trimming value
+ (PMOS)
+ 19
+ 5
+ read-write
+
+
+ TRIMOFFSETN
+ Offset trimming value
+ (NMOS)
+ 24
+ 5
+ read-write
+
+
+ TSTREF
+ TSTREF
+ 29
+ 1
+ read-write
+
+
+ OUTCAL
+ OPAMP 3 ouput status flag
+ 30
+ 1
+ read-only
+
+
+ LOCK
+ OPAMP 3 lock
+ 31
+ 1
+ read-write
+
+
+
+
+ OPAMP4_CSR
+ OPAMP4_CSR
+ control register
+ 0x44
+ 0x20
+ 0x0000
+
+
+ OPAMP4EN
+ OPAMP4 enable
+ 0
+ 1
+ read-write
+
+
+ FORCE_VP
+ FORCE_VP
+ 1
+ 1
+ read-write
+
+
+ VP_SEL
+ OPAMP4 Non inverting input
+ selection
+ 2
+ 2
+ read-write
+
+
+ VM_SEL
+ OPAMP4 inverting input
+ selection
+ 5
+ 2
+ read-write
+
+
+ TCM_EN
+ Timer controlled Mux mode
+ enable
+ 7
+ 1
+ read-write
+
+
+ VMS_SEL
+ OPAMP4 inverting input secondary
+ selection
+ 8
+ 1
+ read-write
+
+
+ VPS_SEL
+ OPAMP4 Non inverting input secondary
+ selection
+ 9
+ 2
+ read-write
+
+
+ CALON
+ Calibration mode enable
+ 11
+ 1
+ read-write
+
+
+ CALSEL
+ Calibration selection
+ 12
+ 2
+ read-write
+
+
+ PGA_GAIN
+ Gain in PGA mode
+ 14
+ 4
+ read-write
+
+
+ USER_TRIM
+ User trimming enable
+ 18
+ 1
+ read-write
+
+
+ TRIMOFFSETP
+ Offset trimming value
+ (PMOS)
+ 19
+ 5
+ read-write
+
+
+ TRIMOFFSETN
+ Offset trimming value
+ (NMOS)
+ 24
+ 5
+ read-write
+
+
+ TSTREF
+ TSTREF
+ 29
+ 1
+ read-write
+
+
+ OUTCAL
+ OPAMP 4 ouput status flag
+ 30
+ 1
+ read-only
+
+
+ LOCK
+ OPAMP 4 lock
+ 31
+ 1
+ read-write
+
+
+
+
+ SYSCFG_CFGR3
+ SYSCFG_CFGR3
+ SYSCFG configuration register
+ 3
+ 0x50
+ 0x20
+ read-write
+ 0x0000
+
+
+ SPI1_RX_DMA_RMP
+ SPI1_RX DMA remapping bit
+ 0
+ 2
+
+
+ SPI1_TX_DMA_RMP
+ SPI1_TX DMA remapping bit
+ 2
+ 2
+
+
+ I2C1_RX_DMA_RMP
+ I2C1_RX DMA remapping bit
+ 4
+ 2
+
+
+ I2C1_TX_DMA_RMP
+ I2C1_TX DMA remapping bit
+ 6
+ 2
+
+
+ ADC2_DMA_RMP
+ ADC2 DMA channel remapping
+ bit
+ 8
+ 2
+
+
+
+
+ SYSCFG_CFGR4
+ SYSCFG_CFGR4
+ SYSCFG configuration register
+ 4
+ 0x48
+ 0x20
+ read-write
+ 0x0000
+
+
+ ADC12_EXT2_RMP
+ Controls the Input trigger of ADC12
+ regular channel EXT2
+ 0
+ 1
+
+
+ ADC12_EXT3_RMP
+ Controls the Input trigger of ADC12
+ regular channel EXT3
+ 1
+ 1
+
+
+ ADC12_EXT5_RMP
+ Controls the Input trigger of ADC12
+ regular channel EXT5
+ 2
+ 1
+
+
+ ADC12_EXT13_RMP
+ Controls the Input trigger of ADC12
+ regular channel EXT13
+ 3
+ 1
+
+
+ ADC12_EXT15_RMP
+ Controls the Input trigger of ADC12
+ regular channel EXT15
+ 4
+ 1
+
+
+ ADC12_JEXT3_RMP
+ Controls the Input trigger of ADC12
+ injected channel EXTI3
+ 5
+ 1
+
+
+ ADC12_JEXT6_RMP
+ Controls the Input trigger of ADC12
+ injected channel EXTI6
+ 6
+ 1
+
+
+ ADC12_JEXT13_RMP
+ Controls the Input trigger of ADC12
+ injected channel EXTI13
+ 7
+ 1
+
+
+ ADC34_EXT5_RMP
+ Controls the Input trigger of ADC34
+ regular channel EXT5
+ 8
+ 1
+
+
+ ADC34_EXT6_RMP
+ Controls the Input trigger of ADC34
+ regular channel EXT6
+ 9
+ 1
+
+
+ ADC34_EXT15_RMP
+ Controls the Input trigger of ADC34
+ regular channel EXT15
+ 10
+ 1
+
+
+ ADC34_JEXT5_RMP
+ Controls the Input trigger of ADC34
+ injected channel JEXT5
+ 11
+ 1
+
+
+ ADC34_JEXT11_RMP
+ Controls the Input trigger of ADC34
+ injected channel JEXT11
+ 12
+ 1
+
+
+ ADC34_JEXT14_RMP
+ Controls the Input trigger of ADC34
+ injected channel JEXT14
+ 13
+ 1
+
+
+
+
+
+
+ FMC
+ Flexible memory controller
+ FMC
+ 0xA0000400
+
+ 0x0
+ 0xC00
+ registers
+
+
+ FMC
+ FSMC global interrupt
+ 48
+
+
+
+ BCR1
+ BCR1
+ SRAM/NOR-Flash chip-select control register
+ 1
+ 0x0
+ 0x20
+ read-write
+ 0x000030D0
+
+
+ CCLKEN
+ CCLKEN
+ 20
+ 1
+
+
+ CBURSTRW
+ CBURSTRW
+ 19
+ 1
+
+
+ ASYNCWAIT
+ ASYNCWAIT
+ 15
+ 1
+
+
+ EXTMOD
+ EXTMOD
+ 14
+ 1
+
+
+ WAITEN
+ WAITEN
+ 13
+ 1
+
+
+ WREN
+ WREN
+ 12
+ 1
+
+
+ WAITCFG
+ WAITCFG
+ 11
+ 1
+
+
+ WAITPOL
+ WAITPOL
+ 9
+ 1
+
+
+ BURSTEN
+ BURSTEN
+ 8
+ 1
+
+
+ FACCEN
+ FACCEN
+ 6
+ 1
+
+
+ MWID
+ MWID
+ 4
+ 2
+
+
+ MTYP
+ MTYP
+ 2
+ 2
+
+
+ MUXEN
+ MUXEN
+ 1
+ 1
+
+
+ MBKEN
+ MBKEN
+ 0
+ 1
+
+
+
+
+ BTR1
+ BTR1
+ SRAM/NOR-Flash chip-select timing register
+ 1
+ 0x4
+ 0x20
+ read-write
+ 0xFFFFFFFF
+
+
+ ACCMOD
+ ACCMOD
+ 28
+ 2
+
+
+ DATLAT
+ DATLAT
+ 24
+ 4
+
+
+ CLKDIV
+ CLKDIV
+ 20
+ 4
+
+
+ BUSTURN
+ BUSTURN
+ 16
+ 4
+
+
+ DATAST
+ DATAST
+ 8
+ 8
+
+
+ ADDHLD
+ ADDHLD
+ 4
+ 4
+
+
+ ADDSET
+ ADDSET
+ 0
+ 4
+
+
+
+
+ BCR2
+ BCR2
+ SRAM/NOR-Flash chip-select control register
+ 2
+ 0x8
+ 0x20
+ read-write
+ 0x000030D0
+
+
+ CBURSTRW
+ CBURSTRW
+ 19
+ 1
+
+
+ ASYNCWAIT
+ ASYNCWAIT
+ 15
+ 1
+
+
+ EXTMOD
+ EXTMOD
+ 14
+ 1
+
+
+ WAITEN
+ WAITEN
+ 13
+ 1
+
+
+ WREN
+ WREN
+ 12
+ 1
+
+
+ WAITCFG
+ WAITCFG
+ 11
+ 1
+
+
+ WRAPMOD
+ WRAPMOD
+ 10
+ 1
+
+
+ WAITPOL
+ WAITPOL
+ 9
+ 1
+
+
+ BURSTEN
+ BURSTEN
+ 8
+ 1
+
+
+ FACCEN
+ FACCEN
+ 6
+ 1
+
+
+ MWID
+ MWID
+ 4
+ 2
+
+
+ MTYP
+ MTYP
+ 2
+ 2
+
+
+ MUXEN
+ MUXEN
+ 1
+ 1
+
+
+ MBKEN
+ MBKEN
+ 0
+ 1
+
+
+
+
+ BTR2
+ BTR2
+ SRAM/NOR-Flash chip-select timing register
+ 2
+ 0xC
+ 0x20
+ read-write
+ 0xFFFFFFFF
+
+
+ ACCMOD
+ ACCMOD
+ 28
+ 2
+
+
+ DATLAT
+ DATLAT
+ 24
+ 4
+
+
+ CLKDIV
+ CLKDIV
+ 20
+ 4
+
+
+ BUSTURN
+ BUSTURN
+ 16
+ 4
+
+
+ DATAST
+ DATAST
+ 8
+ 8
+
+
+ ADDHLD
+ ADDHLD
+ 4
+ 4
+
+
+ ADDSET
+ ADDSET
+ 0
+ 4
+
+
+
+
+ BCR3
+ BCR3
+ SRAM/NOR-Flash chip-select control register
+ 3
+ 0x10
+ 0x20
+ read-write
+ 0x000030D0
+
+
+ CBURSTRW
+ CBURSTRW
+ 19
+ 1
+
+
+ ASYNCWAIT
+ ASYNCWAIT
+ 15
+ 1
+
+
+ EXTMOD
+ EXTMOD
+ 14
+ 1
+
+
+ WAITEN
+ WAITEN
+ 13
+ 1
+
+
+ WREN
+ WREN
+ 12
+ 1
+
+
+ WAITCFG
+ WAITCFG
+ 11
+ 1
+
+
+ WRAPMOD
+ WRAPMOD
+ 10
+ 1
+
+
+ WAITPOL
+ WAITPOL
+ 9
+ 1
+
+
+ BURSTEN
+ BURSTEN
+ 8
+ 1
+
+
+ FACCEN
+ FACCEN
+ 6
+ 1
+
+
+ MWID
+ MWID
+ 4
+ 2
+
+
+ MTYP
+ MTYP
+ 2
+ 2
+
+
+ MUXEN
+ MUXEN
+ 1
+ 1
+
+
+ MBKEN
+ MBKEN
+ 0
+ 1
+
+
+
+
+ BTR3
+ BTR3
+ SRAM/NOR-Flash chip-select timing register
+ 3
+ 0x14
+ 0x20
+ read-write
+ 0xFFFFFFFF
+
+
+ ACCMOD
+ ACCMOD
+ 28
+ 2
+
+
+ DATLAT
+ DATLAT
+ 24
+ 4
+
+
+ CLKDIV
+ CLKDIV
+ 20
+ 4
+
+
+ BUSTURN
+ BUSTURN
+ 16
+ 4
+
+
+ DATAST
+ DATAST
+ 8
+ 8
+
+
+ ADDHLD
+ ADDHLD
+ 4
+ 4
+
+
+ ADDSET
+ ADDSET
+ 0
+ 4
+
+
+
+
+ BCR4
+ BCR4
+ SRAM/NOR-Flash chip-select control register
+ 4
+ 0x18
+ 0x20
+ read-write
+ 0x000030D0
+
+
+ CBURSTRW
+ CBURSTRW
+ 19
+ 1
+
+
+ ASYNCWAIT
+ ASYNCWAIT
+ 15
+ 1
+
+
+ EXTMOD
+ EXTMOD
+ 14
+ 1
+
+
+ WAITEN
+ WAITEN
+ 13
+ 1
+
+
+ WREN
+ WREN
+ 12
+ 1
+
+
+ WAITCFG
+ WAITCFG
+ 11
+ 1
+
+
+ WRAPMOD
+ WRAPMOD
+ 10
+ 1
+
+
+ WAITPOL
+ WAITPOL
+ 9
+ 1
+
+
+ BURSTEN
+ BURSTEN
+ 8
+ 1
+
+
+ FACCEN
+ FACCEN
+ 6
+ 1
+
+
+ MWID
+ MWID
+ 4
+ 2
+
+
+ MTYP
+ MTYP
+ 2
+ 2
+
+
+ MUXEN
+ MUXEN
+ 1
+ 1
+
+
+ MBKEN
+ MBKEN
+ 0
+ 1
+
+
+
+
+ BTR4
+ BTR4
+ SRAM/NOR-Flash chip-select timing register
+ 4
+ 0x1C
+ 0x20
+ read-write
+ 0xFFFFFFFF
+
+
+ ACCMOD
+ ACCMOD
+ 28
+ 2
+
+
+ DATLAT
+ DATLAT
+ 24
+ 4
+
+
+ CLKDIV
+ CLKDIV
+ 20
+ 4
+
+
+ BUSTURN
+ BUSTURN
+ 16
+ 4
+
+
+ DATAST
+ DATAST
+ 8
+ 8
+
+
+ ADDHLD
+ ADDHLD
+ 4
+ 4
+
+
+ ADDSET
+ ADDSET
+ 0
+ 4
+
+
+
+
+ PCR2
+ PCR2
+ PC Card/NAND Flash control register
+ 2
+ 0x60
+ 0x20
+ read-write
+ 0x00000018
+
+
+ ECCPS
+ ECCPS
+ 17
+ 3
+
+
+ TAR
+ TAR
+ 13
+ 4
+
+
+ TCLR
+ TCLR
+ 9
+ 4
+
+
+ ECCEN
+ ECCEN
+ 6
+ 1
+
+
+ PWID
+ PWID
+ 4
+ 2
+
+
+ PTYP
+ PTYP
+ 3
+ 1
+
+
+ PBKEN
+ PBKEN
+ 2
+ 1
+
+
+ PWAITEN
+ PWAITEN
+ 1
+ 1
+
+
+
+
+ SR2
+ SR2
+ FIFO status and interrupt register
+ 2
+ 0x64
+ 0x20
+ 0x00000040
+
+
+ FEMPT
+ FEMPT
+ 6
+ 1
+ read-only
+
+
+ IFEN
+ IFEN
+ 5
+ 1
+ read-write
+
+
+ ILEN
+ ILEN
+ 4
+ 1
+ read-write
+
+
+ IREN
+ IREN
+ 3
+ 1
+ read-write
+
+
+ IFS
+ IFS
+ 2
+ 1
+ read-write
+
+
+ ILS
+ ILS
+ 1
+ 1
+ read-write
+
+
+ IRS
+ IRS
+ 0
+ 1
+ read-write
+
+
+
+
+ PMEM2
+ PMEM2
+ Common memory space timing register
+ 2
+ 0x68
+ 0x20
+ read-write
+ 0xFCFCFCFC
+
+
+ MEMHIZx
+ MEMHIZx
+ 24
+ 8
+
+
+ MEMHOLDx
+ MEMHOLDx
+ 16
+ 8
+
+
+ MEMWAITx
+ MEMWAITx
+ 8
+ 8
+
+
+ MEMSETx
+ MEMSETx
+ 0
+ 8
+
+
+
+
+ PATT2
+ PATT2
+ Attribute memory space timing register
+ 2
+ 0x6C
+ 0x20
+ read-write
+ 0xFCFCFCFC
+
+
+ ATTHIZx
+ ATTHIZx
+ 24
+ 8
+
+
+ ATTHOLDx
+ ATTHOLDx
+ 16
+ 8
+
+
+ ATTWAITx
+ ATTWAITx
+ 8
+ 8
+
+
+ ATTSETx
+ ATTSETx
+ 0
+ 8
+
+
+
+
+ ECCR2
+ ECCR2
+ ECC result register 2
+ 0x74
+ 0x20
+ read-only
+ 0x00000000
+
+
+ ECCx
+ ECCx
+ 0
+ 32
+
+
+
+
+ PCR3
+ PCR3
+ PC Card/NAND Flash control register
+ 3
+ 0x80
+ 0x20
+ read-write
+ 0x00000018
+
+
+ ECCPS
+ ECCPS
+ 17
+ 3
+
+
+ TAR
+ TAR
+ 13
+ 4
+
+
+ TCLR
+ TCLR
+ 9
+ 4
+
+
+ ECCEN
+ ECCEN
+ 6
+ 1
+
+
+ PWID
+ PWID
+ 4
+ 2
+
+
+ PTYP
+ PTYP
+ 3
+ 1
+
+
+ PBKEN
+ PBKEN
+ 2
+ 1
+
+
+ PWAITEN
+ PWAITEN
+ 1
+ 1
+
+
+
+
+ SR3
+ SR3
+ FIFO status and interrupt register
+ 3
+ 0x84
+ 0x20
+ 0x00000040
+
+
+ FEMPT
+ FEMPT
+ 6
+ 1
+ read-only
+
+
+ IFEN
+ IFEN
+ 5
+ 1
+ read-write
+
+
+ ILEN
+ ILEN
+ 4
+ 1
+ read-write
+
+
+ IREN
+ IREN
+ 3
+ 1
+ read-write
+
+
+ IFS
+ IFS
+ 2
+ 1
+ read-write
+
+
+ ILS
+ ILS
+ 1
+ 1
+ read-write
+
+
+ IRS
+ IRS
+ 0
+ 1
+ read-write
+
+
+
+
+ PMEM3
+ PMEM3
+ Common memory space timing register
+ 3
+ 0x88
+ 0x20
+ read-write
+ 0xFCFCFCFC
+
+
+ MEMHIZx
+ MEMHIZx
+ 24
+ 8
+
+
+ MEMHOLDx
+ MEMHOLDx
+ 16
+ 8
+
+
+ MEMWAITx
+ MEMWAITx
+ 8
+ 8
+
+
+ MEMSETx
+ MEMSETx
+ 0
+ 8
+
+
+
+
+ PATT3
+ PATT3
+ Attribute memory space timing register
+ 3
+ 0x8C
+ 0x20
+ read-write
+ 0xFCFCFCFC
+
+
+ ATTHIZx
+ ATTHIZx
+ 24
+ 8
+
+
+ ATTHOLDx
+ ATTHOLDx
+ 16
+ 8
+
+
+ ATTWAITx
+ ATTWAITx
+ 8
+ 8
+
+
+ ATTSETx
+ ATTSETx
+ 0
+ 8
+
+
+
+
+ ECCR3
+ ECCR3
+ ECC result register 3
+ 0x94
+ 0x20
+ read-only
+ 0x00000000
+
+
+ ECCx
+ ECCx
+ 0
+ 32
+
+
+
+
+ PCR4
+ PCR4
+ PC Card/NAND Flash control register
+ 4
+ 0xA0
+ 0x20
+ read-write
+ 0x00000018
+
+
+ ECCPS
+ ECCPS
+ 17
+ 3
+
+
+ TAR
+ TAR
+ 13
+ 4
+
+
+ TCLR
+ TCLR
+ 9
+ 4
+
+
+ ECCEN
+ ECCEN
+ 6
+ 1
+
+
+ PWID
+ PWID
+ 4
+ 2
+
+
+ PTYP
+ PTYP
+ 3
+ 1
+
+
+ PBKEN
+ PBKEN
+ 2
+ 1
+
+
+ PWAITEN
+ PWAITEN
+ 1
+ 1
+
+
+
+
+ SR4
+ SR4
+ FIFO status and interrupt register
+ 4
+ 0xA4
+ 0x20
+ 0x00000040
+
+
+ FEMPT
+ FEMPT
+ 6
+ 1
+ read-only
+
+
+ IFEN
+ IFEN
+ 5
+ 1
+ read-write
+
+
+ ILEN
+ ILEN
+ 4
+ 1
+ read-write
+
+
+ IREN
+ IREN
+ 3
+ 1
+ read-write
+
+
+ IFS
+ IFS
+ 2
+ 1
+ read-write
+
+
+ ILS
+ ILS
+ 1
+ 1
+ read-write
+
+
+ IRS
+ IRS
+ 0
+ 1
+ read-write
+
+
+
+
+ PMEM4
+ PMEM4
+ Common memory space timing register
+ 4
+ 0xA8
+ 0x20
+ read-write
+ 0xFCFCFCFC
+
+
+ MEMHIZx
+ MEMHIZx
+ 24
+ 8
+
+
+ MEMHOLDx
+ MEMHOLDx
+ 16
+ 8
+
+
+ MEMWAITx
+ MEMWAITx
+ 8
+ 8
+
+
+ MEMSETx
+ MEMSETx
+ 0
+ 8
+
+
+
+
+ PATT4
+ PATT4
+ Attribute memory space timing register
+ 4
+ 0xAC
+ 0x20
+ read-write
+ 0xFCFCFCFC
+
+
+ ATTHIZx
+ ATTHIZx
+ 24
+ 8
+
+
+ ATTHOLDx
+ ATTHOLDx
+ 16
+ 8
+
+
+ ATTWAITx
+ ATTWAITx
+ 8
+ 8
+
+
+ ATTSETx
+ ATTSETx
+ 0
+ 8
+
+
+
+
+ PIO4
+ PIO4
+ I/O space timing register 4
+ 0xB0
+ 0x20
+ read-write
+ 0xFCFCFCFC
+
+
+ IOHIZx
+ IOHIZx
+ 24
+ 8
+
+
+ IOHOLDx
+ IOHOLDx
+ 16
+ 8
+
+
+ IOWAITx
+ IOWAITx
+ 8
+ 8
+
+
+ IOSETx
+ IOSETx
+ 0
+ 8
+
+
+
+
+ BWTR1
+ BWTR1
+ SRAM/NOR-Flash write timing registers
+ 1
+ 0x104
+ 0x20
+ read-write
+ 0x0FFFFFFF
+
+
+ ACCMOD
+ ACCMOD
+ 28
+ 2
+
+
+ DATLAT
+ DATLAT
+ 24
+ 4
+
+
+ CLKDIV
+ CLKDIV
+ 20
+ 4
+
+
+ BUSTURN
+ Bus turnaround phase
+ duration
+ 16
+ 4
+
+
+ DATAST
+ DATAST
+ 8
+ 8
+
+
+ ADDHLD
+ ADDHLD
+ 4
+ 4
+
+
+ ADDSET
+ ADDSET
+ 0
+ 4
+
+
+
+
+ BWTR2
+ BWTR2
+ SRAM/NOR-Flash write timing registers
+ 2
+ 0x10C
+ 0x20
+ read-write
+ 0x0FFFFFFF
+
+
+ ACCMOD
+ ACCMOD
+ 28
+ 2
+
+
+ DATLAT
+ DATLAT
+ 24
+ 4
+
+
+ CLKDIV
+ CLKDIV
+ 20
+ 4
+
+
+ BUSTURN
+ Bus turnaround phase
+ duration
+ 16
+ 4
+
+
+ DATAST
+ DATAST
+ 8
+ 8
+
+
+ ADDHLD
+ ADDHLD
+ 4
+ 4
+
+
+ ADDSET
+ ADDSET
+ 0
+ 4
+
+
+
+
+ BWTR3
+ BWTR3
+ SRAM/NOR-Flash write timing registers
+ 3
+ 0x114
+ 0x20
+ read-write
+ 0x0FFFFFFF
+
+
+ ACCMOD
+ ACCMOD
+ 28
+ 2
+
+
+ DATLAT
+ DATLAT
+ 24
+ 4
+
+
+ CLKDIV
+ CLKDIV
+ 20
+ 4
+
+
+ BUSTURN
+ Bus turnaround phase
+ duration
+ 16
+ 4
+
+
+ DATAST
+ DATAST
+ 8
+ 8
+
+
+ ADDHLD
+ ADDHLD
+ 4
+ 4
+
+
+ ADDSET
+ ADDSET
+ 0
+ 4
+
+
+
+
+ BWTR4
+ BWTR4
+ SRAM/NOR-Flash write timing registers
+ 4
+ 0x11C
+ 0x20
+ read-write
+ 0x0FFFFFFF
+
+
+ ACCMOD
+ ACCMOD
+ 28
+ 2
+
+
+ DATLAT
+ DATLAT
+ 24
+ 4
+
+
+ CLKDIV
+ CLKDIV
+ 20
+ 4
+
+
+ BUSTURN
+ Bus turnaround phase
+ duration
+ 16
+ 4
+
+
+ DATAST
+ DATAST
+ 8
+ 8
+
+
+ ADDHLD
+ ADDHLD
+ 4
+ 4
+
+
+ ADDSET
+ ADDSET
+ 0
+ 4
+
+
+
+
+
+
+
diff --git a/satrs-example-stm32f3-disco/build.rs b/satrs-example-stm32f3-disco/build.rs
deleted file mode 100644
index 98f603e..0000000
--- a/satrs-example-stm32f3-disco/build.rs
+++ /dev/null
@@ -1,18 +0,0 @@
-use std::env;
-use std::fs::File;
-use std::io::Write;
-use std::path::PathBuf;
-
-fn main() {
- // Put the linker script somewhere the linker can find it
- let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap());
- File::create(out.join("memory.x"))
- .unwrap()
- .write_all(include_bytes!("memory.x"))
- .unwrap();
- println!("cargo:rustc-link-search={}", out.display());
-
- // Only re-run the build script when memory.x is changed,
- // instead of when any part of the source code changes.
- println!("cargo:rerun-if-changed=memory.x");
-}
diff --git a/satrs-example-stm32f3-disco/jlink.gdb b/satrs-example-stm32f3-disco/legacy/jlink.gdb
similarity index 100%
rename from satrs-example-stm32f3-disco/jlink.gdb
rename to satrs-example-stm32f3-disco/legacy/jlink.gdb
diff --git a/satrs-example-stm32f3-disco/openocd.cfg b/satrs-example-stm32f3-disco/legacy/openocd.cfg
similarity index 100%
rename from satrs-example-stm32f3-disco/openocd.cfg
rename to satrs-example-stm32f3-disco/legacy/openocd.cfg
diff --git a/satrs-example-stm32f3-disco/openocd.gdb b/satrs-example-stm32f3-disco/legacy/openocd.gdb
similarity index 92%
rename from satrs-example-stm32f3-disco/openocd.gdb
rename to satrs-example-stm32f3-disco/legacy/openocd.gdb
index 06e81b1..2453de8 100644
--- a/satrs-example-stm32f3-disco/openocd.gdb
+++ b/satrs-example-stm32f3-disco/legacy/openocd.gdb
@@ -26,7 +26,7 @@ break main
# # 8000000 must match the core clock frequency
# # 2000000 is the frequency of the SWO pin. This was added for newer
# openocd versions like v0.12.0.
-monitor tpiu config internal itm.txt uart off 8000000 2000000
+# monitor tpiu config internal itm.txt uart off 8000000 2000000
# # OR: make the microcontroller SWO pin output compatible with UART (8N1)
# # 8000000 must match the core clock frequency
@@ -34,7 +34,7 @@ monitor tpiu config internal itm.txt uart off 8000000 2000000
# monitor tpiu config external uart off 8000000 2000000
# # enable ITM port 0
-monitor itm port 0 on
+# monitor itm port 0 on
load
diff --git a/satrs-example-stm32f3-disco/pyclient/main.py b/satrs-example-stm32f3-disco/pyclient/main.py
index d37da58..ae3099b 100755
--- a/satrs-example-stm32f3-disco/pyclient/main.py
+++ b/satrs-example-stm32f3-disco/pyclient/main.py
@@ -94,6 +94,7 @@ class SatRsConfigHook(HookBase):
def create_cmd_definition_tree() -> CmdTreeNode:
root_node = CmdTreeNode.root_node()
root_node.add_child(CmdTreeNode("ping", "Send PUS ping TC"))
+ root_node.add_child(CmdTreeNode("change_blink_freq", "Change blink frequency"))
return root_node
@@ -215,6 +216,25 @@ class TcHandler(TcHandlerBase):
if cmd_path == "/ping":
q.add_log_cmd("Sending PUS ping telecommand")
q.add_pus_tc(PusTelecommand(service=17, subservice=1))
+ if cmd_path == "/change_blink_freq":
+ self.create_change_blink_freq_command(q)
+
+ def create_change_blink_freq_command(self, q: DefaultPusQueueHelper):
+ q.add_log_cmd("Changing blink frequency")
+ while True:
+ blink_freq = int(
+ input(
+ "Please specify new blink frequency in ms. Valid Range [2..10000]: "
+ )
+ )
+ if blink_freq < 2 or blink_freq > 10000:
+ print(
+ "Invalid blink frequency. Please specify a value between 2 and 10000."
+ )
+ continue
+ break
+ app_data = struct.pack("!I", blink_freq)
+ q.add_pus_tc(PusTelecommand(service=8, subservice=1, app_data=app_data))
def main():
diff --git a/satrs-example-stm32f3-disco/src/blinky.rs b/satrs-example-stm32f3-disco/src/bin/blinky.rs
similarity index 68%
rename from satrs-example-stm32f3-disco/src/blinky.rs
rename to satrs-example-stm32f3-disco/src/bin/blinky.rs
index eefdbfe..0f96176 100644
--- a/satrs-example-stm32f3-disco/src/blinky.rs
+++ b/satrs-example-stm32f3-disco/src/bin/blinky.rs
@@ -1,17 +1,15 @@
#![no_std]
#![no_main]
+use satrs_example_stm32f3_disco as _;
-extern crate panic_itm;
-
-use cortex_m_rt::entry;
-
+use stm32f3_discovery::leds::Leds;
use stm32f3_discovery::stm32f3xx_hal::delay::Delay;
use stm32f3_discovery::stm32f3xx_hal::{pac, prelude::*};
-use stm32f3_discovery::leds::Leds;
use stm32f3_discovery::switch_hal::{OutputSwitch, ToggleableOutputSwitch};
-#[entry]
-fn main()-> ! {
+#[cortex_m_rt::entry]
+fn main() -> ! {
+ defmt::println!("STM32F3 Discovery Blinky");
let dp = pac::Peripherals::take().unwrap();
let mut rcc = dp.RCC.constrain();
let cp = cortex_m::Peripherals::take().unwrap();
@@ -30,49 +28,49 @@ fn main()-> ! {
gpioe.pe14,
gpioe.pe15,
&mut gpioe.moder,
- &mut gpioe.otyper
+ &mut gpioe.otyper,
);
let delay_ms = 200u16;
loop {
- leds.ld3.toggle().ok();
+ leds.ld3_n.toggle().ok();
delay.delay_ms(delay_ms);
- leds.ld3.toggle().ok();
+ leds.ld3_n.toggle().ok();
delay.delay_ms(delay_ms);
//explicit on/off
- leds.ld4.on().ok();
+ leds.ld4_nw.on().ok();
delay.delay_ms(delay_ms);
- leds.ld4.off().ok();
+ leds.ld4_nw.off().ok();
delay.delay_ms(delay_ms);
- leds.ld5.on().ok();
+ leds.ld5_ne.on().ok();
delay.delay_ms(delay_ms);
- leds.ld5.off().ok();
+ leds.ld5_ne.off().ok();
delay.delay_ms(delay_ms);
- leds.ld6.on().ok();
+ leds.ld6_w.on().ok();
delay.delay_ms(delay_ms);
- leds.ld6.off().ok();
- delay.delay_ms(delay_ms);
-
- leds.ld7.on().ok();
- delay.delay_ms(delay_ms);
- leds.ld7.off().ok();
- delay.delay_ms(delay_ms);
-
- leds.ld8.on().ok();
- delay.delay_ms(delay_ms);
- leds.ld8.off().ok();
- delay.delay_ms(delay_ms);
-
- leds.ld9.on().ok();
- delay.delay_ms(delay_ms);
- leds.ld9.off().ok();
+ leds.ld6_w.off().ok();
delay.delay_ms(delay_ms);
- leds.ld10.on().ok();
+ leds.ld7_e.on().ok();
delay.delay_ms(delay_ms);
- leds.ld10.off().ok();
+ leds.ld7_e.off().ok();
+ delay.delay_ms(delay_ms);
+
+ leds.ld8_sw.on().ok();
+ delay.delay_ms(delay_ms);
+ leds.ld8_sw.off().ok();
+ delay.delay_ms(delay_ms);
+
+ leds.ld9_se.on().ok();
+ delay.delay_ms(delay_ms);
+ leds.ld9_se.off().ok();
+ delay.delay_ms(delay_ms);
+
+ leds.ld10_s.on().ok();
+ delay.delay_ms(delay_ms);
+ leds.ld10_s.off().ok();
delay.delay_ms(delay_ms);
}
}
diff --git a/satrs-example-stm32f3-disco/src/lib.rs b/satrs-example-stm32f3-disco/src/lib.rs
new file mode 100644
index 0000000..284660c
--- /dev/null
+++ b/satrs-example-stm32f3-disco/src/lib.rs
@@ -0,0 +1,51 @@
+#![no_main]
+#![no_std]
+
+use cortex_m_semihosting::debug;
+
+use defmt_brtt as _; // global logger
+
+use stm32f3xx_hal as _; // memory layout
+
+use panic_probe as _;
+
+// same panicking *behavior* as `panic-probe` but doesn't print a panic message
+// this prevents the panic message being printed *twice* when `defmt::panic` is invoked
+#[defmt::panic_handler]
+fn panic() -> ! {
+ cortex_m::asm::udf()
+}
+
+/// Terminates the application and makes a semihosting-capable debug tool exit
+/// with status code 0.
+pub fn exit() -> ! {
+ loop {
+ debug::exit(debug::EXIT_SUCCESS);
+ }
+}
+
+/// Hardfault handler.
+///
+/// Terminates the application and makes a semihosting-capable debug tool exit
+/// with an error. This seems better than the default, which is to spin in a
+/// loop.
+#[cortex_m_rt::exception]
+unsafe fn HardFault(_frame: &cortex_m_rt::ExceptionFrame) -> ! {
+ loop {
+ debug::exit(debug::EXIT_FAILURE);
+ }
+}
+
+// defmt-test 0.3.0 has the limitation that this `#[tests]` attribute can only be used
+// once within a crate. the module can be in any file but there can only be at most
+// one `#[tests]` module in this library crate
+#[cfg(test)]
+#[defmt_test::tests]
+mod unit_tests {
+ use defmt::assert;
+
+ #[test]
+ fn it_works() {
+ assert!(true)
+ }
+}
diff --git a/satrs-example-stm32f3-disco/src/main.rs b/satrs-example-stm32f3-disco/src/main.rs
index 8795786..623ef5f 100644
--- a/satrs-example-stm32f3-disco/src/main.rs
+++ b/satrs-example-stm32f3-disco/src/main.rs
@@ -1,27 +1,31 @@
#![no_std]
#![no_main]
-extern crate panic_itm;
+use satrs::pus::verification::{
+ FailParams, TcStateAccepted, VerificationReportCreator, VerificationToken,
+};
+use satrs::spacepackets::ecss::tc::PusTcReader;
+use satrs::spacepackets::ecss::tm::{PusTmCreator, PusTmSecondaryHeader};
+use satrs::spacepackets::ecss::EcssEnumU16;
+use satrs::spacepackets::CcsdsPacket;
+use satrs::spacepackets::{ByteConversionError, SpHeader};
+// global logger + panicking-behavior + memory layout
+use satrs_example_stm32f3_disco as _;
use rtic::app;
use heapless::{mpmc::Q8, Vec};
#[allow(unused_imports)]
-use itm_logger::{debug, info, logger_init, warn};
-use rtic_monotonics::systick::fugit::TimerInstantU32;
+use rtic_monotonics::systick::fugit::{MillisDurationU32, TimerInstantU32};
use rtic_monotonics::systick::ExtU32;
use satrs::seq_count::SequenceCountProviderCore;
-use satrs::{
- pool::StoreError,
- pus::{EcssChannel, EcssTmSenderCore, EcssTmtcError, PusTmWrapper},
- spacepackets::{ecss::PusPacket, ecss::WritablePusPacket},
-};
+use satrs::spacepackets::{ecss::PusPacket, ecss::WritablePusPacket};
use stm32f3xx_hal::dma::dma1;
use stm32f3xx_hal::gpio::{PushPull, AF7, PA2, PA3};
use stm32f3xx_hal::pac::USART2;
use stm32f3xx_hal::serial::{Rx, RxEvent, Serial, SerialDmaRx, SerialDmaTx, Tx, TxEvent};
const UART_BAUD: u32 = 115200;
-const BLINK_FREQ_MS: u32 = 1000;
+const DEFAULT_BLINK_FREQ_MS: u32 = 1000;
const TX_HANDLER_FREQ_MS: u32 = 20;
const MIN_DELAY_BETWEEN_TX_PACKETS_MS: u32 = 5;
const MAX_TC_LEN: usize = 128;
@@ -54,7 +58,6 @@ type TcPacket = Vec;
static TM_REQUESTS: Q8 = Q8::new();
-use core::cell::RefCell;
use core::sync::atomic::{AtomicU16, Ordering};
pub struct SeqCountProviderAtomicRef {
@@ -93,53 +96,45 @@ pub struct TxIdle {
dma_channel: dma1::C7,
}
-pub struct TmSender {
- vec: Option>>,
- ctx: &'static str,
+#[derive(Debug, defmt::Format)]
+pub enum TmSendError {
+ ByteConversion(ByteConversionError),
+ Queue,
}
-impl TmSender {
- pub fn new(tm_packet: TmPacket, ctx: &'static str) -> Self {
- Self {
- vec: Some(RefCell::new(tm_packet)),
- ctx,
- }
+impl From for TmSendError {
+ fn from(value: ByteConversionError) -> Self {
+ Self::ByteConversion(value)
}
}
-impl EcssChannel for TmSender {
- fn id(&self) -> satrs::ChannelId {
- 0
+fn send_tm(tm_creator: PusTmCreator) -> Result<(), TmSendError> {
+ if tm_creator.len_written() > MAX_TM_LEN {
+ return Err(ByteConversionError::ToSliceTooSmall {
+ expected: tm_creator.len_written(),
+ found: MAX_TM_LEN,
+ }
+ .into());
}
+ let mut tm_vec = TmPacket::new();
+ tm_vec
+ .resize(tm_creator.len_written(), 0)
+ .expect("vec resize failed");
+ tm_creator.write_to_bytes(tm_vec.as_mut_slice())?;
+ defmt::info!(
+ "Sending TM[{},{}] with size {}",
+ tm_creator.service(),
+ tm_creator.subservice(),
+ tm_creator.len_written()
+ );
+ TM_REQUESTS
+ .enqueue(tm_vec)
+ .map_err(|_| TmSendError::Queue)?;
+ Ok(())
}
-impl EcssTmSenderCore for TmSender {
- fn send_tm(&self, tm: PusTmWrapper) -> Result<(), EcssTmtcError> {
- let vec = self.vec.as_ref();
- if vec.is_none() {
- panic!("send_tm should only be called once");
- }
- let vec_ref = vec.unwrap();
- let mut vec = vec_ref.borrow_mut();
- match tm {
- PusTmWrapper::InStore(addr) => return Err(EcssTmtcError::CantSendAddr(addr)),
- PusTmWrapper::Direct(tm) => {
- if tm.len_written() > MAX_TM_LEN {
- return Err(EcssTmtcError::Store(StoreError::DataTooLarge(
- tm.len_written(),
- )));
- }
- vec.resize(tm.len_written(), 0).expect("vec resize failed");
- tm.write_to_bytes(vec.as_mut_slice())?;
- info!(target: self.ctx, "Sending TM[{},{}] with size {}", tm.service(), tm.subservice(), tm.len_written());
- drop(vec);
- TM_REQUESTS
- .enqueue(vec_ref.take())
- .map_err(|_| EcssTmtcError::Store(StoreError::StoreFull(0)))?;
- }
- }
- Ok(())
- }
+fn handle_tm_send_error(error: TmSendError) {
+ defmt::warn!("sending tm failed with error {}", error);
}
pub enum UartTxState {
@@ -154,19 +149,106 @@ pub struct UartTxShared {
state: UartTxState,
}
+pub struct RequestWithToken {
+ token: VerificationToken,
+ request: Request,
+}
+
+#[derive(Debug, defmt::Format)]
+pub enum Request {
+ Ping,
+ ChangeBlinkFrequency(u32),
+}
+
+#[derive(Debug, defmt::Format)]
+pub enum RequestError {
+ InvalidApid = 1,
+ InvalidService = 2,
+ InvalidSubservice = 3,
+ NotEnoughAppData = 4,
+}
+
+pub fn convert_pus_tc_to_request(
+ tc: &PusTcReader,
+ verif_reporter: &mut VerificationReportCreator,
+ src_data_buf: &mut [u8],
+ timestamp: &[u8],
+) -> Result {
+ defmt::info!(
+ "Found PUS TC [{},{}] with length {}",
+ tc.service(),
+ tc.subservice(),
+ tc.len_packed()
+ );
+
+ let token = verif_reporter.add_tc(tc);
+ if tc.apid() != PUS_APID {
+ defmt::warn!("Received tc with unknown APID {}", tc.apid());
+ let result = send_tm(
+ verif_reporter
+ .acceptance_failure(
+ src_data_buf,
+ token,
+ SEQ_COUNT_PROVIDER.get_and_increment(),
+ 0,
+ FailParams::new(timestamp, &EcssEnumU16::new(0), &[]),
+ )
+ .unwrap(),
+ );
+ if let Err(e) = result {
+ handle_tm_send_error(e);
+ }
+ return Err(RequestError::InvalidApid);
+ }
+ let (tm_creator, accepted_token) = verif_reporter
+ .acceptance_success(
+ src_data_buf,
+ token,
+ SEQ_COUNT_PROVIDER.get_and_increment(),
+ 0,
+ timestamp,
+ )
+ .unwrap();
+
+ if let Err(e) = send_tm(tm_creator) {
+ handle_tm_send_error(e);
+ }
+
+ if tc.service() == 17 && tc.subservice() == 1 {
+ if tc.subservice() == 1 {
+ return Ok(RequestWithToken {
+ request: Request::Ping,
+ token: accepted_token,
+ });
+ } else {
+ return Err(RequestError::InvalidSubservice);
+ }
+ } else if tc.service() == 8 {
+ if tc.subservice() == 1 {
+ if tc.user_data().len() < 4 {
+ return Err(RequestError::NotEnoughAppData);
+ }
+ let new_freq_ms = u32::from_be_bytes(tc.user_data()[0..4].try_into().unwrap());
+ return Ok(RequestWithToken {
+ request: Request::ChangeBlinkFrequency(new_freq_ms),
+ token: accepted_token,
+ });
+ } else {
+ return Err(RequestError::InvalidSubservice);
+ }
+ } else {
+ return Err(RequestError::InvalidService);
+ }
+}
+
#[app(device = stm32f3xx_hal::pac, peripherals = true)]
mod app {
use super::*;
use core::slice::Iter;
- use cortex_m::iprintln;
use rtic_monotonics::systick::Systick;
use rtic_monotonics::Monotonic;
- use satrs::pus::verification::FailParams;
- use satrs::pus::verification::VerificationReporterCore;
- use satrs::spacepackets::{
- ecss::tc::PusTcReader, ecss::tm::PusTmCreator, ecss::tm::PusTmSecondaryHeader,
- ecss::EcssEnumU16, time::cds::P_FIELD_BASE, CcsdsPacket, SpHeader,
- };
+ use satrs::pus::verification::{TcStateStarted, VerificationReportCreator};
+ use satrs::spacepackets::{ecss::tc::PusTcReader, time::cds::P_FIELD_BASE};
#[allow(unused_imports)]
use stm32f3_discovery::leds::Direction;
use stm32f3_discovery::leds::Leds;
@@ -179,27 +261,27 @@ mod app {
#[shared]
struct Shared {
+ blink_freq: MillisDurationU32,
tx_shared: UartTxShared,
rx_transfer: Option,
}
#[local]
struct Local {
+ verif_reporter: VerificationReportCreator,
leds: Leds,
last_dir: Direction,
- verif_reporter: VerificationReporterCore,
curr_dir: Iter<'static, Direction>,
}
#[init]
- fn init(mut cx: init::Context) -> (Shared, Local) {
+ fn init(cx: init::Context) -> (Shared, Local) {
let mut rcc = cx.device.RCC.constrain();
// Initialize the systick interrupt & obtain the token to prove that we did
let systick_mono_token = rtic_monotonics::create_systick_token!();
Systick::start(cx.core.SYST, 8_000_000, systick_mono_token);
- logger_init();
let mut flash = cx.device.FLASH.constrain();
let clocks = rcc
.cfgr
@@ -211,15 +293,9 @@ mod app {
// Set up monotonic timer.
//let mono_timer = MonoTimer::new(cx.core.DWT, clocks, &mut cx.core.DCB);
- // setup ITM output
- iprintln!(
- &mut cx.core.ITM.stim[0],
- "Starting sat-rs demo application for the STM32F3-Discovery"
- );
+ defmt::info!("Starting sat-rs demo application for the STM32F3-Discovery");
let mut gpioe = cx.device.GPIOE.split(&mut rcc.ahb);
- let verif_reporter = VerificationReporterCore::new(PUS_APID).unwrap();
-
let leds = Leds::new(
gpioe.pe8,
gpioe.pe9,
@@ -265,11 +341,15 @@ mod app {
// For some reason, this is also immediately triggered..
tx_serial.clear_event(TxEvent::TransmissionComplete);
let rx_transfer = rx_serial.read_exact(unsafe { DMA_RX_BUF.as_mut_slice() }, dma1.ch6);
- info!(target: "init", "Spawning tasks");
+ defmt::info!("Spawning tasks");
blink::spawn().unwrap();
serial_tx_handler::spawn().unwrap();
+
+ let verif_reporter = VerificationReportCreator::new(PUS_APID).unwrap();
+
(
Shared {
+ blink_freq: MillisDurationU32::from_ticks(DEFAULT_BLINK_FREQ_MS),
tx_shared: UartTxShared {
last_completed: None,
state: UartTxState::Idle(Some(TxIdle {
@@ -280,17 +360,16 @@ mod app {
rx_transfer: Some(rx_transfer),
},
Local {
- //timer: mono_timer,
+ verif_reporter,
leds,
last_dir: Direction::North,
curr_dir: Direction::iter(),
- verif_reporter,
},
)
}
- #[task(local = [leds, curr_dir, last_dir])]
- async fn blink(cx: blink::Context) {
+ #[task(local = [leds, curr_dir, last_dir], shared=[blink_freq])]
+ async fn blink(mut cx: blink::Context) {
let blink::LocalResources {
leds,
curr_dir,
@@ -314,7 +393,8 @@ mod app {
toggle_leds(curr_dir.next().unwrap());
}
}
- Systick::delay(BLINK_FREQ_MS.millis()).await;
+ let current_blink_freq = cx.shared.blink_freq.lock(|current| *current);
+ Systick::delay(current_blink_freq).await;
}
}
@@ -389,20 +469,19 @@ mod app {
#[task(
local = [
- stamp_buf: [u8; 7] = [0; 7],
+ verif_reporter,
decode_buf: [u8; MAX_TC_LEN] = [0; MAX_TC_LEN],
src_data_buf: [u8; MAX_TM_LEN] = [0; MAX_TM_LEN],
- verif_reporter
+ timestamp: [u8; 7] = [0; 7],
],
+ shared = [blink_freq]
)]
async fn serial_rx_handler(
- cx: serial_rx_handler::Context,
+ mut cx: serial_rx_handler::Context,
received_packet: Vec,
) {
- info!("running rx handler");
- let tgt: &'static str = "serial_rx_handler";
- cx.local.stamp_buf[0] = P_FIELD_BASE;
- info!(target: tgt, "Received packet with {} bytes", received_packet.len());
+ cx.local.timestamp[0] = P_FIELD_BASE;
+ defmt::info!("Received packet with {} bytes", received_packet.len());
let decode_buf = cx.local.decode_buf;
let packet = received_packet.as_slice();
let mut start_idx = None;
@@ -413,142 +492,124 @@ mod app {
}
}
if start_idx.is_none() {
- warn!(
- target: tgt,
- "decoding error, can only process cobs encoded frames, data is all 0"
- );
+ defmt::warn!("decoding error, can only process cobs encoded frames, data is all 0");
return;
}
let start_idx = start_idx.unwrap();
match cobs::decode(&received_packet.as_slice()[start_idx..], decode_buf) {
Ok(len) => {
- info!(target: tgt, "Decoded packet length: {}", len);
+ defmt::info!("Decoded packet length: {}", len);
let pus_tc = PusTcReader::new(decode_buf);
- let verif_reporter = cx.local.verif_reporter;
match pus_tc {
- Ok((tc, tc_len)) => handle_tc(
- tc,
- tc_len,
- verif_reporter,
- cx.local.src_data_buf,
- cx.local.stamp_buf,
- tgt,
- ),
+ Ok((tc, _tc_len)) => {
+ match convert_pus_tc_to_request(
+ &tc,
+ cx.local.verif_reporter,
+ cx.local.src_data_buf,
+ cx.local.timestamp,
+ ) {
+ Ok(request_with_token) => {
+ let started_token = handle_start_verification(
+ request_with_token.token,
+ cx.local.verif_reporter,
+ cx.local.src_data_buf,
+ cx.local.timestamp,
+ );
+
+ match request_with_token.request {
+ Request::Ping => {
+ handle_ping_request(cx.local.timestamp);
+ }
+ Request::ChangeBlinkFrequency(new_freq_ms) => {
+ defmt::info!("Received blink frequency change request with new frequncy {}", new_freq_ms);
+ cx.shared.blink_freq.lock(|blink_freq| {
+ *blink_freq =
+ MillisDurationU32::from_ticks(new_freq_ms);
+ });
+ }
+ }
+ handle_completion_verification(
+ started_token,
+ cx.local.verif_reporter,
+ cx.local.src_data_buf,
+ cx.local.timestamp,
+ );
+ }
+ Err(e) => {
+ // TODO: Error handling: Send verification failure based on request error.
+ defmt::warn!("request error {}", e);
+ }
+ }
+ }
Err(e) => {
- warn!(target: tgt, "Error unpacking PUS TC: {}", e);
+ defmt::warn!("Error unpacking PUS TC: {}", e);
}
}
}
Err(_) => {
- warn!(
- target: tgt,
- "decoding error, can only process cobs encoded frames"
- )
+ defmt::warn!("decoding error, can only process cobs encoded frames")
}
}
}
- fn handle_tc(
- tc: PusTcReader,
- tc_len: usize,
- verif_reporter: &mut VerificationReporterCore,
- src_data_buf: &mut [u8; MAX_TM_LEN],
- stamp_buf: &[u8; 7],
- tgt: &'static str,
- ) {
- info!(
- target: tgt,
- "Found PUS TC [{},{}] with length {}",
- tc.service(),
- tc.subservice(),
- tc_len
- );
-
- let token = verif_reporter.add_tc(&tc);
- if tc.apid() != PUS_APID {
- warn!(target: tgt, "Received tc with unknown APID {}", tc.apid());
- let sendable = verif_reporter
- .acceptance_failure(
- src_data_buf,
- token,
- SEQ_COUNT_PROVIDER.get(),
- 0,
- FailParams::new(stamp_buf, &EcssEnumU16::new(0), &[]),
- )
- .unwrap();
- let sender = TmSender::new(TmPacket::new(), tgt);
- if let Err(e) = verif_reporter.send_acceptance_failure(sendable, &sender) {
- warn!(target: tgt, "Sending acceptance failure failed: {:?}", e.0);
- };
+ fn handle_ping_request(timestamp: &[u8]) {
+ defmt::info!("Received PUS ping telecommand, sending ping reply TM[17,2]");
+ let sp_header =
+ SpHeader::new_for_unseg_tc(PUS_APID, SEQ_COUNT_PROVIDER.get_and_increment(), 0);
+ let sec_header = PusTmSecondaryHeader::new_simple(17, 2, timestamp);
+ let ping_reply = PusTmCreator::new(sp_header, sec_header, &[], true);
+ let mut tm_packet = TmPacket::new();
+ tm_packet
+ .resize(ping_reply.len_written(), 0)
+ .expect("vec resize failed");
+ ping_reply.write_to_bytes(&mut tm_packet).unwrap();
+ if TM_REQUESTS.enqueue(tm_packet).is_err() {
+ defmt::warn!("TC queue full");
return;
}
- let sendable = verif_reporter
- .acceptance_success(src_data_buf, token, SEQ_COUNT_PROVIDER.get(), 0, stamp_buf)
+ }
+
+ fn handle_start_verification(
+ accepted_token: VerificationToken,
+ verif_reporter: &mut VerificationReportCreator,
+ src_data_buf: &mut [u8],
+ timestamp: &[u8],
+ ) -> VerificationToken {
+ let (tm_creator, started_token) = verif_reporter
+ .start_success(
+ src_data_buf,
+ accepted_token,
+ SEQ_COUNT_PROVIDER.get(),
+ 0,
+ ×tamp,
+ )
.unwrap();
+ let result = send_tm(tm_creator);
+ if let Err(e) = result {
+ handle_tm_send_error(e);
+ }
+ started_token
+ }
- let sender = TmSender::new(TmPacket::new(), tgt);
- let accepted_token = match verif_reporter.send_acceptance_success(sendable, &sender) {
- Ok(token) => token,
- Err(e) => {
- warn!(target: "serial_rx_handler", "Sending acceptance success failed: {:?}", e.0);
- return;
- }
- };
-
- if tc.service() == 17 {
- if tc.subservice() == 1 {
- let sendable = verif_reporter
- .start_success(
- src_data_buf,
- accepted_token,
- SEQ_COUNT_PROVIDER.get(),
- 0,
- stamp_buf,
- )
- .unwrap();
- // let mem_block = poolmod::TM::alloc().unwrap().init([0u8; MAX_TM_LEN]);
- let sender = TmSender::new(TmPacket::new(), tgt);
- let started_token = match verif_reporter.send_start_success(sendable, &sender) {
- Ok(token) => token,
- Err(e) => {
- warn!(target: tgt, "Sending acceptance success failed: {:?}", e.0);
- return;
- }
- };
- info!(
- target: tgt,
- "Received PUS ping telecommand, sending ping reply TM[17,2]"
- );
- let mut sp_header =
- SpHeader::tc_unseg(PUS_APID, SEQ_COUNT_PROVIDER.get(), 0).unwrap();
- let sec_header = PusTmSecondaryHeader::new_simple(17, 2, stamp_buf);
- let ping_reply = PusTmCreator::new(&mut sp_header, sec_header, &[], true);
- let mut tm_packet = TmPacket::new();
- tm_packet
- .resize(ping_reply.len_written(), 0)
- .expect("vec resize failed");
- ping_reply.write_to_bytes(&mut tm_packet).unwrap();
- if TM_REQUESTS.enqueue(tm_packet).is_err() {
- warn!(target: tgt, "TC queue full");
- return;
- }
- SEQ_COUNT_PROVIDER.increment();
- let sendable = verif_reporter
- .completion_success(
- src_data_buf,
- started_token,
- SEQ_COUNT_PROVIDER.get(),
- 0,
- stamp_buf,
- )
- .unwrap();
- let sender = TmSender::new(TmPacket::new(), tgt);
- if let Err(e) = verif_reporter.send_step_or_completion_success(sendable, &sender) {
- warn!(target: tgt, "Sending completion success failed: {:?}", e.0);
- }
- } else {
- // TODO: Invalid subservice
- }
+ fn handle_completion_verification(
+ started_token: VerificationToken,
+ verif_reporter: &mut VerificationReportCreator,
+ src_data_buf: &mut [u8],
+ timestamp: &[u8],
+ ) {
+ let result = send_tm(
+ verif_reporter
+ .completion_success(
+ src_data_buf,
+ started_token,
+ SEQ_COUNT_PROVIDER.get(),
+ 0,
+ timestamp,
+ )
+ .unwrap(),
+ );
+ if let Err(e) = result {
+ handle_tm_send_error(e);
}
}
@@ -573,7 +634,7 @@ mod app {
serial_rx_handler::spawn(tc_packet).expect("spawning rx handler task failed");
// If this happens, there is a high chance that the maximum packet length was
// exceeded. Circular mode is not used here, so data might be missed.
- warn!(
+ defmt::warn!(
"rx transfer with maximum length {}, might miss data",
TC_BUF_LEN
);
@@ -615,7 +676,6 @@ mod app {
.expect("vec resize failed");
tc_packet[0..rx_len as usize].copy_from_slice(&buf[0..rx_len as usize]);
rx.clear_event(RxEvent::Idle);
- info!("spawning rx task");
serial_rx_handler::spawn(tc_packet).expect("spawning rx handler failed");
*rx_transfer = Some(rx.read_exact(buf, ch));
}
diff --git a/satrs-example-stm32f3-disco/vscode/extensions.json b/satrs-example-stm32f3-disco/vscode/extensions.json
index 57b3fbb..b310f9b 100644
--- a/satrs-example-stm32f3-disco/vscode/extensions.json
+++ b/satrs-example-stm32f3-disco/vscode/extensions.json
@@ -5,7 +5,7 @@
// List of extensions which should be recommended for users of this workspace.
"recommendations": [
"rust-lang.rust",
- "marus25.cortex-debug",
+ "probe-rs.probe-rs-debugger"
],
// List of extensions recommended by VS Code that should not be recommended for users of this workspace.
"unwantedRecommendations": []
diff --git a/satrs-example-stm32f3-disco/vscode/launch.json b/satrs-example-stm32f3-disco/vscode/launch.json
index f9e65f2..f982d67 100644
--- a/satrs-example-stm32f3-disco/vscode/launch.json
+++ b/satrs-example-stm32f3-disco/vscode/launch.json
@@ -1,66 +1,22 @@
{
- /*
- * Requires the Rust Language Server (RLS) and Cortex-Debug extensions
- * https://marketplace.visualstudio.com/items?itemName=rust-lang.rust
- * https://marketplace.visualstudio.com/items?itemName=marus25.cortex-debug
- */
- "version": "0.2.0",
- "configurations": [
+ "version": "0.2.0",
+ "configurations": [
+ {
+ "preLaunchTask": "${defaultBuildTask}",
+ "type": "probe-rs-debug",
+ "request": "launch",
+ "name": "probe-rs Debugging ",
+ "flashingConfig": {
+ "flashingEnabled": true
+ },
+ "chip": "STM32F303VCTx",
+ "coreConfigs": [
{
- /* Launches debug session for currently open example */
- "type": "cortex-debug",
- "request": "launch",
- "name": "Debug",
- "servertype": "openocd",
- "cwd": "${workspaceRoot}",
- "preLaunchTask": "cargo build",
- "runToEntryPoint": "true",
- "executable": "./target/thumbv7em-none-eabihf/debug/satrs-example-stm32f3-disco",
- "preLaunchCommands": ["break rust_begin_unwind"],
- "device": "STM32F303VCT6",
- "configFiles": [
- "${workspaceRoot}/.vscode/openocd-helpers.tcl",
- "interface/stlink.cfg",
- "target/stm32f3x.cfg"
- ],
- "svdFile": "${env:HOME}/.svd/STM32F303.svd",
- "swoConfig": {
- "enabled": true,
- "cpuFrequency": 8000000,
- "swoFrequency": 2000000,
- "source": "probe",
- "decoders": [
- { "type": "console", "label": "ITM", "port": 0 }
- ]
- }
- },
- {
- /* Launches debug session for currently open example */
- "type": "cortex-debug",
- "request": "launch",
- "name": "Release",
- "servertype": "openocd",
- "cwd": "${workspaceRoot}",
- "preLaunchTask": "cargo build",
- "runToEntryPoint": "true",
- "executable": "./target/thumbv7em-none-eabihf/release/satrs-example-stm32f3-disco",
- "preLaunchCommands": ["break rust_begin_unwind"],
- "device": "STM32F303VCT6",
- "configFiles": [
- "${workspaceRoot}/.vscode/openocd-helpers.tcl",
- "interface/stlink.cfg",
- "target/stm32f3x.cfg"
- ],
- "svdFile": "${env:HOME}/.svd/STM32F303.svd",
- "swoConfig": {
- "enabled": true,
- "cpuFrequency": 8000000,
- "swoFrequency": 2000000,
- "source": "probe",
- "decoders": [
- { "type": "console", "label": "ITM", "port": 0 }
- ]
- }
+ "programBinary": "${workspaceFolder}/target/thumbv7em-none-eabihf/debug/satrs-example-stm32f3-disco",
+ "rttEnabled": true,
+ "svdFile": "STM32F303.svd"
}
- ]
-}
\ No newline at end of file
+ ]
+ }
+ ]
+}
diff --git a/satrs-example/Cargo.toml b/satrs-example/Cargo.toml
index 27ffee9..b22904b 100644
--- a/satrs-example/Cargo.toml
+++ b/satrs-example/Cargo.toml
@@ -17,16 +17,23 @@ zerocopy = "0.6"
csv = "1"
num_enum = "0.7"
thiserror = "1"
+lazy_static = "1"
+strum = { version = "0.26", features = ["derive"] }
derive-new = "0.5"
+serde = { version = "1", features = ["derive"] }
+serde_json = "1"
[dependencies.satrs]
-# version = "0.2.0-rc.0"
path = "../satrs"
+features = ["test_util"]
[dependencies.satrs-mib]
version = "0.1.1"
-# path = "../satrs-mib"
+path = "../satrs-mib"
[features]
dyn_tmtc = []
default = ["dyn_tmtc"]
+
+[dev-dependencies]
+env_logger = "0.11"
diff --git a/satrs-example/satrs-tmtc/common.py b/satrs-example/satrs-tmtc/common.py
index 8f57e54..6f56604 100644
--- a/satrs-example/satrs-tmtc/common.py
+++ b/satrs-example/satrs-tmtc/common.py
@@ -4,11 +4,12 @@ import dataclasses
import enum
import struct
-from spacepackets.ecss.tc import PacketId, PacketType
-EXAMPLE_PUS_APID = 0x02
-EXAMPLE_PUS_PACKET_ID_TM = PacketId(PacketType.TM, True, EXAMPLE_PUS_APID)
-TM_PACKET_IDS = [EXAMPLE_PUS_PACKET_ID_TM]
+class Apid(enum.IntEnum):
+ SCHED = 1
+ GENERIC_PUS = 2
+ ACS = 3
+ CFDP = 4
class EventSeverity(enum.IntEnum):
@@ -36,8 +37,8 @@ class EventU32:
)
-class RequestTargetId(enum.IntEnum):
- ACS = 1
+class AcsId(enum.IntEnum):
+ MGM_0 = 0
class AcsHkIds(enum.IntEnum):
diff --git a/satrs-example/satrs-tmtc/main.py b/satrs-example/satrs-tmtc/main.py
index 66a41e4..a3e0caf 100755
--- a/satrs-example/satrs-tmtc/main.py
+++ b/satrs-example/satrs-tmtc/main.py
@@ -3,10 +3,11 @@
import logging
import sys
import time
-from typing import Optional
+from typing import Any, Optional
from prompt_toolkit.history import History
from prompt_toolkit.history import FileHistory
+from spacepackets.ccsds import PacketId, PacketType
import tmtccmd
from spacepackets.ecss import PusTelemetry, PusVerificator
from spacepackets.ecss.pus_17_test import Service17Tm
@@ -16,7 +17,7 @@ from spacepackets.ccsds.time import CdsShortTimestamp
from tmtccmd import TcHandlerBase, ProcedureParamsWrapper
from tmtccmd.core.base import BackendRequest
from tmtccmd.pus import VerificationWrapper
-from tmtccmd.tmtc import CcsdsTmHandler, SpecificApidHandlerBase
+from tmtccmd.tmtc import CcsdsTmHandler, GenericApidHandlerBase
from tmtccmd.com import ComInterface
from tmtccmd.config import (
CmdTreeNode,
@@ -46,7 +47,7 @@ from tmtccmd.util.obj_id import ObjectIdDictT
import pus_tc
-from common import EXAMPLE_PUS_APID, TM_PACKET_IDS, EventU32
+from common import Apid, EventU32
_LOGGER = logging.getLogger()
@@ -62,10 +63,13 @@ class SatRsConfigHook(HookBase):
)
assert self.cfg_path is not None
+ packet_id_list = []
+ for apid in Apid:
+ packet_id_list.append(PacketId(PacketType.TM, True, apid))
cfg = create_com_interface_cfg_default(
com_if_key=com_if_key,
json_cfg_path=self.cfg_path,
- space_packet_ids=TM_PACKET_IDS,
+ space_packet_ids=packet_id_list,
)
assert cfg is not None
return create_com_interface_default(cfg)
@@ -85,19 +89,19 @@ class SatRsConfigHook(HookBase):
return get_core_object_ids()
-class PusHandler(SpecificApidHandlerBase):
+class PusHandler(GenericApidHandlerBase):
def __init__(
self,
file_logger: logging.Logger,
verif_wrapper: VerificationWrapper,
raw_logger: RawTmtcTimedLogWrapper,
):
- super().__init__(EXAMPLE_PUS_APID, None)
+ super().__init__(None)
self.file_logger = file_logger
self.raw_logger = raw_logger
self.verif_wrapper = verif_wrapper
- def handle_tm(self, packet: bytes, _user_args: any):
+ def handle_tm(self, apid: int, packet: bytes, _user_args: Any):
try:
pus_tm = PusTelemetry.unpack(packet, time_reader=CdsShortTimestamp.empty())
except ValueError as e:
@@ -177,7 +181,7 @@ class TcHandler(TcHandlerBase):
tc_sched_timestamp_len=CdsShortTimestamp.TIMESTAMP_SIZE,
seq_cnt_provider=seq_count_provider,
pus_verificator=self.verif_wrapper.pus_verificator,
- default_pus_apid=EXAMPLE_PUS_APID,
+ default_pus_apid=None,
)
def send_cb(self, send_params: SendCbParams):
@@ -221,7 +225,6 @@ def main():
post_args_wrapper.set_params_without_prompts(proc_wrapper)
else:
post_args_wrapper.set_params_with_prompts(proc_wrapper)
- params.apid = EXAMPLE_PUS_APID
setup_args = SetupWrapper(
hook_obj=hook_obj, setup_params=params, proc_param_wrapper=proc_wrapper
)
@@ -233,8 +236,9 @@ def main():
verification_wrapper = VerificationWrapper(verificator, _LOGGER, file_logger)
# Create primary TM handler and add it to the CCSDS Packet Handler
tm_handler = PusHandler(file_logger, verification_wrapper, raw_logger)
- ccsds_handler = CcsdsTmHandler(generic_handler=None)
- ccsds_handler.add_apid_handler(tm_handler)
+ ccsds_handler = CcsdsTmHandler(generic_handler=tm_handler)
+ # TODO: We could add the CFDP handler for the CFDP APID at a later stage.
+ # ccsds_handler.add_apid_handler(tm_handler)
# Create TC handler
seq_count_provider = PusFileSeqCountProvider()
diff --git a/satrs-example/satrs-tmtc/pus_tc.py b/satrs-example/satrs-tmtc/pus_tc.py
index f73b755..b0febdc 100644
--- a/satrs-example/satrs-tmtc/pus_tc.py
+++ b/satrs-example/satrs-tmtc/pus_tc.py
@@ -1,27 +1,58 @@
import datetime
+import struct
import logging
from spacepackets.ccsds import CdsShortTimestamp
from spacepackets.ecss import PusTelecommand
from tmtccmd.config import CmdTreeNode
+from tmtccmd.pus.tc.s200_fsfw_mode import Mode
from tmtccmd.tmtc import DefaultPusQueueHelper
from tmtccmd.pus.s11_tc_sched import create_time_tagged_cmd
-from tmtccmd.pus.tc.s3_fsfw_hk import create_request_one_hk_command
+from tmtccmd.pus.s200_fsfw_mode import Subservice as ModeSubservice
-from common import (
- EXAMPLE_PUS_APID,
- make_addressable_id,
- RequestTargetId,
- AcsHkIds,
-)
+from common import AcsId, Apid
_LOGGER = logging.getLogger(__name__)
+def create_set_mode_cmd(
+ apid: int, unique_id: int, mode: int, submode: int
+) -> PusTelecommand:
+ app_data = bytearray()
+ app_data.extend(struct.pack("!I", unique_id))
+ app_data.extend(struct.pack("!I", mode))
+ app_data.extend(struct.pack("!H", submode))
+ return PusTelecommand(
+ service=200,
+ subservice=ModeSubservice.TC_MODE_COMMAND,
+ apid=apid,
+ app_data=app_data,
+ )
+
+
def create_cmd_definition_tree() -> CmdTreeNode:
root_node = CmdTreeNode.root_node()
+ hk_node = CmdTreeNode("hk", "Housekeeping Node", hide_children_for_print=True)
+ hk_node.add_child(CmdTreeNode("one_shot_hk", "Request One Shot HK set"))
+ hk_node.add_child(
+ CmdTreeNode("enable", "Enable periodic housekeeping data generation")
+ )
+ hk_node.add_child(
+ CmdTreeNode("disable", "Disable periodic housekeeping data generation")
+ )
+
+ mode_node = CmdTreeNode("mode", "Mode Node", hide_children_for_print=True)
+ set_mode_node = CmdTreeNode(
+ "set_mode", "Set Node", hide_children_which_are_leaves=True
+ )
+ set_mode_node.add_child(CmdTreeNode("off", "Set OFF Mode"))
+ set_mode_node.add_child(CmdTreeNode("on", "Set ON Mode"))
+ set_mode_node.add_child(CmdTreeNode("normal", "Set NORMAL Mode"))
+ mode_node.add_child(set_mode_node)
+ mode_node.add_child(CmdTreeNode("read_mode", "Read Mode"))
+
test_node = CmdTreeNode("test", "Test Node")
test_node.add_child(CmdTreeNode("ping", "Send PUS ping TC"))
test_node.add_child(CmdTreeNode("trigger_event", "Send PUS test to trigger event"))
@@ -37,7 +68,9 @@ def create_cmd_definition_tree() -> CmdTreeNode:
acs_node = CmdTreeNode("acs", "ACS Subsystem Node")
mgm_node = CmdTreeNode("mgms", "MGM devices node")
- mgm_node.add_child(CmdTreeNode("one_shot_hk", "Request one shot HK"))
+ mgm_node.add_child(mode_node)
+ mgm_node.add_child(hk_node)
+
acs_node.add_child(mgm_node)
root_node.add_child(acs_node)
@@ -54,10 +87,14 @@ def pack_pus_telecommands(q: DefaultPusQueueHelper, cmd_path: str):
assert len(cmd_path_list) >= 2
if cmd_path_list[1] == "ping":
q.add_log_cmd("Sending PUS ping telecommand")
- return q.add_pus_tc(PusTelecommand(service=17, subservice=1))
+ return q.add_pus_tc(
+ PusTelecommand(apid=Apid.GENERIC_PUS, service=17, subservice=1)
+ )
elif cmd_path_list[1] == "trigger_event":
q.add_log_cmd("Triggering test event")
- return q.add_pus_tc(PusTelecommand(service=17, subservice=128))
+ return q.add_pus_tc(
+ PusTelecommand(apid=Apid.GENERIC_PUS, service=17, subservice=128)
+ )
if cmd_path_list[0] == "scheduler":
assert len(cmd_path_list) >= 2
if cmd_path_list[1] == "schedule_ping_10_secs_ahead":
@@ -69,17 +106,38 @@ def pack_pus_telecommands(q: DefaultPusQueueHelper, cmd_path: str):
create_time_tagged_cmd(
time_stamp,
PusTelecommand(service=17, subservice=1),
- apid=EXAMPLE_PUS_APID,
+ apid=Apid.SCHED,
)
)
if cmd_path_list[0] == "acs":
assert len(cmd_path_list) >= 2
- if cmd_path_list[1] == "mgm":
+ if cmd_path_list[1] == "mgms":
assert len(cmd_path_list) >= 3
- if cmd_path_list[2] == "one_shot_hk":
- q.add_log_cmd("Sending HK one shot request")
- q.add_pus_tc(
- create_request_one_hk_command(
- make_addressable_id(RequestTargetId.ACS, AcsHkIds.MGM_SET)
+ if cmd_path_list[2] == "hk":
+ if cmd_path_list[3] == "one_shot_hk":
+ q.add_log_cmd("Sending HK one shot request")
+ # TODO: Fix
+ # q.add_pus_tc(
+ # create_request_one_hk_command(
+ # make_addressable_id(Apid.ACS, AcsId.MGM_SET)
+ # )
+ # )
+ if cmd_path_list[2] == "mode":
+ if cmd_path_list[3] == "set_mode":
+ handle_set_mode_cmd(
+ q, "MGM 0", cmd_path_list[4], Apid.ACS, AcsId.MGM_0
)
- )
+
+
+def handle_set_mode_cmd(
+ q: DefaultPusQueueHelper, target_str: str, mode_str: str, apid: int, unique_id: int
+):
+ if mode_str == "off":
+ q.add_log_cmd(f"Sending Mode OFF to {target_str}")
+ q.add_pus_tc(create_set_mode_cmd(apid, unique_id, Mode.OFF, 0))
+ elif mode_str == "on":
+ q.add_log_cmd(f"Sending Mode ON to {target_str}")
+ q.add_pus_tc(create_set_mode_cmd(apid, unique_id, Mode.ON, 0))
+ elif mode_str == "normal":
+ q.add_log_cmd(f"Sending Mode NORMAL to {target_str}")
+ q.add_pus_tc(create_set_mode_cmd(apid, unique_id, Mode.NORMAL, 0))
diff --git a/satrs-example/src/acs.rs b/satrs-example/src/acs.rs
deleted file mode 100644
index 4fbea90..0000000
--- a/satrs-example/src/acs.rs
+++ /dev/null
@@ -1,118 +0,0 @@
-use std::sync::mpsc::{self, TryRecvError};
-
-use log::{info, warn};
-use satrs::pus::verification::VerificationReportingProvider;
-use satrs::pus::{EcssTmSender, PusTmWrapper};
-use satrs::request::TargetAndApidId;
-use satrs::spacepackets::ecss::hk::Subservice as HkSubservice;
-use satrs::{
- hk::HkRequest,
- spacepackets::{
- ecss::tm::{PusTmCreator, PusTmSecondaryHeader},
- time::cds::{DaysLen16Bits, TimeProvider},
- SequenceFlags, SpHeader,
- },
-};
-use satrs_example::config::{RequestTargetId, PUS_APID};
-
-use crate::{
- hk::{AcsHkIds, HkUniqueId},
- requests::{Request, RequestWithToken},
- update_time,
-};
-
-pub struct AcsTask {
- timestamp: [u8; 7],
- time_provider: TimeProvider,
- verif_reporter: VerificationReporter,
- tm_sender: Box,
- request_rx: mpsc::Receiver,
-}
-
-impl AcsTask {
- pub fn new(
- tm_sender: impl EcssTmSender,
- request_rx: mpsc::Receiver,
- verif_reporter: VerificationReporter,
- ) -> Self {
- Self {
- timestamp: [0; 7],
- time_provider: TimeProvider::new_with_u16_days(0, 0),
- verif_reporter,
- tm_sender: Box::new(tm_sender),
- request_rx,
- }
- }
-
- fn handle_hk_request(&mut self, target_id: u32, unique_id: u32) {
- assert_eq!(target_id, RequestTargetId::AcsSubsystem as u32);
- if unique_id == AcsHkIds::TestMgmSet as u32 {
- let mut sp_header = SpHeader::tm(PUS_APID, SequenceFlags::Unsegmented, 0, 0).unwrap();
- let sec_header = PusTmSecondaryHeader::new_simple(
- 3,
- HkSubservice::TmHkPacket as u8,
- &self.timestamp,
- );
- let mut buf: [u8; 8] = [0; 8];
- let hk_id = HkUniqueId::new(target_id, unique_id);
- hk_id.write_to_be_bytes(&mut buf).unwrap();
- let pus_tm = PusTmCreator::new(&mut sp_header, sec_header, &buf, true);
- self.tm_sender
- .send_tm(PusTmWrapper::Direct(pus_tm))
- .expect("Sending HK TM failed");
- }
- // TODO: Verification failure for invalid unique IDs.
- }
-
- pub fn try_reading_one_request(&mut self) -> bool {
- match self.request_rx.try_recv() {
- Ok(request) => {
- info!(
- "ACS thread: Received HK request {:?}",
- request.targeted_request
- );
- let target_and_apid_id = TargetAndApidId::from(request.targeted_request.target_id);
- match request.targeted_request.request {
- Request::Hk(hk_req) => match hk_req {
- HkRequest::OneShot(unique_id) => {
- self.handle_hk_request(target_and_apid_id.target(), unique_id)
- }
- HkRequest::Enable(_) => {}
- HkRequest::Disable(_) => {}
- HkRequest::ModifyCollectionInterval(_, _) => {}
- },
- Request::Mode(_mode_req) => {
- warn!("mode request handling not implemented yet")
- }
- Request::Action(_action_req) => {
- warn!("action request handling not implemented yet")
- }
- }
- let started_token = self
- .verif_reporter
- .start_success(request.token, &self.timestamp)
- .expect("Sending start success failed");
- self.verif_reporter
- .completion_success(started_token, &self.timestamp)
- .expect("Sending completion success failed");
- true
- }
- Err(e) => match e {
- TryRecvError::Empty => false,
- TryRecvError::Disconnected => {
- warn!("ACS thread: Message Queue TX disconnected!");
- false
- }
- },
- }
- }
-
- pub fn periodic_operation(&mut self) {
- update_time(&mut self.time_provider, &mut self.timestamp);
- loop {
- if !self.try_reading_one_request() {
- break;
- }
- }
- }
-}
diff --git a/satrs-example/src/acs/mgm.rs b/satrs-example/src/acs/mgm.rs
new file mode 100644
index 0000000..1cb7eee
--- /dev/null
+++ b/satrs-example/src/acs/mgm.rs
@@ -0,0 +1,284 @@
+use derive_new::new;
+use satrs::hk::{HkRequest, HkRequestVariant};
+use satrs::queue::{GenericSendError, GenericTargetedMessagingError};
+use satrs::spacepackets::ecss::hk;
+use satrs::spacepackets::ecss::tm::{PusTmCreator, PusTmSecondaryHeader};
+use satrs::spacepackets::SpHeader;
+use satrs_example::{DeviceMode, TimeStampHelper};
+use std::sync::mpsc::{self};
+use std::sync::{Arc, Mutex};
+
+use satrs::mode::{
+ ModeAndSubmode, ModeError, ModeProvider, ModeReply, ModeRequest, ModeRequestHandler,
+};
+use satrs::pus::{EcssTmSenderCore, PusTmVariant};
+use satrs::request::{GenericMessage, MessageMetadata, UniqueApidTargetId};
+use satrs_example::config::components::PUS_MODE_SERVICE;
+
+use crate::pus::hk::{HkReply, HkReplyVariant};
+use crate::requests::CompositeRequest;
+
+use serde::{Deserialize, Serialize};
+
+const GAUSS_TO_MICROTESLA_FACTOR: f32 = 100.0;
+// This is the selected resoltion for the STM LIS3MDL device for the 4 Gauss sensitivity setting.
+const FIELD_LSB_PER_GAUSS_4_SENS: f32 = 1.0 / 6842.0;
+
+pub trait SpiInterface {
+ type Error;
+ fn transfer(&mut self, tx: &[u8], rx: &mut [u8]) -> Result<(), Self::Error>;
+}
+
+#[derive(Default)]
+pub struct SpiDummyInterface {
+ pub dummy_val_0: i16,
+ pub dummy_val_1: i16,
+ pub dummy_val_2: i16,
+}
+
+impl SpiInterface for SpiDummyInterface {
+ type Error = ();
+
+ fn transfer(&mut self, _tx: &[u8], rx: &mut [u8]) -> Result<(), Self::Error> {
+ rx[0..2].copy_from_slice(&self.dummy_val_0.to_be_bytes());
+ rx[2..4].copy_from_slice(&self.dummy_val_1.to_be_bytes());
+ rx[4..6].copy_from_slice(&self.dummy_val_2.to_be_bytes());
+ Ok(())
+ }
+}
+
+#[derive(Default, Debug, Copy, Clone, Serialize, Deserialize)]
+pub struct MgmData {
+ pub valid: bool,
+ pub x: f32,
+ pub y: f32,
+ pub z: f32,
+}
+
+pub struct MpscModeLeafInterface {
+ pub request_rx: mpsc::Receiver>,
+ pub reply_tx_to_pus: mpsc::Sender>,
+ pub reply_tx_to_parent: mpsc::Sender>,
+}
+
+/// Example MGM device handler strongly based on the LIS3MDL MEMS device.
+#[derive(new)]
+#[allow(clippy::too_many_arguments)]
+pub struct MgmHandlerLis3Mdl {
+ id: UniqueApidTargetId,
+ dev_str: &'static str,
+ mode_interface: MpscModeLeafInterface,
+ composite_request_receiver: mpsc::Receiver>,
+ hk_reply_sender: mpsc::Sender>,
+ tm_sender: TmSender,
+ com_interface: ComInterface,
+ shared_mgm_set: Arc>,
+ #[new(value = "ModeAndSubmode::new(satrs_example::DeviceMode::Off as u32, 0)")]
+ mode_and_submode: ModeAndSubmode,
+ #[new(default)]
+ tx_buf: [u8; 12],
+ #[new(default)]
+ rx_buf: [u8; 12],
+ #[new(default)]
+ tm_buf: [u8; 16],
+ #[new(default)]
+ stamp_helper: TimeStampHelper,
+}
+
+impl
+ MgmHandlerLis3Mdl
+{
+ pub fn periodic_operation(&mut self) {
+ self.stamp_helper.update_from_now();
+ // Handle requests.
+ self.handle_composite_requests();
+ self.handle_mode_requests();
+ if self.mode() == DeviceMode::Normal as u32 {
+ log::trace!("polling LIS3MDL sensor {}", self.dev_str);
+ // Communicate with the device.
+ let result = self.com_interface.transfer(&self.tx_buf, &mut self.rx_buf);
+ assert!(result.is_ok());
+ // Actual data begins on the second byte, similarly to how a lot of SPI devices behave.
+ let x_raw = i16::from_be_bytes(self.rx_buf[1..3].try_into().unwrap());
+ let y_raw = i16::from_be_bytes(self.rx_buf[3..5].try_into().unwrap());
+ let z_raw = i16::from_be_bytes(self.rx_buf[5..7].try_into().unwrap());
+ // Simple scaling to retrieve the float value, assuming a sensor resolution of
+ let mut mgm_guard = self.shared_mgm_set.lock().unwrap();
+ mgm_guard.x = x_raw as f32 * GAUSS_TO_MICROTESLA_FACTOR * FIELD_LSB_PER_GAUSS_4_SENS;
+ mgm_guard.y = y_raw as f32 * GAUSS_TO_MICROTESLA_FACTOR * FIELD_LSB_PER_GAUSS_4_SENS;
+ mgm_guard.z = z_raw as f32 * GAUSS_TO_MICROTESLA_FACTOR * FIELD_LSB_PER_GAUSS_4_SENS;
+ drop(mgm_guard);
+ }
+ }
+
+ pub fn handle_composite_requests(&mut self) {
+ loop {
+ match self.composite_request_receiver.try_recv() {
+ Ok(ref msg) => match &msg.message {
+ CompositeRequest::Hk(hk_request) => {
+ self.handle_hk_request(&msg.requestor_info, hk_request)
+ }
+ // TODO: This object does not have actions (yet).. Still send back completion failure
+ // reply.
+ CompositeRequest::Action(_action_req) => {}
+ },
+
+ Err(e) => {
+ if e != mpsc::TryRecvError::Empty {
+ log::warn!(
+ "{}: failed to receive composite request: {:?}",
+ self.dev_str,
+ e
+ );
+ } else {
+ break;
+ }
+ }
+ }
+ }
+ }
+
+ pub fn handle_hk_request(&mut self, requestor_info: &MessageMetadata, hk_request: &HkRequest) {
+ match hk_request.variant {
+ HkRequestVariant::OneShot => {
+ self.hk_reply_sender
+ .send(GenericMessage::new(
+ *requestor_info,
+ HkReply::new(hk_request.unique_id, HkReplyVariant::Ack),
+ ))
+ .expect("failed to send HK reply");
+ let sec_header = PusTmSecondaryHeader::new(
+ 3,
+ hk::Subservice::TmHkPacket as u8,
+ 0,
+ 0,
+ self.stamp_helper.stamp(),
+ );
+ let mgm_snapshot = *self.shared_mgm_set.lock().unwrap();
+ // Use binary serialization here. We want the data to be tightly packed.
+ self.tm_buf[0] = mgm_snapshot.valid as u8;
+ self.tm_buf[1..5].copy_from_slice(&mgm_snapshot.x.to_be_bytes());
+ self.tm_buf[5..9].copy_from_slice(&mgm_snapshot.y.to_be_bytes());
+ self.tm_buf[9..13].copy_from_slice(&mgm_snapshot.z.to_be_bytes());
+ let hk_tm = PusTmCreator::new(
+ SpHeader::new_from_apid(self.id.apid),
+ sec_header,
+ &self.tm_buf[0..12],
+ true,
+ );
+ self.tm_sender
+ .send_tm(self.id.id(), PusTmVariant::Direct(hk_tm))
+ .expect("failed to send HK TM");
+ }
+ HkRequestVariant::EnablePeriodic => todo!(),
+ HkRequestVariant::DisablePeriodic => todo!(),
+ HkRequestVariant::ModifyCollectionInterval(_) => todo!(),
+ }
+ }
+
+ pub fn handle_mode_requests(&mut self) {
+ loop {
+ // TODO: Only allow one set mode request per cycle?
+ match self.mode_interface.request_rx.try_recv() {
+ Ok(msg) => {
+ let result = self.handle_mode_request(msg);
+ // TODO: Trigger event?
+ if result.is_err() {
+ log::warn!(
+ "{}: mode request failed with error {:?}",
+ self.dev_str,
+ result.err().unwrap()
+ );
+ }
+ }
+ Err(e) => {
+ if e != mpsc::TryRecvError::Empty {
+ log::warn!("{}: failed to receive mode request: {:?}", self.dev_str, e);
+ } else {
+ break;
+ }
+ }
+ }
+ }
+ }
+}
+
+impl ModeProvider
+ for MgmHandlerLis3Mdl
+{
+ fn mode_and_submode(&self) -> ModeAndSubmode {
+ self.mode_and_submode
+ }
+}
+
+impl ModeRequestHandler
+ for MgmHandlerLis3Mdl
+{
+ type Error = ModeError;
+ fn start_transition(
+ &mut self,
+ requestor: MessageMetadata,
+ mode_and_submode: ModeAndSubmode,
+ ) -> Result<(), satrs::mode::ModeError> {
+ log::info!(
+ "{}: transitioning to mode {:?}",
+ self.dev_str,
+ mode_and_submode
+ );
+ self.mode_and_submode = mode_and_submode;
+ self.handle_mode_reached(Some(requestor))?;
+ Ok(())
+ }
+
+ fn announce_mode(&self, _requestor_info: Option, _recursive: bool) {
+ log::info!(
+ "{} announcing mode: {:?}",
+ self.dev_str,
+ self.mode_and_submode
+ );
+ }
+
+ fn handle_mode_reached(
+ &mut self,
+ requestor: Option,
+ ) -> Result<(), Self::Error> {
+ self.announce_mode(requestor, false);
+ if let Some(requestor) = requestor {
+ if requestor.sender_id() != PUS_MODE_SERVICE.id() {
+ log::warn!(
+ "can not send back mode reply to sender {}",
+ requestor.sender_id()
+ );
+ } else {
+ self.send_mode_reply(requestor, ModeReply::ModeReply(self.mode_and_submode()))?;
+ }
+ }
+ Ok(())
+ }
+
+ fn send_mode_reply(
+ &self,
+ requestor: MessageMetadata,
+ reply: ModeReply,
+ ) -> Result<(), Self::Error> {
+ if requestor.sender_id() != PUS_MODE_SERVICE.id() {
+ log::warn!(
+ "can not send back mode reply to sender {}",
+ requestor.sender_id()
+ );
+ }
+ self.mode_interface
+ .reply_tx_to_pus
+ .send(GenericMessage::new(requestor, reply))
+ .map_err(|_| GenericTargetedMessagingError::Send(GenericSendError::RxDisconnected))?;
+ Ok(())
+ }
+
+ fn handle_mode_info(
+ &mut self,
+ _requestor_info: MessageMetadata,
+ _info: ModeAndSubmode,
+ ) -> Result<(), Self::Error> {
+ Ok(())
+ }
+}
diff --git a/satrs-example/src/acs/mod.rs b/satrs-example/src/acs/mod.rs
new file mode 100644
index 0000000..bd61e8b
--- /dev/null
+++ b/satrs-example/src/acs/mod.rs
@@ -0,0 +1 @@
+pub mod mgm;
diff --git a/satrs-example/src/bin/simpleclient.rs b/satrs-example/src/bin/simpleclient.rs
index 04281ca..bbe7609 100644
--- a/satrs-example/src/bin/simpleclient.rs
+++ b/satrs-example/src/bin/simpleclient.rs
@@ -12,8 +12,7 @@ use std::time::Duration;
fn main() {
let mut buf = [0; 32];
let addr = SocketAddr::new(IpAddr::V4(OBSW_SERVER_ADDR), SERVER_PORT);
- let mut sph = SpHeader::tc_unseg(0x02, 0, 0).unwrap();
- let pus_tc = PusTcCreator::new_simple(&mut sph, 17, 1, None, true);
+ let pus_tc = PusTcCreator::new_simple(SpHeader::new_from_apid(0x02), 17, 1, &[], true);
let client = UdpSocket::bind("127.0.0.1:7302").expect("Connecting to UDP server failed");
let tc_req_id = RequestId::new(&pus_tc);
println!("Packing and sending PUS ping command TC[17,1] with request ID {tc_req_id}");
diff --git a/satrs-example/src/ccsds.rs b/satrs-example/src/ccsds.rs
index e61172e..1841d17 100644
--- a/satrs-example/src/ccsds.rs
+++ b/satrs-example/src/ccsds.rs
@@ -1,7 +1,9 @@
use satrs::pus::ReceivesEcssPusTc;
use satrs::spacepackets::{CcsdsPacket, SpHeader};
use satrs::tmtc::{CcsdsPacketHandler, ReceivesCcsdsTc};
-use satrs_example::config::PUS_APID;
+use satrs::ValidatorU16Id;
+use satrs_example::config::components::Apid;
+use satrs_example::config::APID_VALIDATOR;
#[derive(Clone)]
pub struct CcsdsReceiver<
@@ -11,6 +13,16 @@ pub struct CcsdsReceiver<
pub tc_source: TcSource,
}
+impl<
+ TcSource: ReceivesCcsdsTc + ReceivesEcssPusTc + Clone + 'static,
+ E: 'static,
+ > ValidatorU16Id for CcsdsReceiver
+{
+ fn validate(&self, apid: u16) -> bool {
+ APID_VALIDATOR.contains(&apid)
+ }
+}
+
impl<
TcSource: ReceivesCcsdsTc + ReceivesEcssPusTc + Clone + 'static,
E: 'static,
@@ -18,27 +30,24 @@ impl<
{
type Error = E;
- fn valid_apids(&self) -> &'static [u16] {
- &[PUS_APID]
- }
-
- fn handle_known_apid(
+ fn handle_packet_with_valid_apid(
&mut self,
sp_header: &SpHeader,
tc_raw: &[u8],
) -> Result<(), Self::Error> {
- if sp_header.apid() == PUS_APID {
+ if sp_header.apid() == Apid::Cfdp as u16 {
+ } else {
return self.tc_source.pass_ccsds(sp_header, tc_raw);
}
Ok(())
}
- fn handle_unknown_apid(
+ fn handle_packet_with_unknown_apid(
&mut self,
sp_header: &SpHeader,
_tc_raw: &[u8],
) -> Result<(), Self::Error> {
- println!("Unknown APID 0x{:x?} detected", sp_header.apid());
+ log::warn!("unknown APID 0x{:x?} detected", sp_header.apid());
Ok(())
}
}
diff --git a/satrs-example/src/config.rs b/satrs-example/src/config.rs
index 9d04403..7e474e9 100644
--- a/satrs-example/src/config.rs
+++ b/satrs-example/src/config.rs
@@ -1,7 +1,12 @@
-use satrs::res_code::ResultU16;
+use lazy_static::lazy_static;
+use satrs::{
+ res_code::ResultU16,
+ spacepackets::{PacketId, PacketType},
+};
use satrs_mib::res_code::ResultU16Info;
use satrs_mib::resultcode;
-use std::net::Ipv4Addr;
+use std::{collections::HashSet, net::Ipv4Addr};
+use strum::IntoEnumIterator;
use num_enum::{IntoPrimitive, TryFromPrimitive};
use satrs::{
@@ -9,8 +14,6 @@ use satrs::{
pool::{StaticMemoryPool, StaticPoolConfig},
};
-pub const PUS_APID: u16 = 0x02;
-
#[derive(Copy, Clone, PartialEq, Eq, Debug, TryFromPrimitive, IntoPrimitive)]
#[repr(u8)]
pub enum CustomPusServiceId {
@@ -29,6 +32,7 @@ pub const AOCS_APID: u16 = 1;
pub enum GroupId {
Tmtc = 0,
Hk = 1,
+ Mode = 2,
}
pub const OBSW_SERVER_ADDR: Ipv4Addr = Ipv4Addr::UNSPECIFIED;
@@ -37,6 +41,23 @@ pub const SERVER_PORT: u16 = 7301;
pub const TEST_EVENT: EventU32TypedSev =
EventU32TypedSev::::const_new(0, 0);
+lazy_static! {
+ pub static ref PACKET_ID_VALIDATOR: HashSet = {
+ let mut set = HashSet::new();
+ for id in components::Apid::iter() {
+ set.insert(PacketId::new(PacketType::Tc, true, id as u16));
+ }
+ set
+ };
+ pub static ref APID_VALIDATOR: HashSet = {
+ let mut set = HashSet::new();
+ for id in components::Apid::iter() {
+ set.insert(id as u16);
+ }
+ set
+ };
+}
+
pub mod tmtc_err {
use super::*;
@@ -53,6 +74,8 @@ pub mod tmtc_err {
pub const UNKNOWN_TARGET_ID: ResultU16 = ResultU16::new(GroupId::Tmtc as u8, 4);
#[resultcode]
pub const ROUTING_ERROR: ResultU16 = ResultU16::new(GroupId::Tmtc as u8, 5);
+ #[resultcode(info = "Request timeout for targeted PUS request. P1: Request ID. P2: Target ID")]
+ pub const REQUEST_TIMEOUT: ResultU16 = ResultU16::new(GroupId::Tmtc as u8, 6);
#[resultcode(
info = "Not enough data inside the TC application data field. Optionally includes: \
@@ -92,27 +115,59 @@ pub mod hk_err {
];
}
-#[allow(clippy::enum_variant_names)]
-#[derive(Copy, Clone, PartialEq, Eq)]
-pub enum TmSenderId {
- PusVerification = 0,
- PusTest = 1,
- PusEvent = 2,
- PusHk = 3,
- PusAction = 4,
- PusSched = 5,
- AllEvents = 6,
- AcsSubsystem = 7,
+pub mod mode_err {
+ use super::*;
+
+ #[resultcode]
+ pub const WRONG_MODE: ResultU16 = ResultU16::new(GroupId::Mode as u8, 0);
}
-#[derive(Copy, Clone, PartialEq, Eq)]
-pub enum TcReceiverId {
- PusTest = 1,
- PusEvent = 2,
- PusHk = 3,
- PusAction = 4,
- PusSched = 5,
+pub mod components {
+ use satrs::request::UniqueApidTargetId;
+ use strum::EnumIter;
+
+ #[derive(Copy, Clone, PartialEq, Eq, EnumIter)]
+ pub enum Apid {
+ Sched = 1,
+ GenericPus = 2,
+ Acs = 3,
+ Cfdp = 4,
+ }
+
+ // Component IDs for components with the PUS APID.
+ #[derive(Copy, Clone, PartialEq, Eq)]
+ pub enum PusId {
+ PusEventManagement = 0,
+ PusRouting = 1,
+ PusTest = 2,
+ PusAction = 3,
+ PusMode = 4,
+ PusHk = 5,
+ }
+
+ #[derive(Copy, Clone, PartialEq, Eq)]
+ pub enum AcsId {
+ Mgm0 = 0,
+ }
+
+ pub const PUS_ACTION_SERVICE: UniqueApidTargetId =
+ UniqueApidTargetId::new(Apid::GenericPus as u16, PusId::PusAction as u32);
+ pub const PUS_EVENT_MANAGEMENT: UniqueApidTargetId =
+ UniqueApidTargetId::new(Apid::GenericPus as u16, 0);
+ pub const PUS_ROUTING_SERVICE: UniqueApidTargetId =
+ UniqueApidTargetId::new(Apid::GenericPus as u16, PusId::PusRouting as u32);
+ pub const PUS_TEST_SERVICE: UniqueApidTargetId =
+ UniqueApidTargetId::new(Apid::GenericPus as u16, PusId::PusTest as u32);
+ pub const PUS_MODE_SERVICE: UniqueApidTargetId =
+ UniqueApidTargetId::new(Apid::GenericPus as u16, PusId::PusMode as u32);
+ pub const PUS_HK_SERVICE: UniqueApidTargetId =
+ UniqueApidTargetId::new(Apid::GenericPus as u16, PusId::PusHk as u32);
+ pub const PUS_SCHED_SERVICE: UniqueApidTargetId =
+ UniqueApidTargetId::new(Apid::Sched as u16, 0);
+ pub const MGM_HANDLER_0: UniqueApidTargetId =
+ UniqueApidTargetId::new(Apid::Acs as u16, AcsId::Mgm0 as u32);
}
+
pub mod pool {
use super::*;
pub fn create_static_pools() -> (StaticMemoryPool, StaticMemoryPool) {
diff --git a/satrs-example/src/events.rs b/satrs-example/src/events.rs
index a6a0d86..4d7ea9f 100644
--- a/satrs-example/src/events.rs
+++ b/satrs-example/src/events.rs
@@ -1,66 +1,87 @@
use std::sync::mpsc::{self};
+use crate::pus::create_verification_reporter;
+use satrs::event_man::{EventMessageU32, EventRoutingError};
+use satrs::params::WritableToBeBytes;
+use satrs::pus::event::EventTmHookProvider;
+use satrs::pus::verification::VerificationReporter;
+use satrs::pus::EcssTmSenderCore;
+use satrs::request::UniqueApidTargetId;
use satrs::{
event_man::{
EventManagerWithBoundedMpsc, EventSendProvider, EventU32SenderMpscBounded,
MpscEventReceiver,
},
- events::EventU32,
- params::Params,
pus::{
event_man::{
DefaultPusEventU32Dispatcher, EventReporter, EventRequest, EventRequestWithToken,
},
verification::{TcStateStarted, VerificationReportingProvider, VerificationToken},
- EcssTmSender,
},
- spacepackets::time::cds::{self, TimeProvider},
+ spacepackets::time::cds::CdsTime,
};
-use satrs_example::config::PUS_APID;
+use satrs_example::config::components::PUS_EVENT_MANAGEMENT;
use crate::update_time;
-pub struct PusEventHandler {
+// This helper sets the APID of the event sender for the PUS telemetry.
+#[derive(Default)]
+pub struct EventApidSetter {
+ pub next_apid: u16,
+}
+
+impl EventTmHookProvider for EventApidSetter {
+ fn modify_tm(&self, tm: &mut satrs::spacepackets::ecss::tm::PusTmCreator) {
+ tm.set_apid(self.next_apid);
+ }
+}
+
+/// The PUS event handler subscribes for all events and converts them into ECSS PUS 5 event
+/// packets. It also handles the verification completion of PUS event service requests.
+pub struct PusEventHandler {
event_request_rx: mpsc::Receiver,
pus_event_dispatcher: DefaultPusEventU32Dispatcher<()>,
- pus_event_man_rx: mpsc::Receiver<(EventU32, Option)>,
- tm_sender: Box,
- time_provider: TimeProvider,
+ pus_event_man_rx: mpsc::Receiver,
+ tm_sender: TmSender,
+ time_provider: CdsTime,
timestamp: [u8; 7],
verif_handler: VerificationReporter,
+ event_apid_setter: EventApidSetter,
}
-/*
-*/
-impl PusEventHandler {
+impl PusEventHandler {
pub fn new(
+ tm_sender: TmSender,
verif_handler: VerificationReporter,
event_manager: &mut EventManagerWithBoundedMpsc,
event_request_rx: mpsc::Receiver,
- tm_sender: impl EcssTmSender,
) -> Self {
let event_queue_cap = 30;
let (pus_event_man_tx, pus_event_man_rx) = mpsc::sync_channel(event_queue_cap);
// All events sent to the manager are routed to the PUS event manager, which generates PUS event
// telemetry for each event.
- let event_reporter = EventReporter::new(PUS_APID, 128).unwrap();
+ let event_reporter = EventReporter::new(PUS_EVENT_MANAGEMENT.raw(), 0, 0, 128).unwrap();
let pus_event_dispatcher =
DefaultPusEventU32Dispatcher::new_with_default_backend(event_reporter);
- let pus_event_man_send_provider =
- EventU32SenderMpscBounded::new(1, pus_event_man_tx, event_queue_cap);
+ let pus_event_man_send_provider = EventU32SenderMpscBounded::new(
+ PUS_EVENT_MANAGEMENT.raw(),
+ pus_event_man_tx,
+ event_queue_cap,
+ );
- event_manager.subscribe_all(pus_event_man_send_provider.channel_id());
+ event_manager.subscribe_all(pus_event_man_send_provider.target_id());
event_manager.add_sender(pus_event_man_send_provider);
Self {
event_request_rx,
pus_event_dispatcher,
pus_event_man_rx,
- time_provider: cds::TimeProvider::new_with_u16_days(0, 0),
+ time_provider: CdsTime::new_with_u16_days(0, 0),
timestamp: [0; 7],
verif_handler,
- tm_sender: Box::new(tm_sender),
+ tm_sender,
+ event_apid_setter: EventApidSetter::default(),
}
}
@@ -71,7 +92,7 @@ impl PusEventHandler PusEventHandler)>,
+ event_sender: mpsc::Sender,
}
impl EventManagerWrapper {
@@ -121,14 +148,15 @@ impl EventManagerWrapper {
// The sender handle is the primary sender handle for all components which want to create events.
// The event manager will receive the RX handle to receive all the events.
let (event_sender, event_man_rx) = mpsc::channel();
- let event_recv = MpscEventReceiver::::new(event_man_rx);
+ let event_recv = MpscEventReceiver::new(event_man_rx);
Self {
event_manager: EventManagerWithBoundedMpsc::new(event_recv),
event_sender,
}
}
- pub fn clone_event_sender(&self) -> mpsc::Sender<(EventU32, Option)> {
+ // Returns a cached event sender to send events to the event manager for routing.
+ pub fn clone_event_sender(&self) -> mpsc::Sender {
self.event_sender.clone()
}
@@ -137,30 +165,34 @@ impl EventManagerWrapper {
}
pub fn try_event_routing(&mut self) {
+ let error_handler = |event_msg: &EventMessageU32, error: EventRoutingError| {
+ self.routing_error_handler(event_msg, error)
+ };
// Perform the event routing.
- self.event_manager
- .try_event_handling()
- .expect("event handling failed");
+ self.event_manager.try_event_handling(error_handler);
+ }
+
+ pub fn routing_error_handler(&self, event_msg: &EventMessageU32, error: EventRoutingError) {
+ log::warn!("event routing error for event {event_msg:?}: {error:?}");
}
}
-pub struct EventHandler {
+pub struct EventHandler {
pub event_man_wrapper: EventManagerWrapper,
- pub pus_event_handler: PusEventHandler,
+ pub pus_event_handler: PusEventHandler,
}
-impl EventHandler {
+impl EventHandler {
pub fn new(
- tm_sender: impl EcssTmSender,
- verif_handler: VerificationReporter,
+ tm_sender: TmSender,
event_request_rx: mpsc::Receiver,
) -> Self {
let mut event_man_wrapper = EventManagerWrapper::new();
let pus_event_handler = PusEventHandler::new(
- verif_handler,
+ tm_sender,
+ create_verification_reporter(PUS_EVENT_MANAGEMENT.id(), PUS_EVENT_MANAGEMENT.apid),
event_man_wrapper.event_manager(),
event_request_rx,
- tm_sender,
);
Self {
event_man_wrapper,
@@ -168,7 +200,7 @@ impl EventHandler mpsc::Sender<(EventU32, Option)> {
+ pub fn clone_event_sender(&self) -> mpsc::Sender {
self.event_man_wrapper.clone_event_sender()
}
diff --git a/satrs-example/src/hk.rs b/satrs-example/src/hk.rs
index 3147cbf..0852d04 100644
--- a/satrs-example/src/hk.rs
+++ b/satrs-example/src/hk.rs
@@ -1,27 +1,25 @@
use derive_new::new;
+use satrs::hk::UniqueId;
+use satrs::request::UniqueApidTargetId;
use satrs::spacepackets::ByteConversionError;
-#[derive(Debug, Copy, Clone, PartialEq, Eq)]
-pub enum AcsHkIds {
- TestMgmSet = 1,
-}
-
#[derive(Debug, new, Copy, Clone)]
pub struct HkUniqueId {
- target_id: u32,
- set_id: u32,
+ target_id: UniqueApidTargetId,
+ set_id: UniqueId,
}
impl HkUniqueId {
#[allow(dead_code)]
- pub fn target_id(&self) -> u32 {
+ pub fn target_id(&self) -> UniqueApidTargetId {
self.target_id
}
#[allow(dead_code)]
- pub fn set_id(&self) -> u32 {
+ pub fn set_id(&self) -> UniqueId {
self.set_id
}
+ #[allow(dead_code)]
pub fn write_to_be_bytes(&self, buf: &mut [u8]) -> Result {
if buf.len() < 8 {
return Err(ByteConversionError::ToSliceTooSmall {
@@ -29,7 +27,7 @@ impl HkUniqueId {
expected: 8,
});
}
- buf[0..4].copy_from_slice(&self.target_id.to_be_bytes());
+ buf[0..4].copy_from_slice(&self.target_id.unique_id.to_be_bytes());
buf[4..8].copy_from_slice(&self.set_id.to_be_bytes());
Ok(8)
diff --git a/satrs-example/src/lib.rs b/satrs-example/src/lib.rs
index ef68c36..a224fe5 100644
--- a/satrs-example/src/lib.rs
+++ b/satrs-example/src/lib.rs
@@ -1 +1,39 @@
+use satrs::spacepackets::time::{cds::CdsTime, TimeWriter};
+
pub mod config;
+
+#[derive(Debug, PartialEq, Eq, Copy, Clone)]
+pub enum DeviceMode {
+ Off = 0,
+ On = 1,
+ Normal = 2,
+}
+
+pub struct TimeStampHelper {
+ stamper: CdsTime,
+ time_stamp: [u8; 7],
+}
+
+impl TimeStampHelper {
+ pub fn stamp(&self) -> &[u8] {
+ &self.time_stamp
+ }
+
+ pub fn update_from_now(&mut self) {
+ self.stamper
+ .update_from_now()
+ .expect("Updating timestamp failed");
+ self.stamper
+ .write_to_bytes(&mut self.time_stamp)
+ .expect("Writing timestamp failed");
+ }
+}
+
+impl Default for TimeStampHelper {
+ fn default() -> Self {
+ Self {
+ stamper: CdsTime::now_with_u16_days().expect("creating time stamper failed"),
+ time_stamp: Default::default(),
+ }
+ }
+}
diff --git a/satrs-example/src/main.rs b/satrs-example/src/main.rs
index 0cdd462..a6456d6 100644
--- a/satrs-example/src/main.rs
+++ b/satrs-example/src/main.rs
@@ -17,52 +17,44 @@ use log::info;
use pus::test::create_test_service_dynamic;
use satrs::hal::std::tcp_server::ServerConfig;
use satrs::hal::std::udp_server::UdpTcServer;
-use satrs::request::TargetAndApidId;
+use satrs::request::GenericMessage;
use satrs::tmtc::tm_helper::SharedTmPool;
use satrs_example::config::pool::{create_sched_tc_pool, create_static_pools};
use satrs_example::config::tasks::{
FREQ_MS_AOCS, FREQ_MS_EVENT_HANDLING, FREQ_MS_PUS_STACK, FREQ_MS_UDP_TMTC,
};
-use satrs_example::config::{RequestTargetId, TmSenderId, OBSW_SERVER_ADDR, PUS_APID, SERVER_PORT};
+use satrs_example::config::{OBSW_SERVER_ADDR, PACKET_ID_VALIDATOR, SERVER_PORT};
use tmtc::PusTcSourceProviderDynamic;
use udp::DynamicUdpTmHandler;
-use crate::acs::AcsTask;
+use crate::acs::mgm::{MgmHandlerLis3Mdl, MpscModeLeafInterface, SpiDummyInterface};
use crate::ccsds::CcsdsReceiver;
use crate::logger::setup_logger;
use crate::pus::action::{create_action_service_dynamic, create_action_service_static};
use crate::pus::event::{create_event_service_dynamic, create_event_service_static};
use crate::pus::hk::{create_hk_service_dynamic, create_hk_service_static};
+use crate::pus::mode::{create_mode_service_dynamic, create_mode_service_static};
use crate::pus::scheduler::{create_scheduler_service_dynamic, create_scheduler_service_static};
use crate::pus::test::create_test_service_static;
use crate::pus::{PusReceiver, PusTcMpscRouter};
-use crate::requests::{GenericRequestRouter, RequestWithToken};
+use crate::requests::{CompositeRequest, GenericRequestRouter};
use crate::tcp::{SyncTcpTmSource, TcpTask};
use crate::tmtc::{
PusTcSourceProviderSharedPool, SharedTcPool, TcSourceTaskDynamic, TcSourceTaskStatic,
};
use crate::udp::{StaticUdpTmHandler, UdpTmtcServer};
+use satrs::mode::ModeRequest;
use satrs::pus::event_man::EventRequestWithToken;
-use satrs::pus::verification::{VerificationReporterCfg, VerificationReporterWithSender};
-use satrs::pus::{EcssTmSender, TmAsVecSenderWithId, TmInSharedPoolSenderWithId};
-use satrs::spacepackets::{time::cds::TimeProvider, time::TimeWriter};
+use satrs::pus::TmInSharedPoolSender;
+use satrs::spacepackets::{time::cds::CdsTime, time::TimeWriter};
use satrs::tmtc::CcsdsDistributor;
-use satrs::ChannelId;
+use satrs_example::config::components::MGM_HANDLER_0;
use std::net::{IpAddr, SocketAddr};
-use std::sync::mpsc::{self, channel};
+use std::sync::mpsc;
use std::sync::{Arc, RwLock};
use std::thread;
use std::time::Duration;
-fn create_verification_reporter(
- verif_sender: Sender,
-) -> VerificationReporterWithSender {
- let verif_cfg = VerificationReporterCfg::new(PUS_APID, 1, 2, 8).unwrap();
- // Every software component which needs to generate verification telemetry, gets a cloned
- // verification reporter.
- VerificationReporterWithSender::new(&verif_cfg, verif_sender)
-}
-
#[allow(dead_code)]
fn static_tmtc_pool_main() {
let (tm_pool, tc_pool) = create_static_pools();
@@ -74,20 +66,21 @@ fn static_tmtc_pool_main() {
let (tm_funnel_tx, tm_funnel_rx) = mpsc::sync_channel(50);
let (tm_server_tx, tm_server_rx) = mpsc::sync_channel(50);
- // Every software component which needs to generate verification telemetry, receives a cloned
- // verification reporter.
- let verif_reporter = create_verification_reporter(TmInSharedPoolSenderWithId::new(
- TmSenderId::PusVerification as ChannelId,
- "verif_sender",
- shared_tm_pool.clone(),
- tm_funnel_tx.clone(),
- ));
+ let tm_funnel_tx_sender =
+ TmInSharedPoolSender::new(shared_tm_pool.clone(), tm_funnel_tx.clone());
+
+ let (mgm_handler_composite_tx, mgm_handler_composite_rx) =
+ mpsc::channel::>();
+ let (mgm_handler_mode_tx, mgm_handler_mode_rx) = mpsc::channel::>();
- let acs_target_id = TargetAndApidId::new(PUS_APID, RequestTargetId::AcsSubsystem as u32);
- let (acs_thread_tx, acs_thread_rx) = channel::();
// Some request are targetable. This map is used to retrieve sender handles based on a target ID.
let mut request_map = GenericRequestRouter::default();
- request_map.0.insert(acs_target_id.into(), acs_thread_tx);
+ request_map
+ .composite_router_map
+ .insert(MGM_HANDLER_0.id(), mgm_handler_composite_tx);
+ request_map
+ .mode_router_map
+ .insert(MGM_HANDLER_0.id(), mgm_handler_mode_tx);
// This helper structure is used by all telecommand providers which need to send telecommands
// to the TC source.
@@ -103,82 +96,80 @@ fn static_tmtc_pool_main() {
// The event task is the core handler to perform the event routing and TM handling as specified
// in the sat-rs documentation.
- let mut event_handler = EventHandler::new(
- TmInSharedPoolSenderWithId::new(
- TmSenderId::AllEvents as ChannelId,
- "ALL_EVENTS_TX",
- shared_tm_pool.clone(),
- tm_funnel_tx.clone(),
- ),
- verif_reporter.clone(),
- event_request_rx,
- );
+ let mut event_handler = EventHandler::new(tm_funnel_tx.clone(), event_request_rx);
+
+ let (pus_test_tx, pus_test_rx) = mpsc::channel();
+ let (pus_event_tx, pus_event_rx) = mpsc::channel();
+ let (pus_sched_tx, pus_sched_rx) = mpsc::channel();
+ let (pus_hk_tx, pus_hk_rx) = mpsc::channel();
+ let (pus_action_tx, pus_action_rx) = mpsc::channel();
+ let (pus_mode_tx, pus_mode_rx) = mpsc::channel();
+
+ let (_pus_action_reply_tx, pus_action_reply_rx) = mpsc::channel();
+ let (pus_hk_reply_tx, pus_hk_reply_rx) = mpsc::channel();
+ let (pus_mode_reply_tx, pus_mode_reply_rx) = mpsc::channel();
- let (pus_test_tx, pus_test_rx) = channel();
- let (pus_event_tx, pus_event_rx) = channel();
- let (pus_sched_tx, pus_sched_rx) = channel();
- let (pus_hk_tx, pus_hk_rx) = channel();
- let (pus_action_tx, pus_action_rx) = channel();
let pus_router = PusTcMpscRouter {
- test_service_receiver: pus_test_tx,
- event_service_receiver: pus_event_tx,
- sched_service_receiver: pus_sched_tx,
- hk_service_receiver: pus_hk_tx,
- action_service_receiver: pus_action_tx,
+ test_tc_sender: pus_test_tx,
+ event_tc_sender: pus_event_tx,
+ sched_tc_sender: pus_sched_tx,
+ hk_tc_sender: pus_hk_tx,
+ action_tc_sender: pus_action_tx,
+ mode_tc_sender: pus_mode_tx,
};
let pus_test_service = create_test_service_static(
- shared_tm_pool.clone(),
- tm_funnel_tx.clone(),
- verif_reporter.clone(),
+ tm_funnel_tx_sender.clone(),
shared_tc_pool.pool.clone(),
event_handler.clone_event_sender(),
pus_test_rx,
);
let pus_scheduler_service = create_scheduler_service_static(
- shared_tm_pool.clone(),
- tm_funnel_tx.clone(),
- verif_reporter.clone(),
+ tm_funnel_tx_sender.clone(),
tc_source.clone(),
pus_sched_rx,
create_sched_tc_pool(),
);
let pus_event_service = create_event_service_static(
- shared_tm_pool.clone(),
- tm_funnel_tx.clone(),
- verif_reporter.clone(),
+ tm_funnel_tx_sender.clone(),
shared_tc_pool.pool.clone(),
pus_event_rx,
event_request_tx,
);
let pus_action_service = create_action_service_static(
- shared_tm_pool.clone(),
- tm_funnel_tx.clone(),
- verif_reporter.clone(),
+ tm_funnel_tx_sender.clone(),
shared_tc_pool.pool.clone(),
pus_action_rx,
request_map.clone(),
+ pus_action_reply_rx,
);
let pus_hk_service = create_hk_service_static(
- shared_tm_pool.clone(),
- tm_funnel_tx.clone(),
- verif_reporter.clone(),
+ tm_funnel_tx_sender.clone(),
shared_tc_pool.pool.clone(),
pus_hk_rx,
+ request_map.clone(),
+ pus_hk_reply_rx,
+ );
+ let pus_mode_service = create_mode_service_static(
+ tm_funnel_tx_sender.clone(),
+ shared_tc_pool.pool.clone(),
+ pus_mode_rx,
request_map,
+ pus_mode_reply_rx,
);
let mut pus_stack = PusStack::new(
+ pus_test_service,
pus_hk_service,
pus_event_service,
pus_action_service,
pus_scheduler_service,
- pus_test_service,
+ pus_mode_service,
);
let ccsds_receiver = CcsdsReceiver { tc_source };
let mut tmtc_task = TcSourceTaskStatic::new(
shared_tc_pool.clone(),
tc_source_rx,
- PusReceiver::new(verif_reporter.clone(), pus_router),
+ PusReceiver::new(tm_funnel_tx_sender, pus_router),
);
let sock_addr = SocketAddr::new(IpAddr::V4(OBSW_SERVER_ADDR), SERVER_PORT);
@@ -200,20 +191,10 @@ fn static_tmtc_pool_main() {
tcp_server_cfg,
sync_tm_tcp_source.clone(),
tcp_ccsds_distributor,
+ PACKET_ID_VALIDATOR.clone(),
)
.expect("tcp server creation failed");
- let mut acs_task = AcsTask::new(
- TmInSharedPoolSenderWithId::new(
- TmSenderId::AcsSubsystem as ChannelId,
- "ACS_TASK_SENDER",
- shared_tm_pool.clone(),
- tm_funnel_tx.clone(),
- ),
- acs_thread_rx,
- verif_reporter,
- );
-
let mut tm_funnel = TmFunnelStatic::new(
shared_tm_pool,
sync_tm_tcp_source,
@@ -221,6 +202,27 @@ fn static_tmtc_pool_main() {
tm_server_tx,
);
+ let (mgm_handler_mode_reply_to_parent_tx, _mgm_handler_mode_reply_to_parent_rx) =
+ mpsc::channel();
+
+ let dummy_spi_interface = SpiDummyInterface::default();
+ let shared_mgm_set = Arc::default();
+ let mode_leaf_interface = MpscModeLeafInterface {
+ request_rx: mgm_handler_mode_rx,
+ reply_tx_to_pus: pus_mode_reply_tx,
+ reply_tx_to_parent: mgm_handler_mode_reply_to_parent_tx,
+ };
+ let mut mgm_handler = MgmHandlerLis3Mdl::new(
+ MGM_HANDLER_0,
+ "MGM_0",
+ mode_leaf_interface,
+ mgm_handler_composite_rx,
+ pus_hk_reply_tx,
+ tm_funnel_tx,
+ dummy_spi_interface,
+ shared_mgm_set,
+ );
+
info!("Starting TMTC and UDP task");
let jh_udp_tmtc = thread::Builder::new()
.name("TMTC and UDP".to_string())
@@ -266,7 +268,7 @@ fn static_tmtc_pool_main() {
let jh_aocs = thread::Builder::new()
.name("AOCS".to_string())
.spawn(move || loop {
- acs_task.periodic_operation();
+ mgm_handler.periodic_operation();
thread::sleep(Duration::from_millis(FREQ_MS_AOCS));
})
.unwrap();
@@ -300,22 +302,23 @@ fn static_tmtc_pool_main() {
#[allow(dead_code)]
fn dyn_tmtc_pool_main() {
- let (tc_source_tx, tc_source_rx) = channel();
- let (tm_funnel_tx, tm_funnel_rx) = channel();
- let (tm_server_tx, tm_server_rx) = channel();
- // Every software component which needs to generate verification telemetry, gets a cloned
- // verification reporter.
- let verif_reporter = create_verification_reporter(TmAsVecSenderWithId::new(
- TmSenderId::PusVerification as ChannelId,
- "verif_sender",
- tm_funnel_tx.clone(),
- ));
+ let (tc_source_tx, tc_source_rx) = mpsc::channel();
+ let (tm_funnel_tx, tm_funnel_rx) = mpsc::channel();
+ let (tm_server_tx, tm_server_rx) = mpsc::channel();
+
+ // Some request are targetable. This map is used to retrieve sender handles based on a target ID.
+ let (mgm_handler_composite_tx, mgm_handler_composite_rx) =
+ mpsc::channel::>();
+ let (mgm_handler_mode_tx, mgm_handler_mode_rx) = mpsc::channel::>();
- let acs_target_id = TargetAndApidId::new(PUS_APID, RequestTargetId::AcsSubsystem as u32);
- let (acs_thread_tx, acs_thread_rx) = channel::();
// Some request are targetable. This map is used to retrieve sender handles based on a target ID.
let mut request_map = GenericRequestRouter::default();
- request_map.0.insert(acs_target_id.into(), acs_thread_tx);
+ request_map
+ .composite_router_map
+ .insert(MGM_HANDLER_0.raw(), mgm_handler_composite_tx);
+ request_map
+ .mode_router_map
+ .insert(MGM_HANDLER_0.raw(), mgm_handler_mode_tx);
let tc_source = PusTcSourceProviderDynamic(tc_source_tx);
@@ -325,74 +328,74 @@ fn dyn_tmtc_pool_main() {
let (event_request_tx, event_request_rx) = mpsc::channel::();
// The event task is the core handler to perform the event routing and TM handling as specified
// in the sat-rs documentation.
- let mut event_handler = EventHandler::new(
- TmAsVecSenderWithId::new(
- TmSenderId::AllEvents as ChannelId,
- "ALL_EVENTS_TX",
- tm_funnel_tx.clone(),
- ),
- verif_reporter.clone(),
- event_request_rx,
- );
+ let mut event_handler = EventHandler::new(tm_funnel_tx.clone(), event_request_rx);
+
+ let (pus_test_tx, pus_test_rx) = mpsc::channel();
+ let (pus_event_tx, pus_event_rx) = mpsc::channel();
+ let (pus_sched_tx, pus_sched_rx) = mpsc::channel();
+ let (pus_hk_tx, pus_hk_rx) = mpsc::channel();
+ let (pus_action_tx, pus_action_rx) = mpsc::channel();
+ let (pus_mode_tx, pus_mode_rx) = mpsc::channel();
+
+ let (_pus_action_reply_tx, pus_action_reply_rx) = mpsc::channel();
+ let (pus_hk_reply_tx, pus_hk_reply_rx) = mpsc::channel();
+ let (pus_mode_reply_tx, pus_mode_reply_rx) = mpsc::channel();
- let (pus_test_tx, pus_test_rx) = channel();
- let (pus_event_tx, pus_event_rx) = channel();
- let (pus_sched_tx, pus_sched_rx) = channel();
- let (pus_hk_tx, pus_hk_rx) = channel();
- let (pus_action_tx, pus_action_rx) = channel();
let pus_router = PusTcMpscRouter {
- test_service_receiver: pus_test_tx,
- event_service_receiver: pus_event_tx,
- sched_service_receiver: pus_sched_tx,
- hk_service_receiver: pus_hk_tx,
- action_service_receiver: pus_action_tx,
+ test_tc_sender: pus_test_tx,
+ event_tc_sender: pus_event_tx,
+ sched_tc_sender: pus_sched_tx,
+ hk_tc_sender: pus_hk_tx,
+ action_tc_sender: pus_action_tx,
+ mode_tc_sender: pus_mode_tx,
};
let pus_test_service = create_test_service_dynamic(
tm_funnel_tx.clone(),
- verif_reporter.clone(),
event_handler.clone_event_sender(),
pus_test_rx,
);
let pus_scheduler_service = create_scheduler_service_dynamic(
tm_funnel_tx.clone(),
- verif_reporter.clone(),
tc_source.0.clone(),
pus_sched_rx,
create_sched_tc_pool(),
);
- let pus_event_service = create_event_service_dynamic(
- tm_funnel_tx.clone(),
- verif_reporter.clone(),
- pus_event_rx,
- event_request_tx,
- );
+ let pus_event_service =
+ create_event_service_dynamic(tm_funnel_tx.clone(), pus_event_rx, event_request_tx);
let pus_action_service = create_action_service_dynamic(
tm_funnel_tx.clone(),
- verif_reporter.clone(),
pus_action_rx,
request_map.clone(),
+ pus_action_reply_rx,
);
let pus_hk_service = create_hk_service_dynamic(
tm_funnel_tx.clone(),
- verif_reporter.clone(),
pus_hk_rx,
+ request_map.clone(),
+ pus_hk_reply_rx,
+ );
+ let pus_mode_service = create_mode_service_dynamic(
+ tm_funnel_tx.clone(),
+ pus_mode_rx,
request_map,
+ pus_mode_reply_rx,
);
let mut pus_stack = PusStack::new(
+ pus_test_service,
pus_hk_service,
pus_event_service,
pus_action_service,
pus_scheduler_service,
- pus_test_service,
+ pus_mode_service,
);
let ccsds_receiver = CcsdsReceiver { tc_source };
let mut tmtc_task = TcSourceTaskDynamic::new(
tc_source_rx,
- PusReceiver::new(verif_reporter.clone(), pus_router),
+ PusReceiver::new(tm_funnel_tx.clone(), pus_router),
);
let sock_addr = SocketAddr::new(IpAddr::V4(OBSW_SERVER_ADDR), SERVER_PORT);
@@ -413,20 +416,32 @@ fn dyn_tmtc_pool_main() {
tcp_server_cfg,
sync_tm_tcp_source.clone(),
tcp_ccsds_distributor,
+ PACKET_ID_VALIDATOR.clone(),
)
.expect("tcp server creation failed");
- let mut acs_task = AcsTask::new(
- TmAsVecSenderWithId::new(
- TmSenderId::AcsSubsystem as ChannelId,
- "ACS_TASK_SENDER",
- tm_funnel_tx.clone(),
- ),
- acs_thread_rx,
- verif_reporter,
- );
let mut tm_funnel = TmFunnelDynamic::new(sync_tm_tcp_source, tm_funnel_rx, tm_server_tx);
+ let (mgm_handler_mode_reply_to_parent_tx, _mgm_handler_mode_reply_to_parent_rx) =
+ mpsc::channel();
+ let dummy_spi_interface = SpiDummyInterface::default();
+ let shared_mgm_set = Arc::default();
+ let mode_leaf_interface = MpscModeLeafInterface {
+ request_rx: mgm_handler_mode_rx,
+ reply_tx_to_pus: pus_mode_reply_tx,
+ reply_tx_to_parent: mgm_handler_mode_reply_to_parent_tx,
+ };
+ let mut mgm_handler = MgmHandlerLis3Mdl::new(
+ MGM_HANDLER_0,
+ "MGM_0",
+ mode_leaf_interface,
+ mgm_handler_composite_rx,
+ pus_hk_reply_tx,
+ tm_funnel_tx,
+ dummy_spi_interface,
+ shared_mgm_set,
+ );
+
info!("Starting TMTC and UDP task");
let jh_udp_tmtc = thread::Builder::new()
.name("TMTC and UDP".to_string())
@@ -472,7 +487,7 @@ fn dyn_tmtc_pool_main() {
let jh_aocs = thread::Builder::new()
.name("AOCS".to_string())
.spawn(move || loop {
- acs_task.periodic_operation();
+ mgm_handler.periodic_operation();
thread::sleep(Duration::from_millis(FREQ_MS_AOCS));
})
.unwrap();
@@ -513,7 +528,7 @@ fn main() {
dyn_tmtc_pool_main();
}
-pub fn update_time(time_provider: &mut TimeProvider, timestamp: &mut [u8]) {
+pub fn update_time(time_provider: &mut CdsTime, timestamp: &mut [u8]) {
time_provider
.update_from_now()
.expect("Could not get current time");
diff --git a/satrs-example/src/pus/action.rs b/satrs-example/src/pus/action.rs
index ef23786..22b6b93 100644
--- a/satrs-example/src/pus/action.rs
+++ b/satrs-example/src/pus/action.rs
@@ -1,181 +1,274 @@
use log::{error, warn};
-use satrs::action::ActionRequest;
-use satrs::pool::{SharedStaticMemoryPool, StoreAddr};
-use satrs::pus::action::{PusActionToRequestConverter, PusService8ActionHandler};
-use satrs::pus::verification::std_mod::{
- VerificationReporterWithSharedPoolMpscBoundedSender, VerificationReporterWithVecMpscSender,
+use satrs::action::{ActionRequest, ActionRequestVariant};
+use satrs::params::WritableToBeBytes;
+use satrs::pool::SharedStaticMemoryPool;
+use satrs::pus::action::{
+ ActionReplyVariant, ActivePusActionRequestStd, DefaultActiveActionRequestMap, PusActionReply,
};
use satrs::pus::verification::{
- FailParams, TcStateAccepted, VerificationReportingProvider, VerificationToken,
+ FailParams, FailParamsWithStep, TcStateAccepted, TcStateStarted, VerificationReporter,
+ VerificationReportingProvider, VerificationToken,
};
use satrs::pus::{
- EcssTcAndToken, EcssTcInMemConverter, EcssTcInSharedStoreConverter, EcssTcInVecConverter,
- EcssTcReceiverCore, EcssTmSenderCore, MpscTcReceiver, PusPacketHandlerResult,
- PusPacketHandlingError, PusServiceHelper, TmAsVecSenderWithId, TmAsVecSenderWithMpsc,
- TmInSharedPoolSenderWithBoundedMpsc, TmInSharedPoolSenderWithId,
+ ActiveRequestProvider, EcssTcAndToken, EcssTcInMemConverter, EcssTcInSharedStoreConverter,
+ EcssTcInVecConverter, EcssTmSenderCore, EcssTmtcError, GenericConversionError, MpscTcReceiver,
+ MpscTmAsVecSender, MpscTmInSharedPoolSenderBounded, PusPacketHandlerResult, PusReplyHandler,
+ PusServiceHelper, PusTcToRequestConverter, PusTmAsVec, PusTmInPool, TmInSharedPoolSender,
};
-use satrs::request::TargetAndApidId;
+use satrs::request::{GenericMessage, UniqueApidTargetId};
use satrs::spacepackets::ecss::tc::PusTcReader;
-use satrs::spacepackets::ecss::PusPacket;
-use satrs::tmtc::tm_helper::SharedTmPool;
-use satrs::{ChannelId, TargetId};
-use satrs_example::config::{tmtc_err, TcReceiverId, TmSenderId, PUS_APID};
-use std::sync::mpsc::{self};
+use satrs::spacepackets::ecss::{EcssEnumU16, PusPacket};
+use satrs_example::config::components::PUS_ACTION_SERVICE;
+use satrs_example::config::tmtc_err;
+use std::sync::mpsc;
+use std::time::Duration;
use crate::requests::GenericRequestRouter;
-use super::GenericRoutingErrorHandler;
+use super::{
+ create_verification_reporter, generic_pus_request_timeout_handler, HandlingStatus,
+ PusTargetedRequestService, TargetedPusService,
+};
+
+pub struct ActionReplyHandler {
+ fail_data_buf: [u8; 128],
+}
+
+impl Default for ActionReplyHandler {
+ fn default() -> Self {
+ Self {
+ fail_data_buf: [0; 128],
+ }
+ }
+}
+
+impl PusReplyHandler for ActionReplyHandler {
+ type Error = EcssTmtcError;
+
+ fn handle_unrequested_reply(
+ &mut self,
+ reply: &GenericMessage,
+ _tm_sender: &impl EcssTmSenderCore,
+ ) -> Result<(), Self::Error> {
+ warn!("received unexpected reply for service 8: {reply:?}");
+ Ok(())
+ }
+
+ fn handle_reply(
+ &mut self,
+ reply: &GenericMessage,
+ active_request: &ActivePusActionRequestStd,
+ tm_sender: &(impl EcssTmSenderCore + ?Sized),
+ verification_handler: &impl VerificationReportingProvider,
+ time_stamp: &[u8],
+ ) -> Result {
+ let verif_token: VerificationToken = active_request
+ .token()
+ .try_into()
+ .expect("invalid token state");
+ let remove_entry = match &reply.message.variant {
+ ActionReplyVariant::CompletionFailed { error_code, params } => {
+ let mut fail_data_len = 0;
+ if let Some(params) = params {
+ fail_data_len = params.write_to_be_bytes(&mut self.fail_data_buf)?;
+ }
+ verification_handler.completion_failure(
+ tm_sender,
+ verif_token,
+ FailParams::new(time_stamp, error_code, &self.fail_data_buf[..fail_data_len]),
+ )?;
+ true
+ }
+ ActionReplyVariant::StepFailed {
+ error_code,
+ step,
+ params,
+ } => {
+ let mut fail_data_len = 0;
+ if let Some(params) = params {
+ fail_data_len = params.write_to_be_bytes(&mut self.fail_data_buf)?;
+ }
+ verification_handler.step_failure(
+ tm_sender,
+ verif_token,
+ FailParamsWithStep::new(
+ time_stamp,
+ &EcssEnumU16::new(*step),
+ error_code,
+ &self.fail_data_buf[..fail_data_len],
+ ),
+ )?;
+ true
+ }
+ ActionReplyVariant::Completed => {
+ verification_handler.completion_success(tm_sender, verif_token, time_stamp)?;
+ true
+ }
+ ActionReplyVariant::StepSuccess { step } => {
+ verification_handler.step_success(
+ tm_sender,
+ &verif_token,
+ time_stamp,
+ EcssEnumU16::new(*step),
+ )?;
+ false
+ }
+ _ => false,
+ };
+ Ok(remove_entry)
+ }
+
+ fn handle_request_timeout(
+ &mut self,
+ active_request: &ActivePusActionRequestStd,
+ tm_sender: &impl EcssTmSenderCore,
+ verification_handler: &impl VerificationReportingProvider,
+ time_stamp: &[u8],
+ ) -> Result<(), Self::Error> {
+ generic_pus_request_timeout_handler(
+ tm_sender,
+ active_request,
+ verification_handler,
+ time_stamp,
+ "action",
+ )
+ }
+}
#[derive(Default)]
-pub struct ExampleActionRequestConverter {}
+pub struct ActionRequestConverter {}
-impl PusActionToRequestConverter for ExampleActionRequestConverter {
- type Error = PusPacketHandlingError;
+impl PusTcToRequestConverter for ActionRequestConverter {
+ type Error = GenericConversionError;
fn convert(
&mut self,
token: VerificationToken,
tc: &PusTcReader,
- time_stamp: &[u8],
+ tm_sender: &(impl EcssTmSenderCore + ?Sized),
verif_reporter: &impl VerificationReportingProvider,
- ) -> Result<(TargetId, ActionRequest), Self::Error> {
+ time_stamp: &[u8],
+ ) -> Result<(ActivePusActionRequestStd, ActionRequest), Self::Error> {
let subservice = tc.subservice();
let user_data = tc.user_data();
if user_data.len() < 8 {
verif_reporter
.start_failure(
+ tm_sender,
token,
FailParams::new_no_fail_data(time_stamp, &tmtc_err::NOT_ENOUGH_APP_DATA),
)
.expect("Sending start failure failed");
- return Err(PusPacketHandlingError::NotEnoughAppData {
+ return Err(GenericConversionError::NotEnoughAppData {
expected: 8,
found: user_data.len(),
});
}
- let target_id = TargetAndApidId::from_pus_tc(tc).unwrap();
+ let target_id_and_apid = UniqueApidTargetId::from_pus_tc(tc).unwrap();
let action_id = u32::from_be_bytes(user_data[4..8].try_into().unwrap());
if subservice == 128 {
+ let req_variant = if user_data.len() == 8 {
+ ActionRequestVariant::NoData
+ } else {
+ ActionRequestVariant::VecData(user_data[8..].to_vec())
+ };
Ok((
- target_id.raw(),
- ActionRequest::UnsignedIdAndVecData {
+ ActivePusActionRequestStd::new(
action_id,
- data: user_data[8..].to_vec(),
- },
+ target_id_and_apid.into(),
+ token.into(),
+ Duration::from_secs(30),
+ ),
+ ActionRequest::new(action_id, req_variant),
))
} else {
verif_reporter
.start_failure(
+ tm_sender,
token,
FailParams::new_no_fail_data(time_stamp, &tmtc_err::INVALID_PUS_SUBSERVICE),
)
.expect("Sending start failure failed");
- Err(PusPacketHandlingError::InvalidSubservice(subservice))
+ Err(GenericConversionError::InvalidSubservice(subservice))
}
}
}
pub fn create_action_service_static(
- shared_tm_store: SharedTmPool,
- tm_funnel_tx: mpsc::SyncSender,
- verif_reporter: VerificationReporterWithSharedPoolMpscBoundedSender,
+ tm_sender: TmInSharedPoolSender>,
tc_pool: SharedStaticMemoryPool,
pus_action_rx: mpsc::Receiver,
action_router: GenericRequestRouter,
-) -> Pus8Wrapper<
- MpscTcReceiver,
- TmInSharedPoolSenderWithBoundedMpsc,
- EcssTcInSharedStoreConverter,
- VerificationReporterWithSharedPoolMpscBoundedSender,
-> {
- let action_srv_tm_sender = TmInSharedPoolSenderWithId::new(
- TmSenderId::PusAction as ChannelId,
- "PUS_8_TM_SENDER",
- shared_tm_store.clone(),
- tm_funnel_tx.clone(),
- );
- let action_srv_receiver = MpscTcReceiver::new(
- TcReceiverId::PusAction as ChannelId,
- "PUS_8_TC_RECV",
- pus_action_rx,
- );
- let pus_8_handler = PusService8ActionHandler::new(
+ reply_receiver: mpsc::Receiver>,
+) -> ActionServiceWrapper {
+ let action_request_handler = PusTargetedRequestService::new(
PusServiceHelper::new(
- action_srv_receiver,
- action_srv_tm_sender,
- PUS_APID,
- verif_reporter.clone(),
+ PUS_ACTION_SERVICE.id(),
+ pus_action_rx,
+ tm_sender,
+ create_verification_reporter(PUS_ACTION_SERVICE.id(), PUS_ACTION_SERVICE.apid),
EcssTcInSharedStoreConverter::new(tc_pool.clone(), 2048),
),
- ExampleActionRequestConverter::default(),
+ ActionRequestConverter::default(),
+ // TODO: Implementation which does not use run-time allocation? Maybe something like
+ // a bounded wrapper which pre-allocates using [HashMap::with_capacity]..
+ DefaultActiveActionRequestMap::default(),
+ ActionReplyHandler::default(),
action_router,
- GenericRoutingErrorHandler::<8>::default(),
+ reply_receiver,
);
- Pus8Wrapper { pus_8_handler }
+ ActionServiceWrapper {
+ service: action_request_handler,
+ }
}
pub fn create_action_service_dynamic(
- tm_funnel_tx: mpsc::Sender>,
- verif_reporter: VerificationReporterWithVecMpscSender,
+ tm_funnel_tx: mpsc::Sender,
pus_action_rx: mpsc::Receiver,
action_router: GenericRequestRouter,
-) -> Pus8Wrapper<
- MpscTcReceiver,
- TmAsVecSenderWithMpsc,
- EcssTcInVecConverter,
- VerificationReporterWithVecMpscSender,
-> {
- let action_srv_tm_sender = TmAsVecSenderWithId::new(
- TmSenderId::PusAction as ChannelId,
- "PUS_8_TM_SENDER",
- tm_funnel_tx.clone(),
- );
- let action_srv_receiver = MpscTcReceiver::new(
- TcReceiverId::PusAction as ChannelId,
- "PUS_8_TC_RECV",
- pus_action_rx,
- );
- let pus_8_handler = PusService8ActionHandler::new(
+ reply_receiver: mpsc::Receiver>,
+) -> ActionServiceWrapper {
+ let action_request_handler = PusTargetedRequestService::new(
PusServiceHelper::new(
- action_srv_receiver,
- action_srv_tm_sender,
- PUS_APID,
- verif_reporter.clone(),
+ PUS_ACTION_SERVICE.id(),
+ pus_action_rx,
+ tm_funnel_tx,
+ create_verification_reporter(PUS_ACTION_SERVICE.id(), PUS_ACTION_SERVICE.apid),
EcssTcInVecConverter::default(),
),
- ExampleActionRequestConverter::default(),
+ ActionRequestConverter::default(),
+ DefaultActiveActionRequestMap::default(),
+ ActionReplyHandler::default(),
action_router,
- GenericRoutingErrorHandler::<8>::default(),
+ reply_receiver,
);
- Pus8Wrapper { pus_8_handler }
+ ActionServiceWrapper {
+ service: action_request_handler,
+ }
}
-pub struct Pus8Wrapper<
- TcReceiver: EcssTcReceiverCore,
- TmSender: EcssTmSenderCore,
- TcInMemConverter: EcssTcInMemConverter,
- VerificationReporter: VerificationReportingProvider,
-> {
- pub(crate) pus_8_handler: PusService8ActionHandler<
- TcReceiver,
+pub struct ActionServiceWrapper
+{
+ pub(crate) service: PusTargetedRequestService<
+ MpscTcReceiver,
TmSender,
TcInMemConverter,
VerificationReporter,
- ExampleActionRequestConverter,
- GenericRequestRouter,
- GenericRoutingErrorHandler<8>,
+ ActionRequestConverter,
+ ActionReplyHandler,
+ DefaultActiveActionRequestMap,
+ ActivePusActionRequestStd,
+ ActionRequest,
+ PusActionReply,
>,
}
-impl<
- TcReceiver: EcssTcReceiverCore,
- TmSender: EcssTmSenderCore,
- TcInMemConverter: EcssTcInMemConverter,
- VerificationReporter: VerificationReportingProvider,
- > Pus8Wrapper
+impl TargetedPusService
+ for ActionServiceWrapper
{
- pub fn handle_next_packet(&mut self) -> bool {
- match self.pus_8_handler.handle_one_tc() {
+ /// Returns [true] if the packet handling is finished.
+ fn poll_and_handle_next_tc(&mut self, time_stamp: &[u8]) -> bool {
+ match self.service.poll_and_handle_next_tc(time_stamp) {
Ok(result) => match result {
PusPacketHandlerResult::RequestHandled => {}
PusPacketHandlerResult::RequestHandledPartialSuccess(e) => {
@@ -197,4 +290,463 @@ impl<
}
false
}
+
+ fn poll_and_handle_next_reply(&mut self, time_stamp: &[u8]) -> HandlingStatus {
+ // This only fails if all senders disconnected. Treat it like an empty queue.
+ self.service
+ .poll_and_check_next_reply(time_stamp)
+ .unwrap_or_else(|e| {
+ warn!("PUS 8: Handling reply failed with error {e:?}");
+ HandlingStatus::Empty
+ })
+ }
+
+ fn check_for_request_timeouts(&mut self) {
+ self.service.check_for_request_timeouts();
+ }
+}
+
+#[cfg(test)]
+mod tests {
+ use satrs::pus::test_util::{
+ TEST_APID, TEST_COMPONENT_ID_0, TEST_COMPONENT_ID_1, TEST_UNIQUE_ID_0, TEST_UNIQUE_ID_1,
+ };
+ use satrs::pus::verification;
+ use satrs::pus::verification::test_util::TestVerificationReporter;
+ use satrs::request::MessageMetadata;
+ use satrs::ComponentId;
+ use satrs::{
+ res_code::ResultU16,
+ spacepackets::{
+ ecss::{
+ tc::{PusTcCreator, PusTcSecondaryHeader},
+ tm::PusTmReader,
+ WritablePusPacket,
+ },
+ SpHeader,
+ },
+ };
+
+ use crate::{
+ pus::tests::{PusConverterTestbench, ReplyHandlerTestbench, TargetedPusRequestTestbench},
+ requests::CompositeRequest,
+ };
+
+ use super::*;
+
+ impl
+ TargetedPusRequestTestbench<
+ ActionRequestConverter,
+ ActionReplyHandler,
+ DefaultActiveActionRequestMap,
+ ActivePusActionRequestStd,
+ ActionRequest,
+ PusActionReply,
+ >
+ {
+ pub fn new_for_action(owner_id: ComponentId, target_id: ComponentId) -> Self {
+ let _ = env_logger::builder().is_test(true).try_init();
+ let (tm_funnel_tx, tm_funnel_rx) = mpsc::channel();
+ let (pus_action_tx, pus_action_rx) = mpsc::channel();
+ let (action_reply_tx, action_reply_rx) = mpsc::channel();
+ let (action_req_tx, action_req_rx) = mpsc::channel();
+ let verif_reporter = TestVerificationReporter::new(owner_id);
+ let mut generic_req_router = GenericRequestRouter::default();
+ generic_req_router
+ .composite_router_map
+ .insert(target_id, action_req_tx);
+ Self {
+ service: PusTargetedRequestService::new(
+ PusServiceHelper::new(
+ owner_id,
+ pus_action_rx,
+ tm_funnel_tx.clone(),
+ verif_reporter,
+ EcssTcInVecConverter::default(),
+ ),
+ ActionRequestConverter::default(),
+ DefaultActiveActionRequestMap::default(),
+ ActionReplyHandler::default(),
+ generic_req_router,
+ action_reply_rx,
+ ),
+ request_id: None,
+ pus_packet_tx: pus_action_tx,
+ tm_funnel_rx,
+ reply_tx: action_reply_tx,
+ request_rx: action_req_rx,
+ }
+ }
+
+ pub fn verify_packet_started(&self) {
+ self.service
+ .service_helper
+ .common
+ .verif_reporter
+ .check_next_is_started_success(
+ self.service.service_helper.id(),
+ self.request_id.expect("request ID not set").into(),
+ );
+ }
+
+ pub fn verify_packet_completed(&self) {
+ self.service
+ .service_helper
+ .common
+ .verif_reporter
+ .check_next_is_completion_success(
+ self.service.service_helper.id(),
+ self.request_id.expect("request ID not set").into(),
+ );
+ }
+
+ pub fn verify_tm_empty(&self) {
+ let packet = self.tm_funnel_rx.try_recv();
+ if let Err(mpsc::TryRecvError::Empty) = packet {
+ } else {
+ let tm = packet.unwrap();
+ let unexpected_tm = PusTmReader::new(&tm.packet, 7).unwrap().0;
+ panic!("unexpected TM packet {unexpected_tm:?}");
+ }
+ }
+
+ pub fn verify_next_tc_is_handled_properly(&mut self, time_stamp: &[u8]) {
+ let result = self.service.poll_and_handle_next_tc(time_stamp);
+ if let Err(e) = result {
+ panic!("unexpected error {:?}", e);
+ }
+ let result = result.unwrap();
+ match result {
+ PusPacketHandlerResult::RequestHandled => (),
+ _ => panic!("unexpected result {result:?}"),
+ }
+ }
+
+ pub fn verify_all_tcs_handled(&mut self, time_stamp: &[u8]) {
+ let result = self.service.poll_and_handle_next_tc(time_stamp);
+ if let Err(e) = result {
+ panic!("unexpected error {:?}", e);
+ }
+ let result = result.unwrap();
+ match result {
+ PusPacketHandlerResult::Empty => (),
+ _ => panic!("unexpected result {result:?}"),
+ }
+ }
+
+ pub fn verify_next_reply_is_handled_properly(&mut self, time_stamp: &[u8]) {
+ let result = self.service.poll_and_check_next_reply(time_stamp);
+ assert!(result.is_ok());
+ assert_eq!(result.unwrap(), HandlingStatus::HandledOne);
+ }
+
+ pub fn verify_all_replies_handled(&mut self, time_stamp: &[u8]) {
+ let result = self.service.poll_and_check_next_reply(time_stamp);
+ assert!(result.is_ok());
+ assert_eq!(result.unwrap(), HandlingStatus::Empty);
+ }
+
+ pub fn add_tc(&mut self, tc: &PusTcCreator) {
+ self.request_id = Some(verification::RequestId::new(tc).into());
+ let token = self.service.service_helper.verif_reporter_mut().add_tc(tc);
+ let accepted_token = self
+ .service
+ .service_helper
+ .verif_reporter()
+ .acceptance_success(self.service.service_helper.tm_sender(), token, &[0; 7])
+ .expect("TC acceptance failed");
+ self.service
+ .service_helper
+ .verif_reporter()
+ .check_next_was_added(accepted_token.request_id());
+ let id = self.service.service_helper.id();
+ self.service
+ .service_helper
+ .verif_reporter()
+ .check_next_is_acceptance_success(id, accepted_token.request_id());
+ self.pus_packet_tx
+ .send(EcssTcAndToken::new(tc.to_vec().unwrap(), accepted_token))
+ .unwrap();
+ }
+ }
+
+ #[test]
+ fn basic_request() {
+ let mut testbench = TargetedPusRequestTestbench::new_for_action(
+ TEST_COMPONENT_ID_0.id(),
+ TEST_COMPONENT_ID_1.id(),
+ );
+ // Create a basic action request and verify forwarding.
+ let sp_header = SpHeader::new_from_apid(TEST_APID);
+ let sec_header = PusTcSecondaryHeader::new_simple(8, 128);
+ let action_id = 5_u32;
+ let mut app_data: [u8; 8] = [0; 8];
+ app_data[0..4].copy_from_slice(&TEST_UNIQUE_ID_1.to_be_bytes());
+ app_data[4..8].copy_from_slice(&action_id.to_be_bytes());
+ let pus8_packet = PusTcCreator::new(sp_header, sec_header, &app_data, true);
+ testbench.add_tc(&pus8_packet);
+ let time_stamp: [u8; 7] = [0; 7];
+ testbench.verify_next_tc_is_handled_properly(&time_stamp);
+ testbench.verify_all_tcs_handled(&time_stamp);
+
+ testbench.verify_packet_started();
+
+ let possible_req = testbench.request_rx.try_recv();
+ assert!(possible_req.is_ok());
+ let req = possible_req.unwrap();
+ if let CompositeRequest::Action(action_req) = req.message {
+ assert_eq!(action_req.action_id, action_id);
+ assert_eq!(action_req.variant, ActionRequestVariant::NoData);
+ let action_reply = PusActionReply::new(action_id, ActionReplyVariant::Completed);
+ testbench
+ .reply_tx
+ .send(GenericMessage::new(req.requestor_info, action_reply))
+ .unwrap();
+ } else {
+ panic!("unexpected request type");
+ }
+ testbench.verify_next_reply_is_handled_properly(&time_stamp);
+ testbench.verify_all_replies_handled(&time_stamp);
+
+ testbench.verify_packet_completed();
+ testbench.verify_tm_empty();
+ }
+
+ #[test]
+ fn basic_request_routing_error() {
+ let mut testbench = TargetedPusRequestTestbench::new_for_action(
+ TEST_COMPONENT_ID_0.id(),
+ TEST_COMPONENT_ID_1.id(),
+ );
+ // Create a basic action request and verify forwarding.
+ let sec_header = PusTcSecondaryHeader::new_simple(8, 128);
+ let action_id = 5_u32;
+ let mut app_data: [u8; 8] = [0; 8];
+ // Invalid ID, routing should fail.
+ app_data[0..4].copy_from_slice(&0_u32.to_be_bytes());
+ app_data[4..8].copy_from_slice(&action_id.to_be_bytes());
+ let pus8_packet = PusTcCreator::new(
+ SpHeader::new_from_apid(TEST_APID),
+ sec_header,
+ &app_data,
+ true,
+ );
+ testbench.add_tc(&pus8_packet);
+ let time_stamp: [u8; 7] = [0; 7];
+
+ let result = testbench.service.poll_and_handle_next_tc(&time_stamp);
+ assert!(result.is_err());
+ // Verify the correct result and completion failure.
+ }
+
+ #[test]
+ fn converter_action_req_no_data() {
+ let mut testbench = PusConverterTestbench::new(
+ TEST_COMPONENT_ID_0.raw(),
+ ActionRequestConverter::default(),
+ );
+ let sec_header = PusTcSecondaryHeader::new_simple(8, 128);
+ let action_id = 5_u32;
+ let mut app_data: [u8; 8] = [0; 8];
+ // Invalid ID, routing should fail.
+ app_data[0..4].copy_from_slice(&TEST_UNIQUE_ID_0.to_be_bytes());
+ app_data[4..8].copy_from_slice(&action_id.to_be_bytes());
+ let pus8_packet = PusTcCreator::new(
+ SpHeader::new_from_apid(TEST_APID),
+ sec_header,
+ &app_data,
+ true,
+ );
+ let token = testbench.add_tc(&pus8_packet);
+ let result = testbench.convert(token, &[], TEST_APID, TEST_UNIQUE_ID_0);
+ assert!(result.is_ok());
+ let (active_req, request) = result.unwrap();
+ if let ActionRequestVariant::NoData = request.variant {
+ assert_eq!(request.action_id, action_id);
+ assert_eq!(active_req.action_id, action_id);
+ assert_eq!(
+ active_req.target_id(),
+ UniqueApidTargetId::new(TEST_APID, TEST_UNIQUE_ID_0).raw()
+ );
+ assert_eq!(
+ active_req.token().request_id(),
+ testbench.request_id().unwrap()
+ );
+ } else {
+ panic!("unexpected action request variant");
+ }
+ }
+
+ #[test]
+ fn converter_action_req_with_data() {
+ let mut testbench =
+ PusConverterTestbench::new(TEST_COMPONENT_ID_0.id(), ActionRequestConverter::default());
+ let sec_header = PusTcSecondaryHeader::new_simple(8, 128);
+ let action_id = 5_u32;
+ let mut app_data: [u8; 16] = [0; 16];
+ // Invalid ID, routing should fail.
+ app_data[0..4].copy_from_slice(&TEST_UNIQUE_ID_0.to_be_bytes());
+ app_data[4..8].copy_from_slice(&action_id.to_be_bytes());
+ for i in 0..8 {
+ app_data[i + 8] = i as u8;
+ }
+ let pus8_packet = PusTcCreator::new(
+ SpHeader::new_from_apid(TEST_APID),
+ sec_header,
+ &app_data,
+ true,
+ );
+ let token = testbench.add_tc(&pus8_packet);
+ let result = testbench.convert(token, &[], TEST_APID, TEST_UNIQUE_ID_0);
+ assert!(result.is_ok());
+ let (active_req, request) = result.unwrap();
+ if let ActionRequestVariant::VecData(vec) = request.variant {
+ assert_eq!(request.action_id, action_id);
+ assert_eq!(active_req.action_id, action_id);
+ assert_eq!(vec, app_data[8..].to_vec());
+ } else {
+ panic!("unexpected action request variant");
+ }
+ }
+
+ #[test]
+ fn reply_handling_completion_success() {
+ let mut testbench =
+ ReplyHandlerTestbench::new(TEST_COMPONENT_ID_0.id(), ActionReplyHandler::default());
+ let action_id = 5_u32;
+ let (req_id, active_req) = testbench.add_tc(TEST_APID, TEST_UNIQUE_ID_0, &[]);
+ let active_action_req =
+ ActivePusActionRequestStd::new_from_common_req(action_id, active_req);
+ let reply = PusActionReply::new(action_id, ActionReplyVariant::Completed);
+ let generic_reply = GenericMessage::new(MessageMetadata::new(req_id.into(), 0), reply);
+ let result = testbench.handle_reply(&generic_reply, &active_action_req, &[]);
+ assert!(result.is_ok());
+ assert!(result.unwrap());
+ testbench.verif_reporter.assert_full_completion_success(
+ TEST_COMPONENT_ID_0.id(),
+ req_id,
+ None,
+ );
+ }
+
+ #[test]
+ fn reply_handling_completion_failure() {
+ let mut testbench =
+ ReplyHandlerTestbench::new(TEST_COMPONENT_ID_0.id(), ActionReplyHandler::default());
+ let action_id = 5_u32;
+ let (req_id, active_req) = testbench.add_tc(TEST_APID, TEST_UNIQUE_ID_0, &[]);
+ let active_action_req =
+ ActivePusActionRequestStd::new_from_common_req(action_id, active_req);
+ let error_code = ResultU16::new(2, 3);
+ let reply = PusActionReply::new(
+ action_id,
+ ActionReplyVariant::CompletionFailed {
+ error_code,
+ params: None,
+ },
+ );
+ let generic_reply = GenericMessage::new(MessageMetadata::new(req_id.into(), 0), reply);
+ let result = testbench.handle_reply(&generic_reply, &active_action_req, &[]);
+ assert!(result.is_ok());
+ assert!(result.unwrap());
+ testbench.verif_reporter.assert_completion_failure(
+ TEST_COMPONENT_ID_0.into(),
+ req_id,
+ None,
+ error_code.raw() as u64,
+ );
+ }
+
+ #[test]
+ fn reply_handling_step_success() {
+ let mut testbench =
+ ReplyHandlerTestbench::new(TEST_COMPONENT_ID_0.id(), ActionReplyHandler::default());
+ let action_id = 5_u32;
+ let (req_id, active_req) = testbench.add_tc(TEST_APID, TEST_UNIQUE_ID_0, &[]);
+ let active_action_req =
+ ActivePusActionRequestStd::new_from_common_req(action_id, active_req);
+ let reply = PusActionReply::new(action_id, ActionReplyVariant::StepSuccess { step: 1 });
+ let generic_reply = GenericMessage::new(MessageMetadata::new(req_id.into(), 0), reply);
+ let result = testbench.handle_reply(&generic_reply, &active_action_req, &[]);
+ assert!(result.is_ok());
+ // Entry should not be removed, completion not done yet.
+ assert!(!result.unwrap());
+ testbench.verif_reporter.check_next_was_added(req_id);
+ testbench
+ .verif_reporter
+ .check_next_is_acceptance_success(TEST_COMPONENT_ID_0.raw(), req_id);
+ testbench
+ .verif_reporter
+ .check_next_is_started_success(TEST_COMPONENT_ID_0.raw(), req_id);
+ testbench
+ .verif_reporter
+ .check_next_is_step_success(TEST_COMPONENT_ID_0.raw(), req_id, 1);
+ }
+
+ #[test]
+ fn reply_handling_step_failure() {
+ let mut testbench =
+ ReplyHandlerTestbench::new(TEST_COMPONENT_ID_0.id(), ActionReplyHandler::default());
+ let action_id = 5_u32;
+ let (req_id, active_req) = testbench.add_tc(TEST_APID, TEST_UNIQUE_ID_0, &[]);
+ let active_action_req =
+ ActivePusActionRequestStd::new_from_common_req(action_id, active_req);
+ let error_code = ResultU16::new(2, 3);
+ let reply = PusActionReply::new(
+ action_id,
+ ActionReplyVariant::StepFailed {
+ error_code,
+ step: 1,
+ params: None,
+ },
+ );
+ let generic_reply = GenericMessage::new(MessageMetadata::new(req_id.into(), 0), reply);
+ let result = testbench.handle_reply(&generic_reply, &active_action_req, &[]);
+ assert!(result.is_ok());
+ assert!(result.unwrap());
+ testbench.verif_reporter.check_next_was_added(req_id);
+ testbench
+ .verif_reporter
+ .check_next_is_acceptance_success(TEST_COMPONENT_ID_0.id(), req_id);
+ testbench
+ .verif_reporter
+ .check_next_is_started_success(TEST_COMPONENT_ID_0.id(), req_id);
+ testbench.verif_reporter.check_next_is_step_failure(
+ TEST_COMPONENT_ID_0.id(),
+ req_id,
+ error_code.raw().into(),
+ );
+ }
+
+ #[test]
+ fn reply_handling_unrequested_reply() {
+ let mut testbench =
+ ReplyHandlerTestbench::new(TEST_COMPONENT_ID_0.id(), ActionReplyHandler::default());
+ let action_reply = PusActionReply::new(5_u32, ActionReplyVariant::Completed);
+ let unrequested_reply =
+ GenericMessage::new(MessageMetadata::new(10_u32, 15_u64), action_reply);
+ // Right now this function does not do a lot. We simply check that it does not panic or do
+ // weird stuff.
+ let result = testbench.handle_unrequested_reply(&unrequested_reply);
+ assert!(result.is_ok());
+ }
+
+ #[test]
+ fn reply_handling_reply_timeout() {
+ let mut testbench =
+ ReplyHandlerTestbench::new(TEST_COMPONENT_ID_0.id(), ActionReplyHandler::default());
+ let action_id = 5_u32;
+ let (req_id, active_request) = testbench.add_tc(TEST_APID, TEST_UNIQUE_ID_0, &[]);
+ let result = testbench.handle_request_timeout(
+ &ActivePusActionRequestStd::new_from_common_req(action_id, active_request),
+ &[],
+ );
+ assert!(result.is_ok());
+ testbench.verif_reporter.assert_completion_failure(
+ TEST_COMPONENT_ID_0.raw(),
+ req_id,
+ None,
+ tmtc_err::REQUEST_TIMEOUT.raw() as u64,
+ );
+ }
}
diff --git a/satrs-example/src/pus/event.rs b/satrs-example/src/pus/event.rs
index 1d16f5c..865b1f1 100644
--- a/satrs-example/src/pus/event.rs
+++ b/satrs-example/src/pus/event.rs
@@ -1,113 +1,69 @@
use std::sync::mpsc;
+use crate::pus::create_verification_reporter;
use log::{error, warn};
-use satrs::pool::{SharedStaticMemoryPool, StoreAddr};
+use satrs::pool::SharedStaticMemoryPool;
use satrs::pus::event_man::EventRequestWithToken;
-use satrs::pus::event_srv::PusService5EventHandler;
-use satrs::pus::verification::std_mod::{
- VerificationReporterWithSharedPoolMpscBoundedSender, VerificationReporterWithVecMpscSender,
-};
-use satrs::pus::verification::VerificationReportingProvider;
+use satrs::pus::event_srv::PusEventServiceHandler;
+use satrs::pus::verification::VerificationReporter;
use satrs::pus::{
EcssTcAndToken, EcssTcInMemConverter, EcssTcInSharedStoreConverter, EcssTcInVecConverter,
- EcssTcReceiverCore, EcssTmSenderCore, MpscTcReceiver, PusPacketHandlerResult, PusServiceHelper,
- TmAsVecSenderWithId, TmAsVecSenderWithMpsc, TmInSharedPoolSenderWithBoundedMpsc,
- TmInSharedPoolSenderWithId,
+ EcssTmSenderCore, MpscTcReceiver, MpscTmAsVecSender, MpscTmInSharedPoolSenderBounded,
+ PusPacketHandlerResult, PusServiceHelper, PusTmAsVec, PusTmInPool, TmInSharedPoolSender,
};
-use satrs::tmtc::tm_helper::SharedTmPool;
-use satrs::ChannelId;
-use satrs_example::config::{TcReceiverId, TmSenderId, PUS_APID};
+use satrs_example::config::components::PUS_EVENT_MANAGEMENT;
pub fn create_event_service_static(
- shared_tm_store: SharedTmPool,
- tm_funnel_tx: mpsc::SyncSender,
- verif_reporter: VerificationReporterWithSharedPoolMpscBoundedSender,
+ tm_sender: TmInSharedPoolSender>,
tc_pool: SharedStaticMemoryPool,
pus_event_rx: mpsc::Receiver,
event_request_tx: mpsc::Sender,
-) -> Pus5Wrapper<
- MpscTcReceiver,
- TmInSharedPoolSenderWithBoundedMpsc,
- EcssTcInSharedStoreConverter,
- VerificationReporterWithSharedPoolMpscBoundedSender,
-> {
- let event_srv_tm_sender = TmInSharedPoolSenderWithId::new(
- TmSenderId::PusEvent as ChannelId,
- "PUS_5_TM_SENDER",
- shared_tm_store.clone(),
- tm_funnel_tx.clone(),
- );
- let event_srv_receiver = MpscTcReceiver::new(
- TcReceiverId::PusEvent as ChannelId,
- "PUS_5_TC_RECV",
- pus_event_rx,
- );
- let pus_5_handler = PusService5EventHandler::new(
+) -> EventServiceWrapper {
+ let pus_5_handler = PusEventServiceHandler::new(
PusServiceHelper::new(
- event_srv_receiver,
- event_srv_tm_sender,
- PUS_APID,
- verif_reporter.clone(),
+ PUS_EVENT_MANAGEMENT.id(),
+ pus_event_rx,
+ tm_sender,
+ create_verification_reporter(PUS_EVENT_MANAGEMENT.id(), PUS_EVENT_MANAGEMENT.apid),
EcssTcInSharedStoreConverter::new(tc_pool.clone(), 2048),
),
event_request_tx,
);
- Pus5Wrapper { pus_5_handler }
+ EventServiceWrapper {
+ handler: pus_5_handler,
+ }
}
pub fn create_event_service_dynamic(
- tm_funnel_tx: mpsc::Sender>,
- verif_reporter: VerificationReporterWithVecMpscSender,
+ tm_funnel_tx: mpsc::Sender,
pus_event_rx: mpsc::Receiver,
event_request_tx: mpsc::Sender,
-) -> Pus5Wrapper<
- MpscTcReceiver,
- TmAsVecSenderWithMpsc,
- EcssTcInVecConverter,
- VerificationReporterWithVecMpscSender,
-> {
- let event_srv_tm_sender = TmAsVecSenderWithId::new(
- TmSenderId::PusEvent as ChannelId,
- "PUS_5_TM_SENDER",
- tm_funnel_tx,
- );
- let event_srv_receiver = MpscTcReceiver::new(
- TcReceiverId::PusEvent as ChannelId,
- "PUS_5_TC_RECV",
- pus_event_rx,
- );
- let pus_5_handler = PusService5EventHandler::new(
+) -> EventServiceWrapper {
+ let pus_5_handler = PusEventServiceHandler::new(
PusServiceHelper::new(
- event_srv_receiver,
- event_srv_tm_sender,
- PUS_APID,
- verif_reporter.clone(),
+ PUS_EVENT_MANAGEMENT.id(),
+ pus_event_rx,
+ tm_funnel_tx,
+ create_verification_reporter(PUS_EVENT_MANAGEMENT.id(), PUS_EVENT_MANAGEMENT.apid),
EcssTcInVecConverter::default(),
),
event_request_tx,
);
- Pus5Wrapper { pus_5_handler }
+ EventServiceWrapper {
+ handler: pus_5_handler,
+ }
}
-pub struct Pus5Wrapper<
- TcReceiver: EcssTcReceiverCore,
- TmSender: EcssTmSenderCore,
- TcInMemConverter: EcssTcInMemConverter,
- VerificationReporter: VerificationReportingProvider,
-> {
- pub pus_5_handler:
- PusService5EventHandler,
+pub struct EventServiceWrapper {
+ pub handler:
+ PusEventServiceHandler,
}
-impl<
- TcReceiver: EcssTcReceiverCore,
- TmSender: EcssTmSenderCore,
- TcInMemConverter: EcssTcInMemConverter,
- VerificationReporter: VerificationReportingProvider,
- > Pus5Wrapper
+impl
+ EventServiceWrapper
{
- pub fn handle_next_packet(&mut self) -> bool {
- match self.pus_5_handler.handle_one_tc() {
+ pub fn poll_and_handle_next_tc(&mut self, time_stamp: &[u8]) -> bool {
+ match self.handler.poll_and_handle_next_tc(time_stamp) {
Ok(result) => match result {
PusPacketHandlerResult::RequestHandled => {}
PusPacketHandlerResult::RequestHandledPartialSuccess(e) => {
diff --git a/satrs-example/src/pus/hk.rs b/satrs-example/src/pus/hk.rs
index 48a54be..cb3ebb9 100644
--- a/satrs-example/src/pus/hk.rs
+++ b/satrs-example/src/pus/hk.rs
@@ -1,50 +1,127 @@
+use derive_new::new;
use log::{error, warn};
-use satrs::hk::{CollectionIntervalFactor, HkRequest};
-use satrs::pool::{SharedStaticMemoryPool, StoreAddr};
-use satrs::pus::hk::{PusHkToRequestConverter, PusService3HkHandler};
-use satrs::pus::verification::std_mod::{
- VerificationReporterWithSharedPoolMpscBoundedSender, VerificationReporterWithVecMpscSender,
-};
+use satrs::hk::{CollectionIntervalFactor, HkRequest, HkRequestVariant, UniqueId};
+use satrs::pool::SharedStaticMemoryPool;
use satrs::pus::verification::{
- FailParams, TcStateAccepted, VerificationReportingProvider, VerificationToken,
+ FailParams, TcStateAccepted, TcStateStarted, VerificationReporter,
+ VerificationReportingProvider, VerificationToken,
};
use satrs::pus::{
- EcssTcAndToken, EcssTcInMemConverter, EcssTcInSharedStoreConverter, EcssTcInVecConverter,
- EcssTcReceiverCore, EcssTmSenderCore, MpscTcReceiver, PusPacketHandlerResult,
- PusPacketHandlingError, PusServiceHelper, TmAsVecSenderWithId, TmAsVecSenderWithMpsc,
- TmInSharedPoolSenderWithBoundedMpsc, TmInSharedPoolSenderWithId,
+ ActivePusRequestStd, ActiveRequestProvider, DefaultActiveRequestMap, EcssTcAndToken,
+ EcssTcInMemConverter, EcssTcInSharedStoreConverter, EcssTcInVecConverter, EcssTmSenderCore,
+ EcssTmtcError, GenericConversionError, MpscTcReceiver, MpscTmAsVecSender,
+ MpscTmInSharedPoolSenderBounded, PusPacketHandlerResult, PusReplyHandler, PusServiceHelper,
+ PusTcToRequestConverter, PusTmAsVec, PusTmInPool, TmInSharedPoolSender,
};
-use satrs::request::TargetAndApidId;
+use satrs::request::{GenericMessage, UniqueApidTargetId};
use satrs::spacepackets::ecss::tc::PusTcReader;
use satrs::spacepackets::ecss::{hk, PusPacket};
-use satrs::tmtc::tm_helper::SharedTmPool;
-use satrs::{ChannelId, TargetId};
-use satrs_example::config::{hk_err, tmtc_err, TcReceiverId, TmSenderId, PUS_APID};
-use std::sync::mpsc::{self};
+use satrs_example::config::components::PUS_HK_SERVICE;
+use satrs_example::config::{hk_err, tmtc_err};
+use std::sync::mpsc;
+use std::time::Duration;
+use crate::pus::{create_verification_reporter, generic_pus_request_timeout_handler};
use crate::requests::GenericRequestRouter;
-use super::GenericRoutingErrorHandler;
+use super::{HandlingStatus, PusTargetedRequestService};
+
+#[derive(Clone, PartialEq, Debug, new)]
+pub struct HkReply {
+ pub unique_id: UniqueId,
+ pub variant: HkReplyVariant,
+}
+
+#[derive(Clone, PartialEq, Debug)]
+pub enum HkReplyVariant {
+ Ack,
+}
#[derive(Default)]
-pub struct ExampleHkRequestConverter {}
+pub struct HkReplyHandler {}
-impl PusHkToRequestConverter for ExampleHkRequestConverter {
- type Error = PusPacketHandlingError;
+impl PusReplyHandler for HkReplyHandler {
+ type Error = EcssTmtcError;
+
+ fn handle_unrequested_reply(
+ &mut self,
+ reply: &GenericMessage,
+ _tm_sender: &impl EcssTmSenderCore,
+ ) -> Result<(), Self::Error> {
+ log::warn!("received unexpected reply for service 3: {reply:?}");
+ Ok(())
+ }
+
+ fn handle_reply(
+ &mut self,
+ reply: &GenericMessage,
+ active_request: &ActivePusRequestStd,
+ tm_sender: &impl EcssTmSenderCore,
+ verification_handler: &impl VerificationReportingProvider,
+ time_stamp: &[u8],
+ ) -> Result {
+ let started_token: VerificationToken = active_request
+ .token()
+ .try_into()
+ .expect("invalid token state");
+ match reply.message.variant {
+ HkReplyVariant::Ack => {
+ verification_handler
+ .completion_success(tm_sender, started_token, time_stamp)
+ .expect("sending completion success verification failed");
+ }
+ };
+ Ok(true)
+ }
+
+ fn handle_request_timeout(
+ &mut self,
+ active_request: &ActivePusRequestStd,
+ tm_sender: &impl EcssTmSenderCore,
+ verification_handler: &impl VerificationReportingProvider,
+ time_stamp: &[u8],
+ ) -> Result<(), Self::Error> {
+ generic_pus_request_timeout_handler(
+ tm_sender,
+ active_request,
+ verification_handler,
+ time_stamp,
+ "HK",
+ )?;
+ Ok(())
+ }
+}
+
+pub struct HkRequestConverter {
+ timeout: Duration,
+}
+
+impl Default for HkRequestConverter {
+ fn default() -> Self {
+ Self {
+ timeout: Duration::from_secs(60),
+ }
+ }
+}
+
+impl PusTcToRequestConverter for HkRequestConverter {
+ type Error = GenericConversionError;
fn convert(
&mut self,
token: VerificationToken,
tc: &PusTcReader,
- time_stamp: &[u8],
+ tm_sender: &(impl EcssTmSenderCore + ?Sized),
verif_reporter: &impl VerificationReportingProvider,
- ) -> Result<(TargetId, HkRequest), Self::Error> {
+ time_stamp: &[u8],
+ ) -> Result<(ActivePusRequestStd, HkRequest), Self::Error> {
let user_data = tc.user_data();
if user_data.is_empty() {
let user_data_len = user_data.len() as u32;
let user_data_len_raw = user_data_len.to_be_bytes();
verif_reporter
.start_failure(
+ tm_sender,
token,
FailParams::new(
time_stamp,
@@ -53,7 +130,7 @@ impl PusHkToRequestConverter for ExampleHkRequestConverter {
),
)
.expect("Sending start failure TM failed");
- return Err(PusPacketHandlingError::NotEnoughAppData {
+ return Err(GenericConversionError::NotEnoughAppData {
expected: 4,
found: 0,
});
@@ -67,178 +144,164 @@ impl PusHkToRequestConverter for ExampleHkRequestConverter {
let user_data_len = user_data.len() as u32;
let user_data_len_raw = user_data_len.to_be_bytes();
verif_reporter
- .start_failure(token, FailParams::new(time_stamp, err, &user_data_len_raw))
+ .start_failure(
+ tm_sender,
+ token,
+ FailParams::new(time_stamp, err, &user_data_len_raw),
+ )
.expect("Sending start failure TM failed");
- return Err(PusPacketHandlingError::NotEnoughAppData {
+ return Err(GenericConversionError::NotEnoughAppData {
expected: 8,
found: 4,
});
}
let subservice = tc.subservice();
- let target_id = TargetAndApidId::from_pus_tc(tc).expect("invalid tc format");
+ let target_id_and_apid = UniqueApidTargetId::from_pus_tc(tc).expect("invalid tc format");
let unique_id = u32::from_be_bytes(tc.user_data()[4..8].try_into().unwrap());
let standard_subservice = hk::Subservice::try_from(subservice);
if standard_subservice.is_err() {
verif_reporter
.start_failure(
+ tm_sender,
token,
FailParams::new(time_stamp, &tmtc_err::INVALID_PUS_SUBSERVICE, &[subservice]),
)
.expect("Sending start failure TM failed");
- return Err(PusPacketHandlingError::InvalidSubservice(subservice));
+ return Err(GenericConversionError::InvalidSubservice(subservice));
}
- Ok((
- target_id.into(),
- match standard_subservice.unwrap() {
- hk::Subservice::TcEnableHkGeneration | hk::Subservice::TcEnableDiagGeneration => {
- HkRequest::Enable(unique_id)
- }
- hk::Subservice::TcDisableHkGeneration | hk::Subservice::TcDisableDiagGeneration => {
- HkRequest::Disable(unique_id)
- }
- hk::Subservice::TcReportHkReportStructures => todo!(),
- hk::Subservice::TmHkPacket => todo!(),
- hk::Subservice::TcGenerateOneShotHk | hk::Subservice::TcGenerateOneShotDiag => {
- HkRequest::OneShot(unique_id)
- }
- hk::Subservice::TcModifyDiagCollectionInterval
- | hk::Subservice::TcModifyHkCollectionInterval => {
- if user_data.len() < 12 {
- verif_reporter
- .start_failure(
- token,
- FailParams::new_no_fail_data(
- time_stamp,
- &tmtc_err::NOT_ENOUGH_APP_DATA,
- ),
- )
- .expect("Sending start failure TM failed");
- return Err(PusPacketHandlingError::NotEnoughAppData {
- expected: 12,
- found: user_data.len(),
- });
- }
- HkRequest::ModifyCollectionInterval(
- unique_id,
- CollectionIntervalFactor::from_be_bytes(
- user_data[8..12].try_into().unwrap(),
- ),
- )
- }
- _ => {
+ let request = match standard_subservice.unwrap() {
+ hk::Subservice::TcEnableHkGeneration | hk::Subservice::TcEnableDiagGeneration => {
+ HkRequest::new(unique_id, HkRequestVariant::EnablePeriodic)
+ }
+ hk::Subservice::TcDisableHkGeneration | hk::Subservice::TcDisableDiagGeneration => {
+ HkRequest::new(unique_id, HkRequestVariant::DisablePeriodic)
+ }
+ hk::Subservice::TcReportHkReportStructures => todo!(),
+ hk::Subservice::TmHkPacket => todo!(),
+ hk::Subservice::TcGenerateOneShotHk | hk::Subservice::TcGenerateOneShotDiag => {
+ HkRequest::new(unique_id, HkRequestVariant::OneShot)
+ }
+ hk::Subservice::TcModifyDiagCollectionInterval
+ | hk::Subservice::TcModifyHkCollectionInterval => {
+ if user_data.len() < 12 {
verif_reporter
.start_failure(
+ tm_sender,
token,
- FailParams::new(
+ FailParams::new_no_fail_data(
time_stamp,
- &tmtc_err::PUS_SUBSERVICE_NOT_IMPLEMENTED,
- &[subservice],
+ &tmtc_err::NOT_ENOUGH_APP_DATA,
),
)
.expect("Sending start failure TM failed");
- return Err(PusPacketHandlingError::InvalidSubservice(subservice));
+ return Err(GenericConversionError::NotEnoughAppData {
+ expected: 12,
+ found: user_data.len(),
+ });
}
- },
+ HkRequest::new(
+ unique_id,
+ HkRequestVariant::ModifyCollectionInterval(
+ CollectionIntervalFactor::from_be_bytes(
+ user_data[8..12].try_into().unwrap(),
+ ),
+ ),
+ )
+ }
+ _ => {
+ verif_reporter
+ .start_failure(
+ tm_sender,
+ token,
+ FailParams::new(
+ time_stamp,
+ &tmtc_err::PUS_SUBSERVICE_NOT_IMPLEMENTED,
+ &[subservice],
+ ),
+ )
+ .expect("Sending start failure TM failed");
+ return Err(GenericConversionError::InvalidSubservice(subservice));
+ }
+ };
+ Ok((
+ ActivePusRequestStd::new(target_id_and_apid.into(), token, self.timeout),
+ request,
))
}
}
pub fn create_hk_service_static(
- shared_tm_store: SharedTmPool,
- tm_funnel_tx: mpsc::SyncSender,
- verif_reporter: VerificationReporterWithSharedPoolMpscBoundedSender,
+ tm_sender: TmInSharedPoolSender>,
tc_pool: SharedStaticMemoryPool,
pus_hk_rx: mpsc::Receiver,
request_router: GenericRequestRouter,
-) -> Pus3Wrapper<
- MpscTcReceiver,
- TmInSharedPoolSenderWithBoundedMpsc,
- EcssTcInSharedStoreConverter,
- VerificationReporterWithSharedPoolMpscBoundedSender,
-> {
- let hk_srv_tm_sender = TmInSharedPoolSenderWithId::new(
- TmSenderId::PusHk as ChannelId,
- "PUS_3_TM_SENDER",
- shared_tm_store.clone(),
- tm_funnel_tx.clone(),
- );
- let hk_srv_receiver =
- MpscTcReceiver::new(TcReceiverId::PusHk as ChannelId, "PUS_8_TC_RECV", pus_hk_rx);
- let pus_3_handler = PusService3HkHandler::new(
+ reply_receiver: mpsc::Receiver>,
+) -> HkServiceWrapper {
+ let pus_3_handler = PusTargetedRequestService::new(
PusServiceHelper::new(
- hk_srv_receiver,
- hk_srv_tm_sender,
- PUS_APID,
- verif_reporter.clone(),
+ PUS_HK_SERVICE.id(),
+ pus_hk_rx,
+ tm_sender,
+ create_verification_reporter(PUS_HK_SERVICE.id(), PUS_HK_SERVICE.apid),
EcssTcInSharedStoreConverter::new(tc_pool, 2048),
),
- ExampleHkRequestConverter::default(),
+ HkRequestConverter::default(),
+ DefaultActiveRequestMap::default(),
+ HkReplyHandler::default(),
request_router,
- GenericRoutingErrorHandler::default(),
+ reply_receiver,
);
- Pus3Wrapper { pus_3_handler }
+ HkServiceWrapper {
+ service: pus_3_handler,
+ }
}
pub fn create_hk_service_dynamic(
- tm_funnel_tx: mpsc::Sender>,
- verif_reporter: VerificationReporterWithVecMpscSender,
+ tm_funnel_tx: mpsc::Sender,
pus_hk_rx: mpsc::Receiver,
request_router: GenericRequestRouter,
-) -> Pus3Wrapper<
- MpscTcReceiver,
- TmAsVecSenderWithMpsc,
- EcssTcInVecConverter,
- VerificationReporterWithVecMpscSender,
-> {
- let hk_srv_tm_sender = TmAsVecSenderWithId::new(
- TmSenderId::PusHk as ChannelId,
- "PUS_3_TM_SENDER",
- tm_funnel_tx.clone(),
- );
- let hk_srv_receiver =
- MpscTcReceiver::new(TcReceiverId::PusHk as ChannelId, "PUS_8_TC_RECV", pus_hk_rx);
- let pus_3_handler = PusService3HkHandler::new(
+ reply_receiver: mpsc::Receiver>,
+) -> HkServiceWrapper {
+ let pus_3_handler = PusTargetedRequestService::new(
PusServiceHelper::new(
- hk_srv_receiver,
- hk_srv_tm_sender,
- PUS_APID,
- verif_reporter.clone(),
+ PUS_HK_SERVICE.id(),
+ pus_hk_rx,
+ tm_funnel_tx,
+ create_verification_reporter(PUS_HK_SERVICE.id(), PUS_HK_SERVICE.apid),
EcssTcInVecConverter::default(),
),
- ExampleHkRequestConverter::default(),
+ HkRequestConverter::default(),
+ DefaultActiveRequestMap::default(),
+ HkReplyHandler::default(),
request_router,
- GenericRoutingErrorHandler::default(),
+ reply_receiver,
);
- Pus3Wrapper { pus_3_handler }
+ HkServiceWrapper {
+ service: pus_3_handler,
+ }
}
-pub struct Pus3Wrapper<
- TcReceiver: EcssTcReceiverCore,
- TmSender: EcssTmSenderCore,
- TcInMemConverter: EcssTcInMemConverter,
- VerificationReporter: VerificationReportingProvider,
-> {
- pub(crate) pus_3_handler: PusService3HkHandler<
- TcReceiver,
+pub struct HkServiceWrapper {
+ pub(crate) service: PusTargetedRequestService<
+ MpscTcReceiver,
TmSender,
TcInMemConverter,
VerificationReporter,
- ExampleHkRequestConverter,
- GenericRequestRouter,
- GenericRoutingErrorHandler<3>,
+ HkRequestConverter,
+ HkReplyHandler,
+ DefaultActiveRequestMap,
+ ActivePusRequestStd,
+ HkRequest,
+ HkReply,
>,
}
-impl<
- TcReceiver: EcssTcReceiverCore,
- TmSender: EcssTmSenderCore,
- TcInMemConverter: EcssTcInMemConverter,
- VerificationReporter: VerificationReportingProvider,
- > Pus3Wrapper
+impl
+ HkServiceWrapper
{
- pub fn handle_next_packet(&mut self) -> bool {
- match self.pus_3_handler.handle_one_tc() {
+ pub fn poll_and_handle_next_tc(&mut self, time_stamp: &[u8]) -> bool {
+ match self.service.poll_and_handle_next_tc(time_stamp) {
Ok(result) => match result {
PusPacketHandlerResult::RequestHandled => {}
PusPacketHandlerResult::RequestHandledPartialSuccess(e) => {
@@ -260,4 +323,242 @@ impl<
}
false
}
+
+ pub fn poll_and_handle_next_reply(&mut self, time_stamp: &[u8]) -> HandlingStatus {
+ // This only fails if all senders disconnected. Treat it like an empty queue.
+ self.service
+ .poll_and_check_next_reply(time_stamp)
+ .unwrap_or_else(|e| {
+ warn!("PUS 3: Handling reply failed with error {e:?}");
+ HandlingStatus::Empty
+ })
+ }
+
+ pub fn check_for_request_timeouts(&mut self) {
+ self.service.check_for_request_timeouts();
+ }
+}
+
+#[cfg(test)]
+mod tests {
+ use satrs::pus::test_util::{
+ TEST_COMPONENT_ID_0, TEST_COMPONENT_ID_1, TEST_UNIQUE_ID_0, TEST_UNIQUE_ID_1,
+ };
+ use satrs::request::MessageMetadata;
+ use satrs::{
+ hk::HkRequestVariant,
+ pus::test_util::TEST_APID,
+ request::GenericMessage,
+ spacepackets::{
+ ecss::{hk::Subservice, tc::PusTcCreator},
+ SpHeader,
+ },
+ };
+ use satrs_example::config::tmtc_err;
+
+ use crate::pus::{
+ hk::HkReplyVariant,
+ tests::{PusConverterTestbench, ReplyHandlerTestbench},
+ };
+
+ use super::{HkReply, HkReplyHandler, HkRequestConverter};
+
+ #[test]
+ fn hk_converter_one_shot_req() {
+ let mut hk_bench =
+ PusConverterTestbench::new(TEST_COMPONENT_ID_0.id(), HkRequestConverter::default());
+ let sp_header = SpHeader::new_for_unseg_tc(TEST_APID, 0, 0);
+ let target_id = TEST_UNIQUE_ID_0;
+ let unique_id = 5_u32;
+ let mut app_data: [u8; 8] = [0; 8];
+ app_data[0..4].copy_from_slice(&target_id.to_be_bytes());
+ app_data[4..8].copy_from_slice(&unique_id.to_be_bytes());
+
+ let hk_req = PusTcCreator::new_simple(
+ sp_header,
+ 3,
+ Subservice::TcGenerateOneShotHk as u8,
+ &app_data,
+ true,
+ );
+ let accepted_token = hk_bench.add_tc(&hk_req);
+ let (_active_req, req) = hk_bench
+ .convert(accepted_token, &[], TEST_APID, TEST_UNIQUE_ID_0)
+ .expect("conversion failed");
+
+ assert_eq!(req.unique_id, unique_id);
+ if let HkRequestVariant::OneShot = req.variant {
+ } else {
+ panic!("unexpected HK request")
+ }
+ }
+
+ #[test]
+ fn hk_converter_enable_periodic_generation() {
+ let mut hk_bench =
+ PusConverterTestbench::new(TEST_COMPONENT_ID_0.id(), HkRequestConverter::default());
+ let sp_header = SpHeader::new_for_unseg_tc(TEST_APID, 0, 0);
+ let target_id = TEST_UNIQUE_ID_0;
+ let unique_id = 5_u32;
+ let mut app_data: [u8; 8] = [0; 8];
+ app_data[0..4].copy_from_slice(&target_id.to_be_bytes());
+ app_data[4..8].copy_from_slice(&unique_id.to_be_bytes());
+ let mut generic_check = |tc: &PusTcCreator| {
+ let accepted_token = hk_bench.add_tc(tc);
+ let (_active_req, req) = hk_bench
+ .convert(accepted_token, &[], TEST_APID, TEST_UNIQUE_ID_0)
+ .expect("conversion failed");
+ assert_eq!(req.unique_id, unique_id);
+ if let HkRequestVariant::EnablePeriodic = req.variant {
+ } else {
+ panic!("unexpected HK request")
+ }
+ };
+ let tc0 = PusTcCreator::new_simple(
+ sp_header,
+ 3,
+ Subservice::TcEnableHkGeneration as u8,
+ &app_data,
+ true,
+ );
+ generic_check(&tc0);
+ let tc1 = PusTcCreator::new_simple(
+ sp_header,
+ 3,
+ Subservice::TcEnableDiagGeneration as u8,
+ &app_data,
+ true,
+ );
+ generic_check(&tc1);
+ }
+
+ #[test]
+ fn hk_conversion_disable_periodic_generation() {
+ let mut hk_bench =
+ PusConverterTestbench::new(TEST_COMPONENT_ID_0.id(), HkRequestConverter::default());
+ let sp_header = SpHeader::new_for_unseg_tc(TEST_APID, 0, 0);
+ let target_id = TEST_UNIQUE_ID_0;
+ let unique_id = 5_u32;
+ let mut app_data: [u8; 8] = [0; 8];
+ app_data[0..4].copy_from_slice(&target_id.to_be_bytes());
+ app_data[4..8].copy_from_slice(&unique_id.to_be_bytes());
+ let mut generic_check = |tc: &PusTcCreator| {
+ let accepted_token = hk_bench.add_tc(tc);
+ let (_active_req, req) = hk_bench
+ .convert(accepted_token, &[], TEST_APID, TEST_UNIQUE_ID_0)
+ .expect("conversion failed");
+ assert_eq!(req.unique_id, unique_id);
+ if let HkRequestVariant::DisablePeriodic = req.variant {
+ } else {
+ panic!("unexpected HK request")
+ }
+ };
+ let tc0 = PusTcCreator::new_simple(
+ sp_header,
+ 3,
+ Subservice::TcDisableHkGeneration as u8,
+ &app_data,
+ true,
+ );
+ generic_check(&tc0);
+ let tc1 = PusTcCreator::new_simple(
+ sp_header,
+ 3,
+ Subservice::TcDisableDiagGeneration as u8,
+ &app_data,
+ true,
+ );
+ generic_check(&tc1);
+ }
+
+ #[test]
+ fn hk_conversion_modify_interval() {
+ let mut hk_bench =
+ PusConverterTestbench::new(TEST_COMPONENT_ID_0.id(), HkRequestConverter::default());
+ let sp_header = SpHeader::new_for_unseg_tc(TEST_APID, 0, 0);
+ let target_id = TEST_UNIQUE_ID_0;
+ let unique_id = 5_u32;
+ let mut app_data: [u8; 12] = [0; 12];
+ let collection_interval_factor = 5_u32;
+ app_data[0..4].copy_from_slice(&target_id.to_be_bytes());
+ app_data[4..8].copy_from_slice(&unique_id.to_be_bytes());
+ app_data[8..12].copy_from_slice(&collection_interval_factor.to_be_bytes());
+
+ let mut generic_check = |tc: &PusTcCreator| {
+ let accepted_token = hk_bench.add_tc(tc);
+ let (_active_req, req) = hk_bench
+ .convert(accepted_token, &[], TEST_APID, TEST_UNIQUE_ID_0)
+ .expect("conversion failed");
+ assert_eq!(req.unique_id, unique_id);
+ if let HkRequestVariant::ModifyCollectionInterval(interval_factor) = req.variant {
+ assert_eq!(interval_factor, collection_interval_factor);
+ } else {
+ panic!("unexpected HK request")
+ }
+ };
+ let tc0 = PusTcCreator::new_simple(
+ sp_header,
+ 3,
+ Subservice::TcModifyHkCollectionInterval as u8,
+ &app_data,
+ true,
+ );
+ generic_check(&tc0);
+ let tc1 = PusTcCreator::new_simple(
+ sp_header,
+ 3,
+ Subservice::TcModifyDiagCollectionInterval as u8,
+ &app_data,
+ true,
+ );
+ generic_check(&tc1);
+ }
+
+ #[test]
+ fn hk_reply_handler() {
+ let mut reply_testbench =
+ ReplyHandlerTestbench::new(TEST_COMPONENT_ID_0.id(), HkReplyHandler::default());
+ let sender_id = 2_u64;
+ let apid_target_id = 3_u32;
+ let unique_id = 5_u32;
+ let (req_id, active_req) = reply_testbench.add_tc(TEST_APID, apid_target_id, &[]);
+ let reply = GenericMessage::new(
+ MessageMetadata::new(req_id.into(), sender_id),
+ HkReply::new(unique_id, HkReplyVariant::Ack),
+ );
+ let result = reply_testbench.handle_reply(&reply, &active_req, &[]);
+ assert!(result.is_ok());
+ assert!(result.unwrap());
+ reply_testbench
+ .verif_reporter
+ .assert_full_completion_success(TEST_COMPONENT_ID_0.raw(), req_id, None);
+ }
+
+ #[test]
+ fn reply_handling_unrequested_reply() {
+ let mut testbench =
+ ReplyHandlerTestbench::new(TEST_COMPONENT_ID_1.id(), HkReplyHandler::default());
+ let action_reply = HkReply::new(5_u32, HkReplyVariant::Ack);
+ let unrequested_reply =
+ GenericMessage::new(MessageMetadata::new(10_u32, 15_u64), action_reply);
+ // Right now this function does not do a lot. We simply check that it does not panic or do
+ // weird stuff.
+ let result = testbench.handle_unrequested_reply(&unrequested_reply);
+ assert!(result.is_ok());
+ }
+
+ #[test]
+ fn reply_handling_reply_timeout() {
+ let mut testbench =
+ ReplyHandlerTestbench::new(TEST_COMPONENT_ID_1.id(), HkReplyHandler::default());
+ let (req_id, active_request) = testbench.add_tc(TEST_APID, TEST_UNIQUE_ID_1, &[]);
+ let result = testbench.handle_request_timeout(&active_request, &[]);
+ assert!(result.is_ok());
+ testbench.verif_reporter.assert_completion_failure(
+ TEST_COMPONENT_ID_1.raw(),
+ req_id,
+ None,
+ tmtc_err::REQUEST_TIMEOUT.raw() as u64,
+ );
+ }
}
diff --git a/satrs-example/src/pus/mod.rs b/satrs-example/src/pus/mod.rs
index 2b6c3ed..83bd34a 100644
--- a/satrs-example/src/pus/mod.rs
+++ b/satrs-example/src/pus/mod.rs
@@ -1,75 +1,80 @@
+use crate::requests::GenericRequestRouter;
use crate::tmtc::MpscStoreAndSendError;
use log::warn;
-use satrs::pus::verification::{FailParams, VerificationReportingProvider};
-use satrs::pus::{
- EcssTcAndToken, GenericRoutingError, PusPacketHandlerResult, PusRoutingErrorHandler, TcInMemory,
+use satrs::pus::verification::{
+ self, FailParams, TcStateAccepted, TcStateStarted, VerificationReporter,
+ VerificationReporterCfg, VerificationReportingProvider, VerificationToken,
};
+use satrs::pus::{
+ ActiveRequestMapProvider, ActiveRequestProvider, EcssTcAndToken, EcssTcInMemConverter,
+ EcssTcReceiverCore, EcssTmSenderCore, EcssTmtcError, GenericConversionError,
+ GenericRoutingError, PusPacketHandlerResult, PusPacketHandlingError, PusReplyHandler,
+ PusRequestRouter, PusServiceHelper, PusTcToRequestConverter, TcInMemory,
+};
+use satrs::queue::GenericReceiveError;
+use satrs::request::{Apid, GenericMessage, MessageMetadata};
use satrs::spacepackets::ecss::tc::PusTcReader;
use satrs::spacepackets::ecss::PusServiceId;
-use satrs::spacepackets::time::cds::TimeProvider;
-use satrs::spacepackets::time::TimeWriter;
+use satrs::ComponentId;
+use satrs_example::config::components::PUS_ROUTING_SERVICE;
use satrs_example::config::{tmtc_err, CustomPusServiceId};
-use std::sync::mpsc::Sender;
+use satrs_example::TimeStampHelper;
+use std::fmt::Debug;
+use std::sync::mpsc::{self, Sender};
pub mod action;
pub mod event;
pub mod hk;
+pub mod mode;
pub mod scheduler;
pub mod stack;
pub mod test;
-pub struct PusTcMpscRouter {
- pub test_service_receiver: Sender,
- pub event_service_receiver: Sender,
- pub sched_service_receiver: Sender,
- pub hk_service_receiver: Sender,
- pub action_service_receiver: Sender,
+#[derive(Debug, PartialEq, Eq, Copy, Clone)]
+pub enum HandlingStatus {
+ Empty,
+ HandledOne,
}
-pub struct PusReceiver {
+pub fn create_verification_reporter(owner_id: ComponentId, apid: Apid) -> VerificationReporter {
+ let verif_cfg = VerificationReporterCfg::new(apid, 1, 2, 8).unwrap();
+ // Every software component which needs to generate verification telemetry, gets a cloned
+ // verification reporter.
+ VerificationReporter::new(owner_id, &verif_cfg)
+}
+
+/// Simple router structure which forwards PUS telecommands to dedicated handlers.
+pub struct PusTcMpscRouter {
+ pub test_tc_sender: Sender,
+ pub event_tc_sender: Sender,
+ pub sched_tc_sender: Sender,
+ pub hk_tc_sender: Sender,
+ pub action_tc_sender: Sender,
+ pub mode_tc_sender: Sender,
+}
+
+pub struct PusReceiver {
+ pub id: ComponentId,
+ pub tm_sender: TmSender,
pub verif_reporter: VerificationReporter,
pub pus_router: PusTcMpscRouter,
stamp_helper: TimeStampHelper,
}
-struct TimeStampHelper {
- stamper: TimeProvider,
- time_stamp: [u8; 7],
-}
-
-impl TimeStampHelper {
- pub fn new() -> Self {
+impl PusReceiver {
+ pub fn new(tm_sender: TmSender, pus_router: PusTcMpscRouter) -> Self {
Self {
- stamper: TimeProvider::new_with_u16_days(0, 0),
- time_stamp: [0; 7],
- }
- }
-
- pub fn stamp(&self) -> &[u8] {
- &self.time_stamp
- }
-
- pub fn update_from_now(&mut self) {
- self.stamper
- .update_from_now()
- .expect("Updating timestamp failed");
- self.stamper
- .write_to_bytes(&mut self.time_stamp)
- .expect("Writing timestamp failed");
- }
-}
-
-impl PusReceiver {
- pub fn new(verif_reporter: VerificationReporter, pus_router: PusTcMpscRouter) -> Self {
- Self {
- verif_reporter,
+ id: PUS_ROUTING_SERVICE.raw(),
+ tm_sender,
+ verif_reporter: create_verification_reporter(
+ PUS_ROUTING_SERVICE.id(),
+ PUS_ROUTING_SERVICE.apid,
+ ),
pus_router,
- stamp_helper: TimeStampHelper::new(),
+ stamp_helper: TimeStampHelper::default(),
}
}
-}
-impl PusReceiver {
pub fn handle_tc_packet(
&mut self,
tc_in_memory: TcInMemory,
@@ -80,41 +85,34 @@ impl PusReceiver match standard_service {
- PusServiceId::Test => {
- self.pus_router.test_service_receiver.send(EcssTcAndToken {
- tc_in_memory,
- token: Some(accepted_token.into()),
- })?
- }
+ PusServiceId::Test => self.pus_router.test_tc_sender.send(EcssTcAndToken {
+ tc_in_memory,
+ token: Some(accepted_token.into()),
+ })?,
PusServiceId::Housekeeping => {
- self.pus_router.hk_service_receiver.send(EcssTcAndToken {
+ self.pus_router.hk_tc_sender.send(EcssTcAndToken {
tc_in_memory,
token: Some(accepted_token.into()),
})?
}
- PusServiceId::Event => {
- self.pus_router
- .event_service_receiver
- .send(EcssTcAndToken {
- tc_in_memory,
- token: Some(accepted_token.into()),
- })?
- }
+ PusServiceId::Event => self.pus_router.event_tc_sender.send(EcssTcAndToken {
+ tc_in_memory,
+ token: Some(accepted_token.into()),
+ })?,
PusServiceId::Scheduling => {
- self.pus_router
- .sched_service_receiver
- .send(EcssTcAndToken {
- tc_in_memory,
- token: Some(accepted_token.into()),
- })?
+ self.pus_router.sched_tc_sender.send(EcssTcAndToken {
+ tc_in_memory,
+ token: Some(accepted_token.into()),
+ })?
}
_ => {
let result = self.verif_reporter.start_failure(
+ &self.tm_sender,
accepted_token,
FailParams::new(
self.stamp_helper.stamp(),
@@ -131,14 +129,17 @@ impl PusReceiver {
- // TODO: Fix mode service.
- //self.handle_mode_service(pus_tc, accepted_token)
+ self.pus_router.mode_tc_sender.send(EcssTcAndToken {
+ tc_in_memory,
+ token: Some(accepted_token.into()),
+ })?
}
CustomPusServiceId::Health => {}
}
} else {
self.verif_reporter
.start_failure(
+ &self.tm_sender,
accepted_token,
FailParams::new(
self.stamp_helper.stamp(),
@@ -154,55 +155,550 @@ impl PusReceiver {}
+pub trait TargetedPusService {
+ /// Returns [true] if the packet handling is finished.
+ fn poll_and_handle_next_tc(&mut self, time_stamp: &[u8]) -> bool;
+ fn poll_and_handle_next_reply(&mut self, time_stamp: &[u8]) -> HandlingStatus;
+ fn check_for_request_timeouts(&mut self);
+}
-impl PusRoutingErrorHandler for GenericRoutingErrorHandler {
- type Error = satrs::pus::GenericRoutingError;
+/// This is a generic handler class for all PUS services where a PUS telecommand is converted
+/// to a targeted request.
+///
+/// The generic steps for this process are the following
+///
+/// 1. Poll for TC packets
+/// 2. Convert the raw packets to a [PusTcReader].
+/// 3. Convert the PUS TC to a typed request using the [PusTcToRequestConverter].
+/// 4. Route the requests using the [GenericRequestRouter].
+/// 5. Add the request to the active request map using the [ActiveRequestMapProvider] abstraction.
+/// 6. Check for replies which complete the forwarded request. The handler takes care of
+/// the verification process.
+/// 7. Check for timeouts of active requests. Generally, the timeout on the service level should
+/// be highest expected timeout for the given target.
+///
+/// The handler exposes the following API:
+///
+/// 1. [Self::handle_one_tc] which tries to poll and handle one TC packet, covering steps 1-5.
+/// 2. [Self::check_one_reply] which tries to poll and handle one reply, covering step 6.
+/// 3. [Self::check_for_request_timeouts] which checks for request timeouts, covering step 7.
+pub struct PusTargetedRequestService<
+ TcReceiver: EcssTcReceiverCore,
+ TmSender: EcssTmSenderCore,
+ TcInMemConverter: EcssTcInMemConverter,
+ VerificationReporter: VerificationReportingProvider,
+ RequestConverter: PusTcToRequestConverter,
+ ReplyHandler: PusReplyHandler,
+ ActiveRequestMap: ActiveRequestMapProvider,
+ ActiveRequestInfo: ActiveRequestProvider,
+ RequestType,
+ ReplyType,
+> {
+ pub service_helper:
+ PusServiceHelper,
+ pub request_router: GenericRequestRouter,
+ pub request_converter: RequestConverter,
+ pub active_request_map: ActiveRequestMap,
+ pub reply_handler: ReplyHandler,
+ pub reply_receiver: mpsc::Receiver>,
+ phantom: std::marker::PhantomData<(RequestType, ActiveRequestInfo, ReplyType)>,
+}
- fn handle_error(
- &self,
- target_id: satrs::TargetId,
- token: satrs::pus::verification::VerificationToken<
- satrs::pus::verification::TcStateAccepted,
+impl<
+ TcReceiver: EcssTcReceiverCore,
+ TmSender: EcssTmSenderCore,
+ TcInMemConverter: EcssTcInMemConverter,
+ VerificationReporter: VerificationReportingProvider,
+ RequestConverter: PusTcToRequestConverter,
+ ReplyHandler: PusReplyHandler,
+ ActiveRequestMap: ActiveRequestMapProvider,
+ ActiveRequestInfo: ActiveRequestProvider,
+ RequestType,
+ ReplyType,
+ >
+ PusTargetedRequestService<
+ TcReceiver,
+ TmSender,
+ TcInMemConverter,
+ VerificationReporter,
+ RequestConverter,
+ ReplyHandler,
+ ActiveRequestMap,
+ ActiveRequestInfo,
+ RequestType,
+ ReplyType,
+ >
+where
+ GenericRequestRouter: PusRequestRouter,
+{
+ pub fn new(
+ service_helper: PusServiceHelper<
+ TcReceiver,
+ TmSender,
+ TcInMemConverter,
+ VerificationReporter,
>,
- _tc: &PusTcReader,
- error: Self::Error,
+ request_converter: RequestConverter,
+ active_request_map: ActiveRequestMap,
+ reply_hook: ReplyHandler,
+ request_router: GenericRequestRouter,
+ reply_receiver: mpsc::Receiver>,
+ ) -> Self {
+ Self {
+ service_helper,
+ request_converter,
+ active_request_map,
+ reply_handler: reply_hook,
+ request_router,
+ reply_receiver,
+ phantom: std::marker::PhantomData,
+ }
+ }
+
+ pub fn poll_and_handle_next_tc(
+ &mut self,
+ time_stamp: &[u8],
+ ) -> Result {
+ let possible_packet = self.service_helper.retrieve_and_accept_next_packet()?;
+ if possible_packet.is_none() {
+ return Ok(PusPacketHandlerResult::Empty);
+ }
+ let ecss_tc_and_token = possible_packet.unwrap();
+ self.service_helper
+ .tc_in_mem_converter_mut()
+ .cache(&ecss_tc_and_token.tc_in_memory)?;
+ let tc = self.service_helper.tc_in_mem_converter().convert()?;
+ let (mut request_info, request) = match self.request_converter.convert(
+ ecss_tc_and_token.token,
+ &tc,
+ self.service_helper.tm_sender(),
+ &self.service_helper.common.verif_reporter,
+ time_stamp,
+ ) {
+ Ok((info, req)) => (info, req),
+ Err(e) => {
+ self.handle_conversion_to_request_error(&e, ecss_tc_and_token.token, time_stamp);
+ return Err(e.into());
+ }
+ };
+ let accepted_token: VerificationToken = request_info
+ .token()
+ .try_into()
+ .expect("token not in expected accepted state");
+ let verif_request_id = verification::RequestId::new(&tc).raw();
+ match self.request_router.route(
+ MessageMetadata::new(verif_request_id, self.service_helper.id()),
+ request_info.target_id(),
+ request,
+ ) {
+ Ok(()) => {
+ let started_token = self
+ .service_helper
+ .verif_reporter()
+ .start_success(
+ &self.service_helper.common.tm_sender,
+ accepted_token,
+ time_stamp,
+ )
+ .expect("Start success failure");
+ request_info.set_token(started_token.into());
+ self.active_request_map
+ .insert(&verif_request_id, request_info);
+ }
+ Err(e) => {
+ self.request_router.handle_error_generic(
+ &request_info,
+ &tc,
+ e.clone(),
+ self.service_helper.tm_sender(),
+ self.service_helper.verif_reporter(),
+ time_stamp,
+ );
+ return Err(e.into());
+ }
+ }
+ Ok(PusPacketHandlerResult::RequestHandled)
+ }
+
+ fn handle_conversion_to_request_error(
+ &mut self,
+ error: &GenericConversionError,
+ token: VerificationToken,
time_stamp: &[u8],
- verif_reporter: &impl VerificationReportingProvider,
) {
- warn!("Routing request for service {SERVICE_ID} failed: {error:?}");
match error {
- GenericRoutingError::UnknownTargetId(id) => {
- let mut fail_data: [u8; 8] = [0; 8];
- fail_data.copy_from_slice(&id.to_be_bytes());
- verif_reporter
- .start_failure(
+ GenericConversionError::WrongService(service) => {
+ let service_slice: [u8; 1] = [*service];
+ self.service_helper
+ .verif_reporter()
+ .completion_failure(
+ self.service_helper.tm_sender(),
token,
- FailParams::new(time_stamp, &tmtc_err::UNKNOWN_TARGET_ID, &fail_data),
+ FailParams::new(time_stamp, &tmtc_err::INVALID_PUS_SERVICE, &service_slice),
)
- .expect("Sending start failure failed");
+ .expect("Sending completion failure failed");
}
- GenericRoutingError::SendError(_) => {
- let mut fail_data: [u8; 8] = [0; 8];
- fail_data.copy_from_slice(&target_id.to_be_bytes());
- verif_reporter
- .start_failure(
+ GenericConversionError::InvalidSubservice(subservice) => {
+ let subservice_slice: [u8; 1] = [*subservice];
+ self.service_helper
+ .verif_reporter()
+ .completion_failure(
+ self.service_helper.tm_sender(),
token,
- FailParams::new(time_stamp, &tmtc_err::ROUTING_ERROR, &fail_data),
+ FailParams::new(
+ time_stamp,
+ &tmtc_err::INVALID_PUS_SUBSERVICE,
+ &subservice_slice,
+ ),
)
- .expect("Sending start failure failed");
+ .expect("Sending completion failure failed");
}
- GenericRoutingError::NotEnoughAppData { expected, found } => {
- let mut context_info = (found as u32).to_be_bytes().to_vec();
- context_info.extend_from_slice(&(expected as u32).to_be_bytes());
- verif_reporter
- .start_failure(
+ GenericConversionError::NotEnoughAppData { expected, found } => {
+ let mut context_info = (*found as u32).to_be_bytes().to_vec();
+ context_info.extend_from_slice(&(*expected as u32).to_be_bytes());
+ self.service_helper
+ .verif_reporter()
+ .completion_failure(
+ self.service_helper.tm_sender(),
token,
FailParams::new(time_stamp, &tmtc_err::NOT_ENOUGH_APP_DATA, &context_info),
)
- .expect("Sending start failure failed");
+ .expect("Sending completion failure failed");
+ }
+ // Do nothing.. this is service-level and can not be handled generically here.
+ GenericConversionError::InvalidAppData(_) => (),
+ }
+ }
+
+ pub fn poll_and_check_next_reply(
+ &mut self,
+ time_stamp: &[u8],
+ ) -> Result {
+ match self.reply_receiver.try_recv() {
+ Ok(reply) => {
+ self.handle_reply(&reply, time_stamp)?;
+ Ok(HandlingStatus::HandledOne)
+ }
+ Err(e) => match e {
+ mpsc::TryRecvError::Empty => Ok(HandlingStatus::Empty),
+ mpsc::TryRecvError::Disconnected => Err(EcssTmtcError::Receive(
+ GenericReceiveError::TxDisconnected(None),
+ )),
+ },
+ }
+ }
+
+ pub fn handle_reply(
+ &mut self,
+ reply: &GenericMessage,
+ time_stamp: &[u8],
+ ) -> Result<(), EcssTmtcError> {
+ let active_req_opt = self.active_request_map.get(reply.request_id());
+ if active_req_opt.is_none() {
+ self.reply_handler
+ .handle_unrequested_reply(reply, &self.service_helper.common.tm_sender)?;
+ return Ok(());
+ }
+ let active_request = active_req_opt.unwrap();
+ let request_finished = self
+ .reply_handler
+ .handle_reply(
+ reply,
+ active_request,
+ &self.service_helper.common.tm_sender,
+ &self.service_helper.common.verif_reporter,
+ time_stamp,
+ )
+ .unwrap_or(false);
+ if request_finished {
+ self.active_request_map.remove(reply.request_id());
+ }
+ Ok(())
+ }
+
+ pub fn check_for_request_timeouts(&mut self) {
+ let mut requests_to_delete = Vec::new();
+ self.active_request_map
+ .for_each(|request_id, request_info| {
+ if request_info.has_timed_out() {
+ requests_to_delete.push(*request_id);
+ }
+ });
+ if !requests_to_delete.is_empty() {
+ for request_id in requests_to_delete {
+ self.active_request_map.remove(request_id);
}
}
}
}
+
+/// Generic timeout handling: Handle the verification failure with a dedicated return code
+/// and also log the error.
+pub fn generic_pus_request_timeout_handler(
+ sender: &(impl EcssTmSenderCore + ?Sized),
+ active_request: &(impl ActiveRequestProvider + Debug),
+ verification_handler: &impl VerificationReportingProvider,
+ time_stamp: &[u8],
+ service_str: &'static str,
+) -> Result<(), EcssTmtcError> {
+ log::warn!("timeout for active request {active_request:?} on {service_str} service");
+ let started_token: VerificationToken = active_request
+ .token()
+ .try_into()
+ .expect("token not in expected started state");
+ verification_handler.completion_failure(
+ sender,
+ started_token,
+ FailParams::new(time_stamp, &tmtc_err::REQUEST_TIMEOUT, &[]),
+ )?;
+ Ok(())
+}
+
+#[cfg(test)]
+pub(crate) mod tests {
+ use std::time::Duration;
+
+ use satrs::pus::test_util::TEST_COMPONENT_ID_0;
+ use satrs::pus::{MpscTmAsVecSender, PusTmAsVec, PusTmVariant};
+ use satrs::request::RequestId;
+ use satrs::{
+ pus::{
+ verification::test_util::TestVerificationReporter, ActivePusRequestStd,
+ ActiveRequestMapProvider, EcssTcInVecConverter, MpscTcReceiver,
+ },
+ request::UniqueApidTargetId,
+ spacepackets::{
+ ecss::{
+ tc::{PusTcCreator, PusTcSecondaryHeader},
+ WritablePusPacket,
+ },
+ SpHeader,
+ },
+ };
+
+ use crate::requests::CompositeRequest;
+
+ use super::*;
+
+ // Testbench dedicated to the testing of [PusReplyHandler]s
+ pub struct ReplyHandlerTestbench<
+ ReplyHandler: PusReplyHandler,
+ ActiveRequestInfo: ActiveRequestProvider,
+ Reply,
+ > {
+ pub id: ComponentId,
+ pub verif_reporter: TestVerificationReporter,
+ pub reply_handler: ReplyHandler,
+ pub tm_receiver: mpsc::Receiver,
+ pub default_timeout: Duration,
+ tm_sender: MpscTmAsVecSender,
+ phantom: std::marker::PhantomData<(ActiveRequestInfo, Reply)>,
+ }
+
+ impl<
+ ReplyHandler: PusReplyHandler,
+ ActiveRequestInfo: ActiveRequestProvider,
+ Reply,
+ > ReplyHandlerTestbench
+ {
+ pub fn new(owner_id: ComponentId, reply_handler: ReplyHandler) -> Self {
+ let test_verif_reporter = TestVerificationReporter::new(owner_id);
+ let (tm_sender, tm_receiver) = mpsc::channel();
+ Self {
+ id: TEST_COMPONENT_ID_0.raw(),
+ verif_reporter: test_verif_reporter,
+ reply_handler,
+ default_timeout: Duration::from_secs(30),
+ tm_sender,
+ tm_receiver,
+ phantom: std::marker::PhantomData,
+ }
+ }
+
+ pub fn add_tc(
+ &mut self,
+ apid: u16,
+ apid_target: u32,
+ time_stamp: &[u8],
+ ) -> (verification::RequestId, ActivePusRequestStd) {
+ let sp_header = SpHeader::new_from_apid(apid);
+ let sec_header_dummy = PusTcSecondaryHeader::new_simple(0, 0);
+ let init = self.verif_reporter.add_tc(&PusTcCreator::new(
+ sp_header,
+ sec_header_dummy,
+ &[],
+ true,
+ ));
+ let accepted = self
+ .verif_reporter
+ .acceptance_success(&self.tm_sender, init, time_stamp)
+ .expect("acceptance failed");
+ let started = self
+ .verif_reporter
+ .start_success(&self.tm_sender, accepted, time_stamp)
+ .expect("start failed");
+ (
+ started.request_id(),
+ ActivePusRequestStd::new(
+ UniqueApidTargetId::new(apid, apid_target).raw(),
+ started,
+ self.default_timeout,
+ ),
+ )
+ }
+
+ pub fn handle_reply(
+ &mut self,
+ reply: &GenericMessage,
+ active_request: &ActiveRequestInfo,
+ time_stamp: &[u8],
+ ) -> Result {
+ self.reply_handler.handle_reply(
+ reply,
+ active_request,
+ &self.tm_sender,
+ &self.verif_reporter,
+ time_stamp,
+ )
+ }
+
+ pub fn handle_unrequested_reply(
+ &mut self,
+ reply: &GenericMessage,
+ ) -> Result<(), ReplyHandler::Error> {
+ self.reply_handler
+ .handle_unrequested_reply(reply, &self.tm_sender)
+ }
+ pub fn handle_request_timeout(
+ &mut self,
+ active_request_info: &ActiveRequestInfo,
+ time_stamp: &[u8],
+ ) -> Result<(), ReplyHandler::Error> {
+ self.reply_handler.handle_request_timeout(
+ active_request_info,
+ &self.tm_sender,
+ &self.verif_reporter,
+ time_stamp,
+ )
+ }
+ }
+
+ #[derive(Default)]
+ pub struct DummySender {}
+
+ /// Dummy sender component which does nothing on the [Self::send_tm] call.
+ ///
+ /// Useful for unit tests.
+ impl EcssTmSenderCore for DummySender {
+ fn send_tm(&self, _source_id: ComponentId, _tm: PusTmVariant) -> Result<(), EcssTmtcError> {
+ Ok(())
+ }
+ }
+
+ // Testbench dedicated to the testing of [PusTcToRequestConverter]s
+ pub struct PusConverterTestbench<
+ Converter: PusTcToRequestConverter,
+ ActiveRequestInfo: ActiveRequestProvider,
+ Request,
+ > {
+ pub id: ComponentId,
+ pub verif_reporter: TestVerificationReporter,
+ pub converter: Converter,
+ dummy_sender: DummySender,
+ current_request_id: Option,
+ current_packet: Option>,
+ phantom: std::marker::PhantomData<(ActiveRequestInfo, Request)>,
+ }
+
+ impl<
+ Converter: PusTcToRequestConverter,
+ ActiveRequestInfo: ActiveRequestProvider,
+ Request,
+ > PusConverterTestbench
+ {
+ pub fn new(owner_id: ComponentId, converter: Converter) -> Self {
+ let test_verif_reporter = TestVerificationReporter::new(owner_id);
+ Self {
+ id: owner_id,
+ verif_reporter: test_verif_reporter,
+ converter,
+ dummy_sender: DummySender::default(),
+ current_request_id: None,
+ current_packet: None,
+ phantom: std::marker::PhantomData,
+ }
+ }
+
+ pub fn add_tc(&mut self, tc: &PusTcCreator) -> VerificationToken {
+ let token = self.verif_reporter.add_tc(tc);
+ self.current_request_id = Some(verification::RequestId::new(tc));
+ self.current_packet = Some(tc.to_vec().unwrap());
+ self.verif_reporter
+ .acceptance_success(&self.dummy_sender, token, &[])
+ .expect("acceptance failed")
+ }
+
+ pub fn request_id(&self) -> Option {
+ self.current_request_id
+ }
+
+ pub fn convert(
+ &mut self,
+ token: VerificationToken,
+ time_stamp: &[u8],
+ expected_apid: u16,
+ expected_apid_target: u32,
+ ) -> Result<(ActiveRequestInfo, Request), Converter::Error> {
+ if self.current_packet.is_none() {
+ return Err(GenericConversionError::InvalidAppData(
+ "call add_tc first".to_string(),
+ ));
+ }
+ let current_packet = self.current_packet.take().unwrap();
+ let tc_reader = PusTcReader::new(¤t_packet).unwrap();
+ let (active_info, request) = self.converter.convert(
+ token,
+ &tc_reader.0,
+ &self.dummy_sender,
+ &self.verif_reporter,
+ time_stamp,
+ )?;
+ assert_eq!(
+ active_info.token().request_id(),
+ self.request_id().expect("no request id is set")
+ );
+ assert_eq!(
+ active_info.target_id(),
+ UniqueApidTargetId::new(expected_apid, expected_apid_target).raw()
+ );
+ Ok((active_info, request))
+ }
+ }
+
+ pub struct TargetedPusRequestTestbench<
+ RequestConverter: PusTcToRequestConverter,
+ ReplyHandler: PusReplyHandler,
+ ActiveRequestMap: ActiveRequestMapProvider,
+ ActiveRequestInfo: ActiveRequestProvider,
+ RequestType,
+ ReplyType,
+ > {
+ pub service: PusTargetedRequestService<
+ MpscTcReceiver,
+ MpscTmAsVecSender,
+ EcssTcInVecConverter,
+ TestVerificationReporter,
+ RequestConverter,
+ ReplyHandler,
+ ActiveRequestMap,
+ ActiveRequestInfo,
+ RequestType,
+ ReplyType,
+ >,
+ pub request_id: Option,
+ pub tm_funnel_rx: mpsc::Receiver,
+ pub pus_packet_tx: mpsc::Sender,
+ pub reply_tx: mpsc::Sender>,
+ pub request_rx: mpsc::Receiver>,
+ }
+}
diff --git a/satrs-example/src/pus/mode.rs b/satrs-example/src/pus/mode.rs
new file mode 100644
index 0000000..4f2ff13
--- /dev/null
+++ b/satrs-example/src/pus/mode.rs
@@ -0,0 +1,434 @@
+use derive_new::new;
+use log::{error, warn};
+use std::sync::mpsc;
+use std::time::Duration;
+
+use crate::requests::GenericRequestRouter;
+use satrs::pool::SharedStaticMemoryPool;
+use satrs::pus::verification::VerificationReporter;
+use satrs::pus::{
+ DefaultActiveRequestMap, EcssTcAndToken, EcssTcInMemConverter, EcssTcInSharedStoreConverter,
+ EcssTcInVecConverter, MpscTcReceiver, MpscTmAsVecSender, MpscTmInSharedPoolSenderBounded,
+ PusPacketHandlerResult, PusServiceHelper, PusTmAsVec, PusTmInPool, TmInSharedPoolSender,
+};
+use satrs::request::GenericMessage;
+use satrs::{
+ mode::{ModeAndSubmode, ModeReply, ModeRequest},
+ pus::{
+ mode::Subservice,
+ verification::{
+ self, FailParams, TcStateAccepted, TcStateStarted, VerificationReportingProvider,
+ VerificationToken,
+ },
+ ActivePusRequestStd, ActiveRequestProvider, EcssTmSenderCore, EcssTmtcError,
+ GenericConversionError, PusReplyHandler, PusTcToRequestConverter, PusTmVariant,
+ },
+ request::UniqueApidTargetId,
+ spacepackets::{
+ ecss::{
+ tc::PusTcReader,
+ tm::{PusTmCreator, PusTmSecondaryHeader},
+ PusPacket,
+ },
+ SpHeader,
+ },
+ ComponentId,
+};
+use satrs_example::config::components::PUS_MODE_SERVICE;
+use satrs_example::config::{mode_err, tmtc_err};
+
+use super::{
+ create_verification_reporter, generic_pus_request_timeout_handler, HandlingStatus,
+ PusTargetedRequestService, TargetedPusService,
+};
+
+#[derive(new)]
+pub struct ModeReplyHandler {
+ owner_id: ComponentId,
+}
+
+impl PusReplyHandler for ModeReplyHandler {
+ type Error = EcssTmtcError;
+
+ fn handle_unrequested_reply(
+ &mut self,
+ reply: &GenericMessage,
+ _tm_sender: &impl EcssTmSenderCore,
+ ) -> Result<(), Self::Error> {
+ log::warn!("received unexpected reply for mode service 5: {reply:?}");
+ Ok(())
+ }
+
+ fn handle_reply(
+ &mut self,
+ reply: &GenericMessage,
+ active_request: &ActivePusRequestStd,
+ tm_sender: &impl EcssTmSenderCore,
+ verification_handler: &impl VerificationReportingProvider,
+ time_stamp: &[u8],
+ ) -> Result {
+ let started_token: VerificationToken = active_request
+ .token()
+ .try_into()
+ .expect("invalid token state");
+ match reply.message {
+ ModeReply::ModeReply(mode_reply) => {
+ let mut source_data: [u8; 12] = [0; 12];
+ mode_reply
+ .write_to_be_bytes(&mut source_data)
+ .expect("writing mode reply failed");
+ let req_id = verification::RequestId::from(reply.request_id());
+ let sp_header = SpHeader::new_for_unseg_tm(req_id.packet_id().apid(), 0, 0);
+ let sec_header =
+ PusTmSecondaryHeader::new(200, Subservice::TmModeReply as u8, 0, 0, time_stamp);
+ let pus_tm = PusTmCreator::new(sp_header, sec_header, &source_data, true);
+ tm_sender.send_tm(self.owner_id, PusTmVariant::Direct(pus_tm))?;
+ verification_handler.completion_success(tm_sender, started_token, time_stamp)?;
+ }
+ ModeReply::CantReachMode(error_code) => {
+ verification_handler.completion_failure(
+ tm_sender,
+ started_token,
+ FailParams::new(time_stamp, &error_code, &[]),
+ )?;
+ }
+ ModeReply::WrongMode { expected, reached } => {
+ let mut error_info: [u8; 24] = [0; 24];
+ let mut written_len = expected
+ .write_to_be_bytes(&mut error_info[0..ModeAndSubmode::RAW_LEN])
+ .expect("writing expected mode failed");
+ written_len += reached
+ .write_to_be_bytes(&mut error_info[ModeAndSubmode::RAW_LEN..])
+ .expect("writing reached mode failed");
+ verification_handler.completion_failure(
+ tm_sender,
+ started_token,
+ FailParams::new(
+ time_stamp,
+ &mode_err::WRONG_MODE,
+ &error_info[..written_len],
+ ),
+ )?;
+ }
+ };
+ Ok(true)
+ }
+
+ fn handle_request_timeout(
+ &mut self,
+ active_request: &ActivePusRequestStd,
+ tm_sender: &impl EcssTmSenderCore,
+ verification_handler: &impl VerificationReportingProvider,
+ time_stamp: &[u8],
+ ) -> Result<(), Self::Error> {
+ generic_pus_request_timeout_handler(
+ tm_sender,
+ active_request,
+ verification_handler,
+ time_stamp,
+ "HK",
+ )?;
+ Ok(())
+ }
+}
+
+#[derive(Default)]
+pub struct ModeRequestConverter {}
+
+impl PusTcToRequestConverter for ModeRequestConverter {
+ type Error = GenericConversionError;
+
+ fn convert(
+ &mut self,
+ token: VerificationToken,
+ tc: &PusTcReader,
+ tm_sender: &(impl EcssTmSenderCore + ?Sized),
+ verif_reporter: &impl VerificationReportingProvider,
+ time_stamp: &[u8],
+ ) -> Result<(ActivePusRequestStd, ModeRequest), Self::Error> {
+ let subservice = tc.subservice();
+ let user_data = tc.user_data();
+ let not_enough_app_data = |expected: usize| {
+ verif_reporter
+ .start_failure(
+ tm_sender,
+ token,
+ FailParams::new_no_fail_data(time_stamp, &tmtc_err::NOT_ENOUGH_APP_DATA),
+ )
+ .expect("Sending start failure failed");
+ Err(GenericConversionError::NotEnoughAppData {
+ expected,
+ found: user_data.len(),
+ })
+ };
+ if user_data.len() < core::mem::size_of::() {
+ return not_enough_app_data(4);
+ }
+ let target_id_and_apid = UniqueApidTargetId::from_pus_tc(tc).unwrap();
+ let active_request =
+ ActivePusRequestStd::new(target_id_and_apid.into(), token, Duration::from_secs(30));
+ let subservice_typed = Subservice::try_from(subservice);
+ let invalid_subservice = || {
+ // Invalid subservice
+ verif_reporter
+ .start_failure(
+ tm_sender,
+ token,
+ FailParams::new_no_fail_data(time_stamp, &tmtc_err::INVALID_PUS_SUBSERVICE),
+ )
+ .expect("Sending start failure failed");
+ Err(GenericConversionError::InvalidSubservice(subservice))
+ };
+ if subservice_typed.is_err() {
+ return invalid_subservice();
+ }
+ let subservice_typed = subservice_typed.unwrap();
+ match subservice_typed {
+ Subservice::TcSetMode => {
+ if user_data.len() < core::mem::size_of::() + ModeAndSubmode::RAW_LEN {
+ return not_enough_app_data(4 + ModeAndSubmode::RAW_LEN);
+ }
+ let mode_and_submode = ModeAndSubmode::from_be_bytes(&tc.user_data()[4..])
+ .expect("mode and submode extraction failed");
+ Ok((active_request, ModeRequest::SetMode(mode_and_submode)))
+ }
+ Subservice::TcReadMode => Ok((active_request, ModeRequest::ReadMode)),
+ Subservice::TcAnnounceMode => Ok((active_request, ModeRequest::AnnounceMode)),
+ Subservice::TcAnnounceModeRecursive => {
+ Ok((active_request, ModeRequest::AnnounceModeRecursive))
+ }
+ _ => invalid_subservice(),
+ }
+ }
+}
+
+pub fn create_mode_service_static(
+ tm_sender: TmInSharedPoolSender>,
+ tc_pool: SharedStaticMemoryPool,
+ pus_action_rx: mpsc::Receiver,
+ mode_router: GenericRequestRouter,
+ reply_receiver: mpsc::Receiver>,
+) -> ModeServiceWrapper {
+ let mode_request_handler = PusTargetedRequestService::new(
+ PusServiceHelper::new(
+ PUS_MODE_SERVICE.id(),
+ pus_action_rx,
+ tm_sender,
+ create_verification_reporter(PUS_MODE_SERVICE.id(), PUS_MODE_SERVICE.apid),
+ EcssTcInSharedStoreConverter::new(tc_pool, 2048),
+ ),
+ ModeRequestConverter::default(),
+ DefaultActiveRequestMap::default(),
+ ModeReplyHandler::new(PUS_MODE_SERVICE.id()),
+ mode_router,
+ reply_receiver,
+ );
+ ModeServiceWrapper {
+ service: mode_request_handler,
+ }
+}
+
+pub fn create_mode_service_dynamic(
+ tm_funnel_tx: mpsc::Sender,
+ pus_action_rx: mpsc::Receiver,
+ mode_router: GenericRequestRouter,
+ reply_receiver: mpsc::Receiver>,
+) -> ModeServiceWrapper {
+ let mode_request_handler = PusTargetedRequestService::new(
+ PusServiceHelper::new(
+ PUS_MODE_SERVICE.id(),
+ pus_action_rx,
+ tm_funnel_tx,
+ create_verification_reporter(PUS_MODE_SERVICE.id(), PUS_MODE_SERVICE.apid),
+ EcssTcInVecConverter::default(),
+ ),
+ ModeRequestConverter::default(),
+ DefaultActiveRequestMap::default(),
+ ModeReplyHandler::new(PUS_MODE_SERVICE.id()),
+ mode_router,
+ reply_receiver,
+ );
+ ModeServiceWrapper {
+ service: mode_request_handler,
+ }
+}
+
+pub struct ModeServiceWrapper {
+ pub(crate) service: PusTargetedRequestService<
+ MpscTcReceiver,
+ TmSender,
+ TcInMemConverter,
+ VerificationReporter,
+ ModeRequestConverter,
+ ModeReplyHandler,
+ DefaultActiveRequestMap,
+ ActivePusRequestStd,
+ ModeRequest,
+ ModeReply,
+ >,
+}
+
+impl TargetedPusService
+ for ModeServiceWrapper
+{
+ /// Returns [true] if the packet handling is finished.
+ fn poll_and_handle_next_tc(&mut self, time_stamp: &[u8]) -> bool {
+ match self.service.poll_and_handle_next_tc(time_stamp) {
+ Ok(result) => match result {
+ PusPacketHandlerResult::RequestHandled => {}
+ PusPacketHandlerResult::RequestHandledPartialSuccess(e) => {
+ warn!("PUS mode service: partial packet handling success: {e:?}")
+ }
+ PusPacketHandlerResult::CustomSubservice(invalid, _) => {
+ warn!("PUS mode service: invalid subservice {invalid}");
+ }
+ PusPacketHandlerResult::SubserviceNotImplemented(subservice, _) => {
+ warn!("PUS mode service: {subservice} not implemented");
+ }
+ PusPacketHandlerResult::Empty => {
+ return true;
+ }
+ },
+ Err(error) => {
+ error!("PUS mode service: packet handling error: {error:?}")
+ }
+ }
+ false
+ }
+
+ fn poll_and_handle_next_reply(&mut self, time_stamp: &[u8]) -> HandlingStatus {
+ self.service
+ .poll_and_check_next_reply(time_stamp)
+ .unwrap_or_else(|e| {
+ warn!("PUS action service: Handling reply failed with error {e:?}");
+ HandlingStatus::HandledOne
+ })
+ }
+
+ fn check_for_request_timeouts(&mut self) {
+ self.service.check_for_request_timeouts();
+ }
+}
+#[cfg(test)]
+mod tests {
+ use satrs::pus::test_util::{TEST_APID, TEST_COMPONENT_ID_0, TEST_UNIQUE_ID_0};
+ use satrs::request::MessageMetadata;
+ use satrs::{
+ mode::{ModeAndSubmode, ModeReply, ModeRequest},
+ pus::mode::Subservice,
+ request::GenericMessage,
+ spacepackets::{
+ ecss::tc::{PusTcCreator, PusTcSecondaryHeader},
+ SpHeader,
+ },
+ };
+ use satrs_example::config::tmtc_err;
+
+ use crate::pus::{
+ mode::ModeReplyHandler,
+ tests::{PusConverterTestbench, ReplyHandlerTestbench},
+ };
+
+ use super::ModeRequestConverter;
+
+ #[test]
+ fn mode_converter_read_mode_request() {
+ let mut testbench =
+ PusConverterTestbench::new(TEST_COMPONENT_ID_0.id(), ModeRequestConverter::default());
+ let sp_header = SpHeader::new_for_unseg_tc(TEST_APID, 0, 0);
+ let sec_header = PusTcSecondaryHeader::new_simple(200, Subservice::TcReadMode as u8);
+ let mut app_data: [u8; 4] = [0; 4];
+ app_data[0..4].copy_from_slice(&TEST_UNIQUE_ID_0.to_be_bytes());
+ let tc = PusTcCreator::new(sp_header, sec_header, &app_data, true);
+ let token = testbench.add_tc(&tc);
+ let (_active_req, req) = testbench
+ .convert(token, &[], TEST_APID, TEST_UNIQUE_ID_0)
+ .expect("conversion has failed");
+ assert_eq!(req, ModeRequest::ReadMode);
+ }
+
+ #[test]
+ fn mode_converter_set_mode_request() {
+ let mut testbench =
+ PusConverterTestbench::new(TEST_COMPONENT_ID_0.id(), ModeRequestConverter::default());
+ let sp_header = SpHeader::new_for_unseg_tc(TEST_APID, 0, 0);
+ let sec_header = PusTcSecondaryHeader::new_simple(200, Subservice::TcSetMode as u8);
+ let mut app_data: [u8; 4 + ModeAndSubmode::RAW_LEN] = [0; 4 + ModeAndSubmode::RAW_LEN];
+ let mode_and_submode = ModeAndSubmode::new(2, 1);
+ app_data[0..4].copy_from_slice(&TEST_UNIQUE_ID_0.to_be_bytes());
+ mode_and_submode
+ .write_to_be_bytes(&mut app_data[4..])
+ .unwrap();
+ let tc = PusTcCreator::new(sp_header, sec_header, &app_data, true);
+ let token = testbench.add_tc(&tc);
+ let (_active_req, req) = testbench
+ .convert(token, &[], TEST_APID, TEST_UNIQUE_ID_0)
+ .expect("conversion has failed");
+ assert_eq!(req, ModeRequest::SetMode(mode_and_submode));
+ }
+
+ #[test]
+ fn mode_converter_announce_mode() {
+ let mut testbench =
+ PusConverterTestbench::new(TEST_COMPONENT_ID_0.id(), ModeRequestConverter::default());
+ let sp_header = SpHeader::new_for_unseg_tc(TEST_APID, 0, 0);
+ let sec_header = PusTcSecondaryHeader::new_simple(200, Subservice::TcAnnounceMode as u8);
+ let mut app_data: [u8; 4] = [0; 4];
+ app_data[0..4].copy_from_slice(&TEST_UNIQUE_ID_0.to_be_bytes());
+ let tc = PusTcCreator::new(sp_header, sec_header, &app_data, true);
+ let token = testbench.add_tc(&tc);
+ let (_active_req, req) = testbench
+ .convert(token, &[], TEST_APID, TEST_UNIQUE_ID_0)
+ .expect("conversion has failed");
+ assert_eq!(req, ModeRequest::AnnounceMode);
+ }
+
+ #[test]
+ fn mode_converter_announce_mode_recursively() {
+ let mut testbench =
+ PusConverterTestbench::new(TEST_COMPONENT_ID_0.id(), ModeRequestConverter::default());
+ let sp_header = SpHeader::new_for_unseg_tc(TEST_APID, 0, 0);
+ let sec_header =
+ PusTcSecondaryHeader::new_simple(200, Subservice::TcAnnounceModeRecursive as u8);
+ let mut app_data: [u8; 4] = [0; 4];
+ app_data[0..4].copy_from_slice(&TEST_UNIQUE_ID_0.to_be_bytes());
+ let tc = PusTcCreator::new(sp_header, sec_header, &app_data, true);
+ let token = testbench.add_tc(&tc);
+ let (_active_req, req) = testbench
+ .convert(token, &[], TEST_APID, TEST_UNIQUE_ID_0)
+ .expect("conversion has failed");
+ assert_eq!(req, ModeRequest::AnnounceModeRecursive);
+ }
+
+ #[test]
+ fn reply_handling_unrequested_reply() {
+ let mut testbench = ReplyHandlerTestbench::new(
+ TEST_COMPONENT_ID_0.id(),
+ ModeReplyHandler::new(TEST_COMPONENT_ID_0.id()),
+ );
+ let mode_reply = ModeReply::ModeReply(ModeAndSubmode::new(5, 1));
+ let unrequested_reply =
+ GenericMessage::new(MessageMetadata::new(10_u32, 15_u64), mode_reply);
+ // Right now this function does not do a lot. We simply check that it does not panic or do
+ // weird stuff.
+ let result = testbench.handle_unrequested_reply(&unrequested_reply);
+ assert!(result.is_ok());
+ }
+
+ #[test]
+ fn reply_handling_reply_timeout() {
+ let mut testbench = ReplyHandlerTestbench::new(
+ TEST_COMPONENT_ID_0.id(),
+ ModeReplyHandler::new(TEST_COMPONENT_ID_0.id()),
+ );
+ let (req_id, active_request) = testbench.add_tc(TEST_APID, TEST_UNIQUE_ID_0, &[]);
+ let result = testbench.handle_request_timeout(&active_request, &[]);
+ assert!(result.is_ok());
+ testbench.verif_reporter.assert_completion_failure(
+ TEST_COMPONENT_ID_0.raw(),
+ req_id,
+ None,
+ tmtc_err::REQUEST_TIMEOUT.raw() as u64,
+ );
+ }
+}
diff --git a/satrs-example/src/pus/scheduler.rs b/satrs-example/src/pus/scheduler.rs
index c5d2c06..d75c666 100644
--- a/satrs-example/src/pus/scheduler.rs
+++ b/satrs-example/src/pus/scheduler.rs
@@ -1,23 +1,18 @@
use std::sync::mpsc;
use std::time::Duration;
+use crate::pus::create_verification_reporter;
use log::{error, info, warn};
-use satrs::pool::{PoolProvider, StaticMemoryPool, StoreAddr};
+use satrs::pool::{PoolProvider, StaticMemoryPool};
use satrs::pus::scheduler::{PusScheduler, TcInfo};
-use satrs::pus::scheduler_srv::PusService11SchedHandler;
-use satrs::pus::verification::std_mod::{
- VerificationReporterWithSharedPoolMpscBoundedSender, VerificationReporterWithVecMpscSender,
-};
-use satrs::pus::verification::VerificationReportingProvider;
+use satrs::pus::scheduler_srv::PusSchedServiceHandler;
+use satrs::pus::verification::VerificationReporter;
use satrs::pus::{
EcssTcAndToken, EcssTcInMemConverter, EcssTcInSharedStoreConverter, EcssTcInVecConverter,
- EcssTcReceiverCore, EcssTmSenderCore, MpscTcReceiver, PusPacketHandlerResult, PusServiceHelper,
- TmAsVecSenderWithId, TmAsVecSenderWithMpsc, TmInSharedPoolSenderWithBoundedMpsc,
- TmInSharedPoolSenderWithId,
+ EcssTmSenderCore, MpscTcReceiver, MpscTmAsVecSender, MpscTmInSharedPoolSenderBounded,
+ PusPacketHandlerResult, PusServiceHelper, PusTmAsVec, PusTmInPool, TmInSharedPoolSender,
};
-use satrs::tmtc::tm_helper::SharedTmPool;
-use satrs::ChannelId;
-use satrs_example::config::{TcReceiverId, TmSenderId, PUS_APID};
+use satrs_example::config::components::PUS_SCHED_SERVICE;
use crate::tmtc::PusTcSourceProviderSharedPool;
@@ -55,14 +50,12 @@ impl TcReleaser for mpsc::Sender> {
}
}
-pub struct Pus11Wrapper<
- TcReceiver: EcssTcReceiverCore,
+pub struct SchedulingServiceWrapper<
TmSender: EcssTmSenderCore,
TcInMemConverter: EcssTcInMemConverter,
- VerificationReporter: VerificationReportingProvider,
> {
- pub pus_11_handler: PusService11SchedHandler<
- TcReceiver,
+ pub pus_11_handler: PusSchedServiceHandler<
+ MpscTcReceiver,
TmSender,
TcInMemConverter,
VerificationReporter,
@@ -73,12 +66,8 @@ pub struct Pus11Wrapper<
pub tc_releaser: Box,
}
-impl<
- TcReceiver: EcssTcReceiverCore,
- TmSender: EcssTmSenderCore,
- TcInMemConverter: EcssTcInMemConverter,
- VerificationReporter: VerificationReportingProvider,
- > Pus11Wrapper
+impl
+ SchedulingServiceWrapper
{
pub fn release_tcs(&mut self) {
let releaser = |enabled: bool, info: &TcInfo, tc: &[u8]| -> bool {
@@ -103,8 +92,11 @@ impl<
}
}
- pub fn handle_next_packet(&mut self) -> bool {
- match self.pus_11_handler.handle_one_tc(&mut self.sched_tc_pool) {
+ pub fn poll_and_handle_next_tc(&mut self, time_stamp: &[u8]) -> bool {
+ match self
+ .pus_11_handler
+ .poll_and_handle_next_tc(time_stamp, &mut self.sched_tc_pool)
+ {
Ok(result) => match result {
PusPacketHandlerResult::RequestHandled => {}
PusPacketHandlerResult::RequestHandledPartialSuccess(e) => {
@@ -129,42 +121,24 @@ impl<
}
pub fn create_scheduler_service_static(
- shared_tm_store: SharedTmPool,
- tm_funnel_tx: mpsc::SyncSender,
- verif_reporter: VerificationReporterWithSharedPoolMpscBoundedSender,
+ tm_sender: TmInSharedPoolSender>,
tc_releaser: PusTcSourceProviderSharedPool,
pus_sched_rx: mpsc::Receiver,
sched_tc_pool: StaticMemoryPool,
-) -> Pus11Wrapper<
- MpscTcReceiver,
- TmInSharedPoolSenderWithBoundedMpsc,
- EcssTcInSharedStoreConverter,
- VerificationReporterWithSharedPoolMpscBoundedSender,
-> {
- let sched_srv_tm_sender = TmInSharedPoolSenderWithId::new(
- TmSenderId::PusSched as ChannelId,
- "PUS_11_TM_SENDER",
- shared_tm_store.clone(),
- tm_funnel_tx.clone(),
- );
- let sched_srv_receiver = MpscTcReceiver::new(
- TcReceiverId::PusSched as ChannelId,
- "PUS_11_TC_RECV",
- pus_sched_rx,
- );
+) -> SchedulingServiceWrapper {
let scheduler = PusScheduler::new_with_current_init_time(Duration::from_secs(5))
.expect("Creating PUS Scheduler failed");
- let pus_11_handler = PusService11SchedHandler::new(
+ let pus_11_handler = PusSchedServiceHandler::new(
PusServiceHelper::new(
- sched_srv_receiver,
- sched_srv_tm_sender,
- PUS_APID,
- verif_reporter.clone(),
+ PUS_SCHED_SERVICE.id(),
+ pus_sched_rx,
+ tm_sender,
+ create_verification_reporter(PUS_SCHED_SERVICE.id(), PUS_SCHED_SERVICE.apid),
EcssTcInSharedStoreConverter::new(tc_releaser.clone_backing_pool(), 2048),
),
scheduler,
);
- Pus11Wrapper {
+ SchedulingServiceWrapper {
pus_11_handler,
sched_tc_pool,
releaser_buf: [0; 4096],
@@ -173,40 +147,26 @@ pub fn create_scheduler_service_static(
}
pub fn create_scheduler_service_dynamic(
- tm_funnel_tx: mpsc::Sender>,
- verif_reporter: VerificationReporterWithVecMpscSender,
+ tm_funnel_tx: mpsc::Sender,
tc_source_sender: mpsc::Sender>,
pus_sched_rx: mpsc::Receiver,
sched_tc_pool: StaticMemoryPool,
-) -> Pus11Wrapper<
- MpscTcReceiver,
- TmAsVecSenderWithMpsc,
- EcssTcInVecConverter,
- VerificationReporterWithVecMpscSender,
-> {
- let sched_srv_tm_sender = TmAsVecSenderWithId::new(
- TmSenderId::PusSched as ChannelId,
- "PUS_11_TM_SENDER",
- tm_funnel_tx,
- );
- let sched_srv_receiver = MpscTcReceiver::new(
- TcReceiverId::PusSched as ChannelId,
- "PUS_11_TC_RECV",
- pus_sched_rx,
- );
+) -> SchedulingServiceWrapper {
+ //let sched_srv_receiver =
+ //MpscTcReceiver::new(PUS_SCHED_SERVICE.raw(), "PUS_11_TC_RECV", pus_sched_rx);
let scheduler = PusScheduler::new_with_current_init_time(Duration::from_secs(5))
.expect("Creating PUS Scheduler failed");
- let pus_11_handler = PusService11SchedHandler::new(
+ let pus_11_handler = PusSchedServiceHandler::new(
PusServiceHelper::new(
- sched_srv_receiver,
- sched_srv_tm_sender,
- PUS_APID,
- verif_reporter.clone(),
+ PUS_SCHED_SERVICE.id(),
+ pus_sched_rx,
+ tm_funnel_tx,
+ create_verification_reporter(PUS_SCHED_SERVICE.id(), PUS_SCHED_SERVICE.apid),
EcssTcInVecConverter::default(),
),
scheduler,
);
- Pus11Wrapper {
+ SchedulingServiceWrapper {
pus_11_handler,
sched_tc_pool,
releaser_buf: [0; 4096],
diff --git a/satrs-example/src/pus/stack.rs b/satrs-example/src/pus/stack.rs
index ed06e08..a11463c 100644
--- a/satrs-example/src/pus/stack.rs
+++ b/satrs-example/src/pus/stack.rs
@@ -1,69 +1,71 @@
-use satrs::pus::{
- verification::VerificationReportingProvider, EcssTcInMemConverter, EcssTcReceiverCore,
- EcssTmSenderCore,
+use crate::pus::mode::ModeServiceWrapper;
+use derive_new::new;
+use satrs::{
+ pus::{EcssTcInMemConverter, EcssTmSenderCore},
+ spacepackets::time::{cds, TimeWriter},
};
use super::{
- action::Pus8Wrapper, event::Pus5Wrapper, hk::Pus3Wrapper, scheduler::Pus11Wrapper,
- test::Service17CustomWrapper,
+ action::ActionServiceWrapper, event::EventServiceWrapper, hk::HkServiceWrapper,
+ scheduler::SchedulingServiceWrapper, test::TestCustomServiceWrapper, HandlingStatus,
+ TargetedPusService,
};
-pub struct PusStack<
- TcReceiver: EcssTcReceiverCore,
- TmSender: EcssTmSenderCore,
- TcInMemConverter: EcssTcInMemConverter,
- VerificationReporter: VerificationReportingProvider,
-> {
- event_srv: Pus5Wrapper,
- hk_srv: Pus3Wrapper,
- action_srv: Pus8Wrapper,
- schedule_srv: Pus11Wrapper,
- test_srv: Service17CustomWrapper,
+#[derive(new)]
+pub struct PusStack {
+ test_srv: TestCustomServiceWrapper,
+ hk_srv_wrapper: HkServiceWrapper,
+ event_srv: EventServiceWrapper,
+ action_srv_wrapper: ActionServiceWrapper,
+ schedule_srv: SchedulingServiceWrapper