diff --git a/satrs-example-stm32f3-disco/.cargo/def_config.toml b/satrs-example-stm32f3-disco/.cargo/def_config.toml index 4150986..4598c09 100644 --- a/satrs-example-stm32f3-disco/.cargo/def_config.toml +++ b/satrs-example-stm32f3-disco/.cargo/def_config.toml @@ -5,11 +5,17 @@ # runner = "arm-none-eabi-gdb -q -x openocd.gdb" # runner = "gdb-multiarch -q -x openocd.gdb" # runner = "gdb -q -x openocd.gdb" -# runner = "probe-run --chip STM32F303VCTx --connect-under-reset" +runner = "probe-rs run --chip STM32F303VCTx" rustflags = [ + "-C", "linker=flip-link", # LLD (shipped with the Rust toolchain) is used as the default linker "-C", "link-arg=-Tlink.x", + "-C", "link-arg=-Tdefmt.x", + + # This is needed if your flash or ram addresses are not aligned to 0x10000 in memory.x + # See https://github.com/rust-embedded/cortex-m-quickstart/pull/95 + "-C", "link-arg=--nmagic", # if you run into problems with LLD switch to the GNU linker by commenting out # this line @@ -26,3 +32,6 @@ rustflags = [ [build] # comment out the following line if you intend to run unit tests on host machine target = "thumbv7em-none-eabihf" # Cortex-M4F and Cortex-M7F (with FPU) + +[env] +DEFMT_LOG = "info" \ No newline at end of file diff --git a/satrs-example-stm32f3-disco/Cargo.lock b/satrs-example-stm32f3-disco/Cargo.lock index 9043d7a..9fb5086 100644 --- a/satrs-example-stm32f3-disco/Cargo.lock +++ b/satrs-example-stm32f3-disco/Cargo.lock @@ -139,6 +139,15 @@ dependencies = [ "syn 1.0.109", ] +[[package]] +name = "cortex-m-semihosting" +version = "0.5.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "c23234600452033cc77e4b761e740e02d2c4168e11dbf36ab14a0f58973592b0" +dependencies = [ + "cortex-m", +] + [[package]] name = "crc" version = "3.0.1" @@ -194,6 +203,71 @@ dependencies = [ "syn 2.0.53", ] +[[package]] +name = "defmt" +version = "0.3.6" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "3939552907426de152b3c2c6f51ed53f98f448babd26f28694c95f5906194595" +dependencies = [ + "bitflags", + "defmt-macros", +] + +[[package]] +name = "defmt-brtt" +version = "0.1.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "c2f0ac3635d0c89d12b8101fcb44a7625f5f030a1c0491124b74467eb5a58a78" +dependencies = [ + "critical-section", + "defmt", +] + +[[package]] +name = "defmt-macros" +version = "0.3.7" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "18bdc7a7b92ac413e19e95240e75d3a73a8d8e78aa24a594c22cbb4d44b4bbda" +dependencies = [ + "defmt-parser", + "proc-macro-error", + "proc-macro2", + "quote", + "syn 2.0.53", +] + +[[package]] +name = "defmt-parser" +version = "0.3.4" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "ff4a5fefe330e8d7f31b16a318f9ce81000d8e35e69b93eae154d16d2278f70f" +dependencies = [ + "thiserror", +] + +[[package]] +name = "defmt-test" +version = "0.3.2" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "290966e8c38f94b11884877242de876280d0eab934900e9642d58868e77c5df1" +dependencies = [ + "cortex-m-rt", + "cortex-m-semihosting", + "defmt", + "defmt-test-macros", +] + +[[package]] +name = "defmt-test-macros" +version = "0.3.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "984bc6eca246389726ac2826acc2488ca0fe5fcd6b8d9b48797021951d76a125" +dependencies = [ + "proc-macro2", + "quote", + "syn 2.0.53", +] + [[package]] name = "delegate" version = "0.10.0" @@ -371,21 +445,6 @@ dependencies = [ "hashbrown", ] -[[package]] -name = "itm_logger" -version = "0.1.3-alpha.0" -source = "git+https://github.com/robamu/itm_logger.rs.git?branch=all_features#83ee7a6c57f525a70d0cc5bb7e65826d0ce938a0" -dependencies = [ - "cortex-m", - "log", -] - -[[package]] -name = "log" -version = "0.4.21" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "90ed8c1e510134f979dbc4f070f87d4313098b704861a105fe34231c70a3901c" - [[package]] name = "lsm303dlhc" version = "0.2.0" @@ -504,12 +563,13 @@ dependencies = [ ] [[package]] -name = "panic-itm" -version = "0.4.2" +name = "panic-probe" +version = "0.3.1" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "3d577d97d1b31268087b6dddf2470e6794ef5eee87d9dca7fcd0481695391a4c" +checksum = "aa6fa5645ef5a760cd340eaa92af9c1ce131c8c09e7f8926d8a24b59d26652b9" dependencies = [ "cortex-m", + "defmt", ] [[package]] @@ -690,11 +750,14 @@ dependencies = [ "cobs 0.2.3 (git+https://github.com/robamu/cobs.rs.git?branch=all_features)", "cortex-m", "cortex-m-rt", + "cortex-m-semihosting", + "defmt", + "defmt-brtt", + "defmt-test", "embedded-hal 0.2.7", "enumset", "heapless", - "itm_logger", - "panic-itm", + "panic-probe", "rtic", "rtic-monotonics", "satrs", @@ -855,6 +918,26 @@ dependencies = [ "unicode-ident", ] +[[package]] +name = "thiserror" +version = "1.0.58" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "03468839009160513471e86a034bb2c5c0e4baae3b43f79ffc55c4a5427b3297" +dependencies = [ + "thiserror-impl", +] + +[[package]] +name = "thiserror-impl" +version = "1.0.58" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "c61f3ba182994efc43764a46c018c347bc492c79f024e705f46567b418f6d4f7" +dependencies = [ + "proc-macro2", + "quote", + "syn 2.0.53", +] + [[package]] name = "typenum" version = "1.17.0" diff --git a/satrs-example-stm32f3-disco/Cargo.toml b/satrs-example-stm32f3-disco/Cargo.toml index 4337919..dd306c6 100644 --- a/satrs-example-stm32f3-disco/Cargo.toml +++ b/satrs-example-stm32f3-disco/Cargo.toml @@ -2,13 +2,18 @@ name = "satrs-example-stm32f3-disco" version = "0.1.0" edition = "2021" +default-run = "satrs-example-stm32f3-disco" # See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html [dependencies] cortex-m = { version = "0.7", features = ["critical-section-single-core"] } cortex-m-rt = "0.7" +defmt = "0.3" +defmt-brtt = { version = "0.1", default-features = false, features = ["rtt"] } +panic-probe = { version = "0.3", features = ["print-defmt"] } embedded-hal = "0.2.7" +cortex-m-semihosting = "0.5.0" enumset = "1" heapless = "0.8" @@ -25,14 +30,6 @@ git = "https://github.com/robamu/cobs.rs.git" branch = "all_features" default-features = false -[dependencies.panic-itm] -version = "0.4" - -[dependencies.itm_logger] -git = "https://github.com/robamu/itm_logger.rs.git" -branch = "all_features" -version = "0.1.3-alpha.0" - [dependencies.stm32f3xx-hal] git = "https://github.com/robamu/stm32f3xx-hal" version = "0.11.0-alpha.0" @@ -49,17 +46,37 @@ branch = "complete-dma-update-hal" # path = "../stm32f3-discovery" [dependencies.satrs] -# git = "https://egit.irs.uni-stuttgart.de/rust/satrs-core.git" version = "0.2.0-rc.0" default-features = false -# this lets you use `cargo fix`! -# [[bin]] -# name = "stm32f3-blinky" -# test = false -# bench = false +[dev-dependencies] +defmt-test = "0.3" +# cargo test +[profile.test] +codegen-units = 1 +debug = 2 +debug-assertions = true # <- +incremental = false +opt-level = "s" # <- +overflow-checks = true # <- + +# cargo build/run --release [profile.release] -codegen-units = 1 # better optimizations -debug = true # symbols are nice and they don't increase the size on Flash -lto = true # better optimizations +codegen-units = 1 +debug = 2 +debug-assertions = false # <- +incremental = false +lto = 'fat' +opt-level = "s" # <- +overflow-checks = false # <- + +# cargo test --release +[profile.bench] +codegen-units = 1 +debug = 2 +debug-assertions = false # <- +incremental = false +lto = 'fat' +opt-level = "s" # <- +overflow-checks = false # <- diff --git a/satrs-example-stm32f3-disco/README.md b/satrs-example-stm32f3-disco/README.md index 9d502fa..21648b2 100644 --- a/satrs-example-stm32f3-disco/README.md +++ b/satrs-example-stm32f3-disco/README.md @@ -2,26 +2,24 @@ sat-rs example for the STM32F3-Discovery board ======= This example application shows how the [sat-rs framework](https://egit.irs.uni-stuttgart.de/rust/satrs-launchpad) -can be used on an embedded target. It also shows how a relatively simple OBSW could be built when no -standard runtime is available. It uses [RTIC](https://rtic.rs/1/book/en/) as the concurrency -framework. +can be used on an embedded target. +It also shows how a relatively simple OBSW could be built when no standard runtime is available. +It uses [RTIC](https://rtic.rs/1/book/en/) as the concurrency framework and the +[defmt](https://defmt.ferrous-systems.com/) framework for logging. The STM32F3-Discovery device was picked because it is a cheap Cortex-M4 based device which is also used by the [Rust Embedded Book](https://docs.rust-embedded.org/book/intro/hardware.html) and the [Rust Discovery](https://docs.rust-embedded.org/discovery/f3discovery/) book as an introduction to embedded Rust. -If you would like to access the ITM log output, you need to connect the PB3 pin to the CN3 pin -of the SWD header like [shown here](https://docs.rust-embedded.org/discovery/f3discovery/06-hello-world/index.html). - ## Pre-Requisites Make sure the following tools are installed: -1. `openocd`: This is the debug server used to debug the STM32F3. You can install this from - [`xPacks`](https://xpack.github.io/dev-tools/openocd/install/). You can also use the one provided - by a STM32Cube installation. -2. A debugger like `arm-none-eabi-gdb` or `gdb-multiarch`. +1. [`probe-rs`](https://probe.rs/): Application used to flash and debug the MCU. +2. Optional and recommended: [VS Code](https://code.visualstudio.com/) with + [probe-rs plugin](https://marketplace.visualstudio.com/items?itemName=probe-rs.probe-rs-debugger) + for debugging. ## Preparing Rust and the repository @@ -52,23 +50,19 @@ you can simply build the application with cargo build ``` -## Flashing and Debugging from the command line +## Flashing from the command line -Make sure you have `openocd` and `itmdump` installed first. +You can flash the application from the command line using `probe-rs`: -1. Configure a runner inside your `.cargo/config.toml` file by uncommenting an appropriate line - depending on the application you want to use for debugging -2. Start `openocd` inside the project folder. This will start `openocd` with the provided - `openocd.cfg` configuration file. -3. Use `cargo run` to flash and debug the application in your terminal -4. Use `itmdump -F -f itm.txt` to print the logs received from the STM32F3 device. Please note - that the PB3 and CN3 pin of the SWD header need to be connected for this to work. +```sh +probe-rs run --chip STM32F303VCTx +``` ## Debugging with VS Code The STM32F3-Discovery comes with an on-board ST-Link so all that is required to flash and debug -the board is a Mini-USB cable. The code in this repository was debugged using `openocd` -and the VS Code [`Cortex-Debug` plugin](https://marketplace.visualstudio.com/items?itemName=marus25.cortex-debug). +the board is a Mini-USB cable. The code in this repository was debugged using [`probe-rs`](https://probe.rs/docs/tools/debuggerA) +and the VS Code [`probe-rs` plugin](https://marketplace.visualstudio.com/items?itemName=probe-rs.probe-rs-debugger). Make sure to install this plugin first. Sample configuration files are provided inside the `vscode` folder. @@ -80,19 +74,11 @@ to automatically rebuild and flash your application. The `tasks.json` and `launch.json` files are generic and you can use them immediately by opening the folder in VS code or adding it to a workspace. -If you would like to use a custom GDB application, you can specify the gdb binary in the following -configuration variables in your `settings.json`: - -- `"cortex-debug.gdbPath"` -- `"cortex-debug.gdbPath.linux"` -- `"cortex-debug.gdbPath.windows"` -- `"cortex-debug.gdbPath.osx"` - ## Commanding with Python When the SW is running on the Discovery board, you can command the MCU via a serial interface, using COBS encoded PUS packets. - + It is recommended to use a virtual environment to do this. To set up one in the command line, you can use `python3 -m venv venv` on Unix systems or `py -m venv venv` on Windows systems. After doing this, you can check the [venv tutorial](https://docs.python.org/3/tutorial/venv.html) @@ -111,3 +97,9 @@ A default configuration file for the python application is provided and can be u ```sh cp def_tmtc_conf.json tmtc_conf.json ``` + +After that, you can for example send a ping to the MCU using the following command + +```sh +./main.py -p /ping +``` diff --git a/satrs-example-stm32f3-disco/STM32F303.svd b/satrs-example-stm32f3-disco/STM32F303.svd new file mode 100644 index 0000000..63fb761 --- /dev/null +++ b/satrs-example-stm32f3-disco/STM32F303.svd @@ -0,0 +1,38601 @@ + + + + STM32F303 + 1.8 + STM32F303 + + CM4 + r1p0 + little + true + true + 3 + false + + 8 + 32 + 0x20 + 0x0 + 0xFFFFFFFF + + + GPIOA + General-purpose I/Os + GPIO + 0x48000000 + + 0x0 + 0x400 + registers + + + + MODER + MODER + GPIO port mode register + 0x0 + 0x20 + read-write + 0x28000000 + + + MODER15 + Port x configuration bits (y = + 0..15) + 30 + 2 + + + MODER14 + Port x configuration bits (y = + 0..15) + 28 + 2 + + + MODER13 + Port x configuration bits (y = + 0..15) + 26 + 2 + + + MODER12 + Port x configuration bits (y = + 0..15) + 24 + 2 + + + MODER11 + Port x configuration bits (y = + 0..15) + 22 + 2 + + + MODER10 + Port x configuration bits (y = + 0..15) + 20 + 2 + + + MODER9 + Port x configuration bits (y = + 0..15) + 18 + 2 + + + MODER8 + Port x configuration bits (y = + 0..15) + 16 + 2 + + + MODER7 + Port x configuration bits (y = + 0..15) + 14 + 2 + + + MODER6 + Port x configuration bits (y = + 0..15) + 12 + 2 + + + MODER5 + Port x configuration bits (y = + 0..15) + 10 + 2 + + + MODER4 + Port x configuration bits (y = + 0..15) + 8 + 2 + + + MODER3 + Port x configuration bits (y = + 0..15) + 6 + 2 + + + MODER2 + Port x configuration bits (y = + 0..15) + 4 + 2 + + + MODER1 + Port x configuration bits (y = + 0..15) + 2 + 2 + + + MODER0 + Port x configuration bits (y = + 0..15) + 0 + 2 + + + + + OTYPER + OTYPER + GPIO port output type register + 0x4 + 0x20 + read-write + 0x00000000 + + + OT15 + Port x configuration bits (y = + 0..15) + 15 + 1 + + + OT14 + Port x configuration bits (y = + 0..15) + 14 + 1 + + + OT13 + Port x configuration bits (y = + 0..15) + 13 + 1 + + + OT12 + Port x configuration bits (y = + 0..15) + 12 + 1 + + + OT11 + Port x configuration bits (y = + 0..15) + 11 + 1 + + + OT10 + Port x configuration bits (y = + 0..15) + 10 + 1 + + + OT9 + Port x configuration bits (y = + 0..15) + 9 + 1 + + + OT8 + Port x configuration bits (y = + 0..15) + 8 + 1 + + + OT7 + Port x configuration bits (y = + 0..15) + 7 + 1 + + + OT6 + Port x configuration bits (y = + 0..15) + 6 + 1 + + + OT5 + Port x configuration bits (y = + 0..15) + 5 + 1 + + + OT4 + Port x configuration bits (y = + 0..15) + 4 + 1 + + + OT3 + Port x configuration bits (y = + 0..15) + 3 + 1 + + + OT2 + Port x configuration bits (y = + 0..15) + 2 + 1 + + + OT1 + Port x configuration bits (y = + 0..15) + 1 + 1 + + + OT0 + Port x configuration bits (y = + 0..15) + 0 + 1 + + + + + OSPEEDR + OSPEEDR + GPIO port output speed + register + 0x8 + 0x20 + read-write + 0x00000000 + + + OSPEEDR15 + Port x configuration bits (y = + 0..15) + 30 + 2 + + + OSPEEDR14 + Port x configuration bits (y = + 0..15) + 28 + 2 + + + OSPEEDR13 + Port x configuration bits (y = + 0..15) + 26 + 2 + + + OSPEEDR12 + Port x configuration bits (y = + 0..15) + 24 + 2 + + + OSPEEDR11 + Port x configuration bits (y = + 0..15) + 22 + 2 + + + OSPEEDR10 + Port x configuration bits (y = + 0..15) + 20 + 2 + + + OSPEEDR9 + Port x configuration bits (y = + 0..15) + 18 + 2 + + + OSPEEDR8 + Port x configuration bits (y = + 0..15) + 16 + 2 + + + OSPEEDR7 + Port x configuration bits (y = + 0..15) + 14 + 2 + + + OSPEEDR6 + Port x configuration bits (y = + 0..15) + 12 + 2 + + + OSPEEDR5 + Port x configuration bits (y = + 0..15) + 10 + 2 + + + OSPEEDR4 + Port x configuration bits (y = + 0..15) + 8 + 2 + + + OSPEEDR3 + Port x configuration bits (y = + 0..15) + 6 + 2 + + + OSPEEDR2 + Port x configuration bits (y = + 0..15) + 4 + 2 + + + OSPEEDR1 + Port x configuration bits (y = + 0..15) + 2 + 2 + + + OSPEEDR0 + Port x configuration bits (y = + 0..15) + 0 + 2 + + + + + PUPDR + PUPDR + GPIO port pull-up/pull-down + register + 0xC + 0x20 + read-write + 0x24000000 + + + PUPDR15 + Port x configuration bits (y = + 0..15) + 30 + 2 + + + PUPDR14 + Port x configuration bits (y = + 0..15) + 28 + 2 + + + PUPDR13 + Port x configuration bits (y = + 0..15) + 26 + 2 + + + PUPDR12 + Port x configuration bits (y = + 0..15) + 24 + 2 + + + PUPDR11 + Port x configuration bits (y = + 0..15) + 22 + 2 + + + PUPDR10 + Port x configuration bits (y = + 0..15) + 20 + 2 + + + PUPDR9 + Port x configuration bits (y = + 0..15) + 18 + 2 + + + PUPDR8 + Port x configuration bits (y = + 0..15) + 16 + 2 + + + PUPDR7 + Port x configuration bits (y = + 0..15) + 14 + 2 + + + PUPDR6 + Port x configuration bits (y = + 0..15) + 12 + 2 + + + PUPDR5 + Port x configuration bits (y = + 0..15) + 10 + 2 + + + PUPDR4 + Port x configuration bits (y = + 0..15) + 8 + 2 + + + PUPDR3 + Port x configuration bits (y = + 0..15) + 6 + 2 + + + PUPDR2 + Port x configuration bits (y = + 0..15) + 4 + 2 + + + PUPDR1 + Port x configuration bits (y = + 0..15) + 2 + 2 + + + PUPDR0 + Port x configuration bits (y = + 0..15) + 0 + 2 + + + + + IDR + IDR + GPIO port input data register + 0x10 + 0x20 + read-only + 0x00000000 + + + IDR15 + Port input data (y = + 0..15) + 15 + 1 + + + IDR14 + Port input data (y = + 0..15) + 14 + 1 + + + IDR13 + Port input data (y = + 0..15) + 13 + 1 + + + IDR12 + Port input data (y = + 0..15) + 12 + 1 + + + IDR11 + Port input data (y = + 0..15) + 11 + 1 + + + IDR10 + Port input data (y = + 0..15) + 10 + 1 + + + IDR9 + Port input data (y = + 0..15) + 9 + 1 + + + IDR8 + Port input data (y = + 0..15) + 8 + 1 + + + IDR7 + Port input data (y = + 0..15) + 7 + 1 + + + IDR6 + Port input data (y = + 0..15) + 6 + 1 + + + IDR5 + Port input data (y = + 0..15) + 5 + 1 + + + IDR4 + Port input data (y = + 0..15) + 4 + 1 + + + IDR3 + Port input data (y = + 0..15) + 3 + 1 + + + IDR2 + Port input data (y = + 0..15) + 2 + 1 + + + IDR1 + Port input data (y = + 0..15) + 1 + 1 + + + IDR0 + Port input data (y = + 0..15) + 0 + 1 + + + + + ODR + ODR + GPIO port output data register + 0x14 + 0x20 + read-write + 0x00000000 + + + ODR15 + Port output data (y = + 0..15) + 15 + 1 + + + ODR14 + Port output data (y = + 0..15) + 14 + 1 + + + ODR13 + Port output data (y = + 0..15) + 13 + 1 + + + ODR12 + Port output data (y = + 0..15) + 12 + 1 + + + ODR11 + Port output data (y = + 0..15) + 11 + 1 + + + ODR10 + Port output data (y = + 0..15) + 10 + 1 + + + ODR9 + Port output data (y = + 0..15) + 9 + 1 + + + ODR8 + Port output data (y = + 0..15) + 8 + 1 + + + ODR7 + Port output data (y = + 0..15) + 7 + 1 + + + ODR6 + Port output data (y = + 0..15) + 6 + 1 + + + ODR5 + Port output data (y = + 0..15) + 5 + 1 + + + ODR4 + Port output data (y = + 0..15) + 4 + 1 + + + ODR3 + Port output data (y = + 0..15) + 3 + 1 + + + ODR2 + Port output data (y = + 0..15) + 2 + 1 + + + ODR1 + Port output data (y = + 0..15) + 1 + 1 + + + ODR0 + Port output data (y = + 0..15) + 0 + 1 + + + + + BSRR + BSRR + GPIO port bit set/reset + register + 0x18 + 0x20 + write-only + 0x00000000 + + + BR15 + Port x reset bit y (y = + 0..15) + 31 + 1 + + + BR14 + Port x reset bit y (y = + 0..15) + 30 + 1 + + + BR13 + Port x reset bit y (y = + 0..15) + 29 + 1 + + + BR12 + Port x reset bit y (y = + 0..15) + 28 + 1 + + + BR11 + Port x reset bit y (y = + 0..15) + 27 + 1 + + + BR10 + Port x reset bit y (y = + 0..15) + 26 + 1 + + + BR9 + Port x reset bit y (y = + 0..15) + 25 + 1 + + + BR8 + Port x reset bit y (y = + 0..15) + 24 + 1 + + + BR7 + Port x reset bit y (y = + 0..15) + 23 + 1 + + + BR6 + Port x reset bit y (y = + 0..15) + 22 + 1 + + + BR5 + Port x reset bit y (y = + 0..15) + 21 + 1 + + + BR4 + Port x reset bit y (y = + 0..15) + 20 + 1 + + + BR3 + Port x reset bit y (y = + 0..15) + 19 + 1 + + + BR2 + Port x reset bit y (y = + 0..15) + 18 + 1 + + + BR1 + Port x reset bit y (y = + 0..15) + 17 + 1 + + + BR0 + Port x set bit y (y= + 0..15) + 16 + 1 + + + BS15 + Port x set bit y (y= + 0..15) + 15 + 1 + + + BS14 + Port x set bit y (y= + 0..15) + 14 + 1 + + + BS13 + Port x set bit y (y= + 0..15) + 13 + 1 + + + BS12 + Port x set bit y (y= + 0..15) + 12 + 1 + + + BS11 + Port x set bit y (y= + 0..15) + 11 + 1 + + + BS10 + Port x set bit y (y= + 0..15) + 10 + 1 + + + BS9 + Port x set bit y (y= + 0..15) + 9 + 1 + + + BS8 + Port x set bit y (y= + 0..15) + 8 + 1 + + + BS7 + Port x set bit y (y= + 0..15) + 7 + 1 + + + BS6 + Port x set bit y (y= + 0..15) + 6 + 1 + + + BS5 + Port x set bit y (y= + 0..15) + 5 + 1 + + + BS4 + Port x set bit y (y= + 0..15) + 4 + 1 + + + BS3 + Port x set bit y (y= + 0..15) + 3 + 1 + + + BS2 + Port x set bit y (y= + 0..15) + 2 + 1 + + + BS1 + Port x set bit y (y= + 0..15) + 1 + 1 + + + BS0 + Port x set bit y (y= + 0..15) + 0 + 1 + + + + + LCKR + LCKR + GPIO port configuration lock + register + 0x1C + 0x20 + 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0..15) + 3 + 1 + + + BS2 + Port x set bit y (y= + 0..15) + 2 + 1 + + + BS1 + Port x set bit y (y= + 0..15) + 1 + 1 + + + BS0 + Port x set bit y (y= + 0..15) + 0 + 1 + + + + + LCKR + LCKR + GPIO port configuration lock + register + 0x1C + 0x20 + read-write + 0x00000000 + + + LCKK + Lok Key + 16 + 1 + + + LCK15 + Port x lock bit y (y= + 0..15) + 15 + 1 + + + LCK14 + Port x lock bit y (y= + 0..15) + 14 + 1 + + + LCK13 + Port x lock bit y (y= + 0..15) + 13 + 1 + + + LCK12 + Port x lock bit y (y= + 0..15) + 12 + 1 + + + LCK11 + Port x lock bit y (y= + 0..15) + 11 + 1 + + + LCK10 + Port x lock bit y (y= + 0..15) + 10 + 1 + + + LCK9 + Port x lock bit y (y= + 0..15) + 9 + 1 + + + LCK8 + Port x lock bit y (y= + 0..15) + 8 + 1 + + + LCK7 + Port x lock bit y (y= + 0..15) + 7 + 1 + + + LCK6 + Port x lock bit y (y= + 0..15) + 6 + 1 + + + LCK5 + Port x lock bit y (y= + 0..15) + 5 + 1 + + + LCK4 + Port x lock bit y (y= + 0..15) + 4 + 1 + + + LCK3 + Port x lock bit y (y= + 0..15) + 3 + 1 + + + LCK2 + Port x lock bit y (y= + 0..15) + 2 + 1 + + + LCK1 + Port x lock bit y (y= + 0..15) + 1 + 1 + + + LCK0 + Port x lock bit y (y= + 0..15) + 0 + 1 + + + + + AFRL + AFRL + GPIO alternate function low + register + 0x20 + 0x20 + read-write + 0x00000000 + + + AFRL7 + Alternate function selection for port x + bit y (y = 0..7) + 28 + 4 + + + AFRL6 + Alternate function selection for port x + bit y (y = 0..7) + 24 + 4 + + + AFRL5 + Alternate function selection for port x + bit y (y = 0..7) + 20 + 4 + + + AFRL4 + Alternate function selection for port x + bit y (y = 0..7) + 16 + 4 + + + AFRL3 + Alternate function selection for port x + bit y (y = 0..7) + 12 + 4 + + + AFRL2 + Alternate function selection for port x + bit y (y = 0..7) + 8 + 4 + + + AFRL1 + Alternate function selection for port x + bit y (y = 0..7) + 4 + 4 + + + AFRL0 + Alternate function selection for port x + bit y (y = 0..7) + 0 + 4 + + + + + AFRH + AFRH + GPIO alternate function high + register + 0x24 + 0x20 + read-write + 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Schmitt trigger hysteresis + mode + 16 + 1 + + + G5_IO2 + G5_IO2 Schmitt trigger hysteresis + mode + 17 + 1 + + + G5_IO3 + G5_IO3 Schmitt trigger hysteresis + mode + 18 + 1 + + + G5_IO4 + G5_IO4 Schmitt trigger hysteresis + mode + 19 + 1 + + + G6_IO1 + G6_IO1 Schmitt trigger hysteresis + mode + 20 + 1 + + + G6_IO2 + G6_IO2 Schmitt trigger hysteresis + mode + 21 + 1 + + + G6_IO3 + G6_IO3 Schmitt trigger hysteresis + mode + 22 + 1 + + + G6_IO4 + G6_IO4 Schmitt trigger hysteresis + mode + 23 + 1 + + + G7_IO1 + G7_IO1 Schmitt trigger hysteresis + mode + 24 + 1 + + + G7_IO2 + G7_IO2 Schmitt trigger hysteresis + mode + 25 + 1 + + + G7_IO3 + G7_IO3 Schmitt trigger hysteresis + mode + 26 + 1 + + + G7_IO4 + G7_IO4 Schmitt trigger hysteresis + mode + 27 + 1 + + + G8_IO1 + G8_IO1 Schmitt trigger hysteresis + mode + 28 + 1 + + + G8_IO2 + G8_IO2 Schmitt trigger hysteresis + mode + 29 + 1 + + + G8_IO3 + G8_IO3 Schmitt trigger hysteresis + mode + 30 + 1 + + + G8_IO4 + G8_IO4 Schmitt trigger hysteresis + mode + 31 + 1 + + + + + IOASCR + IOASCR + I/O analog switch control + register + 0x18 + 0x20 + read-write + 0x00000000 + + + G1_IO1 + G1_IO1 analog switch + enable + 0 + 1 + + + G1_IO2 + G1_IO2 analog switch + enable + 1 + 1 + + + G1_IO3 + G1_IO3 analog switch + enable + 2 + 1 + + + G1_IO4 + G1_IO4 analog switch + enable + 3 + 1 + + + G2_IO1 + G2_IO1 analog switch + enable + 4 + 1 + + + G2_IO2 + G2_IO2 analog switch + enable + 5 + 1 + + + G2_IO3 + G2_IO3 analog switch + enable + 6 + 1 + + + G2_IO4 + G2_IO4 analog switch + enable + 7 + 1 + + + G3_IO1 + G3_IO1 analog switch + enable + 8 + 1 + + + G3_IO2 + G3_IO2 analog switch + enable + 9 + 1 + + + G3_IO3 + G3_IO3 analog switch + enable + 10 + 1 + + + G3_IO4 + G3_IO4 analog switch + enable + 11 + 1 + + + G4_IO1 + G4_IO1 analog switch + enable + 12 + 1 + + + G4_IO2 + G4_IO2 analog switch + enable + 13 + 1 + + + G4_IO3 + G4_IO3 analog switch + enable + 14 + 1 + + + G4_IO4 + G4_IO4 analog switch + enable + 15 + 1 + + + G5_IO1 + G5_IO1 analog switch + enable + 16 + 1 + + + G5_IO2 + G5_IO2 analog switch + enable + 17 + 1 + + + G5_IO3 + G5_IO3 analog switch + enable + 18 + 1 + + + G5_IO4 + G5_IO4 analog switch + enable + 19 + 1 + + + G6_IO1 + G6_IO1 analog switch + enable + 20 + 1 + + + G6_IO2 + G6_IO2 analog switch + enable + 21 + 1 + + + G6_IO3 + G6_IO3 analog switch + enable + 22 + 1 + + + G6_IO4 + G6_IO4 analog switch + enable + 23 + 1 + + + G7_IO1 + G7_IO1 analog switch + enable + 24 + 1 + + + G7_IO2 + G7_IO2 analog switch + enable + 25 + 1 + + + G7_IO3 + G7_IO3 analog switch + enable + 26 + 1 + + + G7_IO4 + G7_IO4 analog switch + enable + 27 + 1 + + + G8_IO1 + G8_IO1 analog switch + enable + 28 + 1 + + + G8_IO2 + G8_IO2 analog switch + enable + 29 + 1 + + + G8_IO3 + G8_IO3 analog switch + enable + 30 + 1 + + + G8_IO4 + G8_IO4 analog switch + enable + 31 + 1 + + + + + IOSCR + IOSCR + I/O sampling control register + 0x20 + 0x20 + read-write + 0x00000000 + + + G1_IO1 + G1_IO1 sampling mode + 0 + 1 + + + G1_IO2 + G1_IO2 sampling mode + 1 + 1 + + + G1_IO3 + G1_IO3 sampling mode + 2 + 1 + + + G1_IO4 + G1_IO4 sampling mode + 3 + 1 + + + G2_IO1 + G2_IO1 sampling mode + 4 + 1 + + + G2_IO2 + G2_IO2 sampling mode + 5 + 1 + + + G2_IO3 + G2_IO3 sampling mode + 6 + 1 + + + G2_IO4 + G2_IO4 sampling mode + 7 + 1 + + + G3_IO1 + G3_IO1 sampling mode + 8 + 1 + + + G3_IO2 + G3_IO2 sampling mode + 9 + 1 + + + G3_IO3 + G3_IO3 sampling mode + 10 + 1 + + + G3_IO4 + G3_IO4 sampling mode + 11 + 1 + + + G4_IO1 + G4_IO1 sampling mode + 12 + 1 + + + G4_IO2 + G4_IO2 sampling mode + 13 + 1 + + + G4_IO3 + G4_IO3 sampling mode + 14 + 1 + + + G4_IO4 + G4_IO4 sampling mode + 15 + 1 + + + G5_IO1 + G5_IO1 sampling mode + 16 + 1 + + + G5_IO2 + G5_IO2 sampling mode + 17 + 1 + + + G5_IO3 + G5_IO3 sampling mode + 18 + 1 + + + G5_IO4 + G5_IO4 sampling mode + 19 + 1 + + + G6_IO1 + G6_IO1 sampling mode + 20 + 1 + + + G6_IO2 + G6_IO2 sampling mode + 21 + 1 + + + G6_IO3 + G6_IO3 sampling mode + 22 + 1 + + + G6_IO4 + G6_IO4 sampling mode + 23 + 1 + + + G7_IO1 + G7_IO1 sampling mode + 24 + 1 + + + G7_IO2 + G7_IO2 sampling mode + 25 + 1 + + + G7_IO3 + G7_IO3 sampling mode + 26 + 1 + + + G7_IO4 + G7_IO4 sampling mode + 27 + 1 + + + G8_IO1 + G8_IO1 sampling mode + 28 + 1 + + + G8_IO2 + G8_IO2 sampling mode + 29 + 1 + + + G8_IO3 + G8_IO3 sampling mode + 30 + 1 + + + G8_IO4 + G8_IO4 sampling mode + 31 + 1 + + + + + IOCCR + IOCCR + I/O channel control register + 0x28 + 0x20 + read-write + 0x00000000 + + + G1_IO1 + G1_IO1 channel mode + 0 + 1 + + + G1_IO2 + G1_IO2 channel mode + 1 + 1 + + + G1_IO3 + G1_IO3 channel mode + 2 + 1 + + + G1_IO4 + G1_IO4 channel mode + 3 + 1 + + + G2_IO1 + G2_IO1 channel mode + 4 + 1 + + + G2_IO2 + G2_IO2 channel mode + 5 + 1 + + + G2_IO3 + G2_IO3 channel mode + 6 + 1 + + + G2_IO4 + G2_IO4 channel mode + 7 + 1 + + + G3_IO1 + G3_IO1 channel mode + 8 + 1 + + + G3_IO2 + G3_IO2 channel mode + 9 + 1 + + + G3_IO3 + G3_IO3 channel mode + 10 + 1 + + + G3_IO4 + G3_IO4 channel mode + 11 + 1 + + + G4_IO1 + G4_IO1 channel mode + 12 + 1 + + + G4_IO2 + G4_IO2 channel mode + 13 + 1 + + + G4_IO3 + G4_IO3 channel mode + 14 + 1 + + + G4_IO4 + G4_IO4 channel mode + 15 + 1 + + + G5_IO1 + G5_IO1 channel mode + 16 + 1 + + + G5_IO2 + G5_IO2 channel mode + 17 + 1 + + + G5_IO3 + G5_IO3 channel mode + 18 + 1 + + + G5_IO4 + G5_IO4 channel mode + 19 + 1 + + + G6_IO1 + G6_IO1 channel mode + 20 + 1 + + + G6_IO2 + G6_IO2 channel mode + 21 + 1 + + + G6_IO3 + G6_IO3 channel mode + 22 + 1 + + + G6_IO4 + G6_IO4 channel mode + 23 + 1 + + + G7_IO1 + G7_IO1 channel mode + 24 + 1 + + + G7_IO2 + G7_IO2 channel mode + 25 + 1 + + + G7_IO3 + G7_IO3 channel mode + 26 + 1 + + + G7_IO4 + G7_IO4 channel mode + 27 + 1 + + + G8_IO1 + G8_IO1 channel mode + 28 + 1 + + + G8_IO2 + G8_IO2 channel mode + 29 + 1 + + + G8_IO3 + G8_IO3 channel mode + 30 + 1 + + + G8_IO4 + G8_IO4 channel mode + 31 + 1 + + + + + IOGCSR + IOGCSR + I/O group control status + register + 0x30 + 0x20 + 0x00000000 + + + G8S + Analog I/O group x status + 23 + 1 + read-write + + + G7S + Analog I/O group x status + 22 + 1 + read-write + + + G6S + Analog I/O group x status + 21 + 1 + read-only + + + G5S + Analog I/O group x status + 20 + 1 + read-only + + + G4S + Analog I/O group x status + 19 + 1 + read-only + + + G3S + Analog I/O group x status + 18 + 1 + read-only + + + G2S + Analog I/O group x status + 17 + 1 + read-only + + + G1S + Analog I/O group x status + 16 + 1 + read-only + + + G8E + Analog I/O group x enable + 7 + 1 + read-write + + + G7E + Analog I/O group x enable + 6 + 1 + read-write + + + G6E + Analog I/O group x enable + 5 + 1 + read-write + + + G5E + Analog I/O group x enable + 4 + 1 + read-write + + + G4E + Analog I/O group x enable + 3 + 1 + read-write + + + G3E + Analog I/O group x enable + 2 + 1 + read-write + + + G2E + Analog I/O group x enable + 1 + 1 + read-write + + + G1E + Analog I/O group x enable + 0 + 1 + read-write + + + + + IOG1CR + IOG1CR + I/O group x counter register + 0x34 + 0x20 + read-only + 0x00000000 + + + CNT + Counter value + 0 + 14 + + + + + IOG2CR + IOG2CR + I/O group x counter register + 0x38 + 0x20 + read-only + 0x00000000 + + + CNT + Counter value + 0 + 14 + + + + + IOG3CR + IOG3CR + I/O group x counter register + 0x3C + 0x20 + read-only + 0x00000000 + + + CNT + Counter value + 0 + 14 + + + + + IOG4CR + IOG4CR + I/O group x counter register + 0x40 + 0x20 + read-only + 0x00000000 + + + CNT + Counter value + 0 + 14 + + + + + IOG5CR + IOG5CR + I/O group x counter register + 0x44 + 0x20 + read-only + 0x00000000 + + + CNT + Counter value + 0 + 14 + + + + + IOG6CR + IOG6CR + I/O group x counter register + 0x48 + 0x20 + read-only + 0x00000000 + + + CNT + Counter value + 0 + 14 + + + + + IOG7CR + IOG7CR + I/O group x counter register + 0x4C + 0x20 + read-only + 0x00000000 + + + CNT + Counter value + 0 + 14 + + + + + IOG8CR + IOG8CR + I/O group x counter register + 0x50 + 0x20 + read-only + 0x00000000 + + + CNT + Counter value + 0 + 14 + + + + + + + CRC + cyclic redundancy check calculation + unit + CRC + 0x40023000 + + 0x0 + 0x400 + registers + + + + DR + DR + Data register + 0x0 + 0x20 + read-write + 0xFFFFFFFF + + + DR + Data register bits + 0 + 32 + + + + + IDR + IDR + Independent data register + 0x4 + 0x20 + read-write + 0x00000000 + + + IDR + General-purpose 8-bit data register + bits + 0 + 8 + + + + + CR + CR + Control register + 0x8 + 0x20 + read-write + 0x00000000 + + + RESET + reset bit + 0 + 1 + + + POLYSIZE + Polynomial size + 3 + 2 + + + REV_IN + Reverse input data + 5 + 2 + + + REV_OUT + Reverse output data + 7 + 1 + + + + + INIT + INIT + Initial CRC value + 0x10 + 0x20 + read-write + 0xFFFFFFFF + + + INIT + Programmable initial CRC + value + 0 + 32 + + + + + POL + POL + CRC polynomial + 0x14 + 0x20 + read-write + 0x04C11DB7 + + + POL + Programmable polynomial + 0 + 32 + + + + + + + Flash + Flash + Flash + 0x40022000 + + 0x0 + 0x400 + registers + + + FLASH + Flash global interrupt + 4 + + + + ACR + ACR + Flash access control register + 0x0 + 0x20 + 0x00000030 + + + LATENCY + LATENCY + 0 + 3 + read-write + + + PRFTBE + PRFTBE + 4 + 1 + read-write + + + PRFTBS + PRFTBS + 5 + 1 + read-only + + + + + KEYR + KEYR + Flash key register + 0x4 + 0x20 + write-only + 0x00000000 + + + FKEYR + Flash Key + 0 + 32 + + + + + OPTKEYR + OPTKEYR + Flash option key register + 0x8 + 0x20 + write-only + 0x00000000 + + + OPTKEYR + Option byte key + 0 + 32 + + + + + SR + SR + Flash status register + 0xC + 0x20 + 0x00000000 + + + EOP + End of operation + 5 + 1 + read-write + + + WRPRT + Write protection error + 4 + 1 + read-write + + + PGERR + Programming error + 2 + 1 + read-write + + + BSY + Busy + 0 + 1 + read-only + + + + + CR + CR + Flash control register + 0x10 + 0x20 + read-write + 0x00000080 + + + FORCE_OPTLOAD + Force option byte loading + 13 + 1 + + + EOPIE + End of operation interrupt + enable + 12 + 1 + + + ERRIE + Error interrupt enable + 10 + 1 + + + OPTWRE + Option bytes write enable + 9 + 1 + + + LOCK + Lock + 7 + 1 + + + STRT + Start + 6 + 1 + + + OPTER + Option byte erase + 5 + 1 + + + OPTPG + Option byte programming + 4 + 1 + + + MER + Mass erase + 2 + 1 + + + PER + Page erase + 1 + 1 + + + PG + Programming + 0 + 1 + + + + + AR + AR + Flash address register + 0x14 + 0x20 + write-only + 0x00000000 + + + FAR + Flash address + 0 + 32 + + + + + OBR + OBR + Option byte register + 0x1C + 0x20 + read-only + 0xFFFFFF02 + + + OPTERR + Option byte error + 0 + 1 + + + LEVEL1_PROT + Level 1 protection status + 1 + 1 + + + LEVEL2_PROT + Level 2 protection status + 2 + 1 + + + WDG_SW + WDG_SW + 8 + 1 + + + nRST_STOP + nRST_STOP + 9 + 1 + + + nRST_STDBY + nRST_STDBY + 10 + 1 + + + BOOT1 + BOOT1 + 12 + 1 + + + VDDA_MONITOR + VDDA_MONITOR + 13 + 1 + + + SRAM_PARITY_CHECK + SRAM_PARITY_CHECK + 14 + 1 + + + Data0 + Data0 + 16 + 8 + + + Data1 + Data1 + 24 + 8 + + + + + WRPR + WRPR + Write protection register + 0x20 + 0x20 + read-only + 0xFFFFFFFF + + + WRP + Write protect + 0 + 32 + + + + + + + RCC + Reset and clock control + RCC + 0x40021000 + + 0x0 + 0x400 + registers + + + RCC + RCC global interrupt + 5 + + + + CR + CR + Clock control register + 0x0 + 0x20 + 0x00000083 + + + HSION + Internal High Speed clock + enable + 0 + 1 + read-write + + + HSIRDY + Internal High Speed clock ready + flag + 1 + 1 + read-only + + + HSITRIM + Internal High Speed clock + trimming + 3 + 5 + read-write + + + HSICAL + Internal High Speed clock + Calibration + 8 + 8 + read-only + + + HSEON + External High Speed clock + enable + 16 + 1 + read-write + + + HSERDY + External High Speed clock ready + flag + 17 + 1 + read-only + + + HSEBYP + External High Speed clock + Bypass + 18 + 1 + read-write + + + CSSON + Clock Security System + enable + 19 + 1 + read-write + + + PLLON + PLL enable + 24 + 1 + read-write + + + PLLRDY + PLL clock ready flag + 25 + 1 + read-only + + + + + CFGR + CFGR + Clock configuration register + (RCC_CFGR) + 0x4 + 0x20 + 0x00000000 + + + SW + System clock Switch + 0 + 2 + read-write + + + SWS + System Clock Switch Status + 2 + 2 + read-only + + + HPRE + AHB prescaler + 4 + 4 + read-write + + + PPRE1 + APB Low speed prescaler + (APB1) + 8 + 3 + read-write + + + PPRE2 + APB high speed prescaler + (APB2) + 11 + 3 + read-write + + + PLLSRC + PLL entry clock source + 15 + 2 + read-write + + + PLLXTPRE + HSE divider for PLL entry + 17 + 1 + read-write + + + PLLMUL + PLL Multiplication Factor + 18 + 4 + read-write + + + USBPRES + USB prescaler + 22 + 1 + read-write + + + MCO + Microcontroller clock + output + 24 + 3 + read-write + + + MCOF + Microcontroller Clock Output + Flag + 28 + 1 + read-only + + + I2SSRC + I2S external clock source + selection + 23 + 1 + read-write + + + + + CIR + CIR + Clock interrupt register + (RCC_CIR) + 0x8 + 0x20 + 0x00000000 + + + LSIRDYF + LSI Ready Interrupt flag + 0 + 1 + read-only + + + LSERDYF + LSE Ready Interrupt flag + 1 + 1 + read-only + + + HSIRDYF + HSI Ready Interrupt flag + 2 + 1 + read-only + + + HSERDYF + HSE Ready Interrupt flag + 3 + 1 + read-only + + + PLLRDYF + PLL Ready Interrupt flag + 4 + 1 + read-only + + + CSSF + Clock Security System Interrupt + flag + 7 + 1 + read-only + + + LSIRDYIE + LSI Ready Interrupt Enable + 8 + 1 + read-write + + + LSERDYIE + LSE Ready Interrupt Enable + 9 + 1 + read-write + + + HSIRDYIE + HSI Ready Interrupt Enable + 10 + 1 + read-write + + + HSERDYIE + HSE Ready Interrupt Enable + 11 + 1 + read-write + + + PLLRDYIE + PLL Ready Interrupt Enable + 12 + 1 + read-write + + + LSIRDYC + LSI Ready Interrupt Clear + 16 + 1 + write-only + + + LSERDYC + LSE Ready Interrupt Clear + 17 + 1 + write-only + + + HSIRDYC + HSI Ready Interrupt Clear + 18 + 1 + write-only + + + HSERDYC + HSE Ready Interrupt Clear + 19 + 1 + write-only + + + PLLRDYC + PLL Ready Interrupt Clear + 20 + 1 + write-only + + + CSSC + Clock security system interrupt + clear + 23 + 1 + write-only + + + + + APB2RSTR + APB2RSTR + APB2 peripheral reset register + (RCC_APB2RSTR) + 0xC + 0x20 + read-write + 0x00000000 + + + SYSCFGRST + SYSCFG and COMP reset + 0 + 1 + + + TIM1RST + TIM1 timer reset + 11 + 1 + + + SPI1RST + SPI 1 reset + 12 + 1 + + + TIM8RST + TIM8 timer reset + 13 + 1 + + + USART1RST + USART1 reset + 14 + 1 + + + TIM15RST + TIM15 timer reset + 16 + 1 + + + TIM16RST + TIM16 timer reset + 17 + 1 + + + TIM17RST + TIM17 timer reset + 18 + 1 + + + + + APB1RSTR + APB1RSTR + APB1 peripheral reset register + (RCC_APB1RSTR) + 0x10 + 0x20 + read-write + 0x00000000 + + + TIM2RST + Timer 2 reset + 0 + 1 + + + TIM3RST + Timer 3 reset + 1 + 1 + + + TIM4RST + Timer 14 reset + 2 + 1 + + + TIM6RST + Timer 6 reset + 4 + 1 + + + TIM7RST + Timer 7 reset + 5 + 1 + + + WWDGRST + Window watchdog reset + 11 + 1 + + + SPI2RST + SPI2 reset + 14 + 1 + + + SPI3RST + SPI3 reset + 15 + 1 + + + USART2RST + USART 2 reset + 17 + 1 + + + USART3RST + USART3 reset + 18 + 1 + + + UART4RST + UART 4 reset + 19 + 1 + + + UART5RST + UART 5 reset + 20 + 1 + + + I2C1RST + I2C1 reset + 21 + 1 + + + I2C2RST + I2C2 reset + 22 + 1 + + + USBRST + USB reset + 23 + 1 + + + CANRST + CAN reset + 25 + 1 + + + PWRRST + Power interface reset + 28 + 1 + + + DACRST + DAC interface reset + 29 + 1 + + + I2C3RST + I2C3 reset + 30 + 1 + + + + + AHBENR + AHBENR + AHB Peripheral Clock enable register + (RCC_AHBENR) + 0x14 + 0x20 + read-write + 0x00000014 + + + DMAEN + DMA1 clock enable + 0 + 1 + + + DMA2EN + DMA2 clock enable + 1 + 1 + + + SRAMEN + SRAM interface clock + enable + 2 + 1 + + + FLITFEN + FLITF clock enable + 4 + 1 + + + FMCEN + FMC clock enable + 5 + 1 + + + CRCEN + CRC clock enable + 6 + 1 + + + IOPHEN + IO port H clock enable + 16 + 1 + + + IOPAEN + I/O port A clock enable + 17 + 1 + + + IOPBEN + I/O port B clock enable + 18 + 1 + + + IOPCEN + I/O port C clock enable + 19 + 1 + + + IOPDEN + I/O port D clock enable + 20 + 1 + + + IOPEEN + I/O port E clock enable + 21 + 1 + + + IOPFEN + I/O port F clock enable + 22 + 1 + + + IOPGEN + I/O port G clock enable + 23 + 1 + + + TSCEN + Touch sensing controller clock + enable + 24 + 1 + + + ADC12EN + ADC1 and ADC2 clock enable + 28 + 1 + + + ADC34EN + ADC3 and ADC4 clock enable + 29 + 1 + + + + + APB2ENR + APB2ENR + APB2 peripheral clock enable register + (RCC_APB2ENR) + 0x18 + 0x20 + read-write + 0x00000000 + + + SYSCFGEN + SYSCFG clock enable + 0 + 1 + + + TIM1EN + TIM1 Timer clock enable + 11 + 1 + + + SPI1EN + SPI 1 clock enable + 12 + 1 + + + TIM8EN + TIM8 Timer clock enable + 13 + 1 + + + USART1EN + USART1 clock enable + 14 + 1 + + + TIM15EN + TIM15 timer clock enable + 16 + 1 + + + TIM16EN + TIM16 timer clock enable + 17 + 1 + + + TIM17EN + TIM17 timer clock enable + 18 + 1 + + + + + APB1ENR + APB1ENR + APB1 peripheral clock enable register + (RCC_APB1ENR) + 0x1C + 0x20 + read-write + 0x00000000 + + + TIM2EN + Timer 2 clock enable + 0 + 1 + + + TIM3EN + Timer 3 clock enable + 1 + 1 + + + TIM4EN + Timer 4 clock enable + 2 + 1 + + + TIM6EN + Timer 6 clock enable + 4 + 1 + + + TIM7EN + Timer 7 clock enable + 5 + 1 + + + WWDGEN + Window watchdog clock + enable + 11 + 1 + + + SPI2EN + SPI 2 clock enable + 14 + 1 + + + SPI3EN + SPI 3 clock enable + 15 + 1 + + + USART2EN + USART 2 clock enable + 17 + 1 + + + USART3EN + USART 3 clock enable + 18 + 1 + + + USART4EN + USART 4 clock enable + 19 + 1 + + + USART5EN + USART 5 clock enable + 20 + 1 + + + I2C1EN + I2C 1 clock enable + 21 + 1 + + + I2C2EN + I2C 2 clock enable + 22 + 1 + + + USBEN + USB clock enable + 23 + 1 + + + CANEN + CAN clock enable + 25 + 1 + + + DAC2EN + DAC2 interface clock + enable + 26 + 1 + + + PWREN + Power interface clock + enable + 28 + 1 + + + DACEN + DAC interface clock enable + 29 + 1 + + + I2C3EN + I2C3 clock enable + 30 + 1 + + + + + BDCR + BDCR + Backup domain control register + (RCC_BDCR) + 0x20 + 0x20 + 0x00000000 + + + LSEON + External Low Speed oscillator + enable + 0 + 1 + read-write + + + LSERDY + External Low Speed oscillator + ready + 1 + 1 + read-only + + + LSEBYP + External Low Speed oscillator + bypass + 2 + 1 + read-write + + + LSEDRV + LSE oscillator drive + capability + 3 + 2 + read-write + + + RTCSEL + RTC clock source selection + 8 + 2 + read-write + + + RTCEN + RTC clock enable + 15 + 1 + read-write + + + BDRST + Backup domain software + reset + 16 + 1 + read-write + + + + + CSR + CSR + Control/status register + (RCC_CSR) + 0x24 + 0x20 + 0x0C000000 + + + LSION + Internal low speed oscillator + enable + 0 + 1 + read-write + + + LSIRDY + Internal low speed oscillator + ready + 1 + 1 + read-only + + + RMVF + Remove reset flag + 24 + 1 + read-write + + + OBLRSTF + Option byte loader reset + flag + 25 + 1 + read-write + + + PINRSTF + PIN reset flag + 26 + 1 + read-write + + + PORRSTF + POR/PDR reset flag + 27 + 1 + read-write + + + SFTRSTF + Software reset flag + 28 + 1 + read-write + + + IWDGRSTF + Independent watchdog reset + flag + 29 + 1 + read-write + + + WWDGRSTF + Window watchdog reset flag + 30 + 1 + read-write + + + LPWRRSTF + Low-power reset flag + 31 + 1 + read-write + + + + + AHBRSTR + AHBRSTR + AHB peripheral reset register + 0x28 + 0x20 + read-write + 0x00000000 + + + FMCRST + FMC reset + 5 + 1 + + + IOPHRST + I/O port H reset + 16 + 1 + + + IOPARST + I/O port A reset + 17 + 1 + + + IOPBRST + I/O port B reset + 18 + 1 + + + IOPCRST + I/O port C reset + 19 + 1 + + + IOPDRST + I/O port D reset + 20 + 1 + + + IOPERST + I/O port E reset + 21 + 1 + + + IOPFRST + I/O port F reset + 22 + 1 + + + IOPGRST + Touch sensing controller + reset + 23 + 1 + + + TSCRST + Touch sensing controller + reset + 24 + 1 + + + ADC12RST + ADC1 and ADC2 reset + 28 + 1 + + + ADC34RST + ADC3 and ADC4 reset + 29 + 1 + + + + + CFGR2 + CFGR2 + Clock configuration register 2 + 0x2C + 0x20 + read-write + 0x00000000 + + + PREDIV + PREDIV division factor + 0 + 4 + + + ADC12PRES + ADC1 and ADC2 prescaler + 4 + 5 + + + ADC34PRES + ADC3 and ADC4 prescaler + 9 + 5 + + + + + CFGR3 + CFGR3 + Clock configuration register 3 + 0x30 + 0x20 + read-write + 0x00000000 + + + USART1SW + USART1 clock source + selection + 0 + 2 + + + I2C1SW + I2C1 clock source + selection + 4 + 1 + + + I2C2SW + I2C2 clock source + selection + 5 + 1 + + + I2C3SW + I2C3 clock source + selection + 6 + 1 + + + USART2SW + USART2 clock source + selection + 16 + 2 + + + USART3SW + USART3 clock source + selection + 18 + 2 + + + TIM1SW + Timer1 clock source + selection + 8 + 1 + + + TIM8SW + Timer8 clock source + selection + 9 + 1 + + + UART4SW + UART4 clock source + selection + 20 + 2 + + + UART5SW + UART5 clock source + selection + 22 + 2 + + + + + + + DMA1 + DMA controller 1 + DMA + 0x40020000 + + 0x0 + 0x400 + registers + + + DMA1_CH1 + DMA1 channel 1 interrupt + 11 + + + DMA1_CH2 + DMA1 channel 2 interrupt + 12 + + + DMA1_CH3 + DMA1 channel 3 interrupt + 13 + + + DMA1_CH4 + DMA1 channel 4 interrupt + 14 + + + DMA1_CH5 + DMA1 channel 5 interrupt + 15 + + + DMA1_CH6 + DMA1 channel 6 interrupt + 16 + + + DMA1_CH7 + DMA1 channel 7interrupt + 17 + + + + ISR + ISR + DMA interrupt status register + (DMA_ISR) + 0x0 + 0x20 + read-only + 0x00000000 + + + GIF1 + Channel 1 Global interrupt + flag + 0 + 1 + + + TCIF1 + Channel 1 Transfer Complete + flag + 1 + 1 + + + HTIF1 + Channel 1 Half Transfer Complete + flag + 2 + 1 + + + TEIF1 + Channel 1 Transfer Error + flag + 3 + 1 + + + GIF2 + Channel 2 Global interrupt + flag + 4 + 1 + + + TCIF2 + Channel 2 Transfer Complete + flag + 5 + 1 + + + HTIF2 + Channel 2 Half Transfer Complete + flag + 6 + 1 + + + TEIF2 + Channel 2 Transfer Error + flag + 7 + 1 + + + GIF3 + Channel 3 Global interrupt + flag + 8 + 1 + + + TCIF3 + Channel 3 Transfer Complete + flag + 9 + 1 + + + HTIF3 + Channel 3 Half Transfer Complete + flag + 10 + 1 + + + TEIF3 + Channel 3 Transfer Error + flag + 11 + 1 + + + GIF4 + Channel 4 Global interrupt + flag + 12 + 1 + + + TCIF4 + Channel 4 Transfer Complete + flag + 13 + 1 + + + HTIF4 + Channel 4 Half Transfer Complete + flag + 14 + 1 + + + TEIF4 + Channel 4 Transfer Error + flag + 15 + 1 + + + GIF5 + Channel 5 Global interrupt + flag + 16 + 1 + + + TCIF5 + Channel 5 Transfer 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register 3 + 0x8 + 0x20 + read-write + 0x0000 + + + WUFIE + Wakeup from Stop mode interrupt + enable + 22 + 1 + + + WUS + Wakeup from Stop mode interrupt flag + selection + 20 + 2 + + + SCARCNT + Smartcard auto-retry count + 17 + 3 + + + DEP + Driver enable polarity + selection + 15 + 1 + + + DEM + Driver enable mode + 14 + 1 + + + DDRE + DMA Disable on Reception + Error + 13 + 1 + + + OVRDIS + Overrun Disable + 12 + 1 + + + ONEBIT + One sample bit method + enable + 11 + 1 + + + CTSIE + CTS interrupt enable + 10 + 1 + + + CTSE + CTS enable + 9 + 1 + + + RTSE + RTS enable + 8 + 1 + + + DMAT + DMA enable transmitter + 7 + 1 + + + DMAR + DMA enable receiver + 6 + 1 + + + SCEN + Smartcard mode enable + 5 + 1 + + + NACK + Smartcard NACK enable + 4 + 1 + + + HDSEL + Half-duplex selection + 3 + 1 + + + IRLP + IrDA low-power + 2 + 1 + + + IREN + IrDA mode enable + 1 + 1 + + + EIE + Error interrupt enable + 0 + 1 + + + + + BRR + BRR + Baud rate register + 0xC + 0x20 + read-write + 0x0000 + + + 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+ 5 + 1 + + + ADD6 + Device address + 6 + 1 + + + EF + Enable function + 7 + 1 + + + + + BTABLE + BTABLE + Buffer table address + 0x50 + 0x20 + read-write + 0x0000 + + + BTABLE + Buffer table + 3 + 13 + + + + + + + I2C1 + Inter-integrated circuit + I2C + 0x40005400 + + 0x0 + 0x400 + registers + + + I2C1_EV_EXTI23 + I2C1 event interrupt and EXTI Line23 + interrupt + 31 + + + I2C1_EV_EXTI23 + I2C1 event interrupt and EXTI Line23 + interrupt + 31 + + + I2C1_ER + I2C1 error interrupt + 32 + + + + CR1 + CR1 + Control register 1 + 0x0 + 0x20 + 0x00000000 + + + PE + Peripheral enable + 0 + 1 + read-write + + + TXIE + TX Interrupt enable + 1 + 1 + read-write + + + RXIE + RX Interrupt enable + 2 + 1 + read-write + + + ADDRIE + Address match interrupt enable (slave + only) + 3 + 1 + read-write + + + NACKIE + Not acknowledge received interrupt + enable + 4 + 1 + read-write + + + STOPIE + STOP detection Interrupt + enable + 5 + 1 + read-write + + + TCIE + Transfer Complete interrupt + enable + 6 + 1 + read-write + + + ERRIE + Error interrupts enable + 7 + 1 + read-write + + + DNF + Digital noise filter + 8 + 4 + read-write + + + ANFOFF + Analog noise filter OFF + 12 + 1 + read-write + + + SWRST + Software reset + 13 + 1 + write-only + + + TXDMAEN + DMA transmission requests + enable + 14 + 1 + read-write + + + RXDMAEN + DMA reception requests + enable + 15 + 1 + read-write + + + SBC + Slave byte control + 16 + 1 + read-write + + + NOSTRETCH + Clock stretching disable + 17 + 1 + read-write + + + WUPEN + Wakeup from STOP enable + 18 + 1 + read-write + + + GCEN + General call enable + 19 + 1 + read-write + + + SMBHEN + SMBus Host address enable + 20 + 1 + read-write + + + SMBDEN + SMBus Device Default address + enable + 21 + 1 + read-write + + + ALERTEN + SMBUS alert enable + 22 + 1 + read-write + + + PECEN + PEC enable + 23 + 1 + read-write + + + + + CR2 + CR2 + Control register 2 + 0x4 + 0x20 + read-write + 0x00000000 + + + PECBYTE + Packet error checking byte + 26 + 1 + + + AUTOEND + Automatic end mode (master + mode) + 25 + 1 + + + RELOAD + NBYTES reload mode + 24 + 1 + + + NBYTES + Number of bytes + 16 + 8 + + + NACK + NACK generation (slave + mode) + 15 + 1 + + + STOP + Stop generation (master + mode) + 14 + 1 + + + START + Start generation + 13 + 1 + + + HEAD10R + 10-bit address header only read + direction (master receiver mode) + 12 + 1 + + + ADD10 + 10-bit addressing mode (master + mode) + 11 + 1 + + + RD_WRN + Transfer direction (master + mode) + 10 + 1 + + + SADD8 + Slave address bit 9:8 (master + mode) + 8 + 2 + + + SADD1 + Slave address bit 7:1 (master + mode) + 1 + 7 + + + SADD0 + Slave address bit 0 (master + mode) + 0 + 1 + + + + + OAR1 + OAR1 + Own address register 1 + 0x8 + 0x20 + read-write + 0x00000000 + + + OA1_0 + Interface address + 0 + 1 + + + OA1_1 + Interface address + 1 + 7 + + + OA1_8 + Interface address + 8 + 2 + + + OA1MODE + Own Address 1 10-bit mode + 10 + 1 + + + OA1EN + Own Address 1 enable + 15 + 1 + + + + + OAR2 + OAR2 + Own address register 2 + 0xC + 0x20 + read-write + 0x00000000 + + + OA2 + Interface address + 1 + 7 + + + OA2MSK + Own Address 2 masks + 8 + 3 + + + OA2EN + Own Address 2 enable + 15 + 1 + + + + + TIMINGR + TIMINGR + Timing register + 0x10 + 0x20 + read-write + 0x00000000 + + + SCLL + SCL low period (master + mode) + 0 + 8 + + + SCLH + SCL high period (master + mode) + 8 + 8 + + + SDADEL + Data hold time + 16 + 4 + + + SCLDEL + Data setup time + 20 + 4 + + + PRESC + Timing prescaler + 28 + 4 + + + + + TIMEOUTR + TIMEOUTR + Status register 1 + 0x14 + 0x20 + read-write + 0x00000000 + + + TIMEOUTA + Bus timeout A + 0 + 12 + + + TIDLE + Idle clock timeout + detection + 12 + 1 + + + TIMOUTEN + Clock timeout enable + 15 + 1 + + + TIMEOUTB + Bus timeout B + 16 + 12 + + + TEXTEN + Extended clock timeout + enable + 31 + 1 + + + + + ISR + ISR + Interrupt and Status register + 0x18 + 0x20 + 0x00000001 + + + ADDCODE + Address match code (Slave + mode) + 17 + 7 + read-only + + + DIR + Transfer direction (Slave + mode) + 16 + 1 + read-only + + + BUSY + Bus busy + 15 + 1 + read-only + + + ALERT + SMBus alert + 13 + 1 + read-only + + + TIMEOUT + Timeout or t_low detection + flag + 12 + 1 + read-only + + + PECERR + PEC Error in reception + 11 + 1 + read-only + + + OVR + Overrun/Underrun (slave + mode) + 10 + 1 + read-only + + + ARLO + Arbitration lost + 9 + 1 + read-only + + + BERR + Bus error + 8 + 1 + read-only + + + TCR + Transfer Complete Reload + 7 + 1 + read-only + + + TC + Transfer Complete (master + mode) + 6 + 1 + read-only + + + STOPF + Stop detection flag + 5 + 1 + read-only + + + NACKF + Not acknowledge received + flag + 4 + 1 + read-only + + + ADDR + Address matched (slave + mode) + 3 + 1 + read-only + + + RXNE + Receive data register not empty + (receivers) + 2 + 1 + read-only + + + TXIS + Transmit interrupt status + (transmitters) + 1 + 1 + read-write + + + TXE + Transmit data register empty + (transmitters) + 0 + 1 + read-write + + + + + ICR + ICR + Interrupt clear register + 0x1C + 0x20 + write-only + 0x00000000 + + + ALERTCF + Alert flag clear + 13 + 1 + + + TIMOUTCF + Timeout detection flag + clear + 12 + 1 + + + PECCF + PEC Error flag clear + 11 + 1 + + + OVRCF + Overrun/Underrun flag + clear + 10 + 1 + + + ARLOCF + Arbitration lost flag + clear + 9 + 1 + + + BERRCF + Bus error flag clear + 8 + 1 + + + STOPCF + Stop detection flag clear + 5 + 1 + + + NACKCF + Not Acknowledge flag clear + 4 + 1 + + + ADDRCF + Address Matched flag clear + 3 + 1 + + + + + PECR + PECR + PEC register + 0x20 + 0x20 + read-only + 0x00000000 + + + PEC + Packet error checking + register + 0 + 8 + + + + + RXDR + RXDR + Receive data register + 0x24 + 0x20 + read-only + 0x00000000 + + + RXDATA + 8-bit receive data + 0 + 8 + + + + + TXDR + TXDR + Transmit data register + 0x28 + 0x20 + read-write + 0x00000000 + + + TXDATA + 8-bit transmit data + 0 + 8 + + + + + + + I2C2 + 0x40005800 + + I2C2_EV_EXTI24 + I2C2 event interrupt & EXTI Line24 + interrupt + 33 + + + I2C2_ER + I2C2 error interrupt + 34 + + + + I2C3 + 0x40007800 + + I2C3_EV + I2C3 Event interrupt + 72 + + + I2C3_ER + I2C3 Error interrupt + 73 + + + + IWDG + Independent watchdog + IWDG + 0x40003000 + + 0x0 + 0x400 + registers + + + + KR + KR + Key register + 0x0 + 0x20 + write-only + 0x00000000 + + + KEY + Key value + 0 + 16 + + + + + PR + PR + Prescaler register + 0x4 + 0x20 + read-write + 0x00000000 + + + PR + Prescaler divider + 0 + 3 + + + + + RLR + RLR + Reload register + 0x8 + 0x20 + read-write + 0x00000FFF + + + RL + Watchdog counter reload + value + 0 + 12 + + + + + SR + SR + Status register + 0xC + 0x20 + read-only + 0x00000000 + + + PVU + Watchdog prescaler value + update + 0 + 1 + + + RVU + Watchdog counter reload value + update + 1 + 1 + + + WVU + Watchdog counter window value + update + 2 + 1 + + + + + WINR + WINR + Window register + 0x10 + 0x20 + read-write + 0x00000FFF + + + WIN + Watchdog counter window + value + 0 + 12 + + + + + + + WWDG + Window watchdog + WWDG + 0x40002C00 + + 0x0 + 0x400 + registers + + + WWDG + Window Watchdog interrupt + 0 + + + + CR + CR + Control register + 0x0 + 0x20 + read-write + 0x0000007F + + + T + 7-bit counter + 0 + 7 + + + WDGA + Activation bit + 7 + 1 + + + + + CFR + CFR + Configuration register + 0x4 + 0x20 + read-write + 0x0000007F + + + EWI + Early wakeup interrupt + 9 + 1 + + + WDGTB + Timer base + 7 + 2 + + + W + 7-bit window value + 0 + 7 + + + + + SR + SR + Status register + 0x8 + 0x20 + read-write + 0x00000000 + + + EWIF + Early wakeup interrupt + flag + 0 + 1 + + + + + + + RTC + Real-time clock + RTC + 0x40002800 + + 0x0 + 0x400 + registers + + + RTC_WKUP + RTC Wakeup interrupt through the EXTI + line + 3 + + + RTCAlarm + RTC alarm interrupt + 41 + + + + TR + TR + time register + 0x0 + 0x20 + read-write + 0x00000000 + + + PM + AM/PM notation + 22 + 1 + + + HT + Hour tens in BCD format + 20 + 2 + + + HU + Hour units in BCD format + 16 + 4 + + + MNT + Minute tens in BCD format + 12 + 3 + + + MNU + Minute units in BCD format + 8 + 4 + + + ST + Second tens in BCD format + 4 + 3 + + + SU + Second units in BCD format + 0 + 4 + + + + + DR + DR + date register + 0x4 + 0x20 + read-write + 0x00002101 + + + YT + Year tens in BCD format + 20 + 4 + + + YU + Year units in BCD format + 16 + 4 + + + WDU + Week day units + 13 + 3 + + + MT + Month tens in BCD format + 12 + 1 + + + MU + Month units in BCD format + 8 + 4 + + + DT + Date tens in BCD format + 4 + 2 + + + DU + Date units in BCD format + 0 + 4 + + + + + CR + CR + control register + 0x8 + 0x20 + read-write + 0x00000000 + + + WCKSEL + Wakeup clock selection + 0 + 3 + + + TSEDGE + Time-stamp event active + edge + 3 + 1 + + + REFCKON + Reference clock detection enable (50 or + 60 Hz) + 4 + 1 + + + BYPSHAD + Bypass the shadow + registers + 5 + 1 + + + FMT + Hour format + 6 + 1 + + + ALRAE + Alarm A enable + 8 + 1 + + + ALRBE + Alarm B enable + 9 + 1 + + + WUTE + Wakeup timer enable + 10 + 1 + + + TSE + Time stamp enable + 11 + 1 + + + ALRAIE + Alarm A interrupt enable + 12 + 1 + + + ALRBIE + Alarm B interrupt enable + 13 + 1 + + + WUTIE + Wakeup timer interrupt + enable + 14 + 1 + + + TSIE + Time-stamp interrupt + enable + 15 + 1 + + + ADD1H + Add 1 hour (summer time + change) + 16 + 1 + + + SUB1H + Subtract 1 hour (winter time + change) + 17 + 1 + + + BKP + Backup + 18 + 1 + + + COSEL + Calibration output + selection + 19 + 1 + + + POL + Output polarity + 20 + 1 + + + OSEL + Output selection + 21 + 2 + + + COE + Calibration output enable + 23 + 1 + + + + + ISR + ISR + initialization and status + register + 0xC + 0x20 + 0x00000007 + + + ALRAWF + Alarm A write flag + 0 + 1 + read-only + + + ALRBWF + Alarm B write flag + 1 + 1 + read-only + + + WUTWF + Wakeup timer write flag + 2 + 1 + read-only + + + SHPF + Shift operation pending + 3 + 1 + read-write + + + INITS + Initialization status flag + 4 + 1 + read-only + + + RSF + Registers synchronization + flag + 5 + 1 + read-write + + + INITF + Initialization flag + 6 + 1 + read-only + + + INIT + Initialization mode + 7 + 1 + read-write + + + ALRAF + Alarm A flag + 8 + 1 + read-write + + + ALRBF + Alarm B flag + 9 + 1 + read-write + + + WUTF + Wakeup timer flag + 10 + 1 + read-write + + + TSF + Time-stamp flag + 11 + 1 + read-write + + + TSOVF + Time-stamp overflow flag + 12 + 1 + read-write + + + TAMP1F + Tamper detection flag + 13 + 1 + read-write + + + TAMP2F + RTC_TAMP2 detection flag + 14 + 1 + read-write + + + TAMP3F + RTC_TAMP3 detection flag + 15 + 1 + read-write + + + RECALPF + Recalibration pending Flag + 16 + 1 + read-only + + + + + PRER + PRER + prescaler register + 0x10 + 0x20 + read-write + 0x007F00FF + + + PREDIV_A + Asynchronous prescaler + factor + 16 + 7 + + + PREDIV_S + Synchronous prescaler + factor + 0 + 15 + + + + + WUTR + WUTR + wakeup timer register + 0x14 + 0x20 + read-write + 0x0000FFFF + + + WUT + Wakeup auto-reload value + bits + 0 + 16 + + + + + ALRMAR + ALRMAR + alarm A register + 0x1C + 0x20 + read-write + 0x00000000 + + + MSK4 + Alarm A date mask + 31 + 1 + + + WDSEL + Week day selection + 30 + 1 + + + DT + Date tens in BCD format + 28 + 2 + + + DU + Date units or day in BCD + format + 24 + 4 + + + MSK3 + Alarm A hours mask + 23 + 1 + + + PM + AM/PM notation + 22 + 1 + + + HT + Hour tens in BCD format + 20 + 2 + + + HU + Hour units in BCD format + 16 + 4 + + + MSK2 + Alarm A minutes mask + 15 + 1 + + + MNT + Minute tens in BCD format + 12 + 3 + + + MNU + Minute units in BCD format + 8 + 4 + + + MSK1 + Alarm A seconds mask + 7 + 1 + + + ST + Second tens in BCD format + 4 + 3 + + + SU + Second units in BCD format + 0 + 4 + + + + + ALRMBR + ALRMBR + alarm B register + 0x20 + 0x20 + read-write + 0x00000000 + + + MSK4 + Alarm B date mask + 31 + 1 + + + WDSEL + Week day selection + 30 + 1 + + + DT + Date tens in BCD format + 28 + 2 + + + DU + Date units or day in BCD + format + 24 + 4 + + + MSK3 + Alarm B hours mask + 23 + 1 + + + PM + AM/PM notation + 22 + 1 + + + HT + Hour tens in BCD format + 20 + 2 + + + HU + Hour units in BCD format + 16 + 4 + + + MSK2 + Alarm B minutes mask + 15 + 1 + + + MNT + Minute tens in BCD format + 12 + 3 + + + MNU + Minute units in BCD format + 8 + 4 + + + MSK1 + Alarm B seconds mask + 7 + 1 + + + ST + Second tens in BCD format + 4 + 3 + + + SU + Second units in BCD format + 0 + 4 + + + + + WPR + WPR + write protection register + 0x24 + 0x20 + write-only + 0x00000000 + + + KEY + Write protection key + 0 + 8 + + + + + SSR + SSR + sub second register + 0x28 + 0x20 + read-only + 0x00000000 + + + SS + Sub second value + 0 + 16 + + + + + SHIFTR + SHIFTR + shift control register + 0x2C + 0x20 + write-only + 0x00000000 + + + ADD1S + Add one second + 31 + 1 + + + SUBFS + Subtract a fraction of a + second + 0 + 15 + + + + + TSTR + TSTR + time stamp time register + 0x30 + 0x20 + read-only + 0x00000000 + + + SU + Second units in BCD format + 0 + 4 + + + ST + Second tens in BCD format + 4 + 3 + + + MNU + Minute units in BCD format + 8 + 4 + + + MNT + Minute tens in BCD format + 12 + 3 + + + HU + Hour units in BCD format + 16 + 4 + + + HT + Hour tens in BCD format + 20 + 2 + + + PM + AM/PM notation + 22 + 1 + + + + + TSDR + TSDR + time stamp date register + 0x34 + 0x20 + read-only + 0x00000000 + + + WDU + Week day units + 13 + 3 + + + MT + Month tens in BCD format + 12 + 1 + + + MU + Month units in BCD format + 8 + 4 + + + DT + Date tens in BCD format + 4 + 2 + + + DU + Date units in BCD format + 0 + 4 + + + + + TSSSR + TSSSR + timestamp sub second register + 0x38 + 0x20 + read-only + 0x00000000 + + + SS + Sub second value + 0 + 16 + + + + + CALR + CALR + calibration register + 0x3C + 0x20 + read-write + 0x00000000 + + + CALP + Increase frequency of RTC by 488.5 + ppm + 15 + 1 + + + CALW8 + Use an 8-second calibration cycle + period + 14 + 1 + + + CALW16 + Use a 16-second calibration cycle + period + 13 + 1 + + + CALM + Calibration minus + 0 + 9 + + + + + TAFCR + TAFCR + tamper and alternate function configuration + register + 0x40 + 0x20 + read-write + 0x00000000 + + + TAMP1E + Tamper 1 detection enable + 0 + 1 + + + TAMP1TRG + Active level for tamper 1 + 1 + 1 + + + TAMPIE + Tamper interrupt enable + 2 + 1 + + + TAMP2E + Tamper 2 detection enable + 3 + 1 + + + TAMP2TRG + Active level for tamper 2 + 4 + 1 + + + TAMP3E + Tamper 3 detection enable + 5 + 1 + + + TAMP3TRG + Active level for tamper 3 + 6 + 1 + + + TAMPTS + Activate timestamp on tamper detection + event + 7 + 1 + + + TAMPFREQ + Tamper sampling frequency + 8 + 3 + + + TAMPFLT + Tamper filter count + 11 + 2 + + + TAMPPRCH + Tamper precharge duration + 13 + 2 + + + TAMPPUDIS + TAMPER pull-up disable + 15 + 1 + + + PC13VALUE + PC13 value + 18 + 1 + + + PC13MODE + PC13 mode + 19 + 1 + + + PC14VALUE + PC14 value + 20 + 1 + + + PC14MODE + PC 14 mode + 21 + 1 + + + PC15VALUE + PC15 value + 22 + 1 + + + PC15MODE + PC15 mode + 23 + 1 + + + + + ALRMASSR + ALRMASSR + alarm A sub second register + 0x44 + 0x20 + read-write + 0x00000000 + + + MASKSS + Mask the most-significant bits starting + at this bit + 24 + 4 + + + SS + Sub seconds value + 0 + 15 + + + + + ALRMBSSR + ALRMBSSR + alarm B sub second register + 0x48 + 0x20 + read-write + 0x00000000 + + + MASKSS + Mask the most-significant bits starting + at this bit + 24 + 4 + + + SS + Sub seconds value + 0 + 15 + + + + + BKP0R + BKP0R + backup register + 0x50 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP1R + BKP1R + backup register + 0x54 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP2R + BKP2R + backup register + 0x58 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP3R + BKP3R + backup register + 0x5C + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP4R + BKP4R + backup register + 0x60 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP5R + BKP5R + backup register + 0x64 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP6R + BKP6R + backup register + 0x68 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP7R + BKP7R + backup register + 0x6C + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP8R + BKP8R + backup register + 0x70 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP9R + BKP9R + backup register + 0x74 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP10R + BKP10R + backup register + 0x78 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP11R + BKP11R + backup register + 0x7C + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP12R + BKP12R + backup register + 0x80 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP13R + BKP13R + backup register + 0x84 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP14R + BKP14R + backup register + 0x88 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP15R + BKP15R + backup register + 0x8C + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP16R + BKP16R + backup register + 0x90 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP17R + BKP17R + backup register + 0x94 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP18R + BKP18R + backup register + 0x98 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP19R + BKP19R + backup register + 0x9C + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP20R + BKP20R + backup register + 0xA0 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP21R + BKP21R + backup register + 0xA4 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP22R + BKP22R + backup register + 0xA8 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP23R + BKP23R + backup register + 0xAC + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP24R + BKP24R + backup register + 0xB0 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP25R + BKP25R + backup register + 0xB4 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP26R + BKP26R + backup register + 0xB8 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP27R + BKP27R + backup register + 0xBC + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP28R + BKP28R + backup register + 0xC0 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP29R + BKP29R + backup register + 0xC4 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP30R + BKP30R + backup register + 0xC8 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP31R + BKP31R + backup register + 0xCC + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + + + TIM6 + Basic timers + TIMs + 0x40001000 + + 0x0 + 0x400 + registers + + + TIM6_DACUNDER + TIM6 global and DAC12 underrun + interrupts + 54 + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + CEN + Counter enable + 0 + 1 + + + UDIS + Update disable + 1 + 1 + + + URS + Update request source + 2 + 1 + + + OPM + One-pulse mode + 3 + 1 + + + ARPE + Auto-reload preload enable + 7 + 1 + + + UIFREMAP + UIF status bit remapping + 11 + 1 + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + MMS + Master mode selection + 4 + 3 + + + + + DIER + DIER + DMA/Interrupt enable register + 0xC + 0x20 + read-write + 0x0000 + + + UDE + Update DMA request enable + 8 + 1 + + + UIE + Update interrupt enable + 0 + 1 + + + + + SR + SR + status register + 0x10 + 0x20 + read-write + 0x0000 + + + UIF + Update interrupt flag + 0 + 1 + + + + + EGR + EGR + event generation register + 0x14 + 0x20 + write-only + 0x0000 + + + UG + Update generation + 0 + 1 + + + + + CNT + CNT + counter + 0x24 + 0x20 + 0x00000000 + + + CNT + Low counter value + 0 + 16 + read-write + + + UIFCPY + UIF Copy + 31 + 1 + read-only + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x0000 + + + PSC + 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0x24 + 0x20 + read-write + 0x00000000 + + + DACC2DHR + DAC channel2 12-bit left-aligned + data + 20 + 12 + + + DACC1DHR + DAC channel1 12-bit left-aligned + data + 4 + 12 + + + + + DHR8RD + DHR8RD + DUAL DAC 8-bit right aligned data holding + register + 0x28 + 0x20 + read-write + 0x00000000 + + + DACC2DHR + DAC channel2 8-bit right-aligned + data + 8 + 8 + + + DACC1DHR + DAC channel1 8-bit right-aligned + data + 0 + 8 + + + + + DOR1 + DOR1 + channel1 data output register + 0x2C + 0x20 + read-only + 0x00000000 + + + DACC1DOR + DAC channel1 data output + 0 + 12 + + + + + DOR2 + DOR2 + channel2 data output register + 0x30 + 0x20 + read-only + 0x00000000 + + + DACC2DOR + DAC channel2 data output + 0 + 12 + + + + + SR + SR + status register + 0x34 + 0x20 + read-write + 0x00000000 + + + DMAUDR2 + DAC channel2 DMA underrun + flag + 29 + 1 + + + DMAUDR1 + DAC channel1 DMA underrun + flag + 13 + 1 + + + + + + + DBGMCU + Debug support + DBGMCU + 0xE0042000 + + 0x0 + 0x400 + registers + + + + IDCODE + IDCODE + MCU Device ID Code Register + 0x0 + 0x20 + read-only + 0x0 + + + DEV_ID + Device Identifier + 0 + 12 + + + REV_ID + Revision Identifier + 16 + 16 + + + + + CR + CR + Debug MCU Configuration + Register + 0x4 + 0x20 + read-write + 0x0 + + + DBG_SLEEP + Debug Sleep mode + 0 + 1 + + + DBG_STOP + Debug Stop Mode + 1 + 1 + + + DBG_STANDBY + Debug Standby Mode + 2 + 1 + + + TRACE_IOEN + Trace pin assignment + control + 5 + 1 + + + TRACE_MODE + Trace pin assignment + control + 6 + 2 + + + + + APB1FZ + APB1FZ + APB Low Freeze Register + 0x8 + 0x20 + read-write + 0x0 + + + DBG_TIM2_STOP + Debug Timer 2 stopped when Core is + halted + 0 + 1 + + + DBG_TIM3_STOP + Debug Timer 3 stopped when Core is + halted + 1 + 1 + + + DBG_TIM4_STOP + Debug Timer 4 stopped when Core is + halted + 2 + 1 + + + DBG_TIM5_STOP + Debug Timer 5 stopped when Core is + halted + 3 + 1 + + + DBG_TIM6_STOP + Debug Timer 6 stopped when Core is + halted + 4 + 1 + + + DBG_TIM7_STOP + Debug Timer 7 stopped when Core is + halted + 5 + 1 + + + DBG_TIM12_STOP + Debug Timer 12 stopped when Core is + halted + 6 + 1 + + + DBG_TIM13_STOP + Debug Timer 13 stopped when Core is + halted + 7 + 1 + + + DBG_TIMER14_STOP + Debug Timer 14 stopped when Core is + halted + 8 + 1 + + + DBG_TIM18_STOP + Debug Timer 18 stopped when Core is + halted + 9 + 1 + + + DBG_RTC_STOP + Debug RTC stopped when Core is + halted + 10 + 1 + + + DBG_WWDG_STOP + Debug Window Wachdog stopped when Core + is halted + 11 + 1 + + + DBG_IWDG_STOP + Debug Independent Wachdog stopped when + Core is halted + 12 + 1 + + + I2C1_SMBUS_TIMEOUT + SMBUS timeout mode stopped when Core is + halted + 21 + 1 + + + I2C2_SMBUS_TIMEOUT + SMBUS timeout mode stopped when Core is + halted + 22 + 1 + + + DBG_CAN_STOP + Debug CAN stopped when core is + halted + 25 + 1 + + + + + APB2FZ + APB2FZ + APB High Freeze Register + 0xC + 0x20 + read-write + 0x0 + + + DBG_TIM15_STOP + Debug Timer 15 stopped when Core is + halted + 2 + 1 + + + DBG_TIM16_STOP + Debug Timer 16 stopped when Core is + halted + 3 + 1 + + + DBG_TIM17_STO + Debug Timer 17 stopped when Core is + halted + 4 + 1 + + + DBG_TIM19_STOP + Debug Timer 19 stopped when Core is + halted + 5 + 1 + + + + + + + TIM1 + Advanced timer + TIMs + 0x40012C00 + + 0x0 + 0x400 + registers + + + TIM1_BRK_TIM15 + TIM1 Break/TIM15 global + interruts + 24 + + + TIM1_UP_TIM16 + TIM1 Update/TIM16 global + interrupts + 25 + + + TIM1_TRG_COM_TIM17 + TIM1 trigger and commutation/TIM17 + interrupts + 26 + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + CEN + Counter enable + 0 + 1 + + + UDIS + Update disable + 1 + 1 + + + URS + Update request source + 2 + 1 + + + OPM + One-pulse mode + 3 + 1 + + + DIR + Direction + 4 + 1 + + + CMS + Center-aligned mode + selection + 5 + 2 + + + ARPE + Auto-reload preload enable + 7 + 1 + + + CKD + Clock division + 8 + 2 + + + UIFREMAP + UIF status bit remapping + 11 + 1 + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 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CC1NE + Capture/Compare 1 complementary output + enable + 2 + 1 + + + CC1NP + Capture/Compare 1 output + Polarity + 3 + 1 + + + CC2E + Capture/Compare 2 output + enable + 4 + 1 + + + CC2P + Capture/Compare 2 output + Polarity + 5 + 1 + + + CC2NE + Capture/Compare 2 complementary output + enable + 6 + 1 + + + CC2NP + Capture/Compare 2 output + Polarity + 7 + 1 + + + CC3E + Capture/Compare 3 output + enable + 8 + 1 + + + CC3P + Capture/Compare 3 output + Polarity + 9 + 1 + + + CC3NE + Capture/Compare 3 complementary output + enable + 10 + 1 + + + CC3NP + Capture/Compare 3 output + Polarity + 11 + 1 + + + CC4E + Capture/Compare 4 output + enable + 12 + 1 + + + CC4P + Capture/Compare 3 output + Polarity + 13 + 1 + + + CC4NP + Capture/Compare 4 output + Polarity + 15 + 1 + + + CC5E + Capture/Compare 5 output + enable + 16 + 1 + + + CC5P + Capture/Compare 5 output + Polarity + 17 + 1 + + + CC6E + Capture/Compare 6 output + enable + 20 + 1 + + + CC6P + Capture/Compare 6 output + Polarity + 21 + 1 + + + + + CNT + CNT + counter + 0x24 + 0x20 + 0x00000000 + + + CNT + counter value + 0 + 16 + read-write + + + UIFCPY + UIF copy + 31 + 1 + read-only + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x0000 + + + PSC + Prescaler value + 0 + 16 + + + + + ARR + ARR + auto-reload register + 0x2C + 0x20 + read-write + 0x00000000 + + + ARR + Auto-reload value + 0 + 16 + + + + + RCR + RCR + repetition counter register + 0x30 + 0x20 + read-write + 0x0000 + + + REP + Repetition counter value + 0 + 16 + + + + + CCR1 + CCR1 + capture/compare register 1 + 0x34 + 0x20 + read-write + 0x00000000 + + + CCR1 + Capture/Compare 1 value + 0 + 16 + + + + + CCR2 + CCR2 + capture/compare register 2 + 0x38 + 0x20 + read-write + 0x00000000 + + + CCR2 + Capture/Compare 2 value + 0 + 16 + + + + + CCR3 + CCR3 + capture/compare register 3 + 0x3C + 0x20 + read-write + 0x00000000 + + + CCR3 + Capture/Compare 3 value + 0 + 16 + + + + + CCR4 + CCR4 + capture/compare register 4 + 0x40 + 0x20 + read-write + 0x00000000 + + + CCR4 + Capture/Compare 3 value + 0 + 16 + + + + + BDTR + BDTR + break and dead-time register + 0x44 + 0x20 + read-write + 0x00000000 + + + DTG + Dead-time generator setup + 0 + 8 + + + LOCK + Lock configuration + 8 + 2 + + + OSSI + Off-state selection for Idle + mode + 10 + 1 + + + OSSR + Off-state selection for Run + mode + 11 + 1 + + + BKE + Break enable + 12 + 1 + + + BKP + Break polarity + 13 + 1 + + + AOE + Automatic output enable + 14 + 1 + + + MOE + Main output enable + 15 + 1 + + + BKF + Break filter + 16 + 4 + + + BK2F + Break 2 filter + 20 + 4 + + + BK2E + Break 2 enable + 24 + 1 + + + BK2P + Break 2 polarity + 25 + 1 + + + + + DCR + DCR + DMA control register + 0x48 + 0x20 + read-write + 0x00000000 + + + DBL + DMA burst length + 8 + 5 + + + DBA + DMA base address + 0 + 5 + + + + + DMAR + DMAR + DMA address for full transfer + 0x4C + 0x20 + read-write + 0x00000000 + + + DMAB + DMA register for burst + accesses + 0 + 16 + + + + + CCMR3_Output + CCMR3_Output + capture/compare mode register 3 (output + mode) + 0x54 + 0x20 + read-write + 0x00000000 + + + OC5FE + Output compare 5 fast + enable + 2 + 1 + + + OC5PE + Output compare 5 preload + enable + 3 + 1 + + + OC5M + Output compare 5 mode + 4 + 3 + + + OC5CE + Output compare 5 clear + enable + 7 + 1 + + + OC6FE + Output compare 6 fast + enable + 10 + 1 + + + OC6PE + Output compare 6 preload + enable + 11 + 1 + + + OC6M + Output compare 6 mode + 12 + 3 + + + OC6CE + Output compare 6 clear + enable + 15 + 1 + + + OC5M_3 + Outout Compare 5 mode bit + 3 + 16 + 1 + + + OC6M_3 + Outout Compare 6 mode bit + 3 + 24 + 1 + + + + + CCR5 + CCR5 + capture/compare register 5 + 0x58 + 0x20 + read-write + 0x00000000 + + + CCR5 + Capture/Compare 5 value + 0 + 16 + + + GC5C1 + Group Channel 5 and Channel + 1 + 29 + 1 + + + GC5C2 + Group Channel 5 and Channel + 2 + 30 + 1 + + + GC5C3 + Group Channel 5 and Channel + 3 + 31 + 1 + + + + + CCR6 + CCR6 + capture/compare register 6 + 0x5C + 0x20 + read-write + 0x00000000 + + + CCR6 + Capture/Compare 6 value + 0 + 16 + + + + + OR + OR + option registers + 0x60 + 0x20 + read-write + 0x00000000 + + + TIM1_ETR_ADC1_RMP + TIM1_ETR_ADC1 remapping + capability + 0 + 2 + + + TIM1_ETR_ADC4_RMP + TIM1_ETR_ADC4 remapping + capability + 2 + 2 + + + + + + + TIM20 + 0x40015000 + + TIM1_CC + TIM1 capture compare interrupt + 27 + + + TIM20_BRK + TIM20 Break interrupt + 77 + + + TIM20_UP + TIM20 Upgrade interrupt + 78 + + + TIM20_TRG_COM + TIM20 Trigger and Commutation + interrupt + 79 + + + TIM20_CC + TIM20 Capture Compare interrupt + 80 + + + + TIM8 + Advanced-timers + TIMs + 0x40013400 + + 0x0 + 0x400 + registers + + + TIM8_BRK + TIM8 break interrupt + 43 + + + TIM8_UP + TIM8 update interrupt + 44 + + + TIM8_TRG_COM + TIM8 Trigger and commutation + interrupts + 45 + + + TIM8_CC + TIM8 capture compare interrupt + 46 + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + CEN + Counter enable + 0 + 1 + + + UDIS + Update disable + 1 + 1 + + + URS + Update request source + 2 + 1 + + + OPM + One-pulse mode + 3 + 1 + + + DIR + Direction + 4 + 1 + + + CMS + Center-aligned mode + selection + 5 + 2 + + + ARPE + Auto-reload preload enable + 7 + 1 + + + CKD + Clock division + 8 + 2 + + + UIFREMAP + UIF status bit remapping + 11 + 1 + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + CCPC + Capture/compare preloaded + control + 0 + 1 + + + CCUS + Capture/compare control update + selection + 2 + 1 + + + CCDS + Capture/compare DMA + selection + 3 + 1 + + + MMS + Master mode selection + 4 + 3 + + + TI1S + TI1 selection + 7 + 1 + + + OIS1 + Output Idle state 1 + 8 + 1 + + + OIS1N + Output Idle state 1 + 9 + 1 + + + OIS2 + Output Idle state 2 + 10 + 1 + + + OIS2N + Output Idle state 2 + 11 + 1 + + + OIS3 + Output Idle state 3 + 12 + 1 + + + OIS3N + Output Idle state 3 + 13 + 1 + + + OIS4 + Output Idle state 4 + 14 + 1 + + + OIS5 + Output Idle state 5 + 16 + 1 + + + OIS6 + Output Idle state 6 + 18 + 1 + + + MMS2 + Master mode selection 2 + 20 + 4 + + + + + SMCR + SMCR + slave mode control register + 0x8 + 0x20 + read-write + 0x0000 + + + SMS + Slave mode selection + 0 + 3 + + + OCCS + OCREF clear selection + 3 + 1 + + + TS + Trigger selection + 4 + 3 + + + MSM + Master/Slave mode + 7 + 1 + + + ETF + External trigger filter + 8 + 4 + + + ETPS + External trigger prescaler + 12 + 2 + + + ECE + External clock enable + 14 + 1 + + + ETP + External trigger polarity + 15 + 1 + + + SMS3 + Slave mode selection bit 3 + 16 + 1 + + + + + DIER + DIER + DMA/Interrupt enable register + 0xC + 0x20 + read-write + 0x0000 + + + TDE + Trigger DMA request enable + 14 + 1 + + + COMDE + COM DMA request enable + 13 + 1 + + + CC4DE + Capture/Compare 4 DMA request + enable + 12 + 1 + + + CC3DE + Capture/Compare 3 DMA request + enable + 11 + 1 + + + CC2DE + Capture/Compare 2 DMA request + enable + 10 + 1 + + + CC1DE + Capture/Compare 1 DMA request + enable + 9 + 1 + + + UDE + Update DMA request enable + 8 + 1 + + + BIE + Break interrupt enable + 7 + 1 + + + TIE + Trigger interrupt enable + 6 + 1 + + + COMIE + COM interrupt enable + 5 + 1 + + + CC4IE + Capture/Compare 4 interrupt + enable + 4 + 1 + + + CC3IE + Capture/Compare 3 interrupt + enable + 3 + 1 + + + CC2IE + Capture/Compare 2 interrupt + enable + 2 + 1 + + + CC1IE + Capture/Compare 1 interrupt + enable + 1 + 1 + + + UIE + Update interrupt enable + 0 + 1 + + + + + SR + SR + status register + 0x10 + 0x20 + read-write + 0x0000 + + + UIF + Update interrupt flag + 0 + 1 + + + CC1IF + Capture/compare 1 interrupt + flag + 1 + 1 + + + CC2IF + Capture/Compare 2 interrupt + flag + 2 + 1 + + + CC3IF + Capture/Compare 3 interrupt + flag + 3 + 1 + + + CC4IF + Capture/Compare 4 interrupt + flag + 4 + 1 + + + COMIF + COM interrupt flag + 5 + 1 + + + TIF + Trigger interrupt flag + 6 + 1 + + + BIF + Break interrupt flag + 7 + 1 + + + B2IF + Break 2 interrupt flag + 8 + 1 + + + CC1OF + Capture/Compare 1 overcapture + flag + 9 + 1 + + + CC2OF + Capture/compare 2 overcapture + flag + 10 + 1 + + + CC3OF + Capture/Compare 3 overcapture + flag + 11 + 1 + + + CC4OF + Capture/Compare 4 overcapture + flag + 12 + 1 + + + C5IF + Capture/Compare 5 interrupt + flag + 16 + 1 + + + C6IF + Capture/Compare 6 interrupt + flag + 17 + 1 + + + + + EGR + EGR + event generation register + 0x14 + 0x20 + write-only + 0x0000 + + + UG + Update generation + 0 + 1 + + + CC1G + Capture/compare 1 + generation + 1 + 1 + + + CC2G + Capture/compare 2 + generation + 2 + 1 + + + CC3G + Capture/compare 3 + generation + 3 + 1 + + + CC4G + Capture/compare 4 + generation + 4 + 1 + + + COMG + Capture/Compare control update + generation + 5 + 1 + + + TG + Trigger generation + 6 + 1 + + + BG + Break generation + 7 + 1 + + + B2G + Break 2 generation + 8 + 1 + + + + + CCMR1_Output + CCMR1_Output + capture/compare mode register (output + mode) + 0x18 + 0x20 + read-write + 0x00000000 + + + OC2CE + Output Compare 2 clear + enable + 15 + 1 + + + OC2M + Output Compare 2 mode + 12 + 3 + + + OC2PE + Output Compare 2 preload + enable + 11 + 1 + + + OC2FE + Output Compare 2 fast + enable + 10 + 1 + + + CC2S + Capture/Compare 2 + selection + 8 + 2 + + + OC1CE + Output Compare 1 clear + enable + 7 + 1 + + + OC1M + Output Compare 1 mode + 4 + 3 + + + OC1PE + Output Compare 1 preload + enable + 3 + 1 + + + OC1FE + Output Compare 1 fast + enable + 2 + 1 + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + OC1M_3 + Output Compare 1 mode bit + 3 + 16 + 1 + + + OC2M_3 + Output Compare 2 mode bit + 3 + 24 + 1 + + + + + CCMR1_Input + CCMR1_Input + capture/compare mode register 1 (input + mode) + CCMR1_Output + 0x18 + 0x20 + read-write + 0x00000000 + + + IC2F + Input capture 2 filter + 12 + 4 + + + IC2PCS + Input capture 2 prescaler + 10 + 2 + + + CC2S + Capture/Compare 2 + selection + 8 + 2 + + + IC1F + Input capture 1 filter + 4 + 4 + + + IC1PCS + Input capture 1 prescaler + 2 + 2 + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + + + CCMR2_Output + CCMR2_Output + capture/compare mode register (output + mode) + 0x1C + 0x20 + read-write + 0x00000000 + + + OC4CE + Output compare 4 clear + enable + 15 + 1 + + + OC4M + Output compare 4 mode + 12 + 3 + + + OC4PE + Output compare 4 preload + enable + 11 + 1 + + + OC4FE + Output compare 4 fast + enable + 10 + 1 + + + CC4S + Capture/Compare 4 + selection + 8 + 2 + + + OC3CE + Output compare 3 clear + enable + 7 + 1 + + + OC3M + Output compare 3 mode + 4 + 3 + + + OC3PE + Output compare 3 preload + enable + 3 + 1 + + + OC3FE + Output compare 3 fast + enable + 2 + 1 + + + CC3S + Capture/Compare 3 + selection + 0 + 2 + + + OC3M_3 + Output Compare 3 mode bit + 3 + 16 + 1 + + + OC4M_3 + Output Compare 4 mode bit + 3 + 24 + 1 + + + + + CCMR2_Input + CCMR2_Input + capture/compare mode register 2 (input + mode) + CCMR2_Output + 0x1C + 0x20 + read-write + 0x00000000 + + + IC4F + Input capture 4 filter + 12 + 4 + + + IC4PSC + Input capture 4 prescaler + 10 + 2 + + + CC4S + Capture/Compare 4 + selection + 8 + 2 + + + IC3F + Input capture 3 filter + 4 + 4 + + + IC3PSC + Input capture 3 prescaler + 2 + 2 + + + CC3S + Capture/compare 3 + selection + 0 + 2 + + + + + CCER + CCER + capture/compare enable + register + 0x20 + 0x20 + read-write + 0x0000 + + + CC1E + Capture/Compare 1 output + enable + 0 + 1 + + + CC1P + Capture/Compare 1 output + Polarity + 1 + 1 + + + CC1NE + Capture/Compare 1 complementary output + enable + 2 + 1 + + + CC1NP + Capture/Compare 1 output + Polarity + 3 + 1 + + + CC2E + Capture/Compare 2 output + enable + 4 + 1 + + + CC2P + Capture/Compare 2 output + Polarity + 5 + 1 + + + CC2NE + Capture/Compare 2 complementary output + enable + 6 + 1 + + + CC2NP + Capture/Compare 2 output + Polarity + 7 + 1 + + + CC3E + Capture/Compare 3 output + enable + 8 + 1 + + + CC3P + Capture/Compare 3 output + Polarity + 9 + 1 + + + CC3NE + Capture/Compare 3 complementary output + enable + 10 + 1 + + + CC3NP + Capture/Compare 3 output + Polarity + 11 + 1 + + + CC4E + Capture/Compare 4 output + enable + 12 + 1 + + + CC4P + Capture/Compare 3 output + Polarity + 13 + 1 + + + CC4NP + Capture/Compare 4 output + Polarity + 15 + 1 + + + CC5E + Capture/Compare 5 output + enable + 16 + 1 + + + CC5P + Capture/Compare 5 output + Polarity + 17 + 1 + + + CC6E + Capture/Compare 6 output + enable + 20 + 1 + + + CC6P + Capture/Compare 6 output + Polarity + 21 + 1 + + + + + CNT + CNT + counter + 0x24 + 0x20 + 0x00000000 + + + CNT + counter value + 0 + 16 + read-write + + + UIFCPY + UIF copy + 31 + 1 + read-only + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x0000 + + + PSC + Prescaler value + 0 + 16 + + + + + ARR + ARR + auto-reload register + 0x2C + 0x20 + read-write + 0x00000000 + + + ARR + Auto-reload value + 0 + 16 + + + + + RCR + RCR + repetition counter register + 0x30 + 0x20 + read-write + 0x0000 + + + REP + Repetition counter value + 0 + 16 + + + + + CCR1 + CCR1 + capture/compare register 1 + 0x34 + 0x20 + read-write + 0x00000000 + + + CCR1 + Capture/Compare 1 value + 0 + 16 + + + + + CCR2 + CCR2 + capture/compare register 2 + 0x38 + 0x20 + read-write + 0x00000000 + + + CCR2 + Capture/Compare 2 value + 0 + 16 + + + + + CCR3 + CCR3 + capture/compare register 3 + 0x3C + 0x20 + read-write + 0x00000000 + + + CCR3 + Capture/Compare 3 value + 0 + 16 + + + + + CCR4 + CCR4 + capture/compare register 4 + 0x40 + 0x20 + read-write + 0x00000000 + + + CCR4 + Capture/Compare 3 value + 0 + 16 + + + + + BDTR + BDTR + break and dead-time register + 0x44 + 0x20 + read-write + 0x00000000 + + + DTG + Dead-time generator setup + 0 + 8 + + + LOCK + Lock configuration + 8 + 2 + + + OSSI + Off-state selection for Idle + mode + 10 + 1 + + + OSSR + Off-state selection for Run + mode + 11 + 1 + + + BKE + Break enable + 12 + 1 + + + BKP + Break polarity + 13 + 1 + + + AOE + Automatic output enable + 14 + 1 + + + MOE + Main output enable + 15 + 1 + + + BKF + Break filter + 16 + 4 + + + BK2F + Break 2 filter + 20 + 4 + + + BK2E + Break 2 enable + 24 + 1 + + + BK2P + Break 2 polarity + 25 + 1 + + + + + DCR + DCR + DMA control register + 0x48 + 0x20 + read-write + 0x00000000 + + + DBL + DMA burst length + 8 + 5 + + + DBA + DMA base address + 0 + 5 + + + + + DMAR + DMAR + DMA address for full transfer + 0x4C + 0x20 + read-write + 0x00000000 + + + DMAB + DMA register for burst + accesses + 0 + 16 + + + + + CCMR3_Output + CCMR3_Output + capture/compare mode register 3 (output + mode) + 0x54 + 0x20 + read-write + 0x00000000 + + + OC5FE + Output compare 5 fast + enable + 2 + 1 + + + OC5PE + Output compare 5 preload + enable + 3 + 1 + + + OC5M + Output compare 5 mode + 4 + 3 + + + OC5CE + Output compare 5 clear + enable + 7 + 1 + + + OC6FE + Output compare 6 fast + enable + 10 + 1 + + + OC6PE + Output compare 6 preload + enable + 11 + 1 + + + OC6M + Output compare 6 mode + 12 + 3 + + + OC6CE + Output compare 6 clear + enable + 15 + 1 + + + OC5M_3 + Outout Compare 5 mode bit + 3 + 16 + 1 + + + OC6M_3 + Outout Compare 6 mode bit + 3 + 24 + 1 + + + + + CCR5 + CCR5 + capture/compare register 5 + 0x58 + 0x20 + read-write + 0x00000000 + + + CCR5 + Capture/Compare 5 value + 0 + 16 + + + GC5C1 + Group Channel 5 and Channel + 1 + 29 + 1 + + + GC5C2 + Group Channel 5 and Channel + 2 + 30 + 1 + + + GC5C3 + Group Channel 5 and Channel + 3 + 31 + 1 + + + + + CCR6 + CCR6 + capture/compare register 6 + 0x5C + 0x20 + read-write + 0x00000000 + + + CCR6 + Capture/Compare 6 value + 0 + 16 + + + + + OR + OR + option registers + 0x60 + 0x20 + read-write + 0x00000000 + + + TIM8_ETR_ADC2_RMP + TIM8_ETR_ADC2 remapping + capability + 0 + 2 + + + TIM8_ETR_ADC3_RMP + TIM8_ETR_ADC3 remapping + capability + 2 + 2 + + + + + + + ADC1 + Analog-to-Digital Converter + ADC + 0x50000000 + + 0x0 + 0x100 + registers + + + + ISR + ISR + interrupt and status register + 0x0 + 0x20 + read-write + 0x00000000 + + + JQOVF + JQOVF + 10 + 1 + + + AWD3 + AWD3 + 9 + 1 + + + AWD2 + AWD2 + 8 + 1 + + + AWD1 + AWD1 + 7 + 1 + + + JEOS + JEOS + 6 + 1 + + + JEOC + JEOC + 5 + 1 + + + OVR + OVR + 4 + 1 + + + EOS + EOS + 3 + 1 + + + EOC + EOC + 2 + 1 + + + EOSMP + EOSMP + 1 + 1 + + + ADRDY + ADRDY + 0 + 1 + + + + + IER + IER + interrupt enable register + 0x4 + 0x20 + read-write + 0x00000000 + + + JQOVFIE + JQOVFIE + 10 + 1 + + + AWD3IE + AWD3IE + 9 + 1 + + + AWD2IE + AWD2IE + 8 + 1 + + + AWD1IE + AWD1IE + 7 + 1 + + + JEOSIE + JEOSIE + 6 + 1 + + + JEOCIE + JEOCIE + 5 + 1 + + + OVRIE + OVRIE + 4 + 1 + + + EOSIE + EOSIE + 3 + 1 + + + EOCIE + EOCIE + 2 + 1 + + + EOSMPIE + EOSMPIE + 1 + 1 + + + ADRDYIE + ADRDYIE + 0 + 1 + + + + + CR + CR + control register + 0x8 + 0x20 + read-write + 0x00000000 + + + ADCAL + ADCAL + 31 + 1 + + + ADCALDIF + ADCALDIF + 30 + 1 + + + ADVREGEN + ADVREGEN + 28 + 2 + + + JADSTP + JADSTP + 5 + 1 + + + ADSTP + ADSTP + 4 + 1 + + + JADSTART + JADSTART + 3 + 1 + + + ADSTART + ADSTART + 2 + 1 + + + ADDIS + ADDIS + 1 + 1 + + + ADEN + ADEN + 0 + 1 + + + + + CFGR + CFGR + configuration register + 0xC + 0x20 + read-write + 0x00000000 + + + AWDCH1CH + AWDCH1CH + 26 + 5 + + + JAUTO + JAUTO + 25 + 1 + + + JAWD1EN + JAWD1EN + 24 + 1 + + + AWD1EN + AWD1EN + 23 + 1 + + + AWD1SGL + AWD1SGL + 22 + 1 + + + JQM + JQM + 21 + 1 + + + JDISCEN + JDISCEN + 20 + 1 + + + DISCNUM + DISCNUM + 17 + 3 + + + DISCEN + DISCEN + 16 + 1 + + + AUTDLY + AUTDLY + 14 + 1 + + + CONT + CONT + 13 + 1 + + + OVRMOD + OVRMOD + 12 + 1 + + + EXTEN + EXTEN + 10 + 2 + + + EXTSEL + EXTSEL + 6 + 4 + + + ALIGN + ALIGN + 5 + 1 + + + RES + RES + 3 + 2 + + + DMACFG + DMACFG + 1 + 1 + + + DMAEN + DMAEN + 0 + 1 + + + + + SMPR1 + SMPR1 + sample time register 1 + 0x14 + 0x20 + read-write + 0x00000000 + + + SMP9 + SMP9 + 27 + 3 + + + SMP8 + SMP8 + 24 + 3 + + + SMP7 + SMP7 + 21 + 3 + + + SMP6 + SMP6 + 18 + 3 + + + SMP5 + SMP5 + 15 + 3 + + + SMP4 + SMP4 + 12 + 3 + + + SMP3 + SMP3 + 9 + 3 + + + SMP2 + SMP2 + 6 + 3 + + + SMP1 + SMP1 + 3 + 3 + + + + + SMPR2 + SMPR2 + sample time register 2 + 0x18 + 0x20 + read-write + 0x00000000 + + + SMP18 + SMP18 + 24 + 3 + + + SMP17 + SMP17 + 21 + 3 + + + SMP16 + SMP16 + 18 + 3 + + + SMP15 + SMP15 + 15 + 3 + + + SMP14 + SMP14 + 12 + 3 + + + SMP13 + SMP13 + 9 + 3 + + + SMP12 + SMP12 + 6 + 3 + + + SMP11 + SMP11 + 3 + 3 + + + SMP10 + SMP10 + 0 + 3 + + + + + TR1 + TR1 + watchdog threshold register 1 + 0x20 + 0x20 + read-write + 0x0FFF0000 + + + HT1 + HT1 + 16 + 12 + + + LT1 + LT1 + 0 + 12 + + + + + TR2 + TR2 + watchdog threshold register + 0x24 + 0x20 + read-write + 0x0FFF0000 + + + HT2 + HT2 + 16 + 8 + + + LT2 + LT2 + 0 + 8 + + + + + TR3 + TR3 + watchdog threshold register 3 + 0x28 + 0x20 + read-write + 0x0FFF0000 + + + HT3 + HT3 + 16 + 8 + + + LT3 + LT3 + 0 + 8 + + + + + SQR1 + SQR1 + regular sequence register 1 + 0x30 + 0x20 + read-write + 0x00000000 + + + SQ4 + SQ4 + 24 + 5 + + + SQ3 + SQ3 + 18 + 5 + + + SQ2 + SQ2 + 12 + 5 + + + SQ1 + SQ1 + 6 + 5 + + + L3 + L3 + 0 + 4 + + + + + SQR2 + SQR2 + regular sequence register 2 + 0x34 + 0x20 + read-write + 0x00000000 + + + SQ9 + SQ9 + 24 + 5 + + + SQ8 + SQ8 + 18 + 5 + + + SQ7 + SQ7 + 12 + 5 + + + SQ6 + SQ6 + 6 + 5 + + + SQ5 + SQ5 + 0 + 5 + + + + + SQR3 + SQR3 + regular sequence register 3 + 0x38 + 0x20 + read-write + 0x00000000 + + + SQ14 + SQ14 + 24 + 5 + + + SQ13 + SQ13 + 18 + 5 + + + SQ12 + SQ12 + 12 + 5 + + + SQ11 + SQ11 + 6 + 5 + + + SQ10 + SQ10 + 0 + 5 + + + + + SQR4 + SQR4 + regular sequence register 4 + 0x3C + 0x20 + read-write + 0x00000000 + + + SQ16 + SQ16 + 6 + 5 + + + SQ15 + SQ15 + 0 + 5 + + + + + DR + DR + regular Data Register + 0x40 + 0x20 + read-only + 0x00000000 + + + regularDATA + regularDATA + 0 + 16 + + + + + JSQR + JSQR + injected sequence register + 0x4C + 0x20 + read-write + 0x00000000 + + + JSQ4 + JSQ4 + 26 + 5 + + + JSQ3 + JSQ3 + 20 + 5 + + + JSQ2 + JSQ2 + 14 + 5 + + + JSQ1 + JSQ1 + 8 + 5 + + + JEXTEN + JEXTEN + 6 + 2 + + + JEXTSEL + JEXTSEL + 2 + 4 + + + JL + JL + 0 + 2 + + + + + OFR1 + OFR1 + offset register 1 + 0x60 + 0x20 + read-write + 0x00000000 + + + OFFSET1_EN + OFFSET1_EN + 31 + 1 + + + OFFSET1_CH + OFFSET1_CH + 26 + 5 + + + OFFSET1 + OFFSET1 + 0 + 12 + + + + + OFR2 + OFR2 + offset register 2 + 0x64 + 0x20 + read-write + 0x00000000 + + + OFFSET2_EN + OFFSET2_EN + 31 + 1 + + + OFFSET2_CH + OFFSET2_CH + 26 + 5 + + + OFFSET2 + OFFSET2 + 0 + 12 + + + + + OFR3 + OFR3 + offset register 3 + 0x68 + 0x20 + read-write + 0x00000000 + + + OFFSET3_EN + OFFSET3_EN + 31 + 1 + + + OFFSET3_CH + OFFSET3_CH + 26 + 5 + + + OFFSET3 + OFFSET3 + 0 + 12 + + + + + OFR4 + OFR4 + offset register 4 + 0x6C + 0x20 + read-write + 0x00000000 + + + OFFSET4_EN + OFFSET4_EN + 31 + 1 + + + OFFSET4_CH + OFFSET4_CH + 26 + 5 + + + OFFSET4 + OFFSET4 + 0 + 12 + + + + + JDR1 + JDR1 + injected data register 1 + 0x80 + 0x20 + read-only + 0x00000000 + + + JDATA1 + JDATA1 + 0 + 16 + + + + + JDR2 + JDR2 + injected data register 2 + 0x84 + 0x20 + read-only + 0x00000000 + + + JDATA2 + JDATA2 + 0 + 16 + + + + + JDR3 + JDR3 + injected data register 3 + 0x88 + 0x20 + read-only + 0x00000000 + + + JDATA3 + JDATA3 + 0 + 16 + + + + + JDR4 + JDR4 + injected data register 4 + 0x8C + 0x20 + read-only + 0x00000000 + + + JDATA4 + JDATA4 + 0 + 16 + + + + + AWD2CR + AWD2CR + Analog Watchdog 2 Configuration + Register + 0xA0 + 0x20 + read-write + 0x00000000 + + + AWD2CH + AWD2CH + 1 + 18 + + + + + AWD3CR + AWD3CR + Analog Watchdog 3 Configuration + Register + 0xA4 + 0x20 + read-write + 0x00000000 + + + AWD3CH + AWD3CH + 1 + 18 + + + + + DIFSEL + DIFSEL + Differential Mode Selection Register + 2 + 0xB0 + 0x20 + 0x00000000 + + + DIFSEL_1_15 + Differential mode for channels 15 to + 1 + 1 + 15 + read-write + + + DIFSEL_16_18 + Differential mode for channels 18 to + 16 + 16 + 3 + read-only + + + + + CALFACT + CALFACT + Calibration Factors + 0xB4 + 0x20 + read-write + 0x00000000 + + + CALFACT_D + CALFACT_D + 16 + 7 + + + CALFACT_S + CALFACT_S + 0 + 7 + + + + + + + ADC2 + 0x50000100 + + + ADC3 + 0x50000400 + + ADC3 + ADC3 global interrupt + 47 + + + + ADC4 + 0x50000500 + + ADC4 + ADC4 global interrupt + 61 + + + + ADC1_2 + Analog-to-Digital Converter + ADC + 0x50000300 + + 0x0 + 0x10 + registers + + + ADC1_2 + ADC1 and ADC2 global interrupt + 18 + + + + CSR + CSR + ADC Common status register + 0x0 + 0x20 + read-only + 0x00000000 + + + ADDRDY_MST + ADDRDY_MST + 0 + 1 + + + EOSMP_MST + EOSMP_MST + 1 + 1 + + + EOC_MST + EOC_MST + 2 + 1 + + + EOS_MST + EOS_MST + 3 + 1 + + + OVR_MST + OVR_MST + 4 + 1 + + + JEOC_MST + JEOC_MST + 5 + 1 + + + JEOS_MST + JEOS_MST + 6 + 1 + + + AWD1_MST + AWD1_MST + 7 + 1 + + + AWD2_MST + AWD2_MST + 8 + 1 + + + AWD3_MST + AWD3_MST + 9 + 1 + + + JQOVF_MST + JQOVF_MST + 10 + 1 + + + ADRDY_SLV + ADRDY_SLV + 16 + 1 + + + EOSMP_SLV + EOSMP_SLV + 17 + 1 + + + EOC_SLV + End of regular conversion of the slave + ADC + 18 + 1 + + + EOS_SLV + End of regular sequence flag of the + slave ADC + 19 + 1 + + + OVR_SLV + Overrun flag of the slave + ADC + 20 + 1 + + + JEOC_SLV + End of injected conversion flag of the + slave ADC + 21 + 1 + + + JEOS_SLV + End of injected sequence flag of the + slave ADC + 22 + 1 + + + AWD1_SLV + Analog watchdog 1 flag of the slave + ADC + 23 + 1 + + + AWD2_SLV + Analog watchdog 2 flag of the slave + ADC + 24 + 1 + + + AWD3_SLV + Analog watchdog 3 flag of the slave + ADC + 25 + 1 + + + JQOVF_SLV + Injected Context Queue Overflow flag of + the slave ADC + 26 + 1 + + + + + CCR + CCR + ADC common control register + 0x8 + 0x20 + read-write + 0x00000000 + + + MULT + Multi ADC mode selection + 0 + 5 + + + DELAY + Delay between 2 sampling + phases + 8 + 4 + + + DMACFG + DMA configuration (for multi-ADC + mode) + 13 + 1 + + + MDMA + Direct memory access mode for multi ADC + mode + 14 + 2 + + + CKMODE + ADC clock mode + 16 + 2 + + + VREFEN + VREFINT enable + 22 + 1 + + + TSEN + Temperature sensor enable + 23 + 1 + + + VBATEN + VBAT enable + 24 + 1 + + + + + CDR + CDR + ADC common regular data register for dual + and triple modes + 0xC + 0x20 + read-only + 0x00000000 + + + RDATA_SLV + Regular data of the slave + ADC + 16 + 16 + + + RDATA_MST + Regular data of the master + ADC + 0 + 16 + + + + + + + ADC3_4 + 0x50000700 + + + SYSCFG_COMP_OPAMP + System configuration controller _Comparator and + Operational amplifier + SYSCFG_COMP_OPAMP + 0x40010000 + + 0x0 + 0x400 + registers + + + COMP123 + COMP1 & COMP2 & COMP3 interrupts + combined with EXTI Lines 21, 22 and 29 + interrupts + 64 + + + COMP456 + COMP4 & COMP5 & COMP6 interrupts + combined with EXTI Lines 30, 31 and 32 + interrupts + 65 + + + COMP7 + COMP7 interrupt combined with EXTI Line 33 + interrupt + 66 + + + + SYSCFG_CFGR1 + SYSCFG_CFGR1 + configuration register 1 + 0x0 + 0x20 + read-write + 0x00000000 + + + MEM_MODE + Memory mapping selection + bits + 0 + 2 + + + USB_IT_RMP + USB interrupt remap + 5 + 1 + + + TIM1_ITR_RMP + Timer 1 ITR3 selection + 6 + 1 + + + DAC_TRIG_RMP + DAC trigger remap (when TSEL = + 001) + 7 + 1 + + + ADC24_DMA_RMP + ADC24 DMA remapping bit + 8 + 1 + + + TIM16_DMA_RMP + TIM16 DMA request remapping + bit + 11 + 1 + + + TIM17_DMA_RMP + TIM17 DMA request remapping + bit + 12 + 1 + + + TIM6_DAC1_DMA_RMP + TIM6 and DAC1 DMA request remapping + bit + 13 + 1 + + + TIM7_DAC2_DMA_RMP + TIM7 and DAC2 DMA request remapping + bit + 14 + 1 + + + I2C_PB6_FM + Fast Mode Plus (FM+) driving capability + activation bits. + 16 + 1 + + + I2C_PB7_FM + Fast Mode Plus (FM+) driving capability + activation bits. + 17 + 1 + + + I2C_PB8_FM + Fast Mode Plus (FM+) driving capability + activation bits. + 18 + 1 + + + I2C_PB9_FM + Fast Mode Plus (FM+) driving capability + activation bits. + 19 + 1 + + + I2C1_FM + I2C1 Fast Mode Plus + 20 + 1 + + + I2C2_FM + I2C2 Fast Mode Plus + 21 + 1 + + + ENCODER_MODE + Encoder mode + 22 + 2 + + + FPU_IT + Interrupt enable bits from + FPU + 26 + 6 + + + + + SYSCFG_EXTICR1 + SYSCFG_EXTICR1 + external interrupt configuration register + 1 + 0x8 + 0x20 + read-write + 0x0000 + + + EXTI3 + EXTI 3 configuration bits + 12 + 4 + + + EXTI2 + EXTI 2 configuration bits + 8 + 4 + + + EXTI1 + EXTI 1 configuration bits + 4 + 4 + + + EXTI0 + EXTI 0 configuration bits + 0 + 4 + + + + + SYSCFG_EXTICR2 + SYSCFG_EXTICR2 + external interrupt configuration register + 2 + 0xC + 0x20 + read-write + 0x0000 + + + EXTI7 + EXTI 7 configuration bits + 12 + 4 + + + EXTI6 + EXTI 6 configuration bits + 8 + 4 + + + EXTI5 + EXTI 5 configuration bits + 4 + 4 + + + EXTI4 + EXTI 4 configuration bits + 0 + 4 + + + + + SYSCFG_EXTICR3 + SYSCFG_EXTICR3 + external interrupt configuration register + 3 + 0x10 + 0x20 + read-write + 0x0000 + + + EXTI11 + EXTI 11 configuration bits + 12 + 4 + + + EXTI10 + EXTI 10 configuration bits + 8 + 4 + + + EXTI9 + EXTI 9 configuration bits + 4 + 4 + + + EXTI8 + EXTI 8 configuration bits + 0 + 4 + + + + + SYSCFG_EXTICR4 + SYSCFG_EXTICR4 + external interrupt configuration register + 4 + 0x14 + 0x20 + read-write + 0x0000 + + + EXTI15 + EXTI 15 configuration bits + 12 + 4 + + + EXTI14 + EXTI 14 configuration bits + 8 + 4 + + + EXTI13 + EXTI 13 configuration bits + 4 + 4 + + + EXTI12 + EXTI 12 configuration bits + 0 + 4 + + + + + SYSCFG_CFGR2 + SYSCFG_CFGR2 + configuration register 2 + 0x18 + 0x20 + read-write + 0x0000 + + + LOCUP_LOCK + Cortex-M0 LOCKUP bit enable + bit + 0 + 1 + + + SRAM_PARITY_LOCK + SRAM parity lock bit + 1 + 1 + + + PVD_LOCK + PVD lock enable bit + 2 + 1 + + + BYP_ADD_PAR + Bypass address bit 29 in parity + calculation + 4 + 1 + + + SRAM_PEF + SRAM parity flag + 8 + 1 + + + + + SYSCFG_RCR + SYSCFG_RCR + CCM SRAM protection register + 0x4 + 0x20 + read-write + 0x0000 + + + PAGE0_WP + CCM SRAM page write protection + bit + 0 + 1 + + + PAGE1_WP + CCM SRAM page write protection + bit + 1 + 1 + + + PAGE2_WP + CCM SRAM page write protection + bit + 2 + 1 + + + PAGE3_WP + CCM SRAM page write protection + bit + 3 + 1 + + + PAGE4_WP + CCM SRAM page write protection + bit + 4 + 1 + + + PAGE5_WP + CCM SRAM page write protection + bit + 5 + 1 + + + PAGE6_WP + CCM SRAM page write protection + bit + 6 + 1 + + + PAGE7_WP + CCM SRAM page write protection + bit + 7 + 1 + + + + + COMP1_CSR + COMP1_CSR + control and status register + 0x1C + 0x20 + 0x0000 + + + COMP1EN + Comparator 1 enable + 0 + 1 + read-write + + + COMP1_INP_DAC + COMP1_INP_DAC + 1 + 1 + read-write + + + COMP1MODE + Comparator 1 mode + 2 + 2 + read-write + + + COMP1INSEL + Comparator 1 inverting input + selection + 4 + 3 + read-write + + + COMP1_OUT_SEL + Comparator 1 output + selection + 10 + 4 + read-write + + + COMP1POL + Comparator 1 output + polarity + 15 + 1 + read-write + + + COMP1HYST + Comparator 1 hysteresis + 16 + 2 + read-write + + + COMP1_BLANKING + Comparator 1 blanking + source + 18 + 3 + read-write + + + COMP1OUT + Comparator 1 output + 30 + 1 + read-only + + + COMP1LOCK + Comparator 1 lock + 31 + 1 + read-write + + + + + COMP2_CSR + COMP2_CSR + control and status register + 0x20 + 0x20 + read-write + 0x0000 + + + COMP2EN + Comparator 2 enable + 0 + 1 + + + COMP2MODE + Comparator 2 mode + 2 + 2 + + + COMP2INSEL + Comparator 2 inverting input + selection + 4 + 3 + + + COMP2INPSEL + Comparator 2 non inverted input + selection + 7 + 1 + + + COMP2INMSEL + Comparator 1inverting input + selection + 9 + 1 + + + COMP2_OUT_SEL + Comparator 2 output + selection + 10 + 4 + + + COMP2POL + Comparator 2 output + polarity + 15 + 1 + + + COMP2HYST + Comparator 2 hysteresis + 16 + 2 + + + COMP2_BLANKING + Comparator 2 blanking + source + 18 + 3 + + + COMP2LOCK + Comparator 2 lock + 31 + 1 + + + COMP2OUT + Comparator 2 output + 30 + 1 + + + + + COMP3_CSR + COMP3_CSR + control and status register + 0x24 + 0x20 + 0x0000 + + + COMP3EN + Comparator 3 enable + 0 + 1 + read-write + + + COMP3MODE + Comparator 3 mode + 2 + 2 + read-write + + + COMP3INSEL + Comparator 3 inverting input + selection + 4 + 3 + read-write + + + COMP3INPSEL + Comparator 3 non inverted input + selection + 7 + 1 + read-write + + + COMP3_OUT_SEL + Comparator 3 output + selection + 10 + 4 + read-write + + + COMP3POL + Comparator 3 output + polarity + 15 + 1 + read-write + + + COMP3HYST + Comparator 3 hysteresis + 16 + 2 + read-write + + + COMP3_BLANKING + Comparator 3 blanking + source + 18 + 3 + read-write + + + COMP3OUT + Comparator 3 output + 30 + 1 + read-only + + + COMP3LOCK + Comparator 3 lock + 31 + 1 + read-write + + + + + COMP4_CSR + COMP4_CSR + control and status register + 0x28 + 0x20 + 0x0000 + + + COMP4EN + Comparator 4 enable + 0 + 1 + read-write + + + COMP4MODE + Comparator 4 mode + 2 + 2 + read-write + + + COMP4INSEL + Comparator 4 inverting input + selection + 4 + 3 + read-write + + + COMP4INPSEL + Comparator 4 non inverted input + selection + 7 + 1 + read-write + + + COM4WINMODE + Comparator 4 window mode + 9 + 1 + read-write + + + COMP4_OUT_SEL + Comparator 4 output + selection + 10 + 4 + read-write + + + COMP4POL + Comparator 4 output + polarity + 15 + 1 + read-write + + + COMP4HYST + Comparator 4 hysteresis + 16 + 2 + read-write + + + COMP4_BLANKING + Comparator 4 blanking + source + 18 + 3 + read-write + + + COMP4OUT + Comparator 4 output + 30 + 1 + read-only + + + COMP4LOCK + Comparator 4 lock + 31 + 1 + read-write + + + + + COMP5_CSR + COMP5_CSR + control and status register + 0x2C + 0x20 + 0x0000 + + + COMP5EN + Comparator 5 enable + 0 + 1 + read-write + + + COMP5MODE + Comparator 5 mode + 2 + 2 + read-write + + + COMP5INSEL + Comparator 5 inverting input + selection + 4 + 3 + read-write + + + COMP5INPSEL + Comparator 5 non inverted input + selection + 7 + 1 + read-write + + + COMP5_OUT_SEL + Comparator 5 output + selection + 10 + 4 + read-write + + + COMP5POL + Comparator 5 output + polarity + 15 + 1 + read-write + + + COMP5HYST + Comparator 5 hysteresis + 16 + 2 + read-write + + + COMP5_BLANKING + Comparator 5 blanking + source + 18 + 3 + read-write + + + COMP5OUT + Comparator51 output + 30 + 1 + read-only + + + COMP5LOCK + Comparator 5 lock + 31 + 1 + read-write + + + + + COMP6_CSR + COMP6_CSR + control and status register + 0x30 + 0x20 + 0x0000 + + + COMP6EN + Comparator 6 enable + 0 + 1 + read-write + + + COMP6MODE + Comparator 6 mode + 2 + 2 + read-write + + + COMP6INSEL + Comparator 6 inverting input + selection + 4 + 3 + read-write + + + COMP6INPSEL + Comparator 6 non inverted input + selection + 7 + 1 + read-write + + + COM6WINMODE + Comparator 6 window mode + 9 + 1 + read-write + + + COMP6_OUT_SEL + Comparator 6 output + selection + 10 + 4 + read-write + + + COMP6POL + Comparator 6 output + polarity + 15 + 1 + read-write + + + COMP6HYST + Comparator 6 hysteresis + 16 + 2 + read-write + + + COMP6_BLANKING + Comparator 6 blanking + source + 18 + 3 + read-write + + + COMP6OUT + Comparator 6 output + 30 + 1 + read-only + + + COMP6LOCK + Comparator 6 lock + 31 + 1 + read-write + + + + + COMP7_CSR + COMP7_CSR + control and status register + 0x34 + 0x20 + 0x0000 + + + COMP7EN + Comparator 7 enable + 0 + 1 + read-write + + + COMP7MODE + Comparator 7 mode + 2 + 2 + read-write + + + COMP7INSEL + Comparator 7 inverting input + selection + 4 + 3 + read-write + + + COMP7INPSEL + Comparator 7 non inverted input + selection + 7 + 1 + read-write + + + COMP7_OUT_SEL + Comparator 7 output + selection + 10 + 4 + read-write + + + COMP7POL + Comparator 7 output + polarity + 15 + 1 + read-write + + + COMP7HYST + Comparator 7 hysteresis + 16 + 2 + read-write + + + COMP7_BLANKING + Comparator 7 blanking + source + 18 + 3 + read-write + + + COMP7OUT + Comparator 7 output + 30 + 1 + read-only + + + COMP7LOCK + Comparator 7 lock + 31 + 1 + read-write + + + + + OPAMP1_CSR + OPAMP1_CSR + control register + 0x38 + 0x20 + 0x0000 + + + OPAMP1_EN + OPAMP1 enable + 0 + 1 + read-write + + + FORCE_VP + FORCE_VP + 1 + 1 + read-write + + + VP_SEL + OPAMP1 Non inverting input + selection + 2 + 2 + read-write + + + VM_SEL + OPAMP1 inverting input + selection + 5 + 2 + read-write + + + TCM_EN + Timer controlled Mux mode + enable + 7 + 1 + read-write + + + VMS_SEL + OPAMP1 inverting input secondary + selection + 8 + 1 + read-write + + + VPS_SEL + OPAMP1 Non inverting input secondary + selection + 9 + 2 + read-write + + + CALON + Calibration mode enable + 11 + 1 + read-write + + + CALSEL + Calibration selection + 12 + 2 + read-write + + + PGA_GAIN + Gain in PGA mode + 14 + 4 + read-write + + + USER_TRIM + User trimming enable + 18 + 1 + read-write + + + TRIMOFFSETP + Offset trimming value + (PMOS) + 19 + 5 + read-write + + + TRIMOFFSETN + Offset trimming value + (NMOS) + 24 + 5 + read-write + + + TSTREF + TSTREF + 29 + 1 + read-write + + + OUTCAL + OPAMP 1 ouput status flag + 30 + 1 + read-only + + + LOCK + OPAMP 1 lock + 31 + 1 + read-write + + + + + OPAMP2_CSR + OPAMP2_CSR + control register + 0x3C + 0x20 + 0x0000 + + + OPAMP2EN + OPAMP2 enable + 0 + 1 + read-write + + + FORCE_VP + FORCE_VP + 1 + 1 + read-write + + + VP_SEL + OPAMP2 Non inverting input + selection + 2 + 2 + read-write + + + VM_SEL + OPAMP2 inverting input + selection + 5 + 2 + read-write + + + TCM_EN + Timer controlled Mux mode + enable + 7 + 1 + read-write + + + VMS_SEL + OPAMP2 inverting input secondary + selection + 8 + 1 + read-write + + + VPS_SEL + OPAMP2 Non inverting input secondary + selection + 9 + 2 + read-write + + + CALON + Calibration mode enable + 11 + 1 + read-write + + + CALSEL + Calibration selection + 12 + 2 + read-write + + + PGA_GAIN + Gain in PGA mode + 14 + 4 + read-write + + + USER_TRIM + User trimming enable + 18 + 1 + read-write + + + TRIMOFFSETP + Offset trimming value + (PMOS) + 19 + 5 + read-write + + + TRIMOFFSETN + Offset trimming value + (NMOS) + 24 + 5 + read-write + + + TSTREF + TSTREF + 29 + 1 + read-write + + + OUTCAL + OPAMP 2 ouput status flag + 30 + 1 + read-only + + + LOCK + OPAMP 2 lock + 31 + 1 + read-write + + + + + OPAMP3_CSR + OPAMP3_CSR + control register + 0x40 + 0x20 + 0x0000 + + + OPAMP3EN + OPAMP3 enable + 0 + 1 + read-write + + + FORCE_VP + FORCE_VP + 1 + 1 + read-write + + + VP_SEL + OPAMP3 Non inverting input + selection + 2 + 2 + read-write + + + VM_SEL + OPAMP3 inverting input + selection + 5 + 2 + read-write + + + TCM_EN + Timer controlled Mux mode + enable + 7 + 1 + read-write + + + VMS_SEL + OPAMP3 inverting input secondary + selection + 8 + 1 + read-write + + + VPS_SEL + OPAMP3 Non inverting input secondary + selection + 9 + 2 + read-write + + + CALON + Calibration mode enable + 11 + 1 + read-write + + + CALSEL + Calibration selection + 12 + 2 + read-write + + + PGA_GAIN + Gain in PGA mode + 14 + 4 + read-write + + + USER_TRIM + User trimming enable + 18 + 1 + read-write + + + TRIMOFFSETP + Offset trimming value + (PMOS) + 19 + 5 + read-write + + + TRIMOFFSETN + Offset trimming value + (NMOS) + 24 + 5 + read-write + + + TSTREF + TSTREF + 29 + 1 + read-write + + + OUTCAL + OPAMP 3 ouput status flag + 30 + 1 + read-only + + + LOCK + OPAMP 3 lock + 31 + 1 + read-write + + + + + OPAMP4_CSR + OPAMP4_CSR + control register + 0x44 + 0x20 + 0x0000 + + + OPAMP4EN + OPAMP4 enable + 0 + 1 + read-write + + + FORCE_VP + FORCE_VP + 1 + 1 + read-write + + + VP_SEL + OPAMP4 Non inverting input + selection + 2 + 2 + read-write + + + VM_SEL + OPAMP4 inverting input + selection + 5 + 2 + read-write + + + TCM_EN + Timer controlled Mux mode + enable + 7 + 1 + read-write + + + VMS_SEL + OPAMP4 inverting input secondary + selection + 8 + 1 + read-write + + + VPS_SEL + OPAMP4 Non inverting input secondary + selection + 9 + 2 + read-write + + + CALON + Calibration mode enable + 11 + 1 + read-write + + + CALSEL + Calibration selection + 12 + 2 + read-write + + + PGA_GAIN + Gain in PGA mode + 14 + 4 + read-write + + + USER_TRIM + User trimming enable + 18 + 1 + read-write + + + TRIMOFFSETP + Offset trimming value + (PMOS) + 19 + 5 + read-write + + + TRIMOFFSETN + Offset trimming value + (NMOS) + 24 + 5 + read-write + + + TSTREF + TSTREF + 29 + 1 + read-write + + + OUTCAL + OPAMP 4 ouput status flag + 30 + 1 + read-only + + + LOCK + OPAMP 4 lock + 31 + 1 + read-write + + + + + SYSCFG_CFGR3 + SYSCFG_CFGR3 + SYSCFG configuration register + 3 + 0x50 + 0x20 + read-write + 0x0000 + + + SPI1_RX_DMA_RMP + SPI1_RX DMA remapping bit + 0 + 2 + + + SPI1_TX_DMA_RMP + SPI1_TX DMA remapping bit + 2 + 2 + + + I2C1_RX_DMA_RMP + I2C1_RX DMA remapping bit + 4 + 2 + + + I2C1_TX_DMA_RMP + I2C1_TX DMA remapping bit + 6 + 2 + + + ADC2_DMA_RMP + ADC2 DMA channel remapping + bit + 8 + 2 + + + + + SYSCFG_CFGR4 + SYSCFG_CFGR4 + SYSCFG configuration register + 4 + 0x48 + 0x20 + read-write + 0x0000 + + + ADC12_EXT2_RMP + Controls the Input trigger of ADC12 + regular channel EXT2 + 0 + 1 + + + ADC12_EXT3_RMP + Controls the Input trigger of ADC12 + regular channel EXT3 + 1 + 1 + + + ADC12_EXT5_RMP + Controls the Input trigger of ADC12 + regular channel EXT5 + 2 + 1 + + + ADC12_EXT13_RMP + Controls the Input trigger of ADC12 + regular channel EXT13 + 3 + 1 + + + ADC12_EXT15_RMP + Controls the Input trigger of ADC12 + regular channel EXT15 + 4 + 1 + + + ADC12_JEXT3_RMP + Controls the Input trigger of ADC12 + injected channel EXTI3 + 5 + 1 + + + ADC12_JEXT6_RMP + Controls the Input trigger of ADC12 + injected channel EXTI6 + 6 + 1 + + + ADC12_JEXT13_RMP + Controls the Input trigger of ADC12 + injected channel EXTI13 + 7 + 1 + + + ADC34_EXT5_RMP + Controls the Input trigger of ADC34 + regular channel EXT5 + 8 + 1 + + + ADC34_EXT6_RMP + Controls the Input trigger of ADC34 + regular channel EXT6 + 9 + 1 + + + ADC34_EXT15_RMP + Controls the Input trigger of ADC34 + regular channel EXT15 + 10 + 1 + + + ADC34_JEXT5_RMP + Controls the Input trigger of ADC34 + injected channel JEXT5 + 11 + 1 + + + ADC34_JEXT11_RMP + Controls the Input trigger of ADC34 + injected channel JEXT11 + 12 + 1 + + + ADC34_JEXT14_RMP + Controls the Input trigger of ADC34 + injected channel JEXT14 + 13 + 1 + + + + + + + FMC + Flexible memory controller + FMC + 0xA0000400 + + 0x0 + 0xC00 + registers + + + FMC + FSMC global interrupt + 48 + + + + BCR1 + BCR1 + SRAM/NOR-Flash chip-select control register + 1 + 0x0 + 0x20 + read-write + 0x000030D0 + + + CCLKEN + CCLKEN + 20 + 1 + + + CBURSTRW + CBURSTRW + 19 + 1 + + + ASYNCWAIT + ASYNCWAIT + 15 + 1 + + + EXTMOD + EXTMOD + 14 + 1 + + + WAITEN + WAITEN + 13 + 1 + + + WREN + WREN + 12 + 1 + + + WAITCFG + WAITCFG + 11 + 1 + + + WAITPOL + WAITPOL + 9 + 1 + + + BURSTEN + BURSTEN + 8 + 1 + + + FACCEN + FACCEN + 6 + 1 + + + MWID + MWID + 4 + 2 + + + MTYP + MTYP + 2 + 2 + + + MUXEN + MUXEN + 1 + 1 + + + MBKEN + MBKEN + 0 + 1 + + + + + BTR1 + BTR1 + SRAM/NOR-Flash chip-select timing register + 1 + 0x4 + 0x20 + read-write + 0xFFFFFFFF + + + ACCMOD + ACCMOD + 28 + 2 + + + DATLAT + DATLAT + 24 + 4 + + + CLKDIV + CLKDIV + 20 + 4 + + + BUSTURN + BUSTURN + 16 + 4 + + + DATAST + DATAST + 8 + 8 + + + ADDHLD + ADDHLD + 4 + 4 + + + ADDSET + ADDSET + 0 + 4 + + + + + BCR2 + BCR2 + SRAM/NOR-Flash chip-select control register + 2 + 0x8 + 0x20 + read-write + 0x000030D0 + + + CBURSTRW + CBURSTRW + 19 + 1 + + + ASYNCWAIT + ASYNCWAIT + 15 + 1 + + + EXTMOD + EXTMOD + 14 + 1 + + + WAITEN + WAITEN + 13 + 1 + + + WREN + WREN + 12 + 1 + + + WAITCFG + WAITCFG + 11 + 1 + + + WRAPMOD + WRAPMOD + 10 + 1 + + + WAITPOL + WAITPOL + 9 + 1 + + + BURSTEN + BURSTEN + 8 + 1 + + + FACCEN + FACCEN + 6 + 1 + + + MWID + MWID + 4 + 2 + + + MTYP + MTYP + 2 + 2 + + + MUXEN + MUXEN + 1 + 1 + + + MBKEN + MBKEN + 0 + 1 + + + + + BTR2 + BTR2 + SRAM/NOR-Flash chip-select timing register + 2 + 0xC + 0x20 + read-write + 0xFFFFFFFF + + + ACCMOD + ACCMOD + 28 + 2 + + + DATLAT + DATLAT + 24 + 4 + + + CLKDIV + CLKDIV + 20 + 4 + + + BUSTURN + BUSTURN + 16 + 4 + + + DATAST + DATAST + 8 + 8 + + + ADDHLD + ADDHLD + 4 + 4 + + + ADDSET + ADDSET + 0 + 4 + + + + + BCR3 + BCR3 + SRAM/NOR-Flash chip-select control register + 3 + 0x10 + 0x20 + read-write + 0x000030D0 + + + CBURSTRW + CBURSTRW + 19 + 1 + + + ASYNCWAIT + ASYNCWAIT + 15 + 1 + + + EXTMOD + EXTMOD + 14 + 1 + + + WAITEN + WAITEN + 13 + 1 + + + WREN + WREN + 12 + 1 + + + WAITCFG + WAITCFG + 11 + 1 + + + WRAPMOD + WRAPMOD + 10 + 1 + + + WAITPOL + WAITPOL + 9 + 1 + + + BURSTEN + BURSTEN + 8 + 1 + + + FACCEN + FACCEN + 6 + 1 + + + MWID + MWID + 4 + 2 + + + MTYP + MTYP + 2 + 2 + + + MUXEN + MUXEN + 1 + 1 + + + MBKEN + MBKEN + 0 + 1 + + + + + BTR3 + BTR3 + SRAM/NOR-Flash chip-select timing register + 3 + 0x14 + 0x20 + read-write + 0xFFFFFFFF + + + ACCMOD + ACCMOD + 28 + 2 + + + DATLAT + DATLAT + 24 + 4 + + + CLKDIV + CLKDIV + 20 + 4 + + + BUSTURN + BUSTURN + 16 + 4 + + + DATAST + DATAST + 8 + 8 + + + ADDHLD + ADDHLD + 4 + 4 + + + ADDSET + ADDSET + 0 + 4 + + + + + BCR4 + BCR4 + SRAM/NOR-Flash chip-select control register + 4 + 0x18 + 0x20 + read-write + 0x000030D0 + + + CBURSTRW + CBURSTRW + 19 + 1 + + + ASYNCWAIT + ASYNCWAIT + 15 + 1 + + + EXTMOD + EXTMOD + 14 + 1 + + + WAITEN + WAITEN + 13 + 1 + + + WREN + WREN + 12 + 1 + + + WAITCFG + WAITCFG + 11 + 1 + + + WRAPMOD + WRAPMOD + 10 + 1 + + + WAITPOL + WAITPOL + 9 + 1 + + + BURSTEN + BURSTEN + 8 + 1 + + + FACCEN + FACCEN + 6 + 1 + + + MWID + MWID + 4 + 2 + + + MTYP + MTYP + 2 + 2 + + + MUXEN + MUXEN + 1 + 1 + + + MBKEN + MBKEN + 0 + 1 + + + + + BTR4 + BTR4 + SRAM/NOR-Flash chip-select timing register + 4 + 0x1C + 0x20 + read-write + 0xFFFFFFFF + + + ACCMOD + ACCMOD + 28 + 2 + + + DATLAT + DATLAT + 24 + 4 + + + CLKDIV + CLKDIV + 20 + 4 + + + BUSTURN + BUSTURN + 16 + 4 + + + DATAST + DATAST + 8 + 8 + + + ADDHLD + ADDHLD + 4 + 4 + + + ADDSET + ADDSET + 0 + 4 + + + + + PCR2 + PCR2 + PC Card/NAND Flash control register + 2 + 0x60 + 0x20 + read-write + 0x00000018 + + + ECCPS + ECCPS + 17 + 3 + + + TAR + TAR + 13 + 4 + + + TCLR + TCLR + 9 + 4 + + + ECCEN + ECCEN + 6 + 1 + + + PWID + PWID + 4 + 2 + + + PTYP + PTYP + 3 + 1 + + + PBKEN + PBKEN + 2 + 1 + + + PWAITEN + PWAITEN + 1 + 1 + + + + + SR2 + SR2 + FIFO status and interrupt register + 2 + 0x64 + 0x20 + 0x00000040 + + + FEMPT + FEMPT + 6 + 1 + read-only + + + IFEN + IFEN + 5 + 1 + read-write + + + ILEN + ILEN + 4 + 1 + read-write + + + IREN + IREN + 3 + 1 + read-write + + + IFS + IFS + 2 + 1 + read-write + + + ILS + ILS + 1 + 1 + read-write + + + IRS + IRS + 0 + 1 + read-write + + + + + PMEM2 + PMEM2 + Common memory space timing register + 2 + 0x68 + 0x20 + read-write + 0xFCFCFCFC + + + MEMHIZx + MEMHIZx + 24 + 8 + + + MEMHOLDx + MEMHOLDx + 16 + 8 + + + MEMWAITx + MEMWAITx + 8 + 8 + + + MEMSETx + MEMSETx + 0 + 8 + + + + + PATT2 + PATT2 + Attribute memory space timing register + 2 + 0x6C + 0x20 + read-write + 0xFCFCFCFC + + + ATTHIZx + ATTHIZx + 24 + 8 + + + ATTHOLDx + ATTHOLDx + 16 + 8 + + + ATTWAITx + ATTWAITx + 8 + 8 + + + ATTSETx + ATTSETx + 0 + 8 + + + + + ECCR2 + ECCR2 + ECC result register 2 + 0x74 + 0x20 + read-only + 0x00000000 + + + ECCx + ECCx + 0 + 32 + + + + + PCR3 + PCR3 + PC Card/NAND Flash control register + 3 + 0x80 + 0x20 + read-write + 0x00000018 + + + ECCPS + ECCPS + 17 + 3 + + + TAR + TAR + 13 + 4 + + + TCLR + TCLR + 9 + 4 + + + ECCEN + ECCEN + 6 + 1 + + + PWID + PWID + 4 + 2 + + + PTYP + PTYP + 3 + 1 + + + PBKEN + PBKEN + 2 + 1 + + + PWAITEN + PWAITEN + 1 + 1 + + + + + SR3 + SR3 + FIFO status and interrupt register + 3 + 0x84 + 0x20 + 0x00000040 + + + FEMPT + FEMPT + 6 + 1 + read-only + + + IFEN + IFEN + 5 + 1 + read-write + + + ILEN + ILEN + 4 + 1 + read-write + + + IREN + IREN + 3 + 1 + read-write + + + IFS + IFS + 2 + 1 + read-write + + + ILS + ILS + 1 + 1 + read-write + + + IRS + IRS + 0 + 1 + read-write + + + + + PMEM3 + PMEM3 + Common memory space timing register + 3 + 0x88 + 0x20 + read-write + 0xFCFCFCFC + + + MEMHIZx + MEMHIZx + 24 + 8 + + + MEMHOLDx + MEMHOLDx + 16 + 8 + + + MEMWAITx + MEMWAITx + 8 + 8 + + + MEMSETx + MEMSETx + 0 + 8 + + + + + PATT3 + PATT3 + Attribute memory space timing register + 3 + 0x8C + 0x20 + read-write + 0xFCFCFCFC + + + ATTHIZx + ATTHIZx + 24 + 8 + + + ATTHOLDx + ATTHOLDx + 16 + 8 + + + ATTWAITx + ATTWAITx + 8 + 8 + + + ATTSETx + ATTSETx + 0 + 8 + + + + + ECCR3 + ECCR3 + ECC result register 3 + 0x94 + 0x20 + read-only + 0x00000000 + + + ECCx + ECCx + 0 + 32 + + + + + PCR4 + PCR4 + PC Card/NAND Flash control register + 4 + 0xA0 + 0x20 + read-write + 0x00000018 + + + ECCPS + ECCPS + 17 + 3 + + + TAR + TAR + 13 + 4 + + + TCLR + TCLR + 9 + 4 + + + ECCEN + ECCEN + 6 + 1 + + + PWID + PWID + 4 + 2 + + + PTYP + PTYP + 3 + 1 + + + PBKEN + PBKEN + 2 + 1 + + + PWAITEN + PWAITEN + 1 + 1 + + + + + SR4 + SR4 + FIFO status and interrupt register + 4 + 0xA4 + 0x20 + 0x00000040 + + + FEMPT + FEMPT + 6 + 1 + read-only + + + IFEN + IFEN + 5 + 1 + read-write + + + ILEN + ILEN + 4 + 1 + read-write + + + IREN + IREN + 3 + 1 + read-write + + + IFS + IFS + 2 + 1 + read-write + + + ILS + ILS + 1 + 1 + read-write + + + IRS + IRS + 0 + 1 + read-write + + + + + PMEM4 + PMEM4 + Common memory space timing register + 4 + 0xA8 + 0x20 + read-write + 0xFCFCFCFC + + + MEMHIZx + MEMHIZx + 24 + 8 + + + MEMHOLDx + MEMHOLDx + 16 + 8 + + + MEMWAITx + MEMWAITx + 8 + 8 + + + MEMSETx + MEMSETx + 0 + 8 + + + + + PATT4 + PATT4 + Attribute memory space timing register + 4 + 0xAC + 0x20 + read-write + 0xFCFCFCFC + + + ATTHIZx + ATTHIZx + 24 + 8 + + + ATTHOLDx + ATTHOLDx + 16 + 8 + + + ATTWAITx + ATTWAITx + 8 + 8 + + + ATTSETx + ATTSETx + 0 + 8 + + + + + PIO4 + PIO4 + I/O space timing register 4 + 0xB0 + 0x20 + read-write + 0xFCFCFCFC + + + IOHIZx + IOHIZx + 24 + 8 + + + IOHOLDx + IOHOLDx + 16 + 8 + + + IOWAITx + IOWAITx + 8 + 8 + + + IOSETx + IOSETx + 0 + 8 + + + + + BWTR1 + BWTR1 + SRAM/NOR-Flash write timing registers + 1 + 0x104 + 0x20 + read-write + 0x0FFFFFFF + + + ACCMOD + ACCMOD + 28 + 2 + + + DATLAT + DATLAT + 24 + 4 + + + CLKDIV + CLKDIV + 20 + 4 + + + BUSTURN + Bus turnaround phase + duration + 16 + 4 + + + DATAST + DATAST + 8 + 8 + + + ADDHLD + ADDHLD + 4 + 4 + + + ADDSET + ADDSET + 0 + 4 + + + + + BWTR2 + BWTR2 + SRAM/NOR-Flash write timing registers + 2 + 0x10C + 0x20 + read-write + 0x0FFFFFFF + + + ACCMOD + ACCMOD + 28 + 2 + + + DATLAT + DATLAT + 24 + 4 + + + CLKDIV + CLKDIV + 20 + 4 + + + BUSTURN + Bus turnaround phase + duration + 16 + 4 + + + DATAST + DATAST + 8 + 8 + + + ADDHLD + ADDHLD + 4 + 4 + + + ADDSET + ADDSET + 0 + 4 + + + + + BWTR3 + BWTR3 + SRAM/NOR-Flash write timing registers + 3 + 0x114 + 0x20 + read-write + 0x0FFFFFFF + + + ACCMOD + ACCMOD + 28 + 2 + + + DATLAT + DATLAT + 24 + 4 + + + CLKDIV + CLKDIV + 20 + 4 + + + BUSTURN + Bus turnaround phase + duration + 16 + 4 + + + DATAST + DATAST + 8 + 8 + + + ADDHLD + ADDHLD + 4 + 4 + + + ADDSET + ADDSET + 0 + 4 + + + + + BWTR4 + BWTR4 + SRAM/NOR-Flash write timing registers + 4 + 0x11C + 0x20 + read-write + 0x0FFFFFFF + + + ACCMOD + ACCMOD + 28 + 2 + + + DATLAT + DATLAT + 24 + 4 + + + CLKDIV + CLKDIV + 20 + 4 + + + BUSTURN + Bus turnaround phase + duration + 16 + 4 + + + DATAST + DATAST + 8 + 8 + + + ADDHLD + ADDHLD + 4 + 4 + + + ADDSET + ADDSET + 0 + 4 + + + + + + + diff --git a/satrs-example-stm32f3-disco/build.rs b/satrs-example-stm32f3-disco/build.rs deleted file mode 100644 index 98f603e..0000000 --- a/satrs-example-stm32f3-disco/build.rs +++ /dev/null @@ -1,18 +0,0 @@ -use std::env; -use std::fs::File; -use std::io::Write; -use std::path::PathBuf; - -fn main() { - // Put the linker script somewhere the linker can find it - let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap()); - File::create(out.join("memory.x")) - .unwrap() - .write_all(include_bytes!("memory.x")) - .unwrap(); - println!("cargo:rustc-link-search={}", out.display()); - - // Only re-run the build script when memory.x is changed, - // instead of when any part of the source code changes. - println!("cargo:rerun-if-changed=memory.x"); -} diff --git a/satrs-example-stm32f3-disco/jlink.gdb b/satrs-example-stm32f3-disco/legacy/jlink.gdb similarity index 100% rename from satrs-example-stm32f3-disco/jlink.gdb rename to satrs-example-stm32f3-disco/legacy/jlink.gdb diff --git a/satrs-example-stm32f3-disco/openocd.cfg b/satrs-example-stm32f3-disco/legacy/openocd.cfg similarity index 100% rename from satrs-example-stm32f3-disco/openocd.cfg rename to satrs-example-stm32f3-disco/legacy/openocd.cfg diff --git a/satrs-example-stm32f3-disco/openocd.gdb b/satrs-example-stm32f3-disco/legacy/openocd.gdb similarity index 92% rename from satrs-example-stm32f3-disco/openocd.gdb rename to satrs-example-stm32f3-disco/legacy/openocd.gdb index 06e81b1..2453de8 100644 --- a/satrs-example-stm32f3-disco/openocd.gdb +++ b/satrs-example-stm32f3-disco/legacy/openocd.gdb @@ -26,7 +26,7 @@ break main # # 8000000 must match the core clock frequency # # 2000000 is the frequency of the SWO pin. This was added for newer # openocd versions like v0.12.0. -monitor tpiu config internal itm.txt uart off 8000000 2000000 +# monitor tpiu config internal itm.txt uart off 8000000 2000000 # # OR: make the microcontroller SWO pin output compatible with UART (8N1) # # 8000000 must match the core clock frequency @@ -34,7 +34,7 @@ monitor tpiu config internal itm.txt uart off 8000000 2000000 # monitor tpiu config external uart off 8000000 2000000 # # enable ITM port 0 -monitor itm port 0 on +# monitor itm port 0 on load diff --git a/satrs-example-stm32f3-disco/src/blinky.rs b/satrs-example-stm32f3-disco/src/bin/blinky.rs similarity index 68% rename from satrs-example-stm32f3-disco/src/blinky.rs rename to satrs-example-stm32f3-disco/src/bin/blinky.rs index eefdbfe..0f96176 100644 --- a/satrs-example-stm32f3-disco/src/blinky.rs +++ b/satrs-example-stm32f3-disco/src/bin/blinky.rs @@ -1,17 +1,15 @@ #![no_std] #![no_main] +use satrs_example_stm32f3_disco as _; -extern crate panic_itm; - -use cortex_m_rt::entry; - +use stm32f3_discovery::leds::Leds; use stm32f3_discovery::stm32f3xx_hal::delay::Delay; use stm32f3_discovery::stm32f3xx_hal::{pac, prelude::*}; -use stm32f3_discovery::leds::Leds; use stm32f3_discovery::switch_hal::{OutputSwitch, ToggleableOutputSwitch}; -#[entry] -fn main()-> ! { +#[cortex_m_rt::entry] +fn main() -> ! { + defmt::println!("STM32F3 Discovery Blinky"); let dp = pac::Peripherals::take().unwrap(); let mut rcc = dp.RCC.constrain(); let cp = cortex_m::Peripherals::take().unwrap(); @@ -30,49 +28,49 @@ fn main()-> ! { gpioe.pe14, gpioe.pe15, &mut gpioe.moder, - &mut gpioe.otyper + &mut gpioe.otyper, ); let delay_ms = 200u16; loop { - leds.ld3.toggle().ok(); + leds.ld3_n.toggle().ok(); delay.delay_ms(delay_ms); - leds.ld3.toggle().ok(); + leds.ld3_n.toggle().ok(); delay.delay_ms(delay_ms); //explicit on/off - leds.ld4.on().ok(); + leds.ld4_nw.on().ok(); delay.delay_ms(delay_ms); - leds.ld4.off().ok(); + leds.ld4_nw.off().ok(); delay.delay_ms(delay_ms); - leds.ld5.on().ok(); + leds.ld5_ne.on().ok(); delay.delay_ms(delay_ms); - leds.ld5.off().ok(); + leds.ld5_ne.off().ok(); delay.delay_ms(delay_ms); - leds.ld6.on().ok(); + leds.ld6_w.on().ok(); delay.delay_ms(delay_ms); - leds.ld6.off().ok(); - delay.delay_ms(delay_ms); - - leds.ld7.on().ok(); - delay.delay_ms(delay_ms); - leds.ld7.off().ok(); - delay.delay_ms(delay_ms); - - leds.ld8.on().ok(); - delay.delay_ms(delay_ms); - leds.ld8.off().ok(); - delay.delay_ms(delay_ms); - - leds.ld9.on().ok(); - delay.delay_ms(delay_ms); - leds.ld9.off().ok(); + leds.ld6_w.off().ok(); delay.delay_ms(delay_ms); - leds.ld10.on().ok(); + leds.ld7_e.on().ok(); delay.delay_ms(delay_ms); - leds.ld10.off().ok(); + leds.ld7_e.off().ok(); + delay.delay_ms(delay_ms); + + leds.ld8_sw.on().ok(); + delay.delay_ms(delay_ms); + leds.ld8_sw.off().ok(); + delay.delay_ms(delay_ms); + + leds.ld9_se.on().ok(); + delay.delay_ms(delay_ms); + leds.ld9_se.off().ok(); + delay.delay_ms(delay_ms); + + leds.ld10_s.on().ok(); + delay.delay_ms(delay_ms); + leds.ld10_s.off().ok(); delay.delay_ms(delay_ms); } } diff --git a/satrs-example-stm32f3-disco/src/lib.rs b/satrs-example-stm32f3-disco/src/lib.rs new file mode 100644 index 0000000..284660c --- /dev/null +++ b/satrs-example-stm32f3-disco/src/lib.rs @@ -0,0 +1,51 @@ +#![no_main] +#![no_std] + +use cortex_m_semihosting::debug; + +use defmt_brtt as _; // global logger + +use stm32f3xx_hal as _; // memory layout + +use panic_probe as _; + +// same panicking *behavior* as `panic-probe` but doesn't print a panic message +// this prevents the panic message being printed *twice* when `defmt::panic` is invoked +#[defmt::panic_handler] +fn panic() -> ! { + cortex_m::asm::udf() +} + +/// Terminates the application and makes a semihosting-capable debug tool exit +/// with status code 0. +pub fn exit() -> ! { + loop { + debug::exit(debug::EXIT_SUCCESS); + } +} + +/// Hardfault handler. +/// +/// Terminates the application and makes a semihosting-capable debug tool exit +/// with an error. This seems better than the default, which is to spin in a +/// loop. +#[cortex_m_rt::exception] +unsafe fn HardFault(_frame: &cortex_m_rt::ExceptionFrame) -> ! { + loop { + debug::exit(debug::EXIT_FAILURE); + } +} + +// defmt-test 0.3.0 has the limitation that this `#[tests]` attribute can only be used +// once within a crate. the module can be in any file but there can only be at most +// one `#[tests]` module in this library crate +#[cfg(test)] +#[defmt_test::tests] +mod unit_tests { + use defmt::assert; + + #[test] + fn it_works() { + assert!(true) + } +} diff --git a/satrs-example-stm32f3-disco/src/main.rs b/satrs-example-stm32f3-disco/src/main.rs index 8795786..3b58200 100644 --- a/satrs-example-stm32f3-disco/src/main.rs +++ b/satrs-example-stm32f3-disco/src/main.rs @@ -1,12 +1,12 @@ #![no_std] #![no_main] -extern crate panic_itm; +// global logger + panicking-behavior + memory layout +use satrs_example_stm32f3_disco as _; use rtic::app; use heapless::{mpmc::Q8, Vec}; #[allow(unused_imports)] -use itm_logger::{debug, info, logger_init, warn}; use rtic_monotonics::systick::fugit::TimerInstantU32; use rtic_monotonics::systick::ExtU32; use satrs::seq_count::SequenceCountProviderCore; @@ -95,14 +95,12 @@ pub struct TxIdle { pub struct TmSender { vec: Option>>, - ctx: &'static str, } impl TmSender { - pub fn new(tm_packet: TmPacket, ctx: &'static str) -> Self { + pub fn new(tm_packet: TmPacket) -> Self { Self { vec: Some(RefCell::new(tm_packet)), - ctx, } } } @@ -131,7 +129,12 @@ impl EcssTmSenderCore for TmSender { } vec.resize(tm.len_written(), 0).expect("vec resize failed"); tm.write_to_bytes(vec.as_mut_slice())?; - info!(target: self.ctx, "Sending TM[{},{}] with size {}", tm.service(), tm.subservice(), tm.len_written()); + defmt::info!( + "Sending TM[{},{}] with size {}", + tm.service(), + tm.subservice(), + tm.len_written() + ); drop(vec); TM_REQUESTS .enqueue(vec_ref.take()) @@ -158,7 +161,6 @@ pub struct UartTxShared { mod app { use super::*; use core::slice::Iter; - use cortex_m::iprintln; use rtic_monotonics::systick::Systick; use rtic_monotonics::Monotonic; use satrs::pus::verification::FailParams; @@ -192,14 +194,13 @@ mod app { } #[init] - fn init(mut cx: init::Context) -> (Shared, Local) { + fn init(cx: init::Context) -> (Shared, Local) { let mut rcc = cx.device.RCC.constrain(); // Initialize the systick interrupt & obtain the token to prove that we did let systick_mono_token = rtic_monotonics::create_systick_token!(); Systick::start(cx.core.SYST, 8_000_000, systick_mono_token); - logger_init(); let mut flash = cx.device.FLASH.constrain(); let clocks = rcc .cfgr @@ -211,11 +212,7 @@ mod app { // Set up monotonic timer. //let mono_timer = MonoTimer::new(cx.core.DWT, clocks, &mut cx.core.DCB); - // setup ITM output - iprintln!( - &mut cx.core.ITM.stim[0], - "Starting sat-rs demo application for the STM32F3-Discovery" - ); + defmt::info!("Starting sat-rs demo application for the STM32F3-Discovery"); let mut gpioe = cx.device.GPIOE.split(&mut rcc.ahb); let verif_reporter = VerificationReporterCore::new(PUS_APID).unwrap(); @@ -265,7 +262,7 @@ mod app { // For some reason, this is also immediately triggered.. tx_serial.clear_event(TxEvent::TransmissionComplete); let rx_transfer = rx_serial.read_exact(unsafe { DMA_RX_BUF.as_mut_slice() }, dma1.ch6); - info!(target: "init", "Spawning tasks"); + defmt::info!("Spawning tasks"); blink::spawn().unwrap(); serial_tx_handler::spawn().unwrap(); ( @@ -399,10 +396,9 @@ mod app { cx: serial_rx_handler::Context, received_packet: Vec, ) { - info!("running rx handler"); - let tgt: &'static str = "serial_rx_handler"; + defmt::info!("running rx handler"); cx.local.stamp_buf[0] = P_FIELD_BASE; - info!(target: tgt, "Received packet with {} bytes", received_packet.len()); + defmt::info!("Received packet with {} bytes", received_packet.len()); let decode_buf = cx.local.decode_buf; let packet = received_packet.as_slice(); let mut start_idx = None; @@ -413,16 +409,13 @@ mod app { } } if start_idx.is_none() { - warn!( - target: tgt, - "decoding error, can only process cobs encoded frames, data is all 0" - ); + defmt::warn!("decoding error, can only process cobs encoded frames, data is all 0"); return; } let start_idx = start_idx.unwrap(); match cobs::decode(&received_packet.as_slice()[start_idx..], decode_buf) { Ok(len) => { - info!(target: tgt, "Decoded packet length: {}", len); + defmt::info!("Decoded packet length: {}", len); let pus_tc = PusTcReader::new(decode_buf); let verif_reporter = cx.local.verif_reporter; match pus_tc { @@ -432,18 +425,15 @@ mod app { verif_reporter, cx.local.src_data_buf, cx.local.stamp_buf, - tgt, ), - Err(e) => { - warn!(target: tgt, "Error unpacking PUS TC: {}", e); + Err(_e) => { + // TODO: Print error after API rework. + defmt::warn!("Error unpacking PUS TC"); } } } Err(_) => { - warn!( - target: tgt, - "decoding error, can only process cobs encoded frames" - ) + defmt::warn!("decoding error, can only process cobs encoded frames") } } } @@ -454,10 +444,8 @@ mod app { verif_reporter: &mut VerificationReporterCore, src_data_buf: &mut [u8; MAX_TM_LEN], stamp_buf: &[u8; 7], - tgt: &'static str, ) { - info!( - target: tgt, + defmt::info!( "Found PUS TC [{},{}] with length {}", tc.service(), tc.subservice(), @@ -466,7 +454,7 @@ mod app { let token = verif_reporter.add_tc(&tc); if tc.apid() != PUS_APID { - warn!(target: tgt, "Received tc with unknown APID {}", tc.apid()); + defmt::warn!("Received tc with unknown APID {}", tc.apid()); let sendable = verif_reporter .acceptance_failure( src_data_buf, @@ -476,9 +464,9 @@ mod app { FailParams::new(stamp_buf, &EcssEnumU16::new(0), &[]), ) .unwrap(); - let sender = TmSender::new(TmPacket::new(), tgt); - if let Err(e) = verif_reporter.send_acceptance_failure(sendable, &sender) { - warn!(target: tgt, "Sending acceptance failure failed: {:?}", e.0); + let sender = TmSender::new(TmPacket::new()); + if let Err(_e) = verif_reporter.send_acceptance_failure(sendable, &sender) { + defmt::warn!("Sending acceptance failure failed"); }; return; } @@ -486,11 +474,12 @@ mod app { .acceptance_success(src_data_buf, token, SEQ_COUNT_PROVIDER.get(), 0, stamp_buf) .unwrap(); - let sender = TmSender::new(TmPacket::new(), tgt); + let sender = TmSender::new(TmPacket::new()); let accepted_token = match verif_reporter.send_acceptance_success(sendable, &sender) { Ok(token) => token, - Err(e) => { - warn!(target: "serial_rx_handler", "Sending acceptance success failed: {:?}", e.0); + Err(_e) => { + // TODO: Print error as soon as EcssTmtcError has Format attr.. or rework API. + defmt::warn!("Sending acceptance success failed"); return; } }; @@ -507,18 +496,16 @@ mod app { ) .unwrap(); // let mem_block = poolmod::TM::alloc().unwrap().init([0u8; MAX_TM_LEN]); - let sender = TmSender::new(TmPacket::new(), tgt); + let sender = TmSender::new(TmPacket::new()); let started_token = match verif_reporter.send_start_success(sendable, &sender) { Ok(token) => token, - Err(e) => { - warn!(target: tgt, "Sending acceptance success failed: {:?}", e.0); + Err(_e) => { + // TODO: Print error as soon as EcssTmtcError has Format attr.. or rework API. + defmt::warn!("Sending acceptance success failed"); return; } }; - info!( - target: tgt, - "Received PUS ping telecommand, sending ping reply TM[17,2]" - ); + defmt::info!("Received PUS ping telecommand, sending ping reply TM[17,2]"); let mut sp_header = SpHeader::tc_unseg(PUS_APID, SEQ_COUNT_PROVIDER.get(), 0).unwrap(); let sec_header = PusTmSecondaryHeader::new_simple(17, 2, stamp_buf); @@ -529,7 +516,7 @@ mod app { .expect("vec resize failed"); ping_reply.write_to_bytes(&mut tm_packet).unwrap(); if TM_REQUESTS.enqueue(tm_packet).is_err() { - warn!(target: tgt, "TC queue full"); + defmt::warn!("TC queue full"); return; } SEQ_COUNT_PROVIDER.increment(); @@ -542,9 +529,9 @@ mod app { stamp_buf, ) .unwrap(); - let sender = TmSender::new(TmPacket::new(), tgt); - if let Err(e) = verif_reporter.send_step_or_completion_success(sendable, &sender) { - warn!(target: tgt, "Sending completion success failed: {:?}", e.0); + let sender = TmSender::new(TmPacket::new()); + if let Err(_e) = verif_reporter.send_step_or_completion_success(sendable, &sender) { + defmt::warn!("Sending completion success failed"); } } else { // TODO: Invalid subservice @@ -573,7 +560,7 @@ mod app { serial_rx_handler::spawn(tc_packet).expect("spawning rx handler task failed"); // If this happens, there is a high chance that the maximum packet length was // exceeded. Circular mode is not used here, so data might be missed. - warn!( + defmt::warn!( "rx transfer with maximum length {}, might miss data", TC_BUF_LEN ); @@ -615,7 +602,6 @@ mod app { .expect("vec resize failed"); tc_packet[0..rx_len as usize].copy_from_slice(&buf[0..rx_len as usize]); rx.clear_event(RxEvent::Idle); - info!("spawning rx task"); serial_rx_handler::spawn(tc_packet).expect("spawning rx handler failed"); *rx_transfer = Some(rx.read_exact(buf, ch)); } diff --git a/satrs-example-stm32f3-disco/vscode/extensions.json b/satrs-example-stm32f3-disco/vscode/extensions.json index 57b3fbb..b310f9b 100644 --- a/satrs-example-stm32f3-disco/vscode/extensions.json +++ b/satrs-example-stm32f3-disco/vscode/extensions.json @@ -5,7 +5,7 @@ // List of extensions which should be recommended for users of this workspace. "recommendations": [ "rust-lang.rust", - "marus25.cortex-debug", + "probe-rs.probe-rs-debugger" ], // List of extensions recommended by VS Code that should not be recommended for users of this workspace. "unwantedRecommendations": [] diff --git a/satrs-example-stm32f3-disco/vscode/launch.json b/satrs-example-stm32f3-disco/vscode/launch.json index f9e65f2..f982d67 100644 --- a/satrs-example-stm32f3-disco/vscode/launch.json +++ b/satrs-example-stm32f3-disco/vscode/launch.json @@ -1,66 +1,22 @@ { - /* - * Requires the Rust Language Server (RLS) and Cortex-Debug extensions - * https://marketplace.visualstudio.com/items?itemName=rust-lang.rust - * https://marketplace.visualstudio.com/items?itemName=marus25.cortex-debug - */ - "version": "0.2.0", - "configurations": [ + "version": "0.2.0", + "configurations": [ + { + "preLaunchTask": "${defaultBuildTask}", + "type": "probe-rs-debug", + "request": "launch", + "name": "probe-rs Debugging ", + "flashingConfig": { + "flashingEnabled": true + }, + "chip": "STM32F303VCTx", + "coreConfigs": [ { - /* Launches debug session for currently open example */ - "type": "cortex-debug", - "request": "launch", - "name": "Debug", - "servertype": "openocd", - "cwd": "${workspaceRoot}", - "preLaunchTask": "cargo build", - "runToEntryPoint": "true", - "executable": "./target/thumbv7em-none-eabihf/debug/satrs-example-stm32f3-disco", - "preLaunchCommands": ["break rust_begin_unwind"], - "device": "STM32F303VCT6", - "configFiles": [ - "${workspaceRoot}/.vscode/openocd-helpers.tcl", - "interface/stlink.cfg", - "target/stm32f3x.cfg" - ], - "svdFile": "${env:HOME}/.svd/STM32F303.svd", - "swoConfig": { - "enabled": true, - "cpuFrequency": 8000000, - "swoFrequency": 2000000, - "source": "probe", - "decoders": [ - { "type": "console", "label": "ITM", "port": 0 } - ] - } - }, - { - /* Launches debug session for currently open example */ - "type": "cortex-debug", - "request": "launch", - "name": "Release", - "servertype": "openocd", - "cwd": "${workspaceRoot}", - "preLaunchTask": "cargo build", - "runToEntryPoint": "true", - "executable": "./target/thumbv7em-none-eabihf/release/satrs-example-stm32f3-disco", - "preLaunchCommands": ["break rust_begin_unwind"], - "device": "STM32F303VCT6", - "configFiles": [ - "${workspaceRoot}/.vscode/openocd-helpers.tcl", - "interface/stlink.cfg", - "target/stm32f3x.cfg" - ], - "svdFile": "${env:HOME}/.svd/STM32F303.svd", - "swoConfig": { - "enabled": true, - "cpuFrequency": 8000000, - "swoFrequency": 2000000, - "source": "probe", - "decoders": [ - { "type": "console", "label": "ITM", "port": 0 } - ] - } + "programBinary": "${workspaceFolder}/target/thumbv7em-none-eabihf/debug/satrs-example-stm32f3-disco", + "rttEnabled": true, + "svdFile": "STM32F303.svd" } - ] -} \ No newline at end of file + ] + } + ] +}