From 04830087da5b28415fee8f49165339f54c53be67 Mon Sep 17 00:00:00 2001
From: Robin Mueller <robin.mueller.m@gmail.com>
Date: Thu, 11 Nov 2021 18:23:54 +0100
Subject: [PATCH] GPIO optimization and tweaks

- Some functions marked inline
- Doc updated
---
 CHANGELOG.md    |  3 +++
 src/clock.rs    |  3 +++
 src/gpio/mod.rs |  2 +-
 src/gpio/reg.rs | 25 ++++++++++---------------
 src/uart.rs     |  5 ++++-
 5 files changed, 21 insertions(+), 17 deletions(-)

diff --git a/CHANGELOG.md b/CHANGELOG.md
index a8b663d..fc5f967 100644
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -8,6 +8,9 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ## [unreleased]
 
+### Changed
+
+- Minor optimizations and tweaks for GPIO module
 
 ## [0.2.0]
 
diff --git a/src/clock.rs b/src/clock.rs
index e8740ae..d0c9656 100644
--- a/src/clock.rs
+++ b/src/clock.rs
@@ -1,3 +1,6 @@
+//! # API for clock related functionality
+//!
+//! This also includes functionality to enable the peripheral clocks
 use crate::time::Hertz;
 use cortex_m::interrupt::{self, Mutex};
 use once_cell::unsync::OnceCell;
diff --git a/src/gpio/mod.rs b/src/gpio/mod.rs
index fd4f8de..53dbe5f 100644
--- a/src/gpio/mod.rs
+++ b/src/gpio/mod.rs
@@ -1,4 +1,4 @@
-//! # GPIO module
+//! # API for the GPIO peripheral
 //!
 //! The implementation of this GPIO module is heavily based on the
 //! [ATSAMD HAL implementation](https://docs.rs/atsamd-hal/0.13.0/atsamd_hal/gpio/v2/index.html).
diff --git a/src/gpio/reg.rs b/src/gpio/reg.rs
index 13f53b9..72e2e76 100644
--- a/src/gpio/reg.rs
+++ b/src/gpio/reg.rs
@@ -200,11 +200,13 @@ pub(super) unsafe trait RegisterInterface {
         }
     }
 
+    #[inline]
     fn get_perid(&self) -> u32 {
         let portreg = self.port_reg();
         portreg.perid.read().bits()
     }
 
+    #[inline]
     /// Read the logic level of an output pin
     fn read_pin(&self) -> bool {
         let portreg = self.port_reg();
@@ -220,27 +222,25 @@ pub(super) unsafe trait RegisterInterface {
 
     /// Read a pin but use the masked version but check whether the datamask for the pin is
     /// cleared as well
+    #[inline]
     fn read_pin_masked(&self) -> Result<bool, PinError> {
         if !self.datamask() {
             Err(PinError::IsMasked)
         } else {
-            let portreg = self.port_reg();
-            Ok(((portreg.datain().read().bits() >> self.id().num) & 0x01) == 1)
+            Ok(((self.port_reg().datain().read().bits() >> self.id().num) & 0x01) == 1)
         }
     }
 
     /// Write the logic level of an output pin
     #[inline]
     fn write_pin(&mut self, bit: bool) {
-        let portreg = self.port_reg();
-        let mask = self.mask_32();
         // Safety: SETOUT is a "mask" register, and we only write the bit for
         // this pin ID
         unsafe {
             if bit {
-                portreg.setout().write(|w| w.bits(mask));
+                self.port_reg().setout().write(|w| w.bits(self.mask_32()));
             } else {
-                portreg.clrout().write(|w| w.bits(mask));
+                self.port_reg().clrout().write(|w| w.bits(self.mask_32()));
             }
         }
     }
@@ -252,15 +252,13 @@ pub(super) unsafe trait RegisterInterface {
         if !self.datamask() {
             Err(PinError::IsMasked)
         } else {
-            let portreg = self.port_reg();
-            let mask = self.mask_32();
             // Safety: SETOUT is a "mask" register, and we only write the bit for
             // this pin ID
             unsafe {
                 if bit {
-                    portreg.setout().write(|w| w.bits(mask));
+                    self.port_reg().setout().write(|w| w.bits(self.mask_32()));
                 } else {
-                    portreg.clrout().write(|w| w.bits(mask));
+                    self.port_reg().clrout().write(|w| w.bits(self.mask_32()));
                 }
                 Ok(())
             }
@@ -270,18 +268,15 @@ pub(super) unsafe trait RegisterInterface {
     /// Toggle the logic level of an output pin
     #[inline]
     fn toggle(&mut self) {
-        let portreg = self.port_reg();
-        let mask = self.mask_32();
         // Safety: TOGOUT is a "mask" register, and we only write the bit for
         // this pin ID
-        unsafe { portreg.togout().write(|w| w.bits(mask)) };
+        unsafe { self.port_reg().togout().write(|w| w.bits(self.mask_32())) };
     }
 
     /// Only useful for input pins
     #[inline]
     fn filter_type(&self, filter: FilterType, clksel: FilterClkSel) {
-        let iocfg = self.iocfg_port();
-        iocfg.port[self.id().num as usize].modify(|_, w| {
+        self.iocfg_port().port[self.id().num as usize].modify(|_, w| {
             // Safety: Only write to register for this Pin ID
             unsafe {
                 w.flttype().bits(filter as u8);
diff --git a/src/uart.rs b/src/uart.rs
index 499a189..60355f5 100644
--- a/src/uart.rs
+++ b/src/uart.rs
@@ -1,4 +1,7 @@
-//! API for the UART peripheral
+//! # API for the UART peripheral
+//!
+//! ## Examples
+//! - [UART example](https://github.com/robamu-org/va108xx-hal-rs/blob/main/examples/uart.rs)
 use core::{convert::Infallible, ptr};
 use core::{marker::PhantomData, ops::Deref};
 use libm::floorf;