Merge #24
24: Bump to v0.2.3 r=robamu a=robamu - Added API to reset peripherals - Improved API of timer. - Separation of TIM reg and TIM pin interface Co-authored-by: Robin Mueller <robin.mueller.m@gmail.com>
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commit
54e016f0e3
@ -6,12 +6,17 @@ All notable changes to this project will be documented in this file.
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The format is based on [Keep a Changelog](http://keepachangelog.com/)
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and this project adheres to [Semantic Versioning](http://semver.org/).
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## [unreleased]
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## [0.2.3]
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### Added
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- Basic API for EDAC functionality
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- PWM implementation and example
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- API to perform peripheral resets
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### Changed
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- Improved Timer API. It is now possible to simply use `new` on `CountDownTimer`
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## [0.2.2]
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@ -1,6 +1,6 @@
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[package]
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name = "va108xx-hal"
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version = "0.2.2"
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version = "0.2.3"
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authors = ["Robin Mueller <robin.mueller.m@gmail.com>"]
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edition = "2021"
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description = "HAL for the Vorago VA108xx family of microcontrollers"
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@ -139,7 +139,7 @@ fn main() -> ! {
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}
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// Application logic
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let mut delay_tim = CountDownTimer::tim1(&mut dp.SYSCONFIG, 50.mhz().into(), dp.TIM1);
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let mut delay_tim = CountDownTimer::new(&mut dp.SYSCONFIG, 50.mhz().into(), dp.TIM1);
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loop {
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match SPI_BUS_SEL {
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SpiBusSelect::SpiAPortA | SpiBusSelect::SpiAPortB => {
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@ -163,7 +163,7 @@ fn main() -> ! {
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delay.delay_ms(500);
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}
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let mut delay_timer = CountDownTimer::tim1(&mut dp.SYSCONFIG, 50.mhz().into(), dp.TIM1);
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let mut delay_timer = CountDownTimer::new(&mut dp.SYSCONFIG, 50.mhz().into(), dp.TIM1);
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let mut pa0 = pinsa.pa0.into_push_pull_output();
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for _ in 0..5 {
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led1.toggle().ok();
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@ -72,7 +72,7 @@ fn main() -> ! {
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interrupt::OC0,
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);
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let mut second_timer =
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CountDownTimer::tim1(&mut dp.SYSCONFIG, get_sys_clock().unwrap(), dp.TIM1);
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CountDownTimer::new(&mut dp.SYSCONFIG, get_sys_clock().unwrap(), dp.TIM1);
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second_timer.listen(
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Event::TimeOut,
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&mut dp.SYSCONFIG,
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18
src/clock.rs
18
src/clock.rs
@ -2,28 +2,14 @@
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//!
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//! This also includes functionality to enable the peripheral clocks
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use crate::time::Hertz;
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use crate::utility::PeripheralSelect;
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use cortex_m::interrupt::{self, Mutex};
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use once_cell::unsync::OnceCell;
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use va108xx::SYSCONFIG;
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static SYS_CLOCK: Mutex<OnceCell<Hertz>> = Mutex::new(OnceCell::new());
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#[derive(Copy, Clone, PartialEq)]
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pub enum PeripheralClocks {
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PortA = 0,
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PortB = 1,
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Spi0 = 4,
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Spi1 = 5,
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Spi2 = 6,
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Uart0 = 8,
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Uart1 = 9,
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I2c0 = 16,
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I2c1 = 17,
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Irqsel = 21,
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Ioconfig = 22,
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Utility = 23,
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Gpio = 24,
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}
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pub type PeripheralClocks = PeripheralSelect;
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#[derive(Debug, PartialEq)]
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pub enum FilterClkSel {
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40
src/pwm.rs
40
src/pwm.rs
@ -41,7 +41,7 @@ macro_rules! pwm_common_func {
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#[inline]
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fn enable_pwm_a(&mut self) {
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self.reg
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.get_reg_block()
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.reg()
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.ctrl
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.modify(|_, w| unsafe { w.status_sel().bits(StatusSelPwm::PwmA as u8) });
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}
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@ -49,7 +49,7 @@ macro_rules! pwm_common_func {
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#[inline]
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fn enable_pwm_b(&mut self) {
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self.reg
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.get_reg_block()
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.reg()
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.ctrl
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.modify(|_, w| unsafe { w.status_sel().bits(StatusSelPwm::PwmB as u8) });
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}
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@ -69,7 +69,7 @@ macro_rules! pwm_common_func {
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self.pwm_base.current_rst_val =
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self.pwm_base.sys_clk.0 / self.pwm_base.current_period.0;
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self.reg
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.get_reg_block()
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.reg()
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.rst_value
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.write(|w| unsafe { w.bits(self.pwm_base.current_rst_val) });
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}
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@ -98,7 +98,7 @@ macro_rules! pwmb_func {
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* self.pwm_base.current_lower_limit as u64)
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/ DUTY_MAX as u64;
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self.reg
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.get_reg_block()
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.reg()
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.pwmb_value
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.write(|w| unsafe { w.bits(pwmb_val as u32) });
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}
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@ -115,7 +115,7 @@ macro_rules! pwmb_func {
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* self.pwm_base.current_duty as u64)
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/ DUTY_MAX as u64;
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self.reg
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.get_reg_block()
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.reg()
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.pwma_value()
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.write(|w| unsafe { w.bits(pwma_val as u32) });
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}
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@ -127,7 +127,7 @@ macro_rules! pwmb_func {
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//==================================================================================================
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pub struct PwmPin<PIN: TimPin, TIM: ValidTim, MODE = PWMA> {
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reg: TimRegister<PIN, TIM>,
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reg: TimAndPinRegister<PIN, TIM>,
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pwm_base: PwmBase,
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_mode: PhantomData<MODE>,
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}
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@ -151,7 +151,7 @@ where
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current_rst_val: 0,
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sys_clk: sys_clk.into(),
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},
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reg: unsafe { TimRegister::new(vtp.0, vtp.1) },
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reg: unsafe { TimAndPinRegister::new(vtp.0, vtp.1) },
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_mode: PhantomData,
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};
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enable_peripheral_clock(sys_cfg, crate::clock::PeripheralClocks::Gpio);
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@ -308,18 +308,12 @@ macro_rules! pwm_pin_impl {
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() => {
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#[inline]
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fn disable(&mut self) {
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self.reg
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.get_reg_block()
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.ctrl
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.modify(|_, w| w.enable().clear_bit());
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self.reg.reg().ctrl.modify(|_, w| w.enable().clear_bit());
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}
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#[inline]
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fn enable(&mut self) {
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self.reg
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.get_reg_block()
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.ctrl
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.modify(|_, w| w.enable().set_bit());
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self.reg.reg().ctrl.modify(|_, w| w.enable().set_bit());
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}
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#[inline]
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@ -329,7 +323,7 @@ macro_rules! pwm_pin_impl {
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* (DUTY_MAX as u64 - self.pwm_base.current_duty as u64))
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/ DUTY_MAX as u64;
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self.reg
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.get_reg_block()
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.reg()
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.pwma_value()
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.write(|w| unsafe { w.bits(pwma_val as u32) });
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}
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@ -350,18 +344,12 @@ macro_rules! pwm_impl {
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() => {
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#[inline]
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fn disable(&mut self, _channel: Self::Channel) {
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self.reg
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.get_reg_block()
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.ctrl
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.modify(|_, w| w.enable().clear_bit());
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self.reg.reg().ctrl.modify(|_, w| w.enable().clear_bit());
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}
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#[inline]
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fn enable(&mut self, _channel: Self::Channel) {
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self.reg
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.get_reg_block()
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.ctrl
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.modify(|_, w| w.enable().set_bit());
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self.reg.reg().ctrl.modify(|_, w| w.enable().set_bit());
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}
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#[inline]
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@ -376,7 +364,7 @@ macro_rules! pwm_impl {
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* (DUTY_MAX as u64 - self.pwm_base.current_duty as u64))
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/ DUTY_MAX as u64;
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self.reg
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.get_reg_block()
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.reg()
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.pwma_value()
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.write(|w| unsafe { w.bits(pwma_val as u32) });
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}
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@ -393,7 +381,7 @@ macro_rules! pwm_impl {
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}
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self.pwm_base.current_rst_val =
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self.pwm_base.sys_clk.0 / self.pwm_base.current_period.0;
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let reg_block = self.reg.get_reg_block();
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let reg_block = self.reg.reg();
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reg_block
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.rst_value
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.write(|w| unsafe { w.bits(self.pwm_base.current_rst_val) });
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268
src/timer.rs
268
src/timer.rs
@ -11,7 +11,10 @@ use crate::{
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PA9, PB0, PB1, PB10, PB11, PB12, PB13, PB14, PB15, PB16, PB17, PB18, PB19, PB2, PB20, PB21,
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PB22, PB23, PB3, PB4, PB5, PB6,
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},
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pac::{self, tim0},
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pac::{
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self, tim0, TIM0, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM15, TIM16, TIM17, TIM18,
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TIM19, TIM2, TIM20, TIM21, TIM22, TIM23, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TIM9,
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},
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prelude::*,
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private::Sealed,
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time::Hertz,
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@ -161,7 +164,7 @@ pin_and_tim!(PB1, AltFunc3, 1, TIM1);
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pin_and_tim!(PB0, AltFunc3, 0, TIM0);
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//==================================================================================================
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// Register Interface
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// Register Interface for TIM registers and TIM pins
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//==================================================================================================
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pub type TimRegBlock = tim0::RegisterBlock;
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@ -173,20 +176,19 @@ pub type TimRegBlock = tim0::RegisterBlock;
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///
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/// # Safety
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///
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/// Users should only implement the [`id`] function. No default function
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/// Users should only implement the [`tim_id`] function. No default function
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/// implementations should be overridden. The implementing type must also have
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/// "control" over the corresponding pin ID, i.e. it must guarantee that a each
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/// pin ID is a singleton.
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pub(super) unsafe trait TimRegInterface {
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fn tim_id(&self) -> u8;
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fn pin_id(&self) -> DynPinId;
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const PORT_BASE: *const tim0::RegisterBlock = TIM0::ptr() as *const _;
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/// All 24 TIM blocks are identical. This helper functions returns the correct
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/// memory mapped peripheral depending on the TIM ID.
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#[inline(always)]
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fn get_reg_block(&self) -> &TimRegBlock {
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fn reg(&self) -> &TimRegBlock {
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unsafe { &*Self::PORT_BASE.offset(self.tim_id() as isize) }
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}
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@ -194,24 +196,85 @@ pub(super) unsafe trait TimRegInterface {
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fn mask_32(&self) -> u32 {
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1 << self.tim_id()
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}
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/// Clear the reset bit of the TIM, holding it in reset
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///
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/// # Safety
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///
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/// Only the bit related to the corresponding TIM peripheral is modified
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#[inline]
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fn clear_tim_reset_bit(&self) {
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unsafe {
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va108xx::Peripherals::steal()
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.SYSCONFIG
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.tim_reset
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.modify(|r, w| w.bits(r.bits() & !self.mask_32()))
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}
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}
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#[inline]
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fn set_tim_reset_bit(&self) {
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unsafe {
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va108xx::Peripherals::steal()
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.SYSCONFIG
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.tim_reset
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.modify(|r, w| w.bits(r.bits() | self.mask_32()))
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}
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}
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}
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/// Register interface.
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///
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/// This interface provides an interface for TIM pins to access their corresponding
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/// configuration
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///
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/// # Safety
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///
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/// Users should only implement the [`pin_id`] function. No default function
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/// implementations should be overridden. The implementing type must also have
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/// "control" over the corresponding pin ID, i.e. it must guarantee that a each
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/// pin ID is a singleton.
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pub(super) unsafe trait TimPinInterface {
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fn pin_id(&self) -> DynPinId;
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}
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/// Provide a safe register interface for [`ValidTimAndPin`]s
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///
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/// This `struct` takes ownership of a [`ValidTimAndPin`] and provides an API to
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/// access the corresponding registers.
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pub(super) struct TimRegister<PIN: TimPin, TIM: ValidTim> {
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pub(super) struct TimAndPinRegister<PIN: TimPin, TIM: ValidTim> {
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pin: PIN,
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tim: TIM,
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}
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impl<PIN: TimPin, TIM: ValidTim> TimRegister<PIN, TIM>
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pub(super) struct TimRegister<TIM: ValidTim> {
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tim: TIM,
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}
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impl<TIM: ValidTim> TimRegister<TIM> {
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#[inline]
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pub(super) unsafe fn new(tim: TIM) -> Self {
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TimRegister { tim }
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}
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pub(super) fn release(self) -> TIM {
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self.tim
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}
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}
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unsafe impl<TIM: ValidTim> TimRegInterface for TimRegister<TIM> {
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fn tim_id(&self) -> u8 {
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TIM::TIM_ID
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}
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}
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impl<PIN: TimPin, TIM: ValidTim> TimAndPinRegister<PIN, TIM>
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where
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(PIN, TIM): ValidTimAndPin<PIN, TIM>,
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{
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#[inline]
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pub(super) unsafe fn new(pin: PIN, tim: TIM) -> Self {
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TimRegister { pin, tim }
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TimAndPinRegister { pin, tim }
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}
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pub(super) fn release(self) -> (PIN, TIM) {
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@ -219,12 +282,14 @@ where
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}
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}
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unsafe impl<PIN: TimPin, TIM: ValidTim> TimRegInterface for TimRegister<PIN, TIM> {
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unsafe impl<PIN: TimPin, TIM: ValidTim> TimRegInterface for TimAndPinRegister<PIN, TIM> {
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#[inline(always)]
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fn tim_id(&self) -> u8 {
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TIM::TIM_ID
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}
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}
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unsafe impl<PIN: TimPin, TIM: ValidTim> TimPinInterface for TimAndPinRegister<PIN, TIM> {
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#[inline(always)]
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fn pin_id(&self) -> DynPinId {
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PIN::DYN
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@ -236,8 +301,8 @@ pub(super) struct TimDynRegister {
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pin_id: DynPinId,
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}
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impl<PIN: TimPin, TIM: ValidTim> From<TimRegister<PIN, TIM>> for TimDynRegister {
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fn from(_reg: TimRegister<PIN, TIM>) -> Self {
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impl<PIN: TimPin, TIM: ValidTim> From<TimAndPinRegister<PIN, TIM>> for TimDynRegister {
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fn from(_reg: TimAndPinRegister<PIN, TIM>) -> Self {
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Self {
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tim_id: TIM::TIM_ID,
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pin_id: PIN::DYN,
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@ -250,7 +315,9 @@ unsafe impl TimRegInterface for TimDynRegister {
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fn tim_id(&self) -> u8 {
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self.tim_id
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}
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}
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unsafe impl TimPinInterface for TimDynRegister {
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#[inline(always)]
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fn pin_id(&self) -> DynPinId {
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self.pin_id
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@ -262,8 +329,8 @@ unsafe impl TimRegInterface for TimDynRegister {
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//==================================================================================================
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|
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/// Hardware timers
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pub struct CountDownTimer<TIM> {
|
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tim: TIM,
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pub struct CountDownTimer<TIM: ValidTim> {
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tim: TimRegister<TIM>,
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curr_freq: Hertz,
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sys_clk: Hertz,
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rst_val: u32,
|
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@ -277,29 +344,26 @@ fn enable_tim_clk(syscfg: &mut SYSCONFIG, idx: u8) {
|
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.modify(|r, w| unsafe { w.bits(r.bits() | (1 << idx)) });
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}
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|
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macro_rules! timers {
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($($TIM:ident: ($tim:ident, $i:expr),)+) => {
|
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$(
|
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use crate::pac::$TIM;
|
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unsafe impl<TIM: ValidTim> TimRegInterface for CountDownTimer<TIM> {
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fn tim_id(&self) -> u8 {
|
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TIM::TIM_ID
|
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}
|
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}
|
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|
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impl CountDownTimer<$TIM> {
|
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// XXX(why not name this `new`?) bummer: constructors need to have different names
|
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// even if the `$TIM` are non overlapping (compare to the `free` function below
|
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// which just works)
|
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impl<TIM: ValidTim> CountDownTimer<TIM> {
|
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/// Configures a TIM peripheral as a periodic count down timer
|
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pub fn $tim(
|
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syscfg: &mut SYSCONFIG, sys_clk: Hertz, tim: $TIM
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) -> Self {
|
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enable_tim_clk(syscfg, $i);
|
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tim.ctrl.modify(|_, w| w.enable().set_bit());
|
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CountDownTimer {
|
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tim,
|
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pub fn new(syscfg: &mut SYSCONFIG, sys_clk: Hertz, tim: TIM) -> Self {
|
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enable_tim_clk(syscfg, TIM::TIM_ID);
|
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let cd_timer = CountDownTimer {
|
||||
tim: unsafe { TimRegister::new(tim) },
|
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sys_clk,
|
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rst_val: 0,
|
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curr_freq: 0.hz(),
|
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listening: false,
|
||||
last_cnt: 0,
|
||||
}
|
||||
};
|
||||
cd_timer.tim.reg().ctrl.modify(|_, w| w.enable().set_bit());
|
||||
cd_timer
|
||||
}
|
||||
|
||||
/// Listen for events. This also actives the IRQ in the IRQSEL register
|
||||
@ -315,48 +379,58 @@ macro_rules! timers {
|
||||
match event {
|
||||
Event::TimeOut => {
|
||||
enable_peripheral_clock(syscfg, PeripheralClocks::Irqsel);
|
||||
irqsel.tim[$i].write(|w| unsafe { w.bits(interrupt as u32) });
|
||||
self.tim.ctrl.modify(|_, w| w.irq_enb().set_bit());
|
||||
irqsel.tim[TIM::TIM_ID as usize].write(|w| unsafe { w.bits(interrupt as u32) });
|
||||
self.tim.reg().ctrl.modify(|_, w| w.irq_enb().set_bit());
|
||||
self.listening = true;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
pub fn unlisten(
|
||||
&mut self, event: Event, syscfg: &mut SYSCONFIG, irqsel: &mut IRQSEL
|
||||
) {
|
||||
pub fn unlisten(&mut self, event: Event, syscfg: &mut SYSCONFIG, irqsel: &mut IRQSEL) {
|
||||
match event {
|
||||
Event::TimeOut => {
|
||||
enable_peripheral_clock(syscfg, PeripheralClocks::Irqsel);
|
||||
irqsel.tim[$i].write(|w| unsafe { w.bits(IRQ_DST_NONE) });
|
||||
self.tim.ctrl.modify(|_, w| w.irq_enb().clear_bit());
|
||||
irqsel.tim[TIM::TIM_ID as usize].write(|w| unsafe { w.bits(IRQ_DST_NONE) });
|
||||
self.tim.reg().ctrl.modify(|_, w| w.irq_enb().clear_bit());
|
||||
self.listening = false;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
pub fn release(self, syscfg: &mut SYSCONFIG) -> $TIM {
|
||||
self.tim.ctrl.write(|w| w.enable().clear_bit());
|
||||
pub fn release(self, syscfg: &mut SYSCONFIG) -> TIM {
|
||||
self.tim.reg().ctrl.write(|w| w.enable().clear_bit());
|
||||
syscfg
|
||||
.tim_clk_enable
|
||||
.modify(|r, w| unsafe { w.bits(r.bits() & !(1 << $i)) });
|
||||
self.tim
|
||||
.modify(|r, w| unsafe { w.bits(r.bits() & !(1 << TIM::TIM_ID)) });
|
||||
self.tim.release()
|
||||
}
|
||||
|
||||
pub fn auto_disable(self, enable: bool) -> Self {
|
||||
if enable {
|
||||
self.tim.ctrl.modify(|_, w| w.auto_disable().set_bit());
|
||||
self.tim
|
||||
.reg()
|
||||
.ctrl
|
||||
.modify(|_, w| w.auto_disable().set_bit());
|
||||
} else {
|
||||
self.tim.ctrl.modify(|_, w| w.auto_disable().clear_bit());
|
||||
self.tim
|
||||
.reg()
|
||||
.ctrl
|
||||
.modify(|_, w| w.auto_disable().clear_bit());
|
||||
}
|
||||
self
|
||||
}
|
||||
|
||||
pub fn auto_deactivate(self, enable: bool) -> Self {
|
||||
if enable {
|
||||
self.tim.ctrl.modify(|_, w| w.auto_deactivate().set_bit());
|
||||
self.tim
|
||||
.reg()
|
||||
.ctrl
|
||||
.modify(|_, w| w.auto_deactivate().set_bit());
|
||||
} else {
|
||||
self.tim.ctrl.modify(|_, w| w.auto_deactivate().clear_bit());
|
||||
self.tim
|
||||
.reg()
|
||||
.ctrl
|
||||
.modify(|_, w| w.auto_deactivate().clear_bit());
|
||||
}
|
||||
self
|
||||
}
|
||||
@ -368,34 +442,31 @@ macro_rules! timers {
|
||||
pub fn listening(&self) -> bool {
|
||||
self.listening
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/// CountDown implementation for TIMx
|
||||
impl CountDown for CountDownTimer<$TIM> {
|
||||
/// CountDown implementation for TIMx
|
||||
impl<TIM: ValidTim> CountDown for CountDownTimer<TIM> {
|
||||
type Time = Hertz;
|
||||
|
||||
fn start<T>(&mut self, timeout: T)
|
||||
where
|
||||
T: Into<Hertz>,
|
||||
{
|
||||
self.tim.ctrl.modify(|_, w| w.enable().clear_bit());
|
||||
self.tim.reg().ctrl.modify(|_, w| w.enable().clear_bit());
|
||||
self.curr_freq = timeout.into();
|
||||
self.rst_val = self.sys_clk.0 / self.curr_freq.0;
|
||||
unsafe {
|
||||
self.tim.rst_value.write(|w| w.bits(self.rst_val));
|
||||
self.tim.cnt_value.write(|w| w.bits(self.rst_val));
|
||||
self.tim.reg().rst_value.write(|w| w.bits(self.rst_val));
|
||||
self.tim.reg().cnt_value.write(|w| w.bits(self.rst_val));
|
||||
}
|
||||
self.tim.ctrl.modify(|_, w| w.enable().set_bit());
|
||||
self.tim.reg().ctrl.modify(|_, w| w.enable().set_bit());
|
||||
}
|
||||
|
||||
/// Return `Ok` if the timer has wrapped. Peripheral will automatically clear the
|
||||
/// flag and restart the time if configured correctly
|
||||
fn wait(&mut self) -> nb::Result<(), Void> {
|
||||
let cnt = self.tim.cnt_value.read().bits();
|
||||
if cnt > self.last_cnt {
|
||||
self.last_cnt = self.rst_val;
|
||||
Ok(())
|
||||
} else if cnt == 0 {
|
||||
let cnt = self.tim.reg().cnt_value.read().bits();
|
||||
if (cnt > self.last_cnt) || cnt == 0 {
|
||||
self.last_cnt = self.rst_val;
|
||||
Ok(())
|
||||
} else {
|
||||
@ -403,30 +474,30 @@ macro_rules! timers {
|
||||
Err(nb::Error::WouldBlock)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
impl Periodic for CountDownTimer<$TIM> {}
|
||||
impl<TIM: ValidTim> Periodic for CountDownTimer<TIM> {}
|
||||
|
||||
impl Cancel for CountDownTimer<$TIM> {
|
||||
impl<TIM: ValidTim> Cancel for CountDownTimer<TIM> {
|
||||
type Error = TimerErrors;
|
||||
fn cancel(&mut self) -> Result<(), Self::Error> {
|
||||
if !self.tim.ctrl.read().enable().bit_is_set() {
|
||||
if !self.tim.reg().ctrl.read().enable().bit_is_set() {
|
||||
return Err(TimerErrors::Canceled);
|
||||
}
|
||||
self.tim.ctrl.write(|w| w.enable().clear_bit());
|
||||
self.tim.reg().ctrl.write(|w| w.enable().clear_bit());
|
||||
Ok(())
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/// Delay for microseconds.
|
||||
///
|
||||
/// For delays less than 100 us, an assembly delay will be used.
|
||||
/// For larger delays, the timer peripheral will be used.
|
||||
/// Please note that the delay using the peripheral might not
|
||||
/// work properly in debug mode.
|
||||
impl delay::DelayUs<u32> for CountDownTimer<$TIM> {
|
||||
/// Delay for microseconds.
|
||||
///
|
||||
/// For delays less than 100 us, an assembly delay will be used.
|
||||
/// For larger delays, the timer peripheral will be used.
|
||||
/// Please note that the delay using the peripheral might not
|
||||
/// work properly in debug mode.
|
||||
impl<TIM: ValidTim> delay::DelayUs<u32> for CountDownTimer<TIM> {
|
||||
fn delay_us(&mut self, us: u32) {
|
||||
if(us < 100) {
|
||||
if us < 100 {
|
||||
cortex_m::asm::delay(us * (self.sys_clk.0 / 2_000_000));
|
||||
} else {
|
||||
// Configuring the peripheral for higher frequencies is unstable
|
||||
@ -438,41 +509,37 @@ macro_rules! timers {
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
/// Forwards call to u32 variant of delay
|
||||
impl delay::DelayUs<u16> for CountDownTimer<$TIM> {
|
||||
}
|
||||
/// Forwards call to u32 variant of delay
|
||||
impl<TIM: ValidTim> delay::DelayUs<u16> for CountDownTimer<TIM> {
|
||||
fn delay_us(&mut self, us: u16) {
|
||||
self.delay_us(u32::from(us));
|
||||
}
|
||||
}
|
||||
/// Forwards call to u32 variant of delay
|
||||
impl delay::DelayUs<u8> for CountDownTimer<$TIM> {
|
||||
}
|
||||
/// Forwards call to u32 variant of delay
|
||||
impl<TIM: ValidTim> delay::DelayUs<u8> for CountDownTimer<TIM> {
|
||||
fn delay_us(&mut self, us: u8) {
|
||||
self.delay_us(u32::from(us));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
impl delay::DelayMs<u32> for CountDownTimer<$TIM> {
|
||||
impl<TIM: ValidTim> delay::DelayMs<u32> for CountDownTimer<TIM> {
|
||||
fn delay_ms(&mut self, ms: u32) {
|
||||
self.start(1000.hz());
|
||||
for _ in 0..ms {
|
||||
nb::block!(self.wait()).unwrap();
|
||||
}
|
||||
}
|
||||
}
|
||||
impl delay::DelayMs<u16> for CountDownTimer<$TIM> {
|
||||
}
|
||||
impl<TIM: ValidTim> delay::DelayMs<u16> for CountDownTimer<TIM> {
|
||||
fn delay_ms(&mut self, ms: u16) {
|
||||
self.delay_ms(u32::from(ms));
|
||||
}
|
||||
}
|
||||
impl embedded_hal::blocking::delay::DelayMs<u8> for CountDownTimer<$TIM> {
|
||||
}
|
||||
impl<TIM: ValidTim> embedded_hal::blocking::delay::DelayMs<u8> for CountDownTimer<TIM> {
|
||||
fn delay_ms(&mut self, ms: u8) {
|
||||
self.delay_ms(u32::from(ms));
|
||||
}
|
||||
}
|
||||
|
||||
)+
|
||||
}
|
||||
}
|
||||
|
||||
// Set up a millisecond timer on TIM0. Please note that you still need to unmask the related IRQ
|
||||
@ -484,7 +551,7 @@ pub fn set_up_ms_timer(
|
||||
tim0: TIM0,
|
||||
irq: pac::Interrupt,
|
||||
) -> CountDownTimer<TIM0> {
|
||||
let mut ms_timer = CountDownTimer::tim0(syscfg, sys_clk, tim0);
|
||||
let mut ms_timer = CountDownTimer::new(syscfg, sys_clk, tim0);
|
||||
ms_timer.listen(timer::Event::TimeOut, syscfg, irqsel, irq);
|
||||
ms_timer.start(1000.hz());
|
||||
ms_timer
|
||||
@ -505,33 +572,6 @@ pub fn get_ms_ticks() -> u32 {
|
||||
cortex_m::interrupt::free(|cs| MS_COUNTER.borrow(cs).get())
|
||||
}
|
||||
|
||||
timers! {
|
||||
TIM0: (tim0, 0),
|
||||
TIM1: (tim1, 1),
|
||||
TIM2: (tim2, 2),
|
||||
TIM3: (tim3, 3),
|
||||
TIM4: (tim4, 4),
|
||||
TIM5: (tim5, 5),
|
||||
TIM6: (tim6, 6),
|
||||
TIM7: (tim7, 7),
|
||||
TIM8: (tim8, 8),
|
||||
TIM9: (tim9, 9),
|
||||
TIM10: (tim10, 10),
|
||||
TIM11: (tim11, 11),
|
||||
TIM12: (tim12, 12),
|
||||
TIM13: (tim13, 13),
|
||||
TIM14: (tim14, 14),
|
||||
TIM15: (tim15, 15),
|
||||
TIM16: (tim16, 16),
|
||||
TIM17: (tim17, 17),
|
||||
TIM18: (tim18, 18),
|
||||
TIM19: (tim19, 19),
|
||||
TIM20: (tim20, 20),
|
||||
TIM21: (tim21, 21),
|
||||
TIM22: (tim22, 22),
|
||||
TIM23: (tim23, 23),
|
||||
}
|
||||
|
||||
//==================================================================================================
|
||||
// Delay implementations
|
||||
//==================================================================================================
|
||||
|
||||
@ -10,6 +10,23 @@ pub enum UtilityError {
|
||||
InvalidCounterResetVal,
|
||||
}
|
||||
|
||||
#[derive(Copy, Clone, PartialEq)]
|
||||
pub enum PeripheralSelect {
|
||||
PortA = 0,
|
||||
PortB = 1,
|
||||
Spi0 = 4,
|
||||
Spi1 = 5,
|
||||
Spi2 = 6,
|
||||
Uart0 = 8,
|
||||
Uart1 = 9,
|
||||
I2c0 = 16,
|
||||
I2c1 = 17,
|
||||
Irqsel = 21,
|
||||
Ioconfig = 22,
|
||||
Utility = 23,
|
||||
Gpio = 24,
|
||||
}
|
||||
|
||||
/// Enable scrubbing for the ROM
|
||||
///
|
||||
/// Returns [`UtilityError::InvalidCounterResetVal`] if the scrub rate is 0
|
||||
@ -41,3 +58,17 @@ pub fn enable_ram_scrubbing(syscfg: &mut SYSCONFIG, scrub_rate: u32) -> Result<(
|
||||
pub fn disable_ram_scrubbing(syscfg: &mut SYSCONFIG) {
|
||||
syscfg.ram_scrub.write(|w| unsafe { w.bits(0) })
|
||||
}
|
||||
|
||||
/// Clear the reset bit. This register is active low, so doing this will hold the peripheral
|
||||
/// in a reset state
|
||||
pub fn clear_reset_bit(syscfg: &mut SYSCONFIG, periph_sel: PeripheralSelect) {
|
||||
syscfg
|
||||
.peripheral_reset
|
||||
.modify(|r, w| unsafe { w.bits(r.bits() & !(1 << periph_sel as u8)) });
|
||||
}
|
||||
|
||||
pub fn set_reset_bit(syscfg: &mut SYSCONFIG, periph_sel: PeripheralSelect) {
|
||||
syscfg
|
||||
.peripheral_reset
|
||||
.modify(|r, w| unsafe { w.bits(r.bits() | (1 << periph_sel as u8)) });
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user