update changelog and manifest
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- Clippy fixes
This commit is contained in:
Robin Müller 2021-12-20 11:36:02 +01:00
parent a8b484d66f
commit 9a5c9ac53c
3 changed files with 17 additions and 19 deletions

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@ -6,7 +6,12 @@ All notable changes to this project will be documented in this file.
The format is based on [Keep a Changelog](http://keepachangelog.com/)
and this project adheres to [Semantic Versioning](http://semver.org/).
## [unreleased]
## [v0.5.0]
- Reactored IRQ handling, so that `unmask` operations can be moved to HAL
- Added UART IRQ handler. Right now, can only perform reception, TX still needs to be done in
a blocking manner
- Added RTIC template and RTIC UART IRQ application
## [v0.4.3]

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@ -1,6 +1,6 @@
[package]
name = "va108xx-hal"
version = "0.4.3"
version = "0.5.0"
authors = ["Robin Mueller <muellerr@irs.uni-stuttgart.de>"]
edition = "2021"
description = "HAL for the Vorago VA108xx family of microcontrollers"
@ -28,7 +28,6 @@ rt = ["va108xx/rt"]
[dev-dependencies]
cortex-m-rtic = "0.6.0-rc.4"
arrayvec = { version = "0.7.2", default-features = false }
panic-rtt-target = { version = "0.1", features = ["cortex-m"] }
rtt-target = { version = "0.3", features = ["cortex-m"] }
panic-halt = "0.2"

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@ -701,29 +701,27 @@ impl<UART: Instance> UartWithIrqBase<UART> {
let read_handler =
|res: &mut IrqResult, read_res: nb::Result<u8, Error>| -> Result<Option<u8>, Error> {
match read_res {
Ok(byte) => return Ok(Some(byte)),
Err(nb::Error::WouldBlock) => {
return Ok(None);
}
Ok(byte) => Ok(Some(byte)),
Err(nb::Error::WouldBlock) => Ok(None),
Err(nb::Error::Other(e)) => match e {
Error::Overrun => {
res.set_result(IrqResultMask::Overflow);
return Err(Error::IrqError);
Err(Error::IrqError)
}
Error::FramingError => {
res.set_result(IrqResultMask::FramingError);
return Err(Error::IrqError);
Err(Error::IrqError)
}
Error::ParityError => {
res.set_result(IrqResultMask::ParityError);
return Err(Error::IrqError);
Err(Error::IrqError)
}
_ => {
res.set_result(IrqResultMask::Unknown);
return Err(Error::IrqError);
Err(Error::IrqError)
}
},
};
}
};
if irq_end.irq_rx().bit_is_set() {
// If this interrupt bit is set, the trigger level is available at the very least.
@ -771,13 +769,9 @@ impl<UART: Instance> UartWithIrqBase<UART> {
if rx_status.rxto().bit_is_set() {
// A timeout has occured but there might be some leftover data in the FIFO,
// so read that data as well
loop {
if let Some(byte) = read_handler(res, self.uart.read())? {
while let Some(byte) = read_handler(res, self.uart.read())? {
buf[self.irq_info.rx_idx] = byte;
self.irq_info.rx_idx += 1;
} else {
break;
}
}
self.irq_completion_handler(res);
res.set_result(IrqResultMask::Timeout);