Added PWM implementation and example
This commit is contained in:
249
src/timer.rs
249
src/timer.rs
@ -5,8 +5,15 @@
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//! - [MS and second tick implementation](https://github.com/robamu-org/va108xx-hal-rs/blob/main/examples/timer-ticks.rs)
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use crate::{
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clock::{enable_peripheral_clock, PeripheralClocks},
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pac,
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gpio::{
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AltFunc1, AltFunc2, AltFunc3, DynPinId, Pin, PinId, PA0, PA1, PA10, PA11, PA12, PA13, PA14,
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PA15, PA2, PA24, PA25, PA26, PA27, PA28, PA29, PA3, PA30, PA31, PA4, PA5, PA6, PA7, PA8,
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PA9, PB0, PB1, PB10, PB11, PB12, PB13, PB14, PB15, PB16, PB17, PB18, PB19, PB2, PB20, PB21,
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PB22, PB23, PB3, PB4, PB5, PB6,
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},
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pac::{self, tim0},
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prelude::*,
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private::Sealed,
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time::Hertz,
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timer,
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};
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@ -22,15 +29,9 @@ use void::Void;
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const IRQ_DST_NONE: u32 = 0xffffffff;
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pub static MS_COUNTER: Mutex<Cell<u32>> = Mutex::new(Cell::new(0));
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/// Hardware timers
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pub struct CountDownTimer<TIM> {
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tim: TIM,
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curr_freq: Hertz,
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sys_clk: Hertz,
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rst_val: u32,
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last_cnt: u32,
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listening: bool,
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}
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//==================================================================================================
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// Defintions
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//==================================================================================================
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/// Interrupt events
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pub enum Event {
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@ -42,6 +43,234 @@ pub enum TimerErrors {
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Canceled,
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}
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//==================================================================================================
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// Valid TIM and PIN combinations
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//==================================================================================================
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pub trait TimPin {
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const DYN: DynPinId;
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}
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pub trait ValidTim {
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// TIM ID ranging from 0 to 23 for 24 TIM peripherals
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const TIM_ID: u8;
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}
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macro_rules! tim_marker {
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($TIMX:ident, $ID:expr) => {
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impl ValidTim for $TIMX {
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const TIM_ID: u8 = $ID;
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}
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};
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}
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tim_marker!(TIM0, 0);
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tim_marker!(TIM1, 1);
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tim_marker!(TIM2, 2);
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tim_marker!(TIM3, 3);
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tim_marker!(TIM4, 4);
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tim_marker!(TIM5, 5);
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tim_marker!(TIM6, 6);
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tim_marker!(TIM7, 7);
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tim_marker!(TIM8, 8);
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tim_marker!(TIM9, 9);
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tim_marker!(TIM10, 10);
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tim_marker!(TIM11, 11);
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tim_marker!(TIM12, 12);
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tim_marker!(TIM13, 13);
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tim_marker!(TIM14, 14);
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tim_marker!(TIM15, 15);
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tim_marker!(TIM16, 16);
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tim_marker!(TIM17, 17);
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tim_marker!(TIM18, 18);
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tim_marker!(TIM19, 19);
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tim_marker!(TIM20, 20);
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tim_marker!(TIM21, 21);
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tim_marker!(TIM22, 22);
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tim_marker!(TIM23, 23);
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pub trait ValidTimAndPin<PIN: TimPin, TIM: ValidTim>: Sealed {}
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macro_rules! pin_and_tim {
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($PAX:ident, $ALTFUNC:ident, $ID:expr, $TIMX:ident) => {
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impl TimPin for Pin<$PAX, $ALTFUNC>
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where
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$PAX: PinId,
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{
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const DYN: DynPinId = $PAX::DYN;
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}
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impl<PIN: TimPin, TIM: ValidTim> ValidTimAndPin<PIN, TIM> for (Pin<$PAX, $ALTFUNC>, $TIMX)
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where
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Pin<$PAX, $ALTFUNC>: TimPin,
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$PAX: PinId,
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{
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}
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impl Sealed for (Pin<$PAX, $ALTFUNC>, $TIMX) {}
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};
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}
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pin_and_tim!(PA31, AltFunc2, 23, TIM23);
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pin_and_tim!(PA30, AltFunc2, 22, TIM22);
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pin_and_tim!(PA29, AltFunc2, 21, TIM21);
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pin_and_tim!(PA28, AltFunc2, 20, TIM20);
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pin_and_tim!(PA27, AltFunc2, 19, TIM19);
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pin_and_tim!(PA26, AltFunc2, 18, TIM18);
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pin_and_tim!(PA25, AltFunc2, 17, TIM17);
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pin_and_tim!(PA24, AltFunc2, 16, TIM16);
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pin_and_tim!(PA15, AltFunc1, 15, TIM15);
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pin_and_tim!(PA14, AltFunc1, 14, TIM14);
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pin_and_tim!(PA13, AltFunc1, 13, TIM13);
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pin_and_tim!(PA12, AltFunc1, 12, TIM12);
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pin_and_tim!(PA11, AltFunc1, 11, TIM11);
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pin_and_tim!(PA10, AltFunc1, 10, TIM10);
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pin_and_tim!(PA9, AltFunc1, 9, TIM9);
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pin_and_tim!(PA8, AltFunc1, 8, TIM8);
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pin_and_tim!(PA7, AltFunc1, 7, TIM7);
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pin_and_tim!(PA6, AltFunc1, 6, TIM6);
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pin_and_tim!(PA5, AltFunc1, 5, TIM5);
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pin_and_tim!(PA4, AltFunc1, 4, TIM4);
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pin_and_tim!(PA3, AltFunc1, 3, TIM3);
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pin_and_tim!(PA2, AltFunc1, 2, TIM2);
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pin_and_tim!(PA1, AltFunc1, 1, TIM1);
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pin_and_tim!(PA0, AltFunc1, 0, TIM0);
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pin_and_tim!(PB23, AltFunc3, 23, TIM23);
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pin_and_tim!(PB22, AltFunc3, 22, TIM22);
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pin_and_tim!(PB21, AltFunc3, 21, TIM21);
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pin_and_tim!(PB20, AltFunc3, 20, TIM20);
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pin_and_tim!(PB19, AltFunc3, 19, TIM19);
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pin_and_tim!(PB18, AltFunc3, 18, TIM18);
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pin_and_tim!(PB17, AltFunc3, 17, TIM17);
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pin_and_tim!(PB16, AltFunc3, 16, TIM16);
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pin_and_tim!(PB15, AltFunc3, 15, TIM15);
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pin_and_tim!(PB14, AltFunc3, 14, TIM14);
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pin_and_tim!(PB13, AltFunc3, 13, TIM13);
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pin_and_tim!(PB12, AltFunc3, 12, TIM12);
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pin_and_tim!(PB11, AltFunc3, 11, TIM11);
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pin_and_tim!(PB10, AltFunc3, 10, TIM10);
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pin_and_tim!(PB6, AltFunc3, 6, TIM6);
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pin_and_tim!(PB5, AltFunc3, 5, TIM5);
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pin_and_tim!(PB4, AltFunc3, 4, TIM4);
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pin_and_tim!(PB3, AltFunc3, 3, TIM3);
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pin_and_tim!(PB2, AltFunc3, 2, TIM2);
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pin_and_tim!(PB1, AltFunc3, 1, TIM1);
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pin_and_tim!(PB0, AltFunc3, 0, TIM0);
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//==================================================================================================
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// Register Interface
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//==================================================================================================
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pub type TimRegBlock = tim0::RegisterBlock;
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/// Register interface.
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///
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/// This interface provides valid TIM pins a way to access their corresponding TIM
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/// registers
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///
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/// # Safety
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///
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/// Users should only implement the [`id`] function. No default function
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/// implementations should be overridden. The implementing type must also have
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/// "control" over the corresponding pin ID, i.e. it must guarantee that a each
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/// pin ID is a singleton.
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pub(super) unsafe trait TimRegInterface {
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fn tim_id(&self) -> u8;
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fn pin_id(&self) -> DynPinId;
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const PORT_BASE: *const tim0::RegisterBlock = TIM0::ptr() as *const _;
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/// All 24 TIM blocks are identical. This helper functions returns the correct
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/// memory mapped peripheral depending on the TIM ID.
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#[inline(always)]
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fn get_reg_block(&self) -> &TimRegBlock {
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unsafe { &*Self::PORT_BASE.offset(self.tim_id() as isize) }
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}
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#[inline(always)]
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fn mask_32(&self) -> u32 {
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1 << self.tim_id()
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}
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}
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/// Provide a safe register interface for [`ValidTimAndPin`]s
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///
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/// This `struct` takes ownership of a [`ValidTimAndPin`] and provides an API to
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/// access the corresponding registers.
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pub(super) struct TimRegister<PIN: TimPin, TIM: ValidTim> {
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pin: PIN,
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tim: TIM,
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}
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impl<PIN: TimPin, TIM: ValidTim> TimRegister<PIN, TIM>
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where
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(PIN, TIM): ValidTimAndPin<PIN, TIM>,
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{
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#[inline]
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pub(super) unsafe fn new(pin: PIN, tim: TIM) -> Self {
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TimRegister { pin, tim }
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}
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pub(super) fn release(self) -> (PIN, TIM) {
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(self.pin, self.tim)
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}
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}
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unsafe impl<PIN: TimPin, TIM: ValidTim> TimRegInterface for TimRegister<PIN, TIM> {
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#[inline(always)]
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fn tim_id(&self) -> u8 {
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TIM::TIM_ID
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}
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#[inline(always)]
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fn pin_id(&self) -> DynPinId {
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PIN::DYN
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}
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}
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pub(super) struct TimDynRegister {
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tim_id: u8,
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pin_id: DynPinId,
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}
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impl<PIN: TimPin, TIM: ValidTim> From<TimRegister<PIN, TIM>> for TimDynRegister {
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fn from(_reg: TimRegister<PIN, TIM>) -> Self {
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Self {
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tim_id: TIM::TIM_ID,
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pin_id: PIN::DYN,
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}
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}
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}
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unsafe impl TimRegInterface for TimDynRegister {
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#[inline(always)]
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fn tim_id(&self) -> u8 {
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self.tim_id
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}
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#[inline(always)]
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fn pin_id(&self) -> DynPinId {
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self.pin_id
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}
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}
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//==================================================================================================
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// Timers
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//==================================================================================================
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/// Hardware timers
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pub struct CountDownTimer<TIM> {
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tim: TIM,
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curr_freq: Hertz,
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sys_clk: Hertz,
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rst_val: u32,
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last_cnt: u32,
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listening: bool,
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}
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fn enable_tim_clk(syscfg: &mut SYSCONFIG, idx: u8) {
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syscfg
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.tim_clk_enable
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