diff --git a/Cargo.toml b/Cargo.toml
index a6dfde1..8072074 100644
--- a/Cargo.toml
+++ b/Cargo.toml
@@ -45,3 +45,15 @@ opt-level = "s"
 # [profile.release-lto]
 # inherits = "release"
 # lto = true
+
+[[example]]
+name = "timer-ticks"
+required-features = ["rt"]
+
+[[example]]
+name = "tests"
+required-features = ["rt"]
+
+[[example]]
+name = "cascade"
+required-features = ["rt"]
diff --git a/examples/cascade.rs b/examples/cascade.rs
index 3b1c363..03e5c09 100644
--- a/examples/cascade.rs
+++ b/examples/cascade.rs
@@ -11,7 +11,7 @@ use cortex_m_rt::entry;
 use panic_rtt_target as _;
 use rtt_target::{rprintln, rtt_init_print};
 use va108xx_hal::{
-    pac::{self, interrupt, TIM4, TIM5},
+    pac::{self, Interrupt, TIM4, TIM5},
     prelude::*,
     timer::{
         default_ms_irq_handler, set_up_ms_delay_provider, CascadeCtrl, CascadeSource,
diff --git a/src/gpio/dynpins.rs b/src/gpio/dynpins.rs
index 5513fa7..3d91504 100644
--- a/src/gpio/dynpins.rs
+++ b/src/gpio/dynpins.rs
@@ -67,7 +67,7 @@ use super::{
 use crate::{
     clock::FilterClkSel,
     pac::{IRQSEL, SYSCONFIG},
-    utility::{IrqCfg, Funsel},
+    utility::{Funsel, IrqCfg},
 };
 use embedded_hal::digital::v2::{InputPin, OutputPin, ToggleableOutputPin};
 use paste::paste;
@@ -346,7 +346,7 @@ impl DynPin {
         edge_type: InterruptEdge,
         irq_cfg: IrqCfg,
         syscfg: Option<&mut SYSCONFIG>,
-        irqsel: Option<&mut IRQSEL>
+        irqsel: Option<&mut IRQSEL>,
     ) -> Result<Self, PinError> {
         match self.mode {
             DynPinMode::Input(_) | DynPinMode::Output(_) => {
@@ -363,7 +363,7 @@ impl DynPin {
         level_type: InterruptLevel,
         irq_cfg: IrqCfg,
         syscfg: Option<&mut SYSCONFIG>,
-        irqsel: Option<&mut IRQSEL>
+        irqsel: Option<&mut IRQSEL>,
     ) -> Result<Self, PinError> {
         match self.mode {
             DynPinMode::Input(_) | DynPinMode::Output(_) => {
diff --git a/src/gpio/pins.rs b/src/gpio/pins.rs
index d11c04e..ea9dba4 100644
--- a/src/gpio/pins.rs
+++ b/src/gpio/pins.rs
@@ -94,8 +94,8 @@ use super::reg::RegisterInterface;
 use crate::{
     pac::{IOCONFIG, IRQSEL, PORTA, PORTB, SYSCONFIG},
     typelevel::Is,
+    utility::IrqCfg,
     Sealed,
-    utility::IrqCfg
 };
 use core::convert::Infallible;
 use core::marker::PhantomData;
@@ -361,7 +361,6 @@ impl<I: PinId, M: PinMode> AnyPin for Pin<I, M> {
 macro_rules! common_reg_if_functions {
     () => {
         paste!(
-
             #[inline]
             pub fn datamask(&self) -> bool {
                 self.regs.datamask()
@@ -403,7 +402,7 @@ macro_rules! common_reg_if_functions {
                 &mut self,
                 irq_cfg: crate::utility::IrqCfg,
                 syscfg: Option<&mut va108xx::SYSCONFIG>,
-                irqsel: Option<&mut va108xx::IRQSEL>
+                irqsel: Option<&mut va108xx::IRQSEL>,
             ) {
                 if syscfg.is_some() {
                     crate::clock::enable_peripheral_clock(
@@ -585,7 +584,7 @@ impl<I: PinId, C: InputConfig> Pin<I, Input<C>> {
         edge_type: InterruptEdge,
         irq_cfg: IrqCfg,
         syscfg: Option<&mut SYSCONFIG>,
-        irqsel: Option<&mut IRQSEL>
+        irqsel: Option<&mut IRQSEL>,
     ) -> Self {
         self.regs.interrupt_edge(edge_type);
         self.irq_enb(irq_cfg, syscfg, irqsel);
@@ -597,7 +596,7 @@ impl<I: PinId, C: InputConfig> Pin<I, Input<C>> {
         level_type: InterruptLevel,
         irq_cfg: IrqCfg,
         syscfg: Option<&mut SYSCONFIG>,
-        irqsel: Option<&mut IRQSEL>
+        irqsel: Option<&mut IRQSEL>,
     ) -> Self {
         self.regs.interrupt_level(level_type);
         self.irq_enb(irq_cfg, syscfg, irqsel);
@@ -630,7 +629,7 @@ impl<I: PinId, C: OutputConfig> Pin<I, Output<C>> {
         edge_type: InterruptEdge,
         irq_cfg: IrqCfg,
         syscfg: Option<&mut SYSCONFIG>,
-        irqsel: Option<&mut IRQSEL>
+        irqsel: Option<&mut IRQSEL>,
     ) -> Self {
         self.regs.interrupt_edge(edge_type);
         self.irq_enb(irq_cfg, syscfg, irqsel);
@@ -642,7 +641,7 @@ impl<I: PinId, C: OutputConfig> Pin<I, Output<C>> {
         level_type: InterruptLevel,
         irq_cfg: IrqCfg,
         syscfg: Option<&mut SYSCONFIG>,
-        irqsel: Option<&mut IRQSEL>
+        irqsel: Option<&mut IRQSEL>,
     ) -> Self {
         self.regs.interrupt_level(level_type);
         self.irq_enb(irq_cfg, syscfg, irqsel);
diff --git a/src/timer.rs b/src/timer.rs
index 19b3607..99d0c80 100644
--- a/src/timer.rs
+++ b/src/timer.rs
@@ -7,7 +7,6 @@
 pub use crate::utility::IrqCfg;
 use crate::{
     clock::{enable_peripheral_clock, PeripheralClocks},
-    utility::unmask_irq,
     gpio::{
         AltFunc1, AltFunc2, AltFunc3, DynPinId, Pin, PinId, PA0, PA1, PA10, PA11, PA12, PA13, PA14,
         PA15, PA2, PA24, PA25, PA26, PA27, PA28, PA29, PA3, PA30, PA31, PA4, PA5, PA6, PA7, PA8,
@@ -22,6 +21,7 @@ use crate::{
     private::Sealed,
     time::Hertz,
     timer,
+    utility::unmask_irq,
 };
 use core::cell::Cell;
 use cortex_m::interrupt::Mutex;
diff --git a/src/uart.rs b/src/uart.rs
index 225ac81..6882418 100644
--- a/src/uart.rs
+++ b/src/uart.rs
@@ -16,9 +16,9 @@ use crate::{
         PA31, PA8, PA9, PB18, PB19, PB20, PB21, PB22, PB23, PB6, PB7, PB8, PB9,
     },
     pac::{uarta as uart_base, IRQSEL, SYSCONFIG, UARTA, UARTB},
-    utility::unmask_irq,
     prelude::*,
     time::{Bps, Hertz},
+    utility::unmask_irq,
 };
 
 use embedded_hal::{blocking, serial};
diff --git a/src/utility.rs b/src/utility.rs
index 8101a32..2f8a609 100644
--- a/src/utility.rs
+++ b/src/utility.rs
@@ -139,6 +139,6 @@ pub fn port_mux(
 ///
 /// The unmask function can break mask-based critical sections
 #[inline]
-pub (crate) fn unmask_irq(irq: pac::Interrupt) {
+pub(crate) fn unmask_irq(irq: pac::Interrupt) {
     unsafe { cortex_m::peripheral::NVIC::unmask(irq) };
 }