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Author SHA1 Message Date
Robin Müller 3eb92f8e10
run cargo fmt
Rust/va108xx-hal/pipeline/head This commit looks good Details
2022-05-22 22:33:49 +02:00
Robin Müller dc4639b2f0
some timer extensions
Rust/va108xx-hal/pipeline/head This commit looks good Details
2022-05-02 16:23:19 +02:00
14 changed files with 89 additions and 89 deletions

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@ -6,15 +6,6 @@ All notable changes to this project will be documented in this file.
The format is based on [Keep a Changelog](http://keepachangelog.com/)
and this project adheres to [Semantic Versioning](http://semver.org/).
## [v0.5.1]
### Changes
- Updated dependencies:
- `cortex-m-rtic` (dev-depencency) to 1.1.2
- `once_cell` to 1.12.0
- Other dependencies: Only revision has changed
## [v0.5.0]
### Added

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@ -1,6 +1,6 @@
[package]
name = "va108xx-hal"
version = "0.5.1"
version = "0.5.0"
authors = ["Robin Mueller <muellerr@irs.uni-stuttgart.de>"]
edition = "2021"
description = "HAL for the Vorago VA108xx family of microcontrollers"
@ -8,43 +8,30 @@ homepage = "https://egit.irs.uni-stuttgart.de/rust/va108xx-hal"
repository = "https://egit.irs.uni-stuttgart.de/rust/va108xx-hal"
license = "Apache-2.0"
keywords = ["no-std", "hal", "cortex-m", "vorago", "va108xx"]
categories = ["aerospace", "embedded", "no-std", "hardware-support"]
categories = ["embedded", "no-std", "hardware-support"]
[dependencies]
va108xx = "0.2.4"
cortex-m = "0.7"
cortex-m-rt = "0.7"
nb = "1"
paste = "1.0"
libm = "0.2"
embedded-hal = { features = ["unproven"], version = "0.2.6" }
void = { version = "1.0", default-features = false }
once_cell = { version = "1.8.0", default-features = false }
libm = "0.2.1"
[dependencies.embedded-hal]
version = "0.2.7"
features = ["unproven"]
[dependencies.void]
version = "1.0"
default-features = false
[dependencies.once_cell]
version = "1.14"
default-features = false
[dependencies.va108xx]
version = "0.2.4"
[features]
rt = ["va108xx/rt"]
[dev-dependencies]
cortex-m-rtic = "1.1.2"
cortex-m-rtic = "0.6.0-rc.4"
panic-rtt-target = { version = "0.1", features = ["cortex-m"] }
rtt-target = { version = "0.3", features = ["cortex-m"] }
panic-halt = "0.2"
[dev-dependencies.rtt-target]
version = "0.3"
features = ["cortex-m"]
[dev-dependencies.panic-rtt-target]
version = "0.1"
features = ["cortex-m"]
[profile.dev]
debug = true
lto = false

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@ -1,5 +1,5 @@
[![Crates.io](https://img.shields.io/crates/v/va108xx-hal)](https://crates.io/crates/va108xx-hal)
[![ci](https://github.com/us-irs/va108xx-hal-rs/actions/workflows/ci.yml/badge.svg)](https://github.com/us-irs/va108xx-hal-rs/actions/workflows/ci.yml)
[![ci](https://github.com/robamu-org/va108xx-hal-rs/actions/workflows/ci.yml/badge.svg)](https://github.com/robamu-org/va108xx-hal-rs/actions/workflows/ci.yml)
[![docs.rs](https://img.shields.io/docsrs/va108xx-hal)](https://docs.rs/va108xx-hal)
# HAL for the Vorago VA108xx MCU family
@ -63,7 +63,7 @@ is contained within the
1. Set up your Rust cross-compiler if you have not done so yet. See more in the [build chapter](#Building)
2. Create a new binary crate with `cargo init`
3. To ensure that `cargo build` cross-compiles, it is recommended to create a `.cargo/config.toml`
3. To ensure that `cargo build` cross-compiles, it is recommended to create a `cargo/config.toml`
file. A sample `.cargo/config.toml` file is provided in this repository as well
4. Copy the `memory.x` file into your project. This file contains information required by the linker.
5. Copy the `blinky.rs` file to the `src/main.rs` file in your binary crate

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@ -7,7 +7,5 @@ RUN apt-get --yes upgrade
# tzdata is a dependency, won't install otherwise
ARG DEBIAN_FRONTEND=noninteractive
RUN rustup install nightly && \
rustup target add thumbv6m-none-eabi && \
rustup +nightly target add thumbv6m-none-eabi && \
RUN rustup target add thumbv6m-none-eabi && \
rustup component add rustfmt clippy

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@ -1,34 +1,47 @@
pipeline {
agent {
dockerfile {
dir 'automation'
reuseNode true
}
}
agent any
stages {
stage('Clippy') {
agent {
dockerfile {
dir 'automation'
reuseNode true
}
}
steps {
sh 'cargo clippy'
}
}
stage('Rustfmt') {
agent {
dockerfile {
dir 'automation'
reuseNode true
}
}
steps {
sh 'cargo fmt'
}
}
stage('Docs') {
steps {
sh 'cargo +nightly doc'
}
}
stage('Check') {
agent {
dockerfile {
dir 'automation'
reuseNode true
}
}
steps {
sh 'cargo check --target thumbv6m-none-eabi'
}
}
stage('Check Examples') {
agent {
dockerfile {
dir 'automation'
reuseNode true
}
}
steps {
sh 'cargo check --target thumbv6m-none-eabi --examples'
}

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@ -11,7 +11,7 @@ static SYS_CLOCK: Mutex<OnceCell<Hertz>> = Mutex::new(OnceCell::new());
pub type PeripheralClocks = PeripheralSelect;
#[derive(Debug, PartialEq, Eq)]
#[derive(Debug, PartialEq)]
pub enum FilterClkSel {
SysClk = 0,
Clk1 = 1,

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@ -143,14 +143,14 @@ pub const DYN_ALT_FUNC_3: DynPinMode = DynPinMode::Alternate(DynAlternate::Funse
//==================================================================================================
/// Value-level `enum` for pin groups
#[derive(PartialEq, Eq, Clone, Copy)]
#[derive(PartialEq, Clone, Copy)]
pub enum DynGroup {
A,
B,
}
/// Value-level `struct` representing pin IDs
#[derive(PartialEq, Eq, Clone, Copy)]
#[derive(PartialEq, Clone, Copy)]
pub struct DynPinId {
pub group: DynGroup,
pub num: u8,

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@ -106,27 +106,27 @@ use paste::paste;
// Errors and Definitions
//==================================================================================================
#[derive(Debug, PartialEq, Eq)]
#[derive(Debug, PartialEq)]
pub enum InterruptEdge {
HighToLow,
LowToHigh,
BothEdges,
}
#[derive(Debug, PartialEq, Eq)]
#[derive(Debug, PartialEq)]
pub enum InterruptLevel {
Low = 0,
High = 1,
}
#[derive(Debug, PartialEq, Eq)]
#[derive(Debug, PartialEq)]
pub enum PinState {
Low = 0,
High = 1,
}
/// GPIO error type
#[derive(Debug, PartialEq, Eq)]
#[derive(Debug, PartialEq)]
pub enum PinError {
/// The pin did not have the correct ID or mode for the requested operation.
/// [`DynPin`](crate::gpio::DynPin)s are not tracked and verified at compile-time, so run-time
@ -182,7 +182,7 @@ pub struct Input<C: InputConfig> {
impl<C: InputConfig> Sealed for Input<C> {}
#[derive(Debug, PartialEq, Eq)]
#[derive(Debug, PartialEq)]
pub enum FilterType {
SystemClock = 0,
DirectInputWithSynchronization = 1,

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@ -18,13 +18,13 @@ pub use embedded_hal::blocking::i2c::{SevenBitAddress, TenBitAddress};
// Defintions
//==================================================================================================
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
#[derive(Debug, PartialEq, Copy, Clone)]
pub enum FifoEmptyMode {
Stall = 0,
EndTransaction = 1,
}
#[derive(Debug, PartialEq, Eq)]
#[derive(Debug, PartialEq)]
pub enum Error {
InvalidTimingParams,
ArbitrationLost,
@ -46,19 +46,19 @@ enum I2cCmd {
Cancel = 0b100,
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
#[derive(Debug, PartialEq, Copy, Clone)]
pub enum I2cSpeed {
Regular100khz = 0,
Fast400khz = 1,
}
#[derive(Debug, PartialEq, Eq)]
#[derive(Debug, PartialEq)]
pub enum I2cDirection {
Send = 0,
Read = 1,
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
#[derive(Debug, PartialEq, Copy, Clone)]
pub enum I2cAddress {
Regular(u8),
TenBit(u16),
@ -119,14 +119,14 @@ impl TimingCfg {
}
pub fn reg(&self) -> u32 {
(self.tbuf as u32) << 28
((self.tbuf as u32) << 28
| (self.thd_sta as u32) << 24
| (self.tsu_sta as u32) << 20
| (self.tsu_sto as u32) << 16
| (self.tlow as u32) << 12
| (self.thigh as u32) << 8
| (self.tf as u32) << 4
| (self.tr as u32)
| (self.tr as u32)) as u32
}
}

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@ -25,7 +25,7 @@ use embedded_hal::{
// Defintions
//==================================================================================================
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
#[derive(Debug, PartialEq, Copy, Clone)]
pub enum HwChipSelectId {
Id0 = 0,
Id1 = 1,
@ -38,7 +38,7 @@ pub enum HwChipSelectId {
Invalid = 0xff,
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
#[derive(Debug, PartialEq, Copy, Clone)]
pub enum WordSize {
OneBit = 0x00,
FourBits = 0x03,

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@ -6,7 +6,7 @@
//! allowing it to be converted into frequencies.
/// Bits per second
#[derive(Clone, Copy, PartialEq, Eq, PartialOrd, Debug)]
#[derive(Clone, Copy, PartialEq, PartialOrd, Debug)]
pub struct Bps(pub u32);
/// Hertz
@ -25,7 +25,7 @@ pub struct Bps(pub u32);
///
/// let freq = 60.hz();
/// ```
#[derive(Clone, Copy, PartialEq, Eq, PartialOrd, Debug)]
#[derive(Clone, Copy, PartialEq, PartialOrd, Debug)]
pub struct Hertz(pub u32);
/// Kilohertz
@ -47,7 +47,7 @@ pub struct Hertz(pub u32);
///
/// let freq = 100.khz();
/// ```
#[derive(Clone, Copy, PartialEq, Eq, PartialOrd, Debug)]
#[derive(Clone, Copy, PartialEq, PartialOrd, Debug)]
pub struct KiloHertz(pub u32);
/// Megahertz
@ -68,14 +68,14 @@ pub struct KiloHertz(pub u32);
///
/// let freq = 8.mhz();
/// ```
#[derive(Clone, Copy, PartialEq, Eq, PartialOrd, Debug)]
#[derive(Clone, Copy, PartialEq, PartialOrd, Debug)]
pub struct MegaHertz(pub u32);
/// Time unit
#[derive(PartialEq, Eq, PartialOrd, Clone, Copy)]
#[derive(PartialEq, PartialOrd, Clone, Copy)]
pub struct MilliSeconds(pub u32);
#[derive(PartialEq, Eq, PartialOrd, Clone, Copy)]
#[derive(PartialEq, PartialOrd, Clone, Copy)]
pub struct MicroSeconds(pub u32);
/// Extension trait that adds convenience methods to the `u32` type

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@ -21,7 +21,7 @@ use crate::{
private::Sealed,
time::Hertz,
timer,
utility::unmask_irq,
utility::{mask_irq, unmask_irq},
};
use core::cell::Cell;
use cortex_m::interrupt::Mutex;
@ -45,7 +45,7 @@ pub enum Event {
TimeOut,
}
#[derive(Default, Debug, PartialEq, Eq, Copy, Clone)]
#[derive(Default, Debug, PartialEq, Copy, Clone)]
pub struct CascadeCtrl {
/// Enable Cascade 0 signal active as a requirement for counting
pub enb_start_src_csd0: bool,
@ -74,7 +74,7 @@ pub struct CascadeCtrl {
pub trg_csd2: bool,
}
#[derive(Debug, PartialEq, Eq)]
#[derive(Debug, PartialEq)]
pub enum CascadeSel {
Csd0 = 0,
Csd1 = 1,
@ -82,7 +82,7 @@ pub enum CascadeSel {
}
/// The numbers are the base numbers for bundles like PORTA, PORTB or TIM
#[derive(Debug, PartialEq, Eq)]
#[derive(Debug, PartialEq)]
pub enum CascadeSource {
PortABase = 0,
PortBBase = 32,
@ -95,7 +95,7 @@ pub enum CascadeSource {
ClockDividerBase = 120,
}
#[derive(Debug, PartialEq, Eq)]
#[derive(Debug, PartialEq)]
pub enum TimerErrors {
Canceled,
/// Invalid input for Cascade source
@ -576,6 +576,12 @@ impl<TIM: ValidTim> CountDownTimer<TIM> {
#[inline(always)]
pub fn disable(&mut self) {
self.tim.reg().ctrl.modify(|_, w| w.enable().clear_bit());
if let Some(irq_cfg) = self.irq_cfg {
self.disable_interrupt();
if irq_cfg.enable {
mask_irq(irq_cfg.irq);
}
}
}
/// Disable the counter, setting both enable and active bit to 0
@ -742,9 +748,9 @@ pub fn set_up_ms_timer<TIM: ValidTim>(
sys_cfg: &mut pac::SYSCONFIG,
irq_sel: Option<&mut pac::IRQSEL>,
sys_clk: impl Into<Hertz>,
tim0: TIM,
tim: TIM,
) -> CountDownTimer<TIM> {
let mut ms_timer = CountDownTimer::new(sys_cfg, sys_clk, tim0);
let mut ms_timer = CountDownTimer::new(sys_cfg, sys_clk, tim);
ms_timer.listen(timer::Event::TimeOut, irq_cfg, irq_sel, Some(sys_cfg));
ms_timer.start(1000.hz());
ms_timer

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@ -60,7 +60,7 @@ pub enum Error {
IrqError,
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
#[derive(Debug, PartialEq, Copy, Clone)]
pub enum Event {
// Receiver FIFO interrupt enable. Generates interrupt
// when FIFO is at least half full. Half full is defined as FIFO
@ -84,20 +84,20 @@ pub enum Event {
TxCts,
}
#[derive(Copy, Clone, PartialEq, Eq)]
#[derive(Copy, Clone, PartialEq)]
pub enum Parity {
None,
Odd,
Even,
}
#[derive(Copy, Clone, PartialEq, Eq)]
#[derive(Copy, Clone, PartialEq)]
pub enum StopBits {
One = 0,
Two = 1,
}
#[derive(Copy, Clone, PartialEq, Eq)]
#[derive(Copy, Clone, PartialEq)]
pub enum WordSize {
Five = 0,
Six = 1,
@ -354,7 +354,7 @@ impl<UART: Instance> UartBase<UART> {
};
let x = sys_clk.0 as f32 / (config.baudrate.0 * baud_multiplier) as f32;
let integer_part = floorf(x) as u32;
let frac = floorf(64.0 * (x - integer_part as f32) + 0.5) as u32;
let frac = floorf((64.0 * (x - integer_part as f32) + 0.5) as f32) as u32;
self.uart
.clkscale
.write(|w| unsafe { w.bits(integer_part * 64 + frac) });

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@ -6,7 +6,7 @@
use crate::pac;
use va108xx::{IOCONFIG, SYSCONFIG};
#[derive(PartialEq, Eq, Debug)]
#[derive(PartialEq, Debug)]
pub enum UtilityError {
InvalidCounterResetVal,
InvalidPin,
@ -19,13 +19,13 @@ pub enum Funsel {
Funsel3 = 0b11,
}
#[derive(Debug, Copy, Clone, PartialEq, Eq)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub enum PortSel {
PortA,
PortB,
}
#[derive(Copy, Clone, PartialEq, Eq)]
#[derive(Copy, Clone, PartialEq)]
pub enum PeripheralSelect {
PortA = 0,
PortB = 1,
@ -46,7 +46,7 @@ pub enum PeripheralSelect {
/// use the IRQSEL register to route an interrupt, and whether the IRQ will be unmasked in the
/// Cortex-M0 NVIC. Both are generally necessary for IRQs to work, but the user might perform
/// this steps themselves
#[derive(Debug, PartialEq, Eq, Clone, Copy)]
#[derive(Debug, PartialEq, Clone, Copy)]
pub struct IrqCfg {
/// Interrupt target vector. Should always be set, might be required for disabling IRQs
pub irq: pac::Interrupt,
@ -142,3 +142,8 @@ pub fn port_mux(
pub(crate) fn unmask_irq(irq: pac::Interrupt) {
unsafe { cortex_m::peripheral::NVIC::unmask(irq) };
}
#[inline]
pub(crate) fn mask_irq(irq: pac::Interrupt) {
cortex_m::peripheral::NVIC::mask(irq);
}