EGit integration

- Changed license to Apache-2.0 only
- Added NOTICE file
- Added Jenkins CI/CD files

CHANGELOG.md

@@ -8,35 +8,6 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ## [unreleased]
 
-## [v0.4.2]
-
-### Added
-
-- `port_mux` function to set pin function select manually
-
-### Changed
-
-- Clear TX and RX FIFO in SPI transfer function
-
-## [v0.4.1]
-
-### Fixed
-
-- Initial blockmode setting was not set in SPI constructor
-
-## [v0.4.0]
-
-### Changed
-
-- Replaced `Hertz` by `impl Into<Hertz>` completely and removed
-  `+ Copy` where not necessary
-
-## [v0.3.1]
-
-- Updated all links to point to new repository
-
-## [v0.3.0]
-
 ### Added
 
 - TIM Cascade example
@@ -44,8 +15,6 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 ### Changed
 
 - `CountDownTimer` new function now expects an `impl Into<Hertz>` instead of `Hertz`
-- Primary repository now hosted on IRS external git: https://egit.irs.uni-stuttgart.de/rust/va108xx-hal
-- Relicensed as Apache-2.0
 
 ## [0.2.3]
 

Cargo.toml

@@ -1,7 +1,7 @@
 [package]
 name = "va108xx-hal"
-version = "0.4.2"
+version = "0.2.3"
-authors = ["Robin Mueller <muellerr@irs.uni-stuttgart.de>"]
+authors = ["Robin Mueller <robin.mueller.m@gmail.com>"]
 edition = "2021"
 description = "HAL for the Vorago VA108xx family of microcontrollers"
 homepage = "https://egit.irs.uni-stuttgart.de/rust/va108xx-hal"

README.md

@@ -59,7 +59,7 @@ your custom board.
 
 The hello world of embedded development is usually to blinky a LED. This example
 is contained within the
-[examples folder](https://egit.irs.uni-stuttgart.de/rust/va108xx-hal/src/branch/main/examples/blinky.rs).
+[examples folder](https://github.com/robamu-org/va108xx-hal-rs/tree/main/examples/blinky.rs).
 
 1. Set up your Rust cross-compiler if you have not done so yet. See more in the [build chapter](#Building)
 2. Create a new binary crate with `cargo init`
@@ -81,8 +81,12 @@ is contained within the
 	features = ["rt"]
    ```
 
-6. Build the application with `cargo build`
+6. Build the application with
+
+	```sh
+	cargo build
+	```
 
 7. Flashing the board might work differently for different boards and there is usually
    more than one way. You can find example instructions for the REB1 development board
-   [here](https://github.com/robamu-org/vorago-reb1-rs).
+   [here](https://github.com/robamu/vorago-reb1-rs).

examples/spi.rs

@@ -114,8 +114,12 @@ fn main() -> ! {
     match SPI_BUS_SEL {
         SpiBusSelect::SpiAPortA | SpiBusSelect::SpiAPortB => {
             if let Some(ref mut spi) = *spia_ref.borrow_mut() {
-                let transfer_cfg =
+                let transfer_cfg = TransferConfig::new_no_hw_cs(
-                    TransferConfig::new_no_hw_cs(SPI_SPEED_KHZ.khz(), SPI_MODE, BLOCKMODE, false);
+                    SPI_SPEED_KHZ.khz().into(),
+                    SPI_MODE,
+                    BLOCKMODE,
+                    false,
+                );
                 spi.cfg_transfer(&transfer_cfg);
             }
         }
@@ -123,7 +127,7 @@ fn main() -> ! {
             if let Some(ref mut spi) = *spib_ref.borrow_mut() {
                 let hw_cs_pin = pinsb.pb2.into_funsel_1();
                 let transfer_cfg = TransferConfig::new(
-                    SPI_SPEED_KHZ.khz(),
+                    SPI_SPEED_KHZ.khz().into(),
                     SPI_MODE,
                     Some(hw_cs_pin),
                     BLOCKMODE,

examples/uart.rs

@@ -25,7 +25,7 @@ fn main() -> ! {
         (tx, rx),
         115200.bps(),
         &mut dp.SYSCONFIG,
-        50.mhz(),
+        50.mhz().into(),
     );
     let (mut tx, mut rx) = uartb.split();
     writeln!(tx, "Hello World\r").unwrap();

src/gpio/dynpins.rs

@@ -57,17 +57,14 @@
 //! operation, the trait functions will return
 //! [`InvalidPinType`](PinError::InvalidPinType).
 
-use super::{
+use super::pins::{
-    pins::{
+    common_reg_if_functions, FilterType, InterruptEdge, InterruptLevel, Pin, PinError, PinId,
-        common_reg_if_functions, FilterType, InterruptEdge, InterruptLevel, Pin, PinError, PinId,
+    PinMode, PinState,
-        PinMode, PinState,
-    },
-    reg::RegisterInterface,
 };
+use super::reg::RegisterInterface;
 use crate::{
     clock::FilterClkSel,
     pac::{self, IRQSEL, SYSCONFIG},
-    utility::Funsel,
 };
 use embedded_hal::digital::v2::{InputPin, OutputPin, ToggleableOutputPin};
 use paste::paste;
@@ -101,7 +98,13 @@ pub enum DynOutput {
     ReadableOpenDrain,
 }
 
-pub type DynAlternate = Funsel;
+/// Value-level `enum` for alternate peripheral function configurations
+#[derive(PartialEq, Eq, Clone, Copy)]
+pub enum DynAlternate {
+    Funsel1,
+    Funsel2,
+    Funsel3,
+}
 
 //==================================================================================================
 //  DynPinMode

src/gpio/mod.rs

@@ -20,7 +20,7 @@
 //!
 //! ## Examples
 //!
-//! - [Blinky example](https://egit.irs.uni-stuttgart.de/rust/va108xx-hal/src/branch/main/examples/blinky.rs)
+//! - [Blinky example](https://github.com/robamu-org/va108xx-hal-rs/blob/main/examples/blinky.rs)
 pub mod dynpins;
 pub use dynpins::*;
 

src/gpio/reg.rs

@@ -60,7 +60,18 @@ impl From<DynPinMode> for ModeFields {
                 }
             }
             Alternate(config) => {
-                fields.funsel = config as u8;
+                use dynpins::DynAlternate::*;
+                match config {
+                    Funsel1 => {
+                        fields.funsel = 1;
+                    }
+                    Funsel2 => {
+                        fields.funsel = 2;
+                    }
+                    Funsel3 => {
+                        fields.funsel = 3;
+                    }
+                }
             }
         }
         fields

src/i2c.rs

@@ -231,7 +231,7 @@ macro_rules! i2c_base {
             impl I2cBase<$I2CX> {
                 pub fn $i2cx(
                     i2c: $I2CX,
-                    sys_clk: impl Into<Hertz>,
+                    sys_clk: impl Into<Hertz> + Copy,
                     speed_mode: I2cSpeed,
                     ms_cfg: Option<&MasterConfig>,
                     sl_cfg: Option<&SlaveConfig>,
@@ -740,7 +740,7 @@ macro_rules! i2c_slave {
                 fn $i2cx_slave(
                     i2c: $I2CX,
                     cfg: SlaveConfig,
-                    sys_clk: impl Into<Hertz>,
+                    sys_clk: impl Into<Hertz> + Copy,
                     speed_mode: I2cSpeed,
                     sys_cfg: Option<&mut SYSCONFIG>,
                 ) -> Self {
@@ -897,7 +897,7 @@ macro_rules! i2c_slave {
                 pub fn i2ca(
                     i2c: $I2CX,
                     cfg: SlaveConfig,
-                    sys_clk: impl Into<Hertz>,
+                    sys_clk: impl Into<Hertz> + Copy,
                     speed_mode: I2cSpeed,
                     sys_cfg: Option<&mut SYSCONFIG>,
                 ) -> Result<Self, Error> {
@@ -912,7 +912,7 @@ macro_rules! i2c_slave {
                 pub fn $i2cx(
                     i2c: $I2CX,
                     cfg: SlaveConfig,
-                    sys_clk: impl Into<Hertz>,
+                    sys_clk: impl Into<Hertz> + Copy,
                     speed_mode: I2cSpeed,
                     sys_cfg: Option<&mut SYSCONFIG>,
                 ) -> Self {

src/pwm.rs

@@ -4,7 +4,7 @@
 //!
 //! ## Examples
 //!
-//! - [PWM example](https://egit.irs.uni-stuttgart.de/rust/va108xx-hal/src/branch/main/examples/pwm.rs)
+//! - [PWM example](https://github.com/robamu-org/va108xx-hal-rs/blob/main/examples/pwm.rs)
 use core::marker::PhantomData;
 
 use crate::{clock::enable_peripheral_clock, gpio::DynPinId};

src/spi.rs

@@ -2,7 +2,7 @@
 //!
 //! ## Examples
 //!
-//! - [Blocking SPI example](https://egit.irs.uni-stuttgart.de/rust/va108xx-hal/src/branch/main/examples/spi.rs)
+//! - [Blocking SPI example](https://github.com/robamu-org/va108xx-hal-rs/blob/main/examples/spi.rs)
 use crate::Sealed;
 use crate::{
     clock::{enable_peripheral_clock, PeripheralClocks},
@@ -218,9 +218,9 @@ pub struct ReducedTransferConfig {
 }
 
 impl TransferConfig<NoneT> {
-    pub fn new_no_hw_cs(spi_clk: impl Into<Hertz>, mode: Mode, blockmode: bool, sod: bool) -> Self {
+    pub fn new_no_hw_cs(spi_clk: Hertz, mode: Mode, blockmode: bool, sod: bool) -> Self {
         TransferConfig {
-            spi_clk: spi_clk.into(),
+            spi_clk,
             mode,
             hw_cs: None,
             sod,
@@ -231,14 +231,14 @@ impl TransferConfig<NoneT> {
 
 impl<HWCS: HwCs> TransferConfig<HWCS> {
     pub fn new(
-        spi_clk: impl Into<Hertz>,
+        spi_clk: Hertz,
         mode: Mode,
         hw_cs: Option<HWCS>,
         blockmode: bool,
         sod: bool,
     ) -> Self {
         TransferConfig {
-            spi_clk: spi_clk.into(),
+            spi_clk,
             mode,
             hw_cs,
             sod,
@@ -428,7 +428,6 @@ macro_rules! spi {
                         w.sod().bit(sod);
                         w.ms().bit(ms);
                         w.mdlycap().bit(mdlycap);
-                        w.blockmode().bit(init_blockmode);
                         unsafe { w.ss().bits(ss) }
                     });
 
@@ -453,7 +452,7 @@ macro_rules! spi {
                 }
 
                 #[inline]
-                pub fn cfg_clock(&mut self, spi_clk: impl Into<Hertz>) {
+                pub fn cfg_clock(&mut self, spi_clk: Hertz) {
                     self.spi_base.cfg_clock(spi_clk);
                 }
 
@@ -483,8 +482,8 @@ macro_rules! spi {
 
             impl<WORD: Word> SpiBase<$SPIX, WORD> {
                 #[inline]
-                pub fn cfg_clock(&mut self, spi_clk: impl Into<Hertz>) {
+                pub fn cfg_clock(&mut self, spi_clk: Hertz) {
-                    let clk_prescale = self.sys_clk.0 / (spi_clk.into().0 * (self.cfg.scrdv as u32 + 1));
+                    let clk_prescale = self.sys_clk.0 / (spi_clk.0 * (self.cfg.scrdv as u32 + 1));
                     self.spi
                         .clkprescale
                         .write(|w| unsafe { w.bits(clk_prescale) });
@@ -504,16 +503,6 @@ macro_rules! spi {
                     });
                 }
 
-                #[inline]
-                pub fn clear_tx_fifo(&self) {
-                    self.spi.fifo_clr.write(|w| w.txfifo().set_bit());
-                }
-
-                #[inline]
-                pub fn clear_rx_fifo(&self) {
-                    self.spi.fifo_clr.write(|w| w.rxfifo().set_bit());
-                }
-
                 #[inline]
                 pub fn perid(&self) -> u32 {
                     self.spi.perid.read().bits()
@@ -650,9 +639,6 @@ macro_rules! spi {
                         // FIFO has a depth of 16.
                         const FILL_DEPTH: usize = 12;
 
-                        self.clear_tx_fifo();
-                        self.clear_rx_fifo();
-
                         if self.blockmode {
                             self.spi.ctrl1.modify(|_, w| {
                                 w.mtxpause().set_bit()

src/timer.rs

@@ -2,8 +2,7 @@
 //!
 //! ## Examples
 //!
-//! - [MS and second tick implementation](https://egit.irs.uni-stuttgart.de/rust/va108xx-hal/src/branch/main/examples/timer-ticks.rs)
+//! - [MS and second tick implementation](https://github.com/robamu-org/va108xx-hal-rs/blob/main/examples/timer-ticks.rs)
-//! - [Cascade feature example](https://egit.irs.uni-stuttgart.de/rust/va108xx-hal/src/branch/main/examples/cascade.rs)
 use crate::{
     clock::{enable_peripheral_clock, PeripheralClocks},
     gpio::{

src/uart.rs

@@ -2,7 +2,7 @@
 //!
 //! ## Examples
 //!
-//! - [UART example](https://egit.irs.uni-stuttgart.de/rust/va108xx-hal/src/branch/main/examples/uart.rs)
+//! - [UART example](https://github.com/robamu-org/va108xx-hal-rs/blob/main/examples/uart.rs)
 use core::{convert::Infallible, ptr};
 use core::{marker::PhantomData, ops::Deref};
 use libm::floorf;
@@ -306,12 +306,12 @@ macro_rules! uart_impl {
                     pins: PINS,
                     config: impl Into<Config>,
                     syscfg: &mut SYSCONFIG,
-                    sys_clk: impl Into<Hertz>
+                    sys_clk: Hertz
                 ) -> Self
                 {
                     enable_peripheral_clock(syscfg, $clk_enb_enum);
                     Uart { uart, pins, tx: Tx::new(), rx: Rx::new() }.init(
-                        config.into(), sys_clk.into()
+                        config.into(), sys_clk
                     )
                 }
             }

src/utility.rs

@@ -3,25 +3,11 @@
 //! Some more information about the recommended scrub rates can be found on the
 //! [Vorago White Paper website](https://www.voragotech.com/resources) in the
 //! application note AN1212
-use va108xx::{IOCONFIG, SYSCONFIG};
+use va108xx::SYSCONFIG;
 
 #[derive(PartialEq, Debug)]
 pub enum UtilityError {
     InvalidCounterResetVal,
-    InvalidPin,
-}
-
-#[derive(Debug, Eq, Copy, Clone, PartialEq)]
-pub enum Funsel {
-    Funsel1 = 0b01,
-    Funsel2 = 0b10,
-    Funsel3 = 0b11,
-}
-
-#[derive(Debug, Copy, Clone, PartialEq)]
-pub enum PortSel {
-    PortA,
-    PortB,
 }
 
 #[derive(Copy, Clone, PartialEq)]
@@ -86,28 +72,3 @@ pub fn set_reset_bit(syscfg: &mut SYSCONFIG, periph_sel: PeripheralSelect) {
         .peripheral_reset
         .modify(|r, w| unsafe { w.bits(r.bits() | (1 << periph_sel as u8)) });
 }
-
-/// Can be used to manually manipulate the function select of port pins
-pub fn port_mux(
-    ioconfig: &mut IOCONFIG,
-    port: PortSel,
-    pin: u8,
-    funsel: Funsel,
-) -> Result<(), UtilityError> {
-    match port {
-        PortSel::PortA => {
-            if pin > 31 {
-                return Err(UtilityError::InvalidPin);
-            }
-            ioconfig.porta[pin as usize].modify(|_, w| unsafe { w.funsel().bits(funsel as u8) });
-            Ok(())
-        }
-        PortSel::PortB => {
-            if pin > 23 {
-                return Err(UtilityError::InvalidPin);
-            }
-            ioconfig.portb[pin as usize].modify(|_, w| unsafe { w.funsel().bits(funsel as u8) });
-            Ok(())
-        }
-    }
-}