927 lines
35 KiB
Rust
927 lines
35 KiB
Rust
//! API for the I2C peripheral
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//!
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//! ## Examples
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//!
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//! - [REB1 I2C temperature sensor example](https://egit.irs.uni-stuttgart.de/rust/vorago-reb1/src/branch/main/examples/adt75-temp-sensor.rs)
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use crate::{
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clock::{enable_peripheral_clock, PeripheralClocks},
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pac::{I2CA, I2CB, SYSCONFIG},
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time::Hertz,
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Sealed,
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};
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use core::marker::PhantomData;
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use embedded_hal::blocking::i2c::{Read, Write, WriteIter, WriteIterRead, WriteRead};
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pub use embedded_hal::blocking::i2c::{SevenBitAddress, TenBitAddress};
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//==================================================================================================
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// Defintions
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//==================================================================================================
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#[derive(Debug, PartialEq, Eq, Copy, Clone)]
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pub enum FifoEmptyMode {
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Stall = 0,
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EndTransaction = 1,
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}
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#[derive(Debug, PartialEq, Eq)]
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pub enum Error {
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InvalidTimingParams,
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ArbitrationLost,
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NackAddr,
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/// Data not acknowledged in write operation
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NackData,
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/// Not enough data received in read operation
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InsufficientDataReceived,
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/// Number of bytes in transfer too large (larger than 0x7fe)
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DataTooLarge,
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WrongAddrMode,
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}
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#[derive(Debug, PartialEq, Copy, Clone)]
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enum I2cCmd {
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Start = 0b00,
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Stop = 0b10,
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StartWithStop = 0b11,
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Cancel = 0b100,
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}
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#[derive(Debug, PartialEq, Eq, Copy, Clone)]
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pub enum I2cSpeed {
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Regular100khz = 0,
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Fast400khz = 1,
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}
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#[derive(Debug, PartialEq, Eq)]
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pub enum I2cDirection {
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Send = 0,
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Read = 1,
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}
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#[derive(Debug, PartialEq, Eq, Copy, Clone)]
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pub enum I2cAddress {
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Regular(u8),
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TenBit(u16),
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}
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//==================================================================================================
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// Config
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//==================================================================================================
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pub struct TrTfThighTlow(u8, u8, u8, u8);
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pub struct TsuStoTsuStaThdStaTBuf(u8, u8, u8, u8);
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pub struct TimingCfg {
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// 4 bit max width
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tr: u8,
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// 4 bit max width
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tf: u8,
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// 4 bit max width
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thigh: u8,
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// 4 bit max width
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tlow: u8,
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// 4 bit max width
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tsu_sto: u8,
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// 4 bit max width
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tsu_sta: u8,
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// 4 bit max width
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thd_sta: u8,
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// 4 bit max width
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tbuf: u8,
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}
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impl TimingCfg {
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pub fn new(
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first_16_bits: TrTfThighTlow,
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second_16_bits: TsuStoTsuStaThdStaTBuf,
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) -> Result<Self, Error> {
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if first_16_bits.0 > 0xf
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|| first_16_bits.1 > 0xf
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|| first_16_bits.2 > 0xf
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|| first_16_bits.3 > 0xf
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|| second_16_bits.0 > 0xf
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|| second_16_bits.1 > 0xf
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|| second_16_bits.2 > 0xf
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|| second_16_bits.3 > 0xf
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{
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return Err(Error::InvalidTimingParams);
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}
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Ok(TimingCfg {
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tr: first_16_bits.0,
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tf: first_16_bits.1,
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thigh: first_16_bits.2,
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tlow: first_16_bits.3,
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tsu_sto: second_16_bits.0,
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tsu_sta: second_16_bits.1,
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thd_sta: second_16_bits.2,
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tbuf: second_16_bits.3,
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})
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}
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pub fn reg(&self) -> u32 {
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(self.tbuf as u32) << 28
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| (self.thd_sta as u32) << 24
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| (self.tsu_sta as u32) << 20
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| (self.tsu_sto as u32) << 16
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| (self.tlow as u32) << 12
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| (self.thigh as u32) << 8
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| (self.tf as u32) << 4
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| (self.tr as u32)
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}
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}
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impl Default for TimingCfg {
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fn default() -> Self {
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TimingCfg {
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tr: 0x02,
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tf: 0x01,
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thigh: 0x08,
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tlow: 0x09,
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tsu_sto: 0x8,
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tsu_sta: 0x0a,
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thd_sta: 0x8,
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tbuf: 0xa,
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}
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}
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}
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pub struct MasterConfig {
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pub tx_fe_mode: FifoEmptyMode,
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pub rx_fe_mode: FifoEmptyMode,
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/// Enable the analog delay glitch filter
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pub alg_filt: bool,
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/// Enable the digital glitch filter
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pub dlg_filt: bool,
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pub tm_cfg: Option<TimingCfg>,
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// Loopback mode
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// lbm: bool,
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}
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impl Default for MasterConfig {
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fn default() -> Self {
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MasterConfig {
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tx_fe_mode: FifoEmptyMode::Stall,
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rx_fe_mode: FifoEmptyMode::Stall,
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alg_filt: false,
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dlg_filt: false,
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tm_cfg: None,
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}
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}
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}
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impl Sealed for MasterConfig {}
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pub struct SlaveConfig {
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pub tx_fe_mode: FifoEmptyMode,
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pub rx_fe_mode: FifoEmptyMode,
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/// Maximum number of words before issuing a negative acknowledge.
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/// Range should be 0 to 0x7fe. Setting the value to 0x7ff has the same effect as not setting
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/// the enable bit since RXCOUNT stops counting at 0x7fe.
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pub max_words: Option<usize>,
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/// A received address is compared to the ADDRESS register (addr) using the address mask
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/// (addr_mask). Those bits with a 1 in the address mask must match for there to be an address
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/// match
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pub addr: I2cAddress,
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/// The default address mask will be 0x3ff to only allow full matches
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pub addr_mask: Option<u16>,
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/// Optionally specify a second I2C address the slave interface responds to
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pub addr_b: Option<I2cAddress>,
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pub addr_b_mask: Option<u16>,
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}
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impl SlaveConfig {
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/// Build a default slave config given a specified slave address to respond to
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pub fn new(addr: I2cAddress) -> Self {
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SlaveConfig {
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tx_fe_mode: FifoEmptyMode::Stall,
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rx_fe_mode: FifoEmptyMode::Stall,
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max_words: None,
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addr,
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addr_mask: None,
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addr_b: None,
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addr_b_mask: None,
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}
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}
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}
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impl Sealed for SlaveConfig {}
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//==================================================================================================
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// I2C Base
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//==================================================================================================
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pub struct I2cBase<I2C> {
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i2c: I2C,
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sys_clk: Hertz,
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}
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impl<I2C> I2cBase<I2C> {
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#[inline]
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fn unwrap_addr(addr: I2cAddress) -> (u16, u32) {
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match addr {
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I2cAddress::Regular(addr) => (addr as u16, 0 << 15),
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I2cAddress::TenBit(addr) => (addr, 1 << 15),
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}
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}
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}
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macro_rules! i2c_base {
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($($I2CX:ident: ($i2cx:ident, $clk_enb:path),)+) => {
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$(
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impl I2cBase<$I2CX> {
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pub fn $i2cx(
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i2c: $I2CX,
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sys_clk: impl Into<Hertz>,
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speed_mode: I2cSpeed,
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ms_cfg: Option<&MasterConfig>,
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sl_cfg: Option<&SlaveConfig>,
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sys_cfg: Option<&mut SYSCONFIG>,
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) -> Self {
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if let Some(sys_cfg) = sys_cfg {
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enable_peripheral_clock(sys_cfg, $clk_enb);
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}
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let mut i2c_base = I2cBase {
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i2c,
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sys_clk: sys_clk.into(),
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};
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if let Some(ms_cfg) = ms_cfg {
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i2c_base.cfg_master(ms_cfg);
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}
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if let Some(sl_cfg) = sl_cfg {
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i2c_base.cfg_slave(sl_cfg);
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}
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i2c_base.cfg_clk_scale(speed_mode);
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i2c_base
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}
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fn cfg_master(&mut self, ms_cfg: &MasterConfig) {
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let (txfemd, rxfemd) = match (ms_cfg.tx_fe_mode, ms_cfg.rx_fe_mode) {
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(FifoEmptyMode::Stall, FifoEmptyMode::Stall) => (false, false),
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(FifoEmptyMode::Stall, FifoEmptyMode::EndTransaction) => (false, true),
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(FifoEmptyMode::EndTransaction, FifoEmptyMode::Stall) => (true, false),
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(FifoEmptyMode::EndTransaction, FifoEmptyMode::EndTransaction) => (true, true),
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};
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self.i2c.ctrl.modify(|_, w| {
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w.txfemd().bit(txfemd);
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w.rxffmd().bit(rxfemd);
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w.dlgfilter().bit(ms_cfg.dlg_filt);
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w.algfilter().bit(ms_cfg.alg_filt)
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});
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if let Some(ref tm_cfg) = ms_cfg.tm_cfg {
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self.i2c.tmconfig.write(|w| unsafe { w.bits(tm_cfg.reg()) });
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}
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self.i2c.fifo_clr.write(|w| {
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w.rxfifo().set_bit();
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w.txfifo().set_bit()
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});
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}
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fn cfg_slave(&mut self, sl_cfg: &SlaveConfig) {
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let (txfemd, rxfemd) = match (sl_cfg.tx_fe_mode, sl_cfg.rx_fe_mode) {
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(FifoEmptyMode::Stall, FifoEmptyMode::Stall) => (false, false),
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(FifoEmptyMode::Stall, FifoEmptyMode::EndTransaction) => (false, true),
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(FifoEmptyMode::EndTransaction, FifoEmptyMode::Stall) => (true, false),
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(FifoEmptyMode::EndTransaction, FifoEmptyMode::EndTransaction) => (true, true),
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};
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self.i2c.s0_ctrl.modify(|_, w| {
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w.txfemd().bit(txfemd);
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w.rxffmd().bit(rxfemd)
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});
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self.i2c.s0_fifo_clr.write(|w| {
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w.rxfifo().set_bit();
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w.txfifo().set_bit()
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});
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let max_words = sl_cfg.max_words;
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if let Some(max_words) = max_words {
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self.i2c
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.s0_maxwords
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.write(|w| unsafe { w.bits(1 << 31 | max_words as u32) });
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}
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let (addr, addr_mode_mask) = Self::unwrap_addr(sl_cfg.addr);
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// The first bit is the read/write value. Normally, both read and write are matched
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// using the RWMASK bit of the address mask register
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self.i2c
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.s0_address
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.write(|w| unsafe { w.bits((addr << 1) as u32 | addr_mode_mask) });
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if let Some(addr_mask) = sl_cfg.addr_mask {
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self.i2c
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.s0_addressmask
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.write(|w| unsafe { w.bits((addr_mask << 1) as u32) });
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}
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if let Some(addr_b) = sl_cfg.addr_b {
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let (addr, addr_mode_mask) = Self::unwrap_addr(addr_b);
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self.i2c
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.s0_addressb
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.write(|w| unsafe { w.bits((addr << 1) as u32 | addr_mode_mask) })
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}
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if let Some(addr_b_mask) = sl_cfg.addr_b_mask {
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self.i2c
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.s0_addressmaskb
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.write(|w| unsafe { w.bits((addr_b_mask << 1) as u32) })
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}
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}
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#[inline]
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pub fn filters(&mut self, digital_filt: bool, analog_filt: bool) {
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self.i2c.ctrl.modify(|_, w| {
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w.dlgfilter().bit(digital_filt);
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w.algfilter().bit(analog_filt)
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});
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}
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#[inline]
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pub fn fifo_empty_mode(&mut self, rx: FifoEmptyMode, tx: FifoEmptyMode) {
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self.i2c.ctrl.modify(|_, w| {
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w.txfemd().bit(tx as u8 != 0);
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w.rxffmd().bit(rx as u8 != 0)
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});
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}
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fn calc_clk_div(&self, speed_mode: I2cSpeed) -> u8 {
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if speed_mode == I2cSpeed::Regular100khz {
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((self.sys_clk.0 / (u32::pow(10, 5) * 20)) - 1) as u8
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} else {
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(((10 * self.sys_clk.0) / u32::pow(10, 8)) - 1) as u8
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}
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}
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/// Configures the clock scale for a given speed mode setting
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pub fn cfg_clk_scale(&mut self, speed_mode: I2cSpeed) {
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self.i2c.clkscale.write(|w| unsafe {
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w.bits((speed_mode as u32) << 31 | self.calc_clk_div(speed_mode) as u32)
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});
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}
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pub fn load_address(&mut self, addr: u16) {
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// Load address
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self.i2c
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.address
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.write(|w| unsafe { w.bits((addr << 1) as u32) });
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}
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#[inline]
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fn stop_cmd(&mut self) {
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self.i2c
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.cmd
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.write(|w| unsafe { w.bits(I2cCmd::Stop as u32) });
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}
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}
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)+
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}
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}
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// Unique mode to use the loopback functionality
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// pub struct I2cLoopback<I2C> {
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// i2c_base: I2cBase<I2C>,
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// master_cfg: MasterConfig,
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// slave_cfg: SlaveConfig,
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// }
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i2c_base!(
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I2CA: (i2ca, PeripheralClocks::I2c0),
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I2CB: (i2cb, PeripheralClocks::I2c1),
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);
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//==================================================================================================
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// I2C Master
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//==================================================================================================
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pub struct I2cMaster<I2C, ADDR = SevenBitAddress> {
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i2c_base: I2cBase<I2C>,
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_addr: PhantomData<ADDR>,
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}
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macro_rules! i2c_master {
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($($I2CX:ident: ($i2cx:ident, $clk_enb:path),)+) => {
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$(
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impl<ADDR> I2cMaster<$I2CX, ADDR> {
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pub fn $i2cx(
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i2c: $I2CX,
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cfg: MasterConfig,
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sys_clk: impl Into<Hertz> + Copy,
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speed_mode: I2cSpeed,
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sys_cfg: Option<&mut SYSCONFIG>,
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) -> Self {
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I2cMaster {
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i2c_base: I2cBase::$i2cx(
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i2c,
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sys_clk,
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speed_mode,
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Some(&cfg),
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None,
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sys_cfg
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),
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_addr: PhantomData,
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}
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.enable_master()
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}
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#[inline]
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pub fn cancel_transfer(&self) {
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self.i2c_base
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.i2c
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.cmd
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.write(|w| unsafe { w.bits(I2cCmd::Cancel as u32) });
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}
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#[inline]
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pub fn clear_tx_fifo(&self) {
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self.i2c_base.i2c.fifo_clr.write(|w| w.txfifo().set_bit());
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}
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#[inline]
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pub fn clear_rx_fifo(&self) {
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self.i2c_base.i2c.fifo_clr.write(|w| w.rxfifo().set_bit());
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}
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#[inline]
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pub fn enable_master(self) -> Self {
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self.i2c_base.i2c.ctrl.modify(|_, w| w.enable().set_bit());
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self
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}
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#[inline]
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pub fn disable_master(self) -> Self {
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self.i2c_base.i2c.ctrl.modify(|_, w| w.enable().clear_bit());
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self
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}
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#[inline(always)]
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fn load_fifo(&self, word: u8) {
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self.i2c_base
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.i2c
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.data
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.write(|w| unsafe { w.bits(word as u32) });
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}
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|
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#[inline(always)]
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fn read_fifo(&self) -> u8 {
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self.i2c_base.i2c.data.read().bits() as u8
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}
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fn error_handler_write(&mut self, init_cmd: &I2cCmd) {
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self.clear_tx_fifo();
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if *init_cmd == I2cCmd::Start {
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self.i2c_base.stop_cmd()
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}
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}
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|
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fn write_base(
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&mut self,
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addr: I2cAddress,
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init_cmd: I2cCmd,
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bytes: impl IntoIterator<Item = u8>,
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) -> Result<(), Error> {
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let mut iter = bytes.into_iter();
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// Load address
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let (addr, addr_mode_bit) = I2cBase::<$I2CX>::unwrap_addr(addr);
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self.i2c_base.i2c.address.write(|w| unsafe {
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w.bits(I2cDirection::Send as u32 | (addr << 1) as u32 | addr_mode_bit)
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});
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self.i2c_base
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.i2c
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.cmd
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.write(|w| unsafe { w.bits(init_cmd as u32) });
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let mut load_if_next_available = || {
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if let Some(next_byte) = iter.next() {
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self.load_fifo(next_byte);
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}
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};
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loop {
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let status_reader = self.i2c_base.i2c.status.read();
|
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if status_reader.arblost().bit_is_set() {
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self.error_handler_write(&init_cmd);
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return Err(Error::ArbitrationLost);
|
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} else if status_reader.nackaddr().bit_is_set() {
|
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self.error_handler_write(&init_cmd);
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return Err(Error::NackAddr);
|
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} else if status_reader.nackdata().bit_is_set() {
|
|
self.error_handler_write(&init_cmd);
|
|
return Err(Error::NackData);
|
|
} else if status_reader.idle().bit_is_set() {
|
|
return Ok(());
|
|
} else {
|
|
while !status_reader.txnfull().bit_is_set() {
|
|
load_if_next_available();
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
fn write_from_buffer(
|
|
&mut self,
|
|
init_cmd: I2cCmd,
|
|
addr: I2cAddress,
|
|
output: &[u8],
|
|
) -> Result<(), Error> {
|
|
let len = output.len();
|
|
// It should theoretically possible to transfer larger data sizes by tracking
|
|
// the number of sent words and setting it to 0x7fe as soon as only that many
|
|
// bytes are remaining. However, large transfer like this are not common. This
|
|
// feature will therefore not be supported for now.
|
|
if len > 0x7fe {
|
|
return Err(Error::DataTooLarge);
|
|
}
|
|
// Load number of words
|
|
self.i2c_base
|
|
.i2c
|
|
.words
|
|
.write(|w| unsafe { w.bits(len as u32) });
|
|
let mut bytes = output.iter();
|
|
// FIFO has a depth of 16. We load slightly above the trigger level
|
|
// but not all of it because the transaction might fail immediately
|
|
const FILL_DEPTH: usize = 12;
|
|
|
|
// load the FIFO
|
|
for _ in 0..core::cmp::min(FILL_DEPTH, len) {
|
|
self.load_fifo(*bytes.next().unwrap());
|
|
}
|
|
|
|
self.write_base(addr, init_cmd, output.iter().cloned())
|
|
}
|
|
|
|
fn load_from_iter(
|
|
&self, bytes: impl IntoIterator<Item = u8>
|
|
) -> impl IntoIterator<Item = u8> {
|
|
let mut iter = bytes.into_iter();
|
|
// FIFO has a depth of 16. We load slightly above the trigger level
|
|
// but not all of it because the transaction might fail immediately
|
|
const FILL_DEPTH: usize = 12;
|
|
|
|
// load the FIFO
|
|
for _ in 0..FILL_DEPTH {
|
|
if let Some(next_byte) = iter.next() {
|
|
self.load_fifo(next_byte);
|
|
} else {
|
|
break;
|
|
}
|
|
}
|
|
iter
|
|
}
|
|
|
|
fn read_internal(&mut self, addr: I2cAddress, buffer: &mut [u8]) -> Result<(), Error> {
|
|
let len = buffer.len();
|
|
// It should theoretically possible to transfer larger data sizes by tracking
|
|
// the number of sent words and setting it to 0x7fe as soon as only that many
|
|
// bytes are remaining. However, large transfer like this are not common. This
|
|
// feature will therefore not be supported for now.
|
|
if len > 0x7fe {
|
|
return Err(Error::DataTooLarge);
|
|
}
|
|
// Clear the receive FIFO
|
|
self.clear_rx_fifo();
|
|
|
|
// Load number of words
|
|
self.i2c_base
|
|
.i2c
|
|
.words
|
|
.write(|w| unsafe { w.bits(len as u32) });
|
|
let (addr, addr_mode_bit) = match addr {
|
|
I2cAddress::Regular(addr) => (addr as u16, 0 << 15),
|
|
I2cAddress::TenBit(addr) => (addr, 1 << 15),
|
|
};
|
|
// Load address
|
|
self.i2c_base.i2c.address.write(|w| unsafe {
|
|
w.bits(I2cDirection::Read as u32 | (addr << 1) as u32 | addr_mode_bit)
|
|
});
|
|
|
|
let mut buf_iter = buffer.iter_mut();
|
|
let mut read_bytes = 0;
|
|
// Start receive transfer
|
|
self.i2c_base
|
|
.i2c
|
|
.cmd
|
|
.write(|w| unsafe { w.bits(I2cCmd::StartWithStop as u32) });
|
|
let mut read_if_next_available = || {
|
|
if let Some(next_byte) = buf_iter.next() {
|
|
*next_byte = self.read_fifo();
|
|
}
|
|
};
|
|
loop {
|
|
let status_reader = self.i2c_base.i2c.status.read();
|
|
if status_reader.arblost().bit_is_set() {
|
|
self.clear_rx_fifo();
|
|
return Err(Error::ArbitrationLost);
|
|
} else if status_reader.nackaddr().bit_is_set() {
|
|
self.clear_rx_fifo();
|
|
return Err(Error::NackAddr);
|
|
} else if status_reader.idle().bit_is_set() {
|
|
if read_bytes != len {
|
|
return Err(Error::InsufficientDataReceived);
|
|
}
|
|
return Ok(());
|
|
} else if status_reader.rxnempty().bit_is_set() {
|
|
read_if_next_available();
|
|
read_bytes += 1;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
//======================================================================================
|
|
// Embedded HAL I2C implementations
|
|
//======================================================================================
|
|
|
|
impl Write<SevenBitAddress> for I2cMaster<$I2CX, SevenBitAddress> {
|
|
type Error = Error;
|
|
|
|
fn write(&mut self, addr: u8, output: &[u8]) -> Result<(), Self::Error> {
|
|
self.write_from_buffer(I2cCmd::StartWithStop, I2cAddress::Regular(addr), output)
|
|
}
|
|
}
|
|
|
|
impl Write<TenBitAddress> for I2cMaster<$I2CX, TenBitAddress> {
|
|
type Error = Error;
|
|
|
|
fn write(&mut self, addr: u16, output: &[u8]) -> Result<(), Self::Error> {
|
|
self.write_from_buffer(I2cCmd::StartWithStop, I2cAddress::TenBit(addr), output)
|
|
}
|
|
}
|
|
|
|
impl Read<SevenBitAddress> for I2cMaster<$I2CX, SevenBitAddress> {
|
|
type Error = Error;
|
|
|
|
fn read(&mut self, address: u8, buffer: &mut [u8]) -> Result<(), Self::Error> {
|
|
self.read_internal(I2cAddress::Regular(address), buffer)
|
|
}
|
|
}
|
|
|
|
impl Read<TenBitAddress> for I2cMaster<$I2CX, TenBitAddress> {
|
|
type Error = Error;
|
|
|
|
fn read(&mut self, address: u16, buffer: &mut [u8]) -> Result<(), Self::Error> {
|
|
self.read_internal(I2cAddress::TenBit(address), buffer)
|
|
}
|
|
}
|
|
|
|
impl WriteRead<SevenBitAddress> for I2cMaster<$I2CX, SevenBitAddress> {
|
|
type Error = Error;
|
|
|
|
fn write_read(
|
|
&mut self,
|
|
address: u8,
|
|
bytes: &[u8],
|
|
buffer: &mut [u8],
|
|
) -> Result<(), Self::Error> {
|
|
let addr = I2cAddress::Regular(address);
|
|
self.write_from_buffer(I2cCmd::Start, addr, bytes)?;
|
|
self.read_internal(addr, buffer)
|
|
}
|
|
}
|
|
|
|
impl WriteRead<TenBitAddress> for I2cMaster<$I2CX, TenBitAddress> {
|
|
type Error = Error;
|
|
|
|
fn write_read(
|
|
&mut self,
|
|
address: u16,
|
|
bytes: &[u8],
|
|
buffer: &mut [u8],
|
|
) -> Result<(), Self::Error> {
|
|
let addr = I2cAddress::TenBit(address);
|
|
self.write_from_buffer(I2cCmd::Start, addr, bytes)?;
|
|
self.read_internal(addr, buffer)
|
|
}
|
|
}
|
|
|
|
impl WriteIter<SevenBitAddress> for I2cMaster<$I2CX, SevenBitAddress> {
|
|
type Error = Error;
|
|
|
|
fn write<B>(&mut self, address: u8, bytes: B) -> Result<(), Self::Error>
|
|
where
|
|
B: IntoIterator<Item = u8>,
|
|
{
|
|
let iter = self.load_from_iter(bytes);
|
|
self.write_base(I2cAddress::Regular(address), I2cCmd::Start, iter)
|
|
}
|
|
}
|
|
|
|
impl WriteIterRead<SevenBitAddress> for I2cMaster<$I2CX, SevenBitAddress> {
|
|
type Error = Error;
|
|
fn write_iter_read<B>(
|
|
&mut self,
|
|
address: u8,
|
|
bytes: B,
|
|
buffer: &mut [u8],
|
|
) -> Result<(), Self::Error>
|
|
where
|
|
B: IntoIterator<Item = u8>,
|
|
{
|
|
let iter = self.load_from_iter(bytes);
|
|
let addr = I2cAddress::Regular(address);
|
|
self.write_base(addr, I2cCmd::Start, iter)?;
|
|
self.read_internal(addr, buffer)
|
|
}
|
|
}
|
|
)+
|
|
}
|
|
}
|
|
|
|
i2c_master!(
|
|
I2CA: (i2ca, PeripheralClocks::I2c0),
|
|
I2CB: (i2cb, PeripheralClocks::I2c1),
|
|
);
|
|
|
|
//==================================================================================================
|
|
// I2C Slave
|
|
//==================================================================================================
|
|
|
|
pub struct I2cSlave<I2C, ADDR = SevenBitAddress> {
|
|
i2c_base: I2cBase<I2C>,
|
|
_addr: PhantomData<ADDR>,
|
|
}
|
|
|
|
macro_rules! i2c_slave {
|
|
($($I2CX:ident: ($i2cx:ident, $i2cx_slave:ident),)+) => {
|
|
$(
|
|
impl<ADDR> I2cSlave<$I2CX, ADDR> {
|
|
fn $i2cx_slave(
|
|
i2c: $I2CX,
|
|
cfg: SlaveConfig,
|
|
sys_clk: impl Into<Hertz>,
|
|
speed_mode: I2cSpeed,
|
|
sys_cfg: Option<&mut SYSCONFIG>,
|
|
) -> Self {
|
|
I2cSlave {
|
|
i2c_base: I2cBase::$i2cx(
|
|
i2c,
|
|
sys_clk,
|
|
speed_mode,
|
|
None,
|
|
Some(&cfg),
|
|
sys_cfg
|
|
),
|
|
_addr: PhantomData,
|
|
}
|
|
.enable_slave()
|
|
}
|
|
|
|
#[inline]
|
|
pub fn enable_slave(self) -> Self {
|
|
self.i2c_base
|
|
.i2c
|
|
.s0_ctrl
|
|
.modify(|_, w| w.enable().set_bit());
|
|
self
|
|
}
|
|
|
|
#[inline]
|
|
pub fn disable_slave(self) -> Self {
|
|
self.i2c_base
|
|
.i2c
|
|
.s0_ctrl
|
|
.modify(|_, w| w.enable().clear_bit());
|
|
self
|
|
}
|
|
|
|
#[inline(always)]
|
|
fn load_fifo(&self, word: u8) {
|
|
self.i2c_base
|
|
.i2c
|
|
.s0_data
|
|
.write(|w| unsafe { w.bits(word as u32) });
|
|
}
|
|
|
|
#[inline(always)]
|
|
fn read_fifo(&self) -> u8 {
|
|
self.i2c_base.i2c.s0_data.read().bits() as u8
|
|
}
|
|
|
|
#[inline]
|
|
fn clear_tx_fifo(&self) {
|
|
self.i2c_base
|
|
.i2c
|
|
.s0_fifo_clr
|
|
.write(|w| w.txfifo().set_bit());
|
|
}
|
|
|
|
#[inline]
|
|
fn clear_rx_fifo(&self) {
|
|
self.i2c_base
|
|
.i2c
|
|
.s0_fifo_clr
|
|
.write(|w| w.rxfifo().set_bit());
|
|
}
|
|
|
|
/// Get the last address that was matched by the slave control and the corresponding
|
|
/// master direction
|
|
pub fn last_address(&self) -> (I2cDirection, u32) {
|
|
let bits = self.i2c_base.i2c.s0_lastaddress.read().bits();
|
|
match bits & 0x01 {
|
|
0 => (I2cDirection::Send, bits >> 1),
|
|
1 => (I2cDirection::Read, bits >> 1),
|
|
_ => (I2cDirection::Send, bits >> 1),
|
|
}
|
|
}
|
|
|
|
pub fn write(&mut self, output: &[u8]) -> Result<(), Error> {
|
|
let len = output.len();
|
|
// It should theoretically possible to transfer larger data sizes by tracking
|
|
// the number of sent words and setting it to 0x7fe as soon as only that many
|
|
// bytes are remaining. However, large transfer like this are not common. This
|
|
// feature will therefore not be supported for now.
|
|
if len > 0x7fe {
|
|
return Err(Error::DataTooLarge);
|
|
}
|
|
let mut bytes = output.iter();
|
|
// FIFO has a depth of 16. We load slightly above the trigger level
|
|
// but not all of it because the transaction might fail immediately
|
|
const FILL_DEPTH: usize = 12;
|
|
|
|
// load the FIFO
|
|
for _ in 0..core::cmp::min(FILL_DEPTH, len) {
|
|
self.load_fifo(*bytes.next().unwrap());
|
|
}
|
|
|
|
let status_reader = self.i2c_base.i2c.s0_status.read();
|
|
let mut load_if_next_available = || {
|
|
if let Some(next_byte) = bytes.next() {
|
|
self.load_fifo(*next_byte);
|
|
}
|
|
};
|
|
loop {
|
|
if status_reader.nackdata().bit_is_set() {
|
|
self.clear_tx_fifo();
|
|
return Err(Error::NackData);
|
|
} else if status_reader.idle().bit_is_set() {
|
|
return Ok(());
|
|
} else {
|
|
while !status_reader.txnfull().bit_is_set() {
|
|
load_if_next_available();
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
pub fn read(&mut self, buffer: &mut [u8]) -> Result<(), Error> {
|
|
let len = buffer.len();
|
|
// It should theoretically possible to transfer larger data sizes by tracking
|
|
// the number of sent words and setting it to 0x7fe as soon as only that many
|
|
// bytes are remaining. However, large transfer like this are not common. This
|
|
// feature will therefore not be supported for now.
|
|
if len > 0x7fe {
|
|
return Err(Error::DataTooLarge);
|
|
}
|
|
// Clear the receive FIFO
|
|
self.clear_rx_fifo();
|
|
|
|
let mut buf_iter = buffer.iter_mut();
|
|
let mut read_bytes = 0;
|
|
let mut read_if_next_available = || {
|
|
if let Some(next_byte) = buf_iter.next() {
|
|
*next_byte = self.read_fifo();
|
|
}
|
|
};
|
|
loop {
|
|
let status_reader = self.i2c_base.i2c.s0_status.read();
|
|
if status_reader.idle().bit_is_set() {
|
|
if read_bytes != len {
|
|
return Err(Error::InsufficientDataReceived);
|
|
}
|
|
return Ok(());
|
|
} else if status_reader.rxnempty().bit_is_set() {
|
|
read_bytes += 1;
|
|
read_if_next_available();
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
impl I2cSlave<$I2CX, SevenBitAddress> {
|
|
/// Create a new I2C slave for seven bit addresses
|
|
///
|
|
/// Returns a [`Error::WrongAddrMode`] error if a ten bit address is passed
|
|
pub fn i2ca(
|
|
i2c: $I2CX,
|
|
cfg: SlaveConfig,
|
|
sys_clk: impl Into<Hertz>,
|
|
speed_mode: I2cSpeed,
|
|
sys_cfg: Option<&mut SYSCONFIG>,
|
|
) -> Result<Self, Error> {
|
|
if let I2cAddress::TenBit(_) = cfg.addr {
|
|
return Err(Error::WrongAddrMode);
|
|
}
|
|
Ok(Self::$i2cx_slave(i2c, cfg, sys_clk, speed_mode, sys_cfg))
|
|
}
|
|
}
|
|
|
|
impl I2cSlave<$I2CX, TenBitAddress> {
|
|
pub fn $i2cx(
|
|
i2c: $I2CX,
|
|
cfg: SlaveConfig,
|
|
sys_clk: impl Into<Hertz>,
|
|
speed_mode: I2cSpeed,
|
|
sys_cfg: Option<&mut SYSCONFIG>,
|
|
) -> Self {
|
|
Self::$i2cx_slave(i2c, cfg, sys_clk, speed_mode, sys_cfg)
|
|
}
|
|
}
|
|
)+
|
|
}
|
|
}
|
|
|
|
i2c_slave!(I2CA: (i2ca, i2ca_slave), I2CB: (i2cb, i2cb_slave),);
|