664 lines
24 KiB
Rust
664 lines
24 KiB
Rust
//! API for the GPIO pins
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//!
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//! ## Examples
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//!
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//! - [Blinky example](https://github.com/robamu-org/va108xx-hal-rs/blob/main/examples/blinky.rs)
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use crate::pac::SYSCONFIG;
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use core::convert::Infallible;
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use core::marker::PhantomData;
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use cortex_m::singleton;
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use embedded_hal::digital::v2::{InputPin, OutputPin, StatefulOutputPin, ToggleableOutputPin};
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use va108xx::IOCONFIG;
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/// Extension trait to split a GPIO peripheral in independent pins and registers
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pub trait GpioExt {
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/// The parts to split the GPIO into.
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type Parts;
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/// Splits the GPIO block into independent pins and registers.
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fn split(&mut self, syscfg: &mut SYSCONFIG) -> Option<Self::Parts>;
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}
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#[derive(Debug, PartialEq)]
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pub enum PinModeError {
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InputDisabledForOutput,
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IsMasked,
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}
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#[derive(Debug, PartialEq)]
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pub enum PinState {
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Low = 0,
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High = 1,
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}
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enum PortId {
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A,
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B,
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}
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trait GpioRegExt {
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fn is_low(&self, pos: u8) -> bool;
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fn is_set_low(&self, pos: usize, port_id: &PortId) -> Result<bool, PinModeError>;
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fn input_enabled_for_output(&self, pos: usize, port_id: &PortId) -> bool;
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fn set_high(&self, pos: u8);
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fn set_low(&self, pos: u8);
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fn toggle(&self, pos: u8);
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}
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/// Input mode (type state)
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pub struct Input<MODE> {
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_mode: PhantomData<MODE>,
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}
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/// Output mode (type state)
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pub struct Output<MODE> {
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_mode: PhantomData<MODE>,
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}
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/// Floating input (type state)
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pub struct Floating;
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/// Pulled down input (type state)
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pub struct PullDown;
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/// Pulled up input (type state)
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pub struct PullUp;
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/// Open drain output (type state)
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pub struct OpenDrain;
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// Push-pull output (type state)
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pub struct PushPull;
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pub struct OutputInverted;
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pub struct InputInverted;
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// FUNSEL0 is the regular GPIO port configuration
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pub struct FUNSEL1;
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pub struct FUNSEL2;
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pub struct FUNSEL3;
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/// Function select (type state)
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pub struct AltFunc<FUN> {
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_mode: PhantomData<FUN>,
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}
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pub enum FilterType {
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SystemClock = 0,
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DirectInputWithSynchronization = 1,
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FilterOneClockCycle = 2,
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FilterTwoClockCycles = 3,
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FilterThreeClockCycles = 4,
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FilterFourClockCycles = 5,
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}
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pub enum FilterClkSel {
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SysClk = 0,
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Clk1 = 1,
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Clk2 = 2,
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Clk3 = 3,
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Clk4 = 4,
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Clk5 = 5,
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Clk6 = 6,
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Clk7 = 7,
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}
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/// Fully erased pin
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pub struct Pin<MODE> {
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i: u8,
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port_id: PortId,
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port: *const dyn GpioRegExt,
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_mode: PhantomData<MODE>,
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}
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// NOTE(unsafe) this only enables read access to the same pin from multiple threads
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unsafe impl<MODE> Send for Pin<MODE> {}
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impl<MODE> StatefulOutputPin for Pin<Output<MODE>> {
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#[inline(always)]
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fn is_set_high(&self) -> Result<bool, Self::Error> {
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self.is_set_low().map(|v| !v)
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}
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#[inline(always)]
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fn is_set_low(&self) -> Result<bool, Self::Error> {
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unsafe { (*self.port).is_set_low(self.i.into(), &self.port_id) }
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}
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}
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impl<MODE> OutputPin for Pin<Output<MODE>> {
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type Error = PinModeError;
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#[inline(always)]
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fn set_high(&mut self) -> Result<(), Self::Error> {
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unsafe { (*self.port).set_high(self.i) };
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Ok(())
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}
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#[inline(always)]
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fn set_low(&mut self) -> Result<(), Self::Error> {
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unsafe { (*self.port).set_low(self.i) }
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Ok(())
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}
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}
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impl<MODE> ToggleableOutputPin for Pin<Output<MODE>> {
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type Error = Infallible;
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#[inline(always)]
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fn toggle(&mut self) -> Result<(), Self::Error> {
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unsafe { (*self.port).toggle(self.i) }
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Ok(())
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}
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}
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impl InputPin for Pin<Output<OpenDrain>> {
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type Error = Infallible;
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#[inline(always)]
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fn is_high(&self) -> Result<bool, Self::Error> {
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self.is_low().map(|v| !v)
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}
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#[inline(always)]
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fn is_low(&self) -> Result<bool, Self::Error> {
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Ok(unsafe { (*self.port).is_low(self.i) })
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}
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}
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impl<MODE> InputPin for Pin<Input<MODE>> {
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type Error = Infallible;
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#[inline(always)]
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fn is_high(&self) -> Result<bool, Self::Error> {
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self.is_low().map(|v| !v)
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}
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#[inline(always)]
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fn is_low(&self) -> Result<bool, Self::Error> {
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Ok(unsafe { (*self.port).is_low(self.i) })
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}
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}
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// This is only needs to be implemented for PORTA because PORTB is derived
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// from PORTA
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impl GpioRegExt for crate::pac::porta::RegisterBlock {
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#[inline(always)]
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fn is_low(&self, pos: u8) -> bool {
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self.datainraw().read().bits() & (1 << pos) == 0
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}
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#[inline(always)]
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fn is_set_low(&self, pos: usize, port_id: &PortId) -> Result<bool, PinModeError> {
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if self.input_enabled_for_output(pos, port_id) {
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Ok(self.datainraw().read().bits() & (1 << pos) == 0)
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} else {
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Err(PinModeError::InputDisabledForOutput)
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}
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}
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#[inline(always)]
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fn set_high(&self, pos: u8) {
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unsafe { self.setout().write(|w| w.bits(1 << pos)) }
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}
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#[inline(always)]
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fn set_low(&self, pos: u8) {
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unsafe { self.clrout().write(|w| w.bits(1 << pos)) }
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}
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#[inline(always)]
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fn toggle(&self, pos: u8) {
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unsafe { self.togout().write(|w| w.bits(1 << pos)) }
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}
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#[inline(always)]
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fn input_enabled_for_output(&self, pos: usize, port_id: &PortId) -> bool {
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unsafe {
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let iocfg = &(*IOCONFIG::ptr());
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match port_id {
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PortId::A => iocfg.porta[pos].read().iewo().bit_is_set(),
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PortId::B => iocfg.portb[pos].read().iewo().bit_is_set(),
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}
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}
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}
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}
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macro_rules! gpio {
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($PORTX:ident, $portx:ident, $port_id:path, [
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$($PXi:ident: ($pxi:ident, $i:expr),)+
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]) => {
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pub mod $portx {
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use core::marker::PhantomData;
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use core::convert::Infallible;
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use super::{
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FUNSEL1, FUNSEL2, FUNSEL3, Floating, AltFunc, GpioExt, Input, OpenDrain,
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PullUp, Output, FilterType, FilterClkSel, Pin, GpioRegExt, PushPull,
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PinModeError, PinState, PortId, singleton
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};
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use crate::{pac::$PORTX, pac::SYSCONFIG, pac::IOCONFIG};
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use embedded_hal::digital::v2::{
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InputPin, OutputPin, StatefulOutputPin, ToggleableOutputPin
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};
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pub struct Parts {
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$(
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pub $pxi: $PXi<Input<Floating>>,
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)+
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}
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pub fn get_perid(port: &$PORTX) -> u32 {
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port.perid.read().bits()
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}
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impl GpioExt for $PORTX {
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type Parts = Parts;
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/// This function splits the PORT into the individual pins
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/// Should only be called once and returns None on subsequent calls
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fn split(&mut self, syscfg: &mut SYSCONFIG) -> Option<Parts> {
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let _: &'static mut bool = singleton!(: bool = false)?;
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syscfg.peripheral_clk_enable.modify(|_, w| {
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w.$portx().set_bit();
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w.gpio().set_bit();
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w.ioconfig().set_bit();
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w
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});
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Some(Parts {
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$(
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$pxi: $PXi { _mode : PhantomData },
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)+
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})
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}
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}
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fn _set_alternate_mode(iocfg: &mut IOCONFIG, index: usize, mode: u8) {
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iocfg.$portx[index].modify(|_, w| unsafe {
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w.funsel().bits(mode)
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});
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}
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$(
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pub struct $PXi<MODE> {
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_mode: PhantomData<MODE>,
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}
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impl<MODE> $PXi<MODE> {
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pub fn into_funsel_1(self, iocfg: &mut IOCONFIG) -> $PXi<AltFunc<FUNSEL1>> {
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_set_alternate_mode(iocfg, $i, 1);
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$PXi { _mode: PhantomData }
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}
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pub fn into_funsel_2(self, iocfg: &mut IOCONFIG) -> $PXi<AltFunc<FUNSEL2>> {
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_set_alternate_mode(iocfg, $i, 2);
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$PXi { _mode: PhantomData }
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}
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pub fn into_funsel_3(self, iocfg: &mut IOCONFIG) -> $PXi<AltFunc<FUNSEL3>> {
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_set_alternate_mode(iocfg, $i, 3);
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$PXi { _mode: PhantomData }
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}
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// Get DATAMASK bit for this particular pin
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#[inline(always)]
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pub fn datamask(&self, port: &$PORTX) -> bool {
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(port.datamask().read().bits() >> $i) == 1
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}
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/// Set DATAMASK bit for this particular pin. 1 is the default
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/// state of the bit and allows access of the corresponding bit
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#[inline(always)]
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pub fn set_datamask(self, port: &mut $PORTX) -> Self {
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unsafe {
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port.datamask().modify(|r, w| w.bits(r.bits() | (1 << $i)))
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}
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self
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}
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/// Clear DATAMASK bit for this particular pin. This prevents access
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/// of the corresponding bit for output and input operations
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#[inline(always)]
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pub fn clear_datamask(self, port: &mut $PORTX) -> Self {
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unsafe {
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port.datamask().modify(|r, w| w.bits(r.bits() & !(1 << $i)))
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}
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self
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}
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pub fn into_floating_input(
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self, iocfg: &mut IOCONFIG, port: &mut $PORTX
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) -> $PXi<Input<Floating>> {
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unsafe {
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iocfg.$portx[$i].modify(|_, w| {
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w.funsel().bits(0);
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w.pen().clear_bit();
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w.opendrn().clear_bit()
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});
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port.dir().modify(|r,w| w.bits(r.bits() & !(1 << $i)));
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}
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$PXi { _mode: PhantomData }
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}
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pub fn into_pull_up_input(self, iocfg: &mut IOCONFIG, port: &mut $PORTX) -> $PXi<Input<PullUp>> {
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unsafe {
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iocfg.$portx[$i].modify(|_, w| {
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w.funsel().bits(0);
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w.pen().set_bit();
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w.plevel().set_bit();
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w.opendrn().clear_bit()
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});
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port.dir().modify(|r,w| w.bits(r.bits() & !(1 << $i)));
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}
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$PXi { _mode: PhantomData }
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}
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pub fn into_pull_down_input(
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self, iocfg: &mut IOCONFIG, port: &mut $PORTX
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) -> $PXi<Input<PullUp>> {
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unsafe {
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iocfg.$portx[$i].modify(|_, w| {
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w.funsel().bits(0);
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w.pen().set_bit();
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w.plevel().clear_bit();
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w.opendrn().clear_bit()
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});
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port.dir().modify(|r,w| w.bits(r.bits() & !(1 << $i)));
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}
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$PXi { _mode: PhantomData }
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}
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pub fn into_open_drain_output(
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self, iocfg: &mut IOCONFIG
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) -> $PXi<Output<OpenDrain>> {
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unsafe {
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iocfg.$portx[$i].modify(|_, w| {
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w.funsel().bits(0);
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w.pen().clear_bit();
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w.opendrn().set_bit()
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});
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let port_reg = &(*$PORTX::ptr());
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port_reg.dir().modify(|r,w| w.bits(r.bits() | (1 << $i)));
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}
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$PXi { _mode: PhantomData }
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}
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pub fn into_push_pull_output(
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self, iocfg: &mut IOCONFIG, port_reg: &mut $PORTX
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) -> $PXi<Output<PushPull>> {
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unsafe {
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iocfg.$portx[$i].modify(|_, w| {
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w.funsel().bits(0);
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w.opendrn().clear_bit()
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});
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port_reg.dir().modify(|r,w| w.bits(r.bits() | (1 << $i)));
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port_reg.clrout().write(|w| w.bits(1 << $i))
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}
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$PXi { _mode: PhantomData }
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}
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pub fn filter_type(
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self, iocfg: &mut IOCONFIG, filter: FilterType, clksel: FilterClkSel
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) -> Self {
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unsafe {
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iocfg.$portx[$i].modify(|_, w| {
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w.flttype().bits(filter as u8);
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w.fltclk().bits(clksel as u8)
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});
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}
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self
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}
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}
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impl<MODE> $PXi<Input<MODE>> {
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pub fn input_inversion(self, iocfg: &mut IOCONFIG, enable: bool) -> Self {
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if enable {
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iocfg.$portx[$i].modify(|_, w| w.invinp().set_bit());
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} else {
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iocfg.$portx[$i].modify(|_, w| w.invinp().clear_bit());
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}
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self
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}
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/// This function takes account for the data mask register
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#[inline(always)]
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pub fn is_high_masked(&self, port: &$PORTX) -> Result<bool, PinModeError> {
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self.is_low_masked(port).map(|v| !v)
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}
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/// This function takes account for the data mask register
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#[inline(always)]
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pub fn is_low_masked(&self, port: &$PORTX) -> Result<bool, PinModeError> {
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if ((port.datamask().read().bits() >> $i) & 1) == 0 {
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Err(PinModeError::IsMasked)
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} else {
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Ok(port.datain().read().bits() & (1 << $i) == 0)
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}
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}
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}
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impl<MODE> $PXi<Output<MODE>> {
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pub fn output_inversion(self, iocfg: &mut IOCONFIG, enable: bool) -> Self {
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if enable {
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iocfg.$portx[$i].modify(|_, w| w.invout().set_bit());
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} else {
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iocfg.$portx[$i].modify(|_, w| w.invout().clear_bit());
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}
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self
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}
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/// Enable Input even when in output mode. In
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/// this mode the input receiver is enabled even
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/// if the direction is configured as an output.
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/// This allows monitoring of output values
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pub fn enable_input(self, iocfg: &mut IOCONFIG, enable: bool) -> Self {
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if enable {
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iocfg.$portx[$i].modify(|_, w| w.iewo().set_bit());
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} else {
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iocfg.$portx[$i].modify(|_, w| w.iewo().clear_bit());
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}
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self
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}
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/// Enable Pull up/down even when output is active. The Default is to
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/// disable pull up/down when output is actively driven. This bit enables the
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/// pull up/down all the time.
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///
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/// # Arguments
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///
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/// `enable` - Enable the peripheral functionality
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/// `enable_pullup` - Enable the pullup itself
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pub fn enable_pull_up(
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self, iocfg: &mut IOCONFIG, enable: bool, enable_pullup: bool
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) -> Self {
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iocfg.$portx[$i].modify(|_, w| {
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if enable { w.pwoa().set_bit(); } else { w.pwoa().clear_bit(); }
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if enable_pullup { w.pen().set_bit(); } else { w.pen().clear_bit(); }
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w.plevel().set_bit()
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});
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self
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}
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/// Enable Pull up/down even when output is active. The Default is to disable
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/// pull up/down when output is actively driven. This bit enables the
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/// pull up/down all the time.
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///
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/// # Arguments
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///
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/// `enable` - Enable the peripheral functionality
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/// `enable_pullup` - Enable the pulldown itself
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pub fn enable_pull_down(
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self, iocfg: &mut IOCONFIG, enable: bool, enable_pulldown: bool
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) -> Self {
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iocfg.$portx[$i].modify(|_, w| {
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if enable { w.pwoa().set_bit(); } else { w.pwoa().clear_bit(); }
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if enable_pulldown { w.pen().set_bit(); } else { w.pen().clear_bit(); }
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w.plevel().clear_bit()
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});
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self
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}
|
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}
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impl<MODE> $PXi<Output<MODE>> {
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/// Erases the pin number from the type
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///
|
|
/// This is useful when you want to collect the pins into an array where you
|
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/// need all the elements to have the same type
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pub fn downgrade(self) -> Pin<Output<MODE>> {
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Pin {
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i: $i,
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port_id: $port_id,
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port: $PORTX::ptr() as *const dyn GpioRegExt,
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_mode: self._mode,
|
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}
|
|
}
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|
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/// This function takes account for the data mask register
|
|
#[inline(always)]
|
|
pub fn set_low_masked(&self, port: &$PORTX) -> Result<(), PinModeError> {
|
|
if ((port.datamask().read().bits() >> $i) & 1) == 0 {
|
|
Err(PinModeError::IsMasked)
|
|
} else {
|
|
Ok(unsafe { (*$PORTX::ptr()).set_low($i) })
|
|
}
|
|
}
|
|
/// This function takes account for the data mask register
|
|
#[inline(always)]
|
|
pub fn set_high_masked(&self, port: &$PORTX) -> Result<(), PinModeError> {
|
|
if ((port.datamask().read().bits() >> $i) & 1) == 0 {
|
|
Err(PinModeError::IsMasked)
|
|
} else {
|
|
Ok(unsafe { (*$PORTX::ptr()).set_high($i) })
|
|
}
|
|
}
|
|
|
|
pub fn pulse_mode(self, port: &mut $PORTX, enable: bool, default_state: PinState) -> Self {
|
|
unsafe {
|
|
if enable {
|
|
port.pulse().modify(|r, w| w.bits(r.bits() | (1 << $i)));
|
|
} else {
|
|
port.pulse().modify(|r, w| w.bits(r.bits() & !(1 << $i)));
|
|
}
|
|
if default_state == PinState::Low {
|
|
port.pulsebase().modify(|r,w| w.bits(r.bits() & !(1 << $i)));
|
|
}
|
|
else {
|
|
port.pulsebase().modify(|r,w| w.bits(r.bits() | (1 << $i)));
|
|
}
|
|
}
|
|
self
|
|
}
|
|
|
|
pub fn delay(self, port: &mut $PORTX, delay_1: bool, delay_2: bool) -> Self {
|
|
unsafe {
|
|
if delay_1 {
|
|
port.delay1().modify(|r, w| w.bits(r.bits() | (1 << $i)));
|
|
} else {
|
|
port.delay1().modify(|r, w| w.bits(r.bits() & !(1 << $i)));
|
|
}
|
|
if delay_2 {
|
|
port.delay2().modify(|r, w| w.bits(r.bits() | (1 << $i)));
|
|
} else {
|
|
port.delay2().modify(|r, w| w.bits(r.bits() & !(1 << $i)));
|
|
}
|
|
}
|
|
self
|
|
}
|
|
}
|
|
|
|
impl<MODE> StatefulOutputPin for $PXi<Output<MODE>> {
|
|
#[inline(always)]
|
|
fn is_set_high(&self) -> Result<bool, Self::Error> {
|
|
self.is_set_low().map(|v| !v)
|
|
}
|
|
#[inline(always)]
|
|
fn is_set_low(&self) -> Result<bool, Self::Error> {
|
|
unsafe {
|
|
(*$PORTX::ptr()).is_set_low($i, &$port_id)
|
|
}
|
|
}
|
|
}
|
|
impl<MODE> OutputPin for $PXi<Output<MODE>> {
|
|
type Error = PinModeError;
|
|
#[inline(always)]
|
|
fn set_high(&mut self) -> Result<(), Self::Error> {
|
|
Ok(unsafe { (*$PORTX::ptr()).set_high($i) })
|
|
}
|
|
#[inline(always)]
|
|
fn set_low(&mut self) -> Result<(), Self::Error> {
|
|
Ok(unsafe { (*$PORTX::ptr()).set_low($i) })
|
|
}
|
|
}
|
|
impl<MODE> ToggleableOutputPin for $PXi<Output<MODE>> {
|
|
type Error = Infallible;
|
|
#[inline(always)]
|
|
fn toggle(&mut self) -> Result<(), Self::Error> {
|
|
Ok(unsafe { (*$PORTX::ptr()).toggle($i) })
|
|
}
|
|
}
|
|
impl<MODE> $PXi<Input<MODE>> {
|
|
/// Erases the pin number from the type
|
|
///
|
|
/// This is useful when you want to collect the pins into an array where you
|
|
/// need all the elements to have the same type
|
|
pub fn downgrade(self) -> Pin<Input<MODE>> {
|
|
Pin {
|
|
i: $i,
|
|
port_id: $port_id,
|
|
port: $PORTX::ptr() as *const dyn GpioRegExt,
|
|
_mode: self._mode,
|
|
}
|
|
}
|
|
}
|
|
impl<MODE> InputPin for $PXi<Input<MODE>> {
|
|
type Error = Infallible;
|
|
#[inline(always)]
|
|
fn is_high(&self) -> Result<bool, Self::Error> {
|
|
self.is_low().map(|v| !v)
|
|
}
|
|
#[inline(always)]
|
|
fn is_low(&self) -> Result<bool, Self::Error> {
|
|
Ok(unsafe { (*$PORTX::ptr()).is_low($i) })
|
|
}
|
|
}
|
|
)+
|
|
}
|
|
}
|
|
}
|
|
|
|
gpio!(PORTA, porta, PortId::A, [
|
|
PA0: (pa0, 0),
|
|
PA1: (pa1, 1),
|
|
PA2: (pa2, 2),
|
|
PA3: (pa3, 3),
|
|
PA4: (pa4, 4),
|
|
PA5: (pa5, 5),
|
|
PA6: (pa6, 6),
|
|
PA7: (pa7, 7),
|
|
PA8: (pa8, 8),
|
|
PA9: (pa9, 9),
|
|
PA10: (pa10, 10),
|
|
PA11: (pa11, 11),
|
|
PA12: (pa12, 12),
|
|
PA13: (pa13, 13),
|
|
PA14: (pa14, 14),
|
|
PA15: (pa15, 15),
|
|
PA16: (pa16, 16),
|
|
PA17: (pa17, 17),
|
|
PA18: (pa18, 18),
|
|
PA19: (pa19, 19),
|
|
PA20: (pa20, 20),
|
|
PA21: (pa21, 21),
|
|
PA22: (pa22, 22),
|
|
PA23: (pa23, 23),
|
|
PA24: (pa24, 24),
|
|
PA25: (pa25, 25),
|
|
PA26: (pa26, 26),
|
|
PA27: (pa27, 27),
|
|
PA28: (pa28, 28),
|
|
PA29: (pa29, 29),
|
|
PA30: (pa30, 30),
|
|
PA31: (pa31, 31),
|
|
]);
|
|
|
|
gpio!(PORTB, portb, PortId::B, [
|
|
PB0: (pb0, 0),
|
|
PB1: (pb1, 1),
|
|
PB2: (pb2, 2),
|
|
PB3: (pb3, 3),
|
|
PB4: (pb4, 4),
|
|
PB5: (pb5, 5),
|
|
PB6: (pb6, 6),
|
|
PB7: (pb7, 7),
|
|
PB8: (pb8, 8),
|
|
PB9: (pb9, 9),
|
|
PB10: (pb10, 10),
|
|
PB11: (pb11, 11),
|
|
PB12: (pb12, 12),
|
|
PB13: (pb13, 13),
|
|
PB14: (pb14, 14),
|
|
PB15: (pb15, 15),
|
|
PB16: (pb16, 16),
|
|
PB17: (pb17, 17),
|
|
PB18: (pb18, 18),
|
|
PB19: (pb19, 19),
|
|
PB20: (pb20, 20),
|
|
PB21: (pb21, 21),
|
|
PB22: (pb22, 22),
|
|
PB23: (pb23, 23),
|
|
]);
|