Robin Mueller
3886e2f11f
Initial I2C HAL implementation. Only the I2cMaster was tested so far, I2cSlave will be tested next. Master side was tested with a temerature sensor example application in the vorago-reb1 crate
771 lines
29 KiB
Rust
771 lines
29 KiB
Rust
//! API for the SPI peripheral
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//!
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//! ## Examples
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//!
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//! - [Blocking SPI example](https://github.com/robamu-org/va108xx-hal-rs/blob/main/examples/spi.rs)
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use crate::Sealed;
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use crate::{
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clock::{enable_peripheral_clock, PeripheralClocks},
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gpio::pins::{
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AltFunc1, AltFunc2, AltFunc3, Pin, PA10, PA11, PA12, PA13, PA14, PA15, PA16, PA17, PA18,
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PA19, PA20, PA21, PA22, PA23, PA24, PA25, PA26, PA27, PA28, PA29, PA30, PA31, PB0, PB1,
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PB10, PB11, PB12, PB13, PB14, PB15, PB16, PB17, PB18, PB19, PB2, PB22, PB23, PB3, PB4, PB5,
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PB6, PB7, PB8, PB9,
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},
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pac::{SPIA, SPIB, SPIC, SYSCONFIG},
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time::Hertz,
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};
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use core::{convert::Infallible, fmt::Debug, marker::PhantomData};
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use embedded_hal::{
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blocking,
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spi::{FullDuplex, Mode, MODE_0, MODE_1, MODE_2, MODE_3},
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};
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//==================================================================================================
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// Defintions
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//==================================================================================================
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#[derive(Debug, PartialEq, Copy, Clone)]
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pub enum HwChipSelectId {
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Id0 = 0,
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Id1 = 1,
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Id2 = 2,
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Id3 = 3,
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Id4 = 4,
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Id5 = 5,
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Id6 = 6,
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Id7 = 7,
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Invalid = 0xff,
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}
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#[derive(Debug, PartialEq, Copy, Clone)]
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pub enum WordSize {
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OneBit = 0x00,
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FourBits = 0x03,
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EightBits = 0x07,
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SixteenBits = 0x0f,
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}
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//==================================================================================================
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// Pin type definitions
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//==================================================================================================
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pub trait PinSck<SPI>: Sealed {}
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pub trait PinMosi<SPI>: Sealed {}
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pub trait PinMiso<SPI>: Sealed {}
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pub trait HwCs: Sealed {
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const CS_ID: HwChipSelectId;
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}
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pub trait OptionalHwCs<SPI>: HwCs + Sealed {}
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macro_rules! hw_cs_pin {
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($SPIx:ident, $PXx:ident, $AFx:ident, $HwCsIdent:path, $typedef:ident) => {
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impl HwCs for Pin<$PXx, $AFx> {
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const CS_ID: HwChipSelectId = $HwCsIdent;
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}
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impl OptionalHwCs<$SPIx> for Pin<$PXx, $AFx> {}
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pub type $typedef = Pin<$PXx, $AFx>;
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};
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}
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impl HwCs for NoneT {
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const CS_ID: HwChipSelectId = HwChipSelectId::Invalid;
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}
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impl OptionalHwCs<SPIA> for NoneT {}
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impl OptionalHwCs<SPIB> for NoneT {}
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// SPIA
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impl PinSck<SPIA> for Pin<PA31, AltFunc1> {}
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impl PinMosi<SPIA> for Pin<PA30, AltFunc1> {}
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impl PinMiso<SPIA> for Pin<PA29, AltFunc1> {}
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pub type SpiAPortASck = Pin<PA31, AltFunc1>;
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pub type SpiAPortAMosi = Pin<PA30, AltFunc1>;
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pub type SpiAPortAMiso = Pin<PA29, AltFunc1>;
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impl PinSck<SPIA> for Pin<PB9, AltFunc2> {}
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impl PinMosi<SPIA> for Pin<PB8, AltFunc2> {}
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impl PinMiso<SPIA> for Pin<PB7, AltFunc2> {}
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pub type SpiAPortBSck = Pin<PB9, AltFunc2>;
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pub type SpiAPortBMosi = Pin<PB8, AltFunc2>;
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pub type SpiAPortBMiso = Pin<PB7, AltFunc2>;
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hw_cs_pin!(SPIA, PA28, AltFunc1, HwChipSelectId::Id0, HwCs0SpiAPortA);
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hw_cs_pin!(SPIA, PA27, AltFunc1, HwChipSelectId::Id1, HwCs1SpiAPortA);
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hw_cs_pin!(SPIA, PA26, AltFunc1, HwChipSelectId::Id2, HwCs2SpiAPortA);
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hw_cs_pin!(SPIA, PA25, AltFunc1, HwChipSelectId::Id3, HwCs3SpiAPortA);
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hw_cs_pin!(SPIA, PA24, AltFunc1, HwChipSelectId::Id4, HwCs4SpiAPortA);
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hw_cs_pin!(SPIA, PA23, AltFunc1, HwChipSelectId::Id5, HwCs5SpiAPortA);
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hw_cs_pin!(SPIA, PA22, AltFunc1, HwChipSelectId::Id6, HwCs6SpiAPortA);
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hw_cs_pin!(SPIA, PA21, AltFunc1, HwChipSelectId::Id7, HwCs7SpiAPortA);
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hw_cs_pin!(SPIA, PB6, AltFunc2, HwChipSelectId::Id0, HwCs0SpiAPortB);
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hw_cs_pin!(SPIA, PB5, AltFunc2, HwChipSelectId::Id6, HwCs6SpiAPortB);
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hw_cs_pin!(SPIA, PB4, AltFunc2, HwChipSelectId::Id5, HwCs5SpiAPortB);
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hw_cs_pin!(SPIA, PB3, AltFunc2, HwChipSelectId::Id4, HwCs4SpiAPortB);
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hw_cs_pin!(SPIA, PB2, AltFunc2, HwChipSelectId::Id3, HwCs3SpiAPortB);
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hw_cs_pin!(SPIA, PB1, AltFunc2, HwChipSelectId::Id2, HwCs2SpiAPortB);
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hw_cs_pin!(SPIA, PB0, AltFunc2, HwChipSelectId::Id1, HwCs1SpiAPortB);
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// SPIB
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impl PinSck<SPIB> for Pin<PA20, AltFunc2> {}
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impl PinMosi<SPIB> for Pin<PA19, AltFunc2> {}
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impl PinMiso<SPIB> for Pin<PA18, AltFunc2> {}
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pub type SpiBPortASck = Pin<PA20, AltFunc2>;
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pub type SpiBPortAMosi = Pin<PA19, AltFunc2>;
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pub type SpiBPortAMiso = Pin<PA18, AltFunc2>;
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impl PinSck<SPIB> for Pin<PB19, AltFunc1> {}
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impl PinMosi<SPIB> for Pin<PB18, AltFunc1> {}
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impl PinMiso<SPIB> for Pin<PB17, AltFunc1> {}
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impl PinSck<SPIB> for Pin<PB5, AltFunc1> {}
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impl PinMosi<SPIB> for Pin<PB4, AltFunc1> {}
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impl PinMiso<SPIB> for Pin<PB3, AltFunc1> {}
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hw_cs_pin!(SPIB, PB16, AltFunc1, HwChipSelectId::Id0, HwCs0SpiBPortB0);
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hw_cs_pin!(SPIB, PB15, AltFunc1, HwChipSelectId::Id1, HwCs1SpiBPortB0);
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hw_cs_pin!(SPIB, PB14, AltFunc1, HwChipSelectId::Id2, HwCs2SpiBPortB0);
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hw_cs_pin!(SPIB, PB13, AltFunc1, HwChipSelectId::Id3, HwCs3SpiBPortB);
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hw_cs_pin!(SPIB, PB12, AltFunc1, HwChipSelectId::Id4, HwCs4SpiBPortB);
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hw_cs_pin!(SPIB, PB11, AltFunc1, HwChipSelectId::Id5, HwCs5SpiBPortB);
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hw_cs_pin!(SPIB, PB10, AltFunc1, HwChipSelectId::Id6, HwCs6SpiBPortB);
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hw_cs_pin!(SPIB, PB2, AltFunc1, HwChipSelectId::Id0, HwCs0SpiBPortB1);
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hw_cs_pin!(SPIB, PB1, AltFunc1, HwChipSelectId::Id1, HwCs1SpiBPortB1);
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hw_cs_pin!(SPIB, PB0, AltFunc1, HwChipSelectId::Id2, HwCs2SpiBPortB1);
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hw_cs_pin!(SPIB, PB12, AltFunc2, HwChipSelectId::Id0, HwCs0SpiBPortB2);
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hw_cs_pin!(SPIB, PB11, AltFunc2, HwChipSelectId::Id1, HwCs1SpiBPortB2);
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hw_cs_pin!(SPIB, PB10, AltFunc2, HwChipSelectId::Id2, HwCs2SpiBPortB2);
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hw_cs_pin!(SPIB, PA17, AltFunc2, HwChipSelectId::Id0, HwCs0SpiBPortA);
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hw_cs_pin!(SPIB, PA16, AltFunc2, HwChipSelectId::Id1, HwCs1SpiBPortA);
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hw_cs_pin!(SPIB, PA15, AltFunc2, HwChipSelectId::Id2, HwCs2SpiBPortA);
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hw_cs_pin!(SPIB, PA14, AltFunc2, HwChipSelectId::Id3, HwCs3SpiBPortA);
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hw_cs_pin!(SPIB, PA13, AltFunc2, HwChipSelectId::Id4, HwCs4SpiBPortA);
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hw_cs_pin!(SPIB, PA12, AltFunc2, HwChipSelectId::Id5, HwCs5SpiBPortA0);
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hw_cs_pin!(SPIB, PA11, AltFunc2, HwChipSelectId::Id6, HwCs6SpiBPortA0);
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hw_cs_pin!(SPIB, PA10, AltFunc2, HwChipSelectId::Id7, HwCs7SpiBPortA0);
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hw_cs_pin!(SPIB, PA23, AltFunc2, HwChipSelectId::Id5, HwCs5SpiBPortA1);
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hw_cs_pin!(SPIB, PA22, AltFunc2, HwChipSelectId::Id6, HwCs6SpiBPortA1);
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hw_cs_pin!(SPIB, PA21, AltFunc2, HwChipSelectId::Id7, HwCs7SpiBPortA1);
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// SPIC
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hw_cs_pin!(SPIC, PB9, AltFunc3, HwChipSelectId::Id1, HwCs1SpiCPortB0);
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hw_cs_pin!(SPIC, PB8, AltFunc3, HwChipSelectId::Id2, HwCs2SpiCPortB0);
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hw_cs_pin!(SPIC, PB7, AltFunc3, HwChipSelectId::Id3, HwCs3SpiCPortB);
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hw_cs_pin!(SPIC, PB22, AltFunc3, HwChipSelectId::Id1, HwCs1SpiCPortB1);
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hw_cs_pin!(SPIC, PB23, AltFunc3, HwChipSelectId::Id2, HwCs2SpiCPortB1);
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hw_cs_pin!(SPIC, PA20, AltFunc1, HwChipSelectId::Id1, HwCs1SpiCPortA0);
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hw_cs_pin!(SPIC, PA19, AltFunc1, HwChipSelectId::Id2, HwCs2SpiCPortA0);
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hw_cs_pin!(SPIC, PB18, AltFunc1, HwChipSelectId::Id3, HwCs3SpiCPortA0);
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hw_cs_pin!(SPIC, PA23, AltFunc3, HwChipSelectId::Id1, HwCs1SpiCPortA1);
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hw_cs_pin!(SPIC, PA22, AltFunc3, HwChipSelectId::Id2, HwCs2SpiCPortA1);
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hw_cs_pin!(SPIC, PA21, AltFunc3, HwChipSelectId::Id3, HwCs3SpiCPortA1);
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hw_cs_pin!(SPIC, PA20, AltFunc3, HwChipSelectId::Id4, HwCs4SpiCPortA);
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//==================================================================================================
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// Config
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//==================================================================================================
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pub trait GenericTransferConfig {
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fn sod(&mut self, sod: bool);
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fn blockmode(&mut self, blockmode: bool);
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fn mode(&mut self, mode: Mode);
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fn frequency(&mut self, spi_clk: Hertz);
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fn hw_cs_id(&self) -> u8;
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}
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/// This struct contains all configuration parameter which are transfer specific
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/// and might change for transfers to different SPI slaves
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#[derive(Copy, Clone)]
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pub struct TransferConfig<HWCS> {
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pub spi_clk: Hertz,
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pub mode: Mode,
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/// This only works if the Slave Output Disable (SOD) bit of the [`SpiConfig`] is set to
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/// false
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pub hw_cs: Option<HWCS>,
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pub sod: bool,
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/// If this is enabled, all data in the FIFO is transmitted in a single frame unless
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/// the BMSTOP bit is set on a dataword. A frame is defined as CSn being active for the
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/// duration of multiple data words
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pub blockmode: bool,
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}
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/// Type erased variant of the transfer configuration. This is required to avoid generics in
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/// the SPI constructor.
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pub struct ReducedTransferConfig {
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pub spi_clk: Hertz,
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pub mode: Mode,
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pub sod: bool,
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/// If this is enabled, all data in the FIFO is transmitted in a single frame unless
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/// the BMSTOP bit is set on a dataword. A frame is defined as CSn being active for the
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/// duration of multiple data words
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pub blockmode: bool,
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pub hw_cs: HwChipSelectId,
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}
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impl TransferConfig<NoneT> {
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pub fn new_no_hw_cs(spi_clk: Hertz, mode: Mode, blockmode: bool, sod: bool) -> Self {
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TransferConfig {
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spi_clk,
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mode,
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hw_cs: None,
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sod,
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blockmode,
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}
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}
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}
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impl<HWCS: HwCs> TransferConfig<HWCS> {
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pub fn new(
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spi_clk: Hertz,
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mode: Mode,
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hw_cs: Option<HWCS>,
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blockmode: bool,
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sod: bool,
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) -> Self {
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TransferConfig {
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spi_clk,
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mode,
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hw_cs,
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sod,
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blockmode,
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}
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}
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pub fn downgrade(self) -> ReducedTransferConfig {
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ReducedTransferConfig {
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spi_clk: self.spi_clk,
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mode: self.mode,
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sod: self.sod,
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blockmode: self.blockmode,
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hw_cs: HWCS::CS_ID,
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}
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}
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}
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impl<HWCS: HwCs> GenericTransferConfig for TransferConfig<HWCS> {
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/// Slave Output Disable
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fn sod(&mut self, sod: bool) {
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self.sod = sod;
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}
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fn blockmode(&mut self, blockmode: bool) {
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self.blockmode = blockmode;
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}
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fn mode(&mut self, mode: Mode) {
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self.mode = mode;
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}
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fn frequency(&mut self, spi_clk: Hertz) {
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self.spi_clk = spi_clk;
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}
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fn hw_cs_id(&self) -> u8 {
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HWCS::CS_ID as u8
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}
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}
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#[derive(Default)]
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/// Configuration options for the whole SPI bus. See Programmer Guide p.92 for more details
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pub struct SpiConfig {
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/// Serial clock rate divider. Together with the CLKPRESCALE register, it determines
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/// the SPI clock rate in master mode. 0 by default. Specifying a higher value
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/// limits the maximum attainable SPI speed
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pub scrdv: u8,
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/// By default, configure SPI for master mode (ms == false)
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ms: bool,
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/// Slave output disable. Useful if separate GPIO pins or decoders are used for CS control
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sod: bool,
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/// Loopback mode. If you use this, don't connect MISO to MOSI, they will be tied internally
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lbm: bool,
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/// Enable Master Delayer Capture Mode. See Programmers Guide p.92 for more details
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pub mdlycap: bool,
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}
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impl SpiConfig {
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pub fn loopback(mut self, enable: bool) -> Self {
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self.lbm = enable;
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self
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}
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pub fn master_mode(mut self, master: bool) -> Self {
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self.ms = !master;
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self
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}
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pub fn slave_output_disable(mut self, sod: bool) -> Self {
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self.sod = sod;
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self
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}
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}
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//==================================================================================================
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// Word Size
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//==================================================================================================
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/// Configuration trait for the Word Size
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/// used by the SPI peripheral
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pub trait Word {
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fn word_reg() -> u8;
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}
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impl Word for u8 {
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fn word_reg() -> u8 {
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0x07
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}
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}
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impl Word for u16 {
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fn word_reg() -> u8 {
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0x0f
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}
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}
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//==================================================================================================
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// Spi
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//==================================================================================================
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pub struct SpiBase<SPI, Word = u8> {
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spi: SPI,
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cfg: SpiConfig,
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sys_clk: Hertz,
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blockmode: bool,
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_word: PhantomData<Word>,
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}
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pub struct Spi<SPI, PINS, Word = u8> {
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spi_base: SpiBase<SPI, Word>,
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pins: PINS,
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}
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// Re-export this so it can be used for the constructor
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pub use crate::typelevel::NoneT;
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macro_rules! spi {
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($($SPIX:ident: ($spix:ident, $clk_enb:path) => ($($WORD:ident),+),)+) => {
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$(
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impl<Sck: PinSck<$SPIX>, Miso: PinMiso<$SPIX>, Mosi: PinMosi<$SPIX>,
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WORD: Word> Spi<$SPIX, (Sck, Miso, Mosi), WORD>
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{
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/// Create a new SPI struct
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///
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/// You can delete the pin type information by calling the
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/// [`downgrade`](Self::downgrade) function
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///
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/// ## Arguments
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/// * `spi` - SPI bus to use
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/// * `pins` - Pins to be used for SPI transactions. These pins are consumed
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/// to ensure the pins can not be used for other purposes anymore
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/// * `spi_cfg` - Configuration specific to the SPI bus
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/// * `transfer_cfg` - Optional initial transfer configuration which includes
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/// configuration which can change across individual SPI transfers like SPI mode
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/// or SPI clock. If only one device is connected, this configuration only needs
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/// to be done once.
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/// * `syscfg` - Can be passed optionally to enable the peripheral clock
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pub fn $spix(
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spi: $SPIX,
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pins: (Sck, Miso, Mosi),
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sys_clk: impl Into<Hertz> + Copy,
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spi_cfg: SpiConfig,
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syscfg: Option<&mut SYSCONFIG>,
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transfer_cfg: Option<&ReducedTransferConfig>,
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) -> Self {
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if let Some(syscfg) = syscfg {
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enable_peripheral_clock(syscfg, $clk_enb);
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}
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let SpiConfig {
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scrdv,
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ms,
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sod,
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lbm,
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mdlycap,
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} = spi_cfg;
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let mut mode = MODE_0;
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let mut clk_prescale = 0x02;
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let mut ss = 0;
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let mut init_blockmode = false;
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if let Some(transfer_cfg) = transfer_cfg {
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mode = transfer_cfg.mode;
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clk_prescale = sys_clk.into().0 / (transfer_cfg.spi_clk.0 * (scrdv as u32 + 1));
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if transfer_cfg.hw_cs != HwChipSelectId::Invalid {
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ss = transfer_cfg.hw_cs as u8;
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}
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init_blockmode = transfer_cfg.blockmode;
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}
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let (cpo_bit, cph_bit) = match mode {
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MODE_0 => (false, false),
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MODE_1 => (false, true),
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MODE_2 => (true, false),
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MODE_3 => (true, true),
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};
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spi.ctrl0.write(|w| {
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unsafe {
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w.size().bits(WORD::word_reg());
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w.scrdv().bits(scrdv);
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// Clear clock phase and polarity. Will be set to correct value for each
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// transfer
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w.spo().bit(cpo_bit);
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w.sph().bit(cph_bit)
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}
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});
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spi.ctrl1.write(|w| {
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w.lbm().bit(lbm);
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w.sod().bit(sod);
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w.ms().bit(ms);
|
|
w.mdlycap().bit(mdlycap);
|
|
unsafe { w.ss().bits(ss) }
|
|
});
|
|
|
|
spi.fifo_clr.write(|w| {
|
|
w.rxfifo().set_bit();
|
|
w.txfifo().set_bit()
|
|
});
|
|
spi.clkprescale.write(|w| unsafe { w.bits(clk_prescale) });
|
|
// Enable the peripheral as the last step as recommended in the
|
|
// programmers guide
|
|
spi.ctrl1.modify(|_, w| w.enable().set_bit());
|
|
Spi {
|
|
spi_base: SpiBase {
|
|
spi,
|
|
cfg: spi_cfg,
|
|
sys_clk: sys_clk.into(),
|
|
blockmode: init_blockmode,
|
|
_word: PhantomData,
|
|
},
|
|
pins,
|
|
}
|
|
}
|
|
|
|
#[inline]
|
|
pub fn cfg_clock(&mut self, spi_clk: Hertz) {
|
|
self.spi_base.cfg_clock(spi_clk);
|
|
}
|
|
|
|
#[inline]
|
|
pub fn cfg_mode(&mut self, mode: Mode) {
|
|
self.spi_base.cfg_mode(mode);
|
|
}
|
|
|
|
#[inline]
|
|
pub fn perid(&self) -> u32 {
|
|
self.spi_base.perid()
|
|
}
|
|
|
|
pub fn cfg_transfer<HwCs: OptionalHwCs<$SPIX>>(&mut self, transfer_cfg: &TransferConfig<HwCs>) {
|
|
self.spi_base.cfg_transfer(transfer_cfg);
|
|
}
|
|
|
|
/// Releases the SPI peripheral and associated pins
|
|
pub fn release(self) -> ($SPIX, (Sck, Miso, Mosi), SpiConfig) {
|
|
(self.spi_base.spi, self.pins, self.spi_base.cfg)
|
|
}
|
|
|
|
pub fn downgrade(self) -> SpiBase<$SPIX, WORD> {
|
|
self.spi_base
|
|
}
|
|
}
|
|
|
|
impl<WORD: Word> SpiBase<$SPIX, WORD> {
|
|
#[inline]
|
|
pub fn cfg_clock(&mut self, spi_clk: Hertz) {
|
|
let clk_prescale = self.sys_clk.0 / (spi_clk.0 * (self.cfg.scrdv as u32 + 1));
|
|
self.spi
|
|
.clkprescale
|
|
.write(|w| unsafe { w.bits(clk_prescale) });
|
|
}
|
|
|
|
#[inline]
|
|
pub fn cfg_mode(&mut self, mode: Mode) {
|
|
let (cpo_bit, cph_bit) = match mode {
|
|
MODE_0 => (false, false),
|
|
MODE_1 => (false, true),
|
|
MODE_2 => (true, false),
|
|
MODE_3 => (true, true),
|
|
};
|
|
self.spi.ctrl0.modify(|_, w| {
|
|
w.spo().bit(cpo_bit);
|
|
w.sph().bit(cph_bit)
|
|
});
|
|
}
|
|
|
|
#[inline]
|
|
pub fn perid(&self) -> u32 {
|
|
self.spi.perid.read().bits()
|
|
}
|
|
|
|
pub fn cfg_transfer<HwCs: OptionalHwCs<$SPIX>>(&mut self, transfer_cfg: &TransferConfig<HwCs>) {
|
|
self.cfg_clock(transfer_cfg.spi_clk);
|
|
self.cfg_mode(transfer_cfg.mode);
|
|
self.blockmode = transfer_cfg.blockmode;
|
|
self.spi.ctrl1.modify(|_, w| {
|
|
if transfer_cfg.sod {
|
|
w.sod().set_bit();
|
|
} else if transfer_cfg.hw_cs.is_some() {
|
|
w.sod().clear_bit();
|
|
unsafe {
|
|
w.ss().bits(HwCs::CS_ID as u8);
|
|
}
|
|
} else {
|
|
w.sod().clear_bit();
|
|
}
|
|
if transfer_cfg.blockmode {
|
|
w.blockmode().set_bit();
|
|
} else {
|
|
w.blockmode().clear_bit();
|
|
}
|
|
w
|
|
});
|
|
}
|
|
}
|
|
|
|
/// Changing the word size also requires a type conversion
|
|
impl <Sck: PinSck<$SPIX>, Miso: PinMiso<$SPIX>, Mosi: PinMosi<$SPIX>>
|
|
From<Spi<$SPIX, (Sck, Miso, Mosi), u8>> for Spi<$SPIX, (Sck, Miso, Mosi), u16>
|
|
{
|
|
fn from(
|
|
old_spi: Spi<$SPIX, (Sck, Miso, Mosi), u8>
|
|
) -> Self {
|
|
old_spi.spi_base.spi.ctrl0.modify(|_, w| {
|
|
unsafe {
|
|
w.size().bits(WordSize::SixteenBits as u8)
|
|
}
|
|
});
|
|
Spi {
|
|
spi_base: SpiBase {
|
|
spi: old_spi.spi_base.spi,
|
|
cfg: old_spi.spi_base.cfg,
|
|
blockmode: old_spi.spi_base.blockmode,
|
|
sys_clk: old_spi.spi_base.sys_clk,
|
|
_word: PhantomData,
|
|
},
|
|
pins: old_spi.pins,
|
|
}
|
|
}
|
|
}
|
|
|
|
/// Changing the word size also requires a type conversion
|
|
impl <Sck: PinSck<$SPIX>, Miso: PinMiso<$SPIX>, Mosi: PinMosi<$SPIX>>
|
|
From<Spi<$SPIX, (Sck, Miso, Mosi), u16>> for
|
|
Spi<$SPIX, (Sck, Miso, Mosi), u8>
|
|
{
|
|
fn from(
|
|
old_spi: Spi<$SPIX, (Sck, Miso, Mosi), u16>
|
|
) -> Self {
|
|
old_spi.spi_base.spi.ctrl0.modify(|_, w| {
|
|
unsafe {
|
|
w.size().bits(WordSize::EightBits as u8)
|
|
}
|
|
});
|
|
Spi {
|
|
spi_base: SpiBase {
|
|
spi: old_spi.spi_base.spi,
|
|
cfg: old_spi.spi_base.cfg,
|
|
blockmode: old_spi.spi_base.blockmode,
|
|
sys_clk: old_spi.spi_base.sys_clk,
|
|
_word: PhantomData,
|
|
},
|
|
pins: old_spi.pins,
|
|
}
|
|
}
|
|
}
|
|
|
|
$(
|
|
|
|
impl FullDuplex<$WORD> for SpiBase<$SPIX, $WORD>
|
|
{
|
|
type Error = Infallible;
|
|
|
|
/// Sends a word to the slave
|
|
#[inline(always)]
|
|
fn send(&mut self, word: $WORD) -> nb::Result<(), Self::Error> {
|
|
if self.spi.status.read().tnf().bit_is_clear() {
|
|
return Err(nb::Error::WouldBlock);
|
|
}
|
|
self.spi.data.write(|w| unsafe { w.bits(word as u32) });
|
|
Ok(())
|
|
}
|
|
|
|
/// Read a word from the slave. Must be preceeded by a [`send`](Self::send) call
|
|
#[inline(always)]
|
|
fn read(&mut self) -> nb::Result<$WORD, Self::Error> {
|
|
if self.spi.status.read().rne().bit_is_clear() {
|
|
return Err(nb::Error::WouldBlock);
|
|
}
|
|
Ok((self.spi.data.read().bits() & 0xffff) as $WORD)
|
|
}
|
|
}
|
|
|
|
impl<Sck: PinSck<$SPIX>, Miso: PinMiso<$SPIX>, Mosi: PinMosi<$SPIX>>
|
|
FullDuplex<$WORD> for Spi<$SPIX, (Sck, Miso, Mosi), $WORD>
|
|
{
|
|
type Error = Infallible;
|
|
|
|
#[inline(always)]
|
|
fn read(&mut self) -> nb::Result<$WORD, Self::Error> {
|
|
self.spi_base.read()
|
|
}
|
|
|
|
#[inline(always)]
|
|
fn send(&mut self, word: $WORD) -> nb::Result<(), Self::Error> {
|
|
self.spi_base.send(word)
|
|
}
|
|
}
|
|
|
|
impl SpiBase<$SPIX, $WORD>
|
|
where SpiBase<$SPIX, $WORD>: FullDuplex<$WORD>
|
|
{
|
|
/// Internal implementation for blocking::spi::Transfer and
|
|
/// blocking::spi::Write using the FIFO
|
|
fn transfer_internal<'w>(
|
|
&mut self,
|
|
write_words: &'w [$WORD],
|
|
read_words: Option<&'w mut [$WORD]>,
|
|
) -> Result<(), Infallible> {
|
|
// FIFO has a depth of 16.
|
|
const FILL_DEPTH: usize = 12;
|
|
|
|
if self.blockmode {
|
|
self.spi.ctrl1.modify(|_, w| {
|
|
w.mtxpause().set_bit()
|
|
})
|
|
}
|
|
// Fill the first half of the write FIFO
|
|
let len = write_words.len();
|
|
let mut write = write_words.iter();
|
|
for _ in 0..core::cmp::min(FILL_DEPTH, len) {
|
|
nb::block!(self.send(*write.next().unwrap())).ok().unwrap();
|
|
}
|
|
if self.blockmode {
|
|
self.spi.ctrl1.modify(|_, w| {
|
|
w.mtxpause().clear_bit()
|
|
})
|
|
}
|
|
if let Some(read) = read_words {
|
|
let mut read = read.iter_mut();
|
|
|
|
// Continue filling write FIFO and emptying read FIFO
|
|
for word in write {
|
|
nb::block!(self.send(*word)).ok().unwrap();
|
|
*read.next().unwrap() = nb::block!(self.read()).ok().unwrap();
|
|
}
|
|
|
|
// Finish emptying the read FIFO
|
|
for word in read {
|
|
*word = nb::block!(self.read()).ok().unwrap();
|
|
}
|
|
} else {
|
|
// Continue filling write FIFO and emptying read FIFO
|
|
for word in write {
|
|
nb::block!(self.send(*word)).ok().unwrap();
|
|
let _ = nb::block!(self.read()).ok().unwrap();
|
|
}
|
|
|
|
// Dummy read from the read FIFO
|
|
for _ in 0..core::cmp::min(FILL_DEPTH, len) {
|
|
let _ = nb::block!(self.read()).ok().unwrap();
|
|
}
|
|
}
|
|
Ok(())
|
|
}
|
|
}
|
|
|
|
impl<Sck: PinSck<$SPIX>, Miso: PinMiso<$SPIX>, Mosi: PinMosi<$SPIX>>
|
|
Spi<$SPIX, (Sck, Miso, Mosi), $WORD>
|
|
where Spi<$SPIX, (Sck, Miso, Mosi), $WORD>: FullDuplex<$WORD>
|
|
{
|
|
/// Internal implementation for blocking::spi::Transfer and
|
|
/// blocking::spi::Write using the FIFO
|
|
fn transfer_internal<'w>(
|
|
&mut self,
|
|
write_words: &'w [$WORD],
|
|
read_words: Option<&'w mut [$WORD]>,
|
|
) -> Result<(), Infallible> {
|
|
return self.spi_base.transfer_internal(write_words, read_words)
|
|
}
|
|
}
|
|
|
|
impl blocking::spi::Transfer<$WORD> for SpiBase<$SPIX, $WORD>
|
|
where
|
|
SpiBase<$SPIX, $WORD>: FullDuplex<$WORD>
|
|
{
|
|
type Error = Infallible;
|
|
|
|
fn transfer<'w>(
|
|
&mut self,
|
|
words: &'w mut [$WORD]
|
|
) -> Result<&'w [$WORD], Self::Error> {
|
|
if words.is_empty() {
|
|
return Ok(words);
|
|
}
|
|
// SAFETY: transfer_internal always writes out bytes
|
|
// before modifying them
|
|
let write = unsafe {
|
|
core::slice::from_raw_parts(words.as_ptr(), words.len())
|
|
};
|
|
self.transfer_internal(write, Some(words))?;
|
|
Ok(words)
|
|
}
|
|
}
|
|
|
|
impl<Sck: PinSck<$SPIX>, Miso: PinMiso<$SPIX>, Mosi: PinMosi<$SPIX>>
|
|
blocking::spi::Transfer<$WORD> for Spi<$SPIX, (Sck, Miso, Mosi), $WORD>
|
|
where
|
|
Spi<$SPIX, (Sck, Miso, Mosi), $WORD>: FullDuplex<$WORD>,
|
|
{
|
|
type Error = Infallible;
|
|
|
|
fn transfer<'w>(
|
|
&mut self,
|
|
words: &'w mut [$WORD]
|
|
) -> Result<&'w [$WORD], Self::Error> {
|
|
self.spi_base.transfer(words)
|
|
}
|
|
}
|
|
|
|
impl blocking::spi::Write<$WORD> for SpiBase<$SPIX, $WORD>
|
|
where
|
|
SpiBase<$SPIX, $WORD>: FullDuplex<$WORD>
|
|
{
|
|
type Error = Infallible;
|
|
fn write(&mut self, words: &[$WORD]) -> Result<(), Self::Error> {
|
|
self.transfer_internal(words, None)
|
|
}
|
|
}
|
|
|
|
impl<Sck: PinSck<$SPIX>, Miso: PinMiso<$SPIX>, Mosi: PinMosi<$SPIX>>
|
|
blocking::spi::Write<$WORD> for Spi<$SPIX, (Sck, Miso, Mosi), $WORD>
|
|
where
|
|
Spi<$SPIX, (Sck, Miso, Mosi), $WORD>: FullDuplex<$WORD>,
|
|
{
|
|
type Error = Infallible;
|
|
fn write(&mut self, words: &[$WORD]) -> Result<(), Self::Error> {
|
|
self.transfer_internal(words, None)
|
|
}
|
|
}
|
|
)+
|
|
|
|
)+
|
|
}
|
|
}
|
|
|
|
spi!(
|
|
SPIA: (spia, PeripheralClocks::Spi0) => (u8, u16),
|
|
SPIB: (spib, PeripheralClocks::Spi1) => (u8, u16),
|
|
SPIC: (spic, PeripheralClocks::Spi2) => (u8, u16),
|
|
);
|