Robin Mueller
f376a43f41
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Rust/va108xx-hal/pipeline/head There was a failure building this commit
- Improved IRQ handling, which makes most unsafe unmask operations in user code absolete - Add first UART RX handlers which use an IRQ
117 lines
3.5 KiB
Rust
117 lines
3.5 KiB
Rust
//! MS and Second counter implemented using the TIM0 and TIM1 peripheral
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#![no_main]
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#![no_std]
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use core::cell::Cell;
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use cortex_m::interrupt::Mutex;
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use cortex_m_rt::entry;
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use panic_rtt_target as _;
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use rtt_target::{rprintln, rtt_init_print};
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use va108xx_hal::{
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clock::{get_sys_clock, set_sys_clock},
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pac::{self, interrupt},
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prelude::*,
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time::Hertz,
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timer::{default_ms_irq_handler, set_up_ms_timer, CountDownTimer, Event, IrqCfg, MS_COUNTER},
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};
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#[allow(dead_code)]
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enum LibType {
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Pac,
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Hal,
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}
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static SEC_COUNTER: Mutex<Cell<u32>> = Mutex::new(Cell::new(0));
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#[entry]
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fn main() -> ! {
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rtt_init_print!();
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let mut dp = pac::Peripherals::take().unwrap();
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let mut last_ms = 0;
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rprintln!("-- Vorago system ticks using timers --");
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set_sys_clock(50.mhz());
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let lib_type = LibType::Hal;
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match lib_type {
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LibType::Pac => {
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unsafe {
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dp.SYSCONFIG
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.peripheral_clk_enable
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.modify(|_, w| w.irqsel().set_bit());
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dp.SYSCONFIG
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.tim_clk_enable
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.modify(|r, w| w.bits(r.bits() | (1 << 0) | (1 << 1)));
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dp.IRQSEL.tim[0].write(|w| w.bits(0x00));
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dp.IRQSEL.tim[1].write(|w| w.bits(0x01));
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}
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let sys_clk: Hertz = 50.mhz().into();
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let cnt_ms = sys_clk.0 / 1000 - 1;
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let cnt_sec = sys_clk.0 - 1;
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unsafe {
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dp.TIM0.cnt_value.write(|w| w.bits(cnt_ms));
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dp.TIM0.rst_value.write(|w| w.bits(cnt_ms));
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dp.TIM0.ctrl.write(|w| {
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w.enable().set_bit();
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w.irq_enb().set_bit()
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});
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dp.TIM1.cnt_value.write(|w| w.bits(cnt_sec));
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dp.TIM1.rst_value.write(|w| w.bits(cnt_sec));
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dp.TIM1.ctrl.write(|w| {
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w.enable().set_bit();
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w.irq_enb().set_bit()
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});
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unmask_irqs();
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}
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}
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LibType::Hal => {
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set_up_ms_timer(
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IrqCfg::new(interrupt::OC0, true, true),
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&mut dp.SYSCONFIG,
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Some(&mut dp.IRQSEL),
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50.mhz(),
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dp.TIM0,
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);
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let mut second_timer =
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CountDownTimer::new(&mut dp.SYSCONFIG, get_sys_clock().unwrap(), dp.TIM1);
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second_timer.listen(
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Event::TimeOut,
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IrqCfg::new(interrupt::OC1, true, true),
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Some(&mut dp.IRQSEL),
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Some(&mut dp.SYSCONFIG),
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);
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second_timer.start(1.hz());
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}
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}
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loop {
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let current_ms = cortex_m::interrupt::free(|cs| MS_COUNTER.borrow(cs).get());
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if current_ms - last_ms >= 1000 {
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last_ms = current_ms;
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rprintln!("MS counter: {}", current_ms);
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let second = cortex_m::interrupt::free(|cs| SEC_COUNTER.borrow(cs).get());
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rprintln!("Second counter: {}", second);
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}
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cortex_m::asm::delay(10000);
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}
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}
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fn unmask_irqs() {
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unsafe {
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cortex_m::peripheral::NVIC::unmask(pac::Interrupt::OC0);
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cortex_m::peripheral::NVIC::unmask(pac::Interrupt::OC1);
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}
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}
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#[interrupt]
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fn OC0() {
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default_ms_irq_handler()
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}
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#[interrupt]
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fn OC1() {
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cortex_m::interrupt::free(|cs| {
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let mut sec = SEC_COUNTER.borrow(cs).get();
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sec += 1;
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SEC_COUNTER.borrow(cs).set(sec);
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});
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}
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