277 lines
11 KiB
Plaintext
277 lines
11 KiB
Plaintext
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// pub mod gpioa {
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// use core::marker::PhantomData;
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// use core::convert::Infallible;
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// use cortex_m::interrupt::CriticalSection;
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// use super::{
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// FUNSEL1, FUNSEL2, FUNSEL3, Floating, Funsel, GpioExt, Input, OpenDrain,
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// PullUp, Output, FilterType, FilterClkSel, Pin, GpioRegExt, PushPull
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// };
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// use crate::{pac::PORTA, pac::SYSCONFIG, pac::IOCONFIG};
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// use embedded_hal::digital::v2::{InputPin, OutputPin, StatefulOutputPin, toggleable};
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// pub struct Parts {
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// pub pa0: PA0<Input<Floating>>
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// }
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// impl GpioExt for PORTA {
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// type Parts = Parts;
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// fn split(self, syscfg: &mut SYSCONFIG) -> Parts {
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// syscfg.peripheral_clk_enable.modify(|_, w| {
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// w.porta().set_bit();
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// w.gpio().set_bit();
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// w.ioconfig().set_bit();
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// w
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// });
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// Parts {
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// pa0: PA0 { _mode: PhantomData }
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// }
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// }
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// }
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// fn _set_alternate_mode(index: usize, mode: u8) {
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// unsafe {
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// let reg = &(*IOCONFIG::ptr());
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// reg.porta[index].modify(|_, w| {
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// w.funsel().bits(mode)
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// })
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// }
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// }
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// pub struct PA0<MODE> {
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// _mode: PhantomData<MODE>,
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// }
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// impl<MODE> PA0<MODE> {
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// pub fn into_funsel_1(self, _cs: &CriticalSection) -> PA0<Funsel<FUNSEL1>> {
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// _set_alternate_mode(0, 1);
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// PA0 { _mode: PhantomData }
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// }
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// pub fn into_funsel_2(self, _cs: &CriticalSection) -> PA0<Funsel<FUNSEL2>> {
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// _set_alternate_mode(0, 2);
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// PA0 { _mode: PhantomData }
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// }
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// pub fn into_funsel_3(self, _cs: &CriticalSection) -> PA0<Funsel<FUNSEL3>> {
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// _set_alternate_mode(0, 3);
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// PA0 { _mode: PhantomData }
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// }
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// pub fn into_floating_input(self, _cs: &CriticalSection) -> PA0<Input<Floating>> {
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// unsafe {
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// let reg = &(*IOCONFIG::ptr());
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// reg.porta[0].modify(|_, w| {
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// w.funsel().bits(0);
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// w.pen().clear_bit();
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// w.opendrn().clear_bit()
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// });
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// let port_reg = &(*PORTA::ptr());
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// port_reg.dir().modify(|r,w| w.bits(r.bits() & !(1 << 0)));
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// }
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// PA0 { _mode: PhantomData }
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// }
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// pub fn into_pull_up_input(self, _cs: &CriticalSection) -> PA0<Input<PullUp>> {
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// unsafe {
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// let reg = &(*IOCONFIG::ptr());
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// reg.porta[0].modify(|_, w| {
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// w.funsel().bits(0);
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// w.pen().set_bit();
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// w.plevel().set_bit();
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// w.opendrn().clear_bit()
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// });
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// let port_reg = &(*PORTA::ptr());
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// port_reg.dir().modify(|r,w| w.bits(r.bits() & !(1 << 0)));
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// }
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// PA0 { _mode: PhantomData }
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// }
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// pub fn into_pull_down_input(self, _cs: &CriticalSection) -> PA0<Input<PullUp>> {
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// unsafe {
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// let reg = &(*IOCONFIG::ptr());
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// reg.porta[0].modify(|_, w| {
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// w.funsel().bits(0);
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// w.pen().set_bit();
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// w.plevel().clear_bit();
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// w.opendrn().clear_bit()
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// });
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// let port_reg = &(*PORTA::ptr());
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// port_reg.dir().modify(|r,w| w.bits(r.bits() & !(1 << 0)));
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// }
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// PA0 { _mode: PhantomData }
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// }
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// pub fn into_open_drain_output(self, _cs: &CriticalSection) -> PA0<Output<OpenDrain>> {
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// unsafe {
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// let reg = &(*IOCONFIG::ptr());
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// reg.porta[0].modify(|_, w| {
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// w.funsel().bits(0);
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// w.pen().clear_bit();
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// w.opendrn().set_bit()
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// });
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// let port_reg = &(*PORTA::ptr());
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// port_reg.dir().modify(|r,w| w.bits(r.bits() | (1 << 0)));
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// }
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// let pa0: PA0<Output<OpenDrain>> = PA0 { _mode: PhantomData };
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// // Enable input functionality by default to ensure this is a stateful output pin
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// let pa0 = pa0.enable_input(_cs, true);
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// pa0
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// }
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// pub fn into_push_pull_output(self, _cs: &CriticalSection) -> PA0<Output<PushPull>> {
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// unsafe {
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// let reg = &(*IOCONFIG::ptr());
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// reg.porta[0].modify(|_, w| {
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// w.funsel().bits(0);
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// w.opendrn().clear_bit()
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// });
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// let port_reg = &(*PORTA::ptr());
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// port_reg.dir().modify(|r,w| w.bits(r.bits() | (1 << 0)));
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// }
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// let pa0: PA0<Output<PushPull>> = PA0 { _mode: PhantomData };
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// // Enable input functionality by default to ensure this is a stateful output pin
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// let pa0 = pa0.enable_input(_cs, true);
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// pa0
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// }
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// pub fn filter_type(self, _cs: &CriticalSection, filter: FilterType, clksel: FilterClkSel) -> Self {
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// unsafe {
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// let reg = &(*IOCONFIG::ptr());
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// reg.porta[0].modify(|_, w| {
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// w.flttype().bits(filter as u8);
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// w.fltclk().bits(clksel as u8)
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// })
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// }
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// self
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// }
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// }
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// impl<MODE> PA0<Input<MODE>> {
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// pub fn input_inversion(self, _cs: &CriticalSection, enable: bool) -> Self {
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// unsafe {
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// let reg = &(*IOCONFIG::ptr());
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// if enable {
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// reg.porta[0].modify(|_, w| w.invinp().set_bit());
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// } else {
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// reg.porta[0].modify(|_, w| w.invinp().clear_bit());
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// }
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// }
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// self
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// }
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// }
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// impl<MODE> PA0<Output<MODE>> {
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// pub fn output_inversion(self, _cs: &CriticalSection, enable: bool) -> Self {
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// unsafe {
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// let reg = &(*IOCONFIG::ptr());
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// if enable {
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// reg.porta[0].modify(|_, w| w.invout().set_bit());
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// } else {
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// reg.porta[0].modify(|_, w| w.invout().clear_bit());
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// }
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// }
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// self
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// }
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// /// Enable Input even when in output mode. In
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// /// this mode the input receiver is enabled even
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// /// if the direction is configured as an output.
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// /// This allows monitoring of output values
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// pub fn enable_input(self, _cs: &CriticalSection, enable: bool) -> Self {
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// unsafe {
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// let reg = &(*IOCONFIG::ptr());
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// if enable {
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// reg.porta[0].modify(|_, w| w.iewo().set_bit());
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// } else {
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// reg.porta[0].modify(|_, w| w.iewo().clear_bit());
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// }
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// }
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// self
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// }
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// /// Enable Pull up/down even when output is active. The Default is to disable pull
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// /// up/down when output is actively driven. This bit enables the pull up/down all the time.
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// ///
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// /// # Arguments
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// ///
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// /// `enable` - Enable the peripheral functionality
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// /// `enable_pullup` - Enable the pullup itself
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// pub fn enable_pull_up(self, _cs: &CriticalSection, enable: bool, enable_pullup: bool) -> Self {
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// unsafe {
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// let reg = &(*IOCONFIG::ptr());
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// reg.porta[0].modify(|_, w| {
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// if enable { w.pwoa().set_bit(); } else { w.pwoa().clear_bit(); }
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// if enable_pullup { w.pen().set_bit(); } else { w.pen().clear_bit(); }
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// w.plevel().set_bit()
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// });
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// }
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// self
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// }
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// /// Enable Pull up/down even when output is active. The Default is to disable pull
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// /// up/down when output is actively driven. This bit enables the pull up/down all the time.
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// ///
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// /// # Arguments
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// ///
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// /// `enable` - Enable the peripheral functionality
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// /// `enable_pullup` - Enable the pulldown itself
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// pub fn enable_pull_down(self, _cs: &CriticalSection, enable: bool, enable_pulldown: bool) -> Self {
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// unsafe {
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// let reg = &(*IOCONFIG::ptr());
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// reg.porta[0].modify(|_, w| {
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// if enable { w.pwoa().set_bit(); } else { w.pwoa().clear_bit(); }
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// if enable_pulldown { w.pen().set_bit(); } else { w.pen().clear_bit(); }
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// w.plevel().clear_bit()
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// });
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// }
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// self
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// }
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// }
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// impl<MODE> PA0<Output<MODE>> {
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// /// Erases the pin number from the type
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// ///
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// /// This is useful when you want to collect the pins into an array where you
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// /// need all the elements to have the same type
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// pub fn downgrade(self) -> Pin<Output<MODE>> {
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// Pin {
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// i: 0,
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// port: PORTA::ptr() as *const dyn GpioRegExt,
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// _mode: self._mode,
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// }
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// }
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// }
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// impl<MODE> StatefulOutputPin for PA0<Output<MODE>> {
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// fn is_set_high(&self) -> Result<bool, Self::Error> {
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// self.is_set_low().map(|v| !v)
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// }
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// fn is_set_low(&self) -> Result<bool, Self::Error> {
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// Ok(unsafe { (*PORTA::ptr()).is_set_low(0) })
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// }
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// }
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// impl<MODE> OutputPin for PA0<Output<MODE>> {
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// type Error = Infallible;
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// fn set_high(&mut self) -> Result<(), Self::Error> {
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// Ok(unsafe { (*PORTA::ptr()).set_high(0) })
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// }
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// fn set_low(&mut self) -> Result<(), Self::Error> {
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// Ok(unsafe { (*PORTA::ptr()).set_low(0) })
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// }
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// }
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// impl<MODE> toggleable::Default for PA0<Output<MODE>> {}
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// impl<MODE> PA0<Input<MODE>> {
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// /// Erases the pin number from the type
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// ///
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// /// This is useful when you want to collect the pins into an array where you
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// /// need all the elements to have the same type
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// pub fn downgrade(self) -> Pin<Input<MODE>> {
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// Pin {
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// i: 0,
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// port: PORTA::ptr() as *const dyn GpioRegExt,
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// _mode: self._mode,
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// }
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// }
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// }
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// impl<MODE> InputPin for PA0<Input<MODE>> {
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// type Error = Infallible;
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// fn is_high(&self) -> Result<bool, Self::Error> {
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// self.is_low().map(|v| !v)
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// }
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// fn is_low(&self) -> Result<bool, Self::Error> {
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// Ok(unsafe { (*PORTA::ptr()).is_low(0) })
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// }
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// }
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// }
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