224 lines
12 KiB
Rust
224 lines
12 KiB
Rust
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#[repr(C)]
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#[doc = "Register block"]
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pub struct RegisterBlock {
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data: Data,
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enable: Enable,
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ctrl: Ctrl,
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clkscale: Clkscale,
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rxstatus: Rxstatus,
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txstatus: Txstatus,
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fifo_clr: FifoClr,
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txbreak: Txbreak,
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addr9: Addr9,
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addr9mask: Addr9mask,
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irq_enb: IrqEnb,
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irq_raw: IrqRaw,
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irq_end: IrqEnd,
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irq_clr: IrqClr,
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rxfifoirqtrg: Rxfifoirqtrg,
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txfifoirqtrg: Txfifoirqtrg,
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rxfifortstrg: Rxfifortstrg,
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state: State,
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_reserved18: [u8; 0x0fb4],
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perid: Perid,
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}
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impl RegisterBlock {
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#[doc = "0x00 - Data In/Out Register"]
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#[inline(always)]
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pub const fn data(&self) -> &Data {
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&self.data
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}
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#[doc = "0x04 - Enable Register"]
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#[inline(always)]
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pub const fn enable(&self) -> &Enable {
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&self.enable
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}
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#[doc = "0x08 - Control Register"]
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#[inline(always)]
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pub const fn ctrl(&self) -> &Ctrl {
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&self.ctrl
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}
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#[doc = "0x0c - Clock Scale Register"]
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#[inline(always)]
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pub const fn clkscale(&self) -> &Clkscale {
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&self.clkscale
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}
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#[doc = "0x10 - Status Register"]
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#[inline(always)]
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pub const fn rxstatus(&self) -> &Rxstatus {
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&self.rxstatus
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}
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#[doc = "0x14 - Status Register"]
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#[inline(always)]
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pub const fn txstatus(&self) -> &Txstatus {
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&self.txstatus
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}
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#[doc = "0x18 - Clear FIFO Register"]
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#[inline(always)]
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pub const fn fifo_clr(&self) -> &FifoClr {
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&self.fifo_clr
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}
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#[doc = "0x1c - Break Transmit Register"]
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#[inline(always)]
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pub const fn txbreak(&self) -> &Txbreak {
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&self.txbreak
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}
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#[doc = "0x20 - Address9 Register"]
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#[inline(always)]
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pub const fn addr9(&self) -> &Addr9 {
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&self.addr9
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}
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#[doc = "0x24 - Address9 Mask Register"]
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#[inline(always)]
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pub const fn addr9mask(&self) -> &Addr9mask {
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&self.addr9mask
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}
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#[doc = "0x28 - IRQ Enable Register"]
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#[inline(always)]
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pub const fn irq_enb(&self) -> &IrqEnb {
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&self.irq_enb
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}
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#[doc = "0x2c - IRQ Raw Status Register"]
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#[inline(always)]
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pub const fn irq_raw(&self) -> &IrqRaw {
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&self.irq_raw
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}
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#[doc = "0x30 - IRQ Enabled Status Register"]
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#[inline(always)]
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pub const fn irq_end(&self) -> &IrqEnd {
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&self.irq_end
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}
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#[doc = "0x34 - IRQ Clear Status Register"]
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#[inline(always)]
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pub const fn irq_clr(&self) -> &IrqClr {
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&self.irq_clr
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}
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#[doc = "0x38 - Rx FIFO IRQ Trigger Level"]
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#[inline(always)]
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pub const fn rxfifoirqtrg(&self) -> &Rxfifoirqtrg {
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&self.rxfifoirqtrg
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}
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#[doc = "0x3c - Tx FIFO IRQ Trigger Level"]
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#[inline(always)]
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pub const fn txfifoirqtrg(&self) -> &Txfifoirqtrg {
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&self.txfifoirqtrg
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}
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#[doc = "0x40 - Rx FIFO RTS Trigger Level"]
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#[inline(always)]
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pub const fn rxfifortstrg(&self) -> &Rxfifortstrg {
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&self.rxfifortstrg
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}
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#[doc = "0x44 - Internal STATE of UART Controller"]
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#[inline(always)]
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pub const fn state(&self) -> &State {
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&self.state
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}
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#[doc = "0xffc - Peripheral ID Register"]
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#[inline(always)]
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pub const fn perid(&self) -> &Perid {
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&self.perid
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}
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}
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#[doc = "DATA (rw) register accessor: Data In/Out Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data`]
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module"]
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#[doc(alias = "DATA")]
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pub type Data = crate::Reg<data::DataSpec>;
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#[doc = "Data In/Out Register"]
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pub mod data;
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#[doc = "ENABLE (rw) register accessor: Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enable`]
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module"]
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#[doc(alias = "ENABLE")]
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pub type Enable = crate::Reg<enable::EnableSpec>;
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#[doc = "Enable Register"]
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pub mod enable;
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#[doc = "CTRL (rw) register accessor: Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl`]
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module"]
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#[doc(alias = "CTRL")]
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pub type Ctrl = crate::Reg<ctrl::CtrlSpec>;
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#[doc = "Control Register"]
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pub mod ctrl;
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#[doc = "CLKSCALE (rw) register accessor: Clock Scale Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkscale::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkscale::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clkscale`]
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module"]
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#[doc(alias = "CLKSCALE")]
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pub type Clkscale = crate::Reg<clkscale::ClkscaleSpec>;
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#[doc = "Clock Scale Register"]
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pub mod clkscale;
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#[doc = "RXSTATUS (r) register accessor: Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxstatus::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxstatus`]
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module"]
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#[doc(alias = "RXSTATUS")]
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pub type Rxstatus = crate::Reg<rxstatus::RxstatusSpec>;
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#[doc = "Status Register"]
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pub mod rxstatus;
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#[doc = "TXSTATUS (r) register accessor: Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txstatus::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txstatus`]
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module"]
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#[doc(alias = "TXSTATUS")]
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pub type Txstatus = crate::Reg<txstatus::TxstatusSpec>;
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#[doc = "Status Register"]
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pub mod txstatus;
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#[doc = "FIFO_CLR (w) register accessor: Clear FIFO Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifo_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifo_clr`]
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module"]
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#[doc(alias = "FIFO_CLR")]
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pub type FifoClr = crate::Reg<fifo_clr::FifoClrSpec>;
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#[doc = "Clear FIFO Register"]
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pub mod fifo_clr;
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#[doc = "TXBREAK (w) register accessor: Break Transmit Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txbreak::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txbreak`]
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module"]
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#[doc(alias = "TXBREAK")]
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pub type Txbreak = crate::Reg<txbreak::TxbreakSpec>;
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#[doc = "Break Transmit Register"]
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pub mod txbreak;
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#[doc = "ADDR9 (rw) register accessor: Address9 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`addr9::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`addr9::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@addr9`]
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module"]
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#[doc(alias = "ADDR9")]
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pub type Addr9 = crate::Reg<addr9::Addr9Spec>;
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#[doc = "Address9 Register"]
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pub mod addr9;
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#[doc = "ADDR9MASK (rw) register accessor: Address9 Mask Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`addr9mask::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`addr9mask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@addr9mask`]
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module"]
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#[doc(alias = "ADDR9MASK")]
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pub type Addr9mask = crate::Reg<addr9mask::Addr9maskSpec>;
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#[doc = "Address9 Mask Register"]
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pub mod addr9mask;
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#[doc = "IRQ_ENB (rw) register accessor: IRQ Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_enb::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_enb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_enb`]
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module"]
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#[doc(alias = "IRQ_ENB")]
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pub type IrqEnb = crate::Reg<irq_enb::IrqEnbSpec>;
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#[doc = "IRQ Enable Register"]
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pub mod irq_enb;
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pub use irq_enb as irq_raw;
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pub use irq_enb as irq_end;
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pub use irq_enb as irq_clr;
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pub use IrqEnb as IrqRaw;
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pub use IrqEnb as IrqEnd;
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pub use IrqEnb as IrqClr;
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#[doc = "RXFIFOIRQTRG (rw) register accessor: Rx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxfifoirqtrg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxfifoirqtrg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxfifoirqtrg`]
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module"]
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#[doc(alias = "RXFIFOIRQTRG")]
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pub type Rxfifoirqtrg = crate::Reg<rxfifoirqtrg::RxfifoirqtrgSpec>;
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#[doc = "Rx FIFO IRQ Trigger Level"]
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pub mod rxfifoirqtrg;
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#[doc = "TXFIFOIRQTRG (rw) register accessor: Tx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txfifoirqtrg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txfifoirqtrg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txfifoirqtrg`]
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module"]
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#[doc(alias = "TXFIFOIRQTRG")]
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pub type Txfifoirqtrg = crate::Reg<txfifoirqtrg::TxfifoirqtrgSpec>;
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#[doc = "Tx FIFO IRQ Trigger Level"]
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pub mod txfifoirqtrg;
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#[doc = "RXFIFORTSTRG (rw) register accessor: Rx FIFO RTS Trigger Level\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxfifortstrg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxfifortstrg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxfifortstrg`]
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module"]
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#[doc(alias = "RXFIFORTSTRG")]
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pub type Rxfifortstrg = crate::Reg<rxfifortstrg::RxfifortstrgSpec>;
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#[doc = "Rx FIFO RTS Trigger Level"]
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pub mod rxfifortstrg;
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#[doc = "STATE (r) register accessor: Internal STATE of UART Controller\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`state::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@state`]
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module"]
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#[doc(alias = "STATE")]
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pub type State = crate::Reg<state::StateSpec>;
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#[doc = "Internal STATE of UART Controller"]
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pub mod state;
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#[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`perid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`]
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module"]
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#[doc(alias = "PERID")]
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pub type Perid = crate::Reg<perid::PeridSpec>;
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#[doc = "Peripheral ID Register"]
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pub mod perid;
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