diff --git a/bootloader/src/main.rs b/bootloader/src/main.rs
index 70e287b..a185d39 100644
--- a/bootloader/src/main.rs
+++ b/bootloader/src/main.rs
@@ -15,7 +15,7 @@ use vorago_reb1::m95m01::M95M01;
 // Useful for debugging and see what the bootloader is doing. Enabled currently, because
 // the binary stays small enough.
 const RTT_PRINTOUT: bool = true;
-const DEBUG_PRINTOUTS: bool = false;
+const DEBUG_PRINTOUTS: bool = true;
 
 // Dangerous option! An image with this option set to true will flash itself from RAM directly
 // into the NVM. This can be used as a recovery option from a direct RAM flash to fix the NVM
@@ -47,7 +47,7 @@ const APP_A_SIZE_ADDR: u32 = APP_A_END_ADDR - 8;
 // 0x117FC
 const APP_A_CRC_ADDR: u32 = APP_A_END_ADDR - 4;
 // 0x11800
-pub const APP_A_END_ADDR: u32 = APP_B_END_ADDR - BOOTLOADER_END_ADDR / 2;
+pub const APP_A_END_ADDR: u32 = APP_A_START_ADDR + APP_IMG_SZ;
 // The actual size of the image which is relevant for CRC calculation.
 const APP_B_START_ADDR: u32 = APP_A_END_ADDR;
 // The actual size of the image which is relevant for CRC calculation.
@@ -100,6 +100,10 @@ fn main() -> ! {
     let mut dp = pac::Peripherals::take().unwrap();
     let cp = cortex_m::Peripherals::take().unwrap();
 
+    let vect_tbl = unsafe {
+        core::slice::from_raw_parts(APP_A_START_ADDR as *const u8, VECTOR_TABLE_LEN as usize)
+    };
+    rprintln!("vector table app A: 0x{:x?}", &vect_tbl[0..32]);
     let mut nvm = M95M01::new(&mut dp.sysconfig, CLOCK_FREQ, dp.spic);
 
     if FLASH_SELF {
@@ -253,24 +257,27 @@ fn boot_app(syscfg: &pac::Sysconfig, cp: &cortex_m::Peripherals, app_sel: AppSel
     if DEBUG_PRINTOUTS && RTT_PRINTOUT {
         rprintln!("booting app {:?}", app_sel);
     }
+    // Clear all interrupts set.
+    unsafe {
+        cp.NVIC.icer[0].write(0xFFFFFFFF);
+        cp.NVIC.icpr[0].write(0xFFFFFFFF);
+    }
     // Disable ROM protection.
-    syscfg.rom_prot().write(|w| unsafe { w.bits(1) });
+    syscfg.rom_prot().write(|w| w.wren().set_bit());
     let base_addr = if app_sel == AppSel::A {
         APP_A_START_ADDR
     } else {
         APP_B_START_ADDR
     };
-    // Clear all interrupts set.
     unsafe {
-        cp.NVIC.icer[0].write(0xFFFFFFFF);
-        cp.NVIC.icpr[0].write(0xFFFFFFFF);
-
         // First 4 bytes done with inline assembly, writing to the physical address 0x0 can not
         // be done without it. See https://users.rust-lang.org/t/reading-from-physical-address-0x0/117408/2.
-        core::ptr::read(base_addr as *const u32);
+        //let first_four_bytes = core::ptr::read(base_addr as *const u32);
         core::arch::asm!(
-            "str {0}, [{1}]",    // Load 4 bytes from src into r0 register
-            in(reg)  base_addr,  // Input: App vector table.
+            "ldr r0, [{0}]",    // Load 4 bytes from src into r0 register
+            "str r0, [{1}]",    // Store r0 register into first_four_bytes
+            //"str {0}, [{1}]",
+            in(reg)  base_addr as *const u32,  // Input: App vector table.
             in(reg) BOOTLOADER_START_ADDR as *mut u32,  // Input: destination pointer
         );
         core::slice::from_raw_parts_mut(
@@ -282,10 +289,11 @@ fn boot_app(syscfg: &pac::Sysconfig, cp: &cortex_m::Peripherals, app_sel: AppSel
             (VECTOR_TABLE_LEN - 4) as usize,
         ));
     }
-    /* Disable re-loading from FRAM/code ROM on soft reset */
+    // Disable re-loading from FRAM/code ROM on soft reset
     syscfg
         .rst_cntl_rom()
         .modify(|_, w| w.sysrstreq().clear_bit());
+
     soft_reset(cp);
 }
 
diff --git a/flashloader/image-loader.py b/flashloader/image-loader.py
index ee3178d..bd5eaf1 100755
--- a/flashloader/image-loader.py
+++ b/flashloader/image-loader.py
@@ -328,6 +328,7 @@ def create_loadable_segments(
                 continue
             # Basic validity checks of the base addresses.
             if idx == 0:
+                _LOGGER.debug("data in 0: ", segment.data().hex(sep=','))
                 if (
                     target == Target.BOOTLOADER
                     and segment.header.p_paddr != BOOTLOADER_START_ADDR
diff --git a/flashloader/slot-a-blinky/memory.x b/flashloader/slot-a-blinky/memory.x
index e462ed6..f64b2c6 100644
--- a/flashloader/slot-a-blinky/memory.x
+++ b/flashloader/slot-a-blinky/memory.x
@@ -1,7 +1,7 @@
 /* Special linker script for application slot A with an offset at address 0x3000 */
 MEMORY
 {
-	FLASH : ORIGIN = 0x00003000, LENGTH = 0x20000 /* 128K */
+	FLASH : ORIGIN = 0x00003000, LENGTH = 0xE800
 	RAM : ORIGIN = 0x10000000, LENGTH = 0x08000 /* 32K */
 }
 
diff --git a/flashloader/slot-b-blinky/memory.x b/flashloader/slot-b-blinky/memory.x
index 6217336..4f7b2cf 100644
--- a/flashloader/slot-b-blinky/memory.x
+++ b/flashloader/slot-b-blinky/memory.x
@@ -1,7 +1,7 @@
 /* Special linker script for application slot B with an offset at address 0x11800 */
 MEMORY
 {
-	FLASH : ORIGIN = 0x00011800, LENGTH = 0x20000 /* 128K */
+	FLASH : ORIGIN = 0x00011800, LENGTH = 0xE800
 	RAM : ORIGIN = 0x10000000, LENGTH = 0x08000 /* 32K */
 }
 
diff --git a/flashloader/src/main.rs b/flashloader/src/main.rs
index 8da9585..eb6e356 100644
--- a/flashloader/src/main.rs
+++ b/flashloader/src/main.rs
@@ -292,7 +292,7 @@ mod app {
     fn handle_valid_pus_tc(cx: &mut pus_tc_handler::Context) {
         let pus_tc = PusTcReader::new(cx.local.tc_buf);
         if pus_tc.is_err() {
-            log::warn!("PUS TC error: {}", pus_tc.unwrap_err());
+            log::warn!(target: "TC Handler", "PUS TC error: {}", pus_tc.unwrap_err());
             return;
         }
         let (pus_tc, _) = pus_tc.unwrap();