improve SPI HAL
This commit is contained in:
@ -6,6 +6,10 @@ All notable changes to this project will be documented in this file.
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The format is based on [Keep a Changelog](http://keepachangelog.com/)
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and this project adheres to [Semantic Versioning](http://semver.org/).
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## [v0.7.0] 2024-07-04
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- Replace `uarta` and `uartb` `Uart` constructors by `new` method.
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## [v0.6.0] 2024-06-16
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- Updated `embedded-hal` to v1
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File diff suppressed because it is too large
Load Diff
@ -11,7 +11,7 @@ use libm::floorf;
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pub use crate::IrqCfg;
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use crate::{
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clock::{self, enable_peripheral_clock, PeripheralClocks},
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clock::{enable_peripheral_clock, PeripheralClocks},
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gpio::pins::{
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AltFunc1, AltFunc2, AltFunc3, Pin, PA16, PA17, PA18, PA19, PA2, PA26, PA27, PA3, PA30,
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PA31, PA8, PA9, PB18, PB19, PB20, PB21, PB22, PB23, PB6, PB7, PB8, PB9,
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@ -19,6 +19,7 @@ use crate::{
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pac::{self, uarta as uart_base},
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time::Hertz,
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utility::unmask_irq,
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PeripheralSelect,
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};
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//==================================================================================================
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@ -306,7 +307,7 @@ pub struct UartBase<Uart> {
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}
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/// Serial abstraction. Entry point to create a new UART
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pub struct Uart<Uart, Pins> {
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uart_base: UartBase<Uart>,
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inner: UartBase<Uart>,
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pins: Pins,
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}
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@ -353,6 +354,7 @@ impl<UART> Tx<UART> {
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pub trait Instance: Deref<Target = uart_base::RegisterBlock> {
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fn ptr() -> *const uart_base::RegisterBlock;
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const IDX: u8;
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const PERIPH_SEL: PeripheralSelect;
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}
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impl<UART: Instance> UartBase<UART> {
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@ -483,14 +485,34 @@ impl<UART: Instance> UartBase<UART> {
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}
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}
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impl<UART, PINS> Uart<UART, PINS>
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impl<UartInstance, PinsInstance> Uart<UartInstance, PinsInstance>
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where
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UART: Instance,
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UartInstance: Instance,
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PinsInstance: Pins<UartInstance>,
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{
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pub fn new(
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syscfg: &mut va108xx::Sysconfig,
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sys_clk: impl Into<Hertz>,
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uart: UartInstance,
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pins: PinsInstance,
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config: impl Into<Config>,
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) -> Self {
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crate::clock::enable_peripheral_clock(syscfg, UartInstance::PERIPH_SEL);
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Uart {
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inner: UartBase {
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uart,
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tx: Tx::new(),
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rx: Rx::new(),
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},
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pins,
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}
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.init(config.into(), sys_clk.into())
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}
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/// This function assumes that the peripheral clock was alredy enabled
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/// in the SYSCONFIG register
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fn init(mut self, config: Config, sys_clk: Hertz) -> Self {
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self.uart_base = self.uart_base.init(config, sys_clk);
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self.inner = self.inner.init(config, sys_clk);
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self
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}
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@ -501,7 +523,7 @@ where
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irq_cfg: IrqCfg,
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sys_cfg: Option<&mut pac::Sysconfig>,
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irq_sel: Option<&mut pac::Irqsel>,
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) -> UartWithIrq<UART, PINS> {
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) -> UartWithIrq<UartInstance, PinsInstance> {
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let (uart, pins) = self.downgrade_internal();
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UartWithIrq {
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pins,
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@ -520,75 +542,75 @@ where
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#[inline]
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pub fn enable_rx(&mut self) {
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self.uart_base.enable_rx();
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self.inner.enable_rx();
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}
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#[inline]
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pub fn disable_rx(&mut self) {
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self.uart_base.enable_rx();
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self.inner.enable_rx();
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}
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#[inline]
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pub fn enable_tx(&mut self) {
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self.uart_base.enable_tx();
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self.inner.enable_tx();
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}
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#[inline]
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pub fn disable_tx(&mut self) {
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self.uart_base.disable_tx();
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self.inner.disable_tx();
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}
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#[inline]
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pub fn clear_rx_fifo(&mut self) {
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self.uart_base.clear_rx_fifo();
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self.inner.clear_rx_fifo();
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}
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#[inline]
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pub fn clear_tx_fifo(&mut self) {
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self.uart_base.clear_tx_fifo();
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self.inner.clear_tx_fifo();
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}
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#[inline]
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pub fn clear_rx_status(&mut self) {
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self.uart_base.clear_rx_status();
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self.inner.clear_rx_status();
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}
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#[inline]
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pub fn clear_tx_status(&mut self) {
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self.uart_base.clear_tx_status();
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self.inner.clear_tx_status();
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}
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pub fn listen(&self, event: Event) {
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self.uart_base.listen(event);
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self.inner.listen(event);
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}
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pub fn unlisten(&self, event: Event) {
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self.uart_base.unlisten(event);
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self.inner.unlisten(event);
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}
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pub fn release(self) -> (UART, PINS) {
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(self.uart_base.release(), self.pins)
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pub fn release(self) -> (UartInstance, PinsInstance) {
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(self.inner.release(), self.pins)
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}
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fn downgrade_internal(self) -> (UartBase<UART>, PINS) {
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fn downgrade_internal(self) -> (UartBase<UartInstance>, PinsInstance) {
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let base = UartBase {
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uart: self.uart_base.uart,
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tx: self.uart_base.tx,
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rx: self.uart_base.rx,
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uart: self.inner.uart,
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tx: self.inner.tx,
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rx: self.inner.rx,
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};
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(base, self.pins)
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}
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pub fn downgrade(self) -> UartBase<UART> {
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pub fn downgrade(self) -> UartBase<UartInstance> {
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UartBase {
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uart: self.uart_base.uart,
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tx: self.uart_base.tx,
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rx: self.uart_base.rx,
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uart: self.inner.uart,
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tx: self.inner.tx,
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rx: self.inner.rx,
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}
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}
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pub fn split(self) -> (Tx<UART>, Rx<UART>) {
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self.uart_base.split()
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pub fn split(self) -> (Tx<UartInstance>, Rx<UartInstance>) {
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self.inner.split()
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}
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}
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@ -597,6 +619,8 @@ impl Instance for pac::Uarta {
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pac::Uarta::ptr() as *const _
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}
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const IDX: u8 = 0;
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const PERIPH_SEL: PeripheralSelect = PeripheralSelect::Uart0;
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}
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impl Instance for pac::Uartb {
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@ -604,36 +628,8 @@ impl Instance for pac::Uartb {
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pac::Uartb::ptr() as *const _
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}
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const IDX: u8 = 1;
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}
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macro_rules! uart_impl {
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($($UARTX:path: ($uartx:ident, $clk_enb_enum:path),)+) => {
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$(
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impl<PINS: Pins<$UARTX>> Uart<$UARTX, PINS> {
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pub fn $uartx(
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uart: $UARTX,
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pins: PINS,
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config: impl Into<Config>,
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syscfg: &mut pac::Sysconfig,
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sys_clk: impl Into<Hertz>
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) -> Self
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{
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enable_peripheral_clock(syscfg, $clk_enb_enum);
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Uart {
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uart_base: UartBase {
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uart,
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tx: Tx::new(),
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rx: Rx::new(),
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},
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pins,
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}
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.init(config.into(), sys_clk.into())
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}
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}
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)+
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}
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const PERIPH_SEL: PeripheralSelect = PeripheralSelect::Uart1;
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}
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impl<UART: Instance> UartWithIrqBase<UART> {
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@ -871,10 +867,12 @@ impl<UART: Instance, PINS> UartWithIrq<UART, PINS> {
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}
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}
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/*
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uart_impl! {
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pac::Uarta: (uarta, clock::PeripheralClocks::Uart0),
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pac::Uartb: (uartb, clock::PeripheralClocks::Uart1),
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}
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*/
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impl<Uart> Tx<Uart> where Uart: Instance {}
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