Update and improve HAL library and docs
All checks were successful
Rust/va108xx-rs/pipeline/pr-main This commit looks good

This commit is contained in:
2024-07-04 17:10:01 +02:00
parent abb78c2682
commit 3c8c455c6f
32 changed files with 1541 additions and 1378 deletions

View File

@ -28,6 +28,6 @@ version = "1"
features = ["cortex-m-systick"]
[dependencies.va108xx-hal]
version = "0.6"
version = "0.7"
path = "../../va108xx-hal"
features = ["rt", "defmt"]

View File

@ -21,9 +21,9 @@ fn main() -> ! {
let mut dp = pac::Peripherals::take().unwrap();
let pinsa = PinsA::new(&mut dp.sysconfig, None, dp.porta);
let mut pwm = pwm::PwmPin::new(
(pinsa.pa3.into_funsel_1(), dp.tim3),
50.MHz(),
&mut dp.sysconfig,
50.MHz(),
(pinsa.pa3.into_funsel_1(), dp.tim3),
10.Hz(),
);
let mut delay = set_up_ms_delay_provider(&mut dp.sysconfig, 50.MHz(), dp.tim0);

View File

@ -3,12 +3,14 @@
#![no_std]
use cortex_m_rt::entry;
use panic_halt as _;
use panic_rtt_target as _;
use rtt_target::{rprintln, rtt_init_print};
use va108xx_hal as _;
#[entry]
fn main() -> ! {
rtt_init_print!();
rprintln!("-- VA108XX RTT example --");
let mut counter = 0;
loop {
rprintln!("{}: Hello, world!", counter);

View File

@ -73,12 +73,12 @@ fn main() -> ! {
pinsa.pa30.into_funsel_1(),
pinsa.pa29.into_funsel_1(),
);
let mut spia = Spi::spia(
let mut spia = Spi::new(
&mut dp.sysconfig,
50.MHz(),
dp.spia,
(sck, miso, mosi),
50.MHz(),
spi_cfg,
Some(&mut dp.sysconfig),
None,
);
spia.set_fill_word(FILL_WORD);
@ -90,12 +90,12 @@ fn main() -> ! {
pinsb.pb8.into_funsel_2(),
pinsb.pb7.into_funsel_2(),
);
let mut spia = Spi::spia(
let mut spia = Spi::new(
&mut dp.sysconfig,
50.MHz(),
dp.spia,
(sck, miso, mosi),
50.MHz(),
spi_cfg,
Some(&mut dp.sysconfig),
None,
);
spia.set_fill_word(FILL_WORD);
@ -107,12 +107,12 @@ fn main() -> ! {
pinsb.pb4.into_funsel_1(),
pinsb.pb3.into_funsel_1(),
);
let mut spib = Spi::spib(
let mut spib = Spi::new(
&mut dp.sysconfig,
50.MHz(),
dp.spib,
(sck, miso, mosi),
50.MHz(),
spi_cfg,
Some(&mut dp.sysconfig),
None,
);
spib.set_fill_word(FILL_WORD);
@ -195,6 +195,10 @@ fn main() -> ! {
if EXAMPLE_SEL == ExampleSelect::Loopback {
// Can't really verify correct reply here.
spi.write(&[0x42]).expect("write failed");
// Need small delay.. otherwise we will read back the sent byte (which we don't want here).
// The write function will return as soon as all bytes were shifted out, ignoring the
// reply bytes.
delay.delay_us(50);
// Because of the loopback mode, we should get back the fill word here.
spi.read(&mut reply_buf[0..1]).unwrap();
assert_eq!(reply_buf[0], FILL_WORD);

View File

@ -65,7 +65,7 @@ mod app {
let irq_cfg = IrqCfg::new(pac::interrupt::OC3, true, true);
let (mut irq_uart, _) =
uart::Uart::uartb(dp.uartb, (tx, rx), 115200.Hz(), &mut dp.sysconfig, 50.MHz())
uart::Uart::new(&mut dp.sysconfig, 50.MHz(), dp.uartb, (tx, rx), 115200.Hz())
.into_uart_with_irq(irq_cfg, Some(&mut dp.sysconfig), Some(&mut dp.irqsel))
.downgrade();
irq_uart

View File

@ -28,7 +28,7 @@ fn main() -> ! {
let tx = gpioa.pa9.into_funsel_2();
let rx = gpioa.pa8.into_funsel_2();
let uarta = uart::Uart::uarta(dp.uarta, (tx, rx), 115200.Hz(), &mut dp.sysconfig, 50.MHz());
let uarta = uart::Uart::new(&mut dp.sysconfig, 50.MHz(), dp.uarta, (tx, rx), 115200.Hz());
let (mut tx, mut rx) = uarta.split();
writeln!(tx, "Hello World\r").unwrap();
loop {