continue async uart tx

va108xx-hal/src/uart.rs

@@ -845,6 +845,33 @@ impl<Uart: Instance> Tx<Uart> {
         self.0.enable().modify(|_, w| w.txenable().clear_bit());
     }
 
+    /// Enables the IRQ_TX, IRQ_TX_STATUS and IRQ_TX_EMPTY interrupts.
+    ///
+    /// - The IRQ_TX interrupt is generated when the TX FIFO is at least half empty.
+    /// - The IRQ_TX_STATUS interrupt is generated when write data is lost due to a FIFO overflow
+    /// - The IRQ_TX_EMPTY interrupt is generated when the TX FIFO is empty and the TXBUSY signal
+    ///   is 0
+    #[inline]
+    pub fn enable_interrupts(&self) {
+        self.0.irq_enb().modify(|_, w| {
+            w.irq_tx().set_bit();
+            w.irq_tx_status().set_bit();
+            w.irq_tx_empty().set_bit()
+        });
+    }
+
+    /// Disables the IRQ_TX, IRQ_TX_STATUS and IRQ_TX_EMPTY interrupts.
+    ///
+    /// [Self::enable_interrupts] documents the interrupts.
+    #[inline]
+    pub fn disable_interrupts(&self) {
+        self.0.irq_enb().modify(|_, w| {
+            w.irq_tx().clear_bit();
+            w.irq_tx_empty().clear_bit();
+            w.irq_tx_empty().clear_bit()
+        });
+    }
+
     /// Low level function to write a word to the UART FIFO.
     ///
     /// Uses the [nb] API to allow usage in blocking and non-blocking contexts.