From 52f5d42358880ee167129d964f3fdb680b62cd18 Mon Sep 17 00:00:00 2001 From: Robin Mueller Date: Fri, 27 Sep 2024 15:33:50 +0200 Subject: [PATCH] all flashloader adaptions --- Cargo.toml | 3 ++- flashloader/image-loader.py | 16 ++++++++-------- flashloader/slot-a-blinky/Cargo.toml | 2 +- flashloader/slot-a-blinky/memory.x | 19 +++---------------- flashloader/slot-a-blinky/src/main.rs | 11 ++++++----- flashloader/slot-b-blinky/Cargo.toml | 2 +- flashloader/slot-b-blinky/memory.x | 19 +++---------------- flashloader/slot-b-blinky/src/main.rs | 13 +++++++------ 8 files changed, 31 insertions(+), 54 deletions(-) diff --git a/Cargo.toml b/Cargo.toml index 34c1302..866cfe0 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -11,9 +11,10 @@ members = [ "bootloader", "flashloader", ] - exclude = [ "defmt-testapp", + "flashloader/slot-a-blinky", + "flashloader/slot-b-blinky", ] [profile.dev] diff --git a/flashloader/image-loader.py b/flashloader/image-loader.py index 802cdec..0529bbd 100755 --- a/flashloader/image-loader.py +++ b/flashloader/image-loader.py @@ -25,19 +25,19 @@ from elftools.elf.elffile import ELFFile BAUD_RATE = 115200 BOOTLOADER_START_ADDR = 0x0 -BOOTLOADER_END_ADDR = 0x4000 +BOOTLOADER_END_ADDR = 0x3000 BOOTLOADER_CRC_ADDR = BOOTLOADER_END_ADDR - 4 BOOTLOADER_MAX_SIZE = BOOTLOADER_END_ADDR - BOOTLOADER_START_ADDR - 4 -APP_A_START_ADDR = 0x4000 -APP_A_END_ADDR = 0x22000 +APP_A_START_ADDR = 0x3000 +APP_A_END_ADDR = 0x11800 # The actual size of the image which is relevant for CRC calculation. APP_A_SIZE_ADDR = APP_A_END_ADDR - 8 APP_A_CRC_ADDR = APP_A_END_ADDR - 4 APP_A_MAX_SIZE = APP_A_END_ADDR - APP_A_START_ADDR - 8 -APP_B_START_ADDR = 0x22000 -APP_B_END_ADDR = 0x40000 +APP_B_START_ADDR = APP_A_END_ADDR +APP_B_END_ADDR = 0x20000 # The actual size of the image which is relevant for CRC calculation. APP_B_SIZE_ADDR = APP_B_END_ADDR - 8 APP_B_CRC_ADDR = APP_B_END_ADDR - 4 @@ -45,7 +45,7 @@ APP_B_MAX_SIZE = APP_A_END_ADDR - APP_A_START_ADDR - 8 APP_IMG_SZ = (APP_B_END_ADDR - APP_A_START_ADDR) // 2 -CHUNK_SIZE = 896 +CHUNK_SIZE = 512 MEMORY_SERVICE = 6 ACTION_SERVICE = 8 @@ -229,7 +229,7 @@ class ImageLoader: ) self.com_if.send(bytes(size_write_packet.pack())) time.sleep(0.2) - crc_calc = PredefinedCrc("crc-32") + crc_calc = PredefinedCrc("crc-ccitt-false") for segment in loadable_segments: crc_calc.update(segment.data) checksum = crc_calc.digest() @@ -243,7 +243,7 @@ class ImageLoader: def main() -> int: - print("Python VA416XX Image Loader Application") + print("Python VA108XX Image Loader Application") logging.basicConfig( format="[%(asctime)s] [%(levelname)s] %(message)s", level=logging.DEBUG ) diff --git a/flashloader/slot-a-blinky/Cargo.toml b/flashloader/slot-a-blinky/Cargo.toml index 5e7e23e..701674f 100644 --- a/flashloader/slot-a-blinky/Cargo.toml +++ b/flashloader/slot-a-blinky/Cargo.toml @@ -11,7 +11,7 @@ panic-rtt-target = { version = "0.1.3" } rtt-target = { version = "0.5" } cortex-m = { version = "0.7", features = ["critical-section-single-core"] } embedded-hal = "1" -va416xx-hal = { path = "../../va416xx-hal", features = ["va41630"] } +va108xx-hal = { path = "../../va108xx-hal" } [profile.dev] codegen-units = 1 diff --git a/flashloader/slot-a-blinky/memory.x b/flashloader/slot-a-blinky/memory.x index 9d8c317..95e53ca 100644 --- a/flashloader/slot-a-blinky/memory.x +++ b/flashloader/slot-a-blinky/memory.x @@ -1,24 +1,11 @@ -/* Special linker script for application slot A with an offset at address 0x4000 */ +/* Special linker script for application slot A with an offset at address 0x3000 */ MEMORY { - FLASH : ORIGIN = 0x00004000, LENGTH = 256K - /* RAM is a mandatory region. This RAM refers to the SRAM_0 */ - RAM : ORIGIN = 0x1FFF8000, LENGTH = 32K - SRAM_1 : ORIGIN = 0x20000000, LENGTH = 32K + FLASH : ORIGIN = 0x00000000, LENGTH = 0x3000 /* 128K */ + RAM : ORIGIN = 0x10000000, LENGTH = 0x08000 /* 32K */ } /* This is where the call stack will be allocated. */ /* The stack is of the full descending type. */ /* NOTE Do NOT modify `_stack_start` unless you know what you are doing */ -/* SRAM_0 can be used for all busses: Instruction, Data and System */ -/* SRAM_1 only supports the system bus */ _stack_start = ORIGIN(RAM) + LENGTH(RAM); - -/* Define sections for placing symbols into the extra memory regions above. */ -/* This makes them accessible from code. */ -SECTIONS { - .sram1 (NOLOAD) : ALIGN(8) { - *(.sram1 .sram1.*); - . = ALIGN(4); - } > SRAM_1 -}; diff --git a/flashloader/slot-a-blinky/src/main.rs b/flashloader/slot-a-blinky/src/main.rs index 517b20c..8dc24aa 100644 --- a/flashloader/slot-a-blinky/src/main.rs +++ b/flashloader/slot-a-blinky/src/main.rs @@ -6,18 +6,19 @@ use cortex_m_rt::entry; use embedded_hal::digital::StatefulOutputPin; use panic_rtt_target as _; use rtt_target::{rprintln, rtt_init_print}; -use va416xx_hal::{gpio::PinsG, pac}; +use va108xx_hal::{gpio::PinsA, pac}; #[entry] fn main() -> ! { rtt_init_print!(); - rprintln!("VA416xx HAL blinky example for App Slot A"); + rprintln!("VA108xx HAL blinky example for App Slot A"); let mut dp = pac::Peripherals::take().unwrap(); - let portg = PinsG::new(&mut dp.sysconfig, dp.portg); - let mut led = portg.pg5.into_readable_push_pull_output(); + let porta = PinsA::new(&mut dp.sysconfig, Some(dp.ioconfig), dp.porta); + let mut led1 = porta.pa10.into_readable_push_pull_output(); + loop { cortex_m::asm::delay(1_000_000); - led.toggle().ok(); + led1.toggle().ok(); } } diff --git a/flashloader/slot-b-blinky/Cargo.toml b/flashloader/slot-b-blinky/Cargo.toml index 1b5c3d0..d636e98 100644 --- a/flashloader/slot-b-blinky/Cargo.toml +++ b/flashloader/slot-b-blinky/Cargo.toml @@ -11,7 +11,7 @@ panic-rtt-target = { version = "0.1.3" } rtt-target = { version = "0.5" } cortex-m = { version = "0.7", features = ["critical-section-single-core"] } embedded-hal = "1" -va416xx-hal = { path = "../../va416xx-hal", features = ["va41630"] } +va108xx-hal = { path = "../../va108xx-hal" } [profile.dev] codegen-units = 1 diff --git a/flashloader/slot-b-blinky/memory.x b/flashloader/slot-b-blinky/memory.x index 4a9dcb0..e65a785 100644 --- a/flashloader/slot-b-blinky/memory.x +++ b/flashloader/slot-b-blinky/memory.x @@ -1,24 +1,11 @@ -/* Special linker script for application slot B with an offset at address 0x22000 */ +/* Special linker script for application slot B with an offset at address 0x11800 */ MEMORY { - FLASH : ORIGIN = 0x00022000, LENGTH = 256K - /* RAM is a mandatory region. This RAM refers to the SRAM_0 */ - RAM : ORIGIN = 0x1FFF8000, LENGTH = 32K - SRAM_1 : ORIGIN = 0x20000000, LENGTH = 32K + FLASH : ORIGIN = 0x00000000, LENGTH = 0x11800 /* 128K */ + RAM : ORIGIN = 0x10000000, LENGTH = 0x08000 /* 32K */ } /* This is where the call stack will be allocated. */ /* The stack is of the full descending type. */ /* NOTE Do NOT modify `_stack_start` unless you know what you are doing */ -/* SRAM_0 can be used for all busses: Instruction, Data and System */ -/* SRAM_1 only supports the system bus */ _stack_start = ORIGIN(RAM) + LENGTH(RAM); - -/* Define sections for placing symbols into the extra memory regions above. */ -/* This makes them accessible from code. */ -SECTIONS { - .sram1 (NOLOAD) : ALIGN(8) { - *(.sram1 .sram1.*); - . = ALIGN(4); - } > SRAM_1 -}; diff --git a/flashloader/slot-b-blinky/src/main.rs b/flashloader/slot-b-blinky/src/main.rs index 5663410..df59da0 100644 --- a/flashloader/slot-b-blinky/src/main.rs +++ b/flashloader/slot-b-blinky/src/main.rs @@ -6,18 +6,19 @@ use cortex_m_rt::entry; use embedded_hal::digital::StatefulOutputPin; use panic_rtt_target as _; use rtt_target::{rprintln, rtt_init_print}; -use va416xx_hal::{gpio::PinsG, pac}; +use va108xx_hal::{gpio::PinsA, pac}; #[entry] fn main() -> ! { rtt_init_print!(); - rprintln!("VA416xx HAL blinky example for App Slot B"); + rprintln!("VA108xx HAL blinky example for App Slot B"); let mut dp = pac::Peripherals::take().unwrap(); - let portg = PinsG::new(&mut dp.sysconfig, dp.portg); - let mut led = portg.pg5.into_readable_push_pull_output(); + let porta = PinsA::new(&mut dp.sysconfig, Some(dp.ioconfig), dp.porta); + let mut led2 = porta.pa7.into_readable_push_pull_output(); + loop { - cortex_m::asm::delay(8_000_000); - led.toggle().ok(); + cortex_m::asm::delay(1_000_000); + led2.toggle().ok(); } }