Update for va108xx
- New `va108xx-embassy` crate. - Embassy library uses new crate - Updated all dependencies va108xx-hal - Refactored and simplified PWM driver - Added new raw getter API for TIM peripheral blocks
This commit is contained in:
@ -10,14 +10,12 @@ use core::marker::PhantomData;
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use crate::pac;
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use crate::time::Hertz;
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use crate::timer::{
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TimAndPinRegister, TimDynRegister, TimPin, TimRegInterface, ValidTim, ValidTimAndPin,
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};
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use crate::timer::{TimDynRegister, TimPin, TimRegInterface, ValidTim, ValidTimAndPin};
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use crate::{clock::enable_peripheral_clock, gpio::DynPinId};
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const DUTY_MAX: u16 = u16::MAX;
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pub struct PwmBase {
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pub struct PwmCommon {
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sys_clk: Hertz,
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/// For PWMB, this is the upper limit
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current_duty: u16,
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@ -35,123 +33,13 @@ enum StatusSelPwm {
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pub struct PwmA {}
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pub struct PwmB {}
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//==================================================================================================
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// Common
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//==================================================================================================
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macro_rules! pwm_common_func {
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() => {
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#[inline]
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fn enable_pwm_a(&mut self) {
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self.reg
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.reg()
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.ctrl()
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.modify(|_, w| unsafe { w.status_sel().bits(StatusSelPwm::PwmA as u8) });
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}
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#[inline]
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fn enable_pwm_b(&mut self) {
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self.reg
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.reg()
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.ctrl()
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.modify(|_, w| unsafe { w.status_sel().bits(StatusSelPwm::PwmB as u8) });
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}
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#[inline]
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pub fn get_period(&self) -> Hertz {
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self.pwm_base.current_period
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}
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#[inline]
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pub fn set_period(&mut self, period: impl Into<Hertz>) {
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self.pwm_base.current_period = period.into();
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// Avoid division by 0
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if self.pwm_base.current_period.raw() == 0 {
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return;
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}
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self.pwm_base.current_rst_val =
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self.pwm_base.sys_clk.raw() / self.pwm_base.current_period.raw();
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self.reg
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.reg()
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.rst_value()
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.write(|w| unsafe { w.bits(self.pwm_base.current_rst_val) });
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}
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#[inline]
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pub fn disable(&mut self) {
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self.reg.reg().ctrl().modify(|_, w| w.enable().clear_bit());
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}
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#[inline]
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pub fn enable(&mut self) {
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self.reg.reg().ctrl().modify(|_, w| w.enable().set_bit());
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}
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#[inline]
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pub fn period(&self) -> Hertz {
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self.pwm_base.current_period
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}
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#[inline(always)]
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pub fn duty(&self) -> u16 {
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self.pwm_base.current_duty
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}
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};
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}
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macro_rules! pwmb_func {
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() => {
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pub fn pwmb_lower_limit(&self) -> u16 {
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self.pwm_base.current_lower_limit
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}
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pub fn pwmb_upper_limit(&self) -> u16 {
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self.pwm_base.current_duty
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}
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/// Set the lower limit for PWMB
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///
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/// The PWM signal will be 1 as long as the current RST counter is larger than
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/// the lower limit. For example, with a lower limit of 0.5 and and an upper limit
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/// of 0.7, Only a fixed period between 0.5 * period and 0.7 * period will be in a high
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/// state
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pub fn set_pwmb_lower_limit(&mut self, duty: u16) {
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self.pwm_base.current_lower_limit = duty;
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let pwmb_val: u64 = (self.pwm_base.current_rst_val as u64
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* self.pwm_base.current_lower_limit as u64)
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/ DUTY_MAX as u64;
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self.reg
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.reg()
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.pwmb_value()
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.write(|w| unsafe { w.bits(pwmb_val as u32) });
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}
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/// Set the higher limit for PWMB
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///
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/// The PWM signal will be 1 as long as the current RST counter is smaller than
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/// the higher limit. For example, with a lower limit of 0.5 and and an upper limit
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/// of 0.7, Only a fixed period between 0.5 * period and 0.7 * period will be in a high
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/// state
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pub fn set_pwmb_upper_limit(&mut self, duty: u16) {
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self.pwm_base.current_duty = duty;
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let pwma_val: u64 = (self.pwm_base.current_rst_val as u64
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* self.pwm_base.current_duty as u64)
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/ DUTY_MAX as u64;
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self.reg
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.reg()
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.pwma_value()
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.write(|w| unsafe { w.bits(pwma_val as u32) });
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}
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};
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}
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//==================================================================================================
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// Strongly typed PWM pin
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//==================================================================================================
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pub struct PwmPin<Pin: TimPin, Tim: ValidTim, Mode = PwmA> {
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reg: TimAndPinRegister<Pin, Tim>,
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pwm_base: PwmBase,
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pin_and_tim: (Pin, Tim),
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inner: ReducedPwmPin<Mode>,
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mode: PhantomData<Mode>,
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}
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@ -163,34 +51,82 @@ where
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pub fn new(
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sys_cfg: &mut pac::Sysconfig,
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sys_clk: impl Into<Hertz> + Copy,
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tim_and_pin: (Pin, Tim),
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pin_and_tim: (Pin, Tim),
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initial_period: impl Into<Hertz> + Copy,
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) -> Self {
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let mut pin = PwmPin {
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pwm_base: PwmBase {
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current_duty: 0,
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current_lower_limit: 0,
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current_period: initial_period.into(),
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current_rst_val: 0,
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sys_clk: sys_clk.into(),
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},
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reg: unsafe { TimAndPinRegister::new(tim_and_pin.0, tim_and_pin.1) },
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pin_and_tim,
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inner: ReducedPwmPin::<Mode>::new(
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Tim::TIM_ID,
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Pin::DYN,
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PwmCommon {
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current_duty: 0,
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current_lower_limit: 0,
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current_period: initial_period.into(),
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current_rst_val: 0,
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sys_clk: sys_clk.into(),
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},
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),
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//unsafe { TimAndPin::new(tim_and_pin.0, tim_and_pin.1) },
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mode: PhantomData,
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};
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enable_peripheral_clock(sys_cfg, crate::clock::PeripheralClocks::Gpio);
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enable_peripheral_clock(sys_cfg, crate::clock::PeripheralClocks::Ioconfig);
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sys_cfg
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.tim_clk_enable()
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.modify(|r, w| unsafe { w.bits(r.bits() | pin.reg.mask_32()) });
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.modify(|r, w| unsafe { w.bits(r.bits() | pin.pin_and_tim.1.mask_32()) });
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pin.enable_pwm_a();
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pin.set_period(initial_period);
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pin
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}
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pub fn release(self) -> (Pin, Tim) {
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self.reg.release()
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pub fn reduce(self) -> ReducedPwmPin<Mode> {
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self.inner
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}
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pwm_common_func!();
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pub fn release(self) -> (Pin, Tim) {
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self.pin_and_tim
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}
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#[inline]
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fn enable_pwm_a(&mut self) {
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self.inner.enable_pwm_a();
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}
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#[inline]
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fn enable_pwm_b(&mut self) {
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self.inner.enable_pwm_b();
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}
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#[inline]
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pub fn get_period(&self) -> Hertz {
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self.inner.get_period()
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}
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#[inline]
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pub fn set_period(&mut self, period: impl Into<Hertz>) {
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self.inner.set_period(period);
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}
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#[inline]
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pub fn disable(&mut self) {
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self.inner.disable();
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}
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#[inline]
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pub fn enable(&mut self) {
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self.inner.enable();
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}
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#[inline]
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pub fn period(&self) -> Hertz {
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self.inner.period()
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}
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#[inline(always)]
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pub fn duty(&self) -> u16 {
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self.inner.duty()
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}
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}
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impl<Pin: TimPin, Tim: ValidTim> From<PwmPin<Pin, Tim, PwmA>> for PwmPin<Pin, Tim, PwmB>
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@ -199,9 +135,9 @@ where
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{
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fn from(other: PwmPin<Pin, Tim, PwmA>) -> Self {
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let mut pwmb = Self {
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reg: other.reg,
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pwm_base: other.pwm_base,
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mode: PhantomData,
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pin_and_tim: other.pin_and_tim,
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inner: other.inner.into(),
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};
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pwmb.enable_pwm_b();
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pwmb
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@ -213,13 +149,13 @@ where
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(PIN, TIM): ValidTimAndPin<PIN, TIM>,
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{
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fn from(other: PwmPin<PIN, TIM, PwmB>) -> Self {
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let mut pwmb = Self {
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reg: other.reg,
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pwm_base: other.pwm_base,
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let mut pwma = Self {
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mode: PhantomData,
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pin_and_tim: other.pin_and_tim,
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inner: other.inner.into(),
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};
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pwmb.enable_pwm_a();
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pwmb
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pwma.enable_pwm_a();
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pwma
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}
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}
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@ -263,33 +199,105 @@ where
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/// Reduced version where type information is deleted
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pub struct ReducedPwmPin<Mode = PwmA> {
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reg: TimDynRegister,
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pwm_base: PwmBase,
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pin_id: DynPinId,
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dyn_reg: TimDynRegister,
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common: PwmCommon,
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mode: PhantomData<Mode>,
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}
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impl<PIN: TimPin, TIM: ValidTim> From<PwmPin<PIN, TIM>> for ReducedPwmPin<PwmA> {
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fn from(pwm_pin: PwmPin<PIN, TIM>) -> Self {
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ReducedPwmPin {
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reg: TimDynRegister::from(pwm_pin.reg),
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pwm_base: pwm_pin.pwm_base,
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pin_id: PIN::DYN,
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impl<Mode> ReducedPwmPin<Mode> {
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pub(crate) fn new(tim_id: u8, pin_id: DynPinId, common: PwmCommon) -> Self {
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Self {
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dyn_reg: TimDynRegister { tim_id, pin_id },
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common,
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mode: PhantomData,
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}
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}
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}
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/*
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impl<Pin: TimPin, Tim: ValidTim> From<PwmPin<Pin, Tim>> for ReducedPwmPin<PwmA> {
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fn from(pwm_pin: PwmPin<Pin, Tim>) -> Self {
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ReducedPwmPin {
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dyn_reg: TimDynRegister {
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impl<MODE> ReducedPwmPin<MODE> {
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pwm_common_func!();
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}
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// ::from(pwm_pin.reg),
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common: pwm_pin.pwm_base,
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pin_id: Pin::DYN,
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mode: PhantomData,
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}
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}
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}
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*/
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impl<Mode> ReducedPwmPin<Mode> {
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#[inline]
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fn enable_pwm_a(&mut self) {
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self.dyn_reg
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.reg_block()
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.ctrl()
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.modify(|_, w| unsafe { w.status_sel().bits(StatusSelPwm::PwmA as u8) });
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}
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#[inline]
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fn enable_pwm_b(&mut self) {
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self.dyn_reg
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.reg_block()
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.ctrl()
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.modify(|_, w| unsafe { w.status_sel().bits(StatusSelPwm::PwmB as u8) });
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}
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#[inline]
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pub fn get_period(&self) -> Hertz {
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self.common.current_period
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}
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#[inline]
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pub fn set_period(&mut self, period: impl Into<Hertz>) {
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self.common.current_period = period.into();
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// Avoid division by 0
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if self.common.current_period.raw() == 0 {
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return;
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}
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self.common.current_rst_val = self.common.sys_clk.raw() / self.common.current_period.raw();
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self.dyn_reg
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.reg_block()
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.rst_value()
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.write(|w| unsafe { w.bits(self.common.current_rst_val) });
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}
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#[inline]
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pub fn disable(&mut self) {
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self.dyn_reg
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.reg_block()
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.ctrl()
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.modify(|_, w| w.enable().clear_bit());
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}
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#[inline]
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pub fn enable(&mut self) {
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self.dyn_reg
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.reg_block()
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.ctrl()
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.modify(|_, w| w.enable().set_bit());
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}
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#[inline]
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pub fn period(&self) -> Hertz {
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self.common.current_period
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}
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#[inline(always)]
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pub fn duty(&self) -> u16 {
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self.common.current_duty
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}
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}
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impl From<ReducedPwmPin<PwmA>> for ReducedPwmPin<PwmB> {
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fn from(other: ReducedPwmPin<PwmA>) -> Self {
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let mut pwmb = Self {
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reg: other.reg,
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pwm_base: other.pwm_base,
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pin_id: other.pin_id,
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dyn_reg: other.dyn_reg,
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common: other.common,
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mode: PhantomData,
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};
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pwmb.enable_pwm_b();
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@ -300,9 +308,8 @@ impl From<ReducedPwmPin<PwmA>> for ReducedPwmPin<PwmB> {
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impl From<ReducedPwmPin<PwmB>> for ReducedPwmPin<PwmA> {
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fn from(other: ReducedPwmPin<PwmB>) -> Self {
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let mut pwmb = Self {
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reg: other.reg,
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pwm_base: other.pwm_base,
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pin_id: other.pin_id,
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dyn_reg: other.dyn_reg,
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common: other.common,
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mode: PhantomData,
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};
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pwmb.enable_pwm_a();
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@ -314,15 +321,83 @@ impl From<ReducedPwmPin<PwmB>> for ReducedPwmPin<PwmA> {
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// PWMB implementations
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//==================================================================================================
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impl<PIN: TimPin, TIM: ValidTim> PwmPin<PIN, TIM, PwmB>
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impl<Pin: TimPin, Tim: ValidTim> PwmPin<Pin, Tim, PwmB>
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where
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(PIN, TIM): ValidTimAndPin<PIN, TIM>,
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(Pin, Tim): ValidTimAndPin<Pin, Tim>,
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{
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pwmb_func!();
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pub fn pwmb_lower_limit(&self) -> u16 {
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self.inner.pwmb_lower_limit()
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}
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pub fn pwmb_upper_limit(&self) -> u16 {
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self.inner.pwmb_upper_limit()
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}
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/// Set the lower limit for PWMB
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///
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/// The PWM signal will be 1 as long as the current RST counter is larger than
|
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/// the lower limit. For example, with a lower limit of 0.5 and and an upper limit
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/// of 0.7, Only a fixed period between 0.5 * period and 0.7 * period will be in a high
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/// state
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pub fn set_pwmb_lower_limit(&mut self, duty: u16) {
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self.inner.set_pwmb_lower_limit(duty);
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}
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/// Set the higher limit for PWMB
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///
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/// The PWM signal will be 1 as long as the current RST counter is smaller than
|
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/// the higher limit. For example, with a lower limit of 0.5 and and an upper limit
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/// of 0.7, Only a fixed period between 0.5 * period and 0.7 * period will be in a high
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/// state
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pub fn set_pwmb_upper_limit(&mut self, duty: u16) {
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self.inner.set_pwmb_upper_limit(duty);
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}
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}
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impl ReducedPwmPin<PwmB> {
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pwmb_func!();
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#[inline(always)]
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pub fn pwmb_lower_limit(&self) -> u16 {
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self.common.current_lower_limit
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}
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#[inline(always)]
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pub fn pwmb_upper_limit(&self) -> u16 {
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self.common.current_duty
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}
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/// Set the lower limit for PWMB
|
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///
|
||||
/// The PWM signal will be 1 as long as the current RST counter is larger than
|
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/// the lower limit. For example, with a lower limit of 0.5 and and an upper limit
|
||||
/// of 0.7, Only a fixed period between 0.5 * period and 0.7 * period will be in a high
|
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/// state
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#[inline(always)]
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pub fn set_pwmb_lower_limit(&mut self, duty: u16) {
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self.common.current_lower_limit = duty;
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let pwmb_val: u64 = (self.common.current_rst_val as u64
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* self.common.current_lower_limit as u64)
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/ DUTY_MAX as u64;
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self.dyn_reg
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.reg_block()
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.pwmb_value()
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.write(|w| unsafe { w.bits(pwmb_val as u32) });
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}
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|
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/// Set the higher limit for PWMB
|
||||
///
|
||||
/// The PWM signal will be 1 as long as the current RST counter is smaller than
|
||||
/// the higher limit. For example, with a lower limit of 0.5 and and an upper limit
|
||||
/// of 0.7, Only a fixed period between 0.5 * period and 0.7 * period will be in a high
|
||||
/// state
|
||||
pub fn set_pwmb_upper_limit(&mut self, duty: u16) {
|
||||
self.common.current_duty = duty;
|
||||
let pwma_val: u64 = (self.common.current_rst_val as u64 * self.common.current_duty as u64)
|
||||
/ DUTY_MAX as u64;
|
||||
self.dyn_reg
|
||||
.reg_block()
|
||||
.pwma_value()
|
||||
.write(|w| unsafe { w.bits(pwma_val as u32) });
|
||||
}
|
||||
}
|
||||
|
||||
//==================================================================================================
|
||||
@ -345,12 +420,12 @@ impl embedded_hal::pwm::SetDutyCycle for ReducedPwmPin {
|
||||
|
||||
#[inline]
|
||||
fn set_duty_cycle(&mut self, duty: u16) -> Result<(), Self::Error> {
|
||||
self.pwm_base.current_duty = duty;
|
||||
let pwma_val: u64 = (self.pwm_base.current_rst_val as u64
|
||||
* (DUTY_MAX as u64 - self.pwm_base.current_duty as u64))
|
||||
self.common.current_duty = duty;
|
||||
let pwma_val: u64 = (self.common.current_rst_val as u64
|
||||
* (DUTY_MAX as u64 - self.common.current_duty as u64))
|
||||
/ DUTY_MAX as u64;
|
||||
self.reg
|
||||
.reg()
|
||||
self.dyn_reg
|
||||
.reg_block()
|
||||
.pwma_value()
|
||||
.write(|w| unsafe { w.bits(pwma_val as u32) });
|
||||
Ok(())
|
||||
@ -365,15 +440,7 @@ impl<Pin: TimPin, Tim: ValidTim> embedded_hal::pwm::SetDutyCycle for PwmPin<Pin,
|
||||
|
||||
#[inline]
|
||||
fn set_duty_cycle(&mut self, duty: u16) -> Result<(), Self::Error> {
|
||||
self.pwm_base.current_duty = duty;
|
||||
let pwma_val: u64 = (self.pwm_base.current_rst_val as u64
|
||||
* (DUTY_MAX as u64 - self.pwm_base.current_duty as u64))
|
||||
/ DUTY_MAX as u64;
|
||||
self.reg
|
||||
.reg()
|
||||
.pwma_value()
|
||||
.write(|w| unsafe { w.bits(pwma_val as u32) });
|
||||
Ok(())
|
||||
self.inner.set_duty_cycle(duty)
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@ -26,6 +26,48 @@ use fugit::RateExtU32;
|
||||
const IRQ_DST_NONE: u32 = 0xffffffff;
|
||||
pub static MS_COUNTER: Mutex<Cell<u32>> = Mutex::new(Cell::new(0));
|
||||
|
||||
/// Get the peripheral block of a TIM peripheral given the index.
|
||||
///
|
||||
/// This function panics if the given index is greater than 23.
|
||||
///
|
||||
/// # Safety
|
||||
///
|
||||
/// This returns a direct handle to the peripheral block, which allows to circumvent ownership
|
||||
/// rules for the peripheral block. You have to ensure that the retrieved peripheral block is not
|
||||
/// used by any other software component.
|
||||
#[inline(always)]
|
||||
pub const unsafe fn get_tim_raw(tim_idx: usize) -> &'static pac::tim0::RegisterBlock {
|
||||
match tim_idx {
|
||||
0 => unsafe { &*pac::Tim0::ptr() },
|
||||
1 => unsafe { &*pac::Tim1::ptr() },
|
||||
2 => unsafe { &*pac::Tim2::ptr() },
|
||||
3 => unsafe { &*pac::Tim3::ptr() },
|
||||
4 => unsafe { &*pac::Tim4::ptr() },
|
||||
5 => unsafe { &*pac::Tim5::ptr() },
|
||||
6 => unsafe { &*pac::Tim6::ptr() },
|
||||
7 => unsafe { &*pac::Tim7::ptr() },
|
||||
8 => unsafe { &*pac::Tim8::ptr() },
|
||||
9 => unsafe { &*pac::Tim9::ptr() },
|
||||
10 => unsafe { &*pac::Tim10::ptr() },
|
||||
11 => unsafe { &*pac::Tim11::ptr() },
|
||||
12 => unsafe { &*pac::Tim12::ptr() },
|
||||
13 => unsafe { &*pac::Tim13::ptr() },
|
||||
14 => unsafe { &*pac::Tim14::ptr() },
|
||||
15 => unsafe { &*pac::Tim15::ptr() },
|
||||
16 => unsafe { &*pac::Tim16::ptr() },
|
||||
17 => unsafe { &*pac::Tim17::ptr() },
|
||||
18 => unsafe { &*pac::Tim18::ptr() },
|
||||
19 => unsafe { &*pac::Tim19::ptr() },
|
||||
20 => unsafe { &*pac::Tim20::ptr() },
|
||||
21 => unsafe { &*pac::Tim21::ptr() },
|
||||
22 => unsafe { &*pac::Tim22::ptr() },
|
||||
23 => unsafe { &*pac::Tim23::ptr() },
|
||||
_ => {
|
||||
panic!("invalid alarm timer index")
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
//==================================================================================================
|
||||
// Defintions
|
||||
//==================================================================================================
|
||||
@ -248,7 +290,7 @@ pub type TimRegBlock = tim0::RegisterBlock;
|
||||
/// implementations should be overridden. The implementing type must also have
|
||||
/// "control" over the corresponding pin ID, i.e. it must guarantee that a each
|
||||
/// pin ID is a singleton.
|
||||
pub(super) unsafe trait TimRegInterface {
|
||||
pub unsafe trait TimRegInterface {
|
||||
fn tim_id(&self) -> u8;
|
||||
|
||||
const PORT_BASE: *const tim0::RegisterBlock = pac::Tim0::ptr() as *const _;
|
||||
@ -256,7 +298,7 @@ pub(super) unsafe trait TimRegInterface {
|
||||
/// All 24 TIM blocks are identical. This helper functions returns the correct
|
||||
/// memory mapped peripheral depending on the TIM ID.
|
||||
#[inline(always)]
|
||||
fn reg(&self) -> &TimRegBlock {
|
||||
fn reg_block(&self) -> &TimRegBlock {
|
||||
unsafe { &*Self::PORT_BASE.offset(self.tim_id() as isize) }
|
||||
}
|
||||
|
||||
@ -293,70 +335,16 @@ pub(super) unsafe trait TimRegInterface {
|
||||
}
|
||||
}
|
||||
|
||||
/// Provide a safe register interface for [`ValidTimAndPin`]s
|
||||
///
|
||||
/// This `struct` takes ownership of a [`ValidTimAndPin`] and provides an API to
|
||||
/// access the corresponding registers.
|
||||
pub(super) struct TimAndPinRegister<Pin: TimPin, Tim: ValidTim> {
|
||||
pin: Pin,
|
||||
tim: Tim,
|
||||
}
|
||||
|
||||
pub(super) struct TimRegister<TIM: ValidTim> {
|
||||
tim: TIM,
|
||||
}
|
||||
|
||||
impl<TIM: ValidTim> TimRegister<TIM> {
|
||||
#[inline]
|
||||
pub(super) unsafe fn new(tim: TIM) -> Self {
|
||||
TimRegister { tim }
|
||||
}
|
||||
|
||||
pub(super) fn release(self) -> TIM {
|
||||
self.tim
|
||||
}
|
||||
}
|
||||
|
||||
unsafe impl<TIM: ValidTim> TimRegInterface for TimRegister<TIM> {
|
||||
unsafe impl<Tim: ValidTim> TimRegInterface for Tim {
|
||||
fn tim_id(&self) -> u8 {
|
||||
TIM::TIM_ID
|
||||
Tim::TIM_ID
|
||||
}
|
||||
}
|
||||
|
||||
impl<PIN: TimPin, TIM: ValidTim> TimAndPinRegister<PIN, TIM>
|
||||
where
|
||||
(PIN, TIM): ValidTimAndPin<PIN, TIM>,
|
||||
{
|
||||
#[inline]
|
||||
pub(super) unsafe fn new(pin: PIN, tim: TIM) -> Self {
|
||||
TimAndPinRegister { pin, tim }
|
||||
}
|
||||
|
||||
pub(super) fn release(self) -> (PIN, TIM) {
|
||||
(self.pin, self.tim)
|
||||
}
|
||||
}
|
||||
|
||||
unsafe impl<PIN: TimPin, TIM: ValidTim> TimRegInterface for TimAndPinRegister<PIN, TIM> {
|
||||
#[inline(always)]
|
||||
fn tim_id(&self) -> u8 {
|
||||
TIM::TIM_ID
|
||||
}
|
||||
}
|
||||
|
||||
pub(super) struct TimDynRegister {
|
||||
tim_id: u8,
|
||||
pub(crate) struct TimDynRegister {
|
||||
pub(crate) tim_id: u8,
|
||||
#[allow(dead_code)]
|
||||
pin_id: DynPinId,
|
||||
}
|
||||
|
||||
impl<PIN: TimPin, TIM: ValidTim> From<TimAndPinRegister<PIN, TIM>> for TimDynRegister {
|
||||
fn from(_reg: TimAndPinRegister<PIN, TIM>) -> Self {
|
||||
Self {
|
||||
tim_id: TIM::TIM_ID,
|
||||
pin_id: PIN::DYN,
|
||||
}
|
||||
}
|
||||
pub(crate) pin_id: DynPinId,
|
||||
}
|
||||
|
||||
unsafe impl TimRegInterface for TimDynRegister {
|
||||
@ -371,8 +359,8 @@ unsafe impl TimRegInterface for TimDynRegister {
|
||||
//==================================================================================================
|
||||
|
||||
/// Hardware timers
|
||||
pub struct CountdownTimer<TIM: ValidTim> {
|
||||
tim: TimRegister<TIM>,
|
||||
pub struct CountdownTimer<Tim: ValidTim> {
|
||||
tim: Tim,
|
||||
curr_freq: Hertz,
|
||||
irq_cfg: Option<IrqCfg>,
|
||||
sys_clk: Hertz,
|
||||
@ -401,12 +389,12 @@ unsafe impl<TIM: ValidTim> TimRegInterface for CountdownTimer<TIM> {
|
||||
}
|
||||
}
|
||||
|
||||
impl<TIM: ValidTim> CountdownTimer<TIM> {
|
||||
impl<Tim: ValidTim> CountdownTimer<Tim> {
|
||||
/// Configures a TIM peripheral as a periodic count down timer
|
||||
pub fn new(syscfg: &mut pac::Sysconfig, sys_clk: impl Into<Hertz>, tim: TIM) -> Self {
|
||||
enable_tim_clk(syscfg, TIM::TIM_ID);
|
||||
pub fn new(syscfg: &mut pac::Sysconfig, sys_clk: impl Into<Hertz>, tim: Tim) -> Self {
|
||||
enable_tim_clk(syscfg, Tim::TIM_ID);
|
||||
let cd_timer = CountdownTimer {
|
||||
tim: unsafe { TimRegister::new(tim) },
|
||||
tim,
|
||||
sys_clk: sys_clk.into(),
|
||||
irq_cfg: None,
|
||||
rst_val: 0,
|
||||
@ -416,7 +404,7 @@ impl<TIM: ValidTim> CountdownTimer<TIM> {
|
||||
};
|
||||
cd_timer
|
||||
.tim
|
||||
.reg()
|
||||
.reg_block()
|
||||
.ctrl()
|
||||
.modify(|_, w| w.enable().set_bit());
|
||||
cd_timer
|
||||
@ -441,7 +429,7 @@ impl<TIM: ValidTim> CountdownTimer<TIM> {
|
||||
}
|
||||
if let Some(irq_sel) = irq_sel {
|
||||
irq_sel
|
||||
.tim0(TIM::TIM_ID as usize)
|
||||
.tim0(Tim::TIM_ID as usize)
|
||||
.write(|w| unsafe { w.bits(irq_cfg.irq as u32) });
|
||||
}
|
||||
}
|
||||
@ -460,7 +448,7 @@ impl<TIM: ValidTim> CountdownTimer<TIM> {
|
||||
Event::TimeOut => {
|
||||
enable_peripheral_clock(syscfg, PeripheralClocks::Irqsel);
|
||||
irqsel
|
||||
.tim0(TIM::TIM_ID as usize)
|
||||
.tim0(Tim::TIM_ID as usize)
|
||||
.write(|w| unsafe { w.bits(IRQ_DST_NONE) });
|
||||
self.disable_interrupt();
|
||||
self.listening = false;
|
||||
@ -470,25 +458,37 @@ impl<TIM: ValidTim> CountdownTimer<TIM> {
|
||||
|
||||
#[inline(always)]
|
||||
pub fn enable_interrupt(&mut self) {
|
||||
self.tim.reg().ctrl().modify(|_, w| w.irq_enb().set_bit());
|
||||
self.tim
|
||||
.reg_block()
|
||||
.ctrl()
|
||||
.modify(|_, w| w.irq_enb().set_bit());
|
||||
}
|
||||
|
||||
#[inline(always)]
|
||||
pub fn disable_interrupt(&mut self) {
|
||||
self.tim.reg().ctrl().modify(|_, w| w.irq_enb().clear_bit());
|
||||
self.tim
|
||||
.reg_block()
|
||||
.ctrl()
|
||||
.modify(|_, w| w.irq_enb().clear_bit());
|
||||
}
|
||||
|
||||
pub fn release(self, syscfg: &mut pac::Sysconfig) -> TIM {
|
||||
self.tim.reg().ctrl().write(|w| w.enable().clear_bit());
|
||||
pub fn release(self, syscfg: &mut pac::Sysconfig) -> Tim {
|
||||
self.tim
|
||||
.reg_block()
|
||||
.ctrl()
|
||||
.write(|w| w.enable().clear_bit());
|
||||
syscfg
|
||||
.tim_clk_enable()
|
||||
.modify(|r, w| unsafe { w.bits(r.bits() & !(1 << TIM::TIM_ID)) });
|
||||
self.tim.release()
|
||||
.modify(|r, w| unsafe { w.bits(r.bits() & !(1 << Tim::TIM_ID)) });
|
||||
self.tim
|
||||
}
|
||||
|
||||
/// Load the count down timer with a timeout but do not start it.
|
||||
pub fn load(&mut self, timeout: impl Into<Hertz>) {
|
||||
self.tim.reg().ctrl().modify(|_, w| w.enable().clear_bit());
|
||||
self.tim
|
||||
.reg_block()
|
||||
.ctrl()
|
||||
.modify(|_, w| w.enable().clear_bit());
|
||||
self.curr_freq = timeout.into();
|
||||
self.rst_val = self.sys_clk.raw() / self.curr_freq.raw();
|
||||
self.set_reload(self.rst_val);
|
||||
@ -497,17 +497,23 @@ impl<TIM: ValidTim> CountdownTimer<TIM> {
|
||||
|
||||
#[inline(always)]
|
||||
pub fn set_reload(&mut self, val: u32) {
|
||||
self.tim.reg().rst_value().write(|w| unsafe { w.bits(val) });
|
||||
self.tim
|
||||
.reg_block()
|
||||
.rst_value()
|
||||
.write(|w| unsafe { w.bits(val) });
|
||||
}
|
||||
|
||||
#[inline(always)]
|
||||
pub fn set_count(&mut self, val: u32) {
|
||||
self.tim.reg().cnt_value().write(|w| unsafe { w.bits(val) });
|
||||
self.tim
|
||||
.reg_block()
|
||||
.cnt_value()
|
||||
.write(|w| unsafe { w.bits(val) });
|
||||
}
|
||||
|
||||
#[inline(always)]
|
||||
pub fn count(&self) -> u32 {
|
||||
self.tim.reg().cnt_value().read().bits()
|
||||
self.tim.reg_block().cnt_value().read().bits()
|
||||
}
|
||||
|
||||
#[inline(always)]
|
||||
@ -518,24 +524,30 @@ impl<TIM: ValidTim> CountdownTimer<TIM> {
|
||||
unsafe { enable_interrupt(irq_cfg.irq) };
|
||||
}
|
||||
}
|
||||
self.tim.reg().enable().write(|w| unsafe { w.bits(1) });
|
||||
self.tim
|
||||
.reg_block()
|
||||
.enable()
|
||||
.write(|w| unsafe { w.bits(1) });
|
||||
}
|
||||
|
||||
#[inline(always)]
|
||||
pub fn disable(&mut self) {
|
||||
self.tim.reg().enable().write(|w| unsafe { w.bits(0) });
|
||||
self.tim
|
||||
.reg_block()
|
||||
.enable()
|
||||
.write(|w| unsafe { w.bits(0) });
|
||||
}
|
||||
|
||||
/// Disable the counter, setting both enable and active bit to 0
|
||||
pub fn auto_disable(self, enable: bool) -> Self {
|
||||
if enable {
|
||||
self.tim
|
||||
.reg()
|
||||
.reg_block()
|
||||
.ctrl()
|
||||
.modify(|_, w| w.auto_disable().set_bit());
|
||||
} else {
|
||||
self.tim
|
||||
.reg()
|
||||
.reg_block()
|
||||
.ctrl()
|
||||
.modify(|_, w| w.auto_disable().clear_bit());
|
||||
}
|
||||
@ -549,12 +561,12 @@ impl<TIM: ValidTim> CountdownTimer<TIM> {
|
||||
pub fn auto_deactivate(self, enable: bool) -> Self {
|
||||
if enable {
|
||||
self.tim
|
||||
.reg()
|
||||
.reg_block()
|
||||
.ctrl()
|
||||
.modify(|_, w| w.auto_deactivate().set_bit());
|
||||
} else {
|
||||
self.tim
|
||||
.reg()
|
||||
.reg_block()
|
||||
.ctrl()
|
||||
.modify(|_, w| w.auto_deactivate().clear_bit());
|
||||
}
|
||||
@ -563,7 +575,7 @@ impl<TIM: ValidTim> CountdownTimer<TIM> {
|
||||
|
||||
/// Configure the cascade parameters
|
||||
pub fn cascade_control(&mut self, ctrl: CascadeCtrl) {
|
||||
self.tim.reg().csd_ctrl().write(|w| {
|
||||
self.tim.reg_block().csd_ctrl().write(|w| {
|
||||
w.csden0().bit(ctrl.enb_start_src_csd0);
|
||||
w.csdinv0().bit(ctrl.inv_csd0);
|
||||
w.csden1().bit(ctrl.enb_start_src_csd1);
|
||||
@ -580,7 +592,7 @@ impl<TIM: ValidTim> CountdownTimer<TIM> {
|
||||
pub fn cascade_0_source(&mut self, src: CascadeSource) -> Result<(), InvalidCascadeSourceId> {
|
||||
let id = src.id()?;
|
||||
self.tim
|
||||
.reg()
|
||||
.reg_block()
|
||||
.cascade0()
|
||||
.write(|w| unsafe { w.cassel().bits(id) });
|
||||
Ok(())
|
||||
@ -589,7 +601,7 @@ impl<TIM: ValidTim> CountdownTimer<TIM> {
|
||||
pub fn cascade_1_source(&mut self, src: CascadeSource) -> Result<(), InvalidCascadeSourceId> {
|
||||
let id = src.id()?;
|
||||
self.tim
|
||||
.reg()
|
||||
.reg_block()
|
||||
.cascade1()
|
||||
.write(|w| unsafe { w.cassel().bits(id) });
|
||||
Ok(())
|
||||
@ -598,7 +610,7 @@ impl<TIM: ValidTim> CountdownTimer<TIM> {
|
||||
pub fn cascade_2_source(&mut self, src: CascadeSource) -> Result<(), InvalidCascadeSourceId> {
|
||||
let id = src.id()?;
|
||||
self.tim
|
||||
.reg()
|
||||
.reg_block()
|
||||
.cascade2()
|
||||
.write(|w| unsafe { w.cassel().bits(id) });
|
||||
Ok(())
|
||||
@ -627,7 +639,7 @@ impl<TIM: ValidTim> CountdownTimer<TIM> {
|
||||
/// Return `Ok` if the timer has wrapped. Peripheral will automatically clear the
|
||||
/// flag and restart the time if configured correctly
|
||||
pub fn wait(&mut self) -> nb::Result<(), void::Void> {
|
||||
let cnt = self.tim.reg().cnt_value().read().bits();
|
||||
let cnt = self.tim.reg_block().cnt_value().read().bits();
|
||||
if (cnt > self.last_cnt) || cnt == 0 {
|
||||
self.last_cnt = self.rst_val;
|
||||
Ok(())
|
||||
@ -639,10 +651,13 @@ impl<TIM: ValidTim> CountdownTimer<TIM> {
|
||||
|
||||
/// Returns [false] if the timer was not active, and true otherwise.
|
||||
pub fn cancel(&mut self) -> bool {
|
||||
if !self.tim.reg().ctrl().read().enable().bit_is_set() {
|
||||
if !self.tim.reg_block().ctrl().read().enable().bit_is_set() {
|
||||
return false;
|
||||
}
|
||||
self.tim.reg().ctrl().write(|w| w.enable().clear_bit());
|
||||
self.tim
|
||||
.reg_block()
|
||||
.ctrl()
|
||||
.write(|w| w.enable().clear_bit());
|
||||
true
|
||||
}
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user