UART embedded-io fixes
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@ -8,6 +8,14 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
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## [unreleased]
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## [unreleased]
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## [v0.11.1] 2025-03-10
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## Fixed
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- Fix `embedded_io` UART implementation to implement the documented contract properly.
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The implementation will now block until at least one byte is available or can be written, unless
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the send or receive buffer is empty.
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## [v0.11.0] 2025-03-07
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## [v0.11.0] 2025-03-07
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## Changed
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## Changed
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@ -253,6 +261,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
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- README with basic instructions how to set up own binary crate
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- README with basic instructions how to set up own binary crate
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[unreleased]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/compare/va108xx-hal-v0.11.0...HEAD
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[unreleased]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/compare/va108xx-hal-v0.11.0...HEAD
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[v0.11.1]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/compare/va108xx-hal-v0.11.0...va108xx-hal-v0.11.1
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[v0.11.0]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/compare/va108xx-hal-v0.10.0...va108xx-hal-v0.11.0
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[v0.11.0]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/compare/va108xx-hal-v0.10.0...va108xx-hal-v0.11.0
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[v0.10.0]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/compare/va108xx-hal-v0.9.0...va108xx-hal-v0.10.0
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[v0.10.0]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/compare/va108xx-hal-v0.9.0...va108xx-hal-v0.10.0
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[v0.9.0]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/compare/va108xx-hal-v0.8.0...va108xx-hal-v0.9.0
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[v0.9.0]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/compare/va108xx-hal-v0.8.0...va108xx-hal-v0.9.0
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@ -1,6 +1,6 @@
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[package]
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[package]
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name = "va108xx-hal"
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name = "va108xx-hal"
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version = "0.11.0"
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version = "0.11.1"
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authors = ["Robin Mueller <muellerr@irs.uni-stuttgart.de>"]
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authors = ["Robin Mueller <muellerr@irs.uni-stuttgart.de>"]
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edition = "2021"
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edition = "2021"
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description = "HAL for the Vorago VA108xx family of microcontrollers"
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description = "HAL for the Vorago VA108xx family of microcontrollers"
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@ -892,7 +892,15 @@ impl<Uart: Instance> embedded_hal_nb::serial::Read<u8> for Rx<Uart> {
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impl<Uart: Instance> embedded_io::Read for Rx<Uart> {
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impl<Uart: Instance> embedded_io::Read for Rx<Uart> {
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fn read(&mut self, buf: &mut [u8]) -> Result<usize, Self::Error> {
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fn read(&mut self, buf: &mut [u8]) -> Result<usize, Self::Error> {
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if buf.is_empty() {
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return Ok(0);
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}
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let mut read = 0;
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let mut read = 0;
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loop {
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if self.0.rxstatus().read().rdavl().bit_is_set() {
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break;
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}
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}
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for byte in buf.iter_mut() {
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for byte in buf.iter_mut() {
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match <Self as embedded_hal_nb::serial::Read<u8>>::read(self) {
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match <Self as embedded_hal_nb::serial::Read<u8>>::read(self) {
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Ok(w) => {
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Ok(w) => {
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@ -1058,6 +1066,14 @@ impl<Uart: Instance> embedded_hal_nb::serial::Write<u8> for Tx<Uart> {
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impl<Uart: Instance> embedded_io::Write for Tx<Uart> {
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impl<Uart: Instance> embedded_io::Write for Tx<Uart> {
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fn write(&mut self, buf: &[u8]) -> Result<usize, Self::Error> {
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fn write(&mut self, buf: &[u8]) -> Result<usize, Self::Error> {
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if buf.is_empty() {
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return Ok(0);
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}
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loop {
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if self.0.txstatus().read().wrrdy().bit_is_set() {
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break;
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}
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}
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let mut written = 0;
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let mut written = 0;
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for byte in buf.iter() {
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for byte in buf.iter() {
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match <Self as embedded_hal_nb::serial::Write<u8>>::write(self, *byte) {
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match <Self as embedded_hal_nb::serial::Write<u8>>::write(self, *byte) {
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@ -1066,7 +1082,7 @@ impl<Uart: Instance> embedded_io::Write for Tx<Uart> {
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}
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}
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}
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}
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Ok(buf.len())
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Ok(written)
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}
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}
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fn flush(&mut self) -> Result<(), Self::Error> {
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fn flush(&mut self) -> Result<(), Self::Error> {
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