Merge pull request 'bump PAC version' (#38) from bump-va108xx-version into main

Reviewed-on: #38

examples/rtic/Cargo.toml

@@ -22,5 +22,5 @@ rtic-sync = { version = "1.3", features = ["defmt-03"] }
 once_cell = {version = "1", default-features = false, features = ["critical-section"]}
 ringbuf = { version = "0.4.7", default-features = false, features = ["portable-atomic"] }
 
-va108xx-hal = { version = "0.8", path = "../../va108xx-hal" }
+va108xx-hal = { version = "0.9", path = "../../va108xx-hal" }
 vorago-reb1 = { path = "../../vorago-reb1" }

examples/simple/Cargo.toml

@@ -17,7 +17,7 @@ cortex-m-semihosting = "0.5.0"
 
 [dependencies.va108xx-hal]
 path = "../../va108xx-hal"
-version = "0.8"
+version = "0.9"
 features = ["rt", "defmt"]
 
 [dependencies.vorago-reb1]

va108xx-embassy/src/lib.rs

@@ -299,7 +299,7 @@ impl TimerDriver {
                         .cnt_value()
                         .write(|w| unsafe { w.bits(remaining_ticks.unwrap() as u32) });
                     alarm_tim.ctrl().modify(|_, w| w.irq_enb().set_bit());
-                    alarm_tim.enable().write(|w| unsafe { w.bits(1) })
+                    alarm_tim.enable().write(|w| unsafe { w.bits(1) });
                 }
             }
         })

va108xx-hal/Cargo.toml

@@ -1,6 +1,6 @@
 [package]
 name = "va108xx-hal"
-version = "0.8.0"
+version = "0.9.0"
 authors = ["Robin Mueller <muellerr@irs.uni-stuttgart.de>"]
 edition = "2021"
 description = "HAL for the Vorago VA108xx family of microcontrollers"
@@ -27,7 +27,7 @@ delegate = ">=0.12, <=0.13"
 thiserror = { version = "2", default-features = false }
 void = { version = "1", default-features = false }
 once_cell = {version = "1", default-features = false }
-va108xx = { version = "0.3", default-features = false, features = ["critical-section"] }
+va108xx = { version = "0.4", default-features = false, features = ["critical-section"] }
 embassy-sync = "0.6"
 
 defmt = { version = "0.3", optional = true }

va108xx-hal/src/clock.rs

@@ -39,13 +39,27 @@ pub fn get_sys_clock() -> Option<Hertz> {
 pub fn set_clk_div_register(syscfg: &mut va108xx::Sysconfig, clk_sel: FilterClkSel, div: u32) {
     match clk_sel {
         FilterClkSel::SysClk => (),
-        FilterClkSel::Clk1 => syscfg.ioconfig_clkdiv1().write(|w| unsafe { w.bits(div) }),
+        FilterClkSel::Clk1 => {
-        FilterClkSel::Clk2 => syscfg.ioconfig_clkdiv2().write(|w| unsafe { w.bits(div) }),
+            syscfg.ioconfig_clkdiv1().write(|w| unsafe { w.bits(div) });
-        FilterClkSel::Clk3 => syscfg.ioconfig_clkdiv3().write(|w| unsafe { w.bits(div) }),
+        }
-        FilterClkSel::Clk4 => syscfg.ioconfig_clkdiv4().write(|w| unsafe { w.bits(div) }),
+        FilterClkSel::Clk2 => {
-        FilterClkSel::Clk5 => syscfg.ioconfig_clkdiv5().write(|w| unsafe { w.bits(div) }),
+            syscfg.ioconfig_clkdiv2().write(|w| unsafe { w.bits(div) });
-        FilterClkSel::Clk6 => syscfg.ioconfig_clkdiv6().write(|w| unsafe { w.bits(div) }),
+        }
-        FilterClkSel::Clk7 => syscfg.ioconfig_clkdiv7().write(|w| unsafe { w.bits(div) }),
+        FilterClkSel::Clk3 => {
+            syscfg.ioconfig_clkdiv3().write(|w| unsafe { w.bits(div) });
+        }
+        FilterClkSel::Clk4 => {
+            syscfg.ioconfig_clkdiv4().write(|w| unsafe { w.bits(div) });
+        }
+        FilterClkSel::Clk5 => {
+            syscfg.ioconfig_clkdiv5().write(|w| unsafe { w.bits(div) });
+        }
+        FilterClkSel::Clk6 => {
+            syscfg.ioconfig_clkdiv6().write(|w| unsafe { w.bits(div) });
+        }
+        FilterClkSel::Clk7 => {
+            syscfg.ioconfig_clkdiv7().write(|w| unsafe { w.bits(div) });
+        }
     }
 }
 

va108xx-hal/src/gpio/reg.rs

@@ -304,7 +304,7 @@ pub(super) unsafe trait RegisterInterface {
         unsafe {
             portreg
                 .datamask()
-                .modify(|r, w| w.bits(r.bits() | self.mask_32()))
+                .modify(|r, w| w.bits(r.bits() | self.mask_32()));
         }
     }
 
@@ -316,7 +316,7 @@ pub(super) unsafe trait RegisterInterface {
         unsafe {
             portreg
                 .datamask()
-                .modify(|r, w| w.bits(r.bits() & !self.mask_32()))
+                .modify(|r, w| w.bits(r.bits() & !self.mask_32()));
         }
     }
 

va108xx-hal/src/i2c.rs

@@ -384,12 +384,12 @@ impl<I2c: Instance> I2cBase<I2c> {
             let (addr, addr_mode_mask) = Self::unwrap_addr(addr_b);
             self.i2c
                 .s0_addressb()
-                .write(|w| unsafe { w.bits((addr << 1) as u32 | addr_mode_mask) })
+                .write(|w| unsafe { w.bits((addr << 1) as u32 | addr_mode_mask) });
         }
         if let Some(addr_b_mask) = sl_cfg.addr_b_mask {
             self.i2c
                 .s0_addressmaskb()
-                .write(|w| unsafe { w.bits((addr_b_mask << 1) as u32) })
+                .write(|w| unsafe { w.bits((addr_b_mask << 1) as u32) });
         }
     }
 

va108xx-hal/src/spi.rs

@@ -789,7 +789,7 @@ where
     // initialization. Returns the amount of written bytes.
     fn initial_send_fifo_pumping_with_words(&self, words: &[Word]) -> usize {
         if self.blockmode {
-            self.spi.ctrl1().modify(|_, w| w.mtxpause().set_bit())
+            self.spi.ctrl1().modify(|_, w| w.mtxpause().set_bit());
         }
         // Fill the first half of the write FIFO
         let mut current_write_idx = 0;
@@ -803,7 +803,7 @@ where
             current_write_idx += 1;
         }
         if self.blockmode {
-            self.spi.ctrl1().modify(|_, w| w.mtxpause().clear_bit())
+            self.spi.ctrl1().modify(|_, w| w.mtxpause().clear_bit());
         }
         current_write_idx
     }
@@ -812,7 +812,7 @@ where
     // initialization.
     fn initial_send_fifo_pumping_with_fill_words(&self, send_len: usize) -> usize {
         if self.blockmode {
-            self.spi.ctrl1().modify(|_, w| w.mtxpause().set_bit())
+            self.spi.ctrl1().modify(|_, w| w.mtxpause().set_bit());
         }
         // Fill the first half of the write FIFO
         let mut current_write_idx = 0;
@@ -826,7 +826,7 @@ where
             current_write_idx += 1;
         }
         if self.blockmode {
-            self.spi.ctrl1().modify(|_, w| w.mtxpause().clear_bit())
+            self.spi.ctrl1().modify(|_, w| w.mtxpause().clear_bit());
         }
         current_write_idx
     }

va108xx-hal/src/sysconfig.rs

@@ -20,7 +20,7 @@ pub fn enable_rom_scrubbing(
 }
 
 pub fn disable_rom_scrubbing(syscfg: &mut pac::Sysconfig) {
-    syscfg.rom_scrub().write(|w| unsafe { w.bits(0) })
+    syscfg.rom_scrub().write(|w| unsafe { w.bits(0) });
 }
 
 /// Enable scrubbing for the RAM
@@ -39,7 +39,7 @@ pub fn enable_ram_scrubbing(
 }
 
 pub fn disable_ram_scrubbing(syscfg: &mut pac::Sysconfig) {
-    syscfg.ram_scrub().write(|w| unsafe { w.bits(0) })
+    syscfg.ram_scrub().write(|w| unsafe { w.bits(0) });
 }
 
 /// Clear the reset bit. This register is active low, so doing this will hold the peripheral

va108xx-hal/src/timer.rs

@@ -319,7 +319,7 @@ pub unsafe trait TimRegInterface {
             va108xx::Peripherals::steal()
                 .sysconfig
                 .tim_reset()
-                .modify(|r, w| w.bits(r.bits() & !self.mask_32()))
+                .modify(|r, w| w.bits(r.bits() & !self.mask_32()));
         }
     }
 
@@ -330,7 +330,7 @@ pub unsafe trait TimRegInterface {
             va108xx::Peripherals::steal()
                 .sysconfig
                 .tim_reset()
-                .modify(|r, w| w.bits(r.bits() | self.mask_32()))
+                .modify(|r, w| w.bits(r.bits() | self.mask_32()));
         }
     }
 }

vorago-reb1/Cargo.toml

@@ -20,7 +20,7 @@ max116xx-10bit = "0.3"
 
 [dependencies.va108xx-hal]
 path = "../va108xx-hal"
-version = ">=0.8, <0.9"
+version = "0.9"
 features = ["rt"]
 
 [features]