continue update package
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@ -18,3 +18,6 @@ cortex-m-semihosting = "0.5.0"
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[dependencies.va108xx-hal]
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path = "../../va108xx-hal"
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features = ["rt", "defmt"]
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[dependencies.vorago-reb1]
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path = "../../vorago-reb1"
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@ -16,7 +16,7 @@ use va108xx_hal::{
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pac::{self, interrupt},
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prelude::*,
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pwm::{default_ms_irq_handler, set_up_ms_tick},
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spi::{self, Spi, SpiBase, TransferConfig},
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spi::{self, Spi, SpiBase, SpiClkConfig, TransferConfigWithHwcs},
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IrqCfg,
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};
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@ -55,6 +55,8 @@ fn main() -> ! {
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dp.tim0,
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);
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let spi_clk_cfg = SpiClkConfig::from_clk(50.MHz(), SPI_SPEED_KHZ.kHz())
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.expect("creating SPI clock config failed");
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let spia_ref: RefCell<Option<SpiBase<pac::Spia, u8>>> = RefCell::new(None);
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let spib_ref: RefCell<Option<SpiBase<pac::Spib, u8>>> = RefCell::new(None);
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let pinsa = PinsA::new(&mut dp.sysconfig, None, dp.porta);
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@ -123,17 +125,21 @@ fn main() -> ! {
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match SPI_BUS_SEL {
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SpiBusSelect::SpiAPortA | SpiBusSelect::SpiAPortB => {
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if let Some(ref mut spi) = *spia_ref.borrow_mut() {
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let transfer_cfg =
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TransferConfig::new_no_hw_cs(SPI_SPEED_KHZ.kHz(), SPI_MODE, BLOCKMODE, false);
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let transfer_cfg = TransferConfigWithHwcs::new_no_hw_cs(
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Some(spi_clk_cfg),
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Some(SPI_MODE),
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BLOCKMODE,
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false,
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);
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spi.cfg_transfer(&transfer_cfg);
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}
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}
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SpiBusSelect::SpiBPortB => {
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if let Some(ref mut spi) = *spib_ref.borrow_mut() {
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let hw_cs_pin = pinsb.pb2.into_funsel_1();
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let transfer_cfg = TransferConfig::new(
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SPI_SPEED_KHZ.kHz(),
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SPI_MODE,
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let transfer_cfg = TransferConfigWithHwcs::new(
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Some(spi_clk_cfg),
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Some(SPI_MODE),
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Some(hw_cs_pin),
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BLOCKMODE,
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false,
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