continue update package
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13
Cargo.toml
13
Cargo.toml
@ -8,6 +8,7 @@ members = [
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"examples/rtic",
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"examples/embassy",
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"board-tests",
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"bootloader",
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]
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exclude = [
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@ -19,7 +20,8 @@ codegen-units = 1
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debug = 2
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debug-assertions = true # <-
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incremental = false
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opt-level = 'z' # <-
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# This is problematic for stepping..
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# opt-level = 'z' # <-
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overflow-checks = true # <-
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# cargo build/run --release
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@ -31,3 +33,12 @@ incremental = false
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lto = 'fat'
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opt-level = 3 # <-
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overflow-checks = false # <-
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[profile.small]
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inherits = "release"
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codegen-units = 1
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debug-assertions = false # <-
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lto = true
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opt-level = 'z' # <-
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overflow-checks = false # <-
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strip = true # Automatically strip symbols from the binary.
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25
bootloader/Cargo.toml
Normal file
25
bootloader/Cargo.toml
Normal file
@ -0,0 +1,25 @@
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[package]
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name = "bootloader"
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version = "0.1.0"
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edition = "2021"
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[dependencies]
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cortex-m = "0.7"
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cortex-m-rt = "0.7"
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embedded-hal = "1"
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embedded-hal-bus = "0.2"
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dummy-pin = "1"
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panic-rtt-target = { version = "0.1.3" }
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panic-halt = { version = "0.2" }
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rtt-target = { version = "0.5" }
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crc = "3"
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[dependencies.va108xx-hal]
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path = "../va108xx-hal"
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[dependencies.vorago-reb1]
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path = "../vorago-reb1"
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[features]
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default = []
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rtt-panic = []
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312
bootloader/src/main.rs
Normal file
312
bootloader/src/main.rs
Normal file
@ -0,0 +1,312 @@
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//! Vorago bootloader which can boot from two images.
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//!
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//! Bootloader memory map
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//!
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//! * <0x0> Bootloader start <code up to 0x3FFE bytes>
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//! * <0x3FFE> Bootloader CRC <halfword>
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//! * <0x4000> App image A start <code up to 0x1DFFC (~120K) bytes>
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//! * <0x21FFC> App image A CRC check length <halfword>
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//! * <0x21FFE> App image A CRC check value <halfword>
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//! * <0x22000> App image B start <code up to 0x1DFFC (~120K) bytes>
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//! * <0x3FFFC> App image B CRC check length <halfword>
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//! * <0x3FFFE> App image B CRC check value <halfword>
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//! * <0x40000> <end>
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//!
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//! As opposed to the Vorago example code, this bootloader assumes a 40 MHz external clock
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//! but does not scale that clock up.
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#![no_main]
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#![no_std]
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use cortex_m_rt::entry;
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use crc::{Crc, CRC_16_IBM_3740};
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use embedded_hal_bus::spi::{ExclusiveDevice, NoDelay};
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#[cfg(not(feature = "rtt-panic"))]
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use panic_halt as _;
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#[cfg(feature = "rtt-panic")]
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use panic_rtt_target as _;
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use rtt_target::{rprintln, rtt_init_print};
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use va108xx_hal::{
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pac,
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spi::{RomMiso, RomMosi, RomSck, Spi, SpiClkConfig, SpiConfig},
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time::Hertz,
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};
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use vorago_reb1::m95m01::M95M01;
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// Useful for debugging and see what the bootloader is doing. Enabled currently, because
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// the binary stays small enough.
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const RTT_PRINTOUT: bool = true;
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const DEBUG_PRINTOUTS: bool = false;
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// Dangerous option! An image with this option set to true will flash itself from RAM directly
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// into the NVM. This can be used as a recovery option from a direct RAM flash to fix the NVM
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// boot process. Please note that this will flash an image which will also always perform the
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// self-flash itself. It is recommended that you use a tool like probe-rs, Keil IDE, or a flash
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// loader to boot a bootloader without this feature.
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const FLASH_SELF: bool = false;
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// Register definitions for Cortex-M0 SCB register.
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pub const SCB_AIRCR_VECTKEY_POS: u32 = 16;
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pub const SCB_AIRCR_VECTKEY_MSK: u32 = 0xFFFF << SCB_AIRCR_VECTKEY_POS;
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pub const SCB_AIRCR_SYSRESETREQ_POS: u32 = 2;
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pub const SCB_AIRCR_SYSRESETREQ_MSK: u32 = 1 << SCB_AIRCR_SYSRESETREQ_POS;
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const CLOCK_FREQ: Hertz = Hertz::from_raw(50_000_000);
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// Important bootloader addresses and offsets, vector table information.
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const BOOTLOADER_START_ADDR: u32 = 0x0;
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const BOOTLOADER_CRC_ADDR: u32 = BOOTLOADER_END_ADDR - 2;
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// This is also the maximum size of the bootloader.
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const BOOTLOADER_END_ADDR: u32 = 0x3000;
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const APP_A_START_ADDR: u32 = 0x3000;
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const APP_A_SIZE_ADDR: u32 = APP_A_END_ADDR - 8;
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// Four bytes reserved, even when only 2 byte CRC is used. Leaves flexibility to switch to CRC32.
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const APP_A_CRC_ADDR: u32 = APP_A_END_ADDR - 4;
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pub const APP_A_END_ADDR: u32 = 0x11000;
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// The actual size of the image which is relevant for CRC calculation.
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const APP_B_START_ADDR: u32 = 0x11000;
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// The actual size of the image which is relevant for CRC calculation.
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const APP_B_SIZE_ADDR: u32 = APP_B_END_ADDR - 8;
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// Four bytes reserved, even when only 2 byte CRC is used. Leaves flexibility to switch to CRC32.
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const APP_B_CRC_ADDR: u32 = APP_B_END_ADDR - 4;
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pub const APP_B_END_ADDR: u32 = 0x20000;
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pub const APP_IMG_SZ: u32 = 0xE800;
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pub const VECTOR_TABLE_OFFSET: u32 = 0x0;
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pub const VECTOR_TABLE_LEN: u32 = 0xC0;
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pub const RESET_VECTOR_OFFSET: u32 = 0x4;
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const CRC_ALGO: Crc<u16> = Crc::<u16>::new(&CRC_16_IBM_3740);
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#[derive(Debug, Copy, Clone, PartialEq, Eq)]
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enum AppSel {
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A,
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B,
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}
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/// Complex type, but this is the price we pay for nice abstraction. It is also very explicit.
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pub type Nvm = M95M01<
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ExclusiveDevice<Spi<pac::Spic, (RomSck, RomMiso, RomMosi), u8>, dummy_pin::DummyPin, NoDelay>,
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>;
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#[entry]
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fn main() -> ! {
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if RTT_PRINTOUT {
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rtt_init_print!();
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rprintln!("-- VA108xx bootloader --");
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}
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let mut dp = pac::Peripherals::take().unwrap();
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let cp = cortex_m::Peripherals::take().unwrap();
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let spi = Spi::new(
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&mut dp.sysconfig,
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CLOCK_FREQ,
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dp.spic,
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(RomSck, RomMiso, RomMosi),
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// These values are taken from the vorago bootloader app, don't want to experiment here..
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SpiConfig::default().clk_cfg(SpiClkConfig::new(2, 4)),
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None,
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);
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let mut nvm =
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M95M01::new(ExclusiveDevice::new_no_delay(spi, dummy_pin::DummyPin::new_low()).unwrap())
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.expect("creating NVM structure failed");
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if FLASH_SELF {
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let mut first_four_bytes: [u8; 4] = [0; 4];
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read_four_bytes_at_addr_zero(&mut first_four_bytes);
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let bootloader_data = {
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unsafe {
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&*core::ptr::slice_from_raw_parts(
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(BOOTLOADER_START_ADDR + 4) as *const u8,
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(BOOTLOADER_END_ADDR - BOOTLOADER_START_ADDR - 6) as usize,
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)
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}
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};
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let mut digest = CRC_ALGO.digest();
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digest.update(&first_four_bytes);
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digest.update(bootloader_data);
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let bootloader_crc = digest.finalize();
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nvm.write(0x0, &first_four_bytes)
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.expect("writing to NVM failed");
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nvm.write(0x4, bootloader_data)
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.expect("writing to NVM failed");
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if let Err(e) = nvm.verify(0x0, &first_four_bytes) {
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if RTT_PRINTOUT {
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rprintln!("verification of self-flash to NVM failed: {:?}", e);
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}
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}
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if let Err(e) = nvm.verify(0x4, bootloader_data) {
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if RTT_PRINTOUT {
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rprintln!("verification of self-flash to NVM failed: {:?}", e);
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}
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}
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nvm.write(BOOTLOADER_CRC_ADDR, &bootloader_crc.to_be_bytes())
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.expect("writing CRC failed");
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if let Err(e) = nvm.verify(BOOTLOADER_CRC_ADDR, &bootloader_crc.to_be_bytes()) {
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if RTT_PRINTOUT {
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rprintln!(
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"error: CRC verification for bootloader self-flash failed: {:?}",
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e
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);
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}
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}
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}
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// Check bootloader's CRC (and write it if blank)
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check_own_crc(&dp.sysconfig, &cp, &mut nvm);
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if check_app_crc(AppSel::A) {
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boot_app(&dp.sysconfig, &cp, AppSel::A)
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} else if check_app_crc(AppSel::B) {
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boot_app(&dp.sysconfig, &cp, AppSel::B)
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} else {
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if DEBUG_PRINTOUTS && RTT_PRINTOUT {
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rprintln!("both images corrupt! booting image A");
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}
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// TODO: Shift a CCSDS packet out to inform host/OBC about image corruption.
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// Both images seem to be corrupt. Boot default image A.
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boot_app(&dp.sysconfig, &cp, AppSel::A)
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}
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}
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fn check_own_crc(sysconfig: &pac::Sysconfig, cp: &cortex_m::Peripherals, nvm: &mut Nvm) {
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let crc_exp = unsafe { (BOOTLOADER_CRC_ADDR as *const u16).read_unaligned().to_be() };
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// I'd prefer to use [core::slice::from_raw_parts], but that is problematic
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// because the address of the bootloader is 0x0, so the NULL check fails and the functions
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// panics.
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let mut first_four_bytes: [u8; 4] = [0; 4];
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read_four_bytes_at_addr_zero(&mut first_four_bytes);
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let mut digest = CRC_ALGO.digest();
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digest.update(&first_four_bytes);
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digest.update(unsafe {
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&*core::ptr::slice_from_raw_parts(
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(BOOTLOADER_START_ADDR + 4) as *const u8,
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(BOOTLOADER_END_ADDR - BOOTLOADER_START_ADDR - 6) as usize,
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)
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});
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let crc_calc = digest.finalize();
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if crc_exp == 0x0000 || crc_exp == 0xffff {
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if DEBUG_PRINTOUTS && RTT_PRINTOUT {
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rprintln!("BL CRC blank - prog new CRC");
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}
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// Blank CRC, write it to NVM.
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nvm.write(BOOTLOADER_CRC_ADDR, &crc_calc.to_be_bytes())
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.expect("writing CRC failed");
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// The Vorago bootloader resets here. I am not sure why this is done but I think it is
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// necessary because somehow the boot will not work if we just continue as usual.
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// cortex_m::peripheral::SCB::sys_reset();
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} else if crc_exp != crc_calc {
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// Bootloader is corrupted. Try to run App A.
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if DEBUG_PRINTOUTS && RTT_PRINTOUT {
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rprintln!(
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"bootloader CRC corrupt, read {} and expected {}. booting image A immediately",
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crc_calc,
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crc_exp
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);
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}
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// TODO: Shift out minimal CCSDS frame to notify about bootloader corruption.
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boot_app(sysconfig, cp, AppSel::A);
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}
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}
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// Reading from address 0x0 is problematic in Rust.
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// See https://users.rust-lang.org/t/reading-from-physical-address-0x0/117408/5.
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// This solution falls back to assembler to deal with this.
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fn read_four_bytes_at_addr_zero(buf: &mut [u8; 4]) {
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unsafe {
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core::arch::asm!(
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"ldr r0, [{0}]", // Load 4 bytes from src into r0 register
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"str r0, [{1}]", // Store r0 register into first_four_bytes
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in(reg) BOOTLOADER_START_ADDR as *const u8, // Input: src pointer (0x0)
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in(reg) buf as *mut [u8; 4], // Input: destination pointer
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);
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}
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}
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fn check_app_crc(app_sel: AppSel) -> bool {
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if DEBUG_PRINTOUTS && RTT_PRINTOUT {
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rprintln!("Checking image {:?}", app_sel);
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}
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if app_sel == AppSel::A {
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check_app_given_addr(APP_A_CRC_ADDR, APP_A_START_ADDR, APP_A_SIZE_ADDR)
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} else {
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check_app_given_addr(APP_B_CRC_ADDR, APP_B_START_ADDR, APP_B_SIZE_ADDR)
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}
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}
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fn check_app_given_addr(crc_addr: u32, start_addr: u32, image_size_addr: u32) -> bool {
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let crc_exp = unsafe { (crc_addr as *const u16).read_unaligned().to_be() };
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let image_size = unsafe { (image_size_addr as *const u32).read_unaligned().to_be() };
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// Sanity check.
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if image_size > APP_A_END_ADDR - APP_A_START_ADDR - 8 {
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if RTT_PRINTOUT {
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rprintln!("detected invalid app size {}", image_size);
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}
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return false;
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}
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let crc_calc = CRC_ALGO.checksum(unsafe {
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core::slice::from_raw_parts(start_addr as *const u8, image_size as usize)
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});
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if crc_calc == crc_exp {
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return true;
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}
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false
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}
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// The boot works by copying the interrupt vector table (IVT) of the respective app to the
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// base address in code RAM (0x0) and then performing a soft reset.
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fn boot_app(syscfg: &pac::Sysconfig, cp: &cortex_m::Peripherals, app_sel: AppSel) -> ! {
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if DEBUG_PRINTOUTS && RTT_PRINTOUT {
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rprintln!("booting app {:?}", app_sel);
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}
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// Disable ROM protection.
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syscfg.rom_prot().write(|w| unsafe { w.bits(1) });
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let base_addr = if app_sel == AppSel::A {
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APP_A_START_ADDR
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} else {
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APP_B_START_ADDR
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};
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// Clear all interrupts set.
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unsafe {
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cp.NVIC.icer[0].write(0xFFFFFFFF);
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cp.NVIC.icpr[0].write(0xFFFFFFFF);
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// First 4 bytes done with inline assembly, writing to the physical address 0x0 can not
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// be done without it. See https://users.rust-lang.org/t/reading-from-physical-address-0x0/117408/2.
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core::ptr::read(base_addr as *const u32);
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core::arch::asm!(
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"str {0}, [{1}]", // Load 4 bytes from src into r0 register
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in(reg) base_addr, // Input: App vector table.
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in(reg) BOOTLOADER_START_ADDR as *mut u32, // Input: destination pointer
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);
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core::slice::from_raw_parts_mut(
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(BOOTLOADER_START_ADDR + 4) as *mut u32,
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(VECTOR_TABLE_LEN - 4) as usize,
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)
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.copy_from_slice(core::slice::from_raw_parts(
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(base_addr + 4) as *const u32,
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(VECTOR_TABLE_LEN - 4) as usize,
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));
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}
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/* Disable re-loading from FRAM/code ROM on soft reset */
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syscfg
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.rst_cntl_rom()
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.modify(|_, w| w.sysrstreq().clear_bit());
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soft_reset(cp);
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}
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// Soft reset based on https://github.com/ARM-software/CMSIS_6/blob/5782d6f8057906d360f4b95ec08a2354afe5c9b9/CMSIS/Core/Include/core_cm0.h#L874.
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fn soft_reset(cp: &cortex_m::Peripherals) -> ! {
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// Ensure all outstanding memory accesses included buffered write are completed before reset.
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cortex_m::asm::dsb();
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unsafe {
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cp.SCB
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.aircr
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.write((0x5FA << SCB_AIRCR_VECTKEY_POS) | SCB_AIRCR_SYSRESETREQ_MSK);
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}
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// Ensure completion of memory access.
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cortex_m::asm::dsb();
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unreachable!();
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}
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@ -17,6 +17,9 @@ panic-rtt-target = { version = "0.1" }
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[dependencies.va108xx-hal]
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path = "../../va108xx-hal"
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[dependencies.vorago-reb1]
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path = "../../vorago-reb1"
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[dependencies.rtic]
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version = "2"
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features = ["thumbv6-backend"]
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@ -5,7 +5,7 @@
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#[rtic::app(device = pac)]
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mod app {
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use panic_rtt_target as _;
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use rtic_monotonics::systick::Systick;
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use rtic_example::SYSCLK_FREQ;
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use rtt_target::{rprintln, rtt_init_default, set_print_channel};
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use va108xx_hal::{
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clock::{set_clk_div_register, FilterClkSel},
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@ -17,6 +17,8 @@ mod app {
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use vorago_reb1::button::Button;
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use vorago_reb1::leds::Leds;
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rtic_monotonics::systick_monotonic!(Mono, 1_000);
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#[derive(Debug, PartialEq)]
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pub enum PressMode {
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Toggle,
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@ -44,17 +46,11 @@ mod app {
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struct Shared {}
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#[init]
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fn init(ctx: init::Context) -> (Shared, Local) {
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fn init(cx: init::Context) -> (Shared, Local) {
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let channels = rtt_init_default!();
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set_print_channel(channels.up.0);
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rprintln!("-- Vorago Button IRQ Example --");
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// Initialize the systick interrupt & obtain the token to prove that we did
|
||||
let systick_mono_token = rtic_monotonics::create_systick_token!();
|
||||
Systick::start(
|
||||
ctx.core.SYST,
|
||||
Hertz::from(50.MHz()).raw(),
|
||||
systick_mono_token,
|
||||
);
|
||||
Mono::start(cx.core.SYST, SYSCLK_FREQ.raw());
|
||||
|
||||
let mode = match CFG_MODE {
|
||||
// Ask mode from user via RTT
|
||||
@ -64,7 +60,7 @@ mod app {
|
||||
};
|
||||
rprintln!("Using {:?} mode", mode);
|
||||
|
||||
let mut dp = ctx.device;
|
||||
let mut dp = cx.device;
|
||||
let pinsa = PinsA::new(&mut dp.sysconfig, Some(dp.ioconfig), dp.porta);
|
||||
let edge_irq = match mode {
|
||||
PressMode::Toggle => InterruptEdge::HighToLow,
|
||||
@ -117,14 +113,12 @@ mod app {
|
||||
let mode = cx.local.mode;
|
||||
if *mode == PressMode::Toggle {
|
||||
leds[0].toggle();
|
||||
} else {
|
||||
if button.released() {
|
||||
} else if button.released() {
|
||||
leds[0].off();
|
||||
} else {
|
||||
leds[0].on();
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#[task(binds = OC0)]
|
||||
fn ms_tick(_cx: ms_tick::Context) {
|
||||
@ -138,14 +132,11 @@ mod app {
|
||||
let mut read;
|
||||
loop {
|
||||
read = down_channel.read(&mut read_buf);
|
||||
for i in 0..read {
|
||||
let val = read_buf[i] as char;
|
||||
if val == '0' || val == '1' {
|
||||
return if val == '0' {
|
||||
PressMode::Toggle
|
||||
} else {
|
||||
PressMode::Keep
|
||||
};
|
||||
for &byte in &read_buf[..read] {
|
||||
match byte as char {
|
||||
'0' => return PressMode::Toggle,
|
||||
'1' => return PressMode::Keep,
|
||||
_ => continue, // Ignore other characters
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -18,3 +18,6 @@ cortex-m-semihosting = "0.5.0"
|
||||
[dependencies.va108xx-hal]
|
||||
path = "../../va108xx-hal"
|
||||
features = ["rt", "defmt"]
|
||||
|
||||
[dependencies.vorago-reb1]
|
||||
path = "../../vorago-reb1"
|
||||
|
||||
@ -16,7 +16,7 @@ use va108xx_hal::{
|
||||
pac::{self, interrupt},
|
||||
prelude::*,
|
||||
pwm::{default_ms_irq_handler, set_up_ms_tick},
|
||||
spi::{self, Spi, SpiBase, TransferConfig},
|
||||
spi::{self, Spi, SpiBase, SpiClkConfig, TransferConfigWithHwcs},
|
||||
IrqCfg,
|
||||
};
|
||||
|
||||
@ -55,6 +55,8 @@ fn main() -> ! {
|
||||
dp.tim0,
|
||||
);
|
||||
|
||||
let spi_clk_cfg = SpiClkConfig::from_clk(50.MHz(), SPI_SPEED_KHZ.kHz())
|
||||
.expect("creating SPI clock config failed");
|
||||
let spia_ref: RefCell<Option<SpiBase<pac::Spia, u8>>> = RefCell::new(None);
|
||||
let spib_ref: RefCell<Option<SpiBase<pac::Spib, u8>>> = RefCell::new(None);
|
||||
let pinsa = PinsA::new(&mut dp.sysconfig, None, dp.porta);
|
||||
@ -123,17 +125,21 @@ fn main() -> ! {
|
||||
match SPI_BUS_SEL {
|
||||
SpiBusSelect::SpiAPortA | SpiBusSelect::SpiAPortB => {
|
||||
if let Some(ref mut spi) = *spia_ref.borrow_mut() {
|
||||
let transfer_cfg =
|
||||
TransferConfig::new_no_hw_cs(SPI_SPEED_KHZ.kHz(), SPI_MODE, BLOCKMODE, false);
|
||||
let transfer_cfg = TransferConfigWithHwcs::new_no_hw_cs(
|
||||
Some(spi_clk_cfg),
|
||||
Some(SPI_MODE),
|
||||
BLOCKMODE,
|
||||
false,
|
||||
);
|
||||
spi.cfg_transfer(&transfer_cfg);
|
||||
}
|
||||
}
|
||||
SpiBusSelect::SpiBPortB => {
|
||||
if let Some(ref mut spi) = *spib_ref.borrow_mut() {
|
||||
let hw_cs_pin = pinsb.pb2.into_funsel_1();
|
||||
let transfer_cfg = TransferConfig::new(
|
||||
SPI_SPEED_KHZ.kHz(),
|
||||
SPI_MODE,
|
||||
let transfer_cfg = TransferConfigWithHwcs::new(
|
||||
Some(spi_clk_cfg),
|
||||
Some(SPI_MODE),
|
||||
Some(hw_cs_pin),
|
||||
BLOCKMODE,
|
||||
false,
|
||||
|
||||
@ -26,6 +26,8 @@ use embedded_hal::spi::{Mode, MODE_0, MODE_1, MODE_2, MODE_3};
|
||||
// FIFO has a depth of 16.
|
||||
const FILL_DEPTH: usize = 12;
|
||||
|
||||
pub const DEFAULT_CLK_DIV: u16 = 2;
|
||||
|
||||
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
|
||||
pub enum HwChipSelectId {
|
||||
Id0 = 0,
|
||||
@ -221,6 +223,17 @@ hw_cs_pins!(
|
||||
|
||||
// SPIC
|
||||
|
||||
pub struct RomSck;
|
||||
pub struct RomMosi;
|
||||
pub struct RomMiso;
|
||||
|
||||
impl Sealed for RomSck {}
|
||||
impl PinSck<pac::Spic> for RomSck {}
|
||||
impl Sealed for RomMosi {}
|
||||
impl PinMosi<pac::Spic> for RomMosi {}
|
||||
impl Sealed for RomMiso {}
|
||||
impl PinMiso<pac::Spic> for RomMiso {}
|
||||
|
||||
hw_cs_pins!(
|
||||
pac::Spic, SpiPort::Portc:
|
||||
(PB9, AltFunc3, HwChipSelectId::Id1, HwCs1SpiCPortB0),
|
||||
@ -241,35 +254,28 @@ hw_cs_pins!(
|
||||
// Config
|
||||
//==================================================================================================
|
||||
|
||||
pub trait GenericTransferConfig {
|
||||
pub trait TransferConfigProvider {
|
||||
fn sod(&mut self, sod: bool);
|
||||
fn blockmode(&mut self, blockmode: bool);
|
||||
fn mode(&mut self, mode: Mode);
|
||||
fn frequency(&mut self, spi_clk: Hertz);
|
||||
fn clk_cfg(&mut self, clk_cfg: SpiClkConfig);
|
||||
fn hw_cs_id(&self) -> u8;
|
||||
}
|
||||
|
||||
/// This struct contains all configuration parameter which are transfer specific
|
||||
/// and might change for transfers to different SPI slaves
|
||||
#[derive(Copy, Clone)]
|
||||
pub struct TransferConfig<HwCs> {
|
||||
pub spi_clk: Hertz,
|
||||
pub mode: Mode,
|
||||
/// This only works if the Slave Output Disable (SOD) bit of the [`SpiConfig`] is set to
|
||||
/// false
|
||||
#[derive(Copy, Clone, Debug)]
|
||||
pub struct TransferConfigWithHwcs<HwCs> {
|
||||
pub hw_cs: Option<HwCs>,
|
||||
pub sod: bool,
|
||||
/// If this is enabled, all data in the FIFO is transmitted in a single frame unless
|
||||
/// the BMSTOP bit is set on a dataword. A frame is defined as CSn being active for the
|
||||
/// duration of multiple data words
|
||||
pub blockmode: bool,
|
||||
pub cfg: CommonTransferConfig,
|
||||
}
|
||||
|
||||
/// Type erased variant of the transfer configuration. This is required to avoid generics in
|
||||
/// the SPI constructor.
|
||||
pub struct ReducedTransferConfig {
|
||||
pub spi_clk: Hertz,
|
||||
pub mode: Mode,
|
||||
#[derive(Copy, Clone, Debug)]
|
||||
pub struct CommonTransferConfig {
|
||||
pub clk_cfg: Option<SpiClkConfig>,
|
||||
pub mode: Option<Mode>,
|
||||
pub sod: bool,
|
||||
/// If this is enabled, all data in the FIFO is transmitted in a single frame unless
|
||||
/// the BMSTOP bit is set on a dataword. A frame is defined as CSn being active for the
|
||||
@ -278,62 +284,67 @@ pub struct ReducedTransferConfig {
|
||||
pub hw_cs: HwChipSelectId,
|
||||
}
|
||||
|
||||
impl TransferConfig<NoneT> {
|
||||
pub fn new_no_hw_cs(spi_clk: impl Into<Hertz>, mode: Mode, blockmode: bool, sod: bool) -> Self {
|
||||
TransferConfig {
|
||||
spi_clk: spi_clk.into(),
|
||||
mode,
|
||||
impl TransferConfigWithHwcs<NoneT> {
|
||||
pub fn new_no_hw_cs(
|
||||
clk_cfg: Option<SpiClkConfig>,
|
||||
mode: Option<Mode>,
|
||||
blockmode: bool,
|
||||
sod: bool,
|
||||
) -> Self {
|
||||
TransferConfigWithHwcs {
|
||||
hw_cs: None,
|
||||
cfg: CommonTransferConfig {
|
||||
clk_cfg,
|
||||
mode,
|
||||
sod,
|
||||
blockmode,
|
||||
hw_cs: HwChipSelectId::Invalid,
|
||||
},
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
impl<HwCs: HwCsProvider> TransferConfig<HwCs> {
|
||||
impl<HwCs: HwCsProvider> TransferConfigWithHwcs<HwCs> {
|
||||
pub fn new(
|
||||
spi_clk: impl Into<Hertz>,
|
||||
mode: Mode,
|
||||
clk_cfg: Option<SpiClkConfig>,
|
||||
mode: Option<Mode>,
|
||||
hw_cs: Option<HwCs>,
|
||||
blockmode: bool,
|
||||
sod: bool,
|
||||
) -> Self {
|
||||
TransferConfig {
|
||||
spi_clk: spi_clk.into(),
|
||||
mode,
|
||||
TransferConfigWithHwcs {
|
||||
hw_cs,
|
||||
cfg: CommonTransferConfig {
|
||||
clk_cfg,
|
||||
mode,
|
||||
sod,
|
||||
blockmode,
|
||||
}
|
||||
}
|
||||
|
||||
pub fn downgrade(self) -> ReducedTransferConfig {
|
||||
ReducedTransferConfig {
|
||||
spi_clk: self.spi_clk,
|
||||
mode: self.mode,
|
||||
sod: self.sod,
|
||||
blockmode: self.blockmode,
|
||||
hw_cs: HwCs::CS_ID,
|
||||
}
|
||||
},
|
||||
}
|
||||
}
|
||||
|
||||
impl<HwCs: HwCsProvider> GenericTransferConfig for TransferConfig<HwCs> {
|
||||
pub fn downgrade(self) -> CommonTransferConfig {
|
||||
self.cfg
|
||||
}
|
||||
}
|
||||
|
||||
impl<HwCs: HwCsProvider> TransferConfigProvider for TransferConfigWithHwcs<HwCs> {
|
||||
/// Slave Output Disable
|
||||
fn sod(&mut self, sod: bool) {
|
||||
self.sod = sod;
|
||||
self.cfg.sod = sod;
|
||||
}
|
||||
|
||||
fn blockmode(&mut self, blockmode: bool) {
|
||||
self.blockmode = blockmode;
|
||||
self.cfg.blockmode = blockmode;
|
||||
}
|
||||
|
||||
fn mode(&mut self, mode: Mode) {
|
||||
self.mode = mode;
|
||||
self.cfg.mode = Some(mode);
|
||||
}
|
||||
|
||||
fn frequency(&mut self, spi_clk: Hertz) {
|
||||
self.spi_clk = spi_clk;
|
||||
fn clk_cfg(&mut self, clk_cfg: SpiClkConfig) {
|
||||
self.cfg.clk_cfg = Some(clk_cfg);
|
||||
}
|
||||
|
||||
fn hw_cs_id(&self) -> u8 {
|
||||
@ -341,26 +352,40 @@ impl<HwCs: HwCsProvider> GenericTransferConfig for TransferConfig<HwCs> {
|
||||
}
|
||||
}
|
||||
|
||||
#[derive(Default)]
|
||||
/// Configuration options for the whole SPI bus. See Programmer Guide p.92 for more details
|
||||
pub struct SpiConfig {
|
||||
/// Serial clock rate divider. Together with the CLKPRESCALE register, it determines
|
||||
/// the SPI clock rate in master mode. 0 by default. Specifying a higher value
|
||||
/// limits the maximum attainable SPI speed
|
||||
pub scrdv: u8,
|
||||
clk: SpiClkConfig,
|
||||
/// By default, configure SPI for master mode (ms == false)
|
||||
ms: bool,
|
||||
/// Slave output disable. Useful if separate GPIO pins or decoders are used for CS control
|
||||
sod: bool,
|
||||
pub slave_output_disable: bool,
|
||||
/// Loopback mode. If you use this, don't connect MISO to MOSI, they will be tied internally
|
||||
lbm: bool,
|
||||
pub loopback_mode: bool,
|
||||
/// Enable Master Delayer Capture Mode. See Programmers Guide p.92 for more details
|
||||
pub mdlycap: bool,
|
||||
pub master_delayer_capture: bool,
|
||||
}
|
||||
|
||||
impl Default for SpiConfig {
|
||||
fn default() -> Self {
|
||||
Self {
|
||||
// Default value is definitely valid.
|
||||
clk: SpiClkConfig::from_div(DEFAULT_CLK_DIV).unwrap(),
|
||||
ms: Default::default(),
|
||||
slave_output_disable: Default::default(),
|
||||
loopback_mode: Default::default(),
|
||||
master_delayer_capture: Default::default(),
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
impl SpiConfig {
|
||||
pub fn loopback(mut self, enable: bool) -> Self {
|
||||
self.lbm = enable;
|
||||
self.loopback_mode = enable;
|
||||
self
|
||||
}
|
||||
|
||||
pub fn clk_cfg(mut self, clk_cfg: SpiClkConfig) -> Self {
|
||||
self.clk = clk_cfg;
|
||||
self
|
||||
}
|
||||
|
||||
@ -370,7 +395,7 @@ impl SpiConfig {
|
||||
}
|
||||
|
||||
pub fn slave_output_disable(mut self, sod: bool) -> Self {
|
||||
self.sod = sod;
|
||||
self.slave_output_disable = sod;
|
||||
self
|
||||
}
|
||||
}
|
||||
@ -419,6 +444,119 @@ pub struct Spi<SpiInstance, Pins, Word = u8> {
|
||||
pins: Pins,
|
||||
}
|
||||
|
||||
pub fn mode_to_cpo_cph_bit(mode: embedded_hal::spi::Mode) -> (bool, bool) {
|
||||
match mode {
|
||||
embedded_hal::spi::MODE_0 => (false, false),
|
||||
embedded_hal::spi::MODE_1 => (false, true),
|
||||
embedded_hal::spi::MODE_2 => (true, false),
|
||||
embedded_hal::spi::MODE_3 => (true, true),
|
||||
}
|
||||
}
|
||||
|
||||
#[derive(Debug, Copy, Clone, PartialEq, Eq)]
|
||||
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
|
||||
pub struct SpiClkConfig {
|
||||
prescale_val: u16,
|
||||
scrdv: u8,
|
||||
}
|
||||
|
||||
impl SpiClkConfig {
|
||||
pub fn prescale_val(&self) -> u16 {
|
||||
self.prescale_val
|
||||
}
|
||||
pub fn scrdv(&self) -> u8 {
|
||||
self.scrdv
|
||||
}
|
||||
}
|
||||
|
||||
impl SpiClkConfig {
|
||||
pub fn new(prescale_val: u16, scrdv: u8) -> Self {
|
||||
Self {
|
||||
prescale_val,
|
||||
scrdv,
|
||||
}
|
||||
}
|
||||
|
||||
pub fn from_div(div: u16) -> Result<Self, SpiClkConfigError> {
|
||||
spi_clk_config_from_div(div)
|
||||
}
|
||||
|
||||
pub fn from_clk(sys_clk: impl Into<Hertz>, spi_clk: impl Into<Hertz>) -> Option<Self> {
|
||||
clk_div_for_target_clock(sys_clk, spi_clk).map(|div| spi_clk_config_from_div(div).unwrap())
|
||||
}
|
||||
}
|
||||
|
||||
#[derive(Debug)]
|
||||
pub enum SpiClkConfigError {
|
||||
DivIsZero,
|
||||
DivideValueNotEven,
|
||||
ScrdvValueTooLarge,
|
||||
}
|
||||
|
||||
#[inline]
|
||||
pub fn spi_clk_config_from_div(mut div: u16) -> Result<SpiClkConfig, SpiClkConfigError> {
|
||||
if div == 0 {
|
||||
return Err(SpiClkConfigError::DivIsZero);
|
||||
}
|
||||
if div % 2 != 0 {
|
||||
return Err(SpiClkConfigError::DivideValueNotEven);
|
||||
}
|
||||
let mut prescale_val = 0;
|
||||
|
||||
// find largest (even) prescale value that divides into div
|
||||
for i in (2..=0xfe).rev().step_by(2) {
|
||||
if div % i == 0 {
|
||||
prescale_val = i;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if prescale_val == 0 {
|
||||
return Err(SpiClkConfigError::DivideValueNotEven);
|
||||
}
|
||||
|
||||
div /= prescale_val;
|
||||
if div > u8::MAX as u16 + 1 {
|
||||
return Err(SpiClkConfigError::ScrdvValueTooLarge);
|
||||
}
|
||||
Ok(SpiClkConfig {
|
||||
prescale_val,
|
||||
scrdv: (div - 1) as u8,
|
||||
})
|
||||
}
|
||||
|
||||
#[inline]
|
||||
pub fn clk_div_for_target_clock(
|
||||
sys_clk: impl Into<Hertz>,
|
||||
spi_clk: impl Into<Hertz>,
|
||||
) -> Option<u16> {
|
||||
let spi_clk = spi_clk.into();
|
||||
let sys_clk = sys_clk.into();
|
||||
if spi_clk > sys_clk {
|
||||
return None;
|
||||
}
|
||||
|
||||
// Step 1: Calculate raw divider.
|
||||
let raw_div = sys_clk.raw() / spi_clk.raw();
|
||||
let remainder = sys_clk.raw() % spi_clk.raw();
|
||||
|
||||
// Step 2: Round up if necessary.
|
||||
let mut rounded_div = if remainder * 2 >= spi_clk.raw() {
|
||||
raw_div + 1
|
||||
} else {
|
||||
raw_div
|
||||
};
|
||||
|
||||
if rounded_div % 2 != 0 {
|
||||
// Take slower clock conservatively.
|
||||
rounded_div += 1;
|
||||
}
|
||||
if rounded_div > u16::MAX as u32 {
|
||||
return None;
|
||||
}
|
||||
Some(rounded_div as u16)
|
||||
}
|
||||
|
||||
// Re-export this so it can be used for the constructor
|
||||
pub use crate::typelevel::NoneT;
|
||||
|
||||
@ -453,59 +591,56 @@ where
|
||||
spi: SpiI,
|
||||
pins: (Sck, Miso, Mosi),
|
||||
spi_cfg: SpiConfig,
|
||||
transfer_cfg: Option<&ReducedTransferConfig>,
|
||||
transfer_cfg: Option<&CommonTransferConfig>,
|
||||
) -> Self {
|
||||
enable_peripheral_clock(syscfg, SpiI::PERIPH_SEL);
|
||||
let SpiConfig {
|
||||
scrdv,
|
||||
clk,
|
||||
ms,
|
||||
sod,
|
||||
lbm,
|
||||
mdlycap,
|
||||
slave_output_disable,
|
||||
loopback_mode,
|
||||
master_delayer_capture,
|
||||
} = spi_cfg;
|
||||
let mut mode = MODE_0;
|
||||
let mut clk_prescale = 0x02;
|
||||
let mut init_mode = embedded_hal::spi::MODE_0;
|
||||
let mut ss = 0;
|
||||
let mut init_blockmode = false;
|
||||
if let Some(transfer_cfg) = transfer_cfg {
|
||||
mode = transfer_cfg.mode;
|
||||
clk_prescale = sys_clk.into().raw() / (transfer_cfg.spi_clk.raw() * (scrdv as u32 + 1));
|
||||
if let Some(mode) = transfer_cfg.mode {
|
||||
init_mode = mode;
|
||||
}
|
||||
if transfer_cfg.hw_cs != HwChipSelectId::Invalid {
|
||||
ss = transfer_cfg.hw_cs as u8;
|
||||
}
|
||||
init_blockmode = transfer_cfg.blockmode;
|
||||
}
|
||||
|
||||
let (cpo_bit, cph_bit) = match mode {
|
||||
MODE_0 => (false, false),
|
||||
MODE_1 => (false, true),
|
||||
MODE_2 => (true, false),
|
||||
MODE_3 => (true, true),
|
||||
};
|
||||
let (cpo_bit, cph_bit) = mode_to_cpo_cph_bit(init_mode);
|
||||
spi.ctrl0().write(|w| {
|
||||
unsafe {
|
||||
w.size().bits(Word::word_reg());
|
||||
w.scrdv().bits(scrdv);
|
||||
w.scrdv().bits(clk.scrdv);
|
||||
// Clear clock phase and polarity. Will be set to correct value for each
|
||||
// transfer
|
||||
w.spo().bit(cpo_bit);
|
||||
w.sph().bit(cph_bit)
|
||||
}
|
||||
});
|
||||
|
||||
spi.ctrl1().write(|w| {
|
||||
w.lbm().bit(lbm);
|
||||
w.sod().bit(sod);
|
||||
w.lbm().bit(loopback_mode);
|
||||
w.sod().bit(slave_output_disable);
|
||||
w.ms().bit(ms);
|
||||
w.mdlycap().bit(mdlycap);
|
||||
w.mdlycap().bit(master_delayer_capture);
|
||||
w.blockmode().bit(init_blockmode);
|
||||
unsafe { w.ss().bits(ss) }
|
||||
});
|
||||
spi.clkprescale()
|
||||
.write(|w| unsafe { w.bits(clk.prescale_val as u32) });
|
||||
|
||||
spi.fifo_clr().write(|w| {
|
||||
w.rxfifo().set_bit();
|
||||
w.txfifo().set_bit()
|
||||
});
|
||||
spi.clkprescale().write(|w| unsafe { w.bits(clk_prescale) });
|
||||
// Enable the peripheral as the last step as recommended in the
|
||||
// programmers guide
|
||||
spi.ctrl1().modify(|_, w| w.enable().set_bit());
|
||||
@ -522,33 +657,33 @@ where
|
||||
}
|
||||
}
|
||||
|
||||
delegate::delegate! {
|
||||
to self.inner {
|
||||
#[inline]
|
||||
pub fn cfg_clock(&mut self, spi_clk: impl Into<Hertz>) {
|
||||
self.inner.cfg_clock(spi_clk);
|
||||
}
|
||||
pub fn cfg_clock(&mut self, cfg: SpiClkConfig);
|
||||
|
||||
#[inline]
|
||||
pub fn cfg_mode(&mut self, mode: Mode) {
|
||||
self.inner.cfg_mode(mode);
|
||||
pub fn cfg_clock_from_div(&mut self, div: u16) -> Result<(), SpiClkConfigError>;
|
||||
|
||||
#[inline]
|
||||
pub fn cfg_mode(&mut self, mode: Mode);
|
||||
|
||||
#[inline]
|
||||
pub fn perid(&self) -> u32;
|
||||
|
||||
#[inline]
|
||||
pub fn fill_word(&self) -> Word;
|
||||
|
||||
pub fn cfg_transfer<HwCs: OptionalHwCs<SpiI>>(
|
||||
&mut self, transfer_cfg: &TransferConfigWithHwcs<HwCs>
|
||||
);
|
||||
}
|
||||
}
|
||||
|
||||
pub fn set_fill_word(&mut self, fill_word: Word) {
|
||||
self.inner.fill_word = fill_word;
|
||||
}
|
||||
|
||||
pub fn fill_word(&self) -> Word {
|
||||
self.inner.fill_word
|
||||
}
|
||||
|
||||
#[inline]
|
||||
pub fn perid(&self) -> u32 {
|
||||
self.inner.perid()
|
||||
}
|
||||
|
||||
pub fn cfg_transfer<HwCs: OptionalHwCs<SpiI>>(&mut self, transfer_cfg: &TransferConfig<HwCs>) {
|
||||
self.inner.cfg_transfer(transfer_cfg);
|
||||
}
|
||||
|
||||
/// Releases the SPI peripheral and associated pins
|
||||
pub fn release(self) -> (SpiI, (Sck, Miso, Mosi), SpiConfig) {
|
||||
(self.inner.spi, self.pins, self.inner.cfg)
|
||||
@ -564,12 +699,20 @@ where
|
||||
<Word as TryFrom<u32>>::Error: core::fmt::Debug,
|
||||
{
|
||||
#[inline]
|
||||
pub fn cfg_clock(&mut self, spi_clk: impl Into<Hertz>) {
|
||||
let clk_prescale =
|
||||
self.sys_clk.raw() / (spi_clk.into().raw() * (self.cfg.scrdv as u32 + 1));
|
||||
pub fn cfg_clock(&mut self, cfg: SpiClkConfig) {
|
||||
self.spi
|
||||
.ctrl0()
|
||||
.modify(|_, w| unsafe { w.scrdv().bits(cfg.scrdv) });
|
||||
self.spi
|
||||
.clkprescale()
|
||||
.write(|w| unsafe { w.bits(clk_prescale) });
|
||||
.write(|w| unsafe { w.bits(cfg.prescale_val as u32) });
|
||||
}
|
||||
|
||||
#[inline]
|
||||
pub fn cfg_clock_from_div(&mut self, div: u16) -> Result<(), SpiClkConfigError> {
|
||||
let val = spi_clk_config_from_div(div)?;
|
||||
self.cfg_clock(val);
|
||||
Ok(())
|
||||
}
|
||||
|
||||
#[inline]
|
||||
@ -586,6 +729,11 @@ where
|
||||
});
|
||||
}
|
||||
|
||||
#[inline]
|
||||
pub fn fill_word(&self) -> Word {
|
||||
self.fill_word
|
||||
}
|
||||
|
||||
#[inline]
|
||||
pub fn clear_tx_fifo(&self) {
|
||||
self.spi.fifo_clr().write(|w| w.txfifo().set_bit());
|
||||
@ -629,13 +777,17 @@ where
|
||||
|
||||
pub fn cfg_transfer<HwCs: OptionalHwCs<SpiInstance>>(
|
||||
&mut self,
|
||||
transfer_cfg: &TransferConfig<HwCs>,
|
||||
transfer_cfg: &TransferConfigWithHwcs<HwCs>,
|
||||
) {
|
||||
self.cfg_clock(transfer_cfg.spi_clk);
|
||||
self.cfg_mode(transfer_cfg.mode);
|
||||
self.blockmode = transfer_cfg.blockmode;
|
||||
if let Some(trans_clk_div) = transfer_cfg.cfg.clk_cfg {
|
||||
self.cfg_clock(trans_clk_div);
|
||||
}
|
||||
if let Some(mode) = transfer_cfg.cfg.mode {
|
||||
self.cfg_mode(mode);
|
||||
}
|
||||
self.blockmode = transfer_cfg.cfg.blockmode;
|
||||
self.spi.ctrl1().modify(|_, w| {
|
||||
if transfer_cfg.sod {
|
||||
if transfer_cfg.cfg.sod {
|
||||
w.sod().set_bit();
|
||||
} else if transfer_cfg.hw_cs.is_some() {
|
||||
w.sod().clear_bit();
|
||||
@ -645,7 +797,7 @@ where
|
||||
} else {
|
||||
w.sod().clear_bit();
|
||||
}
|
||||
if transfer_cfg.blockmode {
|
||||
if transfer_cfg.cfg.blockmode {
|
||||
w.blockmode().set_bit();
|
||||
} else {
|
||||
w.blockmode().clear_bit();
|
||||
@ -682,34 +834,52 @@ where
|
||||
.unwrap()
|
||||
}
|
||||
|
||||
fn flush_internal(&self) {
|
||||
let mut status_reg = self.spi.status().read();
|
||||
while status_reg.tfe().bit_is_clear()
|
||||
|| status_reg.rne().bit_is_set()
|
||||
|| status_reg.busy().bit_is_set()
|
||||
{
|
||||
if status_reg.rne().bit_is_set() {
|
||||
self.read_single_word();
|
||||
}
|
||||
status_reg = self.spi.status().read();
|
||||
}
|
||||
}
|
||||
|
||||
fn transfer_preparation(&self, words: &[Word]) -> Result<(), Infallible> {
|
||||
if words.is_empty() {
|
||||
return Ok(());
|
||||
}
|
||||
let mut status_reg = self.spi.status().read();
|
||||
// Wait until all bytes have been transferred.
|
||||
while status_reg.tfe().bit_is_clear() {
|
||||
// Ignore all received read words.
|
||||
if status_reg.rne().bit_is_set() {
|
||||
self.clear_rx_fifo();
|
||||
}
|
||||
status_reg = self.spi.status().read();
|
||||
}
|
||||
// Ignore all received read words.
|
||||
if status_reg.rne().bit_is_set() {
|
||||
self.clear_rx_fifo();
|
||||
}
|
||||
self.flush_internal();
|
||||
Ok(())
|
||||
}
|
||||
|
||||
fn initial_send_fifo_pumping(&self, words: Option<&[Word]>) -> usize {
|
||||
// Returns the actual bytes sent.
|
||||
fn initial_send_fifo_pumping_with_words(&self, words: &[Word]) -> usize {
|
||||
if self.blockmode {
|
||||
self.spi.ctrl1().modify(|_, w| w.mtxpause().set_bit())
|
||||
}
|
||||
// Fill the first half of the write FIFO
|
||||
let mut current_write_idx = 0;
|
||||
for _ in 0..core::cmp::min(FILL_DEPTH, words.map_or(0, |words| words.len())) {
|
||||
self.send_blocking(words.map_or(self.fill_word, |words| words[current_write_idx]));
|
||||
for _ in 0..core::cmp::min(FILL_DEPTH, words.len()) {
|
||||
self.send_blocking(words[current_write_idx]);
|
||||
current_write_idx += 1;
|
||||
}
|
||||
if self.blockmode {
|
||||
self.spi.ctrl1().modify(|_, w| w.mtxpause().clear_bit())
|
||||
}
|
||||
current_write_idx
|
||||
}
|
||||
|
||||
fn initial_send_fifo_pumping_with_fill_words(&self, send_len: usize) -> usize {
|
||||
if self.blockmode {
|
||||
self.spi.ctrl1().modify(|_, w| w.mtxpause().set_bit())
|
||||
}
|
||||
// Fill the first half of the write FIFO
|
||||
let mut current_write_idx = 0;
|
||||
for _ in 0..core::cmp::min(FILL_DEPTH, send_len) {
|
||||
self.send_blocking(self.fill_word);
|
||||
current_write_idx += 1;
|
||||
}
|
||||
if self.blockmode {
|
||||
@ -778,7 +948,7 @@ where
|
||||
fn read(&mut self, words: &mut [Word]) -> Result<(), Self::Error> {
|
||||
self.transfer_preparation(words)?;
|
||||
let mut current_read_idx = 0;
|
||||
let mut current_write_idx = self.initial_send_fifo_pumping(None);
|
||||
let mut current_write_idx = self.initial_send_fifo_pumping_with_fill_words(words.len());
|
||||
loop {
|
||||
if current_write_idx < words.len() {
|
||||
self.send_blocking(self.fill_word);
|
||||
@ -797,7 +967,7 @@ where
|
||||
|
||||
fn write(&mut self, words: &[Word]) -> Result<(), Self::Error> {
|
||||
self.transfer_preparation(words)?;
|
||||
let mut current_write_idx = self.initial_send_fifo_pumping(Some(words));
|
||||
let mut current_write_idx = self.initial_send_fifo_pumping_with_words(words);
|
||||
while current_write_idx < words.len() {
|
||||
self.send_blocking(words[current_write_idx]);
|
||||
current_write_idx += 1;
|
||||
@ -812,7 +982,7 @@ where
|
||||
fn transfer(&mut self, read: &mut [Word], write: &[Word]) -> Result<(), Self::Error> {
|
||||
self.transfer_preparation(write)?;
|
||||
let mut current_read_idx = 0;
|
||||
let mut current_write_idx = self.initial_send_fifo_pumping(Some(write));
|
||||
let mut current_write_idx = self.initial_send_fifo_pumping_with_words(write);
|
||||
while current_read_idx < read.len() || current_write_idx < write.len() {
|
||||
if current_write_idx < write.len() {
|
||||
self.send_blocking(write[current_write_idx]);
|
||||
@ -830,7 +1000,7 @@ where
|
||||
fn transfer_in_place(&mut self, words: &mut [Word]) -> Result<(), Self::Error> {
|
||||
self.transfer_preparation(words)?;
|
||||
let mut current_read_idx = 0;
|
||||
let mut current_write_idx = self.initial_send_fifo_pumping(Some(words));
|
||||
let mut current_write_idx = self.initial_send_fifo_pumping_with_words(words);
|
||||
|
||||
while current_read_idx < words.len() || current_write_idx < words.len() {
|
||||
if current_write_idx < words.len() {
|
||||
@ -846,12 +1016,7 @@ where
|
||||
}
|
||||
|
||||
fn flush(&mut self) -> Result<(), Self::Error> {
|
||||
let status_reg = self.spi.status().read();
|
||||
while status_reg.tfe().bit_is_clear() || status_reg.rne().bit_is_set() {
|
||||
if status_reg.rne().bit_is_set() {
|
||||
self.read_single_word();
|
||||
}
|
||||
}
|
||||
self.flush_internal();
|
||||
Ok(())
|
||||
}
|
||||
}
|
||||
@ -877,23 +1042,13 @@ impl<
|
||||
where
|
||||
<Word as TryFrom<u32>>::Error: core::fmt::Debug,
|
||||
{
|
||||
fn read(&mut self, words: &mut [Word]) -> Result<(), Self::Error> {
|
||||
self.inner.read(words)
|
||||
}
|
||||
|
||||
fn write(&mut self, words: &[Word]) -> Result<(), Self::Error> {
|
||||
self.inner.write(words)
|
||||
}
|
||||
|
||||
fn transfer(&mut self, read: &mut [Word], write: &[Word]) -> Result<(), Self::Error> {
|
||||
self.inner.transfer(read, write)
|
||||
}
|
||||
|
||||
fn transfer_in_place(&mut self, words: &mut [Word]) -> Result<(), Self::Error> {
|
||||
self.inner.transfer_in_place(words)
|
||||
}
|
||||
|
||||
fn flush(&mut self) -> Result<(), Self::Error> {
|
||||
self.inner.flush()
|
||||
delegate::delegate! {
|
||||
to self.inner {
|
||||
fn read(&mut self, words: &mut [Word]) -> Result<(), Self::Error>;
|
||||
fn write(&mut self, words: &[Word]) -> Result<(), Self::Error>;
|
||||
fn transfer(&mut self, read: &mut [Word], write: &[Word]) -> Result<(), Self::Error>;
|
||||
fn transfer_in_place(&mut self, words: &mut [Word]) -> Result<(), Self::Error>;
|
||||
fn flush(&mut self) -> Result<(), Self::Error>;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
@ -14,12 +14,15 @@ categories = ["aerospace", "embedded", "no-std", "hardware-support"]
|
||||
cortex-m = { version = "0.7", features = ["critical-section-single-core"] }
|
||||
cortex-m-rt = "0.7"
|
||||
embedded-hal = "1"
|
||||
nb = "1"
|
||||
bitfield = "0.17"
|
||||
|
||||
[dependencies.max116xx-10bit]
|
||||
version = "0.3"
|
||||
|
||||
[dependencies.va108xx-hal]
|
||||
version = "0.7"
|
||||
version = ">=0.7, <0.8"
|
||||
path = "../va108xx-hal"
|
||||
features = ["rt"]
|
||||
|
||||
[features]
|
||||
@ -28,20 +31,8 @@ rt = ["va108xx-hal/rt"]
|
||||
[dev-dependencies]
|
||||
panic-halt = "0.2"
|
||||
nb = "1"
|
||||
|
||||
[dev-dependencies.rtt-target]
|
||||
version = "0.5"
|
||||
|
||||
[dev-dependencies.panic-rtt-target]
|
||||
version = "0.1"
|
||||
|
||||
[dev-dependencies.rtic]
|
||||
version = "2"
|
||||
features = ["thumbv6-backend"]
|
||||
|
||||
[dev-dependencies.rtic-monotonics]
|
||||
version = "1"
|
||||
features = ["cortex-m-systick"]
|
||||
rtt-target = "0.5"
|
||||
panic-rtt-target = "0.1"
|
||||
|
||||
[package.metadata.docs.rs]
|
||||
all-features = true
|
||||
|
||||
@ -9,11 +9,12 @@ use embedded_hal::spi::SpiBus;
|
||||
use embedded_hal::{delay::DelayNs, digital::OutputPin};
|
||||
use panic_rtt_target as _;
|
||||
use rtt_target::{rprintln, rtt_init_print};
|
||||
use va108xx_hal::spi::SpiClkConfig;
|
||||
use va108xx_hal::{
|
||||
gpio::PinsA,
|
||||
pac,
|
||||
prelude::*,
|
||||
spi::{Spi, SpiConfig, TransferConfig},
|
||||
spi::{Spi, SpiConfig, TransferConfigWithHwcs},
|
||||
timer::set_up_ms_delay_provider,
|
||||
};
|
||||
|
||||
@ -45,9 +46,9 @@ fn main() -> ! {
|
||||
.set_high()
|
||||
.expect("Setting ADC chip select high failed");
|
||||
|
||||
let transfer_cfg = TransferConfig::new(
|
||||
1.MHz(),
|
||||
embedded_hal::spi::MODE_3,
|
||||
let transfer_cfg = TransferConfigWithHwcs::new(
|
||||
Some(SpiClkConfig::from_clk(50.MHz(), 1.MHz()).expect("creating SPI clock config failed")),
|
||||
Some(embedded_hal::spi::MODE_3),
|
||||
Some(cs_pin),
|
||||
false,
|
||||
true,
|
||||
|
||||
@ -15,13 +15,13 @@ use max116xx_10bit::VoltageRefMode;
|
||||
use max116xx_10bit::{AveragingConversions, AveragingResults};
|
||||
use panic_rtt_target as _;
|
||||
use rtt_target::{rprintln, rtt_init_print};
|
||||
use va108xx_hal::spi::{NoneT, OptionalHwCs};
|
||||
use va108xx_hal::spi::{OptionalHwCs, SpiClkConfig};
|
||||
use va108xx_hal::timer::CountDownTimer;
|
||||
use va108xx_hal::{
|
||||
gpio::PinsA,
|
||||
pac::{self, interrupt},
|
||||
prelude::*,
|
||||
spi::{Spi, SpiBase, SpiConfig, TransferConfig},
|
||||
spi::{Spi, SpiBase, SpiConfig, TransferConfigWithHwcs},
|
||||
timer::{default_ms_irq_handler, set_up_ms_tick, DelayMs, IrqCfg},
|
||||
};
|
||||
use va108xx_hal::{port_mux, FunSel, PortSel};
|
||||
@ -103,6 +103,8 @@ impl<Delay: DelayNs, HwCs: OptionalHwCs<pac::Spib>> SpiDevice for SpiWithHwCs<De
|
||||
}
|
||||
}
|
||||
|
||||
const SYS_CLK: Hertz = Hertz::from_raw(50_000_000);
|
||||
|
||||
#[entry]
|
||||
fn main() -> ! {
|
||||
rtt_init_print!();
|
||||
@ -113,7 +115,7 @@ fn main() -> ! {
|
||||
IrqCfg::new(pac::Interrupt::OC0, true, true),
|
||||
&mut dp.sysconfig,
|
||||
Some(&mut dp.irqsel),
|
||||
50.MHz(),
|
||||
SYS_CLK,
|
||||
dp.tim0,
|
||||
);
|
||||
let delay = DelayMs::new(tim0).unwrap();
|
||||
@ -141,7 +143,12 @@ fn main() -> ! {
|
||||
.set_high()
|
||||
.expect("Setting accelerometer chip select high failed");
|
||||
|
||||
let transfer_cfg = TransferConfig::<NoneT>::new(3.MHz(), spi::MODE_0, None, true, false);
|
||||
let transfer_cfg = TransferConfigWithHwcs::new_no_hw_cs(
|
||||
Some(SpiClkConfig::from_clk(SYS_CLK, 3.MHz()).unwrap()),
|
||||
Some(spi::MODE_0),
|
||||
true,
|
||||
false,
|
||||
);
|
||||
let spi = Spi::new(
|
||||
&mut dp.sysconfig,
|
||||
50.MHz(),
|
||||
|
||||
@ -3,5 +3,6 @@
|
||||
|
||||
pub mod button;
|
||||
pub mod leds;
|
||||
pub mod m95m01;
|
||||
pub mod max11619;
|
||||
pub mod temp_sensor;
|
||||
|
||||
138
vorago-reb1/src/m95m01.rs
Normal file
138
vorago-reb1/src/m95m01.rs
Normal file
@ -0,0 +1,138 @@
|
||||
use embedded_hal::spi::SpiDevice;
|
||||
|
||||
bitfield::bitfield! {
|
||||
pub struct StatusReg(u8);
|
||||
impl Debug;
|
||||
u8;
|
||||
status_register_write_protect, _: 7, 0;
|
||||
block_protection_bits, set_block_protection_bits: 3, 2;
|
||||
write_enable_latch, _: 1;
|
||||
write_in_progress, _: 0;
|
||||
}
|
||||
|
||||
// Registers.
|
||||
pub mod regs {
|
||||
/// Write status register command.
|
||||
pub const WRSR: u8 = 0x01;
|
||||
// Write command.
|
||||
pub const WRITE: u8 = 0x02;
|
||||
// Read command.
|
||||
pub const READ: u8 = 0x03;
|
||||
/// Write disable command.
|
||||
pub const WRDI: u8 = 0x04;
|
||||
/// Read status register command.
|
||||
pub const RDSR: u8 = 0x05;
|
||||
/// Write enable command.
|
||||
pub const WREN: u8 = 0x06;
|
||||
}
|
||||
|
||||
use regs::*;
|
||||
|
||||
/// Driver for the ST device M95M01 EEPROM memory.
|
||||
pub struct M95M01<Spi: SpiDevice> {
|
||||
spi: Spi,
|
||||
}
|
||||
|
||||
pub enum Error<SpiError> {
|
||||
Spi(SpiError),
|
||||
BufTooShort,
|
||||
}
|
||||
|
||||
impl<SpiError> From<SpiError> for Error<SpiError> {
|
||||
fn from(value: SpiError) -> Self {
|
||||
Self::Spi(value)
|
||||
}
|
||||
}
|
||||
|
||||
impl<Spi: SpiDevice> M95M01<Spi> {
|
||||
pub fn new(spi: Spi) -> Result<Self, Spi::Error> {
|
||||
let mut spi_dev = Self { spi };
|
||||
spi_dev.clear_block_protection()?;
|
||||
Ok(spi_dev)
|
||||
}
|
||||
|
||||
pub fn release(mut self) -> Result<Spi, Spi::Error> {
|
||||
self.set_block_protection()?;
|
||||
Ok(self.spi)
|
||||
}
|
||||
|
||||
// Wait until the write-in-progress state is cleared. This exposes a [nb] API, so this function
|
||||
// will return [nb::Error::WouldBlock] if the EEPROM is still busy.
|
||||
pub fn writes_are_done(&mut self) -> nb::Result<(), Spi::Error> {
|
||||
let mut read: [u8; 2] = [0; 2];
|
||||
self.spi.transfer(&mut read, &[regs::RDSR, 0x00])?;
|
||||
let rdsr = StatusReg(read[1]);
|
||||
if rdsr.write_in_progress() {
|
||||
return Err(nb::Error::WouldBlock);
|
||||
}
|
||||
Ok(())
|
||||
}
|
||||
|
||||
pub fn write_enable(&mut self) -> Result<(), Spi::Error> {
|
||||
self.spi.write(&[regs::WREN])
|
||||
}
|
||||
|
||||
pub fn clear_block_protection(&mut self) -> Result<(), Spi::Error> {
|
||||
self.spi.write(&[WREN, WRSR, 0x00])
|
||||
}
|
||||
|
||||
pub fn set_block_protection(&mut self) -> Result<(), Spi::Error> {
|
||||
let mut reg = StatusReg(0);
|
||||
reg.set_block_protection_bits(0b11);
|
||||
self.spi.write(&[WREN, WRSR, reg.0])
|
||||
}
|
||||
|
||||
pub fn write(&mut self, address: u32, data: &[u8]) -> Result<(), Spi::Error> {
|
||||
self.write_enable()?;
|
||||
self.spi.write(&[
|
||||
WRITE,
|
||||
((address >> 16) & 0xff) as u8,
|
||||
((address >> 8) & 0xff) as u8,
|
||||
(address & 0xff) as u8,
|
||||
])?;
|
||||
self.spi.write(data)?;
|
||||
Ok(())
|
||||
}
|
||||
|
||||
pub fn read(
|
||||
&mut self,
|
||||
address: u32,
|
||||
size: usize,
|
||||
buf: &mut [u8],
|
||||
) -> Result<(), Error<Spi::Error>> {
|
||||
if buf.len() < size {
|
||||
return Err(Error::BufTooShort);
|
||||
}
|
||||
self.spi.write(&[
|
||||
READ,
|
||||
((address >> 16) & 0xff) as u8,
|
||||
((address >> 8) & 0xff) as u8,
|
||||
(address & 0xff) as u8,
|
||||
])?;
|
||||
self.spi.read(&mut buf[0..size])?;
|
||||
Ok(())
|
||||
}
|
||||
|
||||
pub fn verify(&mut self, address: u32, data: &[u8]) -> Result<bool, Spi::Error> {
|
||||
// Write the read command and address
|
||||
self.spi.write(&[
|
||||
READ,
|
||||
((address >> 16) & 0xff) as u8,
|
||||
((address >> 8) & 0xff) as u8,
|
||||
(address & 0xff) as u8,
|
||||
])?;
|
||||
|
||||
// Read and compare each byte in place
|
||||
for original_byte in data.iter() {
|
||||
let mut read_byte = [0u8];
|
||||
self.spi.read(&mut read_byte)?;
|
||||
|
||||
// Compare read byte with original
|
||||
if read_byte[0] != *original_byte {
|
||||
return Ok(false);
|
||||
}
|
||||
}
|
||||
|
||||
Ok(true)
|
||||
}
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user