New VA108xx Rust workspace structure + dependency updates

- The workspace is now a monorepo without submodules. The HAL, PAC and BSP
  are integrated directly
- Update all dependencies: embedded-hal v1 and RTIC v2

va108xx/src/generic.rs

@@ -0,0 +1,618 @@
+use core::marker;
+#[doc = " Raw register type (`u8`, `u16`, `u32`, ...)"]
+pub trait RawReg:
+    Copy
+    + Default
+    + From<bool>
+    + core::ops::BitOr<Output = Self>
+    + core::ops::BitAnd<Output = Self>
+    + core::ops::BitOrAssign
+    + core::ops::BitAndAssign
+    + core::ops::Not<Output = Self>
+    + core::ops::Shl<u8, Output = Self>
+{
+    #[doc = " Mask for bits of width `WI`"]
+    fn mask<const WI: u8>() -> Self;
+    #[doc = " Mask for bits of width 1"]
+    fn one() -> Self;
+}
+macro_rules! raw_reg {
+    ($ U : ty , $ size : literal , $ mask : ident) => {
+        impl RawReg for $U {
+            #[inline(always)]
+            fn mask<const WI: u8>() -> Self {
+                $mask::<WI>()
+            }
+            #[inline(always)]
+            fn one() -> Self {
+                1
+            }
+        }
+        const fn $mask<const WI: u8>() -> $U {
+            <$U>::MAX >> ($size - WI)
+        }
+        impl FieldSpec for $U {
+            type Ux = $U;
+        }
+    };
+}
+raw_reg!(u8, 8, mask_u8);
+raw_reg!(u16, 16, mask_u16);
+raw_reg!(u32, 32, mask_u32);
+raw_reg!(u64, 64, mask_u64);
+#[doc = " Raw register type"]
+pub trait RegisterSpec {
+    #[doc = " Raw register type (`u8`, `u16`, `u32`, ...)."]
+    type Ux: RawReg;
+}
+#[doc = " Raw field type"]
+pub trait FieldSpec: Sized {
+    #[doc = " Raw field type (`u8`, `u16`, `u32`, ...)."]
+    type Ux: Copy + core::fmt::Debug + PartialEq + From<Self>;
+}
+#[doc = " Marker for fields with fixed values"]
+pub trait IsEnum: FieldSpec {}
+#[doc = " Trait implemented by readable registers to enable the `read` method."]
+#[doc = ""]
+#[doc = " Registers marked with `Writable` can be also be `modify`'ed."]
+pub trait Readable: RegisterSpec {}
+#[doc = " Trait implemented by writeable registers."]
+#[doc = ""]
+#[doc = " This enables the  `write`, `write_with_zero` and `reset` methods."]
+#[doc = ""]
+#[doc = " Registers marked with `Readable` can be also be `modify`'ed."]
+pub trait Writable: RegisterSpec {
+    #[doc = " Is it safe to write any bits to register"]
+    type Safety;
+    #[doc = " Specifies the register bits that are not changed if you pass `1` and are changed if you pass `0`"]
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux;
+    #[doc = " Specifies the register bits that are not changed if you pass `0` and are changed if you pass `1`"]
+    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux;
+}
+#[doc = " Reset value of the register."]
+#[doc = ""]
+#[doc = " This value is the initial value for the `write` method. It can also be directly written to the"]
+#[doc = " register by using the `reset` method."]
+pub trait Resettable: RegisterSpec {
+    #[doc = " Reset value of the register."]
+    const RESET_VALUE: Self::Ux;
+    #[doc = " Reset value of the register."]
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        Self::RESET_VALUE
+    }
+}
+#[doc = " This structure provides volatile access to registers."]
+#[repr(transparent)]
+pub struct Reg<REG: RegisterSpec> {
+    register: vcell::VolatileCell<REG::Ux>,
+    _marker: marker::PhantomData<REG>,
+}
+unsafe impl<REG: RegisterSpec> Send for Reg<REG> where REG::Ux: Send {}
+impl<REG: RegisterSpec> Reg<REG> {
+    #[doc = " Returns the underlying memory address of register."]
+    #[doc = ""]
+    #[doc = " ```ignore"]
+    #[doc = " let reg_ptr = periph.reg.as_ptr();"]
+    #[doc = " ```"]
+    #[inline(always)]
+    pub fn as_ptr(&self) -> *mut REG::Ux {
+        self.register.as_ptr()
+    }
+}
+impl<REG: Readable> Reg<REG> {
+    #[doc = " Reads the contents of a `Readable` register."]
+    #[doc = ""]
+    #[doc = " You can read the raw contents of a register by using `bits`:"]
+    #[doc = " ```ignore"]
+    #[doc = " let bits = periph.reg.read().bits();"]
+    #[doc = " ```"]
+    #[doc = " or get the content of a particular field of a register:"]
+    #[doc = " ```ignore"]
+    #[doc = " let reader = periph.reg.read();"]
+    #[doc = " let bits = reader.field1().bits();"]
+    #[doc = " let flag = reader.field2().bit_is_set();"]
+    #[doc = " ```"]
+    #[inline(always)]
+    pub fn read(&self) -> R<REG> {
+        R {
+            bits: self.register.get(),
+            _reg: marker::PhantomData,
+        }
+    }
+}
+impl<REG: Resettable + Writable> Reg<REG> {
+    #[doc = " Writes the reset value to `Writable` register."]
+    #[doc = ""]
+    #[doc = " Resets the register to its initial state."]
+    #[inline(always)]
+    pub fn reset(&self) {
+        self.register.set(REG::RESET_VALUE)
+    }
+    #[doc = " Writes bits to a `Writable` register."]
+    #[doc = ""]
+    #[doc = " You can write raw bits into a register:"]
+    #[doc = " ```ignore"]
+    #[doc = " periph.reg.write(|w| unsafe { w.bits(rawbits) });"]
+    #[doc = " ```"]
+    #[doc = " or write only the fields you need:"]
+    #[doc = " ```ignore"]
+    #[doc = " periph.reg.write(|w| w"]
+    #[doc = "     .field1().bits(newfield1bits)"]
+    #[doc = "     .field2().set_bit()"]
+    #[doc = "     .field3().variant(VARIANT)"]
+    #[doc = " );"]
+    #[doc = " ```"]
+    #[doc = " or an alternative way of saying the same:"]
+    #[doc = " ```ignore"]
+    #[doc = " periph.reg.write(|w| {"]
+    #[doc = "     w.field1().bits(newfield1bits);"]
+    #[doc = "     w.field2().set_bit();"]
+    #[doc = "     w.field3().variant(VARIANT)"]
+    #[doc = " });"]
+    #[doc = " ```"]
+    #[doc = " In the latter case, other fields will be set to their reset value."]
+    #[inline(always)]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W<REG>) -> &mut W<REG>,
+    {
+        self.register.set(
+            f(&mut W {
+                bits: REG::RESET_VALUE & !REG::ONE_TO_MODIFY_FIELDS_BITMAP
+                    | REG::ZERO_TO_MODIFY_FIELDS_BITMAP,
+                _reg: marker::PhantomData,
+            })
+            .bits,
+        );
+    }
+}
+impl<REG: Writable> Reg<REG> {
+    #[doc = " Writes 0 to a `Writable` register."]
+    #[doc = ""]
+    #[doc = " Similar to `write`, but unused bits will contain 0."]
+    #[doc = ""]
+    #[doc = " # Safety"]
+    #[doc = ""]
+    #[doc = " Unsafe to use with registers which don't allow to write 0."]
+    #[inline(always)]
+    pub unsafe fn write_with_zero<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W<REG>) -> &mut W<REG>,
+    {
+        self.register.set(
+            f(&mut W {
+                bits: REG::Ux::default(),
+                _reg: marker::PhantomData,
+            })
+            .bits,
+        );
+    }
+}
+impl<REG: Readable + Writable> Reg<REG> {
+    #[doc = " Modifies the contents of the register by reading and then writing it."]
+    #[doc = ""]
+    #[doc = " E.g. to do a read-modify-write sequence to change parts of a register:"]
+    #[doc = " ```ignore"]
+    #[doc = " periph.reg.modify(|r, w| unsafe { w.bits("]
+    #[doc = "    r.bits() | 3"]
+    #[doc = " ) });"]
+    #[doc = " ```"]
+    #[doc = " or"]
+    #[doc = " ```ignore"]
+    #[doc = " periph.reg.modify(|_, w| w"]
+    #[doc = "     .field1().bits(newfield1bits)"]
+    #[doc = "     .field2().set_bit()"]
+    #[doc = "     .field3().variant(VARIANT)"]
+    #[doc = " );"]
+    #[doc = " ```"]
+    #[doc = " or an alternative way of saying the same:"]
+    #[doc = " ```ignore"]
+    #[doc = " periph.reg.modify(|_, w| {"]
+    #[doc = "     w.field1().bits(newfield1bits);"]
+    #[doc = "     w.field2().set_bit();"]
+    #[doc = "     w.field3().variant(VARIANT)"]
+    #[doc = " });"]
+    #[doc = " ```"]
+    #[doc = " Other fields will have the value they had before the call to `modify`."]
+    #[inline(always)]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R<REG>, &'w mut W<REG>) -> &'w mut W<REG>,
+    {
+        let bits = self.register.get();
+        self.register.set(
+            f(
+                &R {
+                    bits,
+                    _reg: marker::PhantomData,
+                },
+                &mut W {
+                    bits: bits & !REG::ONE_TO_MODIFY_FIELDS_BITMAP
+                        | REG::ZERO_TO_MODIFY_FIELDS_BITMAP,
+                    _reg: marker::PhantomData,
+                },
+            )
+            .bits,
+        );
+    }
+}
+impl<REG: Readable> core::fmt::Debug for crate::generic::Reg<REG>
+where
+    R<REG>: core::fmt::Debug,
+{
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        core::fmt::Debug::fmt(&self.read(), f)
+    }
+}
+#[doc(hidden)]
+pub mod raw;
+#[doc = " Register reader."]
+#[doc = ""]
+#[doc = " Result of the `read` methods of registers. Also used as a closure argument in the `modify`"]
+#[doc = " method."]
+pub type R<REG> = raw::R<REG>;
+impl<REG: RegisterSpec> R<REG> {
+    #[doc = " Reads raw bits from register."]
+    #[inline(always)]
+    pub const fn bits(&self) -> REG::Ux {
+        self.bits
+    }
+}
+impl<REG: RegisterSpec, FI> PartialEq<FI> for R<REG>
+where
+    REG::Ux: PartialEq,
+    FI: Copy,
+    REG::Ux: From<FI>,
+{
+    #[inline(always)]
+    fn eq(&self, other: &FI) -> bool {
+        self.bits.eq(&REG::Ux::from(*other))
+    }
+}
+#[doc = " Register writer."]
+#[doc = ""]
+#[doc = " Used as an argument to the closures in the `write` and `modify` methods of the register."]
+pub type W<REG> = raw::W<REG>;
+impl<REG: Writable> W<REG> {
+    #[doc = " Writes raw bits to the register."]
+    #[doc = ""]
+    #[doc = " # Safety"]
+    #[doc = ""]
+    #[doc = " Passing incorrect value can cause undefined behaviour. See reference manual"]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: REG::Ux) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+}
+impl<REG> W<REG>
+where
+    REG: Writable<Safety = Safe>,
+{
+    #[doc = " Writes raw bits to the register."]
+    #[inline(always)]
+    pub fn set(&mut self, bits: REG::Ux) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+}
+#[doc = " Field reader."]
+#[doc = ""]
+#[doc = " Result of the `read` methods of fields."]
+pub type FieldReader<FI = u8> = raw::FieldReader<FI>;
+#[doc = " Bit-wise field reader"]
+pub type BitReader<FI = bool> = raw::BitReader<FI>;
+impl<FI: FieldSpec> FieldReader<FI> {
+    #[doc = " Reads raw bits from field."]
+    #[inline(always)]
+    pub const fn bits(&self) -> FI::Ux {
+        self.bits
+    }
+}
+impl<FI: FieldSpec> core::fmt::Debug for FieldReader<FI> {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        core::fmt::Debug::fmt(&self.bits, f)
+    }
+}
+impl<FI> PartialEq<FI> for FieldReader<FI>
+where
+    FI: FieldSpec + Copy,
+{
+    #[inline(always)]
+    fn eq(&self, other: &FI) -> bool {
+        self.bits.eq(&FI::Ux::from(*other))
+    }
+}
+impl<FI> PartialEq<FI> for BitReader<FI>
+where
+    FI: Copy,
+    bool: From<FI>,
+{
+    #[inline(always)]
+    fn eq(&self, other: &FI) -> bool {
+        self.bits.eq(&bool::from(*other))
+    }
+}
+impl<FI> BitReader<FI> {
+    #[doc = " Value of the field as raw bits."]
+    #[inline(always)]
+    pub const fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = " Returns `true` if the bit is clear (0)."]
+    #[inline(always)]
+    pub const fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = " Returns `true` if the bit is set (1)."]
+    #[inline(always)]
+    pub const fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+impl<FI> core::fmt::Debug for BitReader<FI> {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        core::fmt::Debug::fmt(&self.bits, f)
+    }
+}
+#[doc = " Marker for register/field writers which can take any value of specified width"]
+pub struct Safe;
+#[doc = " You should check that value is allowed to pass to register/field writer marked with this"]
+pub struct Unsafe;
+#[doc = " Marker for field writers are safe to write in specified inclusive range"]
+pub struct Range<const MIN: u64, const MAX: u64>;
+#[doc = " Marker for field writers are safe to write in specified inclusive range"]
+pub struct RangeFrom<const MIN: u64>;
+#[doc = " Marker for field writers are safe to write in specified inclusive range"]
+pub struct RangeTo<const MAX: u64>;
+#[doc = " Write field Proxy"]
+pub type FieldWriter<'a, REG, const WI: u8, FI = u8, Safety = Unsafe> =
+    raw::FieldWriter<'a, REG, WI, FI, Safety>;
+impl<'a, REG, const WI: u8, FI, Safety> FieldWriter<'a, REG, WI, FI, Safety>
+where
+    REG: Writable + RegisterSpec,
+    FI: FieldSpec,
+{
+    #[doc = " Field width"]
+    pub const WIDTH: u8 = WI;
+    #[doc = " Field width"]
+    #[inline(always)]
+    pub const fn width(&self) -> u8 {
+        WI
+    }
+    #[doc = " Field offset"]
+    #[inline(always)]
+    pub const fn offset(&self) -> u8 {
+        self.o
+    }
+}
+impl<'a, REG, const WI: u8, FI, Safety> FieldWriter<'a, REG, WI, FI, Safety>
+where
+    REG: Writable + RegisterSpec,
+    FI: FieldSpec,
+    REG::Ux: From<FI::Ux>,
+{
+    #[doc = " Writes raw bits to the field"]
+    #[doc = ""]
+    #[doc = " # Safety"]
+    #[doc = ""]
+    #[doc = " Passing incorrect value can cause undefined behaviour. See reference manual"]
+    #[inline(always)]
+    pub unsafe fn bits(self, value: FI::Ux) -> &'a mut W<REG> {
+        self.w.bits &= !(REG::Ux::mask::<WI>() << self.o);
+        self.w.bits |= (REG::Ux::from(value) & REG::Ux::mask::<WI>()) << self.o;
+        self.w
+    }
+}
+impl<'a, REG, const WI: u8, FI> FieldWriter<'a, REG, WI, FI, Safe>
+where
+    REG: Writable + RegisterSpec,
+    FI: FieldSpec,
+    REG::Ux: From<FI::Ux>,
+{
+    #[doc = " Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn set(self, value: FI::Ux) -> &'a mut W<REG> {
+        unsafe { self.bits(value) }
+    }
+}
+impl<'a, REG, const WI: u8, FI, const MIN: u64, const MAX: u64>
+    FieldWriter<'a, REG, WI, FI, Range<MIN, MAX>>
+where
+    REG: Writable + RegisterSpec,
+    FI: FieldSpec,
+    REG::Ux: From<FI::Ux>,
+    u64: From<FI::Ux>,
+{
+    #[doc = " Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn set(self, value: FI::Ux) -> &'a mut W<REG> {
+        {
+            let value = u64::from(value);
+            assert!(value >= MIN && value <= MAX);
+        }
+        unsafe { self.bits(value) }
+    }
+}
+impl<'a, REG, const WI: u8, FI, const MIN: u64> FieldWriter<'a, REG, WI, FI, RangeFrom<MIN>>
+where
+    REG: Writable + RegisterSpec,
+    FI: FieldSpec,
+    REG::Ux: From<FI::Ux>,
+    u64: From<FI::Ux>,
+{
+    #[doc = " Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn set(self, value: FI::Ux) -> &'a mut W<REG> {
+        {
+            let value = u64::from(value);
+            assert!(value >= MIN);
+        }
+        unsafe { self.bits(value) }
+    }
+}
+impl<'a, REG, const WI: u8, FI, const MAX: u64> FieldWriter<'a, REG, WI, FI, RangeTo<MAX>>
+where
+    REG: Writable + RegisterSpec,
+    FI: FieldSpec,
+    REG::Ux: From<FI::Ux>,
+    u64: From<FI::Ux>,
+{
+    #[doc = " Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn set(self, value: FI::Ux) -> &'a mut W<REG> {
+        {
+            let value = u64::from(value);
+            assert!(value <= MAX);
+        }
+        unsafe { self.bits(value) }
+    }
+}
+impl<'a, REG, const WI: u8, FI, Safety> FieldWriter<'a, REG, WI, FI, Safety>
+where
+    REG: Writable + RegisterSpec,
+    FI: IsEnum,
+    REG::Ux: From<FI::Ux>,
+{
+    #[doc = " Writes `variant` to the field"]
+    #[inline(always)]
+    pub fn variant(self, variant: FI) -> &'a mut W<REG> {
+        unsafe { self.bits(FI::Ux::from(variant)) }
+    }
+}
+macro_rules! bit_proxy {
+    ($ writer : ident , $ mwv : ident) => {
+        #[doc(hidden)]
+        pub struct $mwv;
+        #[doc = " Bit-wise write field proxy"]
+        pub type $writer<'a, REG, FI = bool> = raw::BitWriter<'a, REG, FI, $mwv>;
+        impl<'a, REG, FI> $writer<'a, REG, FI>
+        where
+            REG: Writable + RegisterSpec,
+            bool: From<FI>,
+        {
+            #[doc = " Field width"]
+            pub const WIDTH: u8 = 1;
+            #[doc = " Field width"]
+            #[inline(always)]
+            pub const fn width(&self) -> u8 {
+                Self::WIDTH
+            }
+            #[doc = " Field offset"]
+            #[inline(always)]
+            pub const fn offset(&self) -> u8 {
+                self.o
+            }
+            #[doc = " Writes bit to the field"]
+            #[inline(always)]
+            pub fn bit(self, value: bool) -> &'a mut W<REG> {
+                self.w.bits &= !(REG::Ux::one() << self.o);
+                self.w.bits |= (REG::Ux::from(value) & REG::Ux::one()) << self.o;
+                self.w
+            }
+            #[doc = " Writes `variant` to the field"]
+            #[inline(always)]
+            pub fn variant(self, variant: FI) -> &'a mut W<REG> {
+                self.bit(bool::from(variant))
+            }
+        }
+    };
+}
+bit_proxy!(BitWriter, BitM);
+bit_proxy!(BitWriter1S, Bit1S);
+bit_proxy!(BitWriter0C, Bit0C);
+bit_proxy!(BitWriter1C, Bit1C);
+bit_proxy!(BitWriter0S, Bit0S);
+bit_proxy!(BitWriter1T, Bit1T);
+bit_proxy!(BitWriter0T, Bit0T);
+impl<'a, REG, FI> BitWriter<'a, REG, FI>
+where
+    REG: Writable + RegisterSpec,
+    bool: From<FI>,
+{
+    #[doc = " Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W<REG> {
+        self.w.bits |= REG::Ux::one() << self.o;
+        self.w
+    }
+    #[doc = " Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W<REG> {
+        self.w.bits &= !(REG::Ux::one() << self.o);
+        self.w
+    }
+}
+impl<'a, REG, FI> BitWriter1S<'a, REG, FI>
+where
+    REG: Writable + RegisterSpec,
+    bool: From<FI>,
+{
+    #[doc = " Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W<REG> {
+        self.w.bits |= REG::Ux::one() << self.o;
+        self.w
+    }
+}
+impl<'a, REG, FI> BitWriter0C<'a, REG, FI>
+where
+    REG: Writable + RegisterSpec,
+    bool: From<FI>,
+{
+    #[doc = " Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W<REG> {
+        self.w.bits &= !(REG::Ux::one() << self.o);
+        self.w
+    }
+}
+impl<'a, REG, FI> BitWriter1C<'a, REG, FI>
+where
+    REG: Writable + RegisterSpec,
+    bool: From<FI>,
+{
+    #[doc = "Clears the field bit by passing one"]
+    #[inline(always)]
+    pub fn clear_bit_by_one(self) -> &'a mut W<REG> {
+        self.w.bits |= REG::Ux::one() << self.o;
+        self.w
+    }
+}
+impl<'a, REG, FI> BitWriter0S<'a, REG, FI>
+where
+    REG: Writable + RegisterSpec,
+    bool: From<FI>,
+{
+    #[doc = "Sets the field bit by passing zero"]
+    #[inline(always)]
+    pub fn set_bit_by_zero(self) -> &'a mut W<REG> {
+        self.w.bits &= !(REG::Ux::one() << self.o);
+        self.w
+    }
+}
+impl<'a, REG, FI> BitWriter1T<'a, REG, FI>
+where
+    REG: Writable + RegisterSpec,
+    bool: From<FI>,
+{
+    #[doc = "Toggle the field bit by passing one"]
+    #[inline(always)]
+    pub fn toggle_bit(self) -> &'a mut W<REG> {
+        self.w.bits |= REG::Ux::one() << self.o;
+        self.w
+    }
+}
+impl<'a, REG, FI> BitWriter0T<'a, REG, FI>
+where
+    REG: Writable + RegisterSpec,
+    bool: From<FI>,
+{
+    #[doc = "Toggle the field bit by passing zero"]
+    #[inline(always)]
+    pub fn toggle_bit(self) -> &'a mut W<REG> {
+        self.w.bits &= !(REG::Ux::one() << self.o);
+        self.w
+    }
+}

va108xx/src/generic/raw.rs

@@ -0,0 +1,93 @@
+use super::{marker, BitM, FieldSpec, RegisterSpec, Unsafe, Writable};
+pub struct R<REG: RegisterSpec> {
+    pub(crate) bits: REG::Ux,
+    pub(super) _reg: marker::PhantomData<REG>,
+}
+pub struct W<REG: RegisterSpec> {
+    #[doc = "Writable bits"]
+    pub(crate) bits: REG::Ux,
+    pub(super) _reg: marker::PhantomData<REG>,
+}
+pub struct FieldReader<FI = u8>
+where
+    FI: FieldSpec,
+{
+    pub(crate) bits: FI::Ux,
+    _reg: marker::PhantomData<FI>,
+}
+impl<FI: FieldSpec> FieldReader<FI> {
+    #[doc = " Creates a new instance of the reader."]
+    #[allow(unused)]
+    #[inline(always)]
+    pub(crate) const fn new(bits: FI::Ux) -> Self {
+        Self {
+            bits,
+            _reg: marker::PhantomData,
+        }
+    }
+}
+pub struct BitReader<FI = bool> {
+    pub(crate) bits: bool,
+    _reg: marker::PhantomData<FI>,
+}
+impl<FI> BitReader<FI> {
+    #[doc = " Creates a new instance of the reader."]
+    #[allow(unused)]
+    #[inline(always)]
+    pub(crate) const fn new(bits: bool) -> Self {
+        Self {
+            bits,
+            _reg: marker::PhantomData,
+        }
+    }
+}
+pub struct FieldWriter<'a, REG, const WI: u8, FI = u8, Safety = Unsafe>
+where
+    REG: Writable + RegisterSpec,
+    FI: FieldSpec,
+{
+    pub(crate) w: &'a mut W<REG>,
+    pub(crate) o: u8,
+    _field: marker::PhantomData<(FI, Safety)>,
+}
+impl<'a, REG, const WI: u8, FI, Safety> FieldWriter<'a, REG, WI, FI, Safety>
+where
+    REG: Writable + RegisterSpec,
+    FI: FieldSpec,
+{
+    #[doc = " Creates a new instance of the writer"]
+    #[allow(unused)]
+    #[inline(always)]
+    pub(crate) fn new(w: &'a mut W<REG>, o: u8) -> Self {
+        Self {
+            w,
+            o,
+            _field: marker::PhantomData,
+        }
+    }
+}
+pub struct BitWriter<'a, REG, FI = bool, M = BitM>
+where
+    REG: Writable + RegisterSpec,
+    bool: From<FI>,
+{
+    pub(crate) w: &'a mut W<REG>,
+    pub(crate) o: u8,
+    _field: marker::PhantomData<(FI, M)>,
+}
+impl<'a, REG, FI, M> BitWriter<'a, REG, FI, M>
+where
+    REG: Writable + RegisterSpec,
+    bool: From<FI>,
+{
+    #[doc = " Creates a new instance of the writer"]
+    #[allow(unused)]
+    #[inline(always)]
+    pub(crate) fn new(w: &'a mut W<REG>, o: u8) -> Self {
+        Self {
+            w,
+            o,
+            _field: marker::PhantomData,
+        }
+    }
+}

va108xx/src/i2ca.rs

@@ -0,0 +1,452 @@
+#[repr(C)]
+#[doc = "Register block"]
+pub struct RegisterBlock {
+    ctrl: Ctrl,
+    clkscale: Clkscale,
+    words: Words,
+    address: Address,
+    data: Data,
+    cmd: Cmd,
+    status: Status,
+    state: State,
+    txcount: Txcount,
+    rxcount: Rxcount,
+    irq_enb: IrqEnb,
+    irq_raw: IrqRaw,
+    irq_end: IrqEnd,
+    irq_clr: IrqClr,
+    rxfifoirqtrg: Rxfifoirqtrg,
+    txfifoirqtrg: Txfifoirqtrg,
+    fifo_clr: FifoClr,
+    tmconfig: Tmconfig,
+    clktolimit: Clktolimit,
+    _reserved19: [u8; 0xb4],
+    s0_ctrl: S0Ctrl,
+    s0_maxwords: S0Maxwords,
+    s0_address: S0Address,
+    s0_addressmask: S0Addressmask,
+    s0_data: S0Data,
+    s0_lastaddress: S0Lastaddress,
+    s0_status: S0Status,
+    s0_state: S0State,
+    s0_txcount: S0Txcount,
+    s0_rxcount: S0Rxcount,
+    s0_irq_enb: S0IrqEnb,
+    s0_irq_raw: S0IrqRaw,
+    s0_irq_end: S0IrqEnd,
+    s0_irq_clr: S0IrqClr,
+    s0_rxfifoirqtrg: S0Rxfifoirqtrg,
+    s0_txfifoirqtrg: S0Txfifoirqtrg,
+    s0_fifo_clr: S0FifoClr,
+    s0_addressb: S0Addressb,
+    s0_addressmaskb: S0Addressmaskb,
+    _reserved38: [u8; 0x0eb0],
+    perid: Perid,
+}
+impl RegisterBlock {
+    #[doc = "0x00 - Control Register"]
+    #[inline(always)]
+    pub const fn ctrl(&self) -> &Ctrl {
+        &self.ctrl
+    }
+    #[doc = "0x04 - Clock Scale divide value"]
+    #[inline(always)]
+    pub const fn clkscale(&self) -> &Clkscale {
+        &self.clkscale
+    }
+    #[doc = "0x08 - Word Count value"]
+    #[inline(always)]
+    pub const fn words(&self) -> &Words {
+        &self.words
+    }
+    #[doc = "0x0c - I2C Address value"]
+    #[inline(always)]
+    pub const fn address(&self) -> &Address {
+        &self.address
+    }
+    #[doc = "0x10 - Data Input/Output"]
+    #[inline(always)]
+    pub const fn data(&self) -> &Data {
+        &self.data
+    }
+    #[doc = "0x14 - Command Register"]
+    #[inline(always)]
+    pub const fn cmd(&self) -> &Cmd {
+        &self.cmd
+    }
+    #[doc = "0x18 - I2C Controller Status Register"]
+    #[inline(always)]
+    pub const fn status(&self) -> &Status {
+        &self.status
+    }
+    #[doc = "0x1c - Internal STATE of I2C Master Controller"]
+    #[inline(always)]
+    pub const fn state(&self) -> &State {
+        &self.state
+    }
+    #[doc = "0x20 - TX Count Register"]
+    #[inline(always)]
+    pub const fn txcount(&self) -> &Txcount {
+        &self.txcount
+    }
+    #[doc = "0x24 - RX Count Register"]
+    #[inline(always)]
+    pub const fn rxcount(&self) -> &Rxcount {
+        &self.rxcount
+    }
+    #[doc = "0x28 - Interrupt Enable Register"]
+    #[inline(always)]
+    pub const fn irq_enb(&self) -> &IrqEnb {
+        &self.irq_enb
+    }
+    #[doc = "0x2c - Raw Interrupt Status Register"]
+    #[inline(always)]
+    pub const fn irq_raw(&self) -> &IrqRaw {
+        &self.irq_raw
+    }
+    #[doc = "0x30 - Enabled Interrupt Status Register"]
+    #[inline(always)]
+    pub const fn irq_end(&self) -> &IrqEnd {
+        &self.irq_end
+    }
+    #[doc = "0x34 - Clear Interrupt Status Register"]
+    #[inline(always)]
+    pub const fn irq_clr(&self) -> &IrqClr {
+        &self.irq_clr
+    }
+    #[doc = "0x38 - Rx FIFO IRQ Trigger Level"]
+    #[inline(always)]
+    pub const fn rxfifoirqtrg(&self) -> &Rxfifoirqtrg {
+        &self.rxfifoirqtrg
+    }
+    #[doc = "0x3c - Tx FIFO IRQ Trigger Level"]
+    #[inline(always)]
+    pub const fn txfifoirqtrg(&self) -> &Txfifoirqtrg {
+        &self.txfifoirqtrg
+    }
+    #[doc = "0x40 - Clear FIFO Register"]
+    #[inline(always)]
+    pub const fn fifo_clr(&self) -> &FifoClr {
+        &self.fifo_clr
+    }
+    #[doc = "0x44 - Timing Config Register"]
+    #[inline(always)]
+    pub const fn tmconfig(&self) -> &Tmconfig {
+        &self.tmconfig
+    }
+    #[doc = "0x48 - Clock Low Timeout Limit Register"]
+    #[inline(always)]
+    pub const fn clktolimit(&self) -> &Clktolimit {
+        &self.clktolimit
+    }
+    #[doc = "0x100 - Slave Control Register"]
+    #[inline(always)]
+    pub const fn s0_ctrl(&self) -> &S0Ctrl {
+        &self.s0_ctrl
+    }
+    #[doc = "0x104 - Slave MaxWords Register"]
+    #[inline(always)]
+    pub const fn s0_maxwords(&self) -> &S0Maxwords {
+        &self.s0_maxwords
+    }
+    #[doc = "0x108 - Slave I2C Address Value"]
+    #[inline(always)]
+    pub const fn s0_address(&self) -> &S0Address {
+        &self.s0_address
+    }
+    #[doc = "0x10c - Slave I2C Address Mask value"]
+    #[inline(always)]
+    pub const fn s0_addressmask(&self) -> &S0Addressmask {
+        &self.s0_addressmask
+    }
+    #[doc = "0x110 - Slave Data Input/Output"]
+    #[inline(always)]
+    pub const fn s0_data(&self) -> &S0Data {
+        &self.s0_data
+    }
+    #[doc = "0x114 - Slave I2C Last Address value"]
+    #[inline(always)]
+    pub const fn s0_lastaddress(&self) -> &S0Lastaddress {
+        &self.s0_lastaddress
+    }
+    #[doc = "0x118 - Slave I2C Controller Status Register"]
+    #[inline(always)]
+    pub const fn s0_status(&self) -> &S0Status {
+        &self.s0_status
+    }
+    #[doc = "0x11c - Internal STATE of I2C Slave Controller"]
+    #[inline(always)]
+    pub const fn s0_state(&self) -> &S0State {
+        &self.s0_state
+    }
+    #[doc = "0x120 - Slave TX Count Register"]
+    #[inline(always)]
+    pub const fn s0_txcount(&self) -> &S0Txcount {
+        &self.s0_txcount
+    }
+    #[doc = "0x124 - Slave RX Count Register"]
+    #[inline(always)]
+    pub const fn s0_rxcount(&self) -> &S0Rxcount {
+        &self.s0_rxcount
+    }
+    #[doc = "0x128 - Slave Interrupt Enable Register"]
+    #[inline(always)]
+    pub const fn s0_irq_enb(&self) -> &S0IrqEnb {
+        &self.s0_irq_enb
+    }
+    #[doc = "0x12c - Slave Raw Interrupt Status Register"]
+    #[inline(always)]
+    pub const fn s0_irq_raw(&self) -> &S0IrqRaw {
+        &self.s0_irq_raw
+    }
+    #[doc = "0x130 - Slave Enabled Interrupt Status Register"]
+    #[inline(always)]
+    pub const fn s0_irq_end(&self) -> &S0IrqEnd {
+        &self.s0_irq_end
+    }
+    #[doc = "0x134 - Slave Clear Interrupt Status Register"]
+    #[inline(always)]
+    pub const fn s0_irq_clr(&self) -> &S0IrqClr {
+        &self.s0_irq_clr
+    }
+    #[doc = "0x138 - Slave Rx FIFO IRQ Trigger Level"]
+    #[inline(always)]
+    pub const fn s0_rxfifoirqtrg(&self) -> &S0Rxfifoirqtrg {
+        &self.s0_rxfifoirqtrg
+    }
+    #[doc = "0x13c - Slave Tx FIFO IRQ Trigger Level"]
+    #[inline(always)]
+    pub const fn s0_txfifoirqtrg(&self) -> &S0Txfifoirqtrg {
+        &self.s0_txfifoirqtrg
+    }
+    #[doc = "0x140 - Slave Clear FIFO Register"]
+    #[inline(always)]
+    pub const fn s0_fifo_clr(&self) -> &S0FifoClr {
+        &self.s0_fifo_clr
+    }
+    #[doc = "0x144 - Slave I2C Address B Value"]
+    #[inline(always)]
+    pub const fn s0_addressb(&self) -> &S0Addressb {
+        &self.s0_addressb
+    }
+    #[doc = "0x148 - Slave I2C Address B Mask value"]
+    #[inline(always)]
+    pub const fn s0_addressmaskb(&self) -> &S0Addressmaskb {
+        &self.s0_addressmaskb
+    }
+    #[doc = "0xffc - Peripheral ID Register"]
+    #[inline(always)]
+    pub const fn perid(&self) -> &Perid {
+        &self.perid
+    }
+}
+#[doc = "CTRL (rw) register accessor: Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl`]
+module"]
+#[doc(alias = "CTRL")]
+pub type Ctrl = crate::Reg<ctrl::CtrlSpec>;
+#[doc = "Control Register"]
+pub mod ctrl;
+#[doc = "CLKSCALE (rw) register accessor: Clock Scale divide value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkscale::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkscale::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clkscale`]
+module"]
+#[doc(alias = "CLKSCALE")]
+pub type Clkscale = crate::Reg<clkscale::ClkscaleSpec>;
+#[doc = "Clock Scale divide value"]
+pub mod clkscale;
+#[doc = "WORDS (rw) register accessor: Word Count value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`words::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`words::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@words`]
+module"]
+#[doc(alias = "WORDS")]
+pub type Words = crate::Reg<words::WordsSpec>;
+#[doc = "Word Count value"]
+pub mod words;
+#[doc = "ADDRESS (rw) register accessor: I2C Address value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`address::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`address::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@address`]
+module"]
+#[doc(alias = "ADDRESS")]
+pub type Address = crate::Reg<address::AddressSpec>;
+#[doc = "I2C Address value"]
+pub mod address;
+#[doc = "DATA (rw) register accessor: Data Input/Output\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data`]
+module"]
+#[doc(alias = "DATA")]
+pub type Data = crate::Reg<data::DataSpec>;
+#[doc = "Data Input/Output"]
+pub mod data;
+#[doc = "CMD (rw) register accessor: Command Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmd::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmd`]
+module"]
+#[doc(alias = "CMD")]
+pub type Cmd = crate::Reg<cmd::CmdSpec>;
+#[doc = "Command Register"]
+pub mod cmd;
+#[doc = "STATUS (r) register accessor: I2C Controller Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status`]
+module"]
+#[doc(alias = "STATUS")]
+pub type Status = crate::Reg<status::StatusSpec>;
+#[doc = "I2C Controller Status Register"]
+pub mod status;
+#[doc = "STATE (r) register accessor: Internal STATE of I2C Master Controller\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`state::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@state`]
+module"]
+#[doc(alias = "STATE")]
+pub type State = crate::Reg<state::StateSpec>;
+#[doc = "Internal STATE of I2C Master Controller"]
+pub mod state;
+#[doc = "TXCOUNT (r) register accessor: TX Count Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txcount::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txcount`]
+module"]
+#[doc(alias = "TXCOUNT")]
+pub type Txcount = crate::Reg<txcount::TxcountSpec>;
+#[doc = "TX Count Register"]
+pub mod txcount;
+#[doc = "RXCOUNT (r) register accessor: RX Count Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxcount::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxcount`]
+module"]
+#[doc(alias = "RXCOUNT")]
+pub type Rxcount = crate::Reg<rxcount::RxcountSpec>;
+#[doc = "RX Count Register"]
+pub mod rxcount;
+#[doc = "IRQ_ENB (rw) register accessor: Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_enb::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_enb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_enb`]
+module"]
+#[doc(alias = "IRQ_ENB")]
+pub type IrqEnb = crate::Reg<irq_enb::IrqEnbSpec>;
+#[doc = "Interrupt Enable Register"]
+pub mod irq_enb;
+pub use irq_enb as irq_raw;
+pub use irq_enb as irq_end;
+pub use irq_enb as irq_clr;
+pub use IrqEnb as IrqRaw;
+pub use IrqEnb as IrqEnd;
+pub use IrqEnb as IrqClr;
+#[doc = "RXFIFOIRQTRG (rw) register accessor: Rx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxfifoirqtrg::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxfifoirqtrg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxfifoirqtrg`]
+module"]
+#[doc(alias = "RXFIFOIRQTRG")]
+pub type Rxfifoirqtrg = crate::Reg<rxfifoirqtrg::RxfifoirqtrgSpec>;
+#[doc = "Rx FIFO IRQ Trigger Level"]
+pub mod rxfifoirqtrg;
+#[doc = "TXFIFOIRQTRG (rw) register accessor: Tx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txfifoirqtrg::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txfifoirqtrg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txfifoirqtrg`]
+module"]
+#[doc(alias = "TXFIFOIRQTRG")]
+pub type Txfifoirqtrg = crate::Reg<txfifoirqtrg::TxfifoirqtrgSpec>;
+#[doc = "Tx FIFO IRQ Trigger Level"]
+pub mod txfifoirqtrg;
+#[doc = "FIFO_CLR (w) register accessor: Clear FIFO Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifo_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifo_clr`]
+module"]
+#[doc(alias = "FIFO_CLR")]
+pub type FifoClr = crate::Reg<fifo_clr::FifoClrSpec>;
+#[doc = "Clear FIFO Register"]
+pub mod fifo_clr;
+#[doc = "TMCONFIG (rw) register accessor: Timing Config Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tmconfig::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tmconfig::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tmconfig`]
+module"]
+#[doc(alias = "TMCONFIG")]
+pub type Tmconfig = crate::Reg<tmconfig::TmconfigSpec>;
+#[doc = "Timing Config Register"]
+pub mod tmconfig;
+#[doc = "CLKTOLIMIT (rw) register accessor: Clock Low Timeout Limit Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clktolimit::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clktolimit::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clktolimit`]
+module"]
+#[doc(alias = "CLKTOLIMIT")]
+pub type Clktolimit = crate::Reg<clktolimit::ClktolimitSpec>;
+#[doc = "Clock Low Timeout Limit Register"]
+pub mod clktolimit;
+#[doc = "S0_CTRL (rw) register accessor: Slave Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_ctrl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_ctrl`]
+module"]
+#[doc(alias = "S0_CTRL")]
+pub type S0Ctrl = crate::Reg<s0_ctrl::S0CtrlSpec>;
+#[doc = "Slave Control Register"]
+pub mod s0_ctrl;
+#[doc = "S0_MAXWORDS (rw) register accessor: Slave MaxWords Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_maxwords::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_maxwords::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_maxwords`]
+module"]
+#[doc(alias = "S0_MAXWORDS")]
+pub type S0Maxwords = crate::Reg<s0_maxwords::S0MaxwordsSpec>;
+#[doc = "Slave MaxWords Register"]
+pub mod s0_maxwords;
+#[doc = "S0_ADDRESS (rw) register accessor: Slave I2C Address Value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_address::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_address::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_address`]
+module"]
+#[doc(alias = "S0_ADDRESS")]
+pub type S0Address = crate::Reg<s0_address::S0AddressSpec>;
+#[doc = "Slave I2C Address Value"]
+pub mod s0_address;
+#[doc = "S0_ADDRESSMASK (rw) register accessor: Slave I2C Address Mask value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_addressmask::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_addressmask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_addressmask`]
+module"]
+#[doc(alias = "S0_ADDRESSMASK")]
+pub type S0Addressmask = crate::Reg<s0_addressmask::S0AddressmaskSpec>;
+#[doc = "Slave I2C Address Mask value"]
+pub mod s0_addressmask;
+#[doc = "S0_DATA (rw) register accessor: Slave Data Input/Output\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_data::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_data::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_data`]
+module"]
+#[doc(alias = "S0_DATA")]
+pub type S0Data = crate::Reg<s0_data::S0DataSpec>;
+#[doc = "Slave Data Input/Output"]
+pub mod s0_data;
+#[doc = "S0_LASTADDRESS (r) register accessor: Slave I2C Last Address value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_lastaddress::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_lastaddress`]
+module"]
+#[doc(alias = "S0_LASTADDRESS")]
+pub type S0Lastaddress = crate::Reg<s0_lastaddress::S0LastaddressSpec>;
+#[doc = "Slave I2C Last Address value"]
+pub mod s0_lastaddress;
+#[doc = "S0_STATUS (r) register accessor: Slave I2C Controller Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_status::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_status`]
+module"]
+#[doc(alias = "S0_STATUS")]
+pub type S0Status = crate::Reg<s0_status::S0StatusSpec>;
+#[doc = "Slave I2C Controller Status Register"]
+pub mod s0_status;
+#[doc = "S0_STATE (r) register accessor: Internal STATE of I2C Slave Controller\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_state::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_state`]
+module"]
+#[doc(alias = "S0_STATE")]
+pub type S0State = crate::Reg<s0_state::S0StateSpec>;
+#[doc = "Internal STATE of I2C Slave Controller"]
+pub mod s0_state;
+#[doc = "S0_TXCOUNT (r) register accessor: Slave TX Count Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_txcount::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_txcount`]
+module"]
+#[doc(alias = "S0_TXCOUNT")]
+pub type S0Txcount = crate::Reg<s0_txcount::S0TxcountSpec>;
+#[doc = "Slave TX Count Register"]
+pub mod s0_txcount;
+#[doc = "S0_RXCOUNT (r) register accessor: Slave RX Count Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_rxcount::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_rxcount`]
+module"]
+#[doc(alias = "S0_RXCOUNT")]
+pub type S0Rxcount = crate::Reg<s0_rxcount::S0RxcountSpec>;
+#[doc = "Slave RX Count Register"]
+pub mod s0_rxcount;
+#[doc = "S0_IRQ_ENB (rw) register accessor: Slave Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_irq_enb::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_irq_enb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_irq_enb`]
+module"]
+#[doc(alias = "S0_IRQ_ENB")]
+pub type S0IrqEnb = crate::Reg<s0_irq_enb::S0IrqEnbSpec>;
+#[doc = "Slave Interrupt Enable Register"]
+pub mod s0_irq_enb;
+pub use s0_irq_enb as s0_irq_raw;
+pub use s0_irq_enb as s0_irq_end;
+pub use s0_irq_enb as s0_irq_clr;
+pub use S0IrqEnb as S0IrqRaw;
+pub use S0IrqEnb as S0IrqEnd;
+pub use S0IrqEnb as S0IrqClr;
+#[doc = "S0_RXFIFOIRQTRG (rw) register accessor: Slave Rx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_rxfifoirqtrg::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_rxfifoirqtrg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_rxfifoirqtrg`]
+module"]
+#[doc(alias = "S0_RXFIFOIRQTRG")]
+pub type S0Rxfifoirqtrg = crate::Reg<s0_rxfifoirqtrg::S0RxfifoirqtrgSpec>;
+#[doc = "Slave Rx FIFO IRQ Trigger Level"]
+pub mod s0_rxfifoirqtrg;
+#[doc = "S0_TXFIFOIRQTRG (rw) register accessor: Slave Tx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_txfifoirqtrg::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_txfifoirqtrg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_txfifoirqtrg`]
+module"]
+#[doc(alias = "S0_TXFIFOIRQTRG")]
+pub type S0Txfifoirqtrg = crate::Reg<s0_txfifoirqtrg::S0TxfifoirqtrgSpec>;
+#[doc = "Slave Tx FIFO IRQ Trigger Level"]
+pub mod s0_txfifoirqtrg;
+#[doc = "S0_FIFO_CLR (w) register accessor: Slave Clear FIFO Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_fifo_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_fifo_clr`]
+module"]
+#[doc(alias = "S0_FIFO_CLR")]
+pub type S0FifoClr = crate::Reg<s0_fifo_clr::S0FifoClrSpec>;
+#[doc = "Slave Clear FIFO Register"]
+pub mod s0_fifo_clr;
+#[doc = "S0_ADDRESSB (rw) register accessor: Slave I2C Address B Value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_addressb::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_addressb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_addressb`]
+module"]
+#[doc(alias = "S0_ADDRESSB")]
+pub type S0Addressb = crate::Reg<s0_addressb::S0AddressbSpec>;
+#[doc = "Slave I2C Address B Value"]
+pub mod s0_addressb;
+#[doc = "S0_ADDRESSMASKB (rw) register accessor: Slave I2C Address B Mask value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_addressmaskb::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_addressmaskb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_addressmaskb`]
+module"]
+#[doc(alias = "S0_ADDRESSMASKB")]
+pub type S0Addressmaskb = crate::Reg<s0_addressmaskb::S0AddressmaskbSpec>;
+#[doc = "Slave I2C Address B Mask value"]
+pub mod s0_addressmaskb;
+#[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`perid::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`]
+module"]
+#[doc(alias = "PERID")]
+pub type Perid = crate::Reg<perid::PeridSpec>;
+#[doc = "Peripheral ID Register"]
+pub mod perid;

va108xx/src/i2ca/address.rs

@@ -0,0 +1,27 @@
+#[doc = "Register `ADDRESS` reader"]
+pub type R = crate::R<AddressSpec>;
+#[doc = "Register `ADDRESS` writer"]
+pub type W = crate::W<AddressSpec>;
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        write!(f, "{}", self.bits())
+    }
+}
+impl W {}
+#[doc = "I2C Address value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`address::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`address::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct AddressSpec;
+impl crate::RegisterSpec for AddressSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`address::R`](R) reader structure"]
+impl crate::Readable for AddressSpec {}
+#[doc = "`write(|w| ..)` method takes [`address::W`](W) writer structure"]
+impl crate::Writable for AddressSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets ADDRESS to value 0"]
+impl crate::Resettable for AddressSpec {
+    const RESET_VALUE: u32 = 0;
+}

va108xx/src/i2ca/clkscale.rs

@@ -0,0 +1,55 @@
+#[doc = "Register `CLKSCALE` reader"]
+pub type R = crate::R<ClkscaleSpec>;
+#[doc = "Register `CLKSCALE` writer"]
+pub type W = crate::W<ClkscaleSpec>;
+#[doc = "Field `VALUE` reader - Enable FastMode"]
+pub type ValueR = crate::FieldReader<u32>;
+#[doc = "Field `VALUE` writer - Enable FastMode"]
+pub type ValueW<'a, REG> = crate::FieldWriter<'a, REG, 31, u32>;
+#[doc = "Field `FASTMODE` reader - Enable FastMode"]
+pub type FastmodeR = crate::BitReader;
+#[doc = "Field `FASTMODE` writer - Enable FastMode"]
+pub type FastmodeW<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bits 0:30 - Enable FastMode"]
+    #[inline(always)]
+    pub fn value(&self) -> ValueR {
+        ValueR::new(self.bits & 0x7fff_ffff)
+    }
+    #[doc = "Bit 31 - Enable FastMode"]
+    #[inline(always)]
+    pub fn fastmode(&self) -> FastmodeR {
+        FastmodeR::new(((self.bits >> 31) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bits 0:30 - Enable FastMode"]
+    #[inline(always)]
+    #[must_use]
+    pub fn value(&mut self) -> ValueW<ClkscaleSpec> {
+        ValueW::new(self, 0)
+    }
+    #[doc = "Bit 31 - Enable FastMode"]
+    #[inline(always)]
+    #[must_use]
+    pub fn fastmode(&mut self) -> FastmodeW<ClkscaleSpec> {
+        FastmodeW::new(self, 31)
+    }
+}
+#[doc = "Clock Scale divide value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkscale::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkscale::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct ClkscaleSpec;
+impl crate::RegisterSpec for ClkscaleSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`clkscale::R`](R) reader structure"]
+impl crate::Readable for ClkscaleSpec {}
+#[doc = "`write(|w| ..)` method takes [`clkscale::W`](W) writer structure"]
+impl crate::Writable for ClkscaleSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CLKSCALE to value 0"]
+impl crate::Resettable for ClkscaleSpec {
+    const RESET_VALUE: u32 = 0;
+}

va108xx/src/i2ca/clktolimit.rs

@@ -0,0 +1,27 @@
+#[doc = "Register `CLKTOLIMIT` reader"]
+pub type R = crate::R<ClktolimitSpec>;
+#[doc = "Register `CLKTOLIMIT` writer"]
+pub type W = crate::W<ClktolimitSpec>;
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        write!(f, "{}", self.bits())
+    }
+}
+impl W {}
+#[doc = "Clock Low Timeout Limit Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clktolimit::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clktolimit::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct ClktolimitSpec;
+impl crate::RegisterSpec for ClktolimitSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`clktolimit::R`](R) reader structure"]
+impl crate::Readable for ClktolimitSpec {}
+#[doc = "`write(|w| ..)` method takes [`clktolimit::W`](W) writer structure"]
+impl crate::Writable for ClktolimitSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CLKTOLIMIT to value 0"]
+impl crate::Resettable for ClktolimitSpec {
+    const RESET_VALUE: u32 = 0;
+}

va108xx/src/i2ca/cmd.rs

@@ -0,0 +1,27 @@
+#[doc = "Register `CMD` reader"]
+pub type R = crate::R<CmdSpec>;
+#[doc = "Register `CMD` writer"]
+pub type W = crate::W<CmdSpec>;
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        write!(f, "{}", self.bits())
+    }
+}
+impl W {}
+#[doc = "Command Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmd::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmd::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CmdSpec;
+impl crate::RegisterSpec for CmdSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`cmd::R`](R) reader structure"]
+impl crate::Readable for CmdSpec {}
+#[doc = "`write(|w| ..)` method takes [`cmd::W`](W) writer structure"]
+impl crate::Writable for CmdSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CMD to value 0"]
+impl crate::Resettable for CmdSpec {
+    const RESET_VALUE: u32 = 0;
+}

va108xx/src/i2ca/ctrl.rs

@@ -0,0 +1,160 @@
+#[doc = "Register `CTRL` reader"]
+pub type R = crate::R<CtrlSpec>;
+#[doc = "Register `CTRL` writer"]
+pub type W = crate::W<CtrlSpec>;
+#[doc = "Field `CLKENABLED` reader - I2C CLK Enabled"]
+pub type ClkenabledR = crate::BitReader;
+#[doc = "Field `CLKENABLED` writer - I2C CLK Enabled"]
+pub type ClkenabledW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `ENABLED` reader - I2C Activated"]
+pub type EnabledR = crate::BitReader;
+#[doc = "Field `ENABLED` writer - I2C Activated"]
+pub type EnabledW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `ENABLE` reader - I2C Active"]
+pub type EnableR = crate::BitReader;
+#[doc = "Field `ENABLE` writer - I2C Active"]
+pub type EnableW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TXFEMD` reader - TX FIFIO Empty Mode"]
+pub type TxfemdR = crate::BitReader;
+#[doc = "Field `TXFEMD` writer - TX FIFIO Empty Mode"]
+pub type TxfemdW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `RXFFMD` reader - RX FIFO Full Mode"]
+pub type RxffmdR = crate::BitReader;
+#[doc = "Field `RXFFMD` writer - RX FIFO Full Mode"]
+pub type RxffmdW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `ALGFILTER` reader - Enable Input Analog Glitch Filter"]
+pub type AlgfilterR = crate::BitReader;
+#[doc = "Field `ALGFILTER` writer - Enable Input Analog Glitch Filter"]
+pub type AlgfilterW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `DLGFILTER` reader - Enable Input Digital Glitch Filter"]
+pub type DlgfilterR = crate::BitReader;
+#[doc = "Field `DLGFILTER` writer - Enable Input Digital Glitch Filter"]
+pub type DlgfilterW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `LOOPBACK` reader - Enable LoopBack Mode"]
+pub type LoopbackR = crate::BitReader;
+#[doc = "Field `LOOPBACK` writer - Enable LoopBack Mode"]
+pub type LoopbackW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TMCONFIGENB` reader - Enable Timing Config Register"]
+pub type TmconfigenbR = crate::BitReader;
+#[doc = "Field `TMCONFIGENB` writer - Enable Timing Config Register"]
+pub type TmconfigenbW<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - I2C CLK Enabled"]
+    #[inline(always)]
+    pub fn clkenabled(&self) -> ClkenabledR {
+        ClkenabledR::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - I2C Activated"]
+    #[inline(always)]
+    pub fn enabled(&self) -> EnabledR {
+        EnabledR::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - I2C Active"]
+    #[inline(always)]
+    pub fn enable(&self) -> EnableR {
+        EnableR::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - TX FIFIO Empty Mode"]
+    #[inline(always)]
+    pub fn txfemd(&self) -> TxfemdR {
+        TxfemdR::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - RX FIFO Full Mode"]
+    #[inline(always)]
+    pub fn rxffmd(&self) -> RxffmdR {
+        RxffmdR::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 5 - Enable Input Analog Glitch Filter"]
+    #[inline(always)]
+    pub fn algfilter(&self) -> AlgfilterR {
+        AlgfilterR::new(((self.bits >> 5) & 1) != 0)
+    }
+    #[doc = "Bit 6 - Enable Input Digital Glitch Filter"]
+    #[inline(always)]
+    pub fn dlgfilter(&self) -> DlgfilterR {
+        DlgfilterR::new(((self.bits >> 6) & 1) != 0)
+    }
+    #[doc = "Bit 8 - Enable LoopBack Mode"]
+    #[inline(always)]
+    pub fn loopback(&self) -> LoopbackR {
+        LoopbackR::new(((self.bits >> 8) & 1) != 0)
+    }
+    #[doc = "Bit 9 - Enable Timing Config Register"]
+    #[inline(always)]
+    pub fn tmconfigenb(&self) -> TmconfigenbR {
+        TmconfigenbR::new(((self.bits >> 9) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - I2C CLK Enabled"]
+    #[inline(always)]
+    #[must_use]
+    pub fn clkenabled(&mut self) -> ClkenabledW<CtrlSpec> {
+        ClkenabledW::new(self, 0)
+    }
+    #[doc = "Bit 1 - I2C Activated"]
+    #[inline(always)]
+    #[must_use]
+    pub fn enabled(&mut self) -> EnabledW<CtrlSpec> {
+        EnabledW::new(self, 1)
+    }
+    #[doc = "Bit 2 - I2C Active"]
+    #[inline(always)]
+    #[must_use]
+    pub fn enable(&mut self) -> EnableW<CtrlSpec> {
+        EnableW::new(self, 2)
+    }
+    #[doc = "Bit 3 - TX FIFIO Empty Mode"]
+    #[inline(always)]
+    #[must_use]
+    pub fn txfemd(&mut self) -> TxfemdW<CtrlSpec> {
+        TxfemdW::new(self, 3)
+    }
+    #[doc = "Bit 4 - RX FIFO Full Mode"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rxffmd(&mut self) -> RxffmdW<CtrlSpec> {
+        RxffmdW::new(self, 4)
+    }
+    #[doc = "Bit 5 - Enable Input Analog Glitch Filter"]
+    #[inline(always)]
+    #[must_use]
+    pub fn algfilter(&mut self) -> AlgfilterW<CtrlSpec> {
+        AlgfilterW::new(self, 5)
+    }
+    #[doc = "Bit 6 - Enable Input Digital Glitch Filter"]
+    #[inline(always)]
+    #[must_use]
+    pub fn dlgfilter(&mut self) -> DlgfilterW<CtrlSpec> {
+        DlgfilterW::new(self, 6)
+    }
+    #[doc = "Bit 8 - Enable LoopBack Mode"]
+    #[inline(always)]
+    #[must_use]
+    pub fn loopback(&mut self) -> LoopbackW<CtrlSpec> {
+        LoopbackW::new(self, 8)
+    }
+    #[doc = "Bit 9 - Enable Timing Config Register"]
+    #[inline(always)]
+    #[must_use]
+    pub fn tmconfigenb(&mut self) -> TmconfigenbW<CtrlSpec> {
+        TmconfigenbW::new(self, 9)
+    }
+}
+#[doc = "Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CtrlSpec;
+impl crate::RegisterSpec for CtrlSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`ctrl::R`](R) reader structure"]
+impl crate::Readable for CtrlSpec {}
+#[doc = "`write(|w| ..)` method takes [`ctrl::W`](W) writer structure"]
+impl crate::Writable for CtrlSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CTRL to value 0"]
+impl crate::Resettable for CtrlSpec {
+    const RESET_VALUE: u32 = 0;
+}

va108xx/src/i2ca/data.rs

@@ -0,0 +1,27 @@
+#[doc = "Register `DATA` reader"]
+pub type R = crate::R<DataSpec>;
+#[doc = "Register `DATA` writer"]
+pub type W = crate::W<DataSpec>;
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        write!(f, "{}", self.bits())
+    }
+}
+impl W {}
+#[doc = "Data Input/Output\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct DataSpec;
+impl crate::RegisterSpec for DataSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`data::R`](R) reader structure"]
+impl crate::Readable for DataSpec {}
+#[doc = "`write(|w| ..)` method takes [`data::W`](W) writer structure"]
+impl crate::Writable for DataSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets DATA to value 0"]
+impl crate::Resettable for DataSpec {
+    const RESET_VALUE: u32 = 0;
+}

va108xx/src/i2ca/fifo_clr.rs

@@ -0,0 +1,35 @@
+#[doc = "Register `FIFO_CLR` writer"]
+pub type W = crate::W<FifoClrSpec>;
+#[doc = "Field `RXFIFO` writer - Clear Rx FIFO"]
+pub type RxfifoW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TXFIFO` writer - Clear Tx FIFO"]
+pub type TxfifoW<'a, REG> = crate::BitWriter<'a, REG>;
+impl W {
+    #[doc = "Bit 0 - Clear Rx FIFO"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rxfifo(&mut self) -> RxfifoW<FifoClrSpec> {
+        RxfifoW::new(self, 0)
+    }
+    #[doc = "Bit 1 - Clear Tx FIFO"]
+    #[inline(always)]
+    #[must_use]
+    pub fn txfifo(&mut self) -> TxfifoW<FifoClrSpec> {
+        TxfifoW::new(self, 1)
+    }
+}
+#[doc = "Clear FIFO Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifo_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct FifoClrSpec;
+impl crate::RegisterSpec for FifoClrSpec {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [`fifo_clr::W`](W) writer structure"]
+impl crate::Writable for FifoClrSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets FIFO_CLR to value 0"]
+impl crate::Resettable for FifoClrSpec {
+    const RESET_VALUE: u32 = 0;
+}

va108xx/src/i2ca/irq_enb.rs

@@ -0,0 +1,235 @@
+#[doc = "Register `IRQ_ENB` reader"]
+pub type R = crate::R<IrqEnbSpec>;
+#[doc = "Register `IRQ_ENB` writer"]
+pub type W = crate::W<IrqEnbSpec>;
+#[doc = "Field `I2CIDLE` reader - I2C Bus is Idle"]
+pub type I2cidleR = crate::BitReader;
+#[doc = "Field `I2CIDLE` writer - I2C Bus is Idle"]
+pub type I2cidleW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `IDLE` reader - Controller is Idle"]
+pub type IdleR = crate::BitReader;
+#[doc = "Field `IDLE` writer - Controller is Idle"]
+pub type IdleW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `WAITING` reader - Controller is Waiting"]
+pub type WaitingR = crate::BitReader;
+#[doc = "Field `WAITING` writer - Controller is Waiting"]
+pub type WaitingW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `STALLED` reader - Controller is Stalled"]
+pub type StalledR = crate::BitReader;
+#[doc = "Field `STALLED` writer - Controller is Stalled"]
+pub type StalledW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `ARBLOST` reader - I2C Arbitration was lost"]
+pub type ArblostR = crate::BitReader;
+#[doc = "Field `ARBLOST` writer - I2C Arbitration was lost"]
+pub type ArblostW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `NACKADDR` reader - I2C Address was not Acknowledged"]
+pub type NackaddrR = crate::BitReader;
+#[doc = "Field `NACKADDR` writer - I2C Address was not Acknowledged"]
+pub type NackaddrW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `NACKDATA` reader - I2C Data was not Acknowledged"]
+pub type NackdataR = crate::BitReader;
+#[doc = "Field `NACKDATA` writer - I2C Data was not Acknowledged"]
+pub type NackdataW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CLKLOTO` reader - I2C Clock Low Timeout"]
+pub type ClklotoR = crate::BitReader;
+#[doc = "Field `CLKLOTO` writer - I2C Clock Low Timeout"]
+pub type ClklotoW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TXOVERFLOW` reader - TX FIFO Overflowed"]
+pub type TxoverflowR = crate::BitReader;
+#[doc = "Field `TXOVERFLOW` writer - TX FIFO Overflowed"]
+pub type TxoverflowW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `RXOVERFLOW` reader - TX FIFO Overflowed"]
+pub type RxoverflowR = crate::BitReader;
+#[doc = "Field `RXOVERFLOW` writer - TX FIFO Overflowed"]
+pub type RxoverflowW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TXREADY` reader - TX FIFO Ready"]
+pub type TxreadyR = crate::BitReader;
+#[doc = "Field `TXREADY` writer - TX FIFO Ready"]
+pub type TxreadyW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `RXREADY` reader - RX FIFO Ready"]
+pub type RxreadyR = crate::BitReader;
+#[doc = "Field `RXREADY` writer - RX FIFO Ready"]
+pub type RxreadyW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TXEMPTY` reader - TX FIFO Empty"]
+pub type TxemptyR = crate::BitReader;
+#[doc = "Field `TXEMPTY` writer - TX FIFO Empty"]
+pub type TxemptyW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `RXFULL` reader - RX FIFO Full"]
+pub type RxfullR = crate::BitReader;
+#[doc = "Field `RXFULL` writer - RX FIFO Full"]
+pub type RxfullW<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - I2C Bus is Idle"]
+    #[inline(always)]
+    pub fn i2cidle(&self) -> I2cidleR {
+        I2cidleR::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - Controller is Idle"]
+    #[inline(always)]
+    pub fn idle(&self) -> IdleR {
+        IdleR::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - Controller is Waiting"]
+    #[inline(always)]
+    pub fn waiting(&self) -> WaitingR {
+        WaitingR::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - Controller is Stalled"]
+    #[inline(always)]
+    pub fn stalled(&self) -> StalledR {
+        StalledR::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - I2C Arbitration was lost"]
+    #[inline(always)]
+    pub fn arblost(&self) -> ArblostR {
+        ArblostR::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 5 - I2C Address was not Acknowledged"]
+    #[inline(always)]
+    pub fn nackaddr(&self) -> NackaddrR {
+        NackaddrR::new(((self.bits >> 5) & 1) != 0)
+    }
+    #[doc = "Bit 6 - I2C Data was not Acknowledged"]
+    #[inline(always)]
+    pub fn nackdata(&self) -> NackdataR {
+        NackdataR::new(((self.bits >> 6) & 1) != 0)
+    }
+    #[doc = "Bit 7 - I2C Clock Low Timeout"]
+    #[inline(always)]
+    pub fn clkloto(&self) -> ClklotoR {
+        ClklotoR::new(((self.bits >> 7) & 1) != 0)
+    }
+    #[doc = "Bit 10 - TX FIFO Overflowed"]
+    #[inline(always)]
+    pub fn txoverflow(&self) -> TxoverflowR {
+        TxoverflowR::new(((self.bits >> 10) & 1) != 0)
+    }
+    #[doc = "Bit 11 - TX FIFO Overflowed"]
+    #[inline(always)]
+    pub fn rxoverflow(&self) -> RxoverflowR {
+        RxoverflowR::new(((self.bits >> 11) & 1) != 0)
+    }
+    #[doc = "Bit 12 - TX FIFO Ready"]
+    #[inline(always)]
+    pub fn txready(&self) -> TxreadyR {
+        TxreadyR::new(((self.bits >> 12) & 1) != 0)
+    }
+    #[doc = "Bit 13 - RX FIFO Ready"]
+    #[inline(always)]
+    pub fn rxready(&self) -> RxreadyR {
+        RxreadyR::new(((self.bits >> 13) & 1) != 0)
+    }
+    #[doc = "Bit 14 - TX FIFO Empty"]
+    #[inline(always)]
+    pub fn txempty(&self) -> TxemptyR {
+        TxemptyR::new(((self.bits >> 14) & 1) != 0)
+    }
+    #[doc = "Bit 15 - RX FIFO Full"]
+    #[inline(always)]
+    pub fn rxfull(&self) -> RxfullR {
+        RxfullR::new(((self.bits >> 15) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - I2C Bus is Idle"]
+    #[inline(always)]
+    #[must_use]
+    pub fn i2cidle(&mut self) -> I2cidleW<IrqEnbSpec> {
+        I2cidleW::new(self, 0)
+    }
+    #[doc = "Bit 1 - Controller is Idle"]
+    #[inline(always)]
+    #[must_use]
+    pub fn idle(&mut self) -> IdleW<IrqEnbSpec> {
+        IdleW::new(self, 1)
+    }
+    #[doc = "Bit 2 - Controller is Waiting"]
+    #[inline(always)]
+    #[must_use]
+    pub fn waiting(&mut self) -> WaitingW<IrqEnbSpec> {
+        WaitingW::new(self, 2)
+    }
+    #[doc = "Bit 3 - Controller is Stalled"]
+    #[inline(always)]
+    #[must_use]
+    pub fn stalled(&mut self) -> StalledW<IrqEnbSpec> {
+        StalledW::new(self, 3)
+    }
+    #[doc = "Bit 4 - I2C Arbitration was lost"]
+    #[inline(always)]
+    #[must_use]
+    pub fn arblost(&mut self) -> ArblostW<IrqEnbSpec> {
+        ArblostW::new(self, 4)
+    }
+    #[doc = "Bit 5 - I2C Address was not Acknowledged"]
+    #[inline(always)]
+    #[must_use]
+    pub fn nackaddr(&mut self) -> NackaddrW<IrqEnbSpec> {
+        NackaddrW::new(self, 5)
+    }
+    #[doc = "Bit 6 - I2C Data was not Acknowledged"]
+    #[inline(always)]
+    #[must_use]
+    pub fn nackdata(&mut self) -> NackdataW<IrqEnbSpec> {
+        NackdataW::new(self, 6)
+    }
+    #[doc = "Bit 7 - I2C Clock Low Timeout"]
+    #[inline(always)]
+    #[must_use]
+    pub fn clkloto(&mut self) -> ClklotoW<IrqEnbSpec> {
+        ClklotoW::new(self, 7)
+    }
+    #[doc = "Bit 10 - TX FIFO Overflowed"]
+    #[inline(always)]
+    #[must_use]
+    pub fn txoverflow(&mut self) -> TxoverflowW<IrqEnbSpec> {
+        TxoverflowW::new(self, 10)
+    }
+    #[doc = "Bit 11 - TX FIFO Overflowed"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rxoverflow(&mut self) -> RxoverflowW<IrqEnbSpec> {
+        RxoverflowW::new(self, 11)
+    }
+    #[doc = "Bit 12 - TX FIFO Ready"]
+    #[inline(always)]
+    #[must_use]
+    pub fn txready(&mut self) -> TxreadyW<IrqEnbSpec> {
+        TxreadyW::new(self, 12)
+    }
+    #[doc = "Bit 13 - RX FIFO Ready"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rxready(&mut self) -> RxreadyW<IrqEnbSpec> {
+        RxreadyW::new(self, 13)
+    }
+    #[doc = "Bit 14 - TX FIFO Empty"]
+    #[inline(always)]
+    #[must_use]
+    pub fn txempty(&mut self) -> TxemptyW<IrqEnbSpec> {
+        TxemptyW::new(self, 14)
+    }
+    #[doc = "Bit 15 - RX FIFO Full"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rxfull(&mut self) -> RxfullW<IrqEnbSpec> {
+        RxfullW::new(self, 15)
+    }
+}
+#[doc = "Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_enb::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_enb::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct IrqEnbSpec;
+impl crate::RegisterSpec for IrqEnbSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`irq_enb::R`](R) reader structure"]
+impl crate::Readable for IrqEnbSpec {}
+#[doc = "`write(|w| ..)` method takes [`irq_enb::W`](W) writer structure"]
+impl crate::Writable for IrqEnbSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets IRQ_ENB to value 0"]
+impl crate::Resettable for IrqEnbSpec {
+    const RESET_VALUE: u32 = 0;
+}

va108xx/src/i2ca/perid.rs

@@ -0,0 +1,18 @@
+#[doc = "Register `PERID` reader"]
+pub type R = crate::R<PeridSpec>;
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        write!(f, "{}", self.bits())
+    }
+}
+#[doc = "Peripheral ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`perid::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct PeridSpec;
+impl crate::RegisterSpec for PeridSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`perid::R`](R) reader structure"]
+impl crate::Readable for PeridSpec {}
+#[doc = "`reset()` method sets PERID to value 0x0014_07e1"]
+impl crate::Resettable for PeridSpec {
+    const RESET_VALUE: u32 = 0x0014_07e1;
+}

va108xx/src/i2ca/rxcount.rs

@@ -0,0 +1,18 @@
+#[doc = "Register `RXCOUNT` reader"]
+pub type R = crate::R<RxcountSpec>;
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        write!(f, "{}", self.bits())
+    }
+}
+#[doc = "RX Count Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxcount::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct RxcountSpec;
+impl crate::RegisterSpec for RxcountSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`rxcount::R`](R) reader structure"]
+impl crate::Readable for RxcountSpec {}
+#[doc = "`reset()` method sets RXCOUNT to value 0"]
+impl crate::Resettable for RxcountSpec {
+    const RESET_VALUE: u32 = 0;
+}

va108xx/src/i2ca/rxfifoirqtrg.rs

@@ -0,0 +1,27 @@
+#[doc = "Register `RXFIFOIRQTRG` reader"]
+pub type R = crate::R<RxfifoirqtrgSpec>;
+#[doc = "Register `RXFIFOIRQTRG` writer"]
+pub type W = crate::W<RxfifoirqtrgSpec>;
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        write!(f, "{}", self.bits())
+    }
+}
+impl W {}
+#[doc = "Rx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxfifoirqtrg::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxfifoirqtrg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct RxfifoirqtrgSpec;
+impl crate::RegisterSpec for RxfifoirqtrgSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`rxfifoirqtrg::R`](R) reader structure"]
+impl crate::Readable for RxfifoirqtrgSpec {}
+#[doc = "`write(|w| ..)` method takes [`rxfifoirqtrg::W`](W) writer structure"]
+impl crate::Writable for RxfifoirqtrgSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets RXFIFOIRQTRG to value 0"]
+impl crate::Resettable for RxfifoirqtrgSpec {
+    const RESET_VALUE: u32 = 0;
+}

va108xx/src/i2ca/s0_address.rs

@@ -0,0 +1,27 @@
+#[doc = "Register `S0_ADDRESS` reader"]
+pub type R = crate::R<S0AddressSpec>;
+#[doc = "Register `S0_ADDRESS` writer"]
+pub type W = crate::W<S0AddressSpec>;
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        write!(f, "{}", self.bits())
+    }
+}
+impl W {}
+#[doc = "Slave I2C Address Value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_address::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_address::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct S0AddressSpec;
+impl crate::RegisterSpec for S0AddressSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`s0_address::R`](R) reader structure"]
+impl crate::Readable for S0AddressSpec {}
+#[doc = "`write(|w| ..)` method takes [`s0_address::W`](W) writer structure"]
+impl crate::Writable for S0AddressSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets S0_ADDRESS to value 0"]
+impl crate::Resettable for S0AddressSpec {
+    const RESET_VALUE: u32 = 0;
+}

va108xx/src/i2ca/s0_addressb.rs

@@ -0,0 +1,27 @@
+#[doc = "Register `S0_ADDRESSB` reader"]
+pub type R = crate::R<S0AddressbSpec>;
+#[doc = "Register `S0_ADDRESSB` writer"]
+pub type W = crate::W<S0AddressbSpec>;
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        write!(f, "{}", self.bits())
+    }
+}
+impl W {}
+#[doc = "Slave I2C Address B Value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_addressb::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_addressb::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct S0AddressbSpec;
+impl crate::RegisterSpec for S0AddressbSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`s0_addressb::R`](R) reader structure"]
+impl crate::Readable for S0AddressbSpec {}
+#[doc = "`write(|w| ..)` method takes [`s0_addressb::W`](W) writer structure"]
+impl crate::Writable for S0AddressbSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets S0_ADDRESSB to value 0"]
+impl crate::Resettable for S0AddressbSpec {
+    const RESET_VALUE: u32 = 0;
+}

va108xx/src/i2ca/s0_addressmask.rs

@@ -0,0 +1,27 @@
+#[doc = "Register `S0_ADDRESSMASK` reader"]
+pub type R = crate::R<S0AddressmaskSpec>;
+#[doc = "Register `S0_ADDRESSMASK` writer"]
+pub type W = crate::W<S0AddressmaskSpec>;
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        write!(f, "{}", self.bits())
+    }
+}
+impl W {}
+#[doc = "Slave I2C Address Mask value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_addressmask::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_addressmask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct S0AddressmaskSpec;
+impl crate::RegisterSpec for S0AddressmaskSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`s0_addressmask::R`](R) reader structure"]
+impl crate::Readable for S0AddressmaskSpec {}
+#[doc = "`write(|w| ..)` method takes [`s0_addressmask::W`](W) writer structure"]
+impl crate::Writable for S0AddressmaskSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets S0_ADDRESSMASK to value 0"]
+impl crate::Resettable for S0AddressmaskSpec {
+    const RESET_VALUE: u32 = 0;
+}

va108xx/src/i2ca/s0_addressmaskb.rs

@@ -0,0 +1,27 @@
+#[doc = "Register `S0_ADDRESSMASKB` reader"]
+pub type R = crate::R<S0AddressmaskbSpec>;
+#[doc = "Register `S0_ADDRESSMASKB` writer"]
+pub type W = crate::W<S0AddressmaskbSpec>;
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        write!(f, "{}", self.bits())
+    }
+}
+impl W {}
+#[doc = "Slave I2C Address B Mask value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_addressmaskb::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_addressmaskb::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct S0AddressmaskbSpec;
+impl crate::RegisterSpec for S0AddressmaskbSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`s0_addressmaskb::R`](R) reader structure"]
+impl crate::Readable for S0AddressmaskbSpec {}
+#[doc = "`write(|w| ..)` method takes [`s0_addressmaskb::W`](W) writer structure"]
+impl crate::Writable for S0AddressmaskbSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets S0_ADDRESSMASKB to value 0"]
+impl crate::Resettable for S0AddressmaskbSpec {
+    const RESET_VALUE: u32 = 0;
+}

va108xx/src/i2ca/s0_ctrl.rs

@@ -0,0 +1,100 @@
+#[doc = "Register `S0_CTRL` reader"]
+pub type R = crate::R<S0CtrlSpec>;
+#[doc = "Register `S0_CTRL` writer"]
+pub type W = crate::W<S0CtrlSpec>;
+#[doc = "Field `CLKENABLED` reader - I2C Enabled"]
+pub type ClkenabledR = crate::BitReader;
+#[doc = "Field `CLKENABLED` writer - I2C Enabled"]
+pub type ClkenabledW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `ENABLED` reader - I2C Activated"]
+pub type EnabledR = crate::BitReader;
+#[doc = "Field `ENABLED` writer - I2C Activated"]
+pub type EnabledW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `ENABLE` reader - I2C Active"]
+pub type EnableR = crate::BitReader;
+#[doc = "Field `ENABLE` writer - I2C Active"]
+pub type EnableW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TXFEMD` reader - TX FIFIO Empty Mode"]
+pub type TxfemdR = crate::BitReader;
+#[doc = "Field `TXFEMD` writer - TX FIFIO Empty Mode"]
+pub type TxfemdW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `RXFFMD` reader - RX FIFO Full Mode"]
+pub type RxffmdR = crate::BitReader;
+#[doc = "Field `RXFFMD` writer - RX FIFO Full Mode"]
+pub type RxffmdW<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - I2C Enabled"]
+    #[inline(always)]
+    pub fn clkenabled(&self) -> ClkenabledR {
+        ClkenabledR::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - I2C Activated"]
+    #[inline(always)]
+    pub fn enabled(&self) -> EnabledR {
+        EnabledR::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - I2C Active"]
+    #[inline(always)]
+    pub fn enable(&self) -> EnableR {
+        EnableR::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - TX FIFIO Empty Mode"]
+    #[inline(always)]
+    pub fn txfemd(&self) -> TxfemdR {
+        TxfemdR::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - RX FIFO Full Mode"]
+    #[inline(always)]
+    pub fn rxffmd(&self) -> RxffmdR {
+        RxffmdR::new(((self.bits >> 4) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - I2C Enabled"]
+    #[inline(always)]
+    #[must_use]
+    pub fn clkenabled(&mut self) -> ClkenabledW<S0CtrlSpec> {
+        ClkenabledW::new(self, 0)
+    }
+    #[doc = "Bit 1 - I2C Activated"]
+    #[inline(always)]
+    #[must_use]
+    pub fn enabled(&mut self) -> EnabledW<S0CtrlSpec> {
+        EnabledW::new(self, 1)
+    }
+    #[doc = "Bit 2 - I2C Active"]
+    #[inline(always)]
+    #[must_use]
+    pub fn enable(&mut self) -> EnableW<S0CtrlSpec> {
+        EnableW::new(self, 2)
+    }
+    #[doc = "Bit 3 - TX FIFIO Empty Mode"]
+    #[inline(always)]
+    #[must_use]
+    pub fn txfemd(&mut self) -> TxfemdW<S0CtrlSpec> {
+        TxfemdW::new(self, 3)
+    }
+    #[doc = "Bit 4 - RX FIFO Full Mode"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rxffmd(&mut self) -> RxffmdW<S0CtrlSpec> {
+        RxffmdW::new(self, 4)
+    }
+}
+#[doc = "Slave Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_ctrl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct S0CtrlSpec;
+impl crate::RegisterSpec for S0CtrlSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`s0_ctrl::R`](R) reader structure"]
+impl crate::Readable for S0CtrlSpec {}
+#[doc = "`write(|w| ..)` method takes [`s0_ctrl::W`](W) writer structure"]
+impl crate::Writable for S0CtrlSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets S0_CTRL to value 0"]
+impl crate::Resettable for S0CtrlSpec {
+    const RESET_VALUE: u32 = 0;
+}

va108xx/src/i2ca/s0_data.rs

@@ -0,0 +1,27 @@
+#[doc = "Register `S0_DATA` reader"]
+pub type R = crate::R<S0DataSpec>;
+#[doc = "Register `S0_DATA` writer"]
+pub type W = crate::W<S0DataSpec>;
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        write!(f, "{}", self.bits())
+    }
+}
+impl W {}
+#[doc = "Slave Data Input/Output\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_data::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_data::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct S0DataSpec;
+impl crate::RegisterSpec for S0DataSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`s0_data::R`](R) reader structure"]
+impl crate::Readable for S0DataSpec {}
+#[doc = "`write(|w| ..)` method takes [`s0_data::W`](W) writer structure"]
+impl crate::Writable for S0DataSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets S0_DATA to value 0"]
+impl crate::Resettable for S0DataSpec {
+    const RESET_VALUE: u32 = 0;
+}

va108xx/src/i2ca/s0_fifo_clr.rs

@@ -0,0 +1,35 @@
+#[doc = "Register `S0_FIFO_CLR` writer"]
+pub type W = crate::W<S0FifoClrSpec>;
+#[doc = "Field `RXFIFO` writer - Clear Rx FIFO"]
+pub type RxfifoW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TXFIFO` writer - Clear Tx FIFO"]
+pub type TxfifoW<'a, REG> = crate::BitWriter<'a, REG>;
+impl W {
+    #[doc = "Bit 0 - Clear Rx FIFO"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rxfifo(&mut self) -> RxfifoW<S0FifoClrSpec> {
+        RxfifoW::new(self, 0)
+    }
+    #[doc = "Bit 1 - Clear Tx FIFO"]
+    #[inline(always)]
+    #[must_use]
+    pub fn txfifo(&mut self) -> TxfifoW<S0FifoClrSpec> {
+        TxfifoW::new(self, 1)
+    }
+}
+#[doc = "Slave Clear FIFO Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_fifo_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct S0FifoClrSpec;
+impl crate::RegisterSpec for S0FifoClrSpec {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [`s0_fifo_clr::W`](W) writer structure"]
+impl crate::Writable for S0FifoClrSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets S0_FIFO_CLR to value 0"]
+impl crate::Resettable for S0FifoClrSpec {
+    const RESET_VALUE: u32 = 0;
+}

va108xx/src/i2ca/s0_irq_enb.rs

@@ -0,0 +1,265 @@
+#[doc = "Register `S0_IRQ_ENB` reader"]
+pub type R = crate::R<S0IrqEnbSpec>;
+#[doc = "Register `S0_IRQ_ENB` writer"]
+pub type W = crate::W<S0IrqEnbSpec>;
+#[doc = "Field `COMPLETED` reader - Controller Complted a Transaction"]
+pub type CompletedR = crate::BitReader;
+#[doc = "Field `COMPLETED` writer - Controller Complted a Transaction"]
+pub type CompletedW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `IDLE` reader - Controller is Idle"]
+pub type IdleR = crate::BitReader;
+#[doc = "Field `IDLE` writer - Controller is Idle"]
+pub type IdleW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `WAITING` reader - Controller is Waiting"]
+pub type WaitingR = crate::BitReader;
+#[doc = "Field `WAITING` writer - Controller is Waiting"]
+pub type WaitingW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TXSTALLED` reader - Controller is Tx Stalled"]
+pub type TxstalledR = crate::BitReader;
+#[doc = "Field `TXSTALLED` writer - Controller is Tx Stalled"]
+pub type TxstalledW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `RXSTALLED` reader - Controller is Rx Stalled"]
+pub type RxstalledR = crate::BitReader;
+#[doc = "Field `RXSTALLED` writer - Controller is Rx Stalled"]
+pub type RxstalledW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `ADDRESSMATCH` reader - I2C Address Match"]
+pub type AddressmatchR = crate::BitReader;
+#[doc = "Field `ADDRESSMATCH` writer - I2C Address Match"]
+pub type AddressmatchW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `NACKDATA` reader - I2C Data was not Acknowledged"]
+pub type NackdataR = crate::BitReader;
+#[doc = "Field `NACKDATA` writer - I2C Data was not Acknowledged"]
+pub type NackdataW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `RXDATAFIRST` reader - Pending Data is first Byte following Address"]
+pub type RxdatafirstR = crate::BitReader;
+#[doc = "Field `RXDATAFIRST` writer - Pending Data is first Byte following Address"]
+pub type RxdatafirstW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `I2C_START` reader - I2C Start Condition"]
+pub type I2cStartR = crate::BitReader;
+#[doc = "Field `I2C_START` writer - I2C Start Condition"]
+pub type I2cStartW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `I2C_STOP` reader - I2C Stop Condition"]
+pub type I2cStopR = crate::BitReader;
+#[doc = "Field `I2C_STOP` writer - I2C Stop Condition"]
+pub type I2cStopW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TXUNDERFLOW` reader - TX FIFO Underflowed"]
+pub type TxunderflowR = crate::BitReader;
+#[doc = "Field `TXUNDERFLOW` writer - TX FIFO Underflowed"]
+pub type TxunderflowW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `RXOVERFLOW` reader - TX FIFO Overflowed"]
+pub type RxoverflowR = crate::BitReader;
+#[doc = "Field `RXOVERFLOW` writer - TX FIFO Overflowed"]
+pub type RxoverflowW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TXREADY` reader - TX FIFO Ready"]
+pub type TxreadyR = crate::BitReader;
+#[doc = "Field `TXREADY` writer - TX FIFO Ready"]
+pub type TxreadyW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `RXREADY` reader - RX FIFO Ready"]
+pub type RxreadyR = crate::BitReader;
+#[doc = "Field `RXREADY` writer - RX FIFO Ready"]
+pub type RxreadyW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TXEMPTY` reader - TX FIFO Empty"]
+pub type TxemptyR = crate::BitReader;
+#[doc = "Field `TXEMPTY` writer - TX FIFO Empty"]
+pub type TxemptyW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `RXFULL` reader - RX FIFO Full"]
+pub type RxfullR = crate::BitReader;
+#[doc = "Field `RXFULL` writer - RX FIFO Full"]
+pub type RxfullW<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - Controller Complted a Transaction"]
+    #[inline(always)]
+    pub fn completed(&self) -> CompletedR {
+        CompletedR::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - Controller is Idle"]
+    #[inline(always)]
+    pub fn idle(&self) -> IdleR {
+        IdleR::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - Controller is Waiting"]
+    #[inline(always)]
+    pub fn waiting(&self) -> WaitingR {
+        WaitingR::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - Controller is Tx Stalled"]
+    #[inline(always)]
+    pub fn txstalled(&self) -> TxstalledR {
+        TxstalledR::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - Controller is Rx Stalled"]
+    #[inline(always)]
+    pub fn rxstalled(&self) -> RxstalledR {
+        RxstalledR::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 5 - I2C Address Match"]
+    #[inline(always)]
+    pub fn addressmatch(&self) -> AddressmatchR {
+        AddressmatchR::new(((self.bits >> 5) & 1) != 0)
+    }
+    #[doc = "Bit 6 - I2C Data was not Acknowledged"]
+    #[inline(always)]
+    pub fn nackdata(&self) -> NackdataR {
+        NackdataR::new(((self.bits >> 6) & 1) != 0)
+    }
+    #[doc = "Bit 7 - Pending Data is first Byte following Address"]
+    #[inline(always)]
+    pub fn rxdatafirst(&self) -> RxdatafirstR {
+        RxdatafirstR::new(((self.bits >> 7) & 1) != 0)
+    }
+    #[doc = "Bit 8 - I2C Start Condition"]
+    #[inline(always)]
+    pub fn i2c_start(&self) -> I2cStartR {
+        I2cStartR::new(((self.bits >> 8) & 1) != 0)
+    }
+    #[doc = "Bit 9 - I2C Stop Condition"]
+    #[inline(always)]
+    pub fn i2c_stop(&self) -> I2cStopR {
+        I2cStopR::new(((self.bits >> 9) & 1) != 0)
+    }
+    #[doc = "Bit 10 - TX FIFO Underflowed"]
+    #[inline(always)]
+    pub fn txunderflow(&self) -> TxunderflowR {
+        TxunderflowR::new(((self.bits >> 10) & 1) != 0)
+    }
+    #[doc = "Bit 11 - TX FIFO Overflowed"]
+    #[inline(always)]
+    pub fn rxoverflow(&self) -> RxoverflowR {
+        RxoverflowR::new(((self.bits >> 11) & 1) != 0)
+    }
+    #[doc = "Bit 12 - TX FIFO Ready"]
+    #[inline(always)]
+    pub fn txready(&self) -> TxreadyR {
+        TxreadyR::new(((self.bits >> 12) & 1) != 0)
+    }
+    #[doc = "Bit 13 - RX FIFO Ready"]
+    #[inline(always)]
+    pub fn rxready(&self) -> RxreadyR {
+        RxreadyR::new(((self.bits >> 13) & 1) != 0)
+    }
+    #[doc = "Bit 14 - TX FIFO Empty"]
+    #[inline(always)]
+    pub fn txempty(&self) -> TxemptyR {
+        TxemptyR::new(((self.bits >> 14) & 1) != 0)
+    }
+    #[doc = "Bit 15 - RX FIFO Full"]
+    #[inline(always)]
+    pub fn rxfull(&self) -> RxfullR {
+        RxfullR::new(((self.bits >> 15) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Controller Complted a Transaction"]
+    #[inline(always)]
+    #[must_use]
+    pub fn completed(&mut self) -> CompletedW<S0IrqEnbSpec> {
+        CompletedW::new(self, 0)
+    }
+    #[doc = "Bit 1 - Controller is Idle"]
+    #[inline(always)]
+    #[must_use]
+    pub fn idle(&mut self) -> IdleW<S0IrqEnbSpec> {
+        IdleW::new(self, 1)
+    }
+    #[doc = "Bit 2 - Controller is Waiting"]
+    #[inline(always)]
+    #[must_use]
+    pub fn waiting(&mut self) -> WaitingW<S0IrqEnbSpec> {
+        WaitingW::new(self, 2)
+    }
+    #[doc = "Bit 3 - Controller is Tx Stalled"]
+    #[inline(always)]
+    #[must_use]
+    pub fn txstalled(&mut self) -> TxstalledW<S0IrqEnbSpec> {
+        TxstalledW::new(self, 3)
+    }
+    #[doc = "Bit 4 - Controller is Rx Stalled"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rxstalled(&mut self) -> RxstalledW<S0IrqEnbSpec> {
+        RxstalledW::new(self, 4)
+    }
+    #[doc = "Bit 5 - I2C Address Match"]
+    #[inline(always)]
+    #[must_use]
+    pub fn addressmatch(&mut self) -> AddressmatchW<S0IrqEnbSpec> {
+        AddressmatchW::new(self, 5)
+    }
+    #[doc = "Bit 6 - I2C Data was not Acknowledged"]
+    #[inline(always)]
+    #[must_use]
+    pub fn nackdata(&mut self) -> NackdataW<S0IrqEnbSpec> {
+        NackdataW::new(self, 6)
+    }
+    #[doc = "Bit 7 - Pending Data is first Byte following Address"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rxdatafirst(&mut self) -> RxdatafirstW<S0IrqEnbSpec> {
+        RxdatafirstW::new(self, 7)
+    }
+    #[doc = "Bit 8 - I2C Start Condition"]
+    #[inline(always)]
+    #[must_use]
+    pub fn i2c_start(&mut self) -> I2cStartW<S0IrqEnbSpec> {
+        I2cStartW::new(self, 8)
+    }
+    #[doc = "Bit 9 - I2C Stop Condition"]
+    #[inline(always)]
+    #[must_use]
+    pub fn i2c_stop(&mut self) -> I2cStopW<S0IrqEnbSpec> {
+        I2cStopW::new(self, 9)
+    }
+    #[doc = "Bit 10 - TX FIFO Underflowed"]
+    #[inline(always)]
+    #[must_use]
+    pub fn txunderflow(&mut self) -> TxunderflowW<S0IrqEnbSpec> {
+        TxunderflowW::new(self, 10)
+    }
+    #[doc = "Bit 11 - TX FIFO Overflowed"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rxoverflow(&mut self) -> RxoverflowW<S0IrqEnbSpec> {
+        RxoverflowW::new(self, 11)
+    }
+    #[doc = "Bit 12 - TX FIFO Ready"]
+    #[inline(always)]
+    #[must_use]
+    pub fn txready(&mut self) -> TxreadyW<S0IrqEnbSpec> {
+        TxreadyW::new(self, 12)
+    }
+    #[doc = "Bit 13 - RX FIFO Ready"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rxready(&mut self) -> RxreadyW<S0IrqEnbSpec> {
+        RxreadyW::new(self, 13)
+    }
+    #[doc = "Bit 14 - TX FIFO Empty"]
+    #[inline(always)]
+    #[must_use]
+    pub fn txempty(&mut self) -> TxemptyW<S0IrqEnbSpec> {
+        TxemptyW::new(self, 14)
+    }
+    #[doc = "Bit 15 - RX FIFO Full"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rxfull(&mut self) -> RxfullW<S0IrqEnbSpec> {
+        RxfullW::new(self, 15)
+    }
+}
+#[doc = "Slave Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_irq_enb::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_irq_enb::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct S0IrqEnbSpec;
+impl crate::RegisterSpec for S0IrqEnbSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`s0_irq_enb::R`](R) reader structure"]
+impl crate::Readable for S0IrqEnbSpec {}
+#[doc = "`write(|w| ..)` method takes [`s0_irq_enb::W`](W) writer structure"]
+impl crate::Writable for S0IrqEnbSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets S0_IRQ_ENB to value 0"]
+impl crate::Resettable for S0IrqEnbSpec {
+    const RESET_VALUE: u32 = 0;
+}

va108xx/src/i2ca/s0_lastaddress.rs

@@ -0,0 +1,18 @@
+#[doc = "Register `S0_LASTADDRESS` reader"]
+pub type R = crate::R<S0LastaddressSpec>;
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        write!(f, "{}", self.bits())
+    }
+}
+#[doc = "Slave I2C Last Address value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_lastaddress::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct S0LastaddressSpec;
+impl crate::RegisterSpec for S0LastaddressSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`s0_lastaddress::R`](R) reader structure"]
+impl crate::Readable for S0LastaddressSpec {}
+#[doc = "`reset()` method sets S0_LASTADDRESS to value 0"]
+impl crate::Resettable for S0LastaddressSpec {
+    const RESET_VALUE: u32 = 0;
+}

va108xx/src/i2ca/s0_maxwords.rs

@@ -0,0 +1,27 @@
+#[doc = "Register `S0_MAXWORDS` reader"]
+pub type R = crate::R<S0MaxwordsSpec>;
+#[doc = "Register `S0_MAXWORDS` writer"]
+pub type W = crate::W<S0MaxwordsSpec>;
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        write!(f, "{}", self.bits())
+    }
+}
+impl W {}
+#[doc = "Slave MaxWords Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_maxwords::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_maxwords::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct S0MaxwordsSpec;
+impl crate::RegisterSpec for S0MaxwordsSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`s0_maxwords::R`](R) reader structure"]
+impl crate::Readable for S0MaxwordsSpec {}
+#[doc = "`write(|w| ..)` method takes [`s0_maxwords::W`](W) writer structure"]
+impl crate::Writable for S0MaxwordsSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets S0_MAXWORDS to value 0"]
+impl crate::Resettable for S0MaxwordsSpec {
+    const RESET_VALUE: u32 = 0;
+}

va108xx/src/i2ca/s0_rxcount.rs

@@ -0,0 +1,18 @@
+#[doc = "Register `S0_RXCOUNT` reader"]
+pub type R = crate::R<S0RxcountSpec>;
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        write!(f, "{}", self.bits())
+    }
+}
+#[doc = "Slave RX Count Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_rxcount::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct S0RxcountSpec;
+impl crate::RegisterSpec for S0RxcountSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`s0_rxcount::R`](R) reader structure"]
+impl crate::Readable for S0RxcountSpec {}
+#[doc = "`reset()` method sets S0_RXCOUNT to value 0"]
+impl crate::Resettable for S0RxcountSpec {
+    const RESET_VALUE: u32 = 0;
+}

va108xx/src/i2ca/s0_rxfifoirqtrg.rs

@@ -0,0 +1,27 @@
+#[doc = "Register `S0_RXFIFOIRQTRG` reader"]
+pub type R = crate::R<S0RxfifoirqtrgSpec>;
+#[doc = "Register `S0_RXFIFOIRQTRG` writer"]
+pub type W = crate::W<S0RxfifoirqtrgSpec>;
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        write!(f, "{}", self.bits())
+    }
+}
+impl W {}
+#[doc = "Slave Rx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_rxfifoirqtrg::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_rxfifoirqtrg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct S0RxfifoirqtrgSpec;
+impl crate::RegisterSpec for S0RxfifoirqtrgSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`s0_rxfifoirqtrg::R`](R) reader structure"]
+impl crate::Readable for S0RxfifoirqtrgSpec {}
+#[doc = "`write(|w| ..)` method takes [`s0_rxfifoirqtrg::W`](W) writer structure"]
+impl crate::Writable for S0RxfifoirqtrgSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets S0_RXFIFOIRQTRG to value 0"]
+impl crate::Resettable for S0RxfifoirqtrgSpec {
+    const RESET_VALUE: u32 = 0;
+}

va108xx/src/i2ca/s0_state.rs

@@ -0,0 +1,18 @@
+#[doc = "Register `S0_STATE` reader"]
+pub type R = crate::R<S0StateSpec>;
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        write!(f, "{}", self.bits())
+    }
+}
+#[doc = "Internal STATE of I2C Slave Controller\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_state::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct S0StateSpec;
+impl crate::RegisterSpec for S0StateSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`s0_state::R`](R) reader structure"]
+impl crate::Readable for S0StateSpec {}
+#[doc = "`reset()` method sets S0_STATE to value 0"]
+impl crate::Resettable for S0StateSpec {
+    const RESET_VALUE: u32 = 0;
+}

va108xx/src/i2ca/s0_status.rs

@@ -0,0 +1,134 @@
+#[doc = "Register `S0_STATUS` reader"]
+pub type R = crate::R<S0StatusSpec>;
+#[doc = "Field `COMPLETED` reader - Controller Complted a Transaction"]
+pub type CompletedR = crate::BitReader;
+#[doc = "Field `IDLE` reader - Controller is Idle"]
+pub type IdleR = crate::BitReader;
+#[doc = "Field `WAITING` reader - Controller is Waiting"]
+pub type WaitingR = crate::BitReader;
+#[doc = "Field `TXSTALLED` reader - Controller is Tx Stalled"]
+pub type TxstalledR = crate::BitReader;
+#[doc = "Field `RXSTALLED` reader - Controller is Rx Stalled"]
+pub type RxstalledR = crate::BitReader;
+#[doc = "Field `ADDRESSMATCH` reader - I2C Address Match"]
+pub type AddressmatchR = crate::BitReader;
+#[doc = "Field `NACKDATA` reader - I2C Data was not Acknowledged"]
+pub type NackdataR = crate::BitReader;
+#[doc = "Field `RXDATAFIRST` reader - Pending Data is first Byte following Address"]
+pub type RxdatafirstR = crate::BitReader;
+#[doc = "Field `RXNEMPTY` reader - RX FIFO is Not Empty"]
+pub type RxnemptyR = crate::BitReader;
+#[doc = "Field `RXFULL` reader - RX FIFO is Full"]
+pub type RxfullR = crate::BitReader;
+#[doc = "Field `RXTRIGGER` reader - RX FIFO Above Trigger Level"]
+pub type RxtriggerR = crate::BitReader;
+#[doc = "Field `TXEMPTY` reader - TX FIFO is Empty"]
+pub type TxemptyR = crate::BitReader;
+#[doc = "Field `TXNFULL` reader - TX FIFO is Full"]
+pub type TxnfullR = crate::BitReader;
+#[doc = "Field `TXTRIGGER` reader - TX FIFO Below Trigger Level"]
+pub type TxtriggerR = crate::BitReader;
+#[doc = "Field `RAW_BUSY` reader - I2C Raw Busy value"]
+pub type RawBusyR = crate::BitReader;
+#[doc = "Field `RAW_SDA` reader - I2C Raw SDA value"]
+pub type RawSdaR = crate::BitReader;
+#[doc = "Field `RAW_SCL` reader - I2C Raw SCL value"]
+pub type RawSclR = crate::BitReader;
+impl R {
+    #[doc = "Bit 0 - Controller Complted a Transaction"]
+    #[inline(always)]
+    pub fn completed(&self) -> CompletedR {
+        CompletedR::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - Controller is Idle"]
+    #[inline(always)]
+    pub fn idle(&self) -> IdleR {
+        IdleR::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - Controller is Waiting"]
+    #[inline(always)]
+    pub fn waiting(&self) -> WaitingR {
+        WaitingR::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - Controller is Tx Stalled"]
+    #[inline(always)]
+    pub fn txstalled(&self) -> TxstalledR {
+        TxstalledR::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - Controller is Rx Stalled"]
+    #[inline(always)]
+    pub fn rxstalled(&self) -> RxstalledR {
+        RxstalledR::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 5 - I2C Address Match"]
+    #[inline(always)]
+    pub fn addressmatch(&self) -> AddressmatchR {
+        AddressmatchR::new(((self.bits >> 5) & 1) != 0)
+    }
+    #[doc = "Bit 6 - I2C Data was not Acknowledged"]
+    #[inline(always)]
+    pub fn nackdata(&self) -> NackdataR {
+        NackdataR::new(((self.bits >> 6) & 1) != 0)
+    }
+    #[doc = "Bit 7 - Pending Data is first Byte following Address"]
+    #[inline(always)]
+    pub fn rxdatafirst(&self) -> RxdatafirstR {
+        RxdatafirstR::new(((self.bits >> 7) & 1) != 0)
+    }
+    #[doc = "Bit 8 - RX FIFO is Not Empty"]
+    #[inline(always)]
+    pub fn rxnempty(&self) -> RxnemptyR {
+        RxnemptyR::new(((self.bits >> 8) & 1) != 0)
+    }
+    #[doc = "Bit 9 - RX FIFO is Full"]
+    #[inline(always)]
+    pub fn rxfull(&self) -> RxfullR {
+        RxfullR::new(((self.bits >> 9) & 1) != 0)
+    }
+    #[doc = "Bit 11 - RX FIFO Above Trigger Level"]
+    #[inline(always)]
+    pub fn rxtrigger(&self) -> RxtriggerR {
+        RxtriggerR::new(((self.bits >> 11) & 1) != 0)
+    }
+    #[doc = "Bit 12 - TX FIFO is Empty"]
+    #[inline(always)]
+    pub fn txempty(&self) -> TxemptyR {
+        TxemptyR::new(((self.bits >> 12) & 1) != 0)
+    }
+    #[doc = "Bit 13 - TX FIFO is Full"]
+    #[inline(always)]
+    pub fn txnfull(&self) -> TxnfullR {
+        TxnfullR::new(((self.bits >> 13) & 1) != 0)
+    }
+    #[doc = "Bit 15 - TX FIFO Below Trigger Level"]
+    #[inline(always)]
+    pub fn txtrigger(&self) -> TxtriggerR {
+        TxtriggerR::new(((self.bits >> 15) & 1) != 0)
+    }
+    #[doc = "Bit 29 - I2C Raw Busy value"]
+    #[inline(always)]
+    pub fn raw_busy(&self) -> RawBusyR {
+        RawBusyR::new(((self.bits >> 29) & 1) != 0)
+    }
+    #[doc = "Bit 30 - I2C Raw SDA value"]
+    #[inline(always)]
+    pub fn raw_sda(&self) -> RawSdaR {
+        RawSdaR::new(((self.bits >> 30) & 1) != 0)
+    }
+    #[doc = "Bit 31 - I2C Raw SCL value"]
+    #[inline(always)]
+    pub fn raw_scl(&self) -> RawSclR {
+        RawSclR::new(((self.bits >> 31) & 1) != 0)
+    }
+}
+#[doc = "Slave I2C Controller Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct S0StatusSpec;
+impl crate::RegisterSpec for S0StatusSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`s0_status::R`](R) reader structure"]
+impl crate::Readable for S0StatusSpec {}
+#[doc = "`reset()` method sets S0_STATUS to value 0"]
+impl crate::Resettable for S0StatusSpec {
+    const RESET_VALUE: u32 = 0;
+}

va108xx/src/i2ca/s0_txcount.rs

@@ -0,0 +1,18 @@
+#[doc = "Register `S0_TXCOUNT` reader"]
+pub type R = crate::R<S0TxcountSpec>;
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        write!(f, "{}", self.bits())
+    }
+}
+#[doc = "Slave TX Count Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_txcount::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct S0TxcountSpec;
+impl crate::RegisterSpec for S0TxcountSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`s0_txcount::R`](R) reader structure"]
+impl crate::Readable for S0TxcountSpec {}
+#[doc = "`reset()` method sets S0_TXCOUNT to value 0"]
+impl crate::Resettable for S0TxcountSpec {
+    const RESET_VALUE: u32 = 0;
+}

va108xx/src/i2ca/s0_txfifoirqtrg.rs

@@ -0,0 +1,27 @@
+#[doc = "Register `S0_TXFIFOIRQTRG` reader"]
+pub type R = crate::R<S0TxfifoirqtrgSpec>;
+#[doc = "Register `S0_TXFIFOIRQTRG` writer"]
+pub type W = crate::W<S0TxfifoirqtrgSpec>;
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        write!(f, "{}", self.bits())
+    }
+}
+impl W {}
+#[doc = "Slave Tx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_txfifoirqtrg::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_txfifoirqtrg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct S0TxfifoirqtrgSpec;
+impl crate::RegisterSpec for S0TxfifoirqtrgSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`s0_txfifoirqtrg::R`](R) reader structure"]
+impl crate::Readable for S0TxfifoirqtrgSpec {}
+#[doc = "`write(|w| ..)` method takes [`s0_txfifoirqtrg::W`](W) writer structure"]
+impl crate::Writable for S0TxfifoirqtrgSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets S0_TXFIFOIRQTRG to value 0"]
+impl crate::Resettable for S0TxfifoirqtrgSpec {
+    const RESET_VALUE: u32 = 0;
+}

va108xx/src/i2ca/state.rs

@@ -0,0 +1,18 @@
+#[doc = "Register `STATE` reader"]
+pub type R = crate::R<StateSpec>;
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        write!(f, "{}", self.bits())
+    }
+}
+#[doc = "Internal STATE of I2C Master Controller\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`state::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct StateSpec;
+impl crate::RegisterSpec for StateSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`state::R`](R) reader structure"]
+impl crate::Readable for StateSpec {}
+#[doc = "`reset()` method sets STATE to value 0"]
+impl crate::Resettable for StateSpec {
+    const RESET_VALUE: u32 = 0;
+}

va108xx/src/i2ca/status.rs

@@ -0,0 +1,120 @@
+#[doc = "Register `STATUS` reader"]
+pub type R = crate::R<StatusSpec>;
+#[doc = "Field `I2C_IDLE` reader - I2C bus is Idle"]
+pub type I2cIdleR = crate::BitReader;
+#[doc = "Field `IDLE` reader - Controller is Idle"]
+pub type IdleR = crate::BitReader;
+#[doc = "Field `WAITING` reader - Controller is Waiting"]
+pub type WaitingR = crate::BitReader;
+#[doc = "Field `STALLED` reader - Controller is Stalled"]
+pub type StalledR = crate::BitReader;
+#[doc = "Field `ARBLOST` reader - I2C Arbitration was lost"]
+pub type ArblostR = crate::BitReader;
+#[doc = "Field `NACKADDR` reader - I2C Address was not Acknowledged"]
+pub type NackaddrR = crate::BitReader;
+#[doc = "Field `NACKDATA` reader - I2C Data was not Acknowledged"]
+pub type NackdataR = crate::BitReader;
+#[doc = "Field `RXNEMPTY` reader - RX FIFO is Not Empty"]
+pub type RxnemptyR = crate::BitReader;
+#[doc = "Field `RXFULL` reader - RX FIFO is Full"]
+pub type RxfullR = crate::BitReader;
+#[doc = "Field `RXTRIGGER` reader - RX FIFO Above Trigger Level"]
+pub type RxtriggerR = crate::BitReader;
+#[doc = "Field `TXEMPTY` reader - TX FIFO is Empty"]
+pub type TxemptyR = crate::BitReader;
+#[doc = "Field `TXNFULL` reader - TX FIFO is Full"]
+pub type TxnfullR = crate::BitReader;
+#[doc = "Field `TXTRIGGER` reader - TX FIFO Below Trigger Level"]
+pub type TxtriggerR = crate::BitReader;
+#[doc = "Field `RAW_SDA` reader - I2C Raw SDA value"]
+pub type RawSdaR = crate::BitReader;
+#[doc = "Field `RAW_SCL` reader - I2C Raw SCL value"]
+pub type RawSclR = crate::BitReader;
+impl R {
+    #[doc = "Bit 0 - I2C bus is Idle"]
+    #[inline(always)]
+    pub fn i2c_idle(&self) -> I2cIdleR {
+        I2cIdleR::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - Controller is Idle"]
+    #[inline(always)]
+    pub fn idle(&self) -> IdleR {
+        IdleR::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - Controller is Waiting"]
+    #[inline(always)]
+    pub fn waiting(&self) -> WaitingR {
+        WaitingR::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - Controller is Stalled"]
+    #[inline(always)]
+    pub fn stalled(&self) -> StalledR {
+        StalledR::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - I2C Arbitration was lost"]
+    #[inline(always)]
+    pub fn arblost(&self) -> ArblostR {
+        ArblostR::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 5 - I2C Address was not Acknowledged"]
+    #[inline(always)]
+    pub fn nackaddr(&self) -> NackaddrR {
+        NackaddrR::new(((self.bits >> 5) & 1) != 0)
+    }
+    #[doc = "Bit 6 - I2C Data was not Acknowledged"]
+    #[inline(always)]
+    pub fn nackdata(&self) -> NackdataR {
+        NackdataR::new(((self.bits >> 6) & 1) != 0)
+    }
+    #[doc = "Bit 8 - RX FIFO is Not Empty"]
+    #[inline(always)]
+    pub fn rxnempty(&self) -> RxnemptyR {
+        RxnemptyR::new(((self.bits >> 8) & 1) != 0)
+    }
+    #[doc = "Bit 9 - RX FIFO is Full"]
+    #[inline(always)]
+    pub fn rxfull(&self) -> RxfullR {
+        RxfullR::new(((self.bits >> 9) & 1) != 0)
+    }
+    #[doc = "Bit 11 - RX FIFO Above Trigger Level"]
+    #[inline(always)]
+    pub fn rxtrigger(&self) -> RxtriggerR {
+        RxtriggerR::new(((self.bits >> 11) & 1) != 0)
+    }
+    #[doc = "Bit 12 - TX FIFO is Empty"]
+    #[inline(always)]
+    pub fn txempty(&self) -> TxemptyR {
+        TxemptyR::new(((self.bits >> 12) & 1) != 0)
+    }
+    #[doc = "Bit 13 - TX FIFO is Full"]
+    #[inline(always)]
+    pub fn txnfull(&self) -> TxnfullR {
+        TxnfullR::new(((self.bits >> 13) & 1) != 0)
+    }
+    #[doc = "Bit 15 - TX FIFO Below Trigger Level"]
+    #[inline(always)]
+    pub fn txtrigger(&self) -> TxtriggerR {
+        TxtriggerR::new(((self.bits >> 15) & 1) != 0)
+    }
+    #[doc = "Bit 30 - I2C Raw SDA value"]
+    #[inline(always)]
+    pub fn raw_sda(&self) -> RawSdaR {
+        RawSdaR::new(((self.bits >> 30) & 1) != 0)
+    }
+    #[doc = "Bit 31 - I2C Raw SCL value"]
+    #[inline(always)]
+    pub fn raw_scl(&self) -> RawSclR {
+        RawSclR::new(((self.bits >> 31) & 1) != 0)
+    }
+}
+#[doc = "I2C Controller Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct StatusSpec;
+impl crate::RegisterSpec for StatusSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`status::R`](R) reader structure"]
+impl crate::Readable for StatusSpec {}
+#[doc = "`reset()` method sets STATUS to value 0"]
+impl crate::Resettable for StatusSpec {
+    const RESET_VALUE: u32 = 0;
+}

va108xx/src/i2ca/tmconfig.rs

@@ -0,0 +1,27 @@
+#[doc = "Register `TMCONFIG` reader"]
+pub type R = crate::R<TmconfigSpec>;
+#[doc = "Register `TMCONFIG` writer"]
+pub type W = crate::W<TmconfigSpec>;
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        write!(f, "{}", self.bits())
+    }
+}
+impl W {}
+#[doc = "Timing Config Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tmconfig::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tmconfig::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct TmconfigSpec;
+impl crate::RegisterSpec for TmconfigSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`tmconfig::R`](R) reader structure"]
+impl crate::Readable for TmconfigSpec {}
+#[doc = "`write(|w| ..)` method takes [`tmconfig::W`](W) writer structure"]
+impl crate::Writable for TmconfigSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets TMCONFIG to value 0"]
+impl crate::Resettable for TmconfigSpec {
+    const RESET_VALUE: u32 = 0;
+}

va108xx/src/i2ca/txcount.rs

@@ -0,0 +1,18 @@
+#[doc = "Register `TXCOUNT` reader"]
+pub type R = crate::R<TxcountSpec>;
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        write!(f, "{}", self.bits())
+    }
+}
+#[doc = "TX Count Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txcount::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct TxcountSpec;
+impl crate::RegisterSpec for TxcountSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`txcount::R`](R) reader structure"]
+impl crate::Readable for TxcountSpec {}
+#[doc = "`reset()` method sets TXCOUNT to value 0"]
+impl crate::Resettable for TxcountSpec {
+    const RESET_VALUE: u32 = 0;
+}

va108xx/src/i2ca/txfifoirqtrg.rs

@@ -0,0 +1,27 @@
+#[doc = "Register `TXFIFOIRQTRG` reader"]
+pub type R = crate::R<TxfifoirqtrgSpec>;
+#[doc = "Register `TXFIFOIRQTRG` writer"]
+pub type W = crate::W<TxfifoirqtrgSpec>;
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        write!(f, "{}", self.bits())
+    }
+}
+impl W {}
+#[doc = "Tx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txfifoirqtrg::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txfifoirqtrg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct TxfifoirqtrgSpec;
+impl crate::RegisterSpec for TxfifoirqtrgSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`txfifoirqtrg::R`](R) reader structure"]
+impl crate::Readable for TxfifoirqtrgSpec {}
+#[doc = "`write(|w| ..)` method takes [`txfifoirqtrg::W`](W) writer structure"]
+impl crate::Writable for TxfifoirqtrgSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets TXFIFOIRQTRG to value 0"]
+impl crate::Resettable for TxfifoirqtrgSpec {
+    const RESET_VALUE: u32 = 0;
+}

va108xx/src/i2ca/words.rs

@@ -0,0 +1,27 @@
+#[doc = "Register `WORDS` reader"]
+pub type R = crate::R<WordsSpec>;
+#[doc = "Register `WORDS` writer"]
+pub type W = crate::W<WordsSpec>;
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        write!(f, "{}", self.bits())
+    }
+}
+impl W {}
+#[doc = "Word Count value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`words::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`words::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct WordsSpec;
+impl crate::RegisterSpec for WordsSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`words::R`](R) reader structure"]
+impl crate::Readable for WordsSpec {}
+#[doc = "`write(|w| ..)` method takes [`words::W`](W) writer structure"]
+impl crate::Writable for WordsSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets WORDS to value 0"]
+impl crate::Resettable for WordsSpec {
+    const RESET_VALUE: u32 = 0;
+}

va108xx/src/ioconfig.rs

@@ -0,0 +1,51 @@
+#[repr(C)]
+#[doc = "Register block"]
+pub struct RegisterBlock {
+    porta: [Porta; 32],
+    portb0: [Portb; 32],
+    _reserved2: [u8; 0x0efc],
+    perid: Perid,
+}
+impl RegisterBlock {
+    #[doc = "0x00..0x80 - PORTA Pin Configuration Register"]
+    #[inline(always)]
+    pub const fn porta(&self, n: usize) -> &Porta {
+        &self.porta[n]
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "0x00..0x80 - PORTA Pin Configuration Register"]
+    #[inline(always)]
+    pub fn porta_iter(&self) -> impl Iterator<Item = &Porta> {
+        self.porta.iter()
+    }
+    #[doc = "0x80..0x100 - PORTB Pin Configuration Register"]
+    #[inline(always)]
+    pub const fn portb0(&self, n: usize) -> &Portb {
+        &self.portb0[n]
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "0x80..0x100 - PORTB Pin Configuration Register"]
+    #[inline(always)]
+    pub fn portb0_iter(&self) -> impl Iterator<Item = &Portb> {
+        self.portb0.iter()
+    }
+    #[doc = "0xffc - Peripheral ID Register"]
+    #[inline(always)]
+    pub const fn perid(&self) -> &Perid {
+        &self.perid
+    }
+}
+#[doc = "PORTA (rw) register accessor: PORTA Pin Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`porta::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`porta::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@porta`]
+module"]
+#[doc(alias = "PORTA")]
+pub type Porta = crate::Reg<porta::PortaSpec>;
+#[doc = "PORTA Pin Configuration Register"]
+pub mod porta;
+pub use porta as portb;
+pub use Porta as Portb;
+#[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`perid::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`]
+module"]
+#[doc(alias = "PERID")]
+pub type Perid = crate::Reg<perid::PeridSpec>;
+#[doc = "Peripheral ID Register"]
+pub mod perid;

va108xx/src/ioconfig/perid.rs

@@ -0,0 +1,18 @@
+#[doc = "Register `PERID` reader"]
+pub type R = crate::R<PeridSpec>;
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        write!(f, "{}", self.bits())
+    }
+}
+#[doc = "Peripheral ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`perid::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct PeridSpec;
+impl crate::RegisterSpec for PeridSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`perid::R`](R) reader structure"]
+impl crate::Readable for PeridSpec {}
+#[doc = "`reset()` method sets PERID to value 0x0082_07e1"]
+impl crate::Resettable for PeridSpec {
+    const RESET_VALUE: u32 = 0x0082_07e1;
+}

va108xx/src/ioconfig/porta.rs

@@ -0,0 +1,299 @@
+#[doc = "Register `PORTA[%s]` reader"]
+pub type R = crate::R<PortaSpec>;
+#[doc = "Register `PORTA[%s]` writer"]
+pub type W = crate::W<PortaSpec>;
+#[doc = "Input Filter Selectoin\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+#[repr(u8)]
+pub enum Flttype {
+    #[doc = "0: Synchronize to system clock"]
+    Sync = 0,
+    #[doc = "1: Direct input, no synchronization"]
+    Direct = 1,
+    #[doc = "2: Require 2 samples to have the same value"]
+    Filter1 = 2,
+    #[doc = "3: Require 3 samples to have the same value"]
+    Filter2 = 3,
+    #[doc = "4: Require 4 samples to have the same value"]
+    Filter3 = 4,
+    #[doc = "5: Require 5 samples to have the same value"]
+    Filter4 = 5,
+}
+impl From<Flttype> for u8 {
+    #[inline(always)]
+    fn from(variant: Flttype) -> Self {
+        variant as _
+    }
+}
+impl crate::FieldSpec for Flttype {
+    type Ux = u8;
+}
+impl crate::IsEnum for Flttype {}
+#[doc = "Field `FLTTYPE` reader - Input Filter Selectoin"]
+pub type FlttypeR = crate::FieldReader<Flttype>;
+impl FlttypeR {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub const fn variant(&self) -> Option<Flttype> {
+        match self.bits {
+            0 => Some(Flttype::Sync),
+            1 => Some(Flttype::Direct),
+            2 => Some(Flttype::Filter1),
+            3 => Some(Flttype::Filter2),
+            4 => Some(Flttype::Filter3),
+            5 => Some(Flttype::Filter4),
+            _ => None,
+        }
+    }
+    #[doc = "Synchronize to system clock"]
+    #[inline(always)]
+    pub fn is_sync(&self) -> bool {
+        *self == Flttype::Sync
+    }
+    #[doc = "Direct input, no synchronization"]
+    #[inline(always)]
+    pub fn is_direct(&self) -> bool {
+        *self == Flttype::Direct
+    }
+    #[doc = "Require 2 samples to have the same value"]
+    #[inline(always)]
+    pub fn is_filter1(&self) -> bool {
+        *self == Flttype::Filter1
+    }
+    #[doc = "Require 3 samples to have the same value"]
+    #[inline(always)]
+    pub fn is_filter2(&self) -> bool {
+        *self == Flttype::Filter2
+    }
+    #[doc = "Require 4 samples to have the same value"]
+    #[inline(always)]
+    pub fn is_filter3(&self) -> bool {
+        *self == Flttype::Filter3
+    }
+    #[doc = "Require 5 samples to have the same value"]
+    #[inline(always)]
+    pub fn is_filter4(&self) -> bool {
+        *self == Flttype::Filter4
+    }
+}
+#[doc = "Field `FLTTYPE` writer - Input Filter Selectoin"]
+pub type FlttypeW<'a, REG> = crate::FieldWriter<'a, REG, 3, Flttype>;
+impl<'a, REG> FlttypeW<'a, REG>
+where
+    REG: crate::Writable + crate::RegisterSpec,
+    REG::Ux: From<u8>,
+{
+    #[doc = "Synchronize to system clock"]
+    #[inline(always)]
+    pub fn sync(self) -> &'a mut crate::W<REG> {
+        self.variant(Flttype::Sync)
+    }
+    #[doc = "Direct input, no synchronization"]
+    #[inline(always)]
+    pub fn direct(self) -> &'a mut crate::W<REG> {
+        self.variant(Flttype::Direct)
+    }
+    #[doc = "Require 2 samples to have the same value"]
+    #[inline(always)]
+    pub fn filter1(self) -> &'a mut crate::W<REG> {
+        self.variant(Flttype::Filter1)
+    }
+    #[doc = "Require 3 samples to have the same value"]
+    #[inline(always)]
+    pub fn filter2(self) -> &'a mut crate::W<REG> {
+        self.variant(Flttype::Filter2)
+    }
+    #[doc = "Require 4 samples to have the same value"]
+    #[inline(always)]
+    pub fn filter3(self) -> &'a mut crate::W<REG> {
+        self.variant(Flttype::Filter3)
+    }
+    #[doc = "Require 5 samples to have the same value"]
+    #[inline(always)]
+    pub fn filter4(self) -> &'a mut crate::W<REG> {
+        self.variant(Flttype::Filter4)
+    }
+}
+#[doc = "Field `FLTCLK` reader - Input Filter Clock Selection"]
+pub type FltclkR = crate::FieldReader;
+#[doc = "Field `FLTCLK` writer - Input Filter Clock Selection"]
+pub type FltclkW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
+#[doc = "Field `INVINP` reader - Input Invert Selection"]
+pub type InvinpR = crate::BitReader;
+#[doc = "Field `INVINP` writer - Input Invert Selection"]
+pub type InvinpW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `IEWO` reader - Input Enable While Output enabled"]
+pub type IewoR = crate::BitReader;
+#[doc = "Field `IEWO` writer - Input Enable While Output enabled"]
+pub type IewoW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `OPENDRN` reader - Output Open Drain Mode"]
+pub type OpendrnR = crate::BitReader;
+#[doc = "Field `OPENDRN` writer - Output Open Drain Mode"]
+pub type OpendrnW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `INVOUT` reader - Output Invert Selection"]
+pub type InvoutR = crate::BitReader;
+#[doc = "Field `INVOUT` writer - Output Invert Selection"]
+pub type InvoutW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `PLEVEL` reader - Internal Pull up/down level"]
+pub type PlevelR = crate::BitReader;
+#[doc = "Field `PLEVEL` writer - Internal Pull up/down level"]
+pub type PlevelW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `PEN` reader - Enable Internal Pull up/down"]
+pub type PenR = crate::BitReader;
+#[doc = "Field `PEN` writer - Enable Internal Pull up/down"]
+pub type PenW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `PWOA` reader - Enable Pull when output active"]
+pub type PwoaR = crate::BitReader;
+#[doc = "Field `PWOA` writer - Enable Pull when output active"]
+pub type PwoaW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `FUNSEL` reader - Pin Function Selection"]
+pub type FunselR = crate::FieldReader;
+#[doc = "Field `FUNSEL` writer - Pin Function Selection"]
+pub type FunselW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
+#[doc = "Field `IODIS` reader - IO Pin Disable"]
+pub type IodisR = crate::BitReader;
+#[doc = "Field `IODIS` writer - IO Pin Disable"]
+pub type IodisW<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bits 0:2 - Input Filter Selectoin"]
+    #[inline(always)]
+    pub fn flttype(&self) -> FlttypeR {
+        FlttypeR::new((self.bits & 7) as u8)
+    }
+    #[doc = "Bits 3:5 - Input Filter Clock Selection"]
+    #[inline(always)]
+    pub fn fltclk(&self) -> FltclkR {
+        FltclkR::new(((self.bits >> 3) & 7) as u8)
+    }
+    #[doc = "Bit 6 - Input Invert Selection"]
+    #[inline(always)]
+    pub fn invinp(&self) -> InvinpR {
+        InvinpR::new(((self.bits >> 6) & 1) != 0)
+    }
+    #[doc = "Bit 7 - Input Enable While Output enabled"]
+    #[inline(always)]
+    pub fn iewo(&self) -> IewoR {
+        IewoR::new(((self.bits >> 7) & 1) != 0)
+    }
+    #[doc = "Bit 8 - Output Open Drain Mode"]
+    #[inline(always)]
+    pub fn opendrn(&self) -> OpendrnR {
+        OpendrnR::new(((self.bits >> 8) & 1) != 0)
+    }
+    #[doc = "Bit 9 - Output Invert Selection"]
+    #[inline(always)]
+    pub fn invout(&self) -> InvoutR {
+        InvoutR::new(((self.bits >> 9) & 1) != 0)
+    }
+    #[doc = "Bit 10 - Internal Pull up/down level"]
+    #[inline(always)]
+    pub fn plevel(&self) -> PlevelR {
+        PlevelR::new(((self.bits >> 10) & 1) != 0)
+    }
+    #[doc = "Bit 11 - Enable Internal Pull up/down"]
+    #[inline(always)]
+    pub fn pen(&self) -> PenR {
+        PenR::new(((self.bits >> 11) & 1) != 0)
+    }
+    #[doc = "Bit 12 - Enable Pull when output active"]
+    #[inline(always)]
+    pub fn pwoa(&self) -> PwoaR {
+        PwoaR::new(((self.bits >> 12) & 1) != 0)
+    }
+    #[doc = "Bits 13:15 - Pin Function Selection"]
+    #[inline(always)]
+    pub fn funsel(&self) -> FunselR {
+        FunselR::new(((self.bits >> 13) & 7) as u8)
+    }
+    #[doc = "Bit 16 - IO Pin Disable"]
+    #[inline(always)]
+    pub fn iodis(&self) -> IodisR {
+        IodisR::new(((self.bits >> 16) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bits 0:2 - Input Filter Selectoin"]
+    #[inline(always)]
+    #[must_use]
+    pub fn flttype(&mut self) -> FlttypeW<PortaSpec> {
+        FlttypeW::new(self, 0)
+    }
+    #[doc = "Bits 3:5 - Input Filter Clock Selection"]
+    #[inline(always)]
+    #[must_use]
+    pub fn fltclk(&mut self) -> FltclkW<PortaSpec> {
+        FltclkW::new(self, 3)
+    }
+    #[doc = "Bit 6 - Input Invert Selection"]
+    #[inline(always)]
+    #[must_use]
+    pub fn invinp(&mut self) -> InvinpW<PortaSpec> {
+        InvinpW::new(self, 6)
+    }
+    #[doc = "Bit 7 - Input Enable While Output enabled"]
+    #[inline(always)]
+    #[must_use]
+    pub fn iewo(&mut self) -> IewoW<PortaSpec> {
+        IewoW::new(self, 7)
+    }
+    #[doc = "Bit 8 - Output Open Drain Mode"]
+    #[inline(always)]
+    #[must_use]
+    pub fn opendrn(&mut self) -> OpendrnW<PortaSpec> {
+        OpendrnW::new(self, 8)
+    }
+    #[doc = "Bit 9 - Output Invert Selection"]
+    #[inline(always)]
+    #[must_use]
+    pub fn invout(&mut self) -> InvoutW<PortaSpec> {
+        InvoutW::new(self, 9)
+    }
+    #[doc = "Bit 10 - Internal Pull up/down level"]
+    #[inline(always)]
+    #[must_use]
+    pub fn plevel(&mut self) -> PlevelW<PortaSpec> {
+        PlevelW::new(self, 10)
+    }
+    #[doc = "Bit 11 - Enable Internal Pull up/down"]
+    #[inline(always)]
+    #[must_use]
+    pub fn pen(&mut self) -> PenW<PortaSpec> {
+        PenW::new(self, 11)
+    }
+    #[doc = "Bit 12 - Enable Pull when output active"]
+    #[inline(always)]
+    #[must_use]
+    pub fn pwoa(&mut self) -> PwoaW<PortaSpec> {
+        PwoaW::new(self, 12)
+    }
+    #[doc = "Bits 13:15 - Pin Function Selection"]
+    #[inline(always)]
+    #[must_use]
+    pub fn funsel(&mut self) -> FunselW<PortaSpec> {
+        FunselW::new(self, 13)
+    }
+    #[doc = "Bit 16 - IO Pin Disable"]
+    #[inline(always)]
+    #[must_use]
+    pub fn iodis(&mut self) -> IodisW<PortaSpec> {
+        IodisW::new(self, 16)
+    }
+}
+#[doc = "PORTA Pin Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`porta::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`porta::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct PortaSpec;
+impl crate::RegisterSpec for PortaSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`porta::R`](R) reader structure"]
+impl crate::Readable for PortaSpec {}
+#[doc = "`write(|w| ..)` method takes [`porta::W`](W) writer structure"]
+impl crate::Writable for PortaSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets PORTA[%s]
+to value 0"]
+impl crate::Resettable for PortaSpec {
+    const RESET_VALUE: u32 = 0;
+}

va108xx/src/irqsel.rs

@@ -0,0 +1,221 @@
+#[repr(C)]
+#[doc = "Register block"]
+pub struct RegisterBlock {
+    porta0: [Porta; 32],
+    portb0: [Portb; 32],
+    tim0: [Tim; 32],
+    uart0: [Uart; 4],
+    spi0: [Spi; 4],
+    i2c_ms0: [I2cMs; 4],
+    i2c_sl0: [I2cSl; 4],
+    int_ram_sbe: IntRamSbe,
+    int_ram_mbe: IntRamMbe,
+    int_rom_sbe: IntRomSbe,
+    int_rom_mbe: IntRomMbe,
+    txev: Txev,
+    _reserved12: [u8; 0x062c],
+    irqs0: [Irqs; 32],
+    _reserved13: [u8; 0x68],
+    edbgrq: Edbgrq,
+    mereset: Mereset,
+    watchdog: Watchdog,
+    rxev: Rxev,
+    nmi: Nmi,
+    _reserved18: [u8; 0x0700],
+    perid: Perid,
+}
+impl RegisterBlock {
+    #[doc = "0x00..0x80 - PORTA Interrupt Redirect Selection"]
+    #[inline(always)]
+    pub const fn porta0(&self, n: usize) -> &Porta {
+        &self.porta0[n]
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "0x00..0x80 - PORTA Interrupt Redirect Selection"]
+    #[inline(always)]
+    pub fn porta0_iter(&self) -> impl Iterator<Item = &Porta> {
+        self.porta0.iter()
+    }
+    #[doc = "0x80..0x100 - PORTB Interrupt Redirect Selection"]
+    #[inline(always)]
+    pub const fn portb0(&self, n: usize) -> &Portb {
+        &self.portb0[n]
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "0x80..0x100 - PORTB Interrupt Redirect Selection"]
+    #[inline(always)]
+    pub fn portb0_iter(&self) -> impl Iterator<Item = &Portb> {
+        self.portb0.iter()
+    }
+    #[doc = "0x100..0x180 - TIM Interrupt Redirect Selection"]
+    #[inline(always)]
+    pub const fn tim0(&self, n: usize) -> &Tim {
+        &self.tim0[n]
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "0x100..0x180 - TIM Interrupt Redirect Selection"]
+    #[inline(always)]
+    pub fn tim0_iter(&self) -> impl Iterator<Item = &Tim> {
+        self.tim0.iter()
+    }
+    #[doc = "0x180..0x190 - UART Interrupt Redirect Selection"]
+    #[inline(always)]
+    pub const fn uart0(&self, n: usize) -> &Uart {
+        &self.uart0[n]
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "0x180..0x190 - UART Interrupt Redirect Selection"]
+    #[inline(always)]
+    pub fn uart0_iter(&self) -> impl Iterator<Item = &Uart> {
+        self.uart0.iter()
+    }
+    #[doc = "0x190..0x1a0 - SPI Interrupt Redirect Selection"]
+    #[inline(always)]
+    pub const fn spi0(&self, n: usize) -> &Spi {
+        &self.spi0[n]
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "0x190..0x1a0 - SPI Interrupt Redirect Selection"]
+    #[inline(always)]
+    pub fn spi0_iter(&self) -> impl Iterator<Item = &Spi> {
+        self.spi0.iter()
+    }
+    #[doc = "0x1a0..0x1b0 - Master I2C Interrupt Redirect Selection"]
+    #[inline(always)]
+    pub const fn i2c_ms0(&self, n: usize) -> &I2cMs {
+        &self.i2c_ms0[n]
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "0x1a0..0x1b0 - Master I2C Interrupt Redirect Selection"]
+    #[inline(always)]
+    pub fn i2c_ms0_iter(&self) -> impl Iterator<Item = &I2cMs> {
+        self.i2c_ms0.iter()
+    }
+    #[doc = "0x1b0..0x1c0 - Slave I2C Interrupt Redirect Selection"]
+    #[inline(always)]
+    pub const fn i2c_sl0(&self, n: usize) -> &I2cSl {
+        &self.i2c_sl0[n]
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "0x1b0..0x1c0 - Slave I2C Interrupt Redirect Selection"]
+    #[inline(always)]
+    pub fn i2c_sl0_iter(&self) -> impl Iterator<Item = &I2cSl> {
+        self.i2c_sl0.iter()
+    }
+    #[doc = "0x1c0 - Internal Memory RAM SBE Interrupt Redirect Selection"]
+    #[inline(always)]
+    pub const fn int_ram_sbe(&self) -> &IntRamSbe {
+        &self.int_ram_sbe
+    }
+    #[doc = "0x1c4 - Internal Memory RAM MBE Interrupt Redirect Selection"]
+    #[inline(always)]
+    pub const fn int_ram_mbe(&self) -> &IntRamMbe {
+        &self.int_ram_mbe
+    }
+    #[doc = "0x1c8 - Internal Memory ROM SBE Interrupt Redirect Selection"]
+    #[inline(always)]
+    pub const fn int_rom_sbe(&self) -> &IntRomSbe {
+        &self.int_rom_sbe
+    }
+    #[doc = "0x1cc - Internal Memory ROM MBE Interrupt Redirect Selection"]
+    #[inline(always)]
+    pub const fn int_rom_mbe(&self) -> &IntRomMbe {
+        &self.int_rom_mbe
+    }
+    #[doc = "0x1d0 - Processor TXEV Interrupt Redirect Selection"]
+    #[inline(always)]
+    pub const fn txev(&self) -> &Txev {
+        &self.txev
+    }
+    #[doc = "0x800..0x880 - Interrupt Status Register"]
+    #[inline(always)]
+    pub const fn irqs0(&self, n: usize) -> &Irqs {
+        &self.irqs0[n]
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "0x800..0x880 - Interrupt Status Register"]
+    #[inline(always)]
+    pub fn irqs0_iter(&self) -> impl Iterator<Item = &Irqs> {
+        self.irqs0.iter()
+    }
+    #[doc = "0x8e8 - EDBGRQ Status Register"]
+    #[inline(always)]
+    pub const fn edbgrq(&self) -> &Edbgrq {
+        &self.edbgrq
+    }
+    #[doc = "0x8ec - MERESET Status Register"]
+    #[inline(always)]
+    pub const fn mereset(&self) -> &Mereset {
+        &self.mereset
+    }
+    #[doc = "0x8f0 - WATCHDOG Status Register"]
+    #[inline(always)]
+    pub const fn watchdog(&self) -> &Watchdog {
+        &self.watchdog
+    }
+    #[doc = "0x8f4 - RXEV Status Register"]
+    #[inline(always)]
+    pub const fn rxev(&self) -> &Rxev {
+        &self.rxev
+    }
+    #[doc = "0x8f8 - NMI Status Register"]
+    #[inline(always)]
+    pub const fn nmi(&self) -> &Nmi {
+        &self.nmi
+    }
+    #[doc = "0xffc - Peripheral ID Register"]
+    #[inline(always)]
+    pub const fn perid(&self) -> &Perid {
+        &self.perid
+    }
+}
+#[doc = "INT_RAM_SBE (rw) register accessor: Internal Memory RAM SBE Interrupt Redirect Selection\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_ram_sbe::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_ram_sbe::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_ram_sbe`]
+module"]
+#[doc(alias = "INT_RAM_SBE")]
+pub type IntRamSbe = crate::Reg<int_ram_sbe::IntRamSbeSpec>;
+#[doc = "Internal Memory RAM SBE Interrupt Redirect Selection"]
+pub mod int_ram_sbe;
+pub use int_ram_sbe as porta;
+pub use int_ram_sbe as portb;
+pub use int_ram_sbe as tim;
+pub use int_ram_sbe as uart;
+pub use int_ram_sbe as spi;
+pub use int_ram_sbe as i2c_ms;
+pub use int_ram_sbe as i2c_sl;
+pub use int_ram_sbe as int_ram_mbe;
+pub use int_ram_sbe as int_rom_sbe;
+pub use int_ram_sbe as int_rom_mbe;
+pub use int_ram_sbe as txev;
+pub use IntRamSbe as Porta;
+pub use IntRamSbe as Portb;
+pub use IntRamSbe as Tim;
+pub use IntRamSbe as Uart;
+pub use IntRamSbe as Spi;
+pub use IntRamSbe as I2cMs;
+pub use IntRamSbe as I2cSl;
+pub use IntRamSbe as IntRamMbe;
+pub use IntRamSbe as IntRomSbe;
+pub use IntRamSbe as IntRomMbe;
+pub use IntRamSbe as Txev;
+#[doc = "NMI (r) register accessor: NMI Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`nmi::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@nmi`]
+module"]
+#[doc(alias = "NMI")]
+pub type Nmi = crate::Reg<nmi::NmiSpec>;
+#[doc = "NMI Status Register"]
+pub mod nmi;
+pub use nmi as rxev;
+pub use nmi as watchdog;
+pub use nmi as mereset;
+pub use nmi as edbgrq;
+pub use nmi as irqs;
+pub use Nmi as Rxev;
+pub use Nmi as Watchdog;
+pub use Nmi as Mereset;
+pub use Nmi as Edbgrq;
+pub use Nmi as Irqs;
+#[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`perid::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`]
+module"]
+#[doc(alias = "PERID")]
+pub type Perid = crate::Reg<perid::PeridSpec>;
+#[doc = "Peripheral ID Register"]
+pub mod perid;

va108xx/src/irqsel/int_ram_sbe.rs

@@ -0,0 +1,27 @@
+#[doc = "Register `INT_RAM_SBE` reader"]
+pub type R = crate::R<IntRamSbeSpec>;
+#[doc = "Register `INT_RAM_SBE` writer"]
+pub type W = crate::W<IntRamSbeSpec>;
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        write!(f, "{}", self.bits())
+    }
+}
+impl W {}
+#[doc = "Internal Memory RAM SBE Interrupt Redirect Selection\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_ram_sbe::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_ram_sbe::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct IntRamSbeSpec;
+impl crate::RegisterSpec for IntRamSbeSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`int_ram_sbe::R`](R) reader structure"]
+impl crate::Readable for IntRamSbeSpec {}
+#[doc = "`write(|w| ..)` method takes [`int_ram_sbe::W`](W) writer structure"]
+impl crate::Writable for IntRamSbeSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets INT_RAM_SBE to value 0xffff_ffff"]
+impl crate::Resettable for IntRamSbeSpec {
+    const RESET_VALUE: u32 = 0xffff_ffff;
+}

va108xx/src/irqsel/nmi.rs

@@ -0,0 +1,22 @@
+#[doc = "Register `NMI` reader"]
+pub type R = crate::R<NmiSpec>;
+#[doc = "Field `ACTIVE` reader - Active"]
+pub type ActiveR = crate::BitReader;
+impl R {
+    #[doc = "Bit 0 - Active"]
+    #[inline(always)]
+    pub fn active(&self) -> ActiveR {
+        ActiveR::new((self.bits & 1) != 0)
+    }
+}
+#[doc = "NMI Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`nmi::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct NmiSpec;
+impl crate::RegisterSpec for NmiSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`nmi::R`](R) reader structure"]
+impl crate::Readable for NmiSpec {}
+#[doc = "`reset()` method sets NMI to value 0"]
+impl crate::Resettable for NmiSpec {
+    const RESET_VALUE: u32 = 0;
+}

va108xx/src/irqsel/perid.rs

@@ -0,0 +1,18 @@
+#[doc = "Register `PERID` reader"]
+pub type R = crate::R<PeridSpec>;
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        write!(f, "{}", self.bits())
+    }
+}
+#[doc = "Peripheral ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`perid::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct PeridSpec;
+impl crate::RegisterSpec for PeridSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`perid::R`](R) reader structure"]
+impl crate::Readable for PeridSpec {}
+#[doc = "`reset()` method sets PERID to value 0x0080_07e1"]
+impl crate::Resettable for PeridSpec {
+    const RESET_VALUE: u32 = 0x0080_07e1;
+}

va108xx/src/porta.rs

@@ -0,0 +1,439 @@
+#[repr(C)]
+#[doc = "Register block"]
+pub struct RegisterBlock {
+    _reserved_0_datain: [u8; 0x04],
+    _reserved_1_datainraw: [u8; 0x04],
+    _reserved_2_dataout: [u8; 0x04],
+    _reserved_3_dataoutraw: [u8; 0x04],
+    _reserved_4_setout: [u8; 0x04],
+    _reserved_5_clrout: [u8; 0x04],
+    _reserved_6_togout: [u8; 0x04],
+    _reserved_7_datamask: [u8; 0x04],
+    _reserved_8_dir: [u8; 0x04],
+    _reserved_9_pulse: [u8; 0x04],
+    _reserved_10_pulsebase: [u8; 0x04],
+    _reserved_11_delay: [u8; 0x04],
+    _reserved_12_delay: [u8; 0x04],
+    irq_sen: IrqSen,
+    irq_edge: IrqEdge,
+    irq_evt: IrqEvt,
+    irq_enb: IrqEnb,
+    irq_raw: IrqRaw,
+    irq_end: IrqEnd,
+    edge_status: EdgeStatus,
+    _reserved20: [u8; 0x0fac],
+    perid: Perid,
+}
+impl RegisterBlock {
+    #[doc = "0x00 - Data In Register by Byte"]
+    #[inline(always)]
+    pub const fn datainbyte(&self, n: usize) -> &Datainbyte {
+        #[allow(clippy::no_effect)]
+        [(); 4][n];
+        unsafe { &*(self as *const Self).cast::<u8>().add(0).add(1 * n).cast() }
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "0x00 - Data In Register by Byte"]
+    #[inline(always)]
+    pub fn datainbyte_iter(&self) -> impl Iterator<Item = &Datainbyte> {
+        (0..4)
+            .map(move |n| unsafe { &*(self as *const Self).cast::<u8>().add(0).add(1 * n).cast() })
+    }
+    #[doc = "0x00 - Data In Register"]
+    #[inline(always)]
+    pub const fn datain(&self) -> &Datain {
+        unsafe { &*(self as *const Self).cast::<u8>().add(0).cast() }
+    }
+    #[doc = "0x04 - Data In Raw Register by Byte"]
+    #[inline(always)]
+    pub const fn datainrawbyte0(&self, n: usize) -> &Datainrawbyte {
+        #[allow(clippy::no_effect)]
+        [(); 4][n];
+        unsafe { &*(self as *const Self).cast::<u8>().add(4).add(1 * n).cast() }
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "0x04 - Data In Raw Register by Byte"]
+    #[inline(always)]
+    pub fn datainrawbyte0_iter(&self) -> impl Iterator<Item = &Datainrawbyte> {
+        (0..4)
+            .map(move |n| unsafe { &*(self as *const Self).cast::<u8>().add(4).add(1 * n).cast() })
+    }
+    #[doc = "0x04 - Data In Raw Register"]
+    #[inline(always)]
+    pub const fn datainraw(&self) -> &Datainraw {
+        unsafe { &*(self as *const Self).cast::<u8>().add(4).cast() }
+    }
+    #[doc = "0x08 - Data Out Register by Byte"]
+    #[inline(always)]
+    pub const fn dataoutbyte(&self, n: usize) -> &Dataoutbyte {
+        #[allow(clippy::no_effect)]
+        [(); 4][n];
+        unsafe { &*(self as *const Self).cast::<u8>().add(8).add(1 * n).cast() }
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "0x08 - Data Out Register by Byte"]
+    #[inline(always)]
+    pub fn dataoutbyte_iter(&self) -> impl Iterator<Item = &Dataoutbyte> {
+        (0..4)
+            .map(move |n| unsafe { &*(self as *const Self).cast::<u8>().add(8).add(1 * n).cast() })
+    }
+    #[doc = "0x08 - Data Out Register"]
+    #[inline(always)]
+    pub const fn dataout(&self) -> &Dataout {
+        unsafe { &*(self as *const Self).cast::<u8>().add(8).cast() }
+    }
+    #[doc = "0x0c - Data Out Register by Byte"]
+    #[inline(always)]
+    pub const fn dataoutrawbyte0(&self, n: usize) -> &Dataoutrawbyte {
+        #[allow(clippy::no_effect)]
+        [(); 4][n];
+        unsafe { &*(self as *const Self).cast::<u8>().add(12).add(1 * n).cast() }
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "0x0c - Data Out Register by Byte"]
+    #[inline(always)]
+    pub fn dataoutrawbyte0_iter(&self) -> impl Iterator<Item = &Dataoutrawbyte> {
+        (0..4)
+            .map(move |n| unsafe { &*(self as *const Self).cast::<u8>().add(12).add(1 * n).cast() })
+    }
+    #[doc = "0x0c - Data Out Register"]
+    #[inline(always)]
+    pub const fn dataoutraw(&self) -> &Dataoutraw {
+        unsafe { &*(self as *const Self).cast::<u8>().add(12).cast() }
+    }
+    #[doc = "0x10 - Set Out Register by Byte"]
+    #[inline(always)]
+    pub const fn setoutbyte0(&self, n: usize) -> &Setoutbyte {
+        #[allow(clippy::no_effect)]
+        [(); 4][n];
+        unsafe { &*(self as *const Self).cast::<u8>().add(16).add(1 * n).cast() }
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "0x10 - Set Out Register by Byte"]
+    #[inline(always)]
+    pub fn setoutbyte0_iter(&self) -> impl Iterator<Item = &Setoutbyte> {
+        (0..4)
+            .map(move |n| unsafe { &*(self as *const Self).cast::<u8>().add(16).add(1 * n).cast() })
+    }
+    #[doc = "0x10 - Set Out Register"]
+    #[inline(always)]
+    pub const fn setout(&self) -> &Setout {
+        unsafe { &*(self as *const Self).cast::<u8>().add(16).cast() }
+    }
+    #[doc = "0x14 - Clear Out Register by Byte"]
+    #[inline(always)]
+    pub const fn clroutbyte0(&self, n: usize) -> &Clroutbyte {
+        #[allow(clippy::no_effect)]
+        [(); 4][n];
+        unsafe { &*(self as *const Self).cast::<u8>().add(20).add(1 * n).cast() }
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "0x14 - Clear Out Register by Byte"]
+    #[inline(always)]
+    pub fn clroutbyte0_iter(&self) -> impl Iterator<Item = &Clroutbyte> {
+        (0..4)
+            .map(move |n| unsafe { &*(self as *const Self).cast::<u8>().add(20).add(1 * n).cast() })
+    }
+    #[doc = "0x14 - Clear Out Register"]
+    #[inline(always)]
+    pub const fn clrout(&self) -> &Clrout {
+        unsafe { &*(self as *const Self).cast::<u8>().add(20).cast() }
+    }
+    #[doc = "0x18 - Toggle Out Register by Byte"]
+    #[inline(always)]
+    pub const fn togoutbyte0(&self, n: usize) -> &Togoutbyte {
+        #[allow(clippy::no_effect)]
+        [(); 4][n];
+        unsafe { &*(self as *const Self).cast::<u8>().add(24).add(1 * n).cast() }
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "0x18 - Toggle Out Register by Byte"]
+    #[inline(always)]
+    pub fn togoutbyte0_iter(&self) -> impl Iterator<Item = &Togoutbyte> {
+        (0..4)
+            .map(move |n| unsafe { &*(self as *const Self).cast::<u8>().add(24).add(1 * n).cast() })
+    }
+    #[doc = "0x18 - Toggle Out Register"]
+    #[inline(always)]
+    pub const fn togout(&self) -> &Togout {
+        unsafe { &*(self as *const Self).cast::<u8>().add(24).cast() }
+    }
+    #[doc = "0x1c - Data Out Register by Byte"]
+    #[inline(always)]
+    pub const fn datamaskbyte(&self, n: usize) -> &Datamaskbyte {
+        #[allow(clippy::no_effect)]
+        [(); 4][n];
+        unsafe { &*(self as *const Self).cast::<u8>().add(28).add(1 * n).cast() }
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "0x1c - Data Out Register by Byte"]
+    #[inline(always)]
+    pub fn datamaskbyte_iter(&self) -> impl Iterator<Item = &Datamaskbyte> {
+        (0..4)
+            .map(move |n| unsafe { &*(self as *const Self).cast::<u8>().add(28).add(1 * n).cast() })
+    }
+    #[doc = "0x1c - Data mask Register"]
+    #[inline(always)]
+    pub const fn datamask(&self) -> &Datamask {
+        unsafe { &*(self as *const Self).cast::<u8>().add(28).cast() }
+    }
+    #[doc = "0x20 - Direction Register by Byte"]
+    #[inline(always)]
+    pub const fn dirbyte0(&self, n: usize) -> &Dirbyte {
+        #[allow(clippy::no_effect)]
+        [(); 4][n];
+        unsafe { &*(self as *const Self).cast::<u8>().add(32).add(1 * n).cast() }
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "0x20 - Direction Register by Byte"]
+    #[inline(always)]
+    pub fn dirbyte0_iter(&self) -> impl Iterator<Item = &Dirbyte> {
+        (0..4)
+            .map(move |n| unsafe { &*(self as *const Self).cast::<u8>().add(32).add(1 * n).cast() })
+    }
+    #[doc = "0x20 - Direction Register (1:Output, 0:Input)"]
+    #[inline(always)]
+    pub const fn dir(&self) -> &Dir {
+        unsafe { &*(self as *const Self).cast::<u8>().add(32).cast() }
+    }
+    #[doc = "0x24 - Pulse Mode Register by Byte"]
+    #[inline(always)]
+    pub const fn pulsebyte0(&self, n: usize) -> &Pulsebyte {
+        #[allow(clippy::no_effect)]
+        [(); 4][n];
+        unsafe { &*(self as *const Self).cast::<u8>().add(36).add(1 * n).cast() }
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "0x24 - Pulse Mode Register by Byte"]
+    #[inline(always)]
+    pub fn pulsebyte0_iter(&self) -> impl Iterator<Item = &Pulsebyte> {
+        (0..4)
+            .map(move |n| unsafe { &*(self as *const Self).cast::<u8>().add(36).add(1 * n).cast() })
+    }
+    #[doc = "0x24 - Pulse Mode Register"]
+    #[inline(always)]
+    pub const fn pulse(&self) -> &Pulse {
+        unsafe { &*(self as *const Self).cast::<u8>().add(36).cast() }
+    }
+    #[doc = "0x28 - Pulse Base Mode Register by Byte"]
+    #[inline(always)]
+    pub const fn pulsebasebyte0(&self, n: usize) -> &Pulsebasebyte {
+        #[allow(clippy::no_effect)]
+        [(); 4][n];
+        unsafe { &*(self as *const Self).cast::<u8>().add(40).add(1 * n).cast() }
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "0x28 - Pulse Base Mode Register by Byte"]
+    #[inline(always)]
+    pub fn pulsebasebyte0_iter(&self) -> impl Iterator<Item = &Pulsebasebyte> {
+        (0..4)
+            .map(move |n| unsafe { &*(self as *const Self).cast::<u8>().add(40).add(1 * n).cast() })
+    }
+    #[doc = "0x28 - Pulse Base Value Register"]
+    #[inline(always)]
+    pub const fn pulsebase(&self) -> &Pulsebase {
+        unsafe { &*(self as *const Self).cast::<u8>().add(40).cast() }
+    }
+    #[doc = "0x2c - Delay1 Register by Byte"]
+    #[inline(always)]
+    pub const fn delay1byte0(&self, n: usize) -> &Delay1byte {
+        #[allow(clippy::no_effect)]
+        [(); 4][n];
+        unsafe { &*(self as *const Self).cast::<u8>().add(44).add(1 * n).cast() }
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "0x2c - Delay1 Register by Byte"]
+    #[inline(always)]
+    pub fn delay1byte0_iter(&self) -> impl Iterator<Item = &Delay1byte> {
+        (0..4)
+            .map(move |n| unsafe { &*(self as *const Self).cast::<u8>().add(44).add(1 * n).cast() })
+    }
+    #[doc = "0x2c - Delay1 Register"]
+    #[inline(always)]
+    pub const fn delay1(&self) -> &Delay1 {
+        unsafe { &*(self as *const Self).cast::<u8>().add(44).cast() }
+    }
+    #[doc = "0x30 - Delay2 Register by Byte"]
+    #[inline(always)]
+    pub const fn delay2byte0(&self, n: usize) -> &Delay2byte {
+        #[allow(clippy::no_effect)]
+        [(); 4][n];
+        unsafe { &*(self as *const Self).cast::<u8>().add(48).add(1 * n).cast() }
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "0x30 - Delay2 Register by Byte"]
+    #[inline(always)]
+    pub fn delay2byte0_iter(&self) -> impl Iterator<Item = &Delay2byte> {
+        (0..4)
+            .map(move |n| unsafe { &*(self as *const Self).cast::<u8>().add(48).add(1 * n).cast() })
+    }
+    #[doc = "0x30 - Delay2 Register"]
+    #[inline(always)]
+    pub const fn delay2(&self) -> &Delay2 {
+        unsafe { &*(self as *const Self).cast::<u8>().add(48).cast() }
+    }
+    #[doc = "0x34 - Interrupt Sense Register (1:Level Sensitive, 0:Edge Sensitive)"]
+    #[inline(always)]
+    pub const fn irq_sen(&self) -> &IrqSen {
+        &self.irq_sen
+    }
+    #[doc = "0x38 - Interrupt Both Edge Register (1:Both Edges, 0:Single Edge)"]
+    #[inline(always)]
+    pub const fn irq_edge(&self) -> &IrqEdge {
+        &self.irq_edge
+    }
+    #[doc = "0x3c - Interrupt Event Register (1:HighLevel/L->H Edge, 0:LowLevel/H->L Edge)"]
+    #[inline(always)]
+    pub const fn irq_evt(&self) -> &IrqEvt {
+        &self.irq_evt
+    }
+    #[doc = "0x40 - Interrupt Enable Register"]
+    #[inline(always)]
+    pub const fn irq_enb(&self) -> &IrqEnb {
+        &self.irq_enb
+    }
+    #[doc = "0x44 - Raw Interrupt Status"]
+    #[inline(always)]
+    pub const fn irq_raw(&self) -> &IrqRaw {
+        &self.irq_raw
+    }
+    #[doc = "0x48 - Masked Interrupt Status"]
+    #[inline(always)]
+    pub const fn irq_end(&self) -> &IrqEnd {
+        &self.irq_end
+    }
+    #[doc = "0x4c - Edge Status Register"]
+    #[inline(always)]
+    pub const fn edge_status(&self) -> &EdgeStatus {
+        &self.edge_status
+    }
+    #[doc = "0xffc - Peripheral ID Register"]
+    #[inline(always)]
+    pub const fn perid(&self) -> &Perid {
+        &self.perid
+    }
+}
+#[doc = "DATAIN (r) register accessor: Data In Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`datain::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@datain`]
+module"]
+#[doc(alias = "DATAIN")]
+pub type Datain = crate::Reg<datain::DatainSpec>;
+#[doc = "Data In Register"]
+pub mod datain;
+#[doc = "DATAINBYTE (r) register accessor: Data In Register by Byte\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`datainbyte::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@datainbyte`]
+module"]
+#[doc(alias = "DATAINBYTE")]
+pub type Datainbyte = crate::Reg<datainbyte::DatainbyteSpec>;
+#[doc = "Data In Register by Byte"]
+pub mod datainbyte;
+pub use datain as datainraw;
+pub use datainbyte as datainrawbyte;
+pub use Datain as Datainraw;
+pub use Datainbyte as Datainrawbyte;
+#[doc = "DATAOUT (w) register accessor: Data Out Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dataout::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dataout`]
+module"]
+#[doc(alias = "DATAOUT")]
+pub type Dataout = crate::Reg<dataout::DataoutSpec>;
+#[doc = "Data Out Register"]
+pub mod dataout;
+#[doc = "DATAOUTBYTE (w) register accessor: Data Out Register by Byte\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dataoutbyte::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dataoutbyte`]
+module"]
+#[doc(alias = "DATAOUTBYTE")]
+pub type Dataoutbyte = crate::Reg<dataoutbyte::DataoutbyteSpec>;
+#[doc = "Data Out Register by Byte"]
+pub mod dataoutbyte;
+pub use dataout as dataoutraw;
+pub use dataout as setout;
+pub use dataout as clrout;
+pub use dataout as togout;
+pub use dataoutbyte as dataoutrawbyte;
+pub use dataoutbyte as setoutbyte;
+pub use dataoutbyte as clroutbyte;
+pub use dataoutbyte as togoutbyte;
+pub use Dataout as Dataoutraw;
+pub use Dataout as Setout;
+pub use Dataout as Clrout;
+pub use Dataout as Togout;
+pub use Dataoutbyte as Dataoutrawbyte;
+pub use Dataoutbyte as Setoutbyte;
+pub use Dataoutbyte as Clroutbyte;
+pub use Dataoutbyte as Togoutbyte;
+#[doc = "DATAMASK (rw) register accessor: Data mask Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`datamask::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`datamask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@datamask`]
+module"]
+#[doc(alias = "DATAMASK")]
+pub type Datamask = crate::Reg<datamask::DatamaskSpec>;
+#[doc = "Data mask Register"]
+pub mod datamask;
+#[doc = "DATAMASKBYTE (rw) register accessor: Data Out Register by Byte\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`datamaskbyte::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`datamaskbyte::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@datamaskbyte`]
+module"]
+#[doc(alias = "DATAMASKBYTE")]
+pub type Datamaskbyte = crate::Reg<datamaskbyte::DatamaskbyteSpec>;
+#[doc = "Data Out Register by Byte"]
+pub mod datamaskbyte;
+pub use datamask as dir;
+pub use datamask as pulse;
+pub use datamask as pulsebase;
+pub use datamask as delay1;
+pub use datamask as delay2;
+pub use datamaskbyte as dirbyte;
+pub use datamaskbyte as pulsebyte;
+pub use datamaskbyte as pulsebasebyte;
+pub use datamaskbyte as delay1byte;
+pub use datamaskbyte as delay2byte;
+pub use Datamask as Dir;
+pub use Datamask as Pulse;
+pub use Datamask as Pulsebase;
+pub use Datamask as Delay1;
+pub use Datamask as Delay2;
+pub use Datamaskbyte as Dirbyte;
+pub use Datamaskbyte as Pulsebyte;
+pub use Datamaskbyte as Pulsebasebyte;
+pub use Datamaskbyte as Delay1byte;
+pub use Datamaskbyte as Delay2byte;
+#[doc = "IRQ_SEN (rw) register accessor: Interrupt Sense Register (1:Level Sensitive, 0:Edge Sensitive)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_sen::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_sen::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_sen`]
+module"]
+#[doc(alias = "IRQ_SEN")]
+pub type IrqSen = crate::Reg<irq_sen::IrqSenSpec>;
+#[doc = "Interrupt Sense Register (1:Level Sensitive, 0:Edge Sensitive)"]
+pub mod irq_sen;
+#[doc = "IRQ_EDGE (rw) register accessor: Interrupt Both Edge Register (1:Both Edges, 0:Single Edge)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_edge::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_edge::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_edge`]
+module"]
+#[doc(alias = "IRQ_EDGE")]
+pub type IrqEdge = crate::Reg<irq_edge::IrqEdgeSpec>;
+#[doc = "Interrupt Both Edge Register (1:Both Edges, 0:Single Edge)"]
+pub mod irq_edge;
+#[doc = "IRQ_EVT (rw) register accessor: Interrupt Event Register (1:HighLevel/L->H Edge, 0:LowLevel/H->L Edge)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_evt::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_evt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_evt`]
+module"]
+#[doc(alias = "IRQ_EVT")]
+pub type IrqEvt = crate::Reg<irq_evt::IrqEvtSpec>;
+#[doc = "Interrupt Event Register (1:HighLevel/L->H Edge, 0:LowLevel/H->L Edge)"]
+pub mod irq_evt;
+#[doc = "IRQ_ENB (rw) register accessor: Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_enb::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_enb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_enb`]
+module"]
+#[doc(alias = "IRQ_ENB")]
+pub type IrqEnb = crate::Reg<irq_enb::IrqEnbSpec>;
+#[doc = "Interrupt Enable Register"]
+pub mod irq_enb;
+#[doc = "IRQ_RAW (r) register accessor: Raw Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_raw::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_raw`]
+module"]
+#[doc(alias = "IRQ_RAW")]
+pub type IrqRaw = crate::Reg<irq_raw::IrqRawSpec>;
+#[doc = "Raw Interrupt Status"]
+pub mod irq_raw;
+#[doc = "IRQ_END (r) register accessor: Masked Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_end::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_end`]
+module"]
+#[doc(alias = "IRQ_END")]
+pub type IrqEnd = crate::Reg<irq_end::IrqEndSpec>;
+#[doc = "Masked Interrupt Status"]
+pub mod irq_end;
+#[doc = "EDGE_STATUS (rw) register accessor: Edge Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`edge_status::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`edge_status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@edge_status`]
+module"]
+#[doc(alias = "EDGE_STATUS")]
+pub type EdgeStatus = crate::Reg<edge_status::EdgeStatusSpec>;
+#[doc = "Edge Status Register"]
+pub mod edge_status;
+#[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`perid::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`]
+module"]
+#[doc(alias = "PERID")]
+pub type Perid = crate::Reg<perid::PeridSpec>;
+#[doc = "Peripheral ID Register"]
+pub mod perid;

va108xx/src/porta/datain.rs

@@ -0,0 +1,18 @@
+#[doc = "Register `DATAIN` reader"]
+pub type R = crate::R<DatainSpec>;
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        write!(f, "{}", self.bits())
+    }
+}
+#[doc = "Data In Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`datain::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct DatainSpec;
+impl crate::RegisterSpec for DatainSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`datain::R`](R) reader structure"]
+impl crate::Readable for DatainSpec {}
+#[doc = "`reset()` method sets DATAIN to value 0"]
+impl crate::Resettable for DatainSpec {
+    const RESET_VALUE: u32 = 0;
+}

va108xx/src/porta/datainbyte.rs

@@ -0,0 +1,19 @@
+#[doc = "Register `DATAINBYTE[%s]` reader"]
+pub type R = crate::R<DatainbyteSpec>;
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        write!(f, "{}", self.bits())
+    }
+}
+#[doc = "Data In Register by Byte\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`datainbyte::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct DatainbyteSpec;
+impl crate::RegisterSpec for DatainbyteSpec {
+    type Ux = u8;
+}
+#[doc = "`read()` method returns [`datainbyte::R`](R) reader structure"]
+impl crate::Readable for DatainbyteSpec {}
+#[doc = "`reset()` method sets DATAINBYTE[%s]
+to value 0"]
+impl crate::Resettable for DatainbyteSpec {
+    const RESET_VALUE: u8 = 0;
+}

va108xx/src/porta/datamask.rs

@@ -0,0 +1,27 @@
+#[doc = "Register `DATAMASK` reader"]
+pub type R = crate::R<DatamaskSpec>;
+#[doc = "Register `DATAMASK` writer"]
+pub type W = crate::W<DatamaskSpec>;
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        write!(f, "{}", self.bits())
+    }
+}
+impl W {}
+#[doc = "Data mask Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`datamask::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`datamask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct DatamaskSpec;
+impl crate::RegisterSpec for DatamaskSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`datamask::R`](R) reader structure"]
+impl crate::Readable for DatamaskSpec {}
+#[doc = "`write(|w| ..)` method takes [`datamask::W`](W) writer structure"]
+impl crate::Writable for DatamaskSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets DATAMASK to value 0"]
+impl crate::Resettable for DatamaskSpec {
+    const RESET_VALUE: u32 = 0;
+}

va108xx/src/porta/datamaskbyte.rs

@@ -0,0 +1,28 @@
+#[doc = "Register `DATAMASKBYTE[%s]` reader"]
+pub type R = crate::R<DatamaskbyteSpec>;
+#[doc = "Register `DATAMASKBYTE[%s]` writer"]
+pub type W = crate::W<DatamaskbyteSpec>;
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        write!(f, "{}", self.bits())
+    }
+}
+impl W {}
+#[doc = "Data Out Register by Byte\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`datamaskbyte::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`datamaskbyte::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct DatamaskbyteSpec;
+impl crate::RegisterSpec for DatamaskbyteSpec {
+    type Ux = u8;
+}
+#[doc = "`read()` method returns [`datamaskbyte::R`](R) reader structure"]
+impl crate::Readable for DatamaskbyteSpec {}
+#[doc = "`write(|w| ..)` method takes [`datamaskbyte::W`](W) writer structure"]
+impl crate::Writable for DatamaskbyteSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u8 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u8 = 0;
+}
+#[doc = "`reset()` method sets DATAMASKBYTE[%s]
+to value 0"]
+impl crate::Resettable for DatamaskbyteSpec {
+    const RESET_VALUE: u8 = 0;
+}

va108xx/src/porta/dataout.rs

@@ -0,0 +1,23 @@
+#[doc = "Register `DATAOUT` writer"]
+pub type W = crate::W<DataoutSpec>;
+impl core::fmt::Debug for crate::generic::Reg<DataoutSpec> {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        write!(f, "(not readable)")
+    }
+}
+impl W {}
+#[doc = "Data Out Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dataout::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct DataoutSpec;
+impl crate::RegisterSpec for DataoutSpec {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [`dataout::W`](W) writer structure"]
+impl crate::Writable for DataoutSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets DATAOUT to value 0"]
+impl crate::Resettable for DataoutSpec {
+    const RESET_VALUE: u32 = 0;
+}

va108xx/src/porta/dataoutbyte.rs

@@ -0,0 +1,24 @@
+#[doc = "Register `DATAOUTBYTE[%s]` writer"]
+pub type W = crate::W<DataoutbyteSpec>;
+impl core::fmt::Debug for crate::generic::Reg<DataoutbyteSpec> {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        write!(f, "(not readable)")
+    }
+}
+impl W {}
+#[doc = "Data Out Register by Byte\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dataoutbyte::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct DataoutbyteSpec;
+impl crate::RegisterSpec for DataoutbyteSpec {
+    type Ux = u8;
+}
+#[doc = "`write(|w| ..)` method takes [`dataoutbyte::W`](W) writer structure"]
+impl crate::Writable for DataoutbyteSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u8 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u8 = 0;
+}
+#[doc = "`reset()` method sets DATAOUTBYTE[%s]
+to value 0"]
+impl crate::Resettable for DataoutbyteSpec {
+    const RESET_VALUE: u8 = 0;
+}

va108xx/src/porta/edge_status.rs

@@ -0,0 +1,27 @@
+#[doc = "Register `EDGE_STATUS` reader"]
+pub type R = crate::R<EdgeStatusSpec>;
+#[doc = "Register `EDGE_STATUS` writer"]
+pub type W = crate::W<EdgeStatusSpec>;
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        write!(f, "{}", self.bits())
+    }
+}
+impl W {}
+#[doc = "Edge Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`edge_status::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`edge_status::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct EdgeStatusSpec;
+impl crate::RegisterSpec for EdgeStatusSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`edge_status::R`](R) reader structure"]
+impl crate::Readable for EdgeStatusSpec {}
+#[doc = "`write(|w| ..)` method takes [`edge_status::W`](W) writer structure"]
+impl crate::Writable for EdgeStatusSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets EDGE_STATUS to value 0"]
+impl crate::Resettable for EdgeStatusSpec {
+    const RESET_VALUE: u32 = 0;
+}

va108xx/src/porta/irq_edge.rs

@@ -0,0 +1,27 @@
+#[doc = "Register `IRQ_EDGE` reader"]
+pub type R = crate::R<IrqEdgeSpec>;
+#[doc = "Register `IRQ_EDGE` writer"]
+pub type W = crate::W<IrqEdgeSpec>;
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        write!(f, "{}", self.bits())
+    }
+}
+impl W {}
+#[doc = "Interrupt Both Edge Register (1:Both Edges, 0:Single Edge)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_edge::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_edge::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct IrqEdgeSpec;
+impl crate::RegisterSpec for IrqEdgeSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`irq_edge::R`](R) reader structure"]
+impl crate::Readable for IrqEdgeSpec {}
+#[doc = "`write(|w| ..)` method takes [`irq_edge::W`](W) writer structure"]
+impl crate::Writable for IrqEdgeSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets IRQ_EDGE to value 0"]
+impl crate::Resettable for IrqEdgeSpec {
+    const RESET_VALUE: u32 = 0;
+}

va108xx/src/porta/irq_enb.rs

@@ -0,0 +1,27 @@
+#[doc = "Register `IRQ_ENB` reader"]
+pub type R = crate::R<IrqEnbSpec>;
+#[doc = "Register `IRQ_ENB` writer"]
+pub type W = crate::W<IrqEnbSpec>;
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        write!(f, "{}", self.bits())
+    }
+}
+impl W {}
+#[doc = "Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_enb::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_enb::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct IrqEnbSpec;
+impl crate::RegisterSpec for IrqEnbSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`irq_enb::R`](R) reader structure"]
+impl crate::Readable for IrqEnbSpec {}
+#[doc = "`write(|w| ..)` method takes [`irq_enb::W`](W) writer structure"]
+impl crate::Writable for IrqEnbSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets IRQ_ENB to value 0"]
+impl crate::Resettable for IrqEnbSpec {
+    const RESET_VALUE: u32 = 0;
+}

va108xx/src/porta/irq_end.rs

@@ -0,0 +1,18 @@
+#[doc = "Register `IRQ_END` reader"]
+pub type R = crate::R<IrqEndSpec>;
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        write!(f, "{}", self.bits())
+    }
+}
+#[doc = "Masked Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_end::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct IrqEndSpec;
+impl crate::RegisterSpec for IrqEndSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`irq_end::R`](R) reader structure"]
+impl crate::Readable for IrqEndSpec {}
+#[doc = "`reset()` method sets IRQ_END to value 0"]
+impl crate::Resettable for IrqEndSpec {
+    const RESET_VALUE: u32 = 0;
+}

va108xx/src/porta/irq_evt.rs

@@ -0,0 +1,27 @@
+#[doc = "Register `IRQ_EVT` reader"]
+pub type R = crate::R<IrqEvtSpec>;
+#[doc = "Register `IRQ_EVT` writer"]
+pub type W = crate::W<IrqEvtSpec>;
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        write!(f, "{}", self.bits())
+    }
+}
+impl W {}
+#[doc = "Interrupt Event Register (1:HighLevel/L->H Edge, 0:LowLevel/H->L Edge)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_evt::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_evt::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct IrqEvtSpec;
+impl crate::RegisterSpec for IrqEvtSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`irq_evt::R`](R) reader structure"]
+impl crate::Readable for IrqEvtSpec {}
+#[doc = "`write(|w| ..)` method takes [`irq_evt::W`](W) writer structure"]
+impl crate::Writable for IrqEvtSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets IRQ_EVT to value 0"]
+impl crate::Resettable for IrqEvtSpec {
+    const RESET_VALUE: u32 = 0;
+}

va108xx/src/porta/irq_raw.rs

@@ -0,0 +1,18 @@
+#[doc = "Register `IRQ_RAW` reader"]
+pub type R = crate::R<IrqRawSpec>;
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        write!(f, "{}", self.bits())
+    }
+}
+#[doc = "Raw Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_raw::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct IrqRawSpec;
+impl crate::RegisterSpec for IrqRawSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`irq_raw::R`](R) reader structure"]
+impl crate::Readable for IrqRawSpec {}
+#[doc = "`reset()` method sets IRQ_RAW to value 0"]
+impl crate::Resettable for IrqRawSpec {
+    const RESET_VALUE: u32 = 0;
+}

va108xx/src/porta/irq_sen.rs

@@ -0,0 +1,27 @@
+#[doc = "Register `IRQ_SEN` reader"]
+pub type R = crate::R<IrqSenSpec>;
+#[doc = "Register `IRQ_SEN` writer"]
+pub type W = crate::W<IrqSenSpec>;
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        write!(f, "{}", self.bits())
+    }
+}
+impl W {}
+#[doc = "Interrupt Sense Register (1:Level Sensitive, 0:Edge Sensitive)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_sen::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_sen::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct IrqSenSpec;
+impl crate::RegisterSpec for IrqSenSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`irq_sen::R`](R) reader structure"]
+impl crate::Readable for IrqSenSpec {}
+#[doc = "`write(|w| ..)` method takes [`irq_sen::W`](W) writer structure"]
+impl crate::Writable for IrqSenSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets IRQ_SEN to value 0"]
+impl crate::Resettable for IrqSenSpec {
+    const RESET_VALUE: u32 = 0;
+}

va108xx/src/porta/perid.rs

@@ -0,0 +1,18 @@
+#[doc = "Register `PERID` reader"]
+pub type R = crate::R<PeridSpec>;
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        write!(f, "{}", self.bits())
+    }
+}
+#[doc = "Peripheral ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`perid::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct PeridSpec;
+impl crate::RegisterSpec for PeridSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`perid::R`](R) reader structure"]
+impl crate::Readable for PeridSpec {}
+#[doc = "`reset()` method sets PERID to value 0x0010_07e1"]
+impl crate::Resettable for PeridSpec {
+    const RESET_VALUE: u32 = 0x0010_07e1;
+}

va108xx/src/spia.rs

@@ -0,0 +1,163 @@
+#[repr(C)]
+#[doc = "Register block"]
+pub struct RegisterBlock {
+    ctrl0: Ctrl0,
+    ctrl1: Ctrl1,
+    data: Data,
+    status: Status,
+    clkprescale: Clkprescale,
+    irq_enb: IrqEnb,
+    irq_raw: IrqRaw,
+    irq_end: IrqEnd,
+    irq_clr: IrqClr,
+    rxfifoirqtrg: Rxfifoirqtrg,
+    txfifoirqtrg: Txfifoirqtrg,
+    fifo_clr: FifoClr,
+    state: State,
+    _reserved13: [u8; 0x0fc8],
+    perid: Perid,
+}
+impl RegisterBlock {
+    #[doc = "0x00 - Control Register 0"]
+    #[inline(always)]
+    pub const fn ctrl0(&self) -> &Ctrl0 {
+        &self.ctrl0
+    }
+    #[doc = "0x04 - Control Register 1"]
+    #[inline(always)]
+    pub const fn ctrl1(&self) -> &Ctrl1 {
+        &self.ctrl1
+    }
+    #[doc = "0x08 - Data Input/Output"]
+    #[inline(always)]
+    pub const fn data(&self) -> &Data {
+        &self.data
+    }
+    #[doc = "0x0c - Status Register"]
+    #[inline(always)]
+    pub const fn status(&self) -> &Status {
+        &self.status
+    }
+    #[doc = "0x10 - Clock Pre Scale divide value"]
+    #[inline(always)]
+    pub const fn clkprescale(&self) -> &Clkprescale {
+        &self.clkprescale
+    }
+    #[doc = "0x14 - Interrupt Enable Register"]
+    #[inline(always)]
+    pub const fn irq_enb(&self) -> &IrqEnb {
+        &self.irq_enb
+    }
+    #[doc = "0x18 - Raw Interrupt Status Register"]
+    #[inline(always)]
+    pub const fn irq_raw(&self) -> &IrqRaw {
+        &self.irq_raw
+    }
+    #[doc = "0x1c - Enabled Interrupt Status Register"]
+    #[inline(always)]
+    pub const fn irq_end(&self) -> &IrqEnd {
+        &self.irq_end
+    }
+    #[doc = "0x20 - Clear Interrupt Status Register"]
+    #[inline(always)]
+    pub const fn irq_clr(&self) -> &IrqClr {
+        &self.irq_clr
+    }
+    #[doc = "0x24 - Rx FIFO IRQ Trigger Level"]
+    #[inline(always)]
+    pub const fn rxfifoirqtrg(&self) -> &Rxfifoirqtrg {
+        &self.rxfifoirqtrg
+    }
+    #[doc = "0x28 - Tx FIFO IRQ Trigger Level"]
+    #[inline(always)]
+    pub const fn txfifoirqtrg(&self) -> &Txfifoirqtrg {
+        &self.txfifoirqtrg
+    }
+    #[doc = "0x2c - Clear FIFO Register"]
+    #[inline(always)]
+    pub const fn fifo_clr(&self) -> &FifoClr {
+        &self.fifo_clr
+    }
+    #[doc = "0x30 - Internal STATE of SPI Controller"]
+    #[inline(always)]
+    pub const fn state(&self) -> &State {
+        &self.state
+    }
+    #[doc = "0xffc - Peripheral ID Register"]
+    #[inline(always)]
+    pub const fn perid(&self) -> &Perid {
+        &self.perid
+    }
+}
+#[doc = "CTRL0 (rw) register accessor: Control Register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl0::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl0`]
+module"]
+#[doc(alias = "CTRL0")]
+pub type Ctrl0 = crate::Reg<ctrl0::Ctrl0Spec>;
+#[doc = "Control Register 0"]
+pub mod ctrl0;
+#[doc = "CTRL1 (rw) register accessor: Control Register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl1::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl1`]
+module"]
+#[doc(alias = "CTRL1")]
+pub type Ctrl1 = crate::Reg<ctrl1::Ctrl1Spec>;
+#[doc = "Control Register 1"]
+pub mod ctrl1;
+#[doc = "DATA (rw) register accessor: Data Input/Output\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data`]
+module"]
+#[doc(alias = "DATA")]
+pub type Data = crate::Reg<data::DataSpec>;
+#[doc = "Data Input/Output"]
+pub mod data;
+#[doc = "STATUS (r) register accessor: Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status`]
+module"]
+#[doc(alias = "STATUS")]
+pub type Status = crate::Reg<status::StatusSpec>;
+#[doc = "Status Register"]
+pub mod status;
+#[doc = "CLKPRESCALE (rw) register accessor: Clock Pre Scale divide value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkprescale::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkprescale::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clkprescale`]
+module"]
+#[doc(alias = "CLKPRESCALE")]
+pub type Clkprescale = crate::Reg<clkprescale::ClkprescaleSpec>;
+#[doc = "Clock Pre Scale divide value"]
+pub mod clkprescale;
+#[doc = "IRQ_ENB (rw) register accessor: Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_enb::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_enb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_enb`]
+module"]
+#[doc(alias = "IRQ_ENB")]
+pub type IrqEnb = crate::Reg<irq_enb::IrqEnbSpec>;
+#[doc = "Interrupt Enable Register"]
+pub mod irq_enb;
+pub use irq_enb as irq_raw;
+pub use irq_enb as irq_end;
+pub use irq_enb as irq_clr;
+pub use IrqEnb as IrqRaw;
+pub use IrqEnb as IrqEnd;
+pub use IrqEnb as IrqClr;
+#[doc = "RXFIFOIRQTRG (rw) register accessor: Rx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxfifoirqtrg::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxfifoirqtrg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxfifoirqtrg`]
+module"]
+#[doc(alias = "RXFIFOIRQTRG")]
+pub type Rxfifoirqtrg = crate::Reg<rxfifoirqtrg::RxfifoirqtrgSpec>;
+#[doc = "Rx FIFO IRQ Trigger Level"]
+pub mod rxfifoirqtrg;
+#[doc = "TXFIFOIRQTRG (rw) register accessor: Tx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txfifoirqtrg::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txfifoirqtrg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txfifoirqtrg`]
+module"]
+#[doc(alias = "TXFIFOIRQTRG")]
+pub type Txfifoirqtrg = crate::Reg<txfifoirqtrg::TxfifoirqtrgSpec>;
+#[doc = "Tx FIFO IRQ Trigger Level"]
+pub mod txfifoirqtrg;
+#[doc = "FIFO_CLR (w) register accessor: Clear FIFO Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifo_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifo_clr`]
+module"]
+#[doc(alias = "FIFO_CLR")]
+pub type FifoClr = crate::Reg<fifo_clr::FifoClrSpec>;
+#[doc = "Clear FIFO Register"]
+pub mod fifo_clr;
+#[doc = "STATE (r) register accessor: Internal STATE of SPI Controller\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`state::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@state`]
+module"]
+#[doc(alias = "STATE")]
+pub type State = crate::Reg<state::StateSpec>;
+#[doc = "Internal STATE of SPI Controller"]
+pub mod state;
+#[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`perid::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`]
+module"]
+#[doc(alias = "PERID")]
+pub type Perid = crate::Reg<perid::PeridSpec>;
+#[doc = "Peripheral ID Register"]
+pub mod perid;

va108xx/src/spia/clkprescale.rs

@@ -0,0 +1,27 @@
+#[doc = "Register `CLKPRESCALE` reader"]
+pub type R = crate::R<ClkprescaleSpec>;
+#[doc = "Register `CLKPRESCALE` writer"]
+pub type W = crate::W<ClkprescaleSpec>;
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        write!(f, "{}", self.bits())
+    }
+}
+impl W {}
+#[doc = "Clock Pre Scale divide value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkprescale::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkprescale::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct ClkprescaleSpec;
+impl crate::RegisterSpec for ClkprescaleSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`clkprescale::R`](R) reader structure"]
+impl crate::Readable for ClkprescaleSpec {}
+#[doc = "`write(|w| ..)` method takes [`clkprescale::W`](W) writer structure"]
+impl crate::Writable for ClkprescaleSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CLKPRESCALE to value 0"]
+impl crate::Resettable for ClkprescaleSpec {
+    const RESET_VALUE: u32 = 0;
+}

va108xx/src/spia/ctrl0.rs

@@ -0,0 +1,85 @@
+#[doc = "Register `CTRL0` reader"]
+pub type R = crate::R<Ctrl0Spec>;
+#[doc = "Register `CTRL0` writer"]
+pub type W = crate::W<Ctrl0Spec>;
+#[doc = "Field `SIZE` reader - Data Size(0x3=>4, 0xf=>16)"]
+pub type SizeR = crate::FieldReader;
+#[doc = "Field `SIZE` writer - Data Size(0x3=>4, 0xf=>16)"]
+pub type SizeW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
+#[doc = "Field `SPO` reader - SPI Clock Polarity"]
+pub type SpoR = crate::BitReader;
+#[doc = "Field `SPO` writer - SPI Clock Polarity"]
+pub type SpoW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SPH` reader - SPI Clock Phase"]
+pub type SphR = crate::BitReader;
+#[doc = "Field `SPH` writer - SPI Clock Phase"]
+pub type SphW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SCRDV` reader - Serial Clock Rate divide+1 value"]
+pub type ScrdvR = crate::FieldReader;
+#[doc = "Field `SCRDV` writer - Serial Clock Rate divide+1 value"]
+pub type ScrdvW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
+impl R {
+    #[doc = "Bits 0:3 - Data Size(0x3=>4, 0xf=>16)"]
+    #[inline(always)]
+    pub fn size(&self) -> SizeR {
+        SizeR::new((self.bits & 0x0f) as u8)
+    }
+    #[doc = "Bit 6 - SPI Clock Polarity"]
+    #[inline(always)]
+    pub fn spo(&self) -> SpoR {
+        SpoR::new(((self.bits >> 6) & 1) != 0)
+    }
+    #[doc = "Bit 7 - SPI Clock Phase"]
+    #[inline(always)]
+    pub fn sph(&self) -> SphR {
+        SphR::new(((self.bits >> 7) & 1) != 0)
+    }
+    #[doc = "Bits 8:15 - Serial Clock Rate divide+1 value"]
+    #[inline(always)]
+    pub fn scrdv(&self) -> ScrdvR {
+        ScrdvR::new(((self.bits >> 8) & 0xff) as u8)
+    }
+}
+impl W {
+    #[doc = "Bits 0:3 - Data Size(0x3=>4, 0xf=>16)"]
+    #[inline(always)]
+    #[must_use]
+    pub fn size(&mut self) -> SizeW<Ctrl0Spec> {
+        SizeW::new(self, 0)
+    }
+    #[doc = "Bit 6 - SPI Clock Polarity"]
+    #[inline(always)]
+    #[must_use]
+    pub fn spo(&mut self) -> SpoW<Ctrl0Spec> {
+        SpoW::new(self, 6)
+    }
+    #[doc = "Bit 7 - SPI Clock Phase"]
+    #[inline(always)]
+    #[must_use]
+    pub fn sph(&mut self) -> SphW<Ctrl0Spec> {
+        SphW::new(self, 7)
+    }
+    #[doc = "Bits 8:15 - Serial Clock Rate divide+1 value"]
+    #[inline(always)]
+    #[must_use]
+    pub fn scrdv(&mut self) -> ScrdvW<Ctrl0Spec> {
+        ScrdvW::new(self, 8)
+    }
+}
+#[doc = "Control Register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct Ctrl0Spec;
+impl crate::RegisterSpec for Ctrl0Spec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`ctrl0::R`](R) reader structure"]
+impl crate::Readable for Ctrl0Spec {}
+#[doc = "`write(|w| ..)` method takes [`ctrl0::W`](W) writer structure"]
+impl crate::Writable for Ctrl0Spec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CTRL0 to value 0"]
+impl crate::Resettable for Ctrl0Spec {
+    const RESET_VALUE: u32 = 0;
+}

va108xx/src/spia/ctrl1.rs

@@ -0,0 +1,175 @@
+#[doc = "Register `CTRL1` reader"]
+pub type R = crate::R<Ctrl1Spec>;
+#[doc = "Register `CTRL1` writer"]
+pub type W = crate::W<Ctrl1Spec>;
+#[doc = "Field `LBM` reader - Loop Back"]
+pub type LbmR = crate::BitReader;
+#[doc = "Field `LBM` writer - Loop Back"]
+pub type LbmW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `ENABLE` reader - Enable"]
+pub type EnableR = crate::BitReader;
+#[doc = "Field `ENABLE` writer - Enable"]
+pub type EnableW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `MS` reader - Master/Slave (0:Master, 1:Slave)"]
+pub type MsR = crate::BitReader;
+#[doc = "Field `MS` writer - Master/Slave (0:Master, 1:Slave)"]
+pub type MsW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SOD` reader - Slave output Disable"]
+pub type SodR = crate::BitReader;
+#[doc = "Field `SOD` writer - Slave output Disable"]
+pub type SodW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SS` reader - Slave Select"]
+pub type SsR = crate::FieldReader;
+#[doc = "Field `SS` writer - Slave Select"]
+pub type SsW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
+#[doc = "Field `BLOCKMODE` reader - Block Mode Enable"]
+pub type BlockmodeR = crate::BitReader;
+#[doc = "Field `BLOCKMODE` writer - Block Mode Enable"]
+pub type BlockmodeW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `BMSTART` reader - Block Mode Start Status Enable"]
+pub type BmstartR = crate::BitReader;
+#[doc = "Field `BMSTART` writer - Block Mode Start Status Enable"]
+pub type BmstartW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `BMSTALL` reader - Block Mode Stall Enable"]
+pub type BmstallR = crate::BitReader;
+#[doc = "Field `BMSTALL` writer - Block Mode Stall Enable"]
+pub type BmstallW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `MDLYCAP` reader - Master Delayed Capture Enable"]
+pub type MdlycapR = crate::BitReader;
+#[doc = "Field `MDLYCAP` writer - Master Delayed Capture Enable"]
+pub type MdlycapW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `MTXPAUSE` reader - Master Tx Pause Enable"]
+pub type MtxpauseR = crate::BitReader;
+#[doc = "Field `MTXPAUSE` writer - Master Tx Pause Enable"]
+pub type MtxpauseW<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - Loop Back"]
+    #[inline(always)]
+    pub fn lbm(&self) -> LbmR {
+        LbmR::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - Enable"]
+    #[inline(always)]
+    pub fn enable(&self) -> EnableR {
+        EnableR::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - Master/Slave (0:Master, 1:Slave)"]
+    #[inline(always)]
+    pub fn ms(&self) -> MsR {
+        MsR::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - Slave output Disable"]
+    #[inline(always)]
+    pub fn sod(&self) -> SodR {
+        SodR::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bits 4:6 - Slave Select"]
+    #[inline(always)]
+    pub fn ss(&self) -> SsR {
+        SsR::new(((self.bits >> 4) & 7) as u8)
+    }
+    #[doc = "Bit 7 - Block Mode Enable"]
+    #[inline(always)]
+    pub fn blockmode(&self) -> BlockmodeR {
+        BlockmodeR::new(((self.bits >> 7) & 1) != 0)
+    }
+    #[doc = "Bit 8 - Block Mode Start Status Enable"]
+    #[inline(always)]
+    pub fn bmstart(&self) -> BmstartR {
+        BmstartR::new(((self.bits >> 8) & 1) != 0)
+    }
+    #[doc = "Bit 9 - Block Mode Stall Enable"]
+    #[inline(always)]
+    pub fn bmstall(&self) -> BmstallR {
+        BmstallR::new(((self.bits >> 9) & 1) != 0)
+    }
+    #[doc = "Bit 10 - Master Delayed Capture Enable"]
+    #[inline(always)]
+    pub fn mdlycap(&self) -> MdlycapR {
+        MdlycapR::new(((self.bits >> 10) & 1) != 0)
+    }
+    #[doc = "Bit 11 - Master Tx Pause Enable"]
+    #[inline(always)]
+    pub fn mtxpause(&self) -> MtxpauseR {
+        MtxpauseR::new(((self.bits >> 11) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Loop Back"]
+    #[inline(always)]
+    #[must_use]
+    pub fn lbm(&mut self) -> LbmW<Ctrl1Spec> {
+        LbmW::new(self, 0)
+    }
+    #[doc = "Bit 1 - Enable"]
+    #[inline(always)]
+    #[must_use]
+    pub fn enable(&mut self) -> EnableW<Ctrl1Spec> {
+        EnableW::new(self, 1)
+    }
+    #[doc = "Bit 2 - Master/Slave (0:Master, 1:Slave)"]
+    #[inline(always)]
+    #[must_use]
+    pub fn ms(&mut self) -> MsW<Ctrl1Spec> {
+        MsW::new(self, 2)
+    }
+    #[doc = "Bit 3 - Slave output Disable"]
+    #[inline(always)]
+    #[must_use]
+    pub fn sod(&mut self) -> SodW<Ctrl1Spec> {
+        SodW::new(self, 3)
+    }
+    #[doc = "Bits 4:6 - Slave Select"]
+    #[inline(always)]
+    #[must_use]
+    pub fn ss(&mut self) -> SsW<Ctrl1Spec> {
+        SsW::new(self, 4)
+    }
+    #[doc = "Bit 7 - Block Mode Enable"]
+    #[inline(always)]
+    #[must_use]
+    pub fn blockmode(&mut self) -> BlockmodeW<Ctrl1Spec> {
+        BlockmodeW::new(self, 7)
+    }
+    #[doc = "Bit 8 - Block Mode Start Status Enable"]
+    #[inline(always)]
+    #[must_use]
+    pub fn bmstart(&mut self) -> BmstartW<Ctrl1Spec> {
+        BmstartW::new(self, 8)
+    }
+    #[doc = "Bit 9 - Block Mode Stall Enable"]
+    #[inline(always)]
+    #[must_use]
+    pub fn bmstall(&mut self) -> BmstallW<Ctrl1Spec> {
+        BmstallW::new(self, 9)
+    }
+    #[doc = "Bit 10 - Master Delayed Capture Enable"]
+    #[inline(always)]
+    #[must_use]
+    pub fn mdlycap(&mut self) -> MdlycapW<Ctrl1Spec> {
+        MdlycapW::new(self, 10)
+    }
+    #[doc = "Bit 11 - Master Tx Pause Enable"]
+    #[inline(always)]
+    #[must_use]
+    pub fn mtxpause(&mut self) -> MtxpauseW<Ctrl1Spec> {
+        MtxpauseW::new(self, 11)
+    }
+}
+#[doc = "Control Register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct Ctrl1Spec;
+impl crate::RegisterSpec for Ctrl1Spec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`ctrl1::R`](R) reader structure"]
+impl crate::Readable for Ctrl1Spec {}
+#[doc = "`write(|w| ..)` method takes [`ctrl1::W`](W) writer structure"]
+impl crate::Writable for Ctrl1Spec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CTRL1 to value 0"]
+impl crate::Resettable for Ctrl1Spec {
+    const RESET_VALUE: u32 = 0;
+}

va108xx/src/spia/data.rs

@@ -0,0 +1,27 @@
+#[doc = "Register `DATA` reader"]
+pub type R = crate::R<DataSpec>;
+#[doc = "Register `DATA` writer"]
+pub type W = crate::W<DataSpec>;
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        write!(f, "{}", self.bits())
+    }
+}
+impl W {}
+#[doc = "Data Input/Output\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct DataSpec;
+impl crate::RegisterSpec for DataSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`data::R`](R) reader structure"]
+impl crate::Readable for DataSpec {}
+#[doc = "`write(|w| ..)` method takes [`data::W`](W) writer structure"]
+impl crate::Writable for DataSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets DATA to value 0"]
+impl crate::Resettable for DataSpec {
+    const RESET_VALUE: u32 = 0;
+}

va108xx/src/spia/fifo_clr.rs

@@ -0,0 +1,35 @@
+#[doc = "Register `FIFO_CLR` writer"]
+pub type W = crate::W<FifoClrSpec>;
+#[doc = "Field `RXFIFO` writer - Clear Rx FIFO"]
+pub type RxfifoW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TXFIFO` writer - Clear Tx FIFO"]
+pub type TxfifoW<'a, REG> = crate::BitWriter<'a, REG>;
+impl W {
+    #[doc = "Bit 0 - Clear Rx FIFO"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rxfifo(&mut self) -> RxfifoW<FifoClrSpec> {
+        RxfifoW::new(self, 0)
+    }
+    #[doc = "Bit 1 - Clear Tx FIFO"]
+    #[inline(always)]
+    #[must_use]
+    pub fn txfifo(&mut self) -> TxfifoW<FifoClrSpec> {
+        TxfifoW::new(self, 1)
+    }
+}
+#[doc = "Clear FIFO Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifo_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct FifoClrSpec;
+impl crate::RegisterSpec for FifoClrSpec {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [`fifo_clr::W`](W) writer structure"]
+impl crate::Writable for FifoClrSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets FIFO_CLR to value 0"]
+impl crate::Resettable for FifoClrSpec {
+    const RESET_VALUE: u32 = 0;
+}

va108xx/src/spia/irq_enb.rs

@@ -0,0 +1,85 @@
+#[doc = "Register `IRQ_ENB` reader"]
+pub type R = crate::R<IrqEnbSpec>;
+#[doc = "Register `IRQ_ENB` writer"]
+pub type W = crate::W<IrqEnbSpec>;
+#[doc = "Field `RORIM` reader - RX Overrun"]
+pub type RorimR = crate::BitReader;
+#[doc = "Field `RORIM` writer - RX Overrun"]
+pub type RorimW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `RTIM` reader - RX Timeout"]
+pub type RtimR = crate::BitReader;
+#[doc = "Field `RTIM` writer - RX Timeout"]
+pub type RtimW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `RXIM` reader - RX Fifo is at least half full"]
+pub type RximR = crate::BitReader;
+#[doc = "Field `RXIM` writer - RX Fifo is at least half full"]
+pub type RximW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TXIM` reader - TX Fifo is at least half empty"]
+pub type TximR = crate::BitReader;
+#[doc = "Field `TXIM` writer - TX Fifo is at least half empty"]
+pub type TximW<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - RX Overrun"]
+    #[inline(always)]
+    pub fn rorim(&self) -> RorimR {
+        RorimR::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - RX Timeout"]
+    #[inline(always)]
+    pub fn rtim(&self) -> RtimR {
+        RtimR::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - RX Fifo is at least half full"]
+    #[inline(always)]
+    pub fn rxim(&self) -> RximR {
+        RximR::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - TX Fifo is at least half empty"]
+    #[inline(always)]
+    pub fn txim(&self) -> TximR {
+        TximR::new(((self.bits >> 3) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - RX Overrun"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rorim(&mut self) -> RorimW<IrqEnbSpec> {
+        RorimW::new(self, 0)
+    }
+    #[doc = "Bit 1 - RX Timeout"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rtim(&mut self) -> RtimW<IrqEnbSpec> {
+        RtimW::new(self, 1)
+    }
+    #[doc = "Bit 2 - RX Fifo is at least half full"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rxim(&mut self) -> RximW<IrqEnbSpec> {
+        RximW::new(self, 2)
+    }
+    #[doc = "Bit 3 - TX Fifo is at least half empty"]
+    #[inline(always)]
+    #[must_use]
+    pub fn txim(&mut self) -> TximW<IrqEnbSpec> {
+        TximW::new(self, 3)
+    }
+}
+#[doc = "Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_enb::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_enb::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct IrqEnbSpec;
+impl crate::RegisterSpec for IrqEnbSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`irq_enb::R`](R) reader structure"]
+impl crate::Readable for IrqEnbSpec {}
+#[doc = "`write(|w| ..)` method takes [`irq_enb::W`](W) writer structure"]
+impl crate::Writable for IrqEnbSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets IRQ_ENB to value 0"]
+impl crate::Resettable for IrqEnbSpec {
+    const RESET_VALUE: u32 = 0;
+}

va108xx/src/spia/perid.rs

@@ -0,0 +1,18 @@
+#[doc = "Register `PERID` reader"]
+pub type R = crate::R<PeridSpec>;
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        write!(f, "{}", self.bits())
+    }
+}
+#[doc = "Peripheral ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`perid::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct PeridSpec;
+impl crate::RegisterSpec for PeridSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`perid::R`](R) reader structure"]
+impl crate::Readable for PeridSpec {}
+#[doc = "`reset()` method sets PERID to value 0x0012_07e1"]
+impl crate::Resettable for PeridSpec {
+    const RESET_VALUE: u32 = 0x0012_07e1;
+}

va108xx/src/spia/rxfifoirqtrg.rs

@@ -0,0 +1,27 @@
+#[doc = "Register `RXFIFOIRQTRG` reader"]
+pub type R = crate::R<RxfifoirqtrgSpec>;
+#[doc = "Register `RXFIFOIRQTRG` writer"]
+pub type W = crate::W<RxfifoirqtrgSpec>;
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        write!(f, "{}", self.bits())
+    }
+}
+impl W {}
+#[doc = "Rx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxfifoirqtrg::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxfifoirqtrg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct RxfifoirqtrgSpec;
+impl crate::RegisterSpec for RxfifoirqtrgSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`rxfifoirqtrg::R`](R) reader structure"]
+impl crate::Readable for RxfifoirqtrgSpec {}
+#[doc = "`write(|w| ..)` method takes [`rxfifoirqtrg::W`](W) writer structure"]
+impl crate::Writable for RxfifoirqtrgSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets RXFIFOIRQTRG to value 0"]
+impl crate::Resettable for RxfifoirqtrgSpec {
+    const RESET_VALUE: u32 = 0;
+}

va108xx/src/spia/state.rs

@@ -0,0 +1,18 @@
+#[doc = "Register `STATE` reader"]
+pub type R = crate::R<StateSpec>;
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        write!(f, "{}", self.bits())
+    }
+}
+#[doc = "Internal STATE of SPI Controller\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`state::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct StateSpec;
+impl crate::RegisterSpec for StateSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`state::R`](R) reader structure"]
+impl crate::Readable for StateSpec {}
+#[doc = "`reset()` method sets STATE to value 0"]
+impl crate::Resettable for StateSpec {
+    const RESET_VALUE: u32 = 0;
+}

va108xx/src/spia/status.rs

@@ -0,0 +1,71 @@
+#[doc = "Register `STATUS` reader"]
+pub type R = crate::R<StatusSpec>;
+#[doc = "Field `TFE` reader - Transmit FIFO empty"]
+pub type TfeR = crate::BitReader;
+#[doc = "Field `TNF` reader - Transmit FIFO not full"]
+pub type TnfR = crate::BitReader;
+#[doc = "Field `RNE` reader - Receive FIFO not empty"]
+pub type RneR = crate::BitReader;
+#[doc = "Field `RFF` reader - Receive FIFO Full"]
+pub type RffR = crate::BitReader;
+#[doc = "Field `BUSY` reader - Busy"]
+pub type BusyR = crate::BitReader;
+#[doc = "Field `RXDATAFIRST` reader - Pending Data is first Byte in BLOCKMODE"]
+pub type RxdatafirstR = crate::BitReader;
+#[doc = "Field `RXTRIGGER` reader - RX FIFO Above Trigger Level"]
+pub type RxtriggerR = crate::BitReader;
+#[doc = "Field `TXTRIGGER` reader - TX FIFO Below Trigger Level"]
+pub type TxtriggerR = crate::BitReader;
+impl R {
+    #[doc = "Bit 0 - Transmit FIFO empty"]
+    #[inline(always)]
+    pub fn tfe(&self) -> TfeR {
+        TfeR::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - Transmit FIFO not full"]
+    #[inline(always)]
+    pub fn tnf(&self) -> TnfR {
+        TnfR::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - Receive FIFO not empty"]
+    #[inline(always)]
+    pub fn rne(&self) -> RneR {
+        RneR::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - Receive FIFO Full"]
+    #[inline(always)]
+    pub fn rff(&self) -> RffR {
+        RffR::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - Busy"]
+    #[inline(always)]
+    pub fn busy(&self) -> BusyR {
+        BusyR::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 5 - Pending Data is first Byte in BLOCKMODE"]
+    #[inline(always)]
+    pub fn rxdatafirst(&self) -> RxdatafirstR {
+        RxdatafirstR::new(((self.bits >> 5) & 1) != 0)
+    }
+    #[doc = "Bit 6 - RX FIFO Above Trigger Level"]
+    #[inline(always)]
+    pub fn rxtrigger(&self) -> RxtriggerR {
+        RxtriggerR::new(((self.bits >> 6) & 1) != 0)
+    }
+    #[doc = "Bit 7 - TX FIFO Below Trigger Level"]
+    #[inline(always)]
+    pub fn txtrigger(&self) -> TxtriggerR {
+        TxtriggerR::new(((self.bits >> 7) & 1) != 0)
+    }
+}
+#[doc = "Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct StatusSpec;
+impl crate::RegisterSpec for StatusSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`status::R`](R) reader structure"]
+impl crate::Readable for StatusSpec {}
+#[doc = "`reset()` method sets STATUS to value 0"]
+impl crate::Resettable for StatusSpec {
+    const RESET_VALUE: u32 = 0;
+}

va108xx/src/spia/txfifoirqtrg.rs

@@ -0,0 +1,27 @@
+#[doc = "Register `TXFIFOIRQTRG` reader"]
+pub type R = crate::R<TxfifoirqtrgSpec>;
+#[doc = "Register `TXFIFOIRQTRG` writer"]
+pub type W = crate::W<TxfifoirqtrgSpec>;
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        write!(f, "{}", self.bits())
+    }
+}
+impl W {}
+#[doc = "Tx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txfifoirqtrg::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txfifoirqtrg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct TxfifoirqtrgSpec;
+impl crate::RegisterSpec for TxfifoirqtrgSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`txfifoirqtrg::R`](R) reader structure"]
+impl crate::Readable for TxfifoirqtrgSpec {}
+#[doc = "`write(|w| ..)` method takes [`txfifoirqtrg::W`](W) writer structure"]
+impl crate::Writable for TxfifoirqtrgSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets TXFIFOIRQTRG to value 0"]
+impl crate::Resettable for TxfifoirqtrgSpec {
+    const RESET_VALUE: u32 = 0;
+}

va108xx/src/sysconfig.rs

@@ -0,0 +1,376 @@
+#[repr(C)]
+#[doc = "Register block"]
+pub struct RegisterBlock {
+    rst_stat: RstStat,
+    rst_cntl_rom: RstCntlRom,
+    rst_cntl_ram: RstCntlRam,
+    rom_prot: RomProt,
+    rom_scrub: RomScrub,
+    ram_scrub: RamScrub,
+    rom_trap_addr: RomTrapAddr,
+    rom_trap_synd: RomTrapSynd,
+    ram_trap_addr: RamTrapAddr,
+    ram_trap_synd: RamTrapSynd,
+    irq_enb: IrqEnb,
+    irq_raw: IrqRaw,
+    irq_end: IrqEnd,
+    irq_clr: IrqClr,
+    ram_sbe: RamSbe,
+    ram_mbe: RamMbe,
+    rom_sbe: RomSbe,
+    rom_mbe: RomMbe,
+    ioconfig_clkdiv0: IoconfigClkdiv0,
+    ioconfig_clkdiv: [IoconfigClkdiv; 7],
+    rom_retries: RomRetries,
+    refresh_config: RefreshConfig,
+    tim_reset: TimReset,
+    tim_clk_enable: TimClkEnable,
+    peripheral_reset: PeripheralReset,
+    peripheral_clk_enable: PeripheralClkEnable,
+    lockup_reset: LockupReset,
+    _reserved27: [u8; 0x0f6c],
+    ef_config: EfConfig,
+    ef_id: EfId,
+    procid: Procid,
+    perid: Perid,
+}
+impl RegisterBlock {
+    #[doc = "0x00 - System Reset Status"]
+    #[inline(always)]
+    pub const fn rst_stat(&self) -> &RstStat {
+        &self.rst_stat
+    }
+    #[doc = "0x04 - ROM Reset Control"]
+    #[inline(always)]
+    pub const fn rst_cntl_rom(&self) -> &RstCntlRom {
+        &self.rst_cntl_rom
+    }
+    #[doc = "0x08 - RAM Reset Control"]
+    #[inline(always)]
+    pub const fn rst_cntl_ram(&self) -> &RstCntlRam {
+        &self.rst_cntl_ram
+    }
+    #[doc = "0x0c - ROM Protection Configuration"]
+    #[inline(always)]
+    pub const fn rom_prot(&self) -> &RomProt {
+        &self.rom_prot
+    }
+    #[doc = "0x10 - ROM Scrub Period Configuration"]
+    #[inline(always)]
+    pub const fn rom_scrub(&self) -> &RomScrub {
+        &self.rom_scrub
+    }
+    #[doc = "0x14 - RAM Scrub Period Configuration"]
+    #[inline(always)]
+    pub const fn ram_scrub(&self) -> &RamScrub {
+        &self.ram_scrub
+    }
+    #[doc = "0x18 - ROM Trap Address"]
+    #[inline(always)]
+    pub const fn rom_trap_addr(&self) -> &RomTrapAddr {
+        &self.rom_trap_addr
+    }
+    #[doc = "0x1c - ROM Trap Syndrome"]
+    #[inline(always)]
+    pub const fn rom_trap_synd(&self) -> &RomTrapSynd {
+        &self.rom_trap_synd
+    }
+    #[doc = "0x20 - RAM Trap Address"]
+    #[inline(always)]
+    pub const fn ram_trap_addr(&self) -> &RamTrapAddr {
+        &self.ram_trap_addr
+    }
+    #[doc = "0x24 - RAM Trap Syndrome"]
+    #[inline(always)]
+    pub const fn ram_trap_synd(&self) -> &RamTrapSynd {
+        &self.ram_trap_synd
+    }
+    #[doc = "0x28 - Enable EDAC Error Interrupt Register"]
+    #[inline(always)]
+    pub const fn irq_enb(&self) -> &IrqEnb {
+        &self.irq_enb
+    }
+    #[doc = "0x2c - Raw EDAC Error Interrupt Status"]
+    #[inline(always)]
+    pub const fn irq_raw(&self) -> &IrqRaw {
+        &self.irq_raw
+    }
+    #[doc = "0x30 - Enabled EDAC Error Interrupt Status"]
+    #[inline(always)]
+    pub const fn irq_end(&self) -> &IrqEnd {
+        &self.irq_end
+    }
+    #[doc = "0x34 - Clear EDAC Error Interrupt Status"]
+    #[inline(always)]
+    pub const fn irq_clr(&self) -> &IrqClr {
+        &self.irq_clr
+    }
+    #[doc = "0x38 - Count of RAM EDAC Single Bit Errors"]
+    #[inline(always)]
+    pub const fn ram_sbe(&self) -> &RamSbe {
+        &self.ram_sbe
+    }
+    #[doc = "0x3c - Count of RAM EDAC Multi Bit Errors"]
+    #[inline(always)]
+    pub const fn ram_mbe(&self) -> &RamMbe {
+        &self.ram_mbe
+    }
+    #[doc = "0x40 - Count of ROM EDAC Single Bit Errors"]
+    #[inline(always)]
+    pub const fn rom_sbe(&self) -> &RomSbe {
+        &self.rom_sbe
+    }
+    #[doc = "0x44 - Count of ROM EDAC Multi Bit Errors"]
+    #[inline(always)]
+    pub const fn rom_mbe(&self) -> &RomMbe {
+        &self.rom_mbe
+    }
+    #[doc = "0x48 - IO Configuration Clock Divider Register"]
+    #[inline(always)]
+    pub const fn ioconfig_clkdiv0(&self) -> &IoconfigClkdiv0 {
+        &self.ioconfig_clkdiv0
+    }
+    #[doc = "0x4c..0x68 - IO Configuration Clock Divider Register"]
+    #[inline(always)]
+    pub const fn ioconfig_clkdiv(&self, n: usize) -> &IoconfigClkdiv {
+        &self.ioconfig_clkdiv[n]
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "0x4c..0x68 - IO Configuration Clock Divider Register"]
+    #[inline(always)]
+    pub fn ioconfig_clkdiv_iter(&self) -> impl Iterator<Item = &IoconfigClkdiv> {
+        self.ioconfig_clkdiv.iter()
+    }
+    #[doc = "0x4c - IO Configuration Clock Divider Register"]
+    #[inline(always)]
+    pub const fn ioconfig_clkdiv1(&self) -> &IoconfigClkdiv {
+        self.ioconfig_clkdiv(0)
+    }
+    #[doc = "0x50 - IO Configuration Clock Divider Register"]
+    #[inline(always)]
+    pub const fn ioconfig_clkdiv2(&self) -> &IoconfigClkdiv {
+        self.ioconfig_clkdiv(1)
+    }
+    #[doc = "0x54 - IO Configuration Clock Divider Register"]
+    #[inline(always)]
+    pub const fn ioconfig_clkdiv3(&self) -> &IoconfigClkdiv {
+        self.ioconfig_clkdiv(2)
+    }
+    #[doc = "0x58 - IO Configuration Clock Divider Register"]
+    #[inline(always)]
+    pub const fn ioconfig_clkdiv4(&self) -> &IoconfigClkdiv {
+        self.ioconfig_clkdiv(3)
+    }
+    #[doc = "0x5c - IO Configuration Clock Divider Register"]
+    #[inline(always)]
+    pub const fn ioconfig_clkdiv5(&self) -> &IoconfigClkdiv {
+        self.ioconfig_clkdiv(4)
+    }
+    #[doc = "0x60 - IO Configuration Clock Divider Register"]
+    #[inline(always)]
+    pub const fn ioconfig_clkdiv6(&self) -> &IoconfigClkdiv {
+        self.ioconfig_clkdiv(5)
+    }
+    #[doc = "0x64 - IO Configuration Clock Divider Register"]
+    #[inline(always)]
+    pub const fn ioconfig_clkdiv7(&self) -> &IoconfigClkdiv {
+        self.ioconfig_clkdiv(6)
+    }
+    #[doc = "0x68 - ROM BOOT Retry count"]
+    #[inline(always)]
+    pub const fn rom_retries(&self) -> &RomRetries {
+        &self.rom_retries
+    }
+    #[doc = "0x6c - Register Refresh Control"]
+    #[inline(always)]
+    pub const fn refresh_config(&self) -> &RefreshConfig {
+        &self.refresh_config
+    }
+    #[doc = "0x70 - TIM Reset Control"]
+    #[inline(always)]
+    pub const fn tim_reset(&self) -> &TimReset {
+        &self.tim_reset
+    }
+    #[doc = "0x74 - TIM Enable Control"]
+    #[inline(always)]
+    pub const fn tim_clk_enable(&self) -> &TimClkEnable {
+        &self.tim_clk_enable
+    }
+    #[doc = "0x78 - Peripheral Reset Control"]
+    #[inline(always)]
+    pub const fn peripheral_reset(&self) -> &PeripheralReset {
+        &self.peripheral_reset
+    }
+    #[doc = "0x7c - Peripheral Enable Control"]
+    #[inline(always)]
+    pub const fn peripheral_clk_enable(&self) -> &PeripheralClkEnable {
+        &self.peripheral_clk_enable
+    }
+    #[doc = "0x80 - Lockup Reset Configuration"]
+    #[inline(always)]
+    pub const fn lockup_reset(&self) -> &LockupReset {
+        &self.lockup_reset
+    }
+    #[doc = "0xff0 - EFuse Config Register"]
+    #[inline(always)]
+    pub const fn ef_config(&self) -> &EfConfig {
+        &self.ef_config
+    }
+    #[doc = "0xff4 - EFuse ID Register"]
+    #[inline(always)]
+    pub const fn ef_id(&self) -> &EfId {
+        &self.ef_id
+    }
+    #[doc = "0xff8 - Processor ID Register"]
+    #[inline(always)]
+    pub const fn procid(&self) -> &Procid {
+        &self.procid
+    }
+    #[doc = "0xffc - Peripheral ID Register"]
+    #[inline(always)]
+    pub const fn perid(&self) -> &Perid {
+        &self.perid
+    }
+}
+#[doc = "RST_STAT (rw) register accessor: System Reset Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rst_stat::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rst_stat::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rst_stat`]
+module"]
+#[doc(alias = "RST_STAT")]
+pub type RstStat = crate::Reg<rst_stat::RstStatSpec>;
+#[doc = "System Reset Status"]
+pub mod rst_stat;
+pub use rst_stat as rst_cntl_rom;
+pub use rst_stat as rst_cntl_ram;
+pub use RstStat as RstCntlRom;
+pub use RstStat as RstCntlRam;
+#[doc = "ROM_PROT (rw) register accessor: ROM Protection Configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rom_prot::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rom_prot::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rom_prot`]
+module"]
+#[doc(alias = "ROM_PROT")]
+pub type RomProt = crate::Reg<rom_prot::RomProtSpec>;
+#[doc = "ROM Protection Configuration"]
+pub mod rom_prot;
+#[doc = "ROM_SCRUB (rw) register accessor: ROM Scrub Period Configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rom_scrub::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rom_scrub::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rom_scrub`]
+module"]
+#[doc(alias = "ROM_SCRUB")]
+pub type RomScrub = crate::Reg<rom_scrub::RomScrubSpec>;
+#[doc = "ROM Scrub Period Configuration"]
+pub mod rom_scrub;
+pub use rom_scrub as ram_scrub;
+pub use RomScrub as RamScrub;
+#[doc = "ROM_TRAP_ADDR (rw) register accessor: ROM Trap Address\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rom_trap_addr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rom_trap_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rom_trap_addr`]
+module"]
+#[doc(alias = "ROM_TRAP_ADDR")]
+pub type RomTrapAddr = crate::Reg<rom_trap_addr::RomTrapAddrSpec>;
+#[doc = "ROM Trap Address"]
+pub mod rom_trap_addr;
+#[doc = "ROM_TRAP_SYND (rw) register accessor: ROM Trap Syndrome\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rom_trap_synd::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rom_trap_synd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rom_trap_synd`]
+module"]
+#[doc(alias = "ROM_TRAP_SYND")]
+pub type RomTrapSynd = crate::Reg<rom_trap_synd::RomTrapSyndSpec>;
+#[doc = "ROM Trap Syndrome"]
+pub mod rom_trap_synd;
+pub use rom_trap_addr as ram_trap_addr;
+pub use rom_trap_synd as ram_trap_synd;
+pub use RomTrapAddr as RamTrapAddr;
+pub use RomTrapSynd as RamTrapSynd;
+#[doc = "IRQ_ENB (rw) register accessor: Enable EDAC Error Interrupt Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_enb::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_enb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_enb`]
+module"]
+#[doc(alias = "IRQ_ENB")]
+pub type IrqEnb = crate::Reg<irq_enb::IrqEnbSpec>;
+#[doc = "Enable EDAC Error Interrupt Register"]
+pub mod irq_enb;
+pub use irq_enb as irq_raw;
+pub use irq_enb as irq_end;
+pub use irq_enb as irq_clr;
+pub use IrqEnb as IrqRaw;
+pub use IrqEnb as IrqEnd;
+pub use IrqEnb as IrqClr;
+#[doc = "RAM_SBE (rw) register accessor: Count of RAM EDAC Single Bit Errors\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ram_sbe::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ram_sbe::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ram_sbe`]
+module"]
+#[doc(alias = "RAM_SBE")]
+pub type RamSbe = crate::Reg<ram_sbe::RamSbeSpec>;
+#[doc = "Count of RAM EDAC Single Bit Errors"]
+pub mod ram_sbe;
+pub use ram_sbe as ram_mbe;
+pub use ram_sbe as rom_sbe;
+pub use ram_sbe as rom_mbe;
+pub use RamSbe as RamMbe;
+pub use RamSbe as RomSbe;
+pub use RamSbe as RomMbe;
+#[doc = "IOCONFIG_CLKDIV0 (r) register accessor: IO Configuration Clock Divider Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ioconfig_clkdiv0::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ioconfig_clkdiv0`]
+module"]
+#[doc(alias = "IOCONFIG_CLKDIV0")]
+pub type IoconfigClkdiv0 = crate::Reg<ioconfig_clkdiv0::IoconfigClkdiv0Spec>;
+#[doc = "IO Configuration Clock Divider Register"]
+pub mod ioconfig_clkdiv0;
+#[doc = "IOCONFIG_CLKDIV (rw) register accessor: IO Configuration Clock Divider Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ioconfig_clkdiv::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ioconfig_clkdiv::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ioconfig_clkdiv`]
+module"]
+#[doc(alias = "IOCONFIG_CLKDIV")]
+pub type IoconfigClkdiv = crate::Reg<ioconfig_clkdiv::IoconfigClkdivSpec>;
+#[doc = "IO Configuration Clock Divider Register"]
+pub mod ioconfig_clkdiv;
+#[doc = "ROM_RETRIES (r) register accessor: ROM BOOT Retry count\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rom_retries::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rom_retries`]
+module"]
+#[doc(alias = "ROM_RETRIES")]
+pub type RomRetries = crate::Reg<rom_retries::RomRetriesSpec>;
+#[doc = "ROM BOOT Retry count"]
+pub mod rom_retries;
+#[doc = "REFRESH_CONFIG (rw) register accessor: Register Refresh Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`refresh_config::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`refresh_config::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@refresh_config`]
+module"]
+#[doc(alias = "REFRESH_CONFIG")]
+pub type RefreshConfig = crate::Reg<refresh_config::RefreshConfigSpec>;
+#[doc = "Register Refresh Control"]
+pub mod refresh_config;
+#[doc = "TIM_RESET (rw) register accessor: TIM Reset Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tim_reset::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tim_reset::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tim_reset`]
+module"]
+#[doc(alias = "TIM_RESET")]
+pub type TimReset = crate::Reg<tim_reset::TimResetSpec>;
+#[doc = "TIM Reset Control"]
+pub mod tim_reset;
+#[doc = "TIM_CLK_ENABLE (rw) register accessor: TIM Enable Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tim_clk_enable::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tim_clk_enable::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tim_clk_enable`]
+module"]
+#[doc(alias = "TIM_CLK_ENABLE")]
+pub type TimClkEnable = crate::Reg<tim_clk_enable::TimClkEnableSpec>;
+#[doc = "TIM Enable Control"]
+pub mod tim_clk_enable;
+#[doc = "PERIPHERAL_RESET (rw) register accessor: Peripheral Reset Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`peripheral_reset::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`peripheral_reset::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@peripheral_reset`]
+module"]
+#[doc(alias = "PERIPHERAL_RESET")]
+pub type PeripheralReset = crate::Reg<peripheral_reset::PeripheralResetSpec>;
+#[doc = "Peripheral Reset Control"]
+pub mod peripheral_reset;
+#[doc = "PERIPHERAL_CLK_ENABLE (rw) register accessor: Peripheral Enable Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`peripheral_clk_enable::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`peripheral_clk_enable::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@peripheral_clk_enable`]
+module"]
+#[doc(alias = "PERIPHERAL_CLK_ENABLE")]
+pub type PeripheralClkEnable = crate::Reg<peripheral_clk_enable::PeripheralClkEnableSpec>;
+#[doc = "Peripheral Enable Control"]
+pub mod peripheral_clk_enable;
+#[doc = "LOCKUP_RESET (rw) register accessor: Lockup Reset Configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lockup_reset::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lockup_reset::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lockup_reset`]
+module"]
+#[doc(alias = "LOCKUP_RESET")]
+pub type LockupReset = crate::Reg<lockup_reset::LockupResetSpec>;
+#[doc = "Lockup Reset Configuration"]
+pub mod lockup_reset;
+#[doc = "EF_CONFIG (r) register accessor: EFuse Config Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ef_config::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ef_config`]
+module"]
+#[doc(alias = "EF_CONFIG")]
+pub type EfConfig = crate::Reg<ef_config::EfConfigSpec>;
+#[doc = "EFuse Config Register"]
+pub mod ef_config;
+#[doc = "EF_ID (r) register accessor: EFuse ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ef_id::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ef_id`]
+module"]
+#[doc(alias = "EF_ID")]
+pub type EfId = crate::Reg<ef_id::EfIdSpec>;
+#[doc = "EFuse ID Register"]
+pub mod ef_id;
+#[doc = "PROCID (r) register accessor: Processor ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`procid::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@procid`]
+module"]
+#[doc(alias = "PROCID")]
+pub type Procid = crate::Reg<procid::ProcidSpec>;
+#[doc = "Processor ID Register"]
+pub mod procid;
+#[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`perid::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`]
+module"]
+#[doc(alias = "PERID")]
+pub type Perid = crate::Reg<perid::PeridSpec>;
+#[doc = "Peripheral ID Register"]
+pub mod perid;

va108xx/src/sysconfig/ef_config.rs

@@ -0,0 +1,18 @@
+#[doc = "Register `EF_CONFIG` reader"]
+pub type R = crate::R<EfConfigSpec>;
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        write!(f, "{}", self.bits())
+    }
+}
+#[doc = "EFuse Config Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ef_config::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct EfConfigSpec;
+impl crate::RegisterSpec for EfConfigSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`ef_config::R`](R) reader structure"]
+impl crate::Readable for EfConfigSpec {}
+#[doc = "`reset()` method sets EF_CONFIG to value 0"]
+impl crate::Resettable for EfConfigSpec {
+    const RESET_VALUE: u32 = 0;
+}

va108xx/src/sysconfig/ef_id.rs

@@ -0,0 +1,18 @@
+#[doc = "Register `EF_ID` reader"]
+pub type R = crate::R<EfIdSpec>;
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        write!(f, "{}", self.bits())
+    }
+}
+#[doc = "EFuse ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ef_id::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct EfIdSpec;
+impl crate::RegisterSpec for EfIdSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`ef_id::R`](R) reader structure"]
+impl crate::Readable for EfIdSpec {}
+#[doc = "`reset()` method sets EF_ID to value 0"]
+impl crate::Resettable for EfIdSpec {
+    const RESET_VALUE: u32 = 0;
+}

va108xx/src/sysconfig/ioconfig_clkdiv.rs

@@ -0,0 +1,27 @@
+#[doc = "Register `IOCONFIG_CLKDIV%s` reader"]
+pub type R = crate::R<IoconfigClkdivSpec>;
+#[doc = "Register `IOCONFIG_CLKDIV%s` writer"]
+pub type W = crate::W<IoconfigClkdivSpec>;
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        write!(f, "{}", self.bits())
+    }
+}
+impl W {}
+#[doc = "IO Configuration Clock Divider Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ioconfig_clkdiv::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ioconfig_clkdiv::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct IoconfigClkdivSpec;
+impl crate::RegisterSpec for IoconfigClkdivSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`ioconfig_clkdiv::R`](R) reader structure"]
+impl crate::Readable for IoconfigClkdivSpec {}
+#[doc = "`write(|w| ..)` method takes [`ioconfig_clkdiv::W`](W) writer structure"]
+impl crate::Writable for IoconfigClkdivSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets IOCONFIG_CLKDIV%s to value 0"]
+impl crate::Resettable for IoconfigClkdivSpec {
+    const RESET_VALUE: u32 = 0;
+}

va108xx/src/sysconfig/ioconfig_clkdiv0.rs

@@ -0,0 +1,18 @@
+#[doc = "Register `IOCONFIG_CLKDIV0` reader"]
+pub type R = crate::R<IoconfigClkdiv0Spec>;
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        write!(f, "{}", self.bits())
+    }
+}
+#[doc = "IO Configuration Clock Divider Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ioconfig_clkdiv0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct IoconfigClkdiv0Spec;
+impl crate::RegisterSpec for IoconfigClkdiv0Spec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`ioconfig_clkdiv0::R`](R) reader structure"]
+impl crate::Readable for IoconfigClkdiv0Spec {}
+#[doc = "`reset()` method sets IOCONFIG_CLKDIV0 to value 0"]
+impl crate::Resettable for IoconfigClkdiv0Spec {
+    const RESET_VALUE: u32 = 0;
+}

va108xx/src/sysconfig/irq_enb.rs

@@ -0,0 +1,85 @@
+#[doc = "Register `IRQ_ENB` reader"]
+pub type R = crate::R<IrqEnbSpec>;
+#[doc = "Register `IRQ_ENB` writer"]
+pub type W = crate::W<IrqEnbSpec>;
+#[doc = "Field `RAMSBE` reader - RAM Single Bit Interrupt"]
+pub type RamsbeR = crate::BitReader;
+#[doc = "Field `RAMSBE` writer - RAM Single Bit Interrupt"]
+pub type RamsbeW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `RAMMBE` reader - RAM Multi Bit Interrupt"]
+pub type RammbeR = crate::BitReader;
+#[doc = "Field `RAMMBE` writer - RAM Multi Bit Interrupt"]
+pub type RammbeW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `ROMSBE` reader - ROM Single Bit Interrupt"]
+pub type RomsbeR = crate::BitReader;
+#[doc = "Field `ROMSBE` writer - ROM Single Bit Interrupt"]
+pub type RomsbeW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `ROMMBE` reader - ROM Multi Bit Interrupt"]
+pub type RommbeR = crate::BitReader;
+#[doc = "Field `ROMMBE` writer - ROM Multi Bit Interrupt"]
+pub type RommbeW<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - RAM Single Bit Interrupt"]
+    #[inline(always)]
+    pub fn ramsbe(&self) -> RamsbeR {
+        RamsbeR::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - RAM Multi Bit Interrupt"]
+    #[inline(always)]
+    pub fn rammbe(&self) -> RammbeR {
+        RammbeR::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - ROM Single Bit Interrupt"]
+    #[inline(always)]
+    pub fn romsbe(&self) -> RomsbeR {
+        RomsbeR::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - ROM Multi Bit Interrupt"]
+    #[inline(always)]
+    pub fn rommbe(&self) -> RommbeR {
+        RommbeR::new(((self.bits >> 3) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - RAM Single Bit Interrupt"]
+    #[inline(always)]
+    #[must_use]
+    pub fn ramsbe(&mut self) -> RamsbeW<IrqEnbSpec> {
+        RamsbeW::new(self, 0)
+    }
+    #[doc = "Bit 1 - RAM Multi Bit Interrupt"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rammbe(&mut self) -> RammbeW<IrqEnbSpec> {
+        RammbeW::new(self, 1)
+    }
+    #[doc = "Bit 2 - ROM Single Bit Interrupt"]
+    #[inline(always)]
+    #[must_use]
+    pub fn romsbe(&mut self) -> RomsbeW<IrqEnbSpec> {
+        RomsbeW::new(self, 2)
+    }
+    #[doc = "Bit 3 - ROM Multi Bit Interrupt"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rommbe(&mut self) -> RommbeW<IrqEnbSpec> {
+        RommbeW::new(self, 3)
+    }
+}
+#[doc = "Enable EDAC Error Interrupt Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_enb::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_enb::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct IrqEnbSpec;
+impl crate::RegisterSpec for IrqEnbSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`irq_enb::R`](R) reader structure"]
+impl crate::Readable for IrqEnbSpec {}
+#[doc = "`write(|w| ..)` method takes [`irq_enb::W`](W) writer structure"]
+impl crate::Writable for IrqEnbSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets IRQ_ENB to value 0"]
+impl crate::Resettable for IrqEnbSpec {
+    const RESET_VALUE: u32 = 0;
+}

va108xx/src/sysconfig/lockup_reset.rs

@@ -0,0 +1,40 @@
+#[doc = "Register `LOCKUP_RESET` reader"]
+pub type R = crate::R<LockupResetSpec>;
+#[doc = "Register `LOCKUP_RESET` writer"]
+pub type W = crate::W<LockupResetSpec>;
+#[doc = "Field `LREN` reader - Lockup Reset Enable Bit"]
+pub type LrenR = crate::BitReader;
+#[doc = "Field `LREN` writer - Lockup Reset Enable Bit"]
+pub type LrenW<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - Lockup Reset Enable Bit"]
+    #[inline(always)]
+    pub fn lren(&self) -> LrenR {
+        LrenR::new((self.bits & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Lockup Reset Enable Bit"]
+    #[inline(always)]
+    #[must_use]
+    pub fn lren(&mut self) -> LrenW<LockupResetSpec> {
+        LrenW::new(self, 0)
+    }
+}
+#[doc = "Lockup Reset Configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lockup_reset::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lockup_reset::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct LockupResetSpec;
+impl crate::RegisterSpec for LockupResetSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`lockup_reset::R`](R) reader structure"]
+impl crate::Readable for LockupResetSpec {}
+#[doc = "`write(|w| ..)` method takes [`lockup_reset::W`](W) writer structure"]
+impl crate::Writable for LockupResetSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets LOCKUP_RESET to value 0x01"]
+impl crate::Resettable for LockupResetSpec {
+    const RESET_VALUE: u32 = 0x01;
+}

va108xx/src/sysconfig/perid.rs

@@ -0,0 +1,18 @@
+#[doc = "Register `PERID` reader"]
+pub type R = crate::R<PeridSpec>;
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        write!(f, "{}", self.bits())
+    }
+}
+#[doc = "Peripheral ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`perid::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct PeridSpec;
+impl crate::RegisterSpec for PeridSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`perid::R`](R) reader structure"]
+impl crate::Readable for PeridSpec {}
+#[doc = "`reset()` method sets PERID to value 0x0080_07e1"]
+impl crate::Resettable for PeridSpec {
+    const RESET_VALUE: u32 = 0x0080_07e1;
+}

va108xx/src/sysconfig/peripheral_clk_enable.rs

@@ -0,0 +1,248 @@
+#[doc = "Register `PERIPHERAL_CLK_ENABLE` reader"]
+pub type R = crate::R<PeripheralClkEnableSpec>;
+#[doc = "Register `PERIPHERAL_CLK_ENABLE` writer"]
+pub type W = crate::W<PeripheralClkEnableSpec>;
+#[doc = "Field `PORTA` reader - Enable PORTA clock"]
+pub type PortaR = crate::BitReader;
+#[doc = "Field `PORTA` writer - Enable PORTA clock"]
+pub type PortaW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `PORTB` reader - Enable PORTB clock"]
+pub type PortbR = crate::BitReader;
+#[doc = "Field `PORTB` writer - Enable PORTB clock"]
+pub type PortbW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SPI_0` reader - Enable SPI\\[0\\]
+clock"]
+pub type Spi0R = crate::BitReader;
+#[doc = "Field `SPI_0` writer - Enable SPI\\[0\\]
+clock"]
+pub type Spi0W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SPI_1` reader - Enable SPI\\[1\\]
+clock"]
+pub type Spi1R = crate::BitReader;
+#[doc = "Field `SPI_1` writer - Enable SPI\\[1\\]
+clock"]
+pub type Spi1W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SPI_2` reader - Enable SPI\\[2\\]
+clock"]
+pub type Spi2R = crate::BitReader;
+#[doc = "Field `SPI_2` writer - Enable SPI\\[2\\]
+clock"]
+pub type Spi2W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `UART_0` reader - Enable UART\\[0\\]
+clock"]
+pub type Uart0R = crate::BitReader;
+#[doc = "Field `UART_0` writer - Enable UART\\[0\\]
+clock"]
+pub type Uart0W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `UART_1` reader - Enable UART\\[1\\]
+clock"]
+pub type Uart1R = crate::BitReader;
+#[doc = "Field `UART_1` writer - Enable UART\\[1\\]
+clock"]
+pub type Uart1W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `I2C_0` reader - Enable I2C\\[0\\]
+clock"]
+pub type I2c0R = crate::BitReader;
+#[doc = "Field `I2C_0` writer - Enable I2C\\[0\\]
+clock"]
+pub type I2c0W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `I2C_1` reader - Enable I2C\\[1\\]
+clock"]
+pub type I2c1R = crate::BitReader;
+#[doc = "Field `I2C_1` writer - Enable I2C\\[1\\]
+clock"]
+pub type I2c1W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `IRQSEL` reader - Enable IRQ selector clock"]
+pub type IrqselR = crate::BitReader;
+#[doc = "Field `IRQSEL` writer - Enable IRQ selector clock"]
+pub type IrqselW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `IOCONFIG` reader - Enable IO Configuration block clock"]
+pub type IoconfigR = crate::BitReader;
+#[doc = "Field `IOCONFIG` writer - Enable IO Configuration block clock"]
+pub type IoconfigW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `UTILITY` reader - Enable utility clock"]
+pub type UtilityR = crate::BitReader;
+#[doc = "Field `UTILITY` writer - Enable utility clock"]
+pub type UtilityW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `GPIO` reader - Enable GPIO clock"]
+pub type GpioR = crate::BitReader;
+#[doc = "Field `GPIO` writer - Enable GPIO clock"]
+pub type GpioW<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - Enable PORTA clock"]
+    #[inline(always)]
+    pub fn porta(&self) -> PortaR {
+        PortaR::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - Enable PORTB clock"]
+    #[inline(always)]
+    pub fn portb(&self) -> PortbR {
+        PortbR::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 4 - Enable SPI\\[0\\]
+clock"]
+    #[inline(always)]
+    pub fn spi_0(&self) -> Spi0R {
+        Spi0R::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 5 - Enable SPI\\[1\\]
+clock"]
+    #[inline(always)]
+    pub fn spi_1(&self) -> Spi1R {
+        Spi1R::new(((self.bits >> 5) & 1) != 0)
+    }
+    #[doc = "Bit 6 - Enable SPI\\[2\\]
+clock"]
+    #[inline(always)]
+    pub fn spi_2(&self) -> Spi2R {
+        Spi2R::new(((self.bits >> 6) & 1) != 0)
+    }
+    #[doc = "Bit 8 - Enable UART\\[0\\]
+clock"]
+    #[inline(always)]
+    pub fn uart_0(&self) -> Uart0R {
+        Uart0R::new(((self.bits >> 8) & 1) != 0)
+    }
+    #[doc = "Bit 9 - Enable UART\\[1\\]
+clock"]
+    #[inline(always)]
+    pub fn uart_1(&self) -> Uart1R {
+        Uart1R::new(((self.bits >> 9) & 1) != 0)
+    }
+    #[doc = "Bit 16 - Enable I2C\\[0\\]
+clock"]
+    #[inline(always)]
+    pub fn i2c_0(&self) -> I2c0R {
+        I2c0R::new(((self.bits >> 16) & 1) != 0)
+    }
+    #[doc = "Bit 17 - Enable I2C\\[1\\]
+clock"]
+    #[inline(always)]
+    pub fn i2c_1(&self) -> I2c1R {
+        I2c1R::new(((self.bits >> 17) & 1) != 0)
+    }
+    #[doc = "Bit 21 - Enable IRQ selector clock"]
+    #[inline(always)]
+    pub fn irqsel(&self) -> IrqselR {
+        IrqselR::new(((self.bits >> 21) & 1) != 0)
+    }
+    #[doc = "Bit 22 - Enable IO Configuration block clock"]
+    #[inline(always)]
+    pub fn ioconfig(&self) -> IoconfigR {
+        IoconfigR::new(((self.bits >> 22) & 1) != 0)
+    }
+    #[doc = "Bit 23 - Enable utility clock"]
+    #[inline(always)]
+    pub fn utility(&self) -> UtilityR {
+        UtilityR::new(((self.bits >> 23) & 1) != 0)
+    }
+    #[doc = "Bit 24 - Enable GPIO clock"]
+    #[inline(always)]
+    pub fn gpio(&self) -> GpioR {
+        GpioR::new(((self.bits >> 24) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Enable PORTA clock"]
+    #[inline(always)]
+    #[must_use]
+    pub fn porta(&mut self) -> PortaW<PeripheralClkEnableSpec> {
+        PortaW::new(self, 0)
+    }
+    #[doc = "Bit 1 - Enable PORTB clock"]
+    #[inline(always)]
+    #[must_use]
+    pub fn portb(&mut self) -> PortbW<PeripheralClkEnableSpec> {
+        PortbW::new(self, 1)
+    }
+    #[doc = "Bit 4 - Enable SPI\\[0\\]
+clock"]
+    #[inline(always)]
+    #[must_use]
+    pub fn spi_0(&mut self) -> Spi0W<PeripheralClkEnableSpec> {
+        Spi0W::new(self, 4)
+    }
+    #[doc = "Bit 5 - Enable SPI\\[1\\]
+clock"]
+    #[inline(always)]
+    #[must_use]
+    pub fn spi_1(&mut self) -> Spi1W<PeripheralClkEnableSpec> {
+        Spi1W::new(self, 5)
+    }
+    #[doc = "Bit 6 - Enable SPI\\[2\\]
+clock"]
+    #[inline(always)]
+    #[must_use]
+    pub fn spi_2(&mut self) -> Spi2W<PeripheralClkEnableSpec> {
+        Spi2W::new(self, 6)
+    }
+    #[doc = "Bit 8 - Enable UART\\[0\\]
+clock"]
+    #[inline(always)]
+    #[must_use]
+    pub fn uart_0(&mut self) -> Uart0W<PeripheralClkEnableSpec> {
+        Uart0W::new(self, 8)
+    }
+    #[doc = "Bit 9 - Enable UART\\[1\\]
+clock"]
+    #[inline(always)]
+    #[must_use]
+    pub fn uart_1(&mut self) -> Uart1W<PeripheralClkEnableSpec> {
+        Uart1W::new(self, 9)
+    }
+    #[doc = "Bit 16 - Enable I2C\\[0\\]
+clock"]
+    #[inline(always)]
+    #[must_use]
+    pub fn i2c_0(&mut self) -> I2c0W<PeripheralClkEnableSpec> {
+        I2c0W::new(self, 16)
+    }
+    #[doc = "Bit 17 - Enable I2C\\[1\\]
+clock"]
+    #[inline(always)]
+    #[must_use]
+    pub fn i2c_1(&mut self) -> I2c1W<PeripheralClkEnableSpec> {
+        I2c1W::new(self, 17)
+    }
+    #[doc = "Bit 21 - Enable IRQ selector clock"]
+    #[inline(always)]
+    #[must_use]
+    pub fn irqsel(&mut self) -> IrqselW<PeripheralClkEnableSpec> {
+        IrqselW::new(self, 21)
+    }
+    #[doc = "Bit 22 - Enable IO Configuration block clock"]
+    #[inline(always)]
+    #[must_use]
+    pub fn ioconfig(&mut self) -> IoconfigW<PeripheralClkEnableSpec> {
+        IoconfigW::new(self, 22)
+    }
+    #[doc = "Bit 23 - Enable utility clock"]
+    #[inline(always)]
+    #[must_use]
+    pub fn utility(&mut self) -> UtilityW<PeripheralClkEnableSpec> {
+        UtilityW::new(self, 23)
+    }
+    #[doc = "Bit 24 - Enable GPIO clock"]
+    #[inline(always)]
+    #[must_use]
+    pub fn gpio(&mut self) -> GpioW<PeripheralClkEnableSpec> {
+        GpioW::new(self, 24)
+    }
+}
+#[doc = "Peripheral Enable Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`peripheral_clk_enable::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`peripheral_clk_enable::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct PeripheralClkEnableSpec;
+impl crate::RegisterSpec for PeripheralClkEnableSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`peripheral_clk_enable::R`](R) reader structure"]
+impl crate::Readable for PeripheralClkEnableSpec {}
+#[doc = "`write(|w| ..)` method takes [`peripheral_clk_enable::W`](W) writer structure"]
+impl crate::Writable for PeripheralClkEnableSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets PERIPHERAL_CLK_ENABLE to value 0"]
+impl crate::Resettable for PeripheralClkEnableSpec {
+    const RESET_VALUE: u32 = 0;
+}

va108xx/src/sysconfig/peripheral_reset.rs

@@ -0,0 +1,220 @@
+#[doc = "Register `PERIPHERAL_RESET` reader"]
+pub type R = crate::R<PeripheralResetSpec>;
+#[doc = "Register `PERIPHERAL_RESET` writer"]
+pub type W = crate::W<PeripheralResetSpec>;
+#[doc = "Field `PORTA` reader - Reset PORTA"]
+pub type PortaR = crate::BitReader;
+#[doc = "Field `PORTA` writer - Reset PORTA"]
+pub type PortaW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `PORTB` reader - Reset PORTB"]
+pub type PortbR = crate::BitReader;
+#[doc = "Field `PORTB` writer - Reset PORTB"]
+pub type PortbW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SPI_0` reader - Reset SPI\\[0\\]"]
+pub type Spi0R = crate::BitReader;
+#[doc = "Field `SPI_0` writer - Reset SPI\\[0\\]"]
+pub type Spi0W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SPI_1` reader - Reset SPI\\[1\\]"]
+pub type Spi1R = crate::BitReader;
+#[doc = "Field `SPI_1` writer - Reset SPI\\[1\\]"]
+pub type Spi1W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SPI_2` reader - Reset SPI\\[2\\]"]
+pub type Spi2R = crate::BitReader;
+#[doc = "Field `SPI_2` writer - Reset SPI\\[2\\]"]
+pub type Spi2W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `UART_0` reader - Reset UART\\[0\\]"]
+pub type Uart0R = crate::BitReader;
+#[doc = "Field `UART_0` writer - Reset UART\\[0\\]"]
+pub type Uart0W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `UART_1` reader - Reset UART\\[1\\]"]
+pub type Uart1R = crate::BitReader;
+#[doc = "Field `UART_1` writer - Reset UART\\[1\\]"]
+pub type Uart1W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `I2C_0` reader - Reset I2C\\[0\\]"]
+pub type I2c0R = crate::BitReader;
+#[doc = "Field `I2C_0` writer - Reset I2C\\[0\\]"]
+pub type I2c0W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `I2C_1` reader - Reset I2C\\[1\\]"]
+pub type I2c1R = crate::BitReader;
+#[doc = "Field `I2C_1` writer - Reset I2C\\[1\\]"]
+pub type I2c1W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `IRQSEL` reader - Reset IRQ selector"]
+pub type IrqselR = crate::BitReader;
+#[doc = "Field `IRQSEL` writer - Reset IRQ selector"]
+pub type IrqselW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `IOCONFIG` reader - Reset IO Configuration block"]
+pub type IoconfigR = crate::BitReader;
+#[doc = "Field `IOCONFIG` writer - Reset IO Configuration block"]
+pub type IoconfigW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `UTILITY` reader - Reset Utility Block"]
+pub type UtilityR = crate::BitReader;
+#[doc = "Field `UTILITY` writer - Reset Utility Block"]
+pub type UtilityW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `GPIO` reader - Reset GPIO"]
+pub type GpioR = crate::BitReader;
+#[doc = "Field `GPIO` writer - Reset GPIO"]
+pub type GpioW<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - Reset PORTA"]
+    #[inline(always)]
+    pub fn porta(&self) -> PortaR {
+        PortaR::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - Reset PORTB"]
+    #[inline(always)]
+    pub fn portb(&self) -> PortbR {
+        PortbR::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 4 - Reset SPI\\[0\\]"]
+    #[inline(always)]
+    pub fn spi_0(&self) -> Spi0R {
+        Spi0R::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 5 - Reset SPI\\[1\\]"]
+    #[inline(always)]
+    pub fn spi_1(&self) -> Spi1R {
+        Spi1R::new(((self.bits >> 5) & 1) != 0)
+    }
+    #[doc = "Bit 6 - Reset SPI\\[2\\]"]
+    #[inline(always)]
+    pub fn spi_2(&self) -> Spi2R {
+        Spi2R::new(((self.bits >> 6) & 1) != 0)
+    }
+    #[doc = "Bit 8 - Reset UART\\[0\\]"]
+    #[inline(always)]
+    pub fn uart_0(&self) -> Uart0R {
+        Uart0R::new(((self.bits >> 8) & 1) != 0)
+    }
+    #[doc = "Bit 9 - Reset UART\\[1\\]"]
+    #[inline(always)]
+    pub fn uart_1(&self) -> Uart1R {
+        Uart1R::new(((self.bits >> 9) & 1) != 0)
+    }
+    #[doc = "Bit 16 - Reset I2C\\[0\\]"]
+    #[inline(always)]
+    pub fn i2c_0(&self) -> I2c0R {
+        I2c0R::new(((self.bits >> 16) & 1) != 0)
+    }
+    #[doc = "Bit 17 - Reset I2C\\[1\\]"]
+    #[inline(always)]
+    pub fn i2c_1(&self) -> I2c1R {
+        I2c1R::new(((self.bits >> 17) & 1) != 0)
+    }
+    #[doc = "Bit 21 - Reset IRQ selector"]
+    #[inline(always)]
+    pub fn irqsel(&self) -> IrqselR {
+        IrqselR::new(((self.bits >> 21) & 1) != 0)
+    }
+    #[doc = "Bit 22 - Reset IO Configuration block"]
+    #[inline(always)]
+    pub fn ioconfig(&self) -> IoconfigR {
+        IoconfigR::new(((self.bits >> 22) & 1) != 0)
+    }
+    #[doc = "Bit 23 - Reset Utility Block"]
+    #[inline(always)]
+    pub fn utility(&self) -> UtilityR {
+        UtilityR::new(((self.bits >> 23) & 1) != 0)
+    }
+    #[doc = "Bit 24 - Reset GPIO"]
+    #[inline(always)]
+    pub fn gpio(&self) -> GpioR {
+        GpioR::new(((self.bits >> 24) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Reset PORTA"]
+    #[inline(always)]
+    #[must_use]
+    pub fn porta(&mut self) -> PortaW<PeripheralResetSpec> {
+        PortaW::new(self, 0)
+    }
+    #[doc = "Bit 1 - Reset PORTB"]
+    #[inline(always)]
+    #[must_use]
+    pub fn portb(&mut self) -> PortbW<PeripheralResetSpec> {
+        PortbW::new(self, 1)
+    }
+    #[doc = "Bit 4 - Reset SPI\\[0\\]"]
+    #[inline(always)]
+    #[must_use]
+    pub fn spi_0(&mut self) -> Spi0W<PeripheralResetSpec> {
+        Spi0W::new(self, 4)
+    }
+    #[doc = "Bit 5 - Reset SPI\\[1\\]"]
+    #[inline(always)]
+    #[must_use]
+    pub fn spi_1(&mut self) -> Spi1W<PeripheralResetSpec> {
+        Spi1W::new(self, 5)
+    }
+    #[doc = "Bit 6 - Reset SPI\\[2\\]"]
+    #[inline(always)]
+    #[must_use]
+    pub fn spi_2(&mut self) -> Spi2W<PeripheralResetSpec> {
+        Spi2W::new(self, 6)
+    }
+    #[doc = "Bit 8 - Reset UART\\[0\\]"]
+    #[inline(always)]
+    #[must_use]
+    pub fn uart_0(&mut self) -> Uart0W<PeripheralResetSpec> {
+        Uart0W::new(self, 8)
+    }
+    #[doc = "Bit 9 - Reset UART\\[1\\]"]
+    #[inline(always)]
+    #[must_use]
+    pub fn uart_1(&mut self) -> Uart1W<PeripheralResetSpec> {
+        Uart1W::new(self, 9)
+    }
+    #[doc = "Bit 16 - Reset I2C\\[0\\]"]
+    #[inline(always)]
+    #[must_use]
+    pub fn i2c_0(&mut self) -> I2c0W<PeripheralResetSpec> {
+        I2c0W::new(self, 16)
+    }
+    #[doc = "Bit 17 - Reset I2C\\[1\\]"]
+    #[inline(always)]
+    #[must_use]
+    pub fn i2c_1(&mut self) -> I2c1W<PeripheralResetSpec> {
+        I2c1W::new(self, 17)
+    }
+    #[doc = "Bit 21 - Reset IRQ selector"]
+    #[inline(always)]
+    #[must_use]
+    pub fn irqsel(&mut self) -> IrqselW<PeripheralResetSpec> {
+        IrqselW::new(self, 21)
+    }
+    #[doc = "Bit 22 - Reset IO Configuration block"]
+    #[inline(always)]
+    #[must_use]
+    pub fn ioconfig(&mut self) -> IoconfigW<PeripheralResetSpec> {
+        IoconfigW::new(self, 22)
+    }
+    #[doc = "Bit 23 - Reset Utility Block"]
+    #[inline(always)]
+    #[must_use]
+    pub fn utility(&mut self) -> UtilityW<PeripheralResetSpec> {
+        UtilityW::new(self, 23)
+    }
+    #[doc = "Bit 24 - Reset GPIO"]
+    #[inline(always)]
+    #[must_use]
+    pub fn gpio(&mut self) -> GpioW<PeripheralResetSpec> {
+        GpioW::new(self, 24)
+    }
+}
+#[doc = "Peripheral Reset Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`peripheral_reset::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`peripheral_reset::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct PeripheralResetSpec;
+impl crate::RegisterSpec for PeripheralResetSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`peripheral_reset::R`](R) reader structure"]
+impl crate::Readable for PeripheralResetSpec {}
+#[doc = "`write(|w| ..)` method takes [`peripheral_reset::W`](W) writer structure"]
+impl crate::Writable for PeripheralResetSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets PERIPHERAL_RESET to value 0xffff_ffff"]
+impl crate::Resettable for PeripheralResetSpec {
+    const RESET_VALUE: u32 = 0xffff_ffff;
+}

va108xx/src/sysconfig/procid.rs

@@ -0,0 +1,18 @@
+#[doc = "Register `PROCID` reader"]
+pub type R = crate::R<ProcidSpec>;
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        write!(f, "{}", self.bits())
+    }
+}
+#[doc = "Processor ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`procid::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct ProcidSpec;
+impl crate::RegisterSpec for ProcidSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`procid::R`](R) reader structure"]
+impl crate::Readable for ProcidSpec {}
+#[doc = "`reset()` method sets PROCID to value 0x0400_17e3"]
+impl crate::Resettable for ProcidSpec {
+    const RESET_VALUE: u32 = 0x0400_17e3;
+}

va108xx/src/sysconfig/ram_sbe.rs

@@ -0,0 +1,27 @@
+#[doc = "Register `RAM_SBE` reader"]
+pub type R = crate::R<RamSbeSpec>;
+#[doc = "Register `RAM_SBE` writer"]
+pub type W = crate::W<RamSbeSpec>;
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        write!(f, "{}", self.bits())
+    }
+}
+impl W {}
+#[doc = "Count of RAM EDAC Single Bit Errors\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ram_sbe::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ram_sbe::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct RamSbeSpec;
+impl crate::RegisterSpec for RamSbeSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`ram_sbe::R`](R) reader structure"]
+impl crate::Readable for RamSbeSpec {}
+#[doc = "`write(|w| ..)` method takes [`ram_sbe::W`](W) writer structure"]
+impl crate::Writable for RamSbeSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets RAM_SBE to value 0"]
+impl crate::Resettable for RamSbeSpec {
+    const RESET_VALUE: u32 = 0;
+}

va108xx/src/sysconfig/refresh_config.rs

@@ -0,0 +1,27 @@
+#[doc = "Register `REFRESH_CONFIG` reader"]
+pub type R = crate::R<RefreshConfigSpec>;
+#[doc = "Register `REFRESH_CONFIG` writer"]
+pub type W = crate::W<RefreshConfigSpec>;
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        write!(f, "{}", self.bits())
+    }
+}
+impl W {}
+#[doc = "Register Refresh Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`refresh_config::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`refresh_config::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct RefreshConfigSpec;
+impl crate::RegisterSpec for RefreshConfigSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`refresh_config::R`](R) reader structure"]
+impl crate::Readable for RefreshConfigSpec {}
+#[doc = "`write(|w| ..)` method takes [`refresh_config::W`](W) writer structure"]
+impl crate::Writable for RefreshConfigSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets REFRESH_CONFIG to value 0"]
+impl crate::Resettable for RefreshConfigSpec {
+    const RESET_VALUE: u32 = 0;
+}

va108xx/src/sysconfig/rom_prot.rs

@@ -0,0 +1,40 @@
+#[doc = "Register `ROM_PROT` reader"]
+pub type R = crate::R<RomProtSpec>;
+#[doc = "Register `ROM_PROT` writer"]
+pub type W = crate::W<RomProtSpec>;
+#[doc = "Field `WREN` reader - ROM Write Enable Bit"]
+pub type WrenR = crate::BitReader;
+#[doc = "Field `WREN` writer - ROM Write Enable Bit"]
+pub type WrenW<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - ROM Write Enable Bit"]
+    #[inline(always)]
+    pub fn wren(&self) -> WrenR {
+        WrenR::new((self.bits & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - ROM Write Enable Bit"]
+    #[inline(always)]
+    #[must_use]
+    pub fn wren(&mut self) -> WrenW<RomProtSpec> {
+        WrenW::new(self, 0)
+    }
+}
+#[doc = "ROM Protection Configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rom_prot::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rom_prot::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct RomProtSpec;
+impl crate::RegisterSpec for RomProtSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`rom_prot::R`](R) reader structure"]
+impl crate::Readable for RomProtSpec {}
+#[doc = "`write(|w| ..)` method takes [`rom_prot::W`](W) writer structure"]
+impl crate::Writable for RomProtSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets ROM_PROT to value 0x01"]
+impl crate::Resettable for RomProtSpec {
+    const RESET_VALUE: u32 = 0x01;
+}

va108xx/src/sysconfig/rom_retries.rs

@@ -0,0 +1,18 @@
+#[doc = "Register `ROM_RETRIES` reader"]
+pub type R = crate::R<RomRetriesSpec>;
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        write!(f, "{}", self.bits())
+    }
+}
+#[doc = "ROM BOOT Retry count\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rom_retries::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct RomRetriesSpec;
+impl crate::RegisterSpec for RomRetriesSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`rom_retries::R`](R) reader structure"]
+impl crate::Readable for RomRetriesSpec {}
+#[doc = "`reset()` method sets ROM_RETRIES to value 0"]
+impl crate::Resettable for RomRetriesSpec {
+    const RESET_VALUE: u32 = 0;
+}

va108xx/src/sysconfig/rom_scrub.rs

@@ -0,0 +1,48 @@
+#[doc = "Register `ROM_SCRUB` reader"]
+pub type R = crate::R<RomScrubSpec>;
+#[doc = "Register `ROM_SCRUB` writer"]
+pub type W = crate::W<RomScrubSpec>;
+#[doc = "Field `VALUE` reader - Counter divide value"]
+pub type ValueR = crate::FieldReader<u32>;
+#[doc = "Field `VALUE` writer - Counter divide value"]
+pub type ValueW<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
+#[doc = "Field `RESET` writer - Reset Counter"]
+pub type ResetW<'a, REG> = crate::BitWriter1C<'a, REG>;
+impl R {
+    #[doc = "Bits 0:23 - Counter divide value"]
+    #[inline(always)]
+    pub fn value(&self) -> ValueR {
+        ValueR::new(self.bits & 0x00ff_ffff)
+    }
+}
+impl W {
+    #[doc = "Bits 0:23 - Counter divide value"]
+    #[inline(always)]
+    #[must_use]
+    pub fn value(&mut self) -> ValueW<RomScrubSpec> {
+        ValueW::new(self, 0)
+    }
+    #[doc = "Bit 31 - Reset Counter"]
+    #[inline(always)]
+    #[must_use]
+    pub fn reset(&mut self) -> ResetW<RomScrubSpec> {
+        ResetW::new(self, 31)
+    }
+}
+#[doc = "ROM Scrub Period Configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rom_scrub::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rom_scrub::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct RomScrubSpec;
+impl crate::RegisterSpec for RomScrubSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`rom_scrub::R`](R) reader structure"]
+impl crate::Readable for RomScrubSpec {}
+#[doc = "`write(|w| ..)` method takes [`rom_scrub::W`](W) writer structure"]
+impl crate::Writable for RomScrubSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x8000_0000;
+}
+#[doc = "`reset()` method sets ROM_SCRUB to value 0"]
+impl crate::Resettable for RomScrubSpec {
+    const RESET_VALUE: u32 = 0;
+}

va108xx/src/sysconfig/rom_trap_addr.rs

@@ -0,0 +1,55 @@
+#[doc = "Register `ROM_TRAP_ADDR` reader"]
+pub type R = crate::R<RomTrapAddrSpec>;
+#[doc = "Register `ROM_TRAP_ADDR` writer"]
+pub type W = crate::W<RomTrapAddrSpec>;
+#[doc = "Field `ADDR` reader - Trap Address Match Bits"]
+pub type AddrR = crate::FieldReader<u16>;
+#[doc = "Field `ADDR` writer - Trap Address Match Bits"]
+pub type AddrW<'a, REG> = crate::FieldWriter<'a, REG, 14, u16>;
+#[doc = "Field `ENABLE` reader - Trap Enable Bit"]
+pub type EnableR = crate::BitReader;
+#[doc = "Field `ENABLE` writer - Trap Enable Bit"]
+pub type EnableW<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bits 2:15 - Trap Address Match Bits"]
+    #[inline(always)]
+    pub fn addr(&self) -> AddrR {
+        AddrR::new(((self.bits >> 2) & 0x3fff) as u16)
+    }
+    #[doc = "Bit 31 - Trap Enable Bit"]
+    #[inline(always)]
+    pub fn enable(&self) -> EnableR {
+        EnableR::new(((self.bits >> 31) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bits 2:15 - Trap Address Match Bits"]
+    #[inline(always)]
+    #[must_use]
+    pub fn addr(&mut self) -> AddrW<RomTrapAddrSpec> {
+        AddrW::new(self, 2)
+    }
+    #[doc = "Bit 31 - Trap Enable Bit"]
+    #[inline(always)]
+    #[must_use]
+    pub fn enable(&mut self) -> EnableW<RomTrapAddrSpec> {
+        EnableW::new(self, 31)
+    }
+}
+#[doc = "ROM Trap Address\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rom_trap_addr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rom_trap_addr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct RomTrapAddrSpec;
+impl crate::RegisterSpec for RomTrapAddrSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`rom_trap_addr::R`](R) reader structure"]
+impl crate::Readable for RomTrapAddrSpec {}
+#[doc = "`write(|w| ..)` method takes [`rom_trap_addr::W`](W) writer structure"]
+impl crate::Writable for RomTrapAddrSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets ROM_TRAP_ADDR to value 0"]
+impl crate::Resettable for RomTrapAddrSpec {
+    const RESET_VALUE: u32 = 0;
+}

va108xx/src/sysconfig/rom_trap_synd.rs

@@ -0,0 +1,40 @@
+#[doc = "Register `ROM_TRAP_SYND` reader"]
+pub type R = crate::R<RomTrapSyndSpec>;
+#[doc = "Register `ROM_TRAP_SYND` writer"]
+pub type W = crate::W<RomTrapSyndSpec>;
+#[doc = "Field `SYND` reader - Trap Syndrom Bits"]
+pub type SyndR = crate::FieldReader<u32>;
+#[doc = "Field `SYND` writer - Trap Syndrom Bits"]
+pub type SyndW<'a, REG> = crate::FieldWriter<'a, REG, 20, u32>;
+impl R {
+    #[doc = "Bits 0:19 - Trap Syndrom Bits"]
+    #[inline(always)]
+    pub fn synd(&self) -> SyndR {
+        SyndR::new(self.bits & 0x000f_ffff)
+    }
+}
+impl W {
+    #[doc = "Bits 0:19 - Trap Syndrom Bits"]
+    #[inline(always)]
+    #[must_use]
+    pub fn synd(&mut self) -> SyndW<RomTrapSyndSpec> {
+        SyndW::new(self, 0)
+    }
+}
+#[doc = "ROM Trap Syndrome\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rom_trap_synd::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rom_trap_synd::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct RomTrapSyndSpec;
+impl crate::RegisterSpec for RomTrapSyndSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`rom_trap_synd::R`](R) reader structure"]
+impl crate::Readable for RomTrapSyndSpec {}
+#[doc = "`write(|w| ..)` method takes [`rom_trap_synd::W`](W) writer structure"]
+impl crate::Writable for RomTrapSyndSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets ROM_TRAP_SYND to value 0"]
+impl crate::Resettable for RomTrapSyndSpec {
+    const RESET_VALUE: u32 = 0;
+}

va108xx/src/sysconfig/rst_stat.rs

@@ -0,0 +1,115 @@
+#[doc = "Register `RST_STAT` reader"]
+pub type R = crate::R<RstStatSpec>;
+#[doc = "Register `RST_STAT` writer"]
+pub type W = crate::W<RstStatSpec>;
+#[doc = "Field `POR` reader - Power On Reset Status"]
+pub type PorR = crate::BitReader;
+#[doc = "Field `POR` writer - Power On Reset Status"]
+pub type PorW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `EXTRST` reader - External Reset Status"]
+pub type ExtrstR = crate::BitReader;
+#[doc = "Field `EXTRST` writer - External Reset Status"]
+pub type ExtrstW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SYSRSTREQ` reader - SYSRESETREQ Reset Status"]
+pub type SysrstreqR = crate::BitReader;
+#[doc = "Field `SYSRSTREQ` writer - SYSRESETREQ Reset Status"]
+pub type SysrstreqW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `LOOKUP` reader - LOOKUP Reset Status"]
+pub type LookupR = crate::BitReader;
+#[doc = "Field `LOOKUP` writer - LOOKUP Reset Status"]
+pub type LookupW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `WATCHDOG` reader - WATCHDOG Reset Status"]
+pub type WatchdogR = crate::BitReader;
+#[doc = "Field `WATCHDOG` writer - WATCHDOG Reset Status"]
+pub type WatchdogW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `MEMERR` reader - Memory Error Reset Status"]
+pub type MemerrR = crate::BitReader;
+#[doc = "Field `MEMERR` writer - Memory Error Reset Status"]
+pub type MemerrW<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - Power On Reset Status"]
+    #[inline(always)]
+    pub fn por(&self) -> PorR {
+        PorR::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - External Reset Status"]
+    #[inline(always)]
+    pub fn extrst(&self) -> ExtrstR {
+        ExtrstR::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - SYSRESETREQ Reset Status"]
+    #[inline(always)]
+    pub fn sysrstreq(&self) -> SysrstreqR {
+        SysrstreqR::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - LOOKUP Reset Status"]
+    #[inline(always)]
+    pub fn lookup(&self) -> LookupR {
+        LookupR::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - WATCHDOG Reset Status"]
+    #[inline(always)]
+    pub fn watchdog(&self) -> WatchdogR {
+        WatchdogR::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 5 - Memory Error Reset Status"]
+    #[inline(always)]
+    pub fn memerr(&self) -> MemerrR {
+        MemerrR::new(((self.bits >> 5) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Power On Reset Status"]
+    #[inline(always)]
+    #[must_use]
+    pub fn por(&mut self) -> PorW<RstStatSpec> {
+        PorW::new(self, 0)
+    }
+    #[doc = "Bit 1 - External Reset Status"]
+    #[inline(always)]
+    #[must_use]
+    pub fn extrst(&mut self) -> ExtrstW<RstStatSpec> {
+        ExtrstW::new(self, 1)
+    }
+    #[doc = "Bit 2 - SYSRESETREQ Reset Status"]
+    #[inline(always)]
+    #[must_use]
+    pub fn sysrstreq(&mut self) -> SysrstreqW<RstStatSpec> {
+        SysrstreqW::new(self, 2)
+    }
+    #[doc = "Bit 3 - LOOKUP Reset Status"]
+    #[inline(always)]
+    #[must_use]
+    pub fn lookup(&mut self) -> LookupW<RstStatSpec> {
+        LookupW::new(self, 3)
+    }
+    #[doc = "Bit 4 - WATCHDOG Reset Status"]
+    #[inline(always)]
+    #[must_use]
+    pub fn watchdog(&mut self) -> WatchdogW<RstStatSpec> {
+        WatchdogW::new(self, 4)
+    }
+    #[doc = "Bit 5 - Memory Error Reset Status"]
+    #[inline(always)]
+    #[must_use]
+    pub fn memerr(&mut self) -> MemerrW<RstStatSpec> {
+        MemerrW::new(self, 5)
+    }
+}
+#[doc = "System Reset Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rst_stat::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rst_stat::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct RstStatSpec;
+impl crate::RegisterSpec for RstStatSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`rst_stat::R`](R) reader structure"]
+impl crate::Readable for RstStatSpec {}
+#[doc = "`write(|w| ..)` method takes [`rst_stat::W`](W) writer structure"]
+impl crate::Writable for RstStatSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets RST_STAT to value 0x01"]
+impl crate::Resettable for RstStatSpec {
+    const RESET_VALUE: u32 = 0x01;
+}

va108xx/src/sysconfig/tim_clk_enable.rs

@@ -0,0 +1,27 @@
+#[doc = "Register `TIM_CLK_ENABLE` reader"]
+pub type R = crate::R<TimClkEnableSpec>;
+#[doc = "Register `TIM_CLK_ENABLE` writer"]
+pub type W = crate::W<TimClkEnableSpec>;
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        write!(f, "{}", self.bits())
+    }
+}
+impl W {}
+#[doc = "TIM Enable Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tim_clk_enable::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tim_clk_enable::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct TimClkEnableSpec;
+impl crate::RegisterSpec for TimClkEnableSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`tim_clk_enable::R`](R) reader structure"]
+impl crate::Readable for TimClkEnableSpec {}
+#[doc = "`write(|w| ..)` method takes [`tim_clk_enable::W`](W) writer structure"]
+impl crate::Writable for TimClkEnableSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets TIM_CLK_ENABLE to value 0"]
+impl crate::Resettable for TimClkEnableSpec {
+    const RESET_VALUE: u32 = 0;
+}

va108xx/src/sysconfig/tim_reset.rs

@@ -0,0 +1,27 @@
+#[doc = "Register `TIM_RESET` reader"]
+pub type R = crate::R<TimResetSpec>;
+#[doc = "Register `TIM_RESET` writer"]
+pub type W = crate::W<TimResetSpec>;
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        write!(f, "{}", self.bits())
+    }
+}
+impl W {}
+#[doc = "TIM Reset Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tim_reset::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tim_reset::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct TimResetSpec;
+impl crate::RegisterSpec for TimResetSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`tim_reset::R`](R) reader structure"]
+impl crate::Readable for TimResetSpec {}
+#[doc = "`write(|w| ..)` method takes [`tim_reset::W`](W) writer structure"]
+impl crate::Writable for TimResetSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets TIM_RESET to value 0xffff_ffff"]
+impl crate::Resettable for TimResetSpec {
+    const RESET_VALUE: u32 = 0xffff_ffff;
+}

va108xx/src/tim0.rs

@@ -0,0 +1,142 @@
+#[repr(C)]
+#[doc = "Register block"]
+pub struct RegisterBlock {
+    ctrl: Ctrl,
+    rst_value: RstValue,
+    cnt_value: CntValue,
+    enable: Enable,
+    csd_ctrl: CsdCtrl,
+    cascade0: Cascade0,
+    cascade1: Cascade1,
+    cascade2: Cascade2,
+    _reserved_8_pwm_value: [u8; 0x04],
+    pwmb_value: PwmbValue,
+    _reserved10: [u8; 0x0fd4],
+    perid: Perid,
+}
+impl RegisterBlock {
+    #[doc = "0x00 - Control Register"]
+    #[inline(always)]
+    pub const fn ctrl(&self) -> &Ctrl {
+        &self.ctrl
+    }
+    #[doc = "0x04 - The value that counter start from after reaching 0."]
+    #[inline(always)]
+    pub const fn rst_value(&self) -> &RstValue {
+        &self.rst_value
+    }
+    #[doc = "0x08 - The current value of the counter"]
+    #[inline(always)]
+    pub const fn cnt_value(&self) -> &CntValue {
+        &self.cnt_value
+    }
+    #[doc = "0x0c - Alternate access to the Counter ENABLE bit in the CTRL Register"]
+    #[inline(always)]
+    pub const fn enable(&self) -> &Enable {
+        &self.enable
+    }
+    #[doc = "0x10 - The Cascade Control Register. Controls the counter external enable signals"]
+    #[inline(always)]
+    pub const fn csd_ctrl(&self) -> &CsdCtrl {
+        &self.csd_ctrl
+    }
+    #[doc = "0x14 - Cascade Enable Selection"]
+    #[inline(always)]
+    pub const fn cascade0(&self) -> &Cascade0 {
+        &self.cascade0
+    }
+    #[doc = "0x18 - Cascade Enable Selection"]
+    #[inline(always)]
+    pub const fn cascade1(&self) -> &Cascade1 {
+        &self.cascade1
+    }
+    #[doc = "0x1c - Cascade Enable Selection"]
+    #[inline(always)]
+    pub const fn cascade2(&self) -> &Cascade2 {
+        &self.cascade2
+    }
+    #[doc = "0x20 - The Pulse Width Modulation ValueA"]
+    #[inline(always)]
+    pub const fn pwma_value(&self) -> &PwmaValue {
+        unsafe { &*(self as *const Self).cast::<u8>().add(32).cast() }
+    }
+    #[doc = "0x20 - The Pulse Width Modulation Value"]
+    #[inline(always)]
+    pub const fn pwm_value(&self) -> &PwmValue {
+        unsafe { &*(self as *const Self).cast::<u8>().add(32).cast() }
+    }
+    #[doc = "0x24 - The Pulse Width Modulation ValueB"]
+    #[inline(always)]
+    pub const fn pwmb_value(&self) -> &PwmbValue {
+        &self.pwmb_value
+    }
+    #[doc = "0xffc - Peripheral ID Register"]
+    #[inline(always)]
+    pub const fn perid(&self) -> &Perid {
+        &self.perid
+    }
+}
+#[doc = "CTRL (rw) register accessor: Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl`]
+module"]
+#[doc(alias = "CTRL")]
+pub type Ctrl = crate::Reg<ctrl::CtrlSpec>;
+#[doc = "Control Register"]
+pub mod ctrl;
+#[doc = "RST_VALUE (rw) register accessor: The value that counter start from after reaching 0.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rst_value::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rst_value::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rst_value`]
+module"]
+#[doc(alias = "RST_VALUE")]
+pub type RstValue = crate::Reg<rst_value::RstValueSpec>;
+#[doc = "The value that counter start from after reaching 0."]
+pub mod rst_value;
+#[doc = "CNT_VALUE (rw) register accessor: The current value of the counter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cnt_value::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cnt_value::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cnt_value`]
+module"]
+#[doc(alias = "CNT_VALUE")]
+pub type CntValue = crate::Reg<cnt_value::CntValueSpec>;
+#[doc = "The current value of the counter"]
+pub mod cnt_value;
+#[doc = "ENABLE (rw) register accessor: Alternate access to the Counter ENABLE bit in the CTRL Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enable`]
+module"]
+#[doc(alias = "ENABLE")]
+pub type Enable = crate::Reg<enable::EnableSpec>;
+#[doc = "Alternate access to the Counter ENABLE bit in the CTRL Register"]
+pub mod enable;
+#[doc = "CSD_CTRL (rw) register accessor: The Cascade Control Register. Controls the counter external enable signals\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`csd_ctrl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`csd_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@csd_ctrl`]
+module"]
+#[doc(alias = "CSD_CTRL")]
+pub type CsdCtrl = crate::Reg<csd_ctrl::CsdCtrlSpec>;
+#[doc = "The Cascade Control Register. Controls the counter external enable signals"]
+pub mod csd_ctrl;
+#[doc = "CASCADE0 (rw) register accessor: Cascade Enable Selection\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cascade0::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cascade0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cascade0`]
+module"]
+#[doc(alias = "CASCADE0")]
+pub type Cascade0 = crate::Reg<cascade0::Cascade0Spec>;
+#[doc = "Cascade Enable Selection"]
+pub mod cascade0;
+pub use cascade0 as cascade1;
+pub use cascade0 as cascade2;
+pub use Cascade0 as Cascade1;
+pub use Cascade0 as Cascade2;
+#[doc = "PWM_VALUE (rw) register accessor: The Pulse Width Modulation Value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pwm_value::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pwm_value::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_value`]
+module"]
+#[doc(alias = "PWM_VALUE")]
+pub type PwmValue = crate::Reg<pwm_value::PwmValueSpec>;
+#[doc = "The Pulse Width Modulation Value"]
+pub mod pwm_value;
+#[doc = "PWMA_VALUE (rw) register accessor: The Pulse Width Modulation ValueA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pwma_value::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pwma_value::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwma_value`]
+module"]
+#[doc(alias = "PWMA_VALUE")]
+pub type PwmaValue = crate::Reg<pwma_value::PwmaValueSpec>;
+#[doc = "The Pulse Width Modulation ValueA"]
+pub mod pwma_value;
+#[doc = "PWMB_VALUE (rw) register accessor: The Pulse Width Modulation ValueB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pwmb_value::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pwmb_value::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwmb_value`]
+module"]
+#[doc(alias = "PWMB_VALUE")]
+pub type PwmbValue = crate::Reg<pwmb_value::PwmbValueSpec>;
+#[doc = "The Pulse Width Modulation ValueB"]
+pub mod pwmb_value;
+#[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`perid::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`]
+module"]
+#[doc(alias = "PERID")]
+pub type Perid = crate::Reg<perid::PeridSpec>;
+#[doc = "Peripheral ID Register"]
+pub mod perid;

va108xx/src/tim0/cascade0.rs

@@ -0,0 +1,40 @@
+#[doc = "Register `CASCADE0` reader"]
+pub type R = crate::R<Cascade0Spec>;
+#[doc = "Register `CASCADE0` writer"]
+pub type W = crate::W<Cascade0Spec>;
+#[doc = "Field `CASSEL` reader - Cascade Selection"]
+pub type CasselR = crate::FieldReader;
+#[doc = "Field `CASSEL` writer - Cascade Selection"]
+pub type CasselW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
+impl R {
+    #[doc = "Bits 0:7 - Cascade Selection"]
+    #[inline(always)]
+    pub fn cassel(&self) -> CasselR {
+        CasselR::new((self.bits & 0xff) as u8)
+    }
+}
+impl W {
+    #[doc = "Bits 0:7 - Cascade Selection"]
+    #[inline(always)]
+    #[must_use]
+    pub fn cassel(&mut self) -> CasselW<Cascade0Spec> {
+        CasselW::new(self, 0)
+    }
+}
+#[doc = "Cascade Enable Selection\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cascade0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cascade0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct Cascade0Spec;
+impl crate::RegisterSpec for Cascade0Spec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`cascade0::R`](R) reader structure"]
+impl crate::Readable for Cascade0Spec {}
+#[doc = "`write(|w| ..)` method takes [`cascade0::W`](W) writer structure"]
+impl crate::Writable for Cascade0Spec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CASCADE0 to value 0"]
+impl crate::Resettable for Cascade0Spec {
+    const RESET_VALUE: u32 = 0;
+}

va108xx/src/tim0/cnt_value.rs

@@ -0,0 +1,27 @@
+#[doc = "Register `CNT_VALUE` reader"]
+pub type R = crate::R<CntValueSpec>;
+#[doc = "Register `CNT_VALUE` writer"]
+pub type W = crate::W<CntValueSpec>;
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        write!(f, "{}", self.bits())
+    }
+}
+impl W {}
+#[doc = "The current value of the counter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cnt_value::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cnt_value::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CntValueSpec;
+impl crate::RegisterSpec for CntValueSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`cnt_value::R`](R) reader structure"]
+impl crate::Readable for CntValueSpec {}
+#[doc = "`write(|w| ..)` method takes [`cnt_value::W`](W) writer structure"]
+impl crate::Writable for CntValueSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CNT_VALUE to value 0"]
+impl crate::Resettable for CntValueSpec {
+    const RESET_VALUE: u32 = 0;
+}

va108xx/src/tim0/csd_ctrl.rs

@@ -0,0 +1,190 @@
+#[doc = "Register `CSD_CTRL` reader"]
+pub type R = crate::R<CsdCtrlSpec>;
+#[doc = "Register `CSD_CTRL` writer"]
+pub type W = crate::W<CsdCtrlSpec>;
+#[doc = "Field `CSDEN0` reader - Cascade 0 Enable"]
+pub type Csden0R = crate::BitReader;
+#[doc = "Field `CSDEN0` writer - Cascade 0 Enable"]
+pub type Csden0W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CSDINV0` reader - Cascade 0 Invert"]
+pub type Csdinv0R = crate::BitReader;
+#[doc = "Field `CSDINV0` writer - Cascade 0 Invert"]
+pub type Csdinv0W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CSDEN1` reader - Cascade 1 Enable"]
+pub type Csden1R = crate::BitReader;
+#[doc = "Field `CSDEN1` writer - Cascade 1 Enable"]
+pub type Csden1W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CSDINV1` reader - Cascade 1 Invert"]
+pub type Csdinv1R = crate::BitReader;
+#[doc = "Field `CSDINV1` writer - Cascade 1 Invert"]
+pub type Csdinv1W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `DCASOP` reader - Dual Cascade Operation (0:AND, 1:OR)"]
+pub type DcasopR = crate::BitReader;
+#[doc = "Field `DCASOP` writer - Dual Cascade Operation (0:AND, 1:OR)"]
+pub type DcasopW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CSDTRG0` reader - Cascade 0 Enabled as Trigger"]
+pub type Csdtrg0R = crate::BitReader;
+#[doc = "Field `CSDTRG0` writer - Cascade 0 Enabled as Trigger"]
+pub type Csdtrg0W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CSDTRG1` reader - Cascade 1 Enabled as Trigger"]
+pub type Csdtrg1R = crate::BitReader;
+#[doc = "Field `CSDTRG1` writer - Cascade 1 Enabled as Trigger"]
+pub type Csdtrg1W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CSDEN2` reader - Cascade 2 Enable"]
+pub type Csden2R = crate::BitReader;
+#[doc = "Field `CSDEN2` writer - Cascade 2 Enable"]
+pub type Csden2W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CSDINV2` reader - Cascade 2 Invert"]
+pub type Csdinv2R = crate::BitReader;
+#[doc = "Field `CSDINV2` writer - Cascade 2 Invert"]
+pub type Csdinv2W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CSDTRG2` reader - Cascade 2 Enabled as Trigger"]
+pub type Csdtrg2R = crate::BitReader;
+#[doc = "Field `CSDTRG2` writer - Cascade 2 Enabled as Trigger"]
+pub type Csdtrg2W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CSDXXX2` reader - Cascade 2 test mode"]
+pub type Csdxxx2R = crate::BitReader;
+#[doc = "Field `CSDXXX2` writer - Cascade 2 test mode"]
+pub type Csdxxx2W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - Cascade 0 Enable"]
+    #[inline(always)]
+    pub fn csden0(&self) -> Csden0R {
+        Csden0R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - Cascade 0 Invert"]
+    #[inline(always)]
+    pub fn csdinv0(&self) -> Csdinv0R {
+        Csdinv0R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - Cascade 1 Enable"]
+    #[inline(always)]
+    pub fn csden1(&self) -> Csden1R {
+        Csden1R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - Cascade 1 Invert"]
+    #[inline(always)]
+    pub fn csdinv1(&self) -> Csdinv1R {
+        Csdinv1R::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - Dual Cascade Operation (0:AND, 1:OR)"]
+    #[inline(always)]
+    pub fn dcasop(&self) -> DcasopR {
+        DcasopR::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 6 - Cascade 0 Enabled as Trigger"]
+    #[inline(always)]
+    pub fn csdtrg0(&self) -> Csdtrg0R {
+        Csdtrg0R::new(((self.bits >> 6) & 1) != 0)
+    }
+    #[doc = "Bit 7 - Cascade 1 Enabled as Trigger"]
+    #[inline(always)]
+    pub fn csdtrg1(&self) -> Csdtrg1R {
+        Csdtrg1R::new(((self.bits >> 7) & 1) != 0)
+    }
+    #[doc = "Bit 8 - Cascade 2 Enable"]
+    #[inline(always)]
+    pub fn csden2(&self) -> Csden2R {
+        Csden2R::new(((self.bits >> 8) & 1) != 0)
+    }
+    #[doc = "Bit 9 - Cascade 2 Invert"]
+    #[inline(always)]
+    pub fn csdinv2(&self) -> Csdinv2R {
+        Csdinv2R::new(((self.bits >> 9) & 1) != 0)
+    }
+    #[doc = "Bit 10 - Cascade 2 Enabled as Trigger"]
+    #[inline(always)]
+    pub fn csdtrg2(&self) -> Csdtrg2R {
+        Csdtrg2R::new(((self.bits >> 10) & 1) != 0)
+    }
+    #[doc = "Bit 11 - Cascade 2 test mode"]
+    #[inline(always)]
+    pub fn csdxxx2(&self) -> Csdxxx2R {
+        Csdxxx2R::new(((self.bits >> 11) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Cascade 0 Enable"]
+    #[inline(always)]
+    #[must_use]
+    pub fn csden0(&mut self) -> Csden0W<CsdCtrlSpec> {
+        Csden0W::new(self, 0)
+    }
+    #[doc = "Bit 1 - Cascade 0 Invert"]
+    #[inline(always)]
+    #[must_use]
+    pub fn csdinv0(&mut self) -> Csdinv0W<CsdCtrlSpec> {
+        Csdinv0W::new(self, 1)
+    }
+    #[doc = "Bit 2 - Cascade 1 Enable"]
+    #[inline(always)]
+    #[must_use]
+    pub fn csden1(&mut self) -> Csden1W<CsdCtrlSpec> {
+        Csden1W::new(self, 2)
+    }
+    #[doc = "Bit 3 - Cascade 1 Invert"]
+    #[inline(always)]
+    #[must_use]
+    pub fn csdinv1(&mut self) -> Csdinv1W<CsdCtrlSpec> {
+        Csdinv1W::new(self, 3)
+    }
+    #[doc = "Bit 4 - Dual Cascade Operation (0:AND, 1:OR)"]
+    #[inline(always)]
+    #[must_use]
+    pub fn dcasop(&mut self) -> DcasopW<CsdCtrlSpec> {
+        DcasopW::new(self, 4)
+    }
+    #[doc = "Bit 6 - Cascade 0 Enabled as Trigger"]
+    #[inline(always)]
+    #[must_use]
+    pub fn csdtrg0(&mut self) -> Csdtrg0W<CsdCtrlSpec> {
+        Csdtrg0W::new(self, 6)
+    }
+    #[doc = "Bit 7 - Cascade 1 Enabled as Trigger"]
+    #[inline(always)]
+    #[must_use]
+    pub fn csdtrg1(&mut self) -> Csdtrg1W<CsdCtrlSpec> {
+        Csdtrg1W::new(self, 7)
+    }
+    #[doc = "Bit 8 - Cascade 2 Enable"]
+    #[inline(always)]
+    #[must_use]
+    pub fn csden2(&mut self) -> Csden2W<CsdCtrlSpec> {
+        Csden2W::new(self, 8)
+    }
+    #[doc = "Bit 9 - Cascade 2 Invert"]
+    #[inline(always)]
+    #[must_use]
+    pub fn csdinv2(&mut self) -> Csdinv2W<CsdCtrlSpec> {
+        Csdinv2W::new(self, 9)
+    }
+    #[doc = "Bit 10 - Cascade 2 Enabled as Trigger"]
+    #[inline(always)]
+    #[must_use]
+    pub fn csdtrg2(&mut self) -> Csdtrg2W<CsdCtrlSpec> {
+        Csdtrg2W::new(self, 10)
+    }
+    #[doc = "Bit 11 - Cascade 2 test mode"]
+    #[inline(always)]
+    #[must_use]
+    pub fn csdxxx2(&mut self) -> Csdxxx2W<CsdCtrlSpec> {
+        Csdxxx2W::new(self, 11)
+    }
+}
+#[doc = "The Cascade Control Register. Controls the counter external enable signals\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`csd_ctrl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`csd_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CsdCtrlSpec;
+impl crate::RegisterSpec for CsdCtrlSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`csd_ctrl::R`](R) reader structure"]
+impl crate::Readable for CsdCtrlSpec {}
+#[doc = "`write(|w| ..)` method takes [`csd_ctrl::W`](W) writer structure"]
+impl crate::Writable for CsdCtrlSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CSD_CTRL to value 0"]
+impl crate::Resettable for CsdCtrlSpec {
+    const RESET_VALUE: u32 = 0;
+}

va108xx/src/tim0/ctrl.rs

@@ -0,0 +1,258 @@
+#[doc = "Register `CTRL` reader"]
+pub type R = crate::R<CtrlSpec>;
+#[doc = "Register `CTRL` writer"]
+pub type W = crate::W<CtrlSpec>;
+#[doc = "Field `ENABLE` reader - Counter Enable"]
+pub type EnableR = crate::BitReader;
+#[doc = "Field `ENABLE` writer - Counter Enable"]
+pub type EnableW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `ACTIVE` reader - Counter Active"]
+pub type ActiveR = crate::BitReader;
+#[doc = "Field `AUTO_DISABLE` reader - Auto Disables the counter (set ENABLE to 0) when the count reaches 0"]
+pub type AutoDisableR = crate::BitReader;
+#[doc = "Field `AUTO_DISABLE` writer - Auto Disables the counter (set ENABLE to 0) when the count reaches 0"]
+pub type AutoDisableW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `AUTO_DEACTIVATE` reader - Auto Deactivate the counter (set ACTIVE to 0) when the count reaches 0"]
+pub type AutoDeactivateR = crate::BitReader;
+#[doc = "Field `AUTO_DEACTIVATE` writer - Auto Deactivate the counter (set ACTIVE to 0) when the count reaches 0"]
+pub type AutoDeactivateW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `IRQ_ENB` reader - Interrupt Enable"]
+pub type IrqEnbR = crate::BitReader;
+#[doc = "Field `IRQ_ENB` writer - Interrupt Enable"]
+pub type IrqEnbW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Counter Status Selection\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+#[repr(u8)]
+pub enum StatusSel {
+    #[doc = "0: Single cycle pulse when the counter reaches 0"]
+    Done = 0,
+    #[doc = "1: Returns the counter ACTIVE bit"]
+    Active = 1,
+    #[doc = "2: Toggles the STATUS bit everytime the counter reaches 0. Basically a divide by 2 counter output."]
+    Toggle = 2,
+    #[doc = "3: Selects the Pulse Width Modulated output. It 1 when the counter value is >= the PWMA_VALUE"]
+    Pwma = 3,
+    #[doc = "4: Selects the Pulse Width Modulated output. It 1 when the counter value is &lt; the PWMA_VALUE and value is > PWMA_VALUE"]
+    Pwmb = 4,
+    #[doc = "5: Returns the counter ENABLED bit"]
+    Enabled = 5,
+    #[doc = "6: Selects the Pulse Width Modulated output. It 1 when the counter value is &lt;= the PWMA_VALUE and value is >= 0"]
+    PwmaActive = 6,
+}
+impl From<StatusSel> for u8 {
+    #[inline(always)]
+    fn from(variant: StatusSel) -> Self {
+        variant as _
+    }
+}
+impl crate::FieldSpec for StatusSel {
+    type Ux = u8;
+}
+impl crate::IsEnum for StatusSel {}
+#[doc = "Field `STATUS_SEL` reader - Counter Status Selection"]
+pub type StatusSelR = crate::FieldReader<StatusSel>;
+impl StatusSelR {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub const fn variant(&self) -> Option<StatusSel> {
+        match self.bits {
+            0 => Some(StatusSel::Done),
+            1 => Some(StatusSel::Active),
+            2 => Some(StatusSel::Toggle),
+            3 => Some(StatusSel::Pwma),
+            4 => Some(StatusSel::Pwmb),
+            5 => Some(StatusSel::Enabled),
+            6 => Some(StatusSel::PwmaActive),
+            _ => None,
+        }
+    }
+    #[doc = "Single cycle pulse when the counter reaches 0"]
+    #[inline(always)]
+    pub fn is_done(&self) -> bool {
+        *self == StatusSel::Done
+    }
+    #[doc = "Returns the counter ACTIVE bit"]
+    #[inline(always)]
+    pub fn is_active(&self) -> bool {
+        *self == StatusSel::Active
+    }
+    #[doc = "Toggles the STATUS bit everytime the counter reaches 0. Basically a divide by 2 counter output."]
+    #[inline(always)]
+    pub fn is_toggle(&self) -> bool {
+        *self == StatusSel::Toggle
+    }
+    #[doc = "Selects the Pulse Width Modulated output. It 1 when the counter value is >= the PWMA_VALUE"]
+    #[inline(always)]
+    pub fn is_pwma(&self) -> bool {
+        *self == StatusSel::Pwma
+    }
+    #[doc = "Selects the Pulse Width Modulated output. It 1 when the counter value is &lt; the PWMA_VALUE and value is > PWMA_VALUE"]
+    #[inline(always)]
+    pub fn is_pwmb(&self) -> bool {
+        *self == StatusSel::Pwmb
+    }
+    #[doc = "Returns the counter ENABLED bit"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == StatusSel::Enabled
+    }
+    #[doc = "Selects the Pulse Width Modulated output. It 1 when the counter value is &lt;= the PWMA_VALUE and value is >= 0"]
+    #[inline(always)]
+    pub fn is_pwma_active(&self) -> bool {
+        *self == StatusSel::PwmaActive
+    }
+}
+#[doc = "Field `STATUS_SEL` writer - Counter Status Selection"]
+pub type StatusSelW<'a, REG> = crate::FieldWriter<'a, REG, 3, StatusSel>;
+impl<'a, REG> StatusSelW<'a, REG>
+where
+    REG: crate::Writable + crate::RegisterSpec,
+    REG::Ux: From<u8>,
+{
+    #[doc = "Single cycle pulse when the counter reaches 0"]
+    #[inline(always)]
+    pub fn done(self) -> &'a mut crate::W<REG> {
+        self.variant(StatusSel::Done)
+    }
+    #[doc = "Returns the counter ACTIVE bit"]
+    #[inline(always)]
+    pub fn active(self) -> &'a mut crate::W<REG> {
+        self.variant(StatusSel::Active)
+    }
+    #[doc = "Toggles the STATUS bit everytime the counter reaches 0. Basically a divide by 2 counter output."]
+    #[inline(always)]
+    pub fn toggle(self) -> &'a mut crate::W<REG> {
+        self.variant(StatusSel::Toggle)
+    }
+    #[doc = "Selects the Pulse Width Modulated output. It 1 when the counter value is >= the PWMA_VALUE"]
+    #[inline(always)]
+    pub fn pwma(self) -> &'a mut crate::W<REG> {
+        self.variant(StatusSel::Pwma)
+    }
+    #[doc = "Selects the Pulse Width Modulated output. It 1 when the counter value is &lt; the PWMA_VALUE and value is > PWMA_VALUE"]
+    #[inline(always)]
+    pub fn pwmb(self) -> &'a mut crate::W<REG> {
+        self.variant(StatusSel::Pwmb)
+    }
+    #[doc = "Returns the counter ENABLED bit"]
+    #[inline(always)]
+    pub fn enabled(self) -> &'a mut crate::W<REG> {
+        self.variant(StatusSel::Enabled)
+    }
+    #[doc = "Selects the Pulse Width Modulated output. It 1 when the counter value is &lt;= the PWMA_VALUE and value is >= 0"]
+    #[inline(always)]
+    pub fn pwma_active(self) -> &'a mut crate::W<REG> {
+        self.variant(StatusSel::PwmaActive)
+    }
+}
+#[doc = "Field `STATUS_INV` reader - Invert the Output Status"]
+pub type StatusInvR = crate::BitReader;
+#[doc = "Field `STATUS_INV` writer - Invert the Output Status"]
+pub type StatusInvW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `REQ_STOP` reader - Stop Request"]
+pub type ReqStopR = crate::BitReader;
+#[doc = "Field `REQ_STOP` writer - Stop Request"]
+pub type ReqStopW<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - Counter Enable"]
+    #[inline(always)]
+    pub fn enable(&self) -> EnableR {
+        EnableR::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - Counter Active"]
+    #[inline(always)]
+    pub fn active(&self) -> ActiveR {
+        ActiveR::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - Auto Disables the counter (set ENABLE to 0) when the count reaches 0"]
+    #[inline(always)]
+    pub fn auto_disable(&self) -> AutoDisableR {
+        AutoDisableR::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - Auto Deactivate the counter (set ACTIVE to 0) when the count reaches 0"]
+    #[inline(always)]
+    pub fn auto_deactivate(&self) -> AutoDeactivateR {
+        AutoDeactivateR::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - Interrupt Enable"]
+    #[inline(always)]
+    pub fn irq_enb(&self) -> IrqEnbR {
+        IrqEnbR::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bits 5:7 - Counter Status Selection"]
+    #[inline(always)]
+    pub fn status_sel(&self) -> StatusSelR {
+        StatusSelR::new(((self.bits >> 5) & 7) as u8)
+    }
+    #[doc = "Bit 8 - Invert the Output Status"]
+    #[inline(always)]
+    pub fn status_inv(&self) -> StatusInvR {
+        StatusInvR::new(((self.bits >> 8) & 1) != 0)
+    }
+    #[doc = "Bit 9 - Stop Request"]
+    #[inline(always)]
+    pub fn req_stop(&self) -> ReqStopR {
+        ReqStopR::new(((self.bits >> 9) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Counter Enable"]
+    #[inline(always)]
+    #[must_use]
+    pub fn enable(&mut self) -> EnableW<CtrlSpec> {
+        EnableW::new(self, 0)
+    }
+    #[doc = "Bit 2 - Auto Disables the counter (set ENABLE to 0) when the count reaches 0"]
+    #[inline(always)]
+    #[must_use]
+    pub fn auto_disable(&mut self) -> AutoDisableW<CtrlSpec> {
+        AutoDisableW::new(self, 2)
+    }
+    #[doc = "Bit 3 - Auto Deactivate the counter (set ACTIVE to 0) when the count reaches 0"]
+    #[inline(always)]
+    #[must_use]
+    pub fn auto_deactivate(&mut self) -> AutoDeactivateW<CtrlSpec> {
+        AutoDeactivateW::new(self, 3)
+    }
+    #[doc = "Bit 4 - Interrupt Enable"]
+    #[inline(always)]
+    #[must_use]
+    pub fn irq_enb(&mut self) -> IrqEnbW<CtrlSpec> {
+        IrqEnbW::new(self, 4)
+    }
+    #[doc = "Bits 5:7 - Counter Status Selection"]
+    #[inline(always)]
+    #[must_use]
+    pub fn status_sel(&mut self) -> StatusSelW<CtrlSpec> {
+        StatusSelW::new(self, 5)
+    }
+    #[doc = "Bit 8 - Invert the Output Status"]
+    #[inline(always)]
+    #[must_use]
+    pub fn status_inv(&mut self) -> StatusInvW<CtrlSpec> {
+        StatusInvW::new(self, 8)
+    }
+    #[doc = "Bit 9 - Stop Request"]
+    #[inline(always)]
+    #[must_use]
+    pub fn req_stop(&mut self) -> ReqStopW<CtrlSpec> {
+        ReqStopW::new(self, 9)
+    }
+}
+#[doc = "Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CtrlSpec;
+impl crate::RegisterSpec for CtrlSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`ctrl::R`](R) reader structure"]
+impl crate::Readable for CtrlSpec {}
+#[doc = "`write(|w| ..)` method takes [`ctrl::W`](W) writer structure"]
+impl crate::Writable for CtrlSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CTRL to value 0"]
+impl crate::Resettable for CtrlSpec {
+    const RESET_VALUE: u32 = 0;
+}

va108xx/src/tim0/enable.rs

@@ -0,0 +1,40 @@
+#[doc = "Register `ENABLE` reader"]
+pub type R = crate::R<EnableSpec>;
+#[doc = "Register `ENABLE` writer"]
+pub type W = crate::W<EnableSpec>;
+#[doc = "Field `ENABLE` reader - Counter Enable"]
+pub type EnableR = crate::BitReader;
+#[doc = "Field `ENABLE` writer - Counter Enable"]
+pub type EnableW<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - Counter Enable"]
+    #[inline(always)]
+    pub fn enable(&self) -> EnableR {
+        EnableR::new((self.bits & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Counter Enable"]
+    #[inline(always)]
+    #[must_use]
+    pub fn enable(&mut self) -> EnableW<EnableSpec> {
+        EnableW::new(self, 0)
+    }
+}
+#[doc = "Alternate access to the Counter ENABLE bit in the CTRL Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct EnableSpec;
+impl crate::RegisterSpec for EnableSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`enable::R`](R) reader structure"]
+impl crate::Readable for EnableSpec {}
+#[doc = "`write(|w| ..)` method takes [`enable::W`](W) writer structure"]
+impl crate::Writable for EnableSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets ENABLE to value 0"]
+impl crate::Resettable for EnableSpec {
+    const RESET_VALUE: u32 = 0;
+}

va108xx/src/tim0/perid.rs

@@ -0,0 +1,18 @@
+#[doc = "Register `PERID` reader"]
+pub type R = crate::R<PeridSpec>;
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        write!(f, "{}", self.bits())
+    }
+}
+#[doc = "Peripheral ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`perid::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct PeridSpec;
+impl crate::RegisterSpec for PeridSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`perid::R`](R) reader structure"]
+impl crate::Readable for PeridSpec {}
+#[doc = "`reset()` method sets PERID to value 0x0011_07e1"]
+impl crate::Resettable for PeridSpec {
+    const RESET_VALUE: u32 = 0x0011_07e1;
+}

va108xx/src/tim0/pwm_value.rs

@@ -0,0 +1,27 @@
+#[doc = "Register `PWM_VALUE` reader"]
+pub type R = crate::R<PwmValueSpec>;
+#[doc = "Register `PWM_VALUE` writer"]
+pub type W = crate::W<PwmValueSpec>;
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        write!(f, "{}", self.bits())
+    }
+}
+impl W {}
+#[doc = "The Pulse Width Modulation Value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pwm_value::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pwm_value::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct PwmValueSpec;
+impl crate::RegisterSpec for PwmValueSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`pwm_value::R`](R) reader structure"]
+impl crate::Readable for PwmValueSpec {}
+#[doc = "`write(|w| ..)` method takes [`pwm_value::W`](W) writer structure"]
+impl crate::Writable for PwmValueSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets PWM_VALUE to value 0"]
+impl crate::Resettable for PwmValueSpec {
+    const RESET_VALUE: u32 = 0;
+}