New VA108xx Rust workspace structure + dependency updates
- The workspace is now a monorepo without submodules. The HAL, PAC and BSP are integrated directly - Update all dependencies: embedded-hal v1 and RTIC v2
This commit is contained in:
27
va108xx/src/i2ca/address.rs
Normal file
27
va108xx/src/i2ca/address.rs
Normal file
@ -0,0 +1,27 @@
|
||||
#[doc = "Register `ADDRESS` reader"]
|
||||
pub type R = crate::R<AddressSpec>;
|
||||
#[doc = "Register `ADDRESS` writer"]
|
||||
pub type W = crate::W<AddressSpec>;
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
write!(f, "{}", self.bits())
|
||||
}
|
||||
}
|
||||
impl W {}
|
||||
#[doc = "I2C Address value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`address::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`address::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct AddressSpec;
|
||||
impl crate::RegisterSpec for AddressSpec {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`address::R`](R) reader structure"]
|
||||
impl crate::Readable for AddressSpec {}
|
||||
#[doc = "`write(|w| ..)` method takes [`address::W`](W) writer structure"]
|
||||
impl crate::Writable for AddressSpec {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets ADDRESS to value 0"]
|
||||
impl crate::Resettable for AddressSpec {
|
||||
const RESET_VALUE: u32 = 0;
|
||||
}
|
||||
55
va108xx/src/i2ca/clkscale.rs
Normal file
55
va108xx/src/i2ca/clkscale.rs
Normal file
@ -0,0 +1,55 @@
|
||||
#[doc = "Register `CLKSCALE` reader"]
|
||||
pub type R = crate::R<ClkscaleSpec>;
|
||||
#[doc = "Register `CLKSCALE` writer"]
|
||||
pub type W = crate::W<ClkscaleSpec>;
|
||||
#[doc = "Field `VALUE` reader - Enable FastMode"]
|
||||
pub type ValueR = crate::FieldReader<u32>;
|
||||
#[doc = "Field `VALUE` writer - Enable FastMode"]
|
||||
pub type ValueW<'a, REG> = crate::FieldWriter<'a, REG, 31, u32>;
|
||||
#[doc = "Field `FASTMODE` reader - Enable FastMode"]
|
||||
pub type FastmodeR = crate::BitReader;
|
||||
#[doc = "Field `FASTMODE` writer - Enable FastMode"]
|
||||
pub type FastmodeW<'a, REG> = crate::BitWriter<'a, REG>;
|
||||
impl R {
|
||||
#[doc = "Bits 0:30 - Enable FastMode"]
|
||||
#[inline(always)]
|
||||
pub fn value(&self) -> ValueR {
|
||||
ValueR::new(self.bits & 0x7fff_ffff)
|
||||
}
|
||||
#[doc = "Bit 31 - Enable FastMode"]
|
||||
#[inline(always)]
|
||||
pub fn fastmode(&self) -> FastmodeR {
|
||||
FastmodeR::new(((self.bits >> 31) & 1) != 0)
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bits 0:30 - Enable FastMode"]
|
||||
#[inline(always)]
|
||||
#[must_use]
|
||||
pub fn value(&mut self) -> ValueW<ClkscaleSpec> {
|
||||
ValueW::new(self, 0)
|
||||
}
|
||||
#[doc = "Bit 31 - Enable FastMode"]
|
||||
#[inline(always)]
|
||||
#[must_use]
|
||||
pub fn fastmode(&mut self) -> FastmodeW<ClkscaleSpec> {
|
||||
FastmodeW::new(self, 31)
|
||||
}
|
||||
}
|
||||
#[doc = "Clock Scale divide value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkscale::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkscale::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct ClkscaleSpec;
|
||||
impl crate::RegisterSpec for ClkscaleSpec {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`clkscale::R`](R) reader structure"]
|
||||
impl crate::Readable for ClkscaleSpec {}
|
||||
#[doc = "`write(|w| ..)` method takes [`clkscale::W`](W) writer structure"]
|
||||
impl crate::Writable for ClkscaleSpec {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets CLKSCALE to value 0"]
|
||||
impl crate::Resettable for ClkscaleSpec {
|
||||
const RESET_VALUE: u32 = 0;
|
||||
}
|
||||
27
va108xx/src/i2ca/clktolimit.rs
Normal file
27
va108xx/src/i2ca/clktolimit.rs
Normal file
@ -0,0 +1,27 @@
|
||||
#[doc = "Register `CLKTOLIMIT` reader"]
|
||||
pub type R = crate::R<ClktolimitSpec>;
|
||||
#[doc = "Register `CLKTOLIMIT` writer"]
|
||||
pub type W = crate::W<ClktolimitSpec>;
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
write!(f, "{}", self.bits())
|
||||
}
|
||||
}
|
||||
impl W {}
|
||||
#[doc = "Clock Low Timeout Limit Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clktolimit::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clktolimit::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct ClktolimitSpec;
|
||||
impl crate::RegisterSpec for ClktolimitSpec {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`clktolimit::R`](R) reader structure"]
|
||||
impl crate::Readable for ClktolimitSpec {}
|
||||
#[doc = "`write(|w| ..)` method takes [`clktolimit::W`](W) writer structure"]
|
||||
impl crate::Writable for ClktolimitSpec {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets CLKTOLIMIT to value 0"]
|
||||
impl crate::Resettable for ClktolimitSpec {
|
||||
const RESET_VALUE: u32 = 0;
|
||||
}
|
||||
27
va108xx/src/i2ca/cmd.rs
Normal file
27
va108xx/src/i2ca/cmd.rs
Normal file
@ -0,0 +1,27 @@
|
||||
#[doc = "Register `CMD` reader"]
|
||||
pub type R = crate::R<CmdSpec>;
|
||||
#[doc = "Register `CMD` writer"]
|
||||
pub type W = crate::W<CmdSpec>;
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
write!(f, "{}", self.bits())
|
||||
}
|
||||
}
|
||||
impl W {}
|
||||
#[doc = "Command Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmd::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmd::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct CmdSpec;
|
||||
impl crate::RegisterSpec for CmdSpec {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`cmd::R`](R) reader structure"]
|
||||
impl crate::Readable for CmdSpec {}
|
||||
#[doc = "`write(|w| ..)` method takes [`cmd::W`](W) writer structure"]
|
||||
impl crate::Writable for CmdSpec {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets CMD to value 0"]
|
||||
impl crate::Resettable for CmdSpec {
|
||||
const RESET_VALUE: u32 = 0;
|
||||
}
|
||||
160
va108xx/src/i2ca/ctrl.rs
Normal file
160
va108xx/src/i2ca/ctrl.rs
Normal file
@ -0,0 +1,160 @@
|
||||
#[doc = "Register `CTRL` reader"]
|
||||
pub type R = crate::R<CtrlSpec>;
|
||||
#[doc = "Register `CTRL` writer"]
|
||||
pub type W = crate::W<CtrlSpec>;
|
||||
#[doc = "Field `CLKENABLED` reader - I2C CLK Enabled"]
|
||||
pub type ClkenabledR = crate::BitReader;
|
||||
#[doc = "Field `CLKENABLED` writer - I2C CLK Enabled"]
|
||||
pub type ClkenabledW<'a, REG> = crate::BitWriter<'a, REG>;
|
||||
#[doc = "Field `ENABLED` reader - I2C Activated"]
|
||||
pub type EnabledR = crate::BitReader;
|
||||
#[doc = "Field `ENABLED` writer - I2C Activated"]
|
||||
pub type EnabledW<'a, REG> = crate::BitWriter<'a, REG>;
|
||||
#[doc = "Field `ENABLE` reader - I2C Active"]
|
||||
pub type EnableR = crate::BitReader;
|
||||
#[doc = "Field `ENABLE` writer - I2C Active"]
|
||||
pub type EnableW<'a, REG> = crate::BitWriter<'a, REG>;
|
||||
#[doc = "Field `TXFEMD` reader - TX FIFIO Empty Mode"]
|
||||
pub type TxfemdR = crate::BitReader;
|
||||
#[doc = "Field `TXFEMD` writer - TX FIFIO Empty Mode"]
|
||||
pub type TxfemdW<'a, REG> = crate::BitWriter<'a, REG>;
|
||||
#[doc = "Field `RXFFMD` reader - RX FIFO Full Mode"]
|
||||
pub type RxffmdR = crate::BitReader;
|
||||
#[doc = "Field `RXFFMD` writer - RX FIFO Full Mode"]
|
||||
pub type RxffmdW<'a, REG> = crate::BitWriter<'a, REG>;
|
||||
#[doc = "Field `ALGFILTER` reader - Enable Input Analog Glitch Filter"]
|
||||
pub type AlgfilterR = crate::BitReader;
|
||||
#[doc = "Field `ALGFILTER` writer - Enable Input Analog Glitch Filter"]
|
||||
pub type AlgfilterW<'a, REG> = crate::BitWriter<'a, REG>;
|
||||
#[doc = "Field `DLGFILTER` reader - Enable Input Digital Glitch Filter"]
|
||||
pub type DlgfilterR = crate::BitReader;
|
||||
#[doc = "Field `DLGFILTER` writer - Enable Input Digital Glitch Filter"]
|
||||
pub type DlgfilterW<'a, REG> = crate::BitWriter<'a, REG>;
|
||||
#[doc = "Field `LOOPBACK` reader - Enable LoopBack Mode"]
|
||||
pub type LoopbackR = crate::BitReader;
|
||||
#[doc = "Field `LOOPBACK` writer - Enable LoopBack Mode"]
|
||||
pub type LoopbackW<'a, REG> = crate::BitWriter<'a, REG>;
|
||||
#[doc = "Field `TMCONFIGENB` reader - Enable Timing Config Register"]
|
||||
pub type TmconfigenbR = crate::BitReader;
|
||||
#[doc = "Field `TMCONFIGENB` writer - Enable Timing Config Register"]
|
||||
pub type TmconfigenbW<'a, REG> = crate::BitWriter<'a, REG>;
|
||||
impl R {
|
||||
#[doc = "Bit 0 - I2C CLK Enabled"]
|
||||
#[inline(always)]
|
||||
pub fn clkenabled(&self) -> ClkenabledR {
|
||||
ClkenabledR::new((self.bits & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 1 - I2C Activated"]
|
||||
#[inline(always)]
|
||||
pub fn enabled(&self) -> EnabledR {
|
||||
EnabledR::new(((self.bits >> 1) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 2 - I2C Active"]
|
||||
#[inline(always)]
|
||||
pub fn enable(&self) -> EnableR {
|
||||
EnableR::new(((self.bits >> 2) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 3 - TX FIFIO Empty Mode"]
|
||||
#[inline(always)]
|
||||
pub fn txfemd(&self) -> TxfemdR {
|
||||
TxfemdR::new(((self.bits >> 3) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 4 - RX FIFO Full Mode"]
|
||||
#[inline(always)]
|
||||
pub fn rxffmd(&self) -> RxffmdR {
|
||||
RxffmdR::new(((self.bits >> 4) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 5 - Enable Input Analog Glitch Filter"]
|
||||
#[inline(always)]
|
||||
pub fn algfilter(&self) -> AlgfilterR {
|
||||
AlgfilterR::new(((self.bits >> 5) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 6 - Enable Input Digital Glitch Filter"]
|
||||
#[inline(always)]
|
||||
pub fn dlgfilter(&self) -> DlgfilterR {
|
||||
DlgfilterR::new(((self.bits >> 6) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 8 - Enable LoopBack Mode"]
|
||||
#[inline(always)]
|
||||
pub fn loopback(&self) -> LoopbackR {
|
||||
LoopbackR::new(((self.bits >> 8) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 9 - Enable Timing Config Register"]
|
||||
#[inline(always)]
|
||||
pub fn tmconfigenb(&self) -> TmconfigenbR {
|
||||
TmconfigenbR::new(((self.bits >> 9) & 1) != 0)
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bit 0 - I2C CLK Enabled"]
|
||||
#[inline(always)]
|
||||
#[must_use]
|
||||
pub fn clkenabled(&mut self) -> ClkenabledW<CtrlSpec> {
|
||||
ClkenabledW::new(self, 0)
|
||||
}
|
||||
#[doc = "Bit 1 - I2C Activated"]
|
||||
#[inline(always)]
|
||||
#[must_use]
|
||||
pub fn enabled(&mut self) -> EnabledW<CtrlSpec> {
|
||||
EnabledW::new(self, 1)
|
||||
}
|
||||
#[doc = "Bit 2 - I2C Active"]
|
||||
#[inline(always)]
|
||||
#[must_use]
|
||||
pub fn enable(&mut self) -> EnableW<CtrlSpec> {
|
||||
EnableW::new(self, 2)
|
||||
}
|
||||
#[doc = "Bit 3 - TX FIFIO Empty Mode"]
|
||||
#[inline(always)]
|
||||
#[must_use]
|
||||
pub fn txfemd(&mut self) -> TxfemdW<CtrlSpec> {
|
||||
TxfemdW::new(self, 3)
|
||||
}
|
||||
#[doc = "Bit 4 - RX FIFO Full Mode"]
|
||||
#[inline(always)]
|
||||
#[must_use]
|
||||
pub fn rxffmd(&mut self) -> RxffmdW<CtrlSpec> {
|
||||
RxffmdW::new(self, 4)
|
||||
}
|
||||
#[doc = "Bit 5 - Enable Input Analog Glitch Filter"]
|
||||
#[inline(always)]
|
||||
#[must_use]
|
||||
pub fn algfilter(&mut self) -> AlgfilterW<CtrlSpec> {
|
||||
AlgfilterW::new(self, 5)
|
||||
}
|
||||
#[doc = "Bit 6 - Enable Input Digital Glitch Filter"]
|
||||
#[inline(always)]
|
||||
#[must_use]
|
||||
pub fn dlgfilter(&mut self) -> DlgfilterW<CtrlSpec> {
|
||||
DlgfilterW::new(self, 6)
|
||||
}
|
||||
#[doc = "Bit 8 - Enable LoopBack Mode"]
|
||||
#[inline(always)]
|
||||
#[must_use]
|
||||
pub fn loopback(&mut self) -> LoopbackW<CtrlSpec> {
|
||||
LoopbackW::new(self, 8)
|
||||
}
|
||||
#[doc = "Bit 9 - Enable Timing Config Register"]
|
||||
#[inline(always)]
|
||||
#[must_use]
|
||||
pub fn tmconfigenb(&mut self) -> TmconfigenbW<CtrlSpec> {
|
||||
TmconfigenbW::new(self, 9)
|
||||
}
|
||||
}
|
||||
#[doc = "Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct CtrlSpec;
|
||||
impl crate::RegisterSpec for CtrlSpec {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`ctrl::R`](R) reader structure"]
|
||||
impl crate::Readable for CtrlSpec {}
|
||||
#[doc = "`write(|w| ..)` method takes [`ctrl::W`](W) writer structure"]
|
||||
impl crate::Writable for CtrlSpec {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets CTRL to value 0"]
|
||||
impl crate::Resettable for CtrlSpec {
|
||||
const RESET_VALUE: u32 = 0;
|
||||
}
|
||||
27
va108xx/src/i2ca/data.rs
Normal file
27
va108xx/src/i2ca/data.rs
Normal file
@ -0,0 +1,27 @@
|
||||
#[doc = "Register `DATA` reader"]
|
||||
pub type R = crate::R<DataSpec>;
|
||||
#[doc = "Register `DATA` writer"]
|
||||
pub type W = crate::W<DataSpec>;
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
write!(f, "{}", self.bits())
|
||||
}
|
||||
}
|
||||
impl W {}
|
||||
#[doc = "Data Input/Output\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct DataSpec;
|
||||
impl crate::RegisterSpec for DataSpec {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`data::R`](R) reader structure"]
|
||||
impl crate::Readable for DataSpec {}
|
||||
#[doc = "`write(|w| ..)` method takes [`data::W`](W) writer structure"]
|
||||
impl crate::Writable for DataSpec {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets DATA to value 0"]
|
||||
impl crate::Resettable for DataSpec {
|
||||
const RESET_VALUE: u32 = 0;
|
||||
}
|
||||
35
va108xx/src/i2ca/fifo_clr.rs
Normal file
35
va108xx/src/i2ca/fifo_clr.rs
Normal file
@ -0,0 +1,35 @@
|
||||
#[doc = "Register `FIFO_CLR` writer"]
|
||||
pub type W = crate::W<FifoClrSpec>;
|
||||
#[doc = "Field `RXFIFO` writer - Clear Rx FIFO"]
|
||||
pub type RxfifoW<'a, REG> = crate::BitWriter<'a, REG>;
|
||||
#[doc = "Field `TXFIFO` writer - Clear Tx FIFO"]
|
||||
pub type TxfifoW<'a, REG> = crate::BitWriter<'a, REG>;
|
||||
impl W {
|
||||
#[doc = "Bit 0 - Clear Rx FIFO"]
|
||||
#[inline(always)]
|
||||
#[must_use]
|
||||
pub fn rxfifo(&mut self) -> RxfifoW<FifoClrSpec> {
|
||||
RxfifoW::new(self, 0)
|
||||
}
|
||||
#[doc = "Bit 1 - Clear Tx FIFO"]
|
||||
#[inline(always)]
|
||||
#[must_use]
|
||||
pub fn txfifo(&mut self) -> TxfifoW<FifoClrSpec> {
|
||||
TxfifoW::new(self, 1)
|
||||
}
|
||||
}
|
||||
#[doc = "Clear FIFO Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifo_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct FifoClrSpec;
|
||||
impl crate::RegisterSpec for FifoClrSpec {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`write(|w| ..)` method takes [`fifo_clr::W`](W) writer structure"]
|
||||
impl crate::Writable for FifoClrSpec {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets FIFO_CLR to value 0"]
|
||||
impl crate::Resettable for FifoClrSpec {
|
||||
const RESET_VALUE: u32 = 0;
|
||||
}
|
||||
235
va108xx/src/i2ca/irq_enb.rs
Normal file
235
va108xx/src/i2ca/irq_enb.rs
Normal file
@ -0,0 +1,235 @@
|
||||
#[doc = "Register `IRQ_ENB` reader"]
|
||||
pub type R = crate::R<IrqEnbSpec>;
|
||||
#[doc = "Register `IRQ_ENB` writer"]
|
||||
pub type W = crate::W<IrqEnbSpec>;
|
||||
#[doc = "Field `I2CIDLE` reader - I2C Bus is Idle"]
|
||||
pub type I2cidleR = crate::BitReader;
|
||||
#[doc = "Field `I2CIDLE` writer - I2C Bus is Idle"]
|
||||
pub type I2cidleW<'a, REG> = crate::BitWriter<'a, REG>;
|
||||
#[doc = "Field `IDLE` reader - Controller is Idle"]
|
||||
pub type IdleR = crate::BitReader;
|
||||
#[doc = "Field `IDLE` writer - Controller is Idle"]
|
||||
pub type IdleW<'a, REG> = crate::BitWriter<'a, REG>;
|
||||
#[doc = "Field `WAITING` reader - Controller is Waiting"]
|
||||
pub type WaitingR = crate::BitReader;
|
||||
#[doc = "Field `WAITING` writer - Controller is Waiting"]
|
||||
pub type WaitingW<'a, REG> = crate::BitWriter<'a, REG>;
|
||||
#[doc = "Field `STALLED` reader - Controller is Stalled"]
|
||||
pub type StalledR = crate::BitReader;
|
||||
#[doc = "Field `STALLED` writer - Controller is Stalled"]
|
||||
pub type StalledW<'a, REG> = crate::BitWriter<'a, REG>;
|
||||
#[doc = "Field `ARBLOST` reader - I2C Arbitration was lost"]
|
||||
pub type ArblostR = crate::BitReader;
|
||||
#[doc = "Field `ARBLOST` writer - I2C Arbitration was lost"]
|
||||
pub type ArblostW<'a, REG> = crate::BitWriter<'a, REG>;
|
||||
#[doc = "Field `NACKADDR` reader - I2C Address was not Acknowledged"]
|
||||
pub type NackaddrR = crate::BitReader;
|
||||
#[doc = "Field `NACKADDR` writer - I2C Address was not Acknowledged"]
|
||||
pub type NackaddrW<'a, REG> = crate::BitWriter<'a, REG>;
|
||||
#[doc = "Field `NACKDATA` reader - I2C Data was not Acknowledged"]
|
||||
pub type NackdataR = crate::BitReader;
|
||||
#[doc = "Field `NACKDATA` writer - I2C Data was not Acknowledged"]
|
||||
pub type NackdataW<'a, REG> = crate::BitWriter<'a, REG>;
|
||||
#[doc = "Field `CLKLOTO` reader - I2C Clock Low Timeout"]
|
||||
pub type ClklotoR = crate::BitReader;
|
||||
#[doc = "Field `CLKLOTO` writer - I2C Clock Low Timeout"]
|
||||
pub type ClklotoW<'a, REG> = crate::BitWriter<'a, REG>;
|
||||
#[doc = "Field `TXOVERFLOW` reader - TX FIFO Overflowed"]
|
||||
pub type TxoverflowR = crate::BitReader;
|
||||
#[doc = "Field `TXOVERFLOW` writer - TX FIFO Overflowed"]
|
||||
pub type TxoverflowW<'a, REG> = crate::BitWriter<'a, REG>;
|
||||
#[doc = "Field `RXOVERFLOW` reader - TX FIFO Overflowed"]
|
||||
pub type RxoverflowR = crate::BitReader;
|
||||
#[doc = "Field `RXOVERFLOW` writer - TX FIFO Overflowed"]
|
||||
pub type RxoverflowW<'a, REG> = crate::BitWriter<'a, REG>;
|
||||
#[doc = "Field `TXREADY` reader - TX FIFO Ready"]
|
||||
pub type TxreadyR = crate::BitReader;
|
||||
#[doc = "Field `TXREADY` writer - TX FIFO Ready"]
|
||||
pub type TxreadyW<'a, REG> = crate::BitWriter<'a, REG>;
|
||||
#[doc = "Field `RXREADY` reader - RX FIFO Ready"]
|
||||
pub type RxreadyR = crate::BitReader;
|
||||
#[doc = "Field `RXREADY` writer - RX FIFO Ready"]
|
||||
pub type RxreadyW<'a, REG> = crate::BitWriter<'a, REG>;
|
||||
#[doc = "Field `TXEMPTY` reader - TX FIFO Empty"]
|
||||
pub type TxemptyR = crate::BitReader;
|
||||
#[doc = "Field `TXEMPTY` writer - TX FIFO Empty"]
|
||||
pub type TxemptyW<'a, REG> = crate::BitWriter<'a, REG>;
|
||||
#[doc = "Field `RXFULL` reader - RX FIFO Full"]
|
||||
pub type RxfullR = crate::BitReader;
|
||||
#[doc = "Field `RXFULL` writer - RX FIFO Full"]
|
||||
pub type RxfullW<'a, REG> = crate::BitWriter<'a, REG>;
|
||||
impl R {
|
||||
#[doc = "Bit 0 - I2C Bus is Idle"]
|
||||
#[inline(always)]
|
||||
pub fn i2cidle(&self) -> I2cidleR {
|
||||
I2cidleR::new((self.bits & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 1 - Controller is Idle"]
|
||||
#[inline(always)]
|
||||
pub fn idle(&self) -> IdleR {
|
||||
IdleR::new(((self.bits >> 1) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 2 - Controller is Waiting"]
|
||||
#[inline(always)]
|
||||
pub fn waiting(&self) -> WaitingR {
|
||||
WaitingR::new(((self.bits >> 2) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 3 - Controller is Stalled"]
|
||||
#[inline(always)]
|
||||
pub fn stalled(&self) -> StalledR {
|
||||
StalledR::new(((self.bits >> 3) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 4 - I2C Arbitration was lost"]
|
||||
#[inline(always)]
|
||||
pub fn arblost(&self) -> ArblostR {
|
||||
ArblostR::new(((self.bits >> 4) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 5 - I2C Address was not Acknowledged"]
|
||||
#[inline(always)]
|
||||
pub fn nackaddr(&self) -> NackaddrR {
|
||||
NackaddrR::new(((self.bits >> 5) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 6 - I2C Data was not Acknowledged"]
|
||||
#[inline(always)]
|
||||
pub fn nackdata(&self) -> NackdataR {
|
||||
NackdataR::new(((self.bits >> 6) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 7 - I2C Clock Low Timeout"]
|
||||
#[inline(always)]
|
||||
pub fn clkloto(&self) -> ClklotoR {
|
||||
ClklotoR::new(((self.bits >> 7) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 10 - TX FIFO Overflowed"]
|
||||
#[inline(always)]
|
||||
pub fn txoverflow(&self) -> TxoverflowR {
|
||||
TxoverflowR::new(((self.bits >> 10) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 11 - TX FIFO Overflowed"]
|
||||
#[inline(always)]
|
||||
pub fn rxoverflow(&self) -> RxoverflowR {
|
||||
RxoverflowR::new(((self.bits >> 11) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 12 - TX FIFO Ready"]
|
||||
#[inline(always)]
|
||||
pub fn txready(&self) -> TxreadyR {
|
||||
TxreadyR::new(((self.bits >> 12) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 13 - RX FIFO Ready"]
|
||||
#[inline(always)]
|
||||
pub fn rxready(&self) -> RxreadyR {
|
||||
RxreadyR::new(((self.bits >> 13) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 14 - TX FIFO Empty"]
|
||||
#[inline(always)]
|
||||
pub fn txempty(&self) -> TxemptyR {
|
||||
TxemptyR::new(((self.bits >> 14) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 15 - RX FIFO Full"]
|
||||
#[inline(always)]
|
||||
pub fn rxfull(&self) -> RxfullR {
|
||||
RxfullR::new(((self.bits >> 15) & 1) != 0)
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bit 0 - I2C Bus is Idle"]
|
||||
#[inline(always)]
|
||||
#[must_use]
|
||||
pub fn i2cidle(&mut self) -> I2cidleW<IrqEnbSpec> {
|
||||
I2cidleW::new(self, 0)
|
||||
}
|
||||
#[doc = "Bit 1 - Controller is Idle"]
|
||||
#[inline(always)]
|
||||
#[must_use]
|
||||
pub fn idle(&mut self) -> IdleW<IrqEnbSpec> {
|
||||
IdleW::new(self, 1)
|
||||
}
|
||||
#[doc = "Bit 2 - Controller is Waiting"]
|
||||
#[inline(always)]
|
||||
#[must_use]
|
||||
pub fn waiting(&mut self) -> WaitingW<IrqEnbSpec> {
|
||||
WaitingW::new(self, 2)
|
||||
}
|
||||
#[doc = "Bit 3 - Controller is Stalled"]
|
||||
#[inline(always)]
|
||||
#[must_use]
|
||||
pub fn stalled(&mut self) -> StalledW<IrqEnbSpec> {
|
||||
StalledW::new(self, 3)
|
||||
}
|
||||
#[doc = "Bit 4 - I2C Arbitration was lost"]
|
||||
#[inline(always)]
|
||||
#[must_use]
|
||||
pub fn arblost(&mut self) -> ArblostW<IrqEnbSpec> {
|
||||
ArblostW::new(self, 4)
|
||||
}
|
||||
#[doc = "Bit 5 - I2C Address was not Acknowledged"]
|
||||
#[inline(always)]
|
||||
#[must_use]
|
||||
pub fn nackaddr(&mut self) -> NackaddrW<IrqEnbSpec> {
|
||||
NackaddrW::new(self, 5)
|
||||
}
|
||||
#[doc = "Bit 6 - I2C Data was not Acknowledged"]
|
||||
#[inline(always)]
|
||||
#[must_use]
|
||||
pub fn nackdata(&mut self) -> NackdataW<IrqEnbSpec> {
|
||||
NackdataW::new(self, 6)
|
||||
}
|
||||
#[doc = "Bit 7 - I2C Clock Low Timeout"]
|
||||
#[inline(always)]
|
||||
#[must_use]
|
||||
pub fn clkloto(&mut self) -> ClklotoW<IrqEnbSpec> {
|
||||
ClklotoW::new(self, 7)
|
||||
}
|
||||
#[doc = "Bit 10 - TX FIFO Overflowed"]
|
||||
#[inline(always)]
|
||||
#[must_use]
|
||||
pub fn txoverflow(&mut self) -> TxoverflowW<IrqEnbSpec> {
|
||||
TxoverflowW::new(self, 10)
|
||||
}
|
||||
#[doc = "Bit 11 - TX FIFO Overflowed"]
|
||||
#[inline(always)]
|
||||
#[must_use]
|
||||
pub fn rxoverflow(&mut self) -> RxoverflowW<IrqEnbSpec> {
|
||||
RxoverflowW::new(self, 11)
|
||||
}
|
||||
#[doc = "Bit 12 - TX FIFO Ready"]
|
||||
#[inline(always)]
|
||||
#[must_use]
|
||||
pub fn txready(&mut self) -> TxreadyW<IrqEnbSpec> {
|
||||
TxreadyW::new(self, 12)
|
||||
}
|
||||
#[doc = "Bit 13 - RX FIFO Ready"]
|
||||
#[inline(always)]
|
||||
#[must_use]
|
||||
pub fn rxready(&mut self) -> RxreadyW<IrqEnbSpec> {
|
||||
RxreadyW::new(self, 13)
|
||||
}
|
||||
#[doc = "Bit 14 - TX FIFO Empty"]
|
||||
#[inline(always)]
|
||||
#[must_use]
|
||||
pub fn txempty(&mut self) -> TxemptyW<IrqEnbSpec> {
|
||||
TxemptyW::new(self, 14)
|
||||
}
|
||||
#[doc = "Bit 15 - RX FIFO Full"]
|
||||
#[inline(always)]
|
||||
#[must_use]
|
||||
pub fn rxfull(&mut self) -> RxfullW<IrqEnbSpec> {
|
||||
RxfullW::new(self, 15)
|
||||
}
|
||||
}
|
||||
#[doc = "Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_enb::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_enb::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct IrqEnbSpec;
|
||||
impl crate::RegisterSpec for IrqEnbSpec {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`irq_enb::R`](R) reader structure"]
|
||||
impl crate::Readable for IrqEnbSpec {}
|
||||
#[doc = "`write(|w| ..)` method takes [`irq_enb::W`](W) writer structure"]
|
||||
impl crate::Writable for IrqEnbSpec {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets IRQ_ENB to value 0"]
|
||||
impl crate::Resettable for IrqEnbSpec {
|
||||
const RESET_VALUE: u32 = 0;
|
||||
}
|
||||
18
va108xx/src/i2ca/perid.rs
Normal file
18
va108xx/src/i2ca/perid.rs
Normal file
@ -0,0 +1,18 @@
|
||||
#[doc = "Register `PERID` reader"]
|
||||
pub type R = crate::R<PeridSpec>;
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
write!(f, "{}", self.bits())
|
||||
}
|
||||
}
|
||||
#[doc = "Peripheral ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`perid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct PeridSpec;
|
||||
impl crate::RegisterSpec for PeridSpec {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`perid::R`](R) reader structure"]
|
||||
impl crate::Readable for PeridSpec {}
|
||||
#[doc = "`reset()` method sets PERID to value 0x0014_07e1"]
|
||||
impl crate::Resettable for PeridSpec {
|
||||
const RESET_VALUE: u32 = 0x0014_07e1;
|
||||
}
|
||||
18
va108xx/src/i2ca/rxcount.rs
Normal file
18
va108xx/src/i2ca/rxcount.rs
Normal file
@ -0,0 +1,18 @@
|
||||
#[doc = "Register `RXCOUNT` reader"]
|
||||
pub type R = crate::R<RxcountSpec>;
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
write!(f, "{}", self.bits())
|
||||
}
|
||||
}
|
||||
#[doc = "RX Count Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxcount::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct RxcountSpec;
|
||||
impl crate::RegisterSpec for RxcountSpec {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`rxcount::R`](R) reader structure"]
|
||||
impl crate::Readable for RxcountSpec {}
|
||||
#[doc = "`reset()` method sets RXCOUNT to value 0"]
|
||||
impl crate::Resettable for RxcountSpec {
|
||||
const RESET_VALUE: u32 = 0;
|
||||
}
|
||||
27
va108xx/src/i2ca/rxfifoirqtrg.rs
Normal file
27
va108xx/src/i2ca/rxfifoirqtrg.rs
Normal file
@ -0,0 +1,27 @@
|
||||
#[doc = "Register `RXFIFOIRQTRG` reader"]
|
||||
pub type R = crate::R<RxfifoirqtrgSpec>;
|
||||
#[doc = "Register `RXFIFOIRQTRG` writer"]
|
||||
pub type W = crate::W<RxfifoirqtrgSpec>;
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
write!(f, "{}", self.bits())
|
||||
}
|
||||
}
|
||||
impl W {}
|
||||
#[doc = "Rx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxfifoirqtrg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxfifoirqtrg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct RxfifoirqtrgSpec;
|
||||
impl crate::RegisterSpec for RxfifoirqtrgSpec {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`rxfifoirqtrg::R`](R) reader structure"]
|
||||
impl crate::Readable for RxfifoirqtrgSpec {}
|
||||
#[doc = "`write(|w| ..)` method takes [`rxfifoirqtrg::W`](W) writer structure"]
|
||||
impl crate::Writable for RxfifoirqtrgSpec {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets RXFIFOIRQTRG to value 0"]
|
||||
impl crate::Resettable for RxfifoirqtrgSpec {
|
||||
const RESET_VALUE: u32 = 0;
|
||||
}
|
||||
27
va108xx/src/i2ca/s0_address.rs
Normal file
27
va108xx/src/i2ca/s0_address.rs
Normal file
@ -0,0 +1,27 @@
|
||||
#[doc = "Register `S0_ADDRESS` reader"]
|
||||
pub type R = crate::R<S0AddressSpec>;
|
||||
#[doc = "Register `S0_ADDRESS` writer"]
|
||||
pub type W = crate::W<S0AddressSpec>;
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
write!(f, "{}", self.bits())
|
||||
}
|
||||
}
|
||||
impl W {}
|
||||
#[doc = "Slave I2C Address Value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_address::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_address::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct S0AddressSpec;
|
||||
impl crate::RegisterSpec for S0AddressSpec {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`s0_address::R`](R) reader structure"]
|
||||
impl crate::Readable for S0AddressSpec {}
|
||||
#[doc = "`write(|w| ..)` method takes [`s0_address::W`](W) writer structure"]
|
||||
impl crate::Writable for S0AddressSpec {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets S0_ADDRESS to value 0"]
|
||||
impl crate::Resettable for S0AddressSpec {
|
||||
const RESET_VALUE: u32 = 0;
|
||||
}
|
||||
27
va108xx/src/i2ca/s0_addressb.rs
Normal file
27
va108xx/src/i2ca/s0_addressb.rs
Normal file
@ -0,0 +1,27 @@
|
||||
#[doc = "Register `S0_ADDRESSB` reader"]
|
||||
pub type R = crate::R<S0AddressbSpec>;
|
||||
#[doc = "Register `S0_ADDRESSB` writer"]
|
||||
pub type W = crate::W<S0AddressbSpec>;
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
write!(f, "{}", self.bits())
|
||||
}
|
||||
}
|
||||
impl W {}
|
||||
#[doc = "Slave I2C Address B Value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_addressb::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_addressb::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct S0AddressbSpec;
|
||||
impl crate::RegisterSpec for S0AddressbSpec {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`s0_addressb::R`](R) reader structure"]
|
||||
impl crate::Readable for S0AddressbSpec {}
|
||||
#[doc = "`write(|w| ..)` method takes [`s0_addressb::W`](W) writer structure"]
|
||||
impl crate::Writable for S0AddressbSpec {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets S0_ADDRESSB to value 0"]
|
||||
impl crate::Resettable for S0AddressbSpec {
|
||||
const RESET_VALUE: u32 = 0;
|
||||
}
|
||||
27
va108xx/src/i2ca/s0_addressmask.rs
Normal file
27
va108xx/src/i2ca/s0_addressmask.rs
Normal file
@ -0,0 +1,27 @@
|
||||
#[doc = "Register `S0_ADDRESSMASK` reader"]
|
||||
pub type R = crate::R<S0AddressmaskSpec>;
|
||||
#[doc = "Register `S0_ADDRESSMASK` writer"]
|
||||
pub type W = crate::W<S0AddressmaskSpec>;
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
write!(f, "{}", self.bits())
|
||||
}
|
||||
}
|
||||
impl W {}
|
||||
#[doc = "Slave I2C Address Mask value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_addressmask::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_addressmask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct S0AddressmaskSpec;
|
||||
impl crate::RegisterSpec for S0AddressmaskSpec {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`s0_addressmask::R`](R) reader structure"]
|
||||
impl crate::Readable for S0AddressmaskSpec {}
|
||||
#[doc = "`write(|w| ..)` method takes [`s0_addressmask::W`](W) writer structure"]
|
||||
impl crate::Writable for S0AddressmaskSpec {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets S0_ADDRESSMASK to value 0"]
|
||||
impl crate::Resettable for S0AddressmaskSpec {
|
||||
const RESET_VALUE: u32 = 0;
|
||||
}
|
||||
27
va108xx/src/i2ca/s0_addressmaskb.rs
Normal file
27
va108xx/src/i2ca/s0_addressmaskb.rs
Normal file
@ -0,0 +1,27 @@
|
||||
#[doc = "Register `S0_ADDRESSMASKB` reader"]
|
||||
pub type R = crate::R<S0AddressmaskbSpec>;
|
||||
#[doc = "Register `S0_ADDRESSMASKB` writer"]
|
||||
pub type W = crate::W<S0AddressmaskbSpec>;
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
write!(f, "{}", self.bits())
|
||||
}
|
||||
}
|
||||
impl W {}
|
||||
#[doc = "Slave I2C Address B Mask value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_addressmaskb::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_addressmaskb::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct S0AddressmaskbSpec;
|
||||
impl crate::RegisterSpec for S0AddressmaskbSpec {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`s0_addressmaskb::R`](R) reader structure"]
|
||||
impl crate::Readable for S0AddressmaskbSpec {}
|
||||
#[doc = "`write(|w| ..)` method takes [`s0_addressmaskb::W`](W) writer structure"]
|
||||
impl crate::Writable for S0AddressmaskbSpec {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets S0_ADDRESSMASKB to value 0"]
|
||||
impl crate::Resettable for S0AddressmaskbSpec {
|
||||
const RESET_VALUE: u32 = 0;
|
||||
}
|
||||
100
va108xx/src/i2ca/s0_ctrl.rs
Normal file
100
va108xx/src/i2ca/s0_ctrl.rs
Normal file
@ -0,0 +1,100 @@
|
||||
#[doc = "Register `S0_CTRL` reader"]
|
||||
pub type R = crate::R<S0CtrlSpec>;
|
||||
#[doc = "Register `S0_CTRL` writer"]
|
||||
pub type W = crate::W<S0CtrlSpec>;
|
||||
#[doc = "Field `CLKENABLED` reader - I2C Enabled"]
|
||||
pub type ClkenabledR = crate::BitReader;
|
||||
#[doc = "Field `CLKENABLED` writer - I2C Enabled"]
|
||||
pub type ClkenabledW<'a, REG> = crate::BitWriter<'a, REG>;
|
||||
#[doc = "Field `ENABLED` reader - I2C Activated"]
|
||||
pub type EnabledR = crate::BitReader;
|
||||
#[doc = "Field `ENABLED` writer - I2C Activated"]
|
||||
pub type EnabledW<'a, REG> = crate::BitWriter<'a, REG>;
|
||||
#[doc = "Field `ENABLE` reader - I2C Active"]
|
||||
pub type EnableR = crate::BitReader;
|
||||
#[doc = "Field `ENABLE` writer - I2C Active"]
|
||||
pub type EnableW<'a, REG> = crate::BitWriter<'a, REG>;
|
||||
#[doc = "Field `TXFEMD` reader - TX FIFIO Empty Mode"]
|
||||
pub type TxfemdR = crate::BitReader;
|
||||
#[doc = "Field `TXFEMD` writer - TX FIFIO Empty Mode"]
|
||||
pub type TxfemdW<'a, REG> = crate::BitWriter<'a, REG>;
|
||||
#[doc = "Field `RXFFMD` reader - RX FIFO Full Mode"]
|
||||
pub type RxffmdR = crate::BitReader;
|
||||
#[doc = "Field `RXFFMD` writer - RX FIFO Full Mode"]
|
||||
pub type RxffmdW<'a, REG> = crate::BitWriter<'a, REG>;
|
||||
impl R {
|
||||
#[doc = "Bit 0 - I2C Enabled"]
|
||||
#[inline(always)]
|
||||
pub fn clkenabled(&self) -> ClkenabledR {
|
||||
ClkenabledR::new((self.bits & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 1 - I2C Activated"]
|
||||
#[inline(always)]
|
||||
pub fn enabled(&self) -> EnabledR {
|
||||
EnabledR::new(((self.bits >> 1) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 2 - I2C Active"]
|
||||
#[inline(always)]
|
||||
pub fn enable(&self) -> EnableR {
|
||||
EnableR::new(((self.bits >> 2) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 3 - TX FIFIO Empty Mode"]
|
||||
#[inline(always)]
|
||||
pub fn txfemd(&self) -> TxfemdR {
|
||||
TxfemdR::new(((self.bits >> 3) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 4 - RX FIFO Full Mode"]
|
||||
#[inline(always)]
|
||||
pub fn rxffmd(&self) -> RxffmdR {
|
||||
RxffmdR::new(((self.bits >> 4) & 1) != 0)
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bit 0 - I2C Enabled"]
|
||||
#[inline(always)]
|
||||
#[must_use]
|
||||
pub fn clkenabled(&mut self) -> ClkenabledW<S0CtrlSpec> {
|
||||
ClkenabledW::new(self, 0)
|
||||
}
|
||||
#[doc = "Bit 1 - I2C Activated"]
|
||||
#[inline(always)]
|
||||
#[must_use]
|
||||
pub fn enabled(&mut self) -> EnabledW<S0CtrlSpec> {
|
||||
EnabledW::new(self, 1)
|
||||
}
|
||||
#[doc = "Bit 2 - I2C Active"]
|
||||
#[inline(always)]
|
||||
#[must_use]
|
||||
pub fn enable(&mut self) -> EnableW<S0CtrlSpec> {
|
||||
EnableW::new(self, 2)
|
||||
}
|
||||
#[doc = "Bit 3 - TX FIFIO Empty Mode"]
|
||||
#[inline(always)]
|
||||
#[must_use]
|
||||
pub fn txfemd(&mut self) -> TxfemdW<S0CtrlSpec> {
|
||||
TxfemdW::new(self, 3)
|
||||
}
|
||||
#[doc = "Bit 4 - RX FIFO Full Mode"]
|
||||
#[inline(always)]
|
||||
#[must_use]
|
||||
pub fn rxffmd(&mut self) -> RxffmdW<S0CtrlSpec> {
|
||||
RxffmdW::new(self, 4)
|
||||
}
|
||||
}
|
||||
#[doc = "Slave Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct S0CtrlSpec;
|
||||
impl crate::RegisterSpec for S0CtrlSpec {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`s0_ctrl::R`](R) reader structure"]
|
||||
impl crate::Readable for S0CtrlSpec {}
|
||||
#[doc = "`write(|w| ..)` method takes [`s0_ctrl::W`](W) writer structure"]
|
||||
impl crate::Writable for S0CtrlSpec {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets S0_CTRL to value 0"]
|
||||
impl crate::Resettable for S0CtrlSpec {
|
||||
const RESET_VALUE: u32 = 0;
|
||||
}
|
||||
27
va108xx/src/i2ca/s0_data.rs
Normal file
27
va108xx/src/i2ca/s0_data.rs
Normal file
@ -0,0 +1,27 @@
|
||||
#[doc = "Register `S0_DATA` reader"]
|
||||
pub type R = crate::R<S0DataSpec>;
|
||||
#[doc = "Register `S0_DATA` writer"]
|
||||
pub type W = crate::W<S0DataSpec>;
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
write!(f, "{}", self.bits())
|
||||
}
|
||||
}
|
||||
impl W {}
|
||||
#[doc = "Slave Data Input/Output\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_data::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_data::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct S0DataSpec;
|
||||
impl crate::RegisterSpec for S0DataSpec {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`s0_data::R`](R) reader structure"]
|
||||
impl crate::Readable for S0DataSpec {}
|
||||
#[doc = "`write(|w| ..)` method takes [`s0_data::W`](W) writer structure"]
|
||||
impl crate::Writable for S0DataSpec {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets S0_DATA to value 0"]
|
||||
impl crate::Resettable for S0DataSpec {
|
||||
const RESET_VALUE: u32 = 0;
|
||||
}
|
||||
35
va108xx/src/i2ca/s0_fifo_clr.rs
Normal file
35
va108xx/src/i2ca/s0_fifo_clr.rs
Normal file
@ -0,0 +1,35 @@
|
||||
#[doc = "Register `S0_FIFO_CLR` writer"]
|
||||
pub type W = crate::W<S0FifoClrSpec>;
|
||||
#[doc = "Field `RXFIFO` writer - Clear Rx FIFO"]
|
||||
pub type RxfifoW<'a, REG> = crate::BitWriter<'a, REG>;
|
||||
#[doc = "Field `TXFIFO` writer - Clear Tx FIFO"]
|
||||
pub type TxfifoW<'a, REG> = crate::BitWriter<'a, REG>;
|
||||
impl W {
|
||||
#[doc = "Bit 0 - Clear Rx FIFO"]
|
||||
#[inline(always)]
|
||||
#[must_use]
|
||||
pub fn rxfifo(&mut self) -> RxfifoW<S0FifoClrSpec> {
|
||||
RxfifoW::new(self, 0)
|
||||
}
|
||||
#[doc = "Bit 1 - Clear Tx FIFO"]
|
||||
#[inline(always)]
|
||||
#[must_use]
|
||||
pub fn txfifo(&mut self) -> TxfifoW<S0FifoClrSpec> {
|
||||
TxfifoW::new(self, 1)
|
||||
}
|
||||
}
|
||||
#[doc = "Slave Clear FIFO Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_fifo_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct S0FifoClrSpec;
|
||||
impl crate::RegisterSpec for S0FifoClrSpec {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`write(|w| ..)` method takes [`s0_fifo_clr::W`](W) writer structure"]
|
||||
impl crate::Writable for S0FifoClrSpec {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets S0_FIFO_CLR to value 0"]
|
||||
impl crate::Resettable for S0FifoClrSpec {
|
||||
const RESET_VALUE: u32 = 0;
|
||||
}
|
||||
265
va108xx/src/i2ca/s0_irq_enb.rs
Normal file
265
va108xx/src/i2ca/s0_irq_enb.rs
Normal file
@ -0,0 +1,265 @@
|
||||
#[doc = "Register `S0_IRQ_ENB` reader"]
|
||||
pub type R = crate::R<S0IrqEnbSpec>;
|
||||
#[doc = "Register `S0_IRQ_ENB` writer"]
|
||||
pub type W = crate::W<S0IrqEnbSpec>;
|
||||
#[doc = "Field `COMPLETED` reader - Controller Complted a Transaction"]
|
||||
pub type CompletedR = crate::BitReader;
|
||||
#[doc = "Field `COMPLETED` writer - Controller Complted a Transaction"]
|
||||
pub type CompletedW<'a, REG> = crate::BitWriter<'a, REG>;
|
||||
#[doc = "Field `IDLE` reader - Controller is Idle"]
|
||||
pub type IdleR = crate::BitReader;
|
||||
#[doc = "Field `IDLE` writer - Controller is Idle"]
|
||||
pub type IdleW<'a, REG> = crate::BitWriter<'a, REG>;
|
||||
#[doc = "Field `WAITING` reader - Controller is Waiting"]
|
||||
pub type WaitingR = crate::BitReader;
|
||||
#[doc = "Field `WAITING` writer - Controller is Waiting"]
|
||||
pub type WaitingW<'a, REG> = crate::BitWriter<'a, REG>;
|
||||
#[doc = "Field `TXSTALLED` reader - Controller is Tx Stalled"]
|
||||
pub type TxstalledR = crate::BitReader;
|
||||
#[doc = "Field `TXSTALLED` writer - Controller is Tx Stalled"]
|
||||
pub type TxstalledW<'a, REG> = crate::BitWriter<'a, REG>;
|
||||
#[doc = "Field `RXSTALLED` reader - Controller is Rx Stalled"]
|
||||
pub type RxstalledR = crate::BitReader;
|
||||
#[doc = "Field `RXSTALLED` writer - Controller is Rx Stalled"]
|
||||
pub type RxstalledW<'a, REG> = crate::BitWriter<'a, REG>;
|
||||
#[doc = "Field `ADDRESSMATCH` reader - I2C Address Match"]
|
||||
pub type AddressmatchR = crate::BitReader;
|
||||
#[doc = "Field `ADDRESSMATCH` writer - I2C Address Match"]
|
||||
pub type AddressmatchW<'a, REG> = crate::BitWriter<'a, REG>;
|
||||
#[doc = "Field `NACKDATA` reader - I2C Data was not Acknowledged"]
|
||||
pub type NackdataR = crate::BitReader;
|
||||
#[doc = "Field `NACKDATA` writer - I2C Data was not Acknowledged"]
|
||||
pub type NackdataW<'a, REG> = crate::BitWriter<'a, REG>;
|
||||
#[doc = "Field `RXDATAFIRST` reader - Pending Data is first Byte following Address"]
|
||||
pub type RxdatafirstR = crate::BitReader;
|
||||
#[doc = "Field `RXDATAFIRST` writer - Pending Data is first Byte following Address"]
|
||||
pub type RxdatafirstW<'a, REG> = crate::BitWriter<'a, REG>;
|
||||
#[doc = "Field `I2C_START` reader - I2C Start Condition"]
|
||||
pub type I2cStartR = crate::BitReader;
|
||||
#[doc = "Field `I2C_START` writer - I2C Start Condition"]
|
||||
pub type I2cStartW<'a, REG> = crate::BitWriter<'a, REG>;
|
||||
#[doc = "Field `I2C_STOP` reader - I2C Stop Condition"]
|
||||
pub type I2cStopR = crate::BitReader;
|
||||
#[doc = "Field `I2C_STOP` writer - I2C Stop Condition"]
|
||||
pub type I2cStopW<'a, REG> = crate::BitWriter<'a, REG>;
|
||||
#[doc = "Field `TXUNDERFLOW` reader - TX FIFO Underflowed"]
|
||||
pub type TxunderflowR = crate::BitReader;
|
||||
#[doc = "Field `TXUNDERFLOW` writer - TX FIFO Underflowed"]
|
||||
pub type TxunderflowW<'a, REG> = crate::BitWriter<'a, REG>;
|
||||
#[doc = "Field `RXOVERFLOW` reader - TX FIFO Overflowed"]
|
||||
pub type RxoverflowR = crate::BitReader;
|
||||
#[doc = "Field `RXOVERFLOW` writer - TX FIFO Overflowed"]
|
||||
pub type RxoverflowW<'a, REG> = crate::BitWriter<'a, REG>;
|
||||
#[doc = "Field `TXREADY` reader - TX FIFO Ready"]
|
||||
pub type TxreadyR = crate::BitReader;
|
||||
#[doc = "Field `TXREADY` writer - TX FIFO Ready"]
|
||||
pub type TxreadyW<'a, REG> = crate::BitWriter<'a, REG>;
|
||||
#[doc = "Field `RXREADY` reader - RX FIFO Ready"]
|
||||
pub type RxreadyR = crate::BitReader;
|
||||
#[doc = "Field `RXREADY` writer - RX FIFO Ready"]
|
||||
pub type RxreadyW<'a, REG> = crate::BitWriter<'a, REG>;
|
||||
#[doc = "Field `TXEMPTY` reader - TX FIFO Empty"]
|
||||
pub type TxemptyR = crate::BitReader;
|
||||
#[doc = "Field `TXEMPTY` writer - TX FIFO Empty"]
|
||||
pub type TxemptyW<'a, REG> = crate::BitWriter<'a, REG>;
|
||||
#[doc = "Field `RXFULL` reader - RX FIFO Full"]
|
||||
pub type RxfullR = crate::BitReader;
|
||||
#[doc = "Field `RXFULL` writer - RX FIFO Full"]
|
||||
pub type RxfullW<'a, REG> = crate::BitWriter<'a, REG>;
|
||||
impl R {
|
||||
#[doc = "Bit 0 - Controller Complted a Transaction"]
|
||||
#[inline(always)]
|
||||
pub fn completed(&self) -> CompletedR {
|
||||
CompletedR::new((self.bits & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 1 - Controller is Idle"]
|
||||
#[inline(always)]
|
||||
pub fn idle(&self) -> IdleR {
|
||||
IdleR::new(((self.bits >> 1) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 2 - Controller is Waiting"]
|
||||
#[inline(always)]
|
||||
pub fn waiting(&self) -> WaitingR {
|
||||
WaitingR::new(((self.bits >> 2) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 3 - Controller is Tx Stalled"]
|
||||
#[inline(always)]
|
||||
pub fn txstalled(&self) -> TxstalledR {
|
||||
TxstalledR::new(((self.bits >> 3) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 4 - Controller is Rx Stalled"]
|
||||
#[inline(always)]
|
||||
pub fn rxstalled(&self) -> RxstalledR {
|
||||
RxstalledR::new(((self.bits >> 4) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 5 - I2C Address Match"]
|
||||
#[inline(always)]
|
||||
pub fn addressmatch(&self) -> AddressmatchR {
|
||||
AddressmatchR::new(((self.bits >> 5) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 6 - I2C Data was not Acknowledged"]
|
||||
#[inline(always)]
|
||||
pub fn nackdata(&self) -> NackdataR {
|
||||
NackdataR::new(((self.bits >> 6) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 7 - Pending Data is first Byte following Address"]
|
||||
#[inline(always)]
|
||||
pub fn rxdatafirst(&self) -> RxdatafirstR {
|
||||
RxdatafirstR::new(((self.bits >> 7) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 8 - I2C Start Condition"]
|
||||
#[inline(always)]
|
||||
pub fn i2c_start(&self) -> I2cStartR {
|
||||
I2cStartR::new(((self.bits >> 8) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 9 - I2C Stop Condition"]
|
||||
#[inline(always)]
|
||||
pub fn i2c_stop(&self) -> I2cStopR {
|
||||
I2cStopR::new(((self.bits >> 9) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 10 - TX FIFO Underflowed"]
|
||||
#[inline(always)]
|
||||
pub fn txunderflow(&self) -> TxunderflowR {
|
||||
TxunderflowR::new(((self.bits >> 10) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 11 - TX FIFO Overflowed"]
|
||||
#[inline(always)]
|
||||
pub fn rxoverflow(&self) -> RxoverflowR {
|
||||
RxoverflowR::new(((self.bits >> 11) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 12 - TX FIFO Ready"]
|
||||
#[inline(always)]
|
||||
pub fn txready(&self) -> TxreadyR {
|
||||
TxreadyR::new(((self.bits >> 12) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 13 - RX FIFO Ready"]
|
||||
#[inline(always)]
|
||||
pub fn rxready(&self) -> RxreadyR {
|
||||
RxreadyR::new(((self.bits >> 13) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 14 - TX FIFO Empty"]
|
||||
#[inline(always)]
|
||||
pub fn txempty(&self) -> TxemptyR {
|
||||
TxemptyR::new(((self.bits >> 14) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 15 - RX FIFO Full"]
|
||||
#[inline(always)]
|
||||
pub fn rxfull(&self) -> RxfullR {
|
||||
RxfullR::new(((self.bits >> 15) & 1) != 0)
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bit 0 - Controller Complted a Transaction"]
|
||||
#[inline(always)]
|
||||
#[must_use]
|
||||
pub fn completed(&mut self) -> CompletedW<S0IrqEnbSpec> {
|
||||
CompletedW::new(self, 0)
|
||||
}
|
||||
#[doc = "Bit 1 - Controller is Idle"]
|
||||
#[inline(always)]
|
||||
#[must_use]
|
||||
pub fn idle(&mut self) -> IdleW<S0IrqEnbSpec> {
|
||||
IdleW::new(self, 1)
|
||||
}
|
||||
#[doc = "Bit 2 - Controller is Waiting"]
|
||||
#[inline(always)]
|
||||
#[must_use]
|
||||
pub fn waiting(&mut self) -> WaitingW<S0IrqEnbSpec> {
|
||||
WaitingW::new(self, 2)
|
||||
}
|
||||
#[doc = "Bit 3 - Controller is Tx Stalled"]
|
||||
#[inline(always)]
|
||||
#[must_use]
|
||||
pub fn txstalled(&mut self) -> TxstalledW<S0IrqEnbSpec> {
|
||||
TxstalledW::new(self, 3)
|
||||
}
|
||||
#[doc = "Bit 4 - Controller is Rx Stalled"]
|
||||
#[inline(always)]
|
||||
#[must_use]
|
||||
pub fn rxstalled(&mut self) -> RxstalledW<S0IrqEnbSpec> {
|
||||
RxstalledW::new(self, 4)
|
||||
}
|
||||
#[doc = "Bit 5 - I2C Address Match"]
|
||||
#[inline(always)]
|
||||
#[must_use]
|
||||
pub fn addressmatch(&mut self) -> AddressmatchW<S0IrqEnbSpec> {
|
||||
AddressmatchW::new(self, 5)
|
||||
}
|
||||
#[doc = "Bit 6 - I2C Data was not Acknowledged"]
|
||||
#[inline(always)]
|
||||
#[must_use]
|
||||
pub fn nackdata(&mut self) -> NackdataW<S0IrqEnbSpec> {
|
||||
NackdataW::new(self, 6)
|
||||
}
|
||||
#[doc = "Bit 7 - Pending Data is first Byte following Address"]
|
||||
#[inline(always)]
|
||||
#[must_use]
|
||||
pub fn rxdatafirst(&mut self) -> RxdatafirstW<S0IrqEnbSpec> {
|
||||
RxdatafirstW::new(self, 7)
|
||||
}
|
||||
#[doc = "Bit 8 - I2C Start Condition"]
|
||||
#[inline(always)]
|
||||
#[must_use]
|
||||
pub fn i2c_start(&mut self) -> I2cStartW<S0IrqEnbSpec> {
|
||||
I2cStartW::new(self, 8)
|
||||
}
|
||||
#[doc = "Bit 9 - I2C Stop Condition"]
|
||||
#[inline(always)]
|
||||
#[must_use]
|
||||
pub fn i2c_stop(&mut self) -> I2cStopW<S0IrqEnbSpec> {
|
||||
I2cStopW::new(self, 9)
|
||||
}
|
||||
#[doc = "Bit 10 - TX FIFO Underflowed"]
|
||||
#[inline(always)]
|
||||
#[must_use]
|
||||
pub fn txunderflow(&mut self) -> TxunderflowW<S0IrqEnbSpec> {
|
||||
TxunderflowW::new(self, 10)
|
||||
}
|
||||
#[doc = "Bit 11 - TX FIFO Overflowed"]
|
||||
#[inline(always)]
|
||||
#[must_use]
|
||||
pub fn rxoverflow(&mut self) -> RxoverflowW<S0IrqEnbSpec> {
|
||||
RxoverflowW::new(self, 11)
|
||||
}
|
||||
#[doc = "Bit 12 - TX FIFO Ready"]
|
||||
#[inline(always)]
|
||||
#[must_use]
|
||||
pub fn txready(&mut self) -> TxreadyW<S0IrqEnbSpec> {
|
||||
TxreadyW::new(self, 12)
|
||||
}
|
||||
#[doc = "Bit 13 - RX FIFO Ready"]
|
||||
#[inline(always)]
|
||||
#[must_use]
|
||||
pub fn rxready(&mut self) -> RxreadyW<S0IrqEnbSpec> {
|
||||
RxreadyW::new(self, 13)
|
||||
}
|
||||
#[doc = "Bit 14 - TX FIFO Empty"]
|
||||
#[inline(always)]
|
||||
#[must_use]
|
||||
pub fn txempty(&mut self) -> TxemptyW<S0IrqEnbSpec> {
|
||||
TxemptyW::new(self, 14)
|
||||
}
|
||||
#[doc = "Bit 15 - RX FIFO Full"]
|
||||
#[inline(always)]
|
||||
#[must_use]
|
||||
pub fn rxfull(&mut self) -> RxfullW<S0IrqEnbSpec> {
|
||||
RxfullW::new(self, 15)
|
||||
}
|
||||
}
|
||||
#[doc = "Slave Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_irq_enb::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_irq_enb::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct S0IrqEnbSpec;
|
||||
impl crate::RegisterSpec for S0IrqEnbSpec {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`s0_irq_enb::R`](R) reader structure"]
|
||||
impl crate::Readable for S0IrqEnbSpec {}
|
||||
#[doc = "`write(|w| ..)` method takes [`s0_irq_enb::W`](W) writer structure"]
|
||||
impl crate::Writable for S0IrqEnbSpec {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets S0_IRQ_ENB to value 0"]
|
||||
impl crate::Resettable for S0IrqEnbSpec {
|
||||
const RESET_VALUE: u32 = 0;
|
||||
}
|
||||
18
va108xx/src/i2ca/s0_lastaddress.rs
Normal file
18
va108xx/src/i2ca/s0_lastaddress.rs
Normal file
@ -0,0 +1,18 @@
|
||||
#[doc = "Register `S0_LASTADDRESS` reader"]
|
||||
pub type R = crate::R<S0LastaddressSpec>;
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
write!(f, "{}", self.bits())
|
||||
}
|
||||
}
|
||||
#[doc = "Slave I2C Last Address value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_lastaddress::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct S0LastaddressSpec;
|
||||
impl crate::RegisterSpec for S0LastaddressSpec {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`s0_lastaddress::R`](R) reader structure"]
|
||||
impl crate::Readable for S0LastaddressSpec {}
|
||||
#[doc = "`reset()` method sets S0_LASTADDRESS to value 0"]
|
||||
impl crate::Resettable for S0LastaddressSpec {
|
||||
const RESET_VALUE: u32 = 0;
|
||||
}
|
||||
27
va108xx/src/i2ca/s0_maxwords.rs
Normal file
27
va108xx/src/i2ca/s0_maxwords.rs
Normal file
@ -0,0 +1,27 @@
|
||||
#[doc = "Register `S0_MAXWORDS` reader"]
|
||||
pub type R = crate::R<S0MaxwordsSpec>;
|
||||
#[doc = "Register `S0_MAXWORDS` writer"]
|
||||
pub type W = crate::W<S0MaxwordsSpec>;
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
write!(f, "{}", self.bits())
|
||||
}
|
||||
}
|
||||
impl W {}
|
||||
#[doc = "Slave MaxWords Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_maxwords::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_maxwords::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct S0MaxwordsSpec;
|
||||
impl crate::RegisterSpec for S0MaxwordsSpec {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`s0_maxwords::R`](R) reader structure"]
|
||||
impl crate::Readable for S0MaxwordsSpec {}
|
||||
#[doc = "`write(|w| ..)` method takes [`s0_maxwords::W`](W) writer structure"]
|
||||
impl crate::Writable for S0MaxwordsSpec {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets S0_MAXWORDS to value 0"]
|
||||
impl crate::Resettable for S0MaxwordsSpec {
|
||||
const RESET_VALUE: u32 = 0;
|
||||
}
|
||||
18
va108xx/src/i2ca/s0_rxcount.rs
Normal file
18
va108xx/src/i2ca/s0_rxcount.rs
Normal file
@ -0,0 +1,18 @@
|
||||
#[doc = "Register `S0_RXCOUNT` reader"]
|
||||
pub type R = crate::R<S0RxcountSpec>;
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
write!(f, "{}", self.bits())
|
||||
}
|
||||
}
|
||||
#[doc = "Slave RX Count Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_rxcount::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct S0RxcountSpec;
|
||||
impl crate::RegisterSpec for S0RxcountSpec {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`s0_rxcount::R`](R) reader structure"]
|
||||
impl crate::Readable for S0RxcountSpec {}
|
||||
#[doc = "`reset()` method sets S0_RXCOUNT to value 0"]
|
||||
impl crate::Resettable for S0RxcountSpec {
|
||||
const RESET_VALUE: u32 = 0;
|
||||
}
|
||||
27
va108xx/src/i2ca/s0_rxfifoirqtrg.rs
Normal file
27
va108xx/src/i2ca/s0_rxfifoirqtrg.rs
Normal file
@ -0,0 +1,27 @@
|
||||
#[doc = "Register `S0_RXFIFOIRQTRG` reader"]
|
||||
pub type R = crate::R<S0RxfifoirqtrgSpec>;
|
||||
#[doc = "Register `S0_RXFIFOIRQTRG` writer"]
|
||||
pub type W = crate::W<S0RxfifoirqtrgSpec>;
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
write!(f, "{}", self.bits())
|
||||
}
|
||||
}
|
||||
impl W {}
|
||||
#[doc = "Slave Rx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_rxfifoirqtrg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_rxfifoirqtrg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct S0RxfifoirqtrgSpec;
|
||||
impl crate::RegisterSpec for S0RxfifoirqtrgSpec {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`s0_rxfifoirqtrg::R`](R) reader structure"]
|
||||
impl crate::Readable for S0RxfifoirqtrgSpec {}
|
||||
#[doc = "`write(|w| ..)` method takes [`s0_rxfifoirqtrg::W`](W) writer structure"]
|
||||
impl crate::Writable for S0RxfifoirqtrgSpec {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets S0_RXFIFOIRQTRG to value 0"]
|
||||
impl crate::Resettable for S0RxfifoirqtrgSpec {
|
||||
const RESET_VALUE: u32 = 0;
|
||||
}
|
||||
18
va108xx/src/i2ca/s0_state.rs
Normal file
18
va108xx/src/i2ca/s0_state.rs
Normal file
@ -0,0 +1,18 @@
|
||||
#[doc = "Register `S0_STATE` reader"]
|
||||
pub type R = crate::R<S0StateSpec>;
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
write!(f, "{}", self.bits())
|
||||
}
|
||||
}
|
||||
#[doc = "Internal STATE of I2C Slave Controller\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_state::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct S0StateSpec;
|
||||
impl crate::RegisterSpec for S0StateSpec {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`s0_state::R`](R) reader structure"]
|
||||
impl crate::Readable for S0StateSpec {}
|
||||
#[doc = "`reset()` method sets S0_STATE to value 0"]
|
||||
impl crate::Resettable for S0StateSpec {
|
||||
const RESET_VALUE: u32 = 0;
|
||||
}
|
||||
134
va108xx/src/i2ca/s0_status.rs
Normal file
134
va108xx/src/i2ca/s0_status.rs
Normal file
@ -0,0 +1,134 @@
|
||||
#[doc = "Register `S0_STATUS` reader"]
|
||||
pub type R = crate::R<S0StatusSpec>;
|
||||
#[doc = "Field `COMPLETED` reader - Controller Complted a Transaction"]
|
||||
pub type CompletedR = crate::BitReader;
|
||||
#[doc = "Field `IDLE` reader - Controller is Idle"]
|
||||
pub type IdleR = crate::BitReader;
|
||||
#[doc = "Field `WAITING` reader - Controller is Waiting"]
|
||||
pub type WaitingR = crate::BitReader;
|
||||
#[doc = "Field `TXSTALLED` reader - Controller is Tx Stalled"]
|
||||
pub type TxstalledR = crate::BitReader;
|
||||
#[doc = "Field `RXSTALLED` reader - Controller is Rx Stalled"]
|
||||
pub type RxstalledR = crate::BitReader;
|
||||
#[doc = "Field `ADDRESSMATCH` reader - I2C Address Match"]
|
||||
pub type AddressmatchR = crate::BitReader;
|
||||
#[doc = "Field `NACKDATA` reader - I2C Data was not Acknowledged"]
|
||||
pub type NackdataR = crate::BitReader;
|
||||
#[doc = "Field `RXDATAFIRST` reader - Pending Data is first Byte following Address"]
|
||||
pub type RxdatafirstR = crate::BitReader;
|
||||
#[doc = "Field `RXNEMPTY` reader - RX FIFO is Not Empty"]
|
||||
pub type RxnemptyR = crate::BitReader;
|
||||
#[doc = "Field `RXFULL` reader - RX FIFO is Full"]
|
||||
pub type RxfullR = crate::BitReader;
|
||||
#[doc = "Field `RXTRIGGER` reader - RX FIFO Above Trigger Level"]
|
||||
pub type RxtriggerR = crate::BitReader;
|
||||
#[doc = "Field `TXEMPTY` reader - TX FIFO is Empty"]
|
||||
pub type TxemptyR = crate::BitReader;
|
||||
#[doc = "Field `TXNFULL` reader - TX FIFO is Full"]
|
||||
pub type TxnfullR = crate::BitReader;
|
||||
#[doc = "Field `TXTRIGGER` reader - TX FIFO Below Trigger Level"]
|
||||
pub type TxtriggerR = crate::BitReader;
|
||||
#[doc = "Field `RAW_BUSY` reader - I2C Raw Busy value"]
|
||||
pub type RawBusyR = crate::BitReader;
|
||||
#[doc = "Field `RAW_SDA` reader - I2C Raw SDA value"]
|
||||
pub type RawSdaR = crate::BitReader;
|
||||
#[doc = "Field `RAW_SCL` reader - I2C Raw SCL value"]
|
||||
pub type RawSclR = crate::BitReader;
|
||||
impl R {
|
||||
#[doc = "Bit 0 - Controller Complted a Transaction"]
|
||||
#[inline(always)]
|
||||
pub fn completed(&self) -> CompletedR {
|
||||
CompletedR::new((self.bits & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 1 - Controller is Idle"]
|
||||
#[inline(always)]
|
||||
pub fn idle(&self) -> IdleR {
|
||||
IdleR::new(((self.bits >> 1) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 2 - Controller is Waiting"]
|
||||
#[inline(always)]
|
||||
pub fn waiting(&self) -> WaitingR {
|
||||
WaitingR::new(((self.bits >> 2) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 3 - Controller is Tx Stalled"]
|
||||
#[inline(always)]
|
||||
pub fn txstalled(&self) -> TxstalledR {
|
||||
TxstalledR::new(((self.bits >> 3) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 4 - Controller is Rx Stalled"]
|
||||
#[inline(always)]
|
||||
pub fn rxstalled(&self) -> RxstalledR {
|
||||
RxstalledR::new(((self.bits >> 4) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 5 - I2C Address Match"]
|
||||
#[inline(always)]
|
||||
pub fn addressmatch(&self) -> AddressmatchR {
|
||||
AddressmatchR::new(((self.bits >> 5) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 6 - I2C Data was not Acknowledged"]
|
||||
#[inline(always)]
|
||||
pub fn nackdata(&self) -> NackdataR {
|
||||
NackdataR::new(((self.bits >> 6) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 7 - Pending Data is first Byte following Address"]
|
||||
#[inline(always)]
|
||||
pub fn rxdatafirst(&self) -> RxdatafirstR {
|
||||
RxdatafirstR::new(((self.bits >> 7) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 8 - RX FIFO is Not Empty"]
|
||||
#[inline(always)]
|
||||
pub fn rxnempty(&self) -> RxnemptyR {
|
||||
RxnemptyR::new(((self.bits >> 8) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 9 - RX FIFO is Full"]
|
||||
#[inline(always)]
|
||||
pub fn rxfull(&self) -> RxfullR {
|
||||
RxfullR::new(((self.bits >> 9) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 11 - RX FIFO Above Trigger Level"]
|
||||
#[inline(always)]
|
||||
pub fn rxtrigger(&self) -> RxtriggerR {
|
||||
RxtriggerR::new(((self.bits >> 11) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 12 - TX FIFO is Empty"]
|
||||
#[inline(always)]
|
||||
pub fn txempty(&self) -> TxemptyR {
|
||||
TxemptyR::new(((self.bits >> 12) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 13 - TX FIFO is Full"]
|
||||
#[inline(always)]
|
||||
pub fn txnfull(&self) -> TxnfullR {
|
||||
TxnfullR::new(((self.bits >> 13) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 15 - TX FIFO Below Trigger Level"]
|
||||
#[inline(always)]
|
||||
pub fn txtrigger(&self) -> TxtriggerR {
|
||||
TxtriggerR::new(((self.bits >> 15) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 29 - I2C Raw Busy value"]
|
||||
#[inline(always)]
|
||||
pub fn raw_busy(&self) -> RawBusyR {
|
||||
RawBusyR::new(((self.bits >> 29) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 30 - I2C Raw SDA value"]
|
||||
#[inline(always)]
|
||||
pub fn raw_sda(&self) -> RawSdaR {
|
||||
RawSdaR::new(((self.bits >> 30) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 31 - I2C Raw SCL value"]
|
||||
#[inline(always)]
|
||||
pub fn raw_scl(&self) -> RawSclR {
|
||||
RawSclR::new(((self.bits >> 31) & 1) != 0)
|
||||
}
|
||||
}
|
||||
#[doc = "Slave I2C Controller Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct S0StatusSpec;
|
||||
impl crate::RegisterSpec for S0StatusSpec {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`s0_status::R`](R) reader structure"]
|
||||
impl crate::Readable for S0StatusSpec {}
|
||||
#[doc = "`reset()` method sets S0_STATUS to value 0"]
|
||||
impl crate::Resettable for S0StatusSpec {
|
||||
const RESET_VALUE: u32 = 0;
|
||||
}
|
||||
18
va108xx/src/i2ca/s0_txcount.rs
Normal file
18
va108xx/src/i2ca/s0_txcount.rs
Normal file
@ -0,0 +1,18 @@
|
||||
#[doc = "Register `S0_TXCOUNT` reader"]
|
||||
pub type R = crate::R<S0TxcountSpec>;
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
write!(f, "{}", self.bits())
|
||||
}
|
||||
}
|
||||
#[doc = "Slave TX Count Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_txcount::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct S0TxcountSpec;
|
||||
impl crate::RegisterSpec for S0TxcountSpec {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`s0_txcount::R`](R) reader structure"]
|
||||
impl crate::Readable for S0TxcountSpec {}
|
||||
#[doc = "`reset()` method sets S0_TXCOUNT to value 0"]
|
||||
impl crate::Resettable for S0TxcountSpec {
|
||||
const RESET_VALUE: u32 = 0;
|
||||
}
|
||||
27
va108xx/src/i2ca/s0_txfifoirqtrg.rs
Normal file
27
va108xx/src/i2ca/s0_txfifoirqtrg.rs
Normal file
@ -0,0 +1,27 @@
|
||||
#[doc = "Register `S0_TXFIFOIRQTRG` reader"]
|
||||
pub type R = crate::R<S0TxfifoirqtrgSpec>;
|
||||
#[doc = "Register `S0_TXFIFOIRQTRG` writer"]
|
||||
pub type W = crate::W<S0TxfifoirqtrgSpec>;
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
write!(f, "{}", self.bits())
|
||||
}
|
||||
}
|
||||
impl W {}
|
||||
#[doc = "Slave Tx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_txfifoirqtrg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_txfifoirqtrg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct S0TxfifoirqtrgSpec;
|
||||
impl crate::RegisterSpec for S0TxfifoirqtrgSpec {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`s0_txfifoirqtrg::R`](R) reader structure"]
|
||||
impl crate::Readable for S0TxfifoirqtrgSpec {}
|
||||
#[doc = "`write(|w| ..)` method takes [`s0_txfifoirqtrg::W`](W) writer structure"]
|
||||
impl crate::Writable for S0TxfifoirqtrgSpec {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets S0_TXFIFOIRQTRG to value 0"]
|
||||
impl crate::Resettable for S0TxfifoirqtrgSpec {
|
||||
const RESET_VALUE: u32 = 0;
|
||||
}
|
||||
18
va108xx/src/i2ca/state.rs
Normal file
18
va108xx/src/i2ca/state.rs
Normal file
@ -0,0 +1,18 @@
|
||||
#[doc = "Register `STATE` reader"]
|
||||
pub type R = crate::R<StateSpec>;
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
write!(f, "{}", self.bits())
|
||||
}
|
||||
}
|
||||
#[doc = "Internal STATE of I2C Master Controller\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`state::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct StateSpec;
|
||||
impl crate::RegisterSpec for StateSpec {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`state::R`](R) reader structure"]
|
||||
impl crate::Readable for StateSpec {}
|
||||
#[doc = "`reset()` method sets STATE to value 0"]
|
||||
impl crate::Resettable for StateSpec {
|
||||
const RESET_VALUE: u32 = 0;
|
||||
}
|
||||
120
va108xx/src/i2ca/status.rs
Normal file
120
va108xx/src/i2ca/status.rs
Normal file
@ -0,0 +1,120 @@
|
||||
#[doc = "Register `STATUS` reader"]
|
||||
pub type R = crate::R<StatusSpec>;
|
||||
#[doc = "Field `I2C_IDLE` reader - I2C bus is Idle"]
|
||||
pub type I2cIdleR = crate::BitReader;
|
||||
#[doc = "Field `IDLE` reader - Controller is Idle"]
|
||||
pub type IdleR = crate::BitReader;
|
||||
#[doc = "Field `WAITING` reader - Controller is Waiting"]
|
||||
pub type WaitingR = crate::BitReader;
|
||||
#[doc = "Field `STALLED` reader - Controller is Stalled"]
|
||||
pub type StalledR = crate::BitReader;
|
||||
#[doc = "Field `ARBLOST` reader - I2C Arbitration was lost"]
|
||||
pub type ArblostR = crate::BitReader;
|
||||
#[doc = "Field `NACKADDR` reader - I2C Address was not Acknowledged"]
|
||||
pub type NackaddrR = crate::BitReader;
|
||||
#[doc = "Field `NACKDATA` reader - I2C Data was not Acknowledged"]
|
||||
pub type NackdataR = crate::BitReader;
|
||||
#[doc = "Field `RXNEMPTY` reader - RX FIFO is Not Empty"]
|
||||
pub type RxnemptyR = crate::BitReader;
|
||||
#[doc = "Field `RXFULL` reader - RX FIFO is Full"]
|
||||
pub type RxfullR = crate::BitReader;
|
||||
#[doc = "Field `RXTRIGGER` reader - RX FIFO Above Trigger Level"]
|
||||
pub type RxtriggerR = crate::BitReader;
|
||||
#[doc = "Field `TXEMPTY` reader - TX FIFO is Empty"]
|
||||
pub type TxemptyR = crate::BitReader;
|
||||
#[doc = "Field `TXNFULL` reader - TX FIFO is Full"]
|
||||
pub type TxnfullR = crate::BitReader;
|
||||
#[doc = "Field `TXTRIGGER` reader - TX FIFO Below Trigger Level"]
|
||||
pub type TxtriggerR = crate::BitReader;
|
||||
#[doc = "Field `RAW_SDA` reader - I2C Raw SDA value"]
|
||||
pub type RawSdaR = crate::BitReader;
|
||||
#[doc = "Field `RAW_SCL` reader - I2C Raw SCL value"]
|
||||
pub type RawSclR = crate::BitReader;
|
||||
impl R {
|
||||
#[doc = "Bit 0 - I2C bus is Idle"]
|
||||
#[inline(always)]
|
||||
pub fn i2c_idle(&self) -> I2cIdleR {
|
||||
I2cIdleR::new((self.bits & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 1 - Controller is Idle"]
|
||||
#[inline(always)]
|
||||
pub fn idle(&self) -> IdleR {
|
||||
IdleR::new(((self.bits >> 1) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 2 - Controller is Waiting"]
|
||||
#[inline(always)]
|
||||
pub fn waiting(&self) -> WaitingR {
|
||||
WaitingR::new(((self.bits >> 2) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 3 - Controller is Stalled"]
|
||||
#[inline(always)]
|
||||
pub fn stalled(&self) -> StalledR {
|
||||
StalledR::new(((self.bits >> 3) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 4 - I2C Arbitration was lost"]
|
||||
#[inline(always)]
|
||||
pub fn arblost(&self) -> ArblostR {
|
||||
ArblostR::new(((self.bits >> 4) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 5 - I2C Address was not Acknowledged"]
|
||||
#[inline(always)]
|
||||
pub fn nackaddr(&self) -> NackaddrR {
|
||||
NackaddrR::new(((self.bits >> 5) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 6 - I2C Data was not Acknowledged"]
|
||||
#[inline(always)]
|
||||
pub fn nackdata(&self) -> NackdataR {
|
||||
NackdataR::new(((self.bits >> 6) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 8 - RX FIFO is Not Empty"]
|
||||
#[inline(always)]
|
||||
pub fn rxnempty(&self) -> RxnemptyR {
|
||||
RxnemptyR::new(((self.bits >> 8) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 9 - RX FIFO is Full"]
|
||||
#[inline(always)]
|
||||
pub fn rxfull(&self) -> RxfullR {
|
||||
RxfullR::new(((self.bits >> 9) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 11 - RX FIFO Above Trigger Level"]
|
||||
#[inline(always)]
|
||||
pub fn rxtrigger(&self) -> RxtriggerR {
|
||||
RxtriggerR::new(((self.bits >> 11) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 12 - TX FIFO is Empty"]
|
||||
#[inline(always)]
|
||||
pub fn txempty(&self) -> TxemptyR {
|
||||
TxemptyR::new(((self.bits >> 12) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 13 - TX FIFO is Full"]
|
||||
#[inline(always)]
|
||||
pub fn txnfull(&self) -> TxnfullR {
|
||||
TxnfullR::new(((self.bits >> 13) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 15 - TX FIFO Below Trigger Level"]
|
||||
#[inline(always)]
|
||||
pub fn txtrigger(&self) -> TxtriggerR {
|
||||
TxtriggerR::new(((self.bits >> 15) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 30 - I2C Raw SDA value"]
|
||||
#[inline(always)]
|
||||
pub fn raw_sda(&self) -> RawSdaR {
|
||||
RawSdaR::new(((self.bits >> 30) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 31 - I2C Raw SCL value"]
|
||||
#[inline(always)]
|
||||
pub fn raw_scl(&self) -> RawSclR {
|
||||
RawSclR::new(((self.bits >> 31) & 1) != 0)
|
||||
}
|
||||
}
|
||||
#[doc = "I2C Controller Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct StatusSpec;
|
||||
impl crate::RegisterSpec for StatusSpec {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`status::R`](R) reader structure"]
|
||||
impl crate::Readable for StatusSpec {}
|
||||
#[doc = "`reset()` method sets STATUS to value 0"]
|
||||
impl crate::Resettable for StatusSpec {
|
||||
const RESET_VALUE: u32 = 0;
|
||||
}
|
||||
27
va108xx/src/i2ca/tmconfig.rs
Normal file
27
va108xx/src/i2ca/tmconfig.rs
Normal file
@ -0,0 +1,27 @@
|
||||
#[doc = "Register `TMCONFIG` reader"]
|
||||
pub type R = crate::R<TmconfigSpec>;
|
||||
#[doc = "Register `TMCONFIG` writer"]
|
||||
pub type W = crate::W<TmconfigSpec>;
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
write!(f, "{}", self.bits())
|
||||
}
|
||||
}
|
||||
impl W {}
|
||||
#[doc = "Timing Config Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tmconfig::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tmconfig::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct TmconfigSpec;
|
||||
impl crate::RegisterSpec for TmconfigSpec {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`tmconfig::R`](R) reader structure"]
|
||||
impl crate::Readable for TmconfigSpec {}
|
||||
#[doc = "`write(|w| ..)` method takes [`tmconfig::W`](W) writer structure"]
|
||||
impl crate::Writable for TmconfigSpec {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets TMCONFIG to value 0"]
|
||||
impl crate::Resettable for TmconfigSpec {
|
||||
const RESET_VALUE: u32 = 0;
|
||||
}
|
||||
18
va108xx/src/i2ca/txcount.rs
Normal file
18
va108xx/src/i2ca/txcount.rs
Normal file
@ -0,0 +1,18 @@
|
||||
#[doc = "Register `TXCOUNT` reader"]
|
||||
pub type R = crate::R<TxcountSpec>;
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
write!(f, "{}", self.bits())
|
||||
}
|
||||
}
|
||||
#[doc = "TX Count Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txcount::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct TxcountSpec;
|
||||
impl crate::RegisterSpec for TxcountSpec {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`txcount::R`](R) reader structure"]
|
||||
impl crate::Readable for TxcountSpec {}
|
||||
#[doc = "`reset()` method sets TXCOUNT to value 0"]
|
||||
impl crate::Resettable for TxcountSpec {
|
||||
const RESET_VALUE: u32 = 0;
|
||||
}
|
||||
27
va108xx/src/i2ca/txfifoirqtrg.rs
Normal file
27
va108xx/src/i2ca/txfifoirqtrg.rs
Normal file
@ -0,0 +1,27 @@
|
||||
#[doc = "Register `TXFIFOIRQTRG` reader"]
|
||||
pub type R = crate::R<TxfifoirqtrgSpec>;
|
||||
#[doc = "Register `TXFIFOIRQTRG` writer"]
|
||||
pub type W = crate::W<TxfifoirqtrgSpec>;
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
write!(f, "{}", self.bits())
|
||||
}
|
||||
}
|
||||
impl W {}
|
||||
#[doc = "Tx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txfifoirqtrg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txfifoirqtrg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct TxfifoirqtrgSpec;
|
||||
impl crate::RegisterSpec for TxfifoirqtrgSpec {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`txfifoirqtrg::R`](R) reader structure"]
|
||||
impl crate::Readable for TxfifoirqtrgSpec {}
|
||||
#[doc = "`write(|w| ..)` method takes [`txfifoirqtrg::W`](W) writer structure"]
|
||||
impl crate::Writable for TxfifoirqtrgSpec {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets TXFIFOIRQTRG to value 0"]
|
||||
impl crate::Resettable for TxfifoirqtrgSpec {
|
||||
const RESET_VALUE: u32 = 0;
|
||||
}
|
||||
27
va108xx/src/i2ca/words.rs
Normal file
27
va108xx/src/i2ca/words.rs
Normal file
@ -0,0 +1,27 @@
|
||||
#[doc = "Register `WORDS` reader"]
|
||||
pub type R = crate::R<WordsSpec>;
|
||||
#[doc = "Register `WORDS` writer"]
|
||||
pub type W = crate::W<WordsSpec>;
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
write!(f, "{}", self.bits())
|
||||
}
|
||||
}
|
||||
impl W {}
|
||||
#[doc = "Word Count value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`words::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`words::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct WordsSpec;
|
||||
impl crate::RegisterSpec for WordsSpec {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`words::R`](R) reader structure"]
|
||||
impl crate::Readable for WordsSpec {}
|
||||
#[doc = "`write(|w| ..)` method takes [`words::W`](W) writer structure"]
|
||||
impl crate::Writable for WordsSpec {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets WORDS to value 0"]
|
||||
impl crate::Resettable for WordsSpec {
|
||||
const RESET_VALUE: u32 = 0;
|
||||
}
|
||||
Reference in New Issue
Block a user