New VA108xx Rust workspace structure + dependency updates

- The workspace is now a monorepo without submodules. The HAL, PAC and BSP
  are integrated directly
- Update all dependencies: embedded-hal v1 and RTIC v2

va108xx/src/porta/datain.rs

@@ -0,0 +1,18 @@
+#[doc = "Register `DATAIN` reader"]
+pub type R = crate::R<DatainSpec>;
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        write!(f, "{}", self.bits())
+    }
+}
+#[doc = "Data In Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`datain::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct DatainSpec;
+impl crate::RegisterSpec for DatainSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`datain::R`](R) reader structure"]
+impl crate::Readable for DatainSpec {}
+#[doc = "`reset()` method sets DATAIN to value 0"]
+impl crate::Resettable for DatainSpec {
+    const RESET_VALUE: u32 = 0;
+}

va108xx/src/porta/datainbyte.rs

@@ -0,0 +1,19 @@
+#[doc = "Register `DATAINBYTE[%s]` reader"]
+pub type R = crate::R<DatainbyteSpec>;
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        write!(f, "{}", self.bits())
+    }
+}
+#[doc = "Data In Register by Byte\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`datainbyte::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct DatainbyteSpec;
+impl crate::RegisterSpec for DatainbyteSpec {
+    type Ux = u8;
+}
+#[doc = "`read()` method returns [`datainbyte::R`](R) reader structure"]
+impl crate::Readable for DatainbyteSpec {}
+#[doc = "`reset()` method sets DATAINBYTE[%s]
+to value 0"]
+impl crate::Resettable for DatainbyteSpec {
+    const RESET_VALUE: u8 = 0;
+}

va108xx/src/porta/datamask.rs

@@ -0,0 +1,27 @@
+#[doc = "Register `DATAMASK` reader"]
+pub type R = crate::R<DatamaskSpec>;
+#[doc = "Register `DATAMASK` writer"]
+pub type W = crate::W<DatamaskSpec>;
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        write!(f, "{}", self.bits())
+    }
+}
+impl W {}
+#[doc = "Data mask Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`datamask::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`datamask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct DatamaskSpec;
+impl crate::RegisterSpec for DatamaskSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`datamask::R`](R) reader structure"]
+impl crate::Readable for DatamaskSpec {}
+#[doc = "`write(|w| ..)` method takes [`datamask::W`](W) writer structure"]
+impl crate::Writable for DatamaskSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets DATAMASK to value 0"]
+impl crate::Resettable for DatamaskSpec {
+    const RESET_VALUE: u32 = 0;
+}

va108xx/src/porta/datamaskbyte.rs

@@ -0,0 +1,28 @@
+#[doc = "Register `DATAMASKBYTE[%s]` reader"]
+pub type R = crate::R<DatamaskbyteSpec>;
+#[doc = "Register `DATAMASKBYTE[%s]` writer"]
+pub type W = crate::W<DatamaskbyteSpec>;
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        write!(f, "{}", self.bits())
+    }
+}
+impl W {}
+#[doc = "Data Out Register by Byte\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`datamaskbyte::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`datamaskbyte::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct DatamaskbyteSpec;
+impl crate::RegisterSpec for DatamaskbyteSpec {
+    type Ux = u8;
+}
+#[doc = "`read()` method returns [`datamaskbyte::R`](R) reader structure"]
+impl crate::Readable for DatamaskbyteSpec {}
+#[doc = "`write(|w| ..)` method takes [`datamaskbyte::W`](W) writer structure"]
+impl crate::Writable for DatamaskbyteSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u8 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u8 = 0;
+}
+#[doc = "`reset()` method sets DATAMASKBYTE[%s]
+to value 0"]
+impl crate::Resettable for DatamaskbyteSpec {
+    const RESET_VALUE: u8 = 0;
+}

va108xx/src/porta/dataout.rs

@@ -0,0 +1,23 @@
+#[doc = "Register `DATAOUT` writer"]
+pub type W = crate::W<DataoutSpec>;
+impl core::fmt::Debug for crate::generic::Reg<DataoutSpec> {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        write!(f, "(not readable)")
+    }
+}
+impl W {}
+#[doc = "Data Out Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dataout::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct DataoutSpec;
+impl crate::RegisterSpec for DataoutSpec {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [`dataout::W`](W) writer structure"]
+impl crate::Writable for DataoutSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets DATAOUT to value 0"]
+impl crate::Resettable for DataoutSpec {
+    const RESET_VALUE: u32 = 0;
+}

va108xx/src/porta/dataoutbyte.rs

@@ -0,0 +1,24 @@
+#[doc = "Register `DATAOUTBYTE[%s]` writer"]
+pub type W = crate::W<DataoutbyteSpec>;
+impl core::fmt::Debug for crate::generic::Reg<DataoutbyteSpec> {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        write!(f, "(not readable)")
+    }
+}
+impl W {}
+#[doc = "Data Out Register by Byte\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dataoutbyte::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct DataoutbyteSpec;
+impl crate::RegisterSpec for DataoutbyteSpec {
+    type Ux = u8;
+}
+#[doc = "`write(|w| ..)` method takes [`dataoutbyte::W`](W) writer structure"]
+impl crate::Writable for DataoutbyteSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u8 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u8 = 0;
+}
+#[doc = "`reset()` method sets DATAOUTBYTE[%s]
+to value 0"]
+impl crate::Resettable for DataoutbyteSpec {
+    const RESET_VALUE: u8 = 0;
+}

va108xx/src/porta/edge_status.rs

@@ -0,0 +1,27 @@
+#[doc = "Register `EDGE_STATUS` reader"]
+pub type R = crate::R<EdgeStatusSpec>;
+#[doc = "Register `EDGE_STATUS` writer"]
+pub type W = crate::W<EdgeStatusSpec>;
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        write!(f, "{}", self.bits())
+    }
+}
+impl W {}
+#[doc = "Edge Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`edge_status::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`edge_status::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct EdgeStatusSpec;
+impl crate::RegisterSpec for EdgeStatusSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`edge_status::R`](R) reader structure"]
+impl crate::Readable for EdgeStatusSpec {}
+#[doc = "`write(|w| ..)` method takes [`edge_status::W`](W) writer structure"]
+impl crate::Writable for EdgeStatusSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets EDGE_STATUS to value 0"]
+impl crate::Resettable for EdgeStatusSpec {
+    const RESET_VALUE: u32 = 0;
+}

va108xx/src/porta/irq_edge.rs

@@ -0,0 +1,27 @@
+#[doc = "Register `IRQ_EDGE` reader"]
+pub type R = crate::R<IrqEdgeSpec>;
+#[doc = "Register `IRQ_EDGE` writer"]
+pub type W = crate::W<IrqEdgeSpec>;
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        write!(f, "{}", self.bits())
+    }
+}
+impl W {}
+#[doc = "Interrupt Both Edge Register (1:Both Edges, 0:Single Edge)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_edge::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_edge::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct IrqEdgeSpec;
+impl crate::RegisterSpec for IrqEdgeSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`irq_edge::R`](R) reader structure"]
+impl crate::Readable for IrqEdgeSpec {}
+#[doc = "`write(|w| ..)` method takes [`irq_edge::W`](W) writer structure"]
+impl crate::Writable for IrqEdgeSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets IRQ_EDGE to value 0"]
+impl crate::Resettable for IrqEdgeSpec {
+    const RESET_VALUE: u32 = 0;
+}

va108xx/src/porta/irq_enb.rs

@@ -0,0 +1,27 @@
+#[doc = "Register `IRQ_ENB` reader"]
+pub type R = crate::R<IrqEnbSpec>;
+#[doc = "Register `IRQ_ENB` writer"]
+pub type W = crate::W<IrqEnbSpec>;
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        write!(f, "{}", self.bits())
+    }
+}
+impl W {}
+#[doc = "Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_enb::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_enb::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct IrqEnbSpec;
+impl crate::RegisterSpec for IrqEnbSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`irq_enb::R`](R) reader structure"]
+impl crate::Readable for IrqEnbSpec {}
+#[doc = "`write(|w| ..)` method takes [`irq_enb::W`](W) writer structure"]
+impl crate::Writable for IrqEnbSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets IRQ_ENB to value 0"]
+impl crate::Resettable for IrqEnbSpec {
+    const RESET_VALUE: u32 = 0;
+}

va108xx/src/porta/irq_end.rs

@@ -0,0 +1,18 @@
+#[doc = "Register `IRQ_END` reader"]
+pub type R = crate::R<IrqEndSpec>;
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        write!(f, "{}", self.bits())
+    }
+}
+#[doc = "Masked Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_end::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct IrqEndSpec;
+impl crate::RegisterSpec for IrqEndSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`irq_end::R`](R) reader structure"]
+impl crate::Readable for IrqEndSpec {}
+#[doc = "`reset()` method sets IRQ_END to value 0"]
+impl crate::Resettable for IrqEndSpec {
+    const RESET_VALUE: u32 = 0;
+}

va108xx/src/porta/irq_evt.rs

@@ -0,0 +1,27 @@
+#[doc = "Register `IRQ_EVT` reader"]
+pub type R = crate::R<IrqEvtSpec>;
+#[doc = "Register `IRQ_EVT` writer"]
+pub type W = crate::W<IrqEvtSpec>;
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        write!(f, "{}", self.bits())
+    }
+}
+impl W {}
+#[doc = "Interrupt Event Register (1:HighLevel/L->H Edge, 0:LowLevel/H->L Edge)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_evt::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_evt::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct IrqEvtSpec;
+impl crate::RegisterSpec for IrqEvtSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`irq_evt::R`](R) reader structure"]
+impl crate::Readable for IrqEvtSpec {}
+#[doc = "`write(|w| ..)` method takes [`irq_evt::W`](W) writer structure"]
+impl crate::Writable for IrqEvtSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets IRQ_EVT to value 0"]
+impl crate::Resettable for IrqEvtSpec {
+    const RESET_VALUE: u32 = 0;
+}

va108xx/src/porta/irq_raw.rs

@@ -0,0 +1,18 @@
+#[doc = "Register `IRQ_RAW` reader"]
+pub type R = crate::R<IrqRawSpec>;
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        write!(f, "{}", self.bits())
+    }
+}
+#[doc = "Raw Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_raw::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct IrqRawSpec;
+impl crate::RegisterSpec for IrqRawSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`irq_raw::R`](R) reader structure"]
+impl crate::Readable for IrqRawSpec {}
+#[doc = "`reset()` method sets IRQ_RAW to value 0"]
+impl crate::Resettable for IrqRawSpec {
+    const RESET_VALUE: u32 = 0;
+}

va108xx/src/porta/irq_sen.rs

@@ -0,0 +1,27 @@
+#[doc = "Register `IRQ_SEN` reader"]
+pub type R = crate::R<IrqSenSpec>;
+#[doc = "Register `IRQ_SEN` writer"]
+pub type W = crate::W<IrqSenSpec>;
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        write!(f, "{}", self.bits())
+    }
+}
+impl W {}
+#[doc = "Interrupt Sense Register (1:Level Sensitive, 0:Edge Sensitive)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_sen::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_sen::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct IrqSenSpec;
+impl crate::RegisterSpec for IrqSenSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`irq_sen::R`](R) reader structure"]
+impl crate::Readable for IrqSenSpec {}
+#[doc = "`write(|w| ..)` method takes [`irq_sen::W`](W) writer structure"]
+impl crate::Writable for IrqSenSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets IRQ_SEN to value 0"]
+impl crate::Resettable for IrqSenSpec {
+    const RESET_VALUE: u32 = 0;
+}

va108xx/src/porta/perid.rs

@@ -0,0 +1,18 @@
+#[doc = "Register `PERID` reader"]
+pub type R = crate::R<PeridSpec>;
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        write!(f, "{}", self.bits())
+    }
+}
+#[doc = "Peripheral ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`perid::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct PeridSpec;
+impl crate::RegisterSpec for PeridSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`perid::R`](R) reader structure"]
+impl crate::Readable for PeridSpec {}
+#[doc = "`reset()` method sets PERID to value 0x0010_07e1"]
+impl crate::Resettable for PeridSpec {
+    const RESET_VALUE: u32 = 0x0010_07e1;
+}