New VA108xx Rust workspace structure + dependency updates

- The workspace is now a monorepo without submodules. The HAL, PAC and BSP
  are integrated directly
- Update all dependencies: embedded-hal v1 and RTIC v2

va108xx-hal/src/clock.rs

@@ -0,0 +1,64 @@
+//! # API for clock related functionality
+//!
+//! This also includes functionality to enable the peripheral clocks
+use crate::time::Hertz;
+use crate::PeripheralSelect;
+use cortex_m::interrupt::{self, Mutex};
+use once_cell::unsync::OnceCell;
+
+static SYS_CLOCK: Mutex<OnceCell<Hertz>> = Mutex::new(OnceCell::new());
+
+pub type PeripheralClocks = PeripheralSelect;
+
+#[derive(Debug, PartialEq, Eq)]
+pub enum FilterClkSel {
+    SysClk = 0,
+    Clk1 = 1,
+    Clk2 = 2,
+    Clk3 = 3,
+    Clk4 = 4,
+    Clk5 = 5,
+    Clk6 = 6,
+    Clk7 = 7,
+}
+
+/// The Vorago in powered by an external clock which might have different frequencies.
+/// The clock can be set here so it can be used by other software components as well.
+/// The clock can be set exactly once
+pub fn set_sys_clock(freq: impl Into<Hertz>) {
+    interrupt::free(|cs| {
+        SYS_CLOCK.borrow(cs).set(freq.into()).ok();
+    })
+}
+
+/// Returns the configured system clock
+pub fn get_sys_clock() -> Option<Hertz> {
+    interrupt::free(|cs| SYS_CLOCK.borrow(cs).get().copied())
+}
+
+pub fn set_clk_div_register(syscfg: &mut va108xx::Sysconfig, clk_sel: FilterClkSel, div: u32) {
+    match clk_sel {
+        FilterClkSel::SysClk => (),
+        FilterClkSel::Clk1 => syscfg.ioconfig_clkdiv1().write(|w| unsafe { w.bits(div) }),
+        FilterClkSel::Clk2 => syscfg.ioconfig_clkdiv2().write(|w| unsafe { w.bits(div) }),
+        FilterClkSel::Clk3 => syscfg.ioconfig_clkdiv3().write(|w| unsafe { w.bits(div) }),
+        FilterClkSel::Clk4 => syscfg.ioconfig_clkdiv4().write(|w| unsafe { w.bits(div) }),
+        FilterClkSel::Clk5 => syscfg.ioconfig_clkdiv5().write(|w| unsafe { w.bits(div) }),
+        FilterClkSel::Clk6 => syscfg.ioconfig_clkdiv6().write(|w| unsafe { w.bits(div) }),
+        FilterClkSel::Clk7 => syscfg.ioconfig_clkdiv7().write(|w| unsafe { w.bits(div) }),
+    }
+}
+
+#[inline]
+pub fn enable_peripheral_clock(syscfg: &mut va108xx::Sysconfig, clock: PeripheralClocks) {
+    syscfg
+        .peripheral_clk_enable()
+        .modify(|r, w| unsafe { w.bits(r.bits() | (1 << clock as u8)) });
+}
+
+#[inline]
+pub fn disable_peripheral_clock(syscfg: &mut va108xx::Sysconfig, clock: PeripheralClocks) {
+    syscfg
+        .peripheral_clk_enable()
+        .modify(|r, w| unsafe { w.bits(r.bits() & !(1 << clock as u8)) });
+}

va108xx-hal/src/gpio/dynpins.rs

@@ -0,0 +1,517 @@
+//! # Type-erased, value-level module for GPIO pins
+//!
+//! Although the type-level API is generally preferred, it is not suitable in
+//! all cases. Because each pin is represented by a distinct type, it is not
+//! possible to store multiple pins in a homogeneous data structure. The
+//! value-level API solves this problem by erasing the type information and
+//! tracking the pin at run-time.
+//!
+//! Value-level pins are represented by the [`DynPin`] type. [`DynPin`] has two
+//! fields, `id` and `mode` with types [`DynPinId`] and [`DynPinMode`]
+//! respectively. The implementation of these types closely mirrors the
+//! type-level API.
+//!
+//! Instances of [`DynPin`] cannot be created directly. Rather, they must be
+//! created from their type-level equivalents using [`From`]/[`Into`].
+//!
+//! ```
+//! // Move a pin out of the Pins struct and convert to a DynPin
+//! let pa0: DynPin = pins.pa0.into();
+//! ```
+//!
+//! Conversions between pin modes use a value-level version of the type-level
+//! API.
+//!
+//! ```
+//! // Use one of the literal function names
+//! pa0.into_floating_input();
+//! // Use a method and a DynPinMode variant
+//! pa0.into_mode(DYN_FLOATING_INPUT);
+//! ```
+//!
+//! Because the pin state cannot be tracked at compile-time, many [`DynPin`]
+//! operations become fallible. Run-time checks are inserted to ensure that
+//! users don't try to, for example, set the output level of an input pin.
+//!
+//! Users may try to convert value-level pins back to their type-level
+//! equivalents. However, this option is fallible, because the compiler cannot
+//! guarantee the pin has the correct ID or is in the correct mode at
+//! compile-time. Use [`TryFrom`](core::convert::TryFrom)/
+//! [`TryInto`](core::convert::TryInto) for this conversion.
+//!
+//! ```
+//! // Convert to a `DynPin`
+//! let pa0: DynPin = pins.pa0.into();
+//! // Change pin mode
+//! pa0.into_floating_input();
+//! // Convert back to a `Pin`
+//! let pa0: Pin<PA0, FloatingInput> = pa0.try_into().unwrap();
+//! ```
+//!
+//! # Embedded HAL traits
+//!
+//! This module implements all of the embedded HAL GPIO traits for [`DynPin`].
+//! However, whereas the type-level API uses
+//! `Error = core::convert::Infallible`, the value-level API can return a real
+//! error. If the [`DynPin`] is not in the correct [`DynPinMode`] for the
+//! operation, the trait functions will return
+//! [`InvalidPinType`](PinError::InvalidPinType).
+
+use super::{
+    pins::{FilterType, InterruptEdge, InterruptLevel, Pin, PinId, PinMode, PinState},
+    reg::RegisterInterface,
+};
+use crate::{clock::FilterClkSel, pac, FunSel, IrqCfg};
+
+//==================================================================================================
+//  DynPinMode configurations
+//==================================================================================================
+
+/// Value-level `enum` for disabled configurations
+#[derive(PartialEq, Eq, Clone, Copy)]
+pub enum DynDisabled {
+    Floating,
+    PullDown,
+    PullUp,
+}
+
+/// Value-level `enum` for input configurations
+#[derive(PartialEq, Eq, Clone, Copy)]
+pub enum DynInput {
+    Floating,
+    PullDown,
+    PullUp,
+}
+
+/// Value-level `enum` for output configurations
+#[derive(PartialEq, Eq, Clone, Copy)]
+pub enum DynOutput {
+    PushPull,
+    OpenDrain,
+    ReadablePushPull,
+    ReadableOpenDrain,
+}
+
+pub type DynAlternate = FunSel;
+
+//==============================================================================
+//  Error
+//==============================================================================
+
+/// GPIO error type
+///
+/// [`DynPin`]s are not tracked and verified at compile-time, so run-time
+/// operations are fallible. This `enum` represents the corresponding errors.
+#[derive(Debug, PartialEq, Eq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub struct InvalidPinTypeError;
+
+impl embedded_hal::digital::Error for InvalidPinTypeError {
+    fn kind(&self) -> embedded_hal::digital::ErrorKind {
+        embedded_hal::digital::ErrorKind::Other
+    }
+}
+
+//==================================================================================================
+//  DynPinMode
+//==================================================================================================
+
+/// Value-level `enum` representing pin modes
+#[derive(PartialEq, Eq, Clone, Copy)]
+pub enum DynPinMode {
+    Input(DynInput),
+    Output(DynOutput),
+    Alternate(DynAlternate),
+}
+
+/// Value-level variant of [`DynPinMode`] for floating input mode
+pub const DYN_FLOATING_INPUT: DynPinMode = DynPinMode::Input(DynInput::Floating);
+/// Value-level variant of [`DynPinMode`] for pull-down input mode
+pub const DYN_PULL_DOWN_INPUT: DynPinMode = DynPinMode::Input(DynInput::PullDown);
+/// Value-level variant of [`DynPinMode`] for pull-up input mode
+pub const DYN_PULL_UP_INPUT: DynPinMode = DynPinMode::Input(DynInput::PullUp);
+
+/// Value-level variant of [`DynPinMode`] for push-pull output mode
+pub const DYN_PUSH_PULL_OUTPUT: DynPinMode = DynPinMode::Output(DynOutput::PushPull);
+/// Value-level variant of [`DynPinMode`] for open-drain output mode
+pub const DYN_OPEN_DRAIN_OUTPUT: DynPinMode = DynPinMode::Output(DynOutput::OpenDrain);
+/// Value-level variant of [`DynPinMode`] for readable push-pull output mode
+pub const DYN_RD_PUSH_PULL_OUTPUT: DynPinMode = DynPinMode::Output(DynOutput::ReadablePushPull);
+/// Value-level variant of [`DynPinMode`] for readable opendrain output mode
+pub const DYN_RD_OPEN_DRAIN_OUTPUT: DynPinMode = DynPinMode::Output(DynOutput::ReadableOpenDrain);
+
+/// Value-level variant of [`DynPinMode`] for function select 1
+pub const DYN_ALT_FUNC_1: DynPinMode = DynPinMode::Alternate(DynAlternate::Sel1);
+/// Value-level variant of [`DynPinMode`] for function select 2
+pub const DYN_ALT_FUNC_2: DynPinMode = DynPinMode::Alternate(DynAlternate::Sel2);
+/// Value-level variant of [`DynPinMode`] for function select 3
+pub const DYN_ALT_FUNC_3: DynPinMode = DynPinMode::Alternate(DynAlternate::Sel3);
+
+//==================================================================================================
+//  DynGroup & DynPinId
+//==================================================================================================
+
+/// Value-level `enum` for pin groups
+#[derive(PartialEq, Eq, Clone, Copy)]
+pub enum DynGroup {
+    A,
+    B,
+}
+
+/// Value-level `struct` representing pin IDs
+#[derive(PartialEq, Eq, Clone, Copy)]
+pub struct DynPinId {
+    pub group: DynGroup,
+    pub num: u8,
+}
+
+//==================================================================================================
+//  DynRegisters
+//==================================================================================================
+
+/// Provide a safe register interface for [`DynPin`]s
+///
+/// This `struct` takes ownership of a [`DynPinId`] and provides an API to
+/// access the corresponding regsiters.
+struct DynRegisters {
+    id: DynPinId,
+}
+
+// [`DynRegisters`] takes ownership of the [`DynPinId`], and [`DynPin`]
+// guarantees that each pin is a singleton, so this implementation is safe.
+unsafe impl RegisterInterface for DynRegisters {
+    #[inline]
+    fn id(&self) -> DynPinId {
+        self.id
+    }
+}
+
+impl DynRegisters {
+    /// Create a new instance of [`DynRegisters`]
+    ///
+    /// # Safety
+    ///
+    /// Users must never create two simultaneous instances of this `struct` with
+    /// the same [`DynPinId`]
+    #[inline]
+    unsafe fn new(id: DynPinId) -> Self {
+        DynRegisters { id }
+    }
+}
+
+//==================================================================================================
+//  DynPin
+//==================================================================================================
+
+/// A value-level pin, parameterized by [`DynPinId`] and [`DynPinMode`]
+///
+/// This type acts as a type-erased version of [`Pin`]. Every pin is represented
+/// by the same type, and pins are tracked and distinguished at run-time.
+pub struct DynPin {
+    regs: DynRegisters,
+    mode: DynPinMode,
+}
+
+impl DynPin {
+    /// Create a new [`DynPin`]
+    ///
+    /// # Safety
+    ///
+    /// Each [`DynPin`] must be a singleton. For a given [`DynPinId`], there
+    /// must be at most one corresponding [`DynPin`] in existence at any given
+    /// time.  Violating this requirement is `unsafe`.
+    #[inline]
+    unsafe fn new(id: DynPinId, mode: DynPinMode) -> Self {
+        DynPin {
+            regs: DynRegisters::new(id),
+            mode,
+        }
+    }
+
+    /// Return a copy of the pin ID
+    #[inline]
+    pub fn id(&self) -> DynPinId {
+        self.regs.id
+    }
+
+    /// Return a copy of the pin mode
+    #[inline]
+    pub fn mode(&self) -> DynPinMode {
+        self.mode
+    }
+
+    /// Convert the pin to the requested [`DynPinMode`]
+    #[inline]
+    pub fn into_mode(&mut self, mode: DynPinMode) {
+        // Only modify registers if we are actually changing pin mode
+        if mode != self.mode {
+            self.regs.change_mode(mode);
+            self.mode = mode;
+        }
+    }
+
+    #[inline]
+    pub fn into_funsel_1(&mut self) {
+        self.into_mode(DYN_ALT_FUNC_1);
+    }
+
+    #[inline]
+    pub fn into_funsel_2(&mut self) {
+        self.into_mode(DYN_ALT_FUNC_2);
+    }
+
+    #[inline]
+    pub fn into_funsel_3(&mut self) {
+        self.into_mode(DYN_ALT_FUNC_3);
+    }
+
+    /// Configure the pin to operate as a floating input
+    #[inline]
+    pub fn into_floating_input(&mut self) {
+        self.into_mode(DYN_FLOATING_INPUT);
+    }
+
+    /// Configure the pin to operate as a pulled down input
+    #[inline]
+    pub fn into_pull_down_input(&mut self) {
+        self.into_mode(DYN_PULL_DOWN_INPUT);
+    }
+
+    /// Configure the pin to operate as a pulled up input
+    #[inline]
+    pub fn into_pull_up_input(&mut self) {
+        self.into_mode(DYN_PULL_UP_INPUT);
+    }
+
+    /// Configure the pin to operate as a push-pull output
+    #[inline]
+    pub fn into_push_pull_output(&mut self) {
+        self.into_mode(DYN_PUSH_PULL_OUTPUT);
+    }
+
+    /// Configure the pin to operate as a push-pull output
+    #[inline]
+    pub fn into_open_drain_output(&mut self) {
+        self.into_mode(DYN_OPEN_DRAIN_OUTPUT);
+    }
+
+    /// Configure the pin to operate as a push-pull output
+    #[inline]
+    pub fn into_readable_push_pull_output(&mut self) {
+        self.into_mode(DYN_RD_PUSH_PULL_OUTPUT);
+    }
+
+    /// Configure the pin to operate as a push-pull output
+    #[inline]
+    pub fn into_readable_open_drain_output(&mut self) {
+        self.into_mode(DYN_RD_OPEN_DRAIN_OUTPUT);
+    }
+
+    common_reg_if_functions!();
+
+    /// See p.53 of the programmers guide for more information.
+    /// Possible delays in clock cycles:
+    ///  - Delay 1: 1
+    ///  - Delay 2: 2
+    ///  - Delay 1 + Delay 2: 3
+    #[inline]
+    pub fn delay(self, delay_1: bool, delay_2: bool) -> Result<Self, InvalidPinTypeError> {
+        match self.mode {
+            DynPinMode::Output(_) => {
+                self.regs.delay(delay_1, delay_2);
+                Ok(self)
+            }
+            _ => Err(InvalidPinTypeError),
+        }
+    }
+
+    /// See p.52 of the programmers guide for more information.
+    /// When configured for pulse mode, a given pin will set the non-default state for exactly
+    /// one clock cycle before returning to the configured default state
+    pub fn pulse_mode(
+        self,
+        enable: bool,
+        default_state: PinState,
+    ) -> Result<Self, InvalidPinTypeError> {
+        match self.mode {
+            DynPinMode::Output(_) => {
+                self.regs.pulse_mode(enable, default_state);
+                Ok(self)
+            }
+            _ => Err(InvalidPinTypeError),
+        }
+    }
+
+    /// See p.37 and p.38 of the programmers guide for more information.
+    #[inline]
+    pub fn filter_type(
+        self,
+        filter: FilterType,
+        clksel: FilterClkSel,
+    ) -> Result<Self, InvalidPinTypeError> {
+        match self.mode {
+            DynPinMode::Input(_) => {
+                self.regs.filter_type(filter, clksel);
+                Ok(self)
+            }
+            _ => Err(InvalidPinTypeError),
+        }
+    }
+
+    pub fn interrupt_edge(
+        mut self,
+        edge_type: InterruptEdge,
+        irq_cfg: IrqCfg,
+        syscfg: Option<&mut pac::Sysconfig>,
+        irqsel: Option<&mut pac::Irqsel>,
+    ) -> Result<Self, InvalidPinTypeError> {
+        match self.mode {
+            DynPinMode::Input(_) | DynPinMode::Output(_) => {
+                self.regs.interrupt_edge(edge_type);
+                self.irq_enb(irq_cfg, syscfg, irqsel);
+                Ok(self)
+            }
+            _ => Err(InvalidPinTypeError),
+        }
+    }
+
+    pub fn interrupt_level(
+        mut self,
+        level_type: InterruptLevel,
+        irq_cfg: IrqCfg,
+        syscfg: Option<&mut pac::Sysconfig>,
+        irqsel: Option<&mut pac::Irqsel>,
+    ) -> Result<Self, InvalidPinTypeError> {
+        match self.mode {
+            DynPinMode::Input(_) | DynPinMode::Output(_) => {
+                self.regs.interrupt_level(level_type);
+                self.irq_enb(irq_cfg, syscfg, irqsel);
+                Ok(self)
+            }
+            _ => Err(InvalidPinTypeError),
+        }
+    }
+
+    #[inline]
+    pub fn toggle_with_toggle_reg(&mut self) -> Result<(), InvalidPinTypeError> {
+        match self.mode {
+            DynPinMode::Output(_) => {
+                self.regs.toggle();
+                Ok(())
+            }
+            _ => Err(InvalidPinTypeError),
+        }
+    }
+
+    #[inline]
+    fn _read(&self) -> Result<bool, InvalidPinTypeError> {
+        match self.mode {
+            DynPinMode::Input(_) | DYN_RD_OPEN_DRAIN_OUTPUT | DYN_RD_PUSH_PULL_OUTPUT => {
+                Ok(self.regs.read_pin())
+            }
+            _ => Err(InvalidPinTypeError),
+        }
+    }
+    #[inline]
+    fn _write(&mut self, bit: bool) -> Result<(), InvalidPinTypeError> {
+        match self.mode {
+            DynPinMode::Output(_) => {
+                self.regs.write_pin(bit);
+                Ok(())
+            }
+            _ => Err(InvalidPinTypeError),
+        }
+    }
+
+    #[inline]
+    fn _is_low(&self) -> Result<bool, InvalidPinTypeError> {
+        self._read().map(|v| !v)
+    }
+    #[inline]
+    fn _is_high(&self) -> Result<bool, InvalidPinTypeError> {
+        self._read()
+    }
+    #[inline]
+    fn _set_low(&mut self) -> Result<(), InvalidPinTypeError> {
+        self._write(false)
+    }
+    #[inline]
+    fn _set_high(&mut self) -> Result<(), InvalidPinTypeError> {
+        self._write(true)
+    }
+}
+
+//==================================================================================================
+//  Convert between Pin and DynPin
+//==================================================================================================
+
+impl<I: PinId, M: PinMode> From<Pin<I, M>> for DynPin {
+    /// Erase the type-level information in a [`Pin`] and return a value-level
+    /// [`DynPin`]
+    #[inline]
+    fn from(_pin: Pin<I, M>) -> Self {
+        // The `Pin` is consumed, so it is safe to replace it with the
+        // corresponding `DynPin`
+        unsafe { DynPin::new(I::DYN, M::DYN) }
+    }
+}
+
+impl<I: PinId, M: PinMode> TryFrom<DynPin> for Pin<I, M> {
+    type Error = InvalidPinTypeError;
+
+    /// Try to recreate a type-level [`Pin`] from a value-level [`DynPin`]
+    ///
+    /// There is no way for the compiler to know if the conversion will be
+    /// successful at compile-time. We must verify the conversion at run-time
+    /// or refuse to perform it.
+    #[inline]
+    fn try_from(pin: DynPin) -> Result<Self, Self::Error> {
+        if pin.regs.id == I::DYN && pin.mode == M::DYN {
+            // The `DynPin` is consumed, so it is safe to replace it with the
+            // corresponding `Pin`
+            Ok(unsafe { Self::new() })
+        } else {
+            Err(InvalidPinTypeError)
+        }
+    }
+}
+
+//==================================================================================================
+// Embedded HAL traits
+//==================================================================================================
+
+impl embedded_hal::digital::ErrorType for DynPin {
+    type Error = InvalidPinTypeError;
+}
+
+impl embedded_hal::digital::OutputPin for DynPin {
+    #[inline]
+    fn set_high(&mut self) -> Result<(), Self::Error> {
+        self._set_high()
+    }
+    #[inline]
+    fn set_low(&mut self) -> Result<(), Self::Error> {
+        self._set_low()
+    }
+}
+
+impl embedded_hal::digital::InputPin for DynPin {
+    #[inline]
+    fn is_high(&mut self) -> Result<bool, Self::Error> {
+        self._is_high()
+    }
+    #[inline]
+    fn is_low(&mut self) -> Result<bool, Self::Error> {
+        self._is_low()
+    }
+}
+
+impl embedded_hal::digital::StatefulOutputPin for DynPin {
+    fn is_set_high(&mut self) -> Result<bool, Self::Error> {
+        self._is_high()
+    }
+
+    fn is_set_low(&mut self) -> Result<bool, Self::Error> {
+        self._is_low()
+    }
+}

va108xx-hal/src/gpio/mod.rs

@@ -0,0 +1,111 @@
+//! # API for the GPIO peripheral
+//!
+//! The implementation of this GPIO module is heavily based on the
+//! [ATSAMD HAL implementation](https://docs.rs/atsamd-hal/latest/atsamd_hal/gpio/index.html).
+//!
+//! This API provides two different submodules, [`mod@pins`] and [`dynpins`],
+//! representing two different ways to handle GPIO pins. The default, [`mod@pins`],
+//! is a type-level API that tracks the state of each pin at compile-time. The
+//! alternative, [`dynpins`] is a type-erased, value-level API that tracks the
+//! state of each pin at run-time.
+//!
+//! The type-level API is strongly preferred. By representing the state of each
+//! pin within the type system, the compiler can detect logic errors at
+//! compile-time. Furthermore, the type-level API has absolutely zero run-time
+//! cost.
+//!
+//! If needed, [`dynpins`] can be used to erase the type-level differences
+//! between pins. However, by doing so, pins must now be tracked at run-time,
+//! and each pin has a non-zero memory footprint.
+//!
+//! ## Examples
+//!
+//! - [Blinky example](https://egit.irs.uni-stuttgart.de/rust/va108xx-hal/src/branch/main/examples/blinky.rs)
+//!
+
+#[derive(Debug, PartialEq, Eq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub struct IsMaskedError;
+
+macro_rules! common_reg_if_functions {
+    () => {
+        paste::paste!(
+            #[inline]
+            pub fn datamask(&self) -> bool {
+                self.regs.datamask()
+            }
+
+            #[inline]
+            pub fn clear_datamask(self) -> Self {
+                self.regs.clear_datamask();
+                self
+            }
+
+            #[inline]
+            pub fn set_datamask(self) -> Self {
+                self.regs.set_datamask();
+                self
+            }
+
+            #[inline]
+            pub fn is_high_masked(&self) -> Result<bool, crate::gpio::IsMaskedError> {
+                self.regs.read_pin_masked()
+            }
+
+            #[inline]
+            pub fn is_low_masked(&self) -> Result<bool, crate::gpio::IsMaskedError> {
+                self.regs.read_pin_masked().map(|v| !v)
+            }
+
+            #[inline]
+            pub fn set_high_masked(&mut self) -> Result<(), crate::gpio::IsMaskedError> {
+                self.regs.write_pin_masked(true)
+            }
+
+            #[inline]
+            pub fn set_low_masked(&mut self) -> Result<(), crate::gpio::IsMaskedError> {
+                self.regs.write_pin_masked(false)
+            }
+
+            fn irq_enb(
+                &mut self,
+                irq_cfg: crate::IrqCfg,
+                syscfg: Option<&mut va108xx::Sysconfig>,
+                irqsel: Option<&mut va108xx::Irqsel>,
+            ) {
+                if syscfg.is_some() {
+                    crate::clock::enable_peripheral_clock(
+                        syscfg.unwrap(),
+                        crate::clock::PeripheralClocks::Irqsel,
+                    );
+                }
+                self.regs.enable_irq();
+                if let Some(irqsel) = irqsel {
+                    if irq_cfg.route {
+                        match self.regs.id().group {
+                            // Set the correct interrupt number in the IRQSEL register
+                            DynGroup::A => {
+                                irqsel
+                                    .porta0(self.regs.id().num as usize)
+                                    .write(|w| unsafe { w.bits(irq_cfg.irq as u32) });
+                            }
+                            DynGroup::B => {
+                                irqsel
+                                    .portb0(self.regs.id().num as usize)
+                                    .write(|w| unsafe { w.bits(irq_cfg.irq as u32) });
+                            }
+                        }
+                    }
+                }
+            }
+        );
+    };
+}
+
+pub mod dynpins;
+pub use dynpins::*;
+
+pub mod pins;
+pub use pins::*;
+
+mod reg;

va108xx-hal/src/gpio/pins.rs

@@ -0,0 +1,890 @@
+//! # Type-level module for GPIO pins
+//!
+//! This documentation is strongly based on the
+//! [atsamd documentation](https://docs.rs/atsamd-hal/latest/atsamd_hal/gpio/pin/index.html).
+//!
+//! This module provides a type-level API for GPIO pins. It uses the type system
+//! to track the state of pins at compile-time. Representing GPIO pins in this
+//! manner incurs no run-time overhead. Each [`Pin`] struct is zero-sized, so
+//! there is no data to copy around. Instead, real code is generated as a side
+//! effect of type transformations, and the resulting assembly is nearly
+//! identical to the equivalent, hand-written C.
+//!
+//! To track the state of pins at compile-time, this module uses traits to
+//! represent [type classes] and types as instances of those type classes. For
+//! example, the trait [`InputConfig`] acts as a [type-level enum] of the
+//! available input configurations, and the types [`Floating`], [`PullDown`] and
+//! [`PullUp`] are its type-level variants.
+//!
+//! Type-level [`Pin`]s are parameterized by two type-level enums, [`PinId`] and
+//! [`PinMode`].
+//!
+//! ```
+//! pub struct Pin<I, M>
+//! where
+//!     I: PinId,
+//!     M: PinMode,
+//! {
+//!     // ...
+//! }
+//! ```
+//!
+//! A `PinId` identifies a pin by it's group (A, B, C or D) and pin number. Each
+//! `PinId` instance is named according to its datasheet identifier, e.g.
+//! [`PA02`].
+//!
+//! A `PinMode` represents the various pin modes. The available `PinMode`
+//! variants are [`Disabled`], [`Input`], [`Interrupt`], [`Output`] and
+//! [`Alternate`], each with its own corresponding configurations.
+//!
+//! It is not possible for users to create new instances of a [`Pin`]. Singleton
+//! instances of each pin are made available to users through the [`Pins`]
+//! struct.
+//!
+//! To create the [`Pins`] struct, users must supply the PAC
+//! [`PORT`](crate::pac::PORT) peripheral. The [`Pins`] struct takes
+//! ownership of the [`PORT`] and provides the corresponding pins. Each [`Pin`]
+//! within the [`Pins`] struct can be moved out and used individually.
+//!
+//!
+//! ```
+//! let mut peripherals = Peripherals::take().unwrap();
+//! let pins = Pins::new(peripherals.PORT);
+//! ```
+//!
+//! Pins can be converted between modes using several different methods.
+//!
+//! ```
+//! // Use one of the literal function names
+//! let pa27 = pins.pa27.into_floating_input();
+//! // Use a generic method and one of the `PinMode` variant types
+//! let pa27 = pins.pa27.into_mode::<FloatingInput>();
+//! // Specify the target type and use `From`/`Into`
+//! let pa27: Pin<PA27, FloatingInput> = pins.pa27.into();
+//! ```
+//!
+//! # Embedded HAL traits
+//!
+//! This module implements all of the embedded HAL GPIO traits for each [`Pin`]
+//! in the corresponding [`PinMode`]s, namely: [`InputPin`], [`OutputPin`],
+//! [`ToggleableOutputPin`] and [`StatefulOutputPin`].
+//!
+//! For example, you can control the logic level of an `OutputPin` like so
+//!
+//! ```
+//! use atsamd_hal::pac::Peripherals;
+//! use atsamd_hal::gpio::Pins;
+//! use crate::ehal_02::digital::v2::OutputPin;
+//!
+//! let mut peripherals = Peripherals::take().unwrap();
+//! let mut pins = Pins::new(peripherals.PORT);
+//! pins.pa27.set_high();
+//! ```
+//!
+//! # Type-level features
+//!
+//! This module also provides additional, type-level tools to work with GPIO
+//! pins.
+//!
+//! The [`OptionalPinId`] and [`OptionalPin`] traits use the [`OptionalKind`]
+//! pattern to act as type-level versions of [`Option`] for `PinId` and `Pin`
+//! respectively. And the [`AnyPin`] trait defines an [`AnyKind`] type class
+//! for all `Pin` types.
+//!
+//! [type classes]: crate::typelevel#type-classes
+//! [type-level enum]: crate::typelevel#type-level-enum
+//! [`OptionalKind`]: crate::typelevel#optionalkind-trait-pattern
+//! [`AnyKind`]: crate::typelevel#anykind-trait-pattern
+use super::dynpins::{DynAlternate, DynGroup, DynInput, DynOutput, DynPinId, DynPinMode};
+use super::reg::RegisterInterface;
+use crate::{
+    pac::{Irqsel, Porta, Portb, Sysconfig},
+    typelevel::Sealed,
+    IrqCfg,
+};
+use core::convert::Infallible;
+use core::marker::PhantomData;
+use core::mem::transmute;
+use embedded_hal::digital::{InputPin, OutputPin, StatefulOutputPin};
+use paste::paste;
+
+//==================================================================================================
+//  Errors and Definitions
+//==================================================================================================
+
+#[derive(Debug, PartialEq, Eq)]
+pub enum InterruptEdge {
+    HighToLow,
+    LowToHigh,
+    BothEdges,
+}
+
+#[derive(Debug, PartialEq, Eq)]
+pub enum InterruptLevel {
+    Low = 0,
+    High = 1,
+}
+
+#[derive(Debug, PartialEq, Eq)]
+pub enum PinState {
+    Low = 0,
+    High = 1,
+}
+
+//==================================================================================================
+// Input configuration
+//==================================================================================================
+
+/// Type-level enum for input configurations
+///
+/// The valid options are [`Floating`], [`PullDown`] and [`PullUp`].
+pub trait InputConfig: Sealed {
+    /// Corresponding [`DynInput`](super::DynInput)
+    const DYN: DynInput;
+}
+
+pub enum Floating {}
+pub enum PullDown {}
+pub enum PullUp {}
+
+impl InputConfig for Floating {
+    const DYN: DynInput = DynInput::Floating;
+}
+impl InputConfig for PullDown {
+    const DYN: DynInput = DynInput::PullDown;
+}
+impl InputConfig for PullUp {
+    const DYN: DynInput = DynInput::PullUp;
+}
+
+impl Sealed for Floating {}
+impl Sealed for PullDown {}
+impl Sealed for PullUp {}
+
+/// Type-level variant of [`PinMode`] for floating input mode
+pub type InputFloating = Input<Floating>;
+/// Type-level variant of [`PinMode`] for pull-down input mode
+pub type InputPullDown = Input<PullDown>;
+/// Type-level variant of [`PinMode`] for pull-up input mode
+pub type InputPullUp = Input<PullUp>;
+
+/// Type-level variant of [`PinMode`] for input modes
+///
+/// Type `C` is one of three input configurations: [`Floating`], [`PullDown`] or
+/// [`PullUp`]
+pub struct Input<C: InputConfig> {
+    cfg: PhantomData<C>,
+}
+
+impl<C: InputConfig> Sealed for Input<C> {}
+
+#[derive(Debug, PartialEq, Eq)]
+pub enum FilterType {
+    SystemClock = 0,
+    DirectInputWithSynchronization = 1,
+    FilterOneClockCycle = 2,
+    FilterTwoClockCycles = 3,
+    FilterThreeClockCycles = 4,
+    FilterFourClockCycles = 5,
+}
+
+pub use crate::clock::FilterClkSel;
+
+//==================================================================================================
+// Output configuration
+//==================================================================================================
+
+pub trait OutputConfig: Sealed {
+    const DYN: DynOutput;
+}
+
+pub trait ReadableOutput: Sealed {}
+
+/// Type-level variant of [`OutputConfig`] for a push-pull configuration
+pub enum PushPull {}
+/// Type-level variant of [`OutputConfig`] for an open drain configuration
+pub enum OpenDrain {}
+
+/// Type-level variant of [`OutputConfig`] for a readable push-pull configuration
+pub enum ReadablePushPull {}
+/// Type-level variant of [`OutputConfig`] for a readable open-drain configuration
+pub enum ReadableOpenDrain {}
+
+impl Sealed for PushPull {}
+impl Sealed for OpenDrain {}
+impl Sealed for ReadableOpenDrain {}
+impl Sealed for ReadablePushPull {}
+impl ReadableOutput for ReadableOpenDrain {}
+impl ReadableOutput for ReadablePushPull {}
+
+impl OutputConfig for PushPull {
+    const DYN: DynOutput = DynOutput::PushPull;
+}
+impl OutputConfig for OpenDrain {
+    const DYN: DynOutput = DynOutput::OpenDrain;
+}
+impl OutputConfig for ReadablePushPull {
+    const DYN: DynOutput = DynOutput::ReadablePushPull;
+}
+impl OutputConfig for ReadableOpenDrain {
+    const DYN: DynOutput = DynOutput::ReadableOpenDrain;
+}
+
+/// Type-level variant of [`PinMode`] for output modes
+///
+/// Type `C` is one of four output configurations: [`PushPull`], [`OpenDrain`] or
+/// their respective readable versions
+pub struct Output<C: OutputConfig> {
+    cfg: PhantomData<C>,
+}
+
+impl<C: OutputConfig> Sealed for Output<C> {}
+
+/// Type-level variant of [`PinMode`] for push-pull output mode
+pub type PushPullOutput = Output<PushPull>;
+/// Type-level variant of [`PinMode`] for open drain output mode
+pub type OutputOpenDrain = Output<OpenDrain>;
+
+pub type OutputReadablePushPull = Output<ReadablePushPull>;
+pub type OutputReadableOpenDrain = Output<ReadableOpenDrain>;
+
+//==================================================================================================
+//  Alternate configurations
+//==================================================================================================
+
+/// Type-level enum for alternate peripheral function configurations
+pub trait AlternateConfig: Sealed {
+    const DYN: DynAlternate;
+}
+
+pub enum Funsel1 {}
+pub enum Funsel2 {}
+pub enum Funsel3 {}
+
+impl AlternateConfig for Funsel1 {
+    const DYN: DynAlternate = DynAlternate::Sel1;
+}
+impl AlternateConfig for Funsel2 {
+    const DYN: DynAlternate = DynAlternate::Sel2;
+}
+impl AlternateConfig for Funsel3 {
+    const DYN: DynAlternate = DynAlternate::Sel3;
+}
+
+impl Sealed for Funsel1 {}
+impl Sealed for Funsel2 {}
+impl Sealed for Funsel3 {}
+
+/// Type-level variant of [`PinMode`] for alternate peripheral functions
+///
+/// Type `C` is an [`AlternateConfig`]
+pub struct Alternate<C: AlternateConfig> {
+    cfg: PhantomData<C>,
+}
+
+impl<C: AlternateConfig> Sealed for Alternate<C> {}
+
+pub type AltFunc1 = Alternate<Funsel1>;
+pub type AltFunc2 = Alternate<Funsel2>;
+pub type AltFunc3 = Alternate<Funsel3>;
+
+/// Type alias for the [`PinMode`] at reset
+pub type Reset = InputFloating;
+
+//==================================================================================================
+//  Pin modes
+//==================================================================================================
+
+/// Type-level enum representing pin modes
+///
+/// The valid options are [`Input`], [`Output`] and [`Alternate`].
+pub trait PinMode: Sealed {
+    /// Corresponding [`DynPinMode`](super::DynPinMode)
+    const DYN: DynPinMode;
+}
+
+impl<C: InputConfig> PinMode for Input<C> {
+    const DYN: DynPinMode = DynPinMode::Input(C::DYN);
+}
+impl<C: OutputConfig> PinMode for Output<C> {
+    const DYN: DynPinMode = DynPinMode::Output(C::DYN);
+}
+impl<C: AlternateConfig> PinMode for Alternate<C> {
+    const DYN: DynPinMode = DynPinMode::Alternate(C::DYN);
+}
+
+//==================================================================================================
+//  Pin IDs
+//==================================================================================================
+
+/// Type-level enum for pin IDs
+pub trait PinId: Sealed {
+    /// Corresponding [`DynPinId`](super::DynPinId)
+    const DYN: DynPinId;
+}
+
+macro_rules! pin_id {
+    ($Group:ident, $Id:ident, $NUM:literal) => {
+        // Need paste macro to use ident in doc attribute
+        paste! {
+            #[doc = "Pin ID representing pin " $Id]
+            pub enum $Id {}
+            impl Sealed for $Id {}
+            impl PinId for $Id {
+                const DYN: DynPinId = DynPinId {
+                    group: DynGroup::$Group,
+                    num: $NUM,
+                };
+            }
+        }
+    };
+}
+
+//==================================================================================================
+//  Pin
+//==================================================================================================
+
+/// A type-level GPIO pin, parameterized by [`PinId`] and [`PinMode`] types
+
+pub struct Pin<I: PinId, M: PinMode> {
+    pub(in crate::gpio) regs: Registers<I>,
+    mode: PhantomData<M>,
+}
+
+impl<I: PinId, M: PinMode> Pin<I, M> {
+    /// Create a new [`Pin`]
+    ///
+    /// # Safety
+    ///
+    /// Each [`Pin`] must be a singleton. For a given [`PinId`], there must be
+    /// at most one corresponding [`Pin`] in existence at any given time.
+    /// Violating this requirement is `unsafe`.
+    #[inline]
+    pub(crate) unsafe fn new() -> Pin<I, M> {
+        Pin {
+            regs: Registers::new(),
+            mode: PhantomData,
+        }
+    }
+
+    /// Convert the pin to the requested [`PinMode`]
+    #[inline]
+    pub fn into_mode<N: PinMode>(mut self) -> Pin<I, N> {
+        // Only modify registers if we are actually changing pin mode
+        // This check should compile away
+        if N::DYN != M::DYN {
+            self.regs.change_mode::<N>();
+        }
+        // Safe because we drop the existing Pin
+        unsafe { Pin::new() }
+    }
+
+    /// Configure the pin for function select 1. See Programmer Guide p.40 for the function table
+    #[inline]
+    pub fn into_funsel_1(self) -> Pin<I, AltFunc1> {
+        self.into_mode()
+    }
+
+    /// Configure the pin for function select 2. See Programmer Guide p.40 for the function table
+    #[inline]
+    pub fn into_funsel_2(self) -> Pin<I, AltFunc2> {
+        self.into_mode()
+    }
+
+    /// Configure the pin for function select 3. See Programmer Guide p.40 for the function table
+    #[inline]
+    pub fn into_funsel_3(self) -> Pin<I, AltFunc3> {
+        self.into_mode()
+    }
+
+    /// Configure the pin to operate as a floating input
+    #[inline]
+    pub fn into_floating_input(self) -> Pin<I, InputFloating> {
+        self.into_mode()
+    }
+
+    /// Configure the pin to operate as a pulled down input
+    #[inline]
+    pub fn into_pull_down_input(self) -> Pin<I, InputPullDown> {
+        self.into_mode()
+    }
+
+    /// Configure the pin to operate as a pulled up input
+    #[inline]
+    pub fn into_pull_up_input(self) -> Pin<I, InputPullUp> {
+        self.into_mode()
+    }
+
+    /// Configure the pin to operate as a push-pull output
+    #[inline]
+    pub fn into_push_pull_output(self) -> Pin<I, PushPullOutput> {
+        self.into_mode()
+    }
+
+    /// Configure the pin to operate as a readable push-pull output
+    #[inline]
+    pub fn into_readable_push_pull_output(self) -> Pin<I, OutputReadablePushPull> {
+        self.into_mode()
+    }
+
+    /// Configure the pin to operate as a readable open-drain output
+    #[inline]
+    pub fn into_readable_open_drain_output(self) -> Pin<I, OutputReadableOpenDrain> {
+        self.into_mode()
+    }
+
+    common_reg_if_functions!();
+
+    #[inline]
+    pub(crate) fn _set_high(&mut self) {
+        self.regs.write_pin(true)
+    }
+
+    #[inline]
+    pub(crate) fn _set_low(&mut self) {
+        self.regs.write_pin(false)
+    }
+
+    #[inline]
+    pub(crate) fn _toggle_with_toggle_reg(&mut self) {
+        self.regs.toggle();
+    }
+
+    #[inline]
+    pub(crate) fn _is_low(&self) -> bool {
+        !self.regs.read_pin()
+    }
+
+    #[inline]
+    pub(crate) fn _is_high(&self) -> bool {
+        self.regs.read_pin()
+    }
+}
+
+//==============================================================================
+//  AnyPin
+//==============================================================================
+
+/// Type class for [`Pin`] types
+///
+/// This trait uses the [`AnyKind`] trait pattern to create a [type class] for
+/// [`Pin`] types. See the `AnyKind` documentation for more details on the
+/// pattern.
+///
+/// ## `v1` Compatibility
+///
+/// Normally, this trait would use `Is<Type = SpecificPin<Self>>` as a super
+/// trait. But doing so would restrict implementations to only the `v2` `Pin`
+/// type in this module. To aid in backwards compatibility, we want to implement
+/// `AnyPin` for the `v1` `Pin` type as well. This is possible for a few
+/// reasons. First, both structs are zero-sized, so there is no meaningful
+/// memory layout to begin with. And even if there were, the `v1` `Pin` type is
+/// a newtype wrapper around a `v2` `Pin`, and single-field structs are
+/// guaranteed to have the same layout as the field, even for `repr(Rust)`.
+///
+/// [`AnyKind`]: crate::typelevel#anykind-trait-pattern
+/// [type class]: crate::typelevel#type-classes
+pub trait AnyPin
+where
+    Self: Sealed,
+    Self: From<SpecificPin<Self>>,
+    Self: Into<SpecificPin<Self>>,
+    Self: AsRef<SpecificPin<Self>>,
+    Self: AsMut<SpecificPin<Self>>,
+{
+    /// [`PinId`] of the corresponding [`Pin`]
+    type Id: PinId;
+    /// [`PinMode`] of the corresponding [`Pin`]
+    type Mode: PinMode;
+}
+
+impl<I, M> Sealed for Pin<I, M>
+where
+    I: PinId,
+    M: PinMode,
+{
+}
+
+impl<I, M> AnyPin for Pin<I, M>
+where
+    I: PinId,
+    M: PinMode,
+{
+    type Id = I;
+    type Mode = M;
+}
+
+/// Type alias to recover the specific [`Pin`] type from an implementation of
+/// [`AnyPin`]
+///
+/// See the [`AnyKind`] documentation for more details on the pattern.
+///
+/// [`AnyKind`]: crate::typelevel#anykind-trait-pattern
+pub type SpecificPin<P> = Pin<<P as AnyPin>::Id, <P as AnyPin>::Mode>;
+
+impl<P: AnyPin> AsRef<P> for SpecificPin<P> {
+    #[inline]
+    fn as_ref(&self) -> &P {
+        // SAFETY: This is guaranteed to be safe, because P == SpecificPin<P>
+        // Transmuting between `v1` and `v2` `Pin` types is also safe, because
+        // both are zero-sized, and single-field, newtype structs are guaranteed
+        // to have the same layout as the field anyway, even for repr(Rust).
+        unsafe { transmute(self) }
+    }
+}
+
+impl<P: AnyPin> AsMut<P> for SpecificPin<P> {
+    #[inline]
+    fn as_mut(&mut self) -> &mut P {
+        // SAFETY: This is guaranteed to be safe, because P == SpecificPin<P>
+        // Transmuting between `v1` and `v2` `Pin` types is also safe, because
+        // both are zero-sized, and single-field, newtype structs are guaranteed
+        // to have the same layout as the field anyway, even for repr(Rust).
+        unsafe { transmute(self) }
+    }
+}
+
+//==================================================================================================
+//  Additional functionality
+//==================================================================================================
+
+impl<I: PinId, C: InputConfig> Pin<I, Input<C>> {
+    pub fn interrupt_edge(
+        mut self,
+        edge_type: InterruptEdge,
+        irq_cfg: IrqCfg,
+        syscfg: Option<&mut Sysconfig>,
+        irqsel: Option<&mut Irqsel>,
+    ) -> Self {
+        self.regs.interrupt_edge(edge_type);
+        self.irq_enb(irq_cfg, syscfg, irqsel);
+        self
+    }
+
+    pub fn interrupt_level(
+        mut self,
+        level_type: InterruptLevel,
+        irq_cfg: IrqCfg,
+        syscfg: Option<&mut Sysconfig>,
+        irqsel: Option<&mut Irqsel>,
+    ) -> Self {
+        self.regs.interrupt_level(level_type);
+        self.irq_enb(irq_cfg, syscfg, irqsel);
+        self
+    }
+}
+
+impl<I: PinId, C: OutputConfig> Pin<I, Output<C>> {
+    /// See p.53 of the programmers guide for more information.
+    /// Possible delays in clock cycles:
+    ///  - Delay 1: 1
+    ///  - Delay 2: 2
+    ///  - Delay 1 + Delay 2: 3
+    #[inline]
+    pub fn delay(self, delay_1: bool, delay_2: bool) -> Self {
+        self.regs.delay(delay_1, delay_2);
+        self
+    }
+
+    #[inline]
+    pub fn toggle_with_toggle_reg(&mut self) {
+        self._toggle_with_toggle_reg()
+    }
+
+    /// See p.52 of the programmers guide for more information.
+    /// When configured for pulse mode, a given pin will set the non-default state for exactly
+    /// one clock cycle before returning to the configured default state
+    pub fn pulse_mode(self, enable: bool, default_state: PinState) -> Self {
+        self.regs.pulse_mode(enable, default_state);
+        self
+    }
+
+    pub fn interrupt_edge(
+        mut self,
+        edge_type: InterruptEdge,
+        irq_cfg: IrqCfg,
+        syscfg: Option<&mut Sysconfig>,
+        irqsel: Option<&mut Irqsel>,
+    ) -> Self {
+        self.regs.interrupt_edge(edge_type);
+        self.irq_enb(irq_cfg, syscfg, irqsel);
+        self
+    }
+
+    pub fn interrupt_level(
+        mut self,
+        level_type: InterruptLevel,
+        irq_cfg: IrqCfg,
+        syscfg: Option<&mut Sysconfig>,
+        irqsel: Option<&mut Irqsel>,
+    ) -> Self {
+        self.regs.interrupt_level(level_type);
+        self.irq_enb(irq_cfg, syscfg, irqsel);
+        self
+    }
+}
+
+impl<I: PinId, C: InputConfig> Pin<I, Input<C>> {
+    /// See p.37 and p.38 of the programmers guide for more information.
+    #[inline]
+    pub fn filter_type(self, filter: FilterType, clksel: FilterClkSel) -> Self {
+        self.regs.filter_type(filter, clksel);
+        self
+    }
+}
+
+//==================================================================================================
+//  Embedded HAL traits
+//==================================================================================================
+
+impl<I, M> embedded_hal::digital::ErrorType for Pin<I, M>
+where
+    I: PinId,
+    M: PinMode,
+{
+    type Error = Infallible;
+}
+
+impl<I: PinId, C: OutputConfig> OutputPin for Pin<I, Output<C>> {
+    #[inline]
+    fn set_high(&mut self) -> Result<(), Self::Error> {
+        self._set_high();
+        Ok(())
+    }
+
+    #[inline]
+    fn set_low(&mut self) -> Result<(), Self::Error> {
+        self._set_low();
+        Ok(())
+    }
+}
+
+impl<I, C> InputPin for Pin<I, Input<C>>
+where
+    I: PinId,
+    C: InputConfig,
+{
+    #[inline]
+    fn is_high(&mut self) -> Result<bool, Self::Error> {
+        Ok(self._is_high())
+    }
+    #[inline]
+    fn is_low(&mut self) -> Result<bool, Self::Error> {
+        Ok(self._is_low())
+    }
+}
+
+impl<I, C> StatefulOutputPin for Pin<I, Output<C>>
+where
+    I: PinId,
+    C: OutputConfig + ReadableOutput,
+{
+    #[inline]
+    fn is_set_high(&mut self) -> Result<bool, Self::Error> {
+        Ok(self._is_high())
+    }
+    #[inline]
+    fn is_set_low(&mut self) -> Result<bool, Self::Error> {
+        Ok(self._is_low())
+    }
+}
+
+impl<I, C> InputPin for Pin<I, Output<C>>
+where
+    I: PinId,
+    C: OutputConfig + ReadableOutput,
+{
+    #[inline]
+    fn is_high(&mut self) -> Result<bool, Self::Error> {
+        Ok(self._is_high())
+    }
+
+    #[inline]
+    fn is_low(&mut self) -> Result<bool, Self::Error> {
+        Ok(self._is_low())
+    }
+}
+
+//==================================================================================================
+//  Registers
+//==================================================================================================
+
+/// Provide a safe register interface for [`Pin`]s
+///
+/// This `struct` takes ownership of a [`PinId`] and provides an API to
+/// access the corresponding registers.
+pub(in crate::gpio) struct Registers<I: PinId> {
+    id: PhantomData<I>,
+}
+
+// [`Registers`] takes ownership of the [`PinId`], and [`Pin`] guarantees that
+// each pin is a singleton, so this implementation is safe.
+unsafe impl<I: PinId> RegisterInterface for Registers<I> {
+    #[inline]
+    fn id(&self) -> DynPinId {
+        I::DYN
+    }
+}
+
+impl<I: PinId> Registers<I> {
+    /// Create a new instance of [`Registers`]
+    ///
+    /// # Safety
+    ///
+    /// Users must never create two simultaneous instances of this `struct` with
+    /// the same [`PinId`]
+    #[inline]
+    unsafe fn new() -> Self {
+        Registers { id: PhantomData }
+    }
+
+    /// Provide a type-level equivalent for the
+    /// [`RegisterInterface::change_mode`] method.
+    #[inline]
+    pub(in crate::gpio) fn change_mode<M: PinMode>(&mut self) {
+        RegisterInterface::change_mode(self, M::DYN);
+    }
+}
+
+//==================================================================================================
+//  Pin definitions
+//==================================================================================================
+
+macro_rules! pins {
+    (
+        $Port:ident, $PinsName:ident, $($Id:ident,)+,
+    ) => {
+        paste!(
+            /// Collection of all the individual [`Pin`]s for a given port (PORTA or PORTB)
+            pub struct $PinsName {
+                iocfg: Option<va108xx::Ioconfig>,
+                port: $Port,
+                $(
+                    #[doc = "Pin " $Id]
+                    pub [<$Id:lower>]: Pin<$Id, Reset>,
+                )+
+            }
+
+            impl $PinsName {
+                /// Create a new struct containing all the Pins. Passing the IOCONFIG peripheral
+                /// is optional because it might be required to create pin definitions for both
+                /// ports.
+                #[inline]
+                pub fn new(
+                    syscfg: &mut va108xx::Sysconfig,
+                    iocfg: Option<va108xx::Ioconfig>,
+                    port: $Port
+                ) -> $PinsName {
+                    syscfg.peripheral_clk_enable().modify(|_, w| {
+                        w.[<$Port:lower>]().set_bit();
+                        w.gpio().set_bit();
+                        w.ioconfig().set_bit()
+                    });
+                    $PinsName {
+                        iocfg,
+                        port,
+                        // Safe because we only create one `Pin` per `PinId`
+                        $(
+                            [<$Id:lower>]: unsafe { Pin::new() },
+                        )+
+                    }
+                }
+
+                /// Get the peripheral ID
+                /// Safety: Read-only register
+                pub fn get_perid() -> u32 {
+                    let port = unsafe { &(*$Port::ptr()) };
+                    port.perid().read().bits()
+                }
+
+                /// Consumes the Pins struct and returns the port definitions
+                pub fn release(self) -> (Option<va108xx::Ioconfig>, $Port) {
+                    (self.iocfg, self.port)
+                }
+            }
+        );
+    }
+}
+
+macro_rules! declare_pins {
+    (
+        $Group:ident, $PinsName:ident, $Port:ident, [$(($Id:ident, $NUM:literal),)+]
+    ) => {
+        pins!($Port, $PinsName, $($Id,)+,);
+        $(
+            pin_id!($Group, $Id, $NUM);
+        )+
+    }
+}
+
+declare_pins!(
+    A,
+    PinsA,
+    Porta,
+    [
+        (PA0, 0),
+        (PA1, 1),
+        (PA2, 2),
+        (PA3, 3),
+        (PA4, 4),
+        (PA5, 5),
+        (PA6, 6),
+        (PA7, 7),
+        (PA8, 8),
+        (PA9, 9),
+        (PA10, 10),
+        (PA11, 11),
+        (PA12, 12),
+        (PA13, 13),
+        (PA14, 14),
+        (PA15, 15),
+        (PA16, 16),
+        (PA17, 17),
+        (PA18, 18),
+        (PA19, 19),
+        (PA20, 20),
+        (PA21, 21),
+        (PA22, 22),
+        (PA23, 23),
+        (PA24, 24),
+        (PA25, 25),
+        (PA26, 26),
+        (PA27, 27),
+        (PA28, 28),
+        (PA29, 29),
+        (PA30, 30),
+        (PA31, 31),
+    ]
+);
+
+declare_pins!(
+    B,
+    PinsB,
+    Portb,
+    [
+        (PB0, 0),
+        (PB1, 1),
+        (PB2, 2),
+        (PB3, 3),
+        (PB4, 4),
+        (PB5, 5),
+        (PB6, 6),
+        (PB7, 7),
+        (PB8, 8),
+        (PB9, 9),
+        (PB10, 10),
+        (PB11, 11),
+        (PB12, 12),
+        (PB13, 13),
+        (PB14, 14),
+        (PB15, 15),
+        (PB16, 16),
+        (PB17, 17),
+        (PB18, 18),
+        (PB19, 19),
+        (PB20, 20),
+        (PB21, 21),
+        (PB22, 22),
+        (PB23, 23),
+    ]
+);

va108xx-hal/src/gpio/reg.rs

@@ -0,0 +1,382 @@
+use super::dynpins::{self, DynGroup, DynPinId, DynPinMode};
+use super::pins::{FilterType, InterruptEdge, InterruptLevel, PinState};
+use super::IsMaskedError;
+use crate::clock::FilterClkSel;
+use va108xx::{ioconfig, porta};
+
+/// Type definition to avoid confusion: These register blocks are identical
+type PortRegisterBlock = porta::RegisterBlock;
+
+//==================================================================================================
+//  ModeFields
+//==================================================================================================
+
+/// Collect all fields needed to set the [`PinMode`](super::PinMode)
+#[derive(Default)]
+struct ModeFields {
+    dir: bool,
+    opendrn: bool,
+    pull_en: bool,
+    /// true for pullup, false for pulldown
+    pull_dir: bool,
+    funsel: u8,
+    enb_input: bool,
+}
+
+impl From<DynPinMode> for ModeFields {
+    #[inline]
+    fn from(mode: DynPinMode) -> Self {
+        let mut fields = Self::default();
+        use DynPinMode::*;
+        match mode {
+            Input(config) => {
+                use dynpins::DynInput::*;
+                fields.dir = false;
+                match config {
+                    Floating => (),
+                    PullUp => {
+                        fields.pull_en = true;
+                        fields.pull_dir = true;
+                    }
+                    PullDown => {
+                        fields.pull_en = true;
+                    }
+                }
+            }
+            Output(config) => {
+                use dynpins::DynOutput::*;
+                fields.dir = true;
+                match config {
+                    PushPull => (),
+                    OpenDrain => {
+                        fields.opendrn = true;
+                    }
+                    ReadableOpenDrain => {
+                        fields.enb_input = true;
+                        fields.opendrn = true;
+                    }
+                    ReadablePushPull => {
+                        fields.enb_input = true;
+                    }
+                }
+            }
+            Alternate(config) => {
+                fields.funsel = config as u8;
+            }
+        }
+        fields
+    }
+}
+
+//==================================================================================================
+// Register Interface
+//==================================================================================================
+
+pub type PortReg = ioconfig::Porta;
+/*
+pub type IocfgPort = ioconfig::Porta;
+#[repr(C)]
+pub(super) struct IocfgPortGroup {
+    port: [IocfgPort; 32],
+}
+*/
+
+/// Provide a safe register interface for pin objects
+///
+/// [`PORTA`] and [`PORTB`], like every PAC `struct`, is [`Send`] but not [`Sync`], because it
+/// points to a `RegisterBlock` of `VolatileCell`s. Unfortunately, such an
+/// interface is quite restrictive. Instead, it would be ideal if we could split
+/// the [`PORT`] into independent pins that are both [`Send`] and [`Sync`].
+///
+/// [`PORT`] is a single, zero-sized marker `struct` that provides access to
+/// every [`PORT`] register. Instead, we would like to create zero-sized marker
+/// `struct`s for every pin, where each pin is only allowed to control its own
+/// registers. Furthermore, each pin `struct` should be a singleton, so that
+/// exclusive access to the `struct` also guarantees exclusive access to the
+/// corresponding registers. Finally, the pin `struct`s should not have any
+/// interior mutability. Together, these requirements would allow the pin
+/// `struct`s to be both [`Send`] and [`Sync`].
+///
+/// This trait creates a safe API for accomplishing these goals. Implementers
+/// supply a pin ID through the [`id`] function. The remaining functions provide
+/// a safe API for accessing the registers associated with that pin ID. Any
+/// modification of the registers requires `&mut self`, which destroys interior
+/// mutability.
+///
+/// # Safety
+///
+/// Users should only implement the [`id`] function. No default function
+/// implementations should be overridden. The implementing type must also have
+/// "control" over the corresponding pin ID, i.e. it must guarantee that a each
+/// pin ID is a singleton.
+///
+/// [`id`]: Self::id
+pub(super) unsafe trait RegisterInterface {
+    /// Provide a [`DynPinId`] identifying the set of registers controlled by
+    /// this type.
+    fn id(&self) -> DynPinId;
+
+    const PORTA: *const PortRegisterBlock = va108xx::Porta::ptr();
+    const PORTB: *const PortRegisterBlock = va108xx::Portb::ptr();
+
+    /// Change the pin mode
+    #[inline]
+    fn change_mode(&mut self, mode: DynPinMode) {
+        let ModeFields {
+            dir,
+            funsel,
+            opendrn,
+            pull_dir,
+            pull_en,
+            enb_input,
+        } = mode.into();
+        let (portreg, iocfg) = (self.port_reg(), self.iocfg_port());
+        iocfg.write(|w| {
+            w.opendrn().bit(opendrn);
+            w.pen().bit(pull_en);
+            w.plevel().bit(pull_dir);
+            w.iewo().bit(enb_input);
+            unsafe { w.funsel().bits(funsel) }
+        });
+        let mask = self.mask_32();
+        unsafe {
+            if dir {
+                portreg.dir().modify(|r, w| w.bits(r.bits() | mask));
+                // Clear output
+                portreg.clrout().write(|w| w.bits(mask));
+            } else {
+                portreg.dir().modify(|r, w| w.bits(r.bits() & !mask));
+            }
+        }
+    }
+
+    #[inline]
+    fn port_reg(&self) -> &PortRegisterBlock {
+        match self.id().group {
+            DynGroup::A => unsafe { &(*Self::PORTA) },
+            DynGroup::B => unsafe { &(*Self::PORTB) },
+        }
+    }
+    fn iocfg_port(&self) -> &PortReg {
+        let ioconfig = unsafe { va108xx::Ioconfig::ptr().as_ref().unwrap() };
+        match self.id().group {
+            DynGroup::A => ioconfig.porta(self.id().num as usize),
+            DynGroup::B => ioconfig.portb0(self.id().num as usize),
+        }
+    }
+
+    #[inline]
+    fn mask_32(&self) -> u32 {
+        1 << self.id().num
+    }
+
+    #[inline]
+    fn enable_irq(&self) {
+        self.port_reg()
+            .irq_enb()
+            .modify(|r, w| unsafe { w.bits(r.bits() | self.mask_32()) });
+    }
+
+    #[inline]
+    /// Read the logic level of an output pin
+    fn read_pin(&self) -> bool {
+        let portreg = self.port_reg();
+        ((portreg.datainraw().read().bits() >> self.id().num) & 0x01) == 1
+    }
+
+    // Get DATAMASK bit for this particular pin
+    #[inline(always)]
+    fn datamask(&self) -> bool {
+        let portreg = self.port_reg();
+        (portreg.datamask().read().bits() >> self.id().num) == 1
+    }
+
+    /// Read a pin but use the masked version but check whether the datamask for the pin is
+    /// cleared as well
+    #[inline(always)]
+    fn read_pin_masked(&self) -> Result<bool, IsMaskedError> {
+        if !self.datamask() {
+            Err(IsMaskedError)
+        } else {
+            Ok(((self.port_reg().datain().read().bits() >> self.id().num) & 0x01) == 1)
+        }
+    }
+
+    /// Write the logic level of an output pin
+    #[inline(always)]
+    fn write_pin(&mut self, bit: bool) {
+        // Safety: SETOUT is a "mask" register, and we only write the bit for
+        // this pin ID
+        unsafe {
+            if bit {
+                self.port_reg().setout().write(|w| w.bits(self.mask_32()));
+            } else {
+                self.port_reg().clrout().write(|w| w.bits(self.mask_32()));
+            }
+        }
+    }
+
+    /// Write the logic level of an output pin but check whether the datamask for the pin is
+    /// cleared as well
+    #[inline]
+    fn write_pin_masked(&mut self, bit: bool) -> Result<(), IsMaskedError> {
+        if !self.datamask() {
+            Err(IsMaskedError)
+        } else {
+            // Safety: SETOUT is a "mask" register, and we only write the bit for
+            // this pin ID
+            unsafe {
+                if bit {
+                    self.port_reg().setout().write(|w| w.bits(self.mask_32()));
+                } else {
+                    self.port_reg().clrout().write(|w| w.bits(self.mask_32()));
+                }
+                Ok(())
+            }
+        }
+    }
+
+    /// Toggle the logic level of an output pin
+    #[inline(always)]
+    fn toggle(&mut self) {
+        // Safety: TOGOUT is a "mask" register, and we only write the bit for
+        // this pin ID
+        unsafe { self.port_reg().togout().write(|w| w.bits(self.mask_32())) };
+    }
+
+    /// Only useful for interrupt pins. Configure whether to use edges or level as interrupt soure
+    /// When using edge mode, it is possible to generate interrupts on both edges as well
+    #[inline]
+    fn interrupt_edge(&mut self, edge_type: InterruptEdge) {
+        unsafe {
+            self.port_reg()
+                .irq_sen()
+                .modify(|r, w| w.bits(r.bits() & !self.mask_32()));
+            match edge_type {
+                InterruptEdge::HighToLow => {
+                    self.port_reg()
+                        .irq_evt()
+                        .modify(|r, w| w.bits(r.bits() & !self.mask_32()));
+                }
+                InterruptEdge::LowToHigh => {
+                    self.port_reg()
+                        .irq_evt()
+                        .modify(|r, w| w.bits(r.bits() | self.mask_32()));
+                }
+                InterruptEdge::BothEdges => {
+                    self.port_reg()
+                        .irq_edge()
+                        .modify(|r, w| w.bits(r.bits() | self.mask_32()));
+                }
+            }
+        }
+    }
+
+    /// Configure which edge or level type triggers an interrupt
+    #[inline]
+    fn interrupt_level(&mut self, level: InterruptLevel) {
+        unsafe {
+            self.port_reg()
+                .irq_sen()
+                .modify(|r, w| w.bits(r.bits() | self.mask_32()));
+            if level == InterruptLevel::Low {
+                self.port_reg()
+                    .irq_evt()
+                    .modify(|r, w| w.bits(r.bits() & !self.mask_32()));
+            } else {
+                self.port_reg()
+                    .irq_evt()
+                    .modify(|r, w| w.bits(r.bits() | self.mask_32()));
+            }
+        }
+    }
+
+    /// Only useful for input pins
+    #[inline]
+    fn filter_type(&self, filter: FilterType, clksel: FilterClkSel) {
+        self.iocfg_port().modify(|_, w| {
+            // Safety: Only write to register for this Pin ID
+            unsafe {
+                w.flttype().bits(filter as u8);
+                w.fltclk().bits(clksel as u8)
+            }
+        });
+    }
+
+    /// Set DATAMASK bit for this particular pin. 1 is the default
+    /// state of the bit and allows access of the corresponding bit
+    #[inline(always)]
+    fn set_datamask(&self) {
+        let portreg = self.port_reg();
+        unsafe {
+            portreg
+                .datamask()
+                .modify(|r, w| w.bits(r.bits() | self.mask_32()))
+        }
+    }
+
+    /// Clear DATAMASK bit for this particular pin. This prevents access
+    /// of the corresponding bit for output and input operations
+    #[inline(always)]
+    fn clear_datamask(&self) {
+        let portreg = self.port_reg();
+        unsafe {
+            portreg
+                .datamask()
+                .modify(|r, w| w.bits(r.bits() & !self.mask_32()))
+        }
+    }
+
+    /// Only useful for output pins
+    /// See p.52 of the programmers guide for more information.
+    /// When configured for pulse mode, a given pin will set the non-default state for exactly
+    /// one clock cycle before returning to the configured default state
+    fn pulse_mode(&self, enable: bool, default_state: PinState) {
+        let portreg = self.port_reg();
+        unsafe {
+            if enable {
+                portreg
+                    .pulse()
+                    .modify(|r, w| w.bits(r.bits() | self.mask_32()));
+            } else {
+                portreg
+                    .pulse()
+                    .modify(|r, w| w.bits(r.bits() & !self.mask_32()));
+            }
+            if default_state == PinState::Low {
+                portreg
+                    .pulsebase()
+                    .modify(|r, w| w.bits(r.bits() & !self.mask_32()));
+            } else {
+                portreg
+                    .pulsebase()
+                    .modify(|r, w| w.bits(r.bits() | self.mask_32()));
+            }
+        }
+    }
+
+    /// Only useful for output pins
+    fn delay(&self, delay_1: bool, delay_2: bool) {
+        let portreg = self.port_reg();
+        unsafe {
+            if delay_1 {
+                portreg
+                    .delay1()
+                    .modify(|r, w| w.bits(r.bits() | self.mask_32()));
+            } else {
+                portreg
+                    .delay1()
+                    .modify(|r, w| w.bits(r.bits() & !self.mask_32()));
+            }
+            if delay_2 {
+                portreg
+                    .delay2()
+                    .modify(|r, w| w.bits(r.bits() | self.mask_32()));
+            } else {
+                portreg
+                    .delay2()
+                    .modify(|r, w| w.bits(r.bits() & !self.mask_32()));
+            }
+        }
+    }
+}

va108xx-hal/src/i2c.rs

@@ -0,0 +1,878 @@
+//! API for the I2C peripheral
+//!
+//! ## Examples
+//!
+//! - [REB1 I2C temperature sensor example](https://egit.irs.uni-stuttgart.de/rust/vorago-reb1/src/branch/main/examples/adt75-temp-sensor.rs)
+use crate::{
+    clock::{enable_peripheral_clock, PeripheralClocks},
+    pac,
+    time::Hertz,
+    typelevel::Sealed,
+};
+use core::marker::PhantomData;
+use embedded_hal::i2c::{self, Operation, SevenBitAddress, TenBitAddress};
+
+//==================================================================================================
+// Defintions
+//==================================================================================================
+
+#[derive(Debug, PartialEq, Eq, Copy, Clone)]
+pub enum FifoEmptyMode {
+    Stall = 0,
+    EndTransaction = 1,
+}
+
+#[derive(Debug, PartialEq, Eq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub enum Error {
+    InvalidTimingParams,
+    ArbitrationLost,
+    NackAddr,
+    /// Data not acknowledged in write operation
+    NackData,
+    /// Not enough data received in read operation
+    InsufficientDataReceived,
+    /// Number of bytes in transfer too large (larger than 0x7fe)
+    DataTooLarge,
+    WrongAddrMode,
+}
+
+impl embedded_hal::i2c::Error for Error {
+    fn kind(&self) -> embedded_hal::i2c::ErrorKind {
+        match self {
+            Error::ArbitrationLost => embedded_hal::i2c::ErrorKind::ArbitrationLoss,
+            Error::NackAddr => {
+                embedded_hal::i2c::ErrorKind::NoAcknowledge(i2c::NoAcknowledgeSource::Address)
+            }
+            Error::NackData => {
+                embedded_hal::i2c::ErrorKind::NoAcknowledge(i2c::NoAcknowledgeSource::Data)
+            }
+            Error::DataTooLarge
+            | Error::WrongAddrMode
+            | Error::InsufficientDataReceived
+            | Error::InvalidTimingParams => embedded_hal::i2c::ErrorKind::Other,
+        }
+    }
+}
+
+#[derive(Debug, PartialEq, Copy, Clone)]
+enum I2cCmd {
+    Start = 0b00,
+    Stop = 0b10,
+    StartWithStop = 0b11,
+    Cancel = 0b100,
+}
+
+#[derive(Debug, PartialEq, Eq, Copy, Clone)]
+pub enum I2cSpeed {
+    Regular100khz = 0,
+    Fast400khz = 1,
+}
+
+#[derive(Debug, PartialEq, Eq)]
+pub enum I2cDirection {
+    Send = 0,
+    Read = 1,
+}
+
+#[derive(Debug, PartialEq, Eq, Copy, Clone)]
+pub enum I2cAddress {
+    Regular(u8),
+    TenBit(u16),
+}
+
+//==================================================================================================
+// Config
+//==================================================================================================
+
+pub struct TrTfThighTlow(u8, u8, u8, u8);
+pub struct TsuStoTsuStaThdStaTBuf(u8, u8, u8, u8);
+
+pub struct TimingCfg {
+    // 4 bit max width
+    tr: u8,
+    // 4 bit max width
+    tf: u8,
+    // 4 bit max width
+    thigh: u8,
+    // 4 bit max width
+    tlow: u8,
+    // 4 bit max width
+    tsu_sto: u8,
+    // 4 bit max width
+    tsu_sta: u8,
+    // 4 bit max width
+    thd_sta: u8,
+    // 4 bit max width
+    tbuf: u8,
+}
+
+impl TimingCfg {
+    pub fn new(
+        first_16_bits: TrTfThighTlow,
+        second_16_bits: TsuStoTsuStaThdStaTBuf,
+    ) -> Result<Self, Error> {
+        if first_16_bits.0 > 0xf
+            || first_16_bits.1 > 0xf
+            || first_16_bits.2 > 0xf
+            || first_16_bits.3 > 0xf
+            || second_16_bits.0 > 0xf
+            || second_16_bits.1 > 0xf
+            || second_16_bits.2 > 0xf
+            || second_16_bits.3 > 0xf
+        {
+            return Err(Error::InvalidTimingParams);
+        }
+        Ok(TimingCfg {
+            tr: first_16_bits.0,
+            tf: first_16_bits.1,
+            thigh: first_16_bits.2,
+            tlow: first_16_bits.3,
+            tsu_sto: second_16_bits.0,
+            tsu_sta: second_16_bits.1,
+            thd_sta: second_16_bits.2,
+            tbuf: second_16_bits.3,
+        })
+    }
+
+    pub fn reg(&self) -> u32 {
+        (self.tbuf as u32) << 28
+            | (self.thd_sta as u32) << 24
+            | (self.tsu_sta as u32) << 20
+            | (self.tsu_sto as u32) << 16
+            | (self.tlow as u32) << 12
+            | (self.thigh as u32) << 8
+            | (self.tf as u32) << 4
+            | (self.tr as u32)
+    }
+}
+
+impl Default for TimingCfg {
+    fn default() -> Self {
+        TimingCfg {
+            tr: 0x02,
+            tf: 0x01,
+            thigh: 0x08,
+            tlow: 0x09,
+            tsu_sto: 0x8,
+            tsu_sta: 0x0a,
+            thd_sta: 0x8,
+            tbuf: 0xa,
+        }
+    }
+}
+
+pub struct MasterConfig {
+    pub tx_fe_mode: FifoEmptyMode,
+    pub rx_fe_mode: FifoEmptyMode,
+    /// Enable the analog delay glitch filter
+    pub alg_filt: bool,
+    /// Enable the digital glitch filter
+    pub dlg_filt: bool,
+    pub tm_cfg: Option<TimingCfg>,
+    // Loopback mode
+    // lbm: bool,
+}
+
+impl Default for MasterConfig {
+    fn default() -> Self {
+        MasterConfig {
+            tx_fe_mode: FifoEmptyMode::Stall,
+            rx_fe_mode: FifoEmptyMode::Stall,
+            alg_filt: false,
+            dlg_filt: false,
+            tm_cfg: None,
+        }
+    }
+}
+
+impl Sealed for MasterConfig {}
+
+pub struct SlaveConfig {
+    pub tx_fe_mode: FifoEmptyMode,
+    pub rx_fe_mode: FifoEmptyMode,
+    /// Maximum number of words before issuing a negative acknowledge.
+    /// Range should be 0 to 0x7fe. Setting the value to 0x7ff has the same effect as not setting
+    /// the enable bit since RXCOUNT stops counting at 0x7fe.
+    pub max_words: Option<usize>,
+    /// A received address is compared to the ADDRESS register (addr) using the address mask
+    /// (addr_mask). Those bits with a 1 in the address mask must match for there to be an address
+    /// match
+    pub addr: I2cAddress,
+    /// The default address mask will be 0x3ff to only allow full matches
+    pub addr_mask: Option<u16>,
+    /// Optionally specify a second I2C address the slave interface responds to
+    pub addr_b: Option<I2cAddress>,
+    pub addr_b_mask: Option<u16>,
+}
+
+impl SlaveConfig {
+    /// Build a default slave config given a specified slave address to respond to
+    pub fn new(addr: I2cAddress) -> Self {
+        SlaveConfig {
+            tx_fe_mode: FifoEmptyMode::Stall,
+            rx_fe_mode: FifoEmptyMode::Stall,
+            max_words: None,
+            addr,
+            addr_mask: None,
+            addr_b: None,
+            addr_b_mask: None,
+        }
+    }
+}
+
+impl Sealed for SlaveConfig {}
+
+//==================================================================================================
+// I2C Base
+//==================================================================================================
+
+pub struct I2cBase<I2C> {
+    i2c: I2C,
+    sys_clk: Hertz,
+}
+
+impl<I2C> I2cBase<I2C> {
+    #[inline]
+    fn unwrap_addr(addr: I2cAddress) -> (u16, u32) {
+        match addr {
+            I2cAddress::Regular(addr) => (addr as u16, 0 << 15),
+            I2cAddress::TenBit(addr) => (addr, 1 << 15),
+        }
+    }
+}
+
+macro_rules! i2c_base {
+    ($($I2CX:path: ($i2cx:ident, $clk_enb:path),)+) => {
+        $(
+            impl I2cBase<$I2CX> {
+                pub fn $i2cx(
+                    i2c: $I2CX,
+                    sys_clk: impl Into<Hertz>,
+                    speed_mode: I2cSpeed,
+                    ms_cfg: Option<&MasterConfig>,
+                    sl_cfg: Option<&SlaveConfig>,
+                    sys_cfg: Option<&mut va108xx::Sysconfig>,
+                ) -> Self {
+                    if let Some(sys_cfg) = sys_cfg {
+                        enable_peripheral_clock(sys_cfg, $clk_enb);
+                    }
+                    let mut i2c_base = I2cBase {
+                        i2c,
+                        sys_clk: sys_clk.into(),
+                    };
+                    if let Some(ms_cfg) = ms_cfg {
+                        i2c_base.cfg_master(ms_cfg);
+                    }
+
+                    if let Some(sl_cfg) = sl_cfg {
+                        i2c_base.cfg_slave(sl_cfg);
+                    }
+                    i2c_base.cfg_clk_scale(speed_mode);
+                    i2c_base
+                }
+
+                fn cfg_master(&mut self, ms_cfg: &MasterConfig) {
+                    let (txfemd, rxfemd) = match (ms_cfg.tx_fe_mode, ms_cfg.rx_fe_mode) {
+                        (FifoEmptyMode::Stall, FifoEmptyMode::Stall) => (false, false),
+                        (FifoEmptyMode::Stall, FifoEmptyMode::EndTransaction) => (false, true),
+                        (FifoEmptyMode::EndTransaction, FifoEmptyMode::Stall) => (true, false),
+                        (FifoEmptyMode::EndTransaction, FifoEmptyMode::EndTransaction) => (true, true),
+                    };
+                    self.i2c.ctrl().modify(|_, w| {
+                        w.txfemd().bit(txfemd);
+                        w.rxffmd().bit(rxfemd);
+                        w.dlgfilter().bit(ms_cfg.dlg_filt);
+                        w.algfilter().bit(ms_cfg.alg_filt)
+                    });
+                    if let Some(ref tm_cfg) = ms_cfg.tm_cfg {
+                        self.i2c.tmconfig().write(|w| unsafe { w.bits(tm_cfg.reg()) });
+                    }
+                    self.i2c.fifo_clr().write(|w| {
+                        w.rxfifo().set_bit();
+                        w.txfifo().set_bit()
+                    });
+                }
+
+                fn cfg_slave(&mut self, sl_cfg: &SlaveConfig) {
+                    let (txfemd, rxfemd) = match (sl_cfg.tx_fe_mode, sl_cfg.rx_fe_mode) {
+                        (FifoEmptyMode::Stall, FifoEmptyMode::Stall) => (false, false),
+                        (FifoEmptyMode::Stall, FifoEmptyMode::EndTransaction) => (false, true),
+                        (FifoEmptyMode::EndTransaction, FifoEmptyMode::Stall) => (true, false),
+                        (FifoEmptyMode::EndTransaction, FifoEmptyMode::EndTransaction) => (true, true),
+                    };
+                    self.i2c.s0_ctrl().modify(|_, w| {
+                        w.txfemd().bit(txfemd);
+                        w.rxffmd().bit(rxfemd)
+                    });
+                    self.i2c.s0_fifo_clr().write(|w| {
+                        w.rxfifo().set_bit();
+                        w.txfifo().set_bit()
+                    });
+                    let max_words = sl_cfg.max_words;
+                    if let Some(max_words) = max_words {
+                        self.i2c
+                            .s0_maxwords()
+                            .write(|w| unsafe { w.bits(1 << 31 | max_words as u32) });
+                    }
+                    let (addr, addr_mode_mask) = Self::unwrap_addr(sl_cfg.addr);
+                    // The first bit is the read/write value. Normally, both read and write are matched
+                    // using the RWMASK bit of the address mask register
+                    self.i2c
+                        .s0_address()
+                        .write(|w| unsafe { w.bits((addr << 1) as u32 | addr_mode_mask) });
+                    if let Some(addr_mask) = sl_cfg.addr_mask {
+                        self.i2c
+                            .s0_addressmask()
+                            .write(|w| unsafe { w.bits((addr_mask << 1) as u32) });
+                    }
+                    if let Some(addr_b) = sl_cfg.addr_b {
+                        let (addr, addr_mode_mask) = Self::unwrap_addr(addr_b);
+                        self.i2c
+                            .s0_addressb()
+                            .write(|w| unsafe { w.bits((addr << 1) as u32 | addr_mode_mask) })
+                    }
+                    if let Some(addr_b_mask) = sl_cfg.addr_b_mask {
+                        self.i2c
+                            .s0_addressmaskb()
+                            .write(|w| unsafe { w.bits((addr_b_mask << 1) as u32) })
+                    }
+                }
+
+                #[inline]
+                pub fn filters(&mut self, digital_filt: bool, analog_filt: bool) {
+                    self.i2c.ctrl().modify(|_, w| {
+                        w.dlgfilter().bit(digital_filt);
+                        w.algfilter().bit(analog_filt)
+                    });
+                }
+
+                #[inline]
+                pub fn fifo_empty_mode(&mut self, rx: FifoEmptyMode, tx: FifoEmptyMode) {
+                    self.i2c.ctrl().modify(|_, w| {
+                        w.txfemd().bit(tx as u8 != 0);
+                        w.rxffmd().bit(rx as u8 != 0)
+                    });
+                }
+
+                fn calc_clk_div(&self, speed_mode: I2cSpeed) -> u8 {
+                    if speed_mode == I2cSpeed::Regular100khz {
+                        ((self.sys_clk.raw() / (u32::pow(10, 5) * 20)) - 1) as u8
+                    } else {
+                        (((10 * self.sys_clk.raw()) / u32::pow(10, 8)) - 1) as u8
+                    }
+                }
+
+                /// Configures the clock scale for a given speed mode setting
+                pub fn cfg_clk_scale(&mut self, speed_mode: I2cSpeed) {
+                    self.i2c.clkscale().write(|w| unsafe {
+                        w.bits((speed_mode as u32) << 31 | self.calc_clk_div(speed_mode) as u32)
+                    });
+                }
+
+                pub fn load_address(&mut self, addr: u16) {
+                    // Load address
+                    self.i2c
+                        .address()
+                        .write(|w| unsafe { w.bits((addr << 1) as u32) });
+                }
+
+                #[inline]
+                fn stop_cmd(&mut self) {
+                    self.i2c
+                        .cmd()
+                        .write(|w| unsafe { w.bits(I2cCmd::Stop as u32) });
+                }
+            }
+        )+
+    }
+}
+
+// Unique mode to use the loopback functionality
+// pub struct I2cLoopback<I2C> {
+//     i2c_base: I2cBase<I2C>,
+//     master_cfg: MasterConfig,
+//     slave_cfg: SlaveConfig,
+// }
+
+i2c_base!(
+    pac::I2ca: (i2ca, PeripheralClocks::I2c0),
+    pac::I2cb: (i2cb, PeripheralClocks::I2c1),
+);
+
+//==================================================================================================
+// I2C Master
+//==================================================================================================
+
+pub struct I2cMaster<I2C, ADDR = SevenBitAddress> {
+    i2c_base: I2cBase<I2C>,
+    _addr: PhantomData<ADDR>,
+}
+
+macro_rules! i2c_master {
+    ($($I2CX:path: ($i2cx:ident, $clk_enb:path),)+) => {
+        $(
+            impl<ADDR> I2cMaster<$I2CX, ADDR> {
+                pub fn $i2cx(
+                    i2c: $I2CX,
+                    cfg: MasterConfig,
+                    sys_clk: impl Into<Hertz> + Copy,
+                    speed_mode: I2cSpeed,
+                    sys_cfg: Option<&mut pac::Sysconfig>,
+                ) -> Self {
+                    I2cMaster {
+                        i2c_base: I2cBase::$i2cx(
+                            i2c,
+                            sys_clk,
+                            speed_mode,
+                            Some(&cfg),
+                            None,
+                            sys_cfg
+                        ),
+                        _addr: PhantomData,
+                    }
+                    .enable_master()
+                }
+
+                #[inline]
+                pub fn cancel_transfer(&self) {
+                    self.i2c_base
+                        .i2c
+                        .cmd()
+                        .write(|w| unsafe { w.bits(I2cCmd::Cancel as u32) });
+                }
+
+                #[inline]
+                pub fn clear_tx_fifo(&self) {
+                    self.i2c_base.i2c.fifo_clr().write(|w| w.txfifo().set_bit());
+                }
+
+                #[inline]
+                pub fn clear_rx_fifo(&self) {
+                    self.i2c_base.i2c.fifo_clr().write(|w| w.rxfifo().set_bit());
+                }
+
+                #[inline]
+                pub fn enable_master(self) -> Self {
+                    self.i2c_base.i2c.ctrl().modify(|_, w| w.enable().set_bit());
+                    self
+                }
+
+                #[inline]
+                pub fn disable_master(self) -> Self {
+                    self.i2c_base.i2c.ctrl().modify(|_, w| w.enable().clear_bit());
+                    self
+                }
+
+                #[inline(always)]
+                fn load_fifo(&self, word: u8) {
+                    self.i2c_base
+                        .i2c
+                        .data()
+                        .write(|w| unsafe { w.bits(word as u32) });
+                }
+
+                #[inline(always)]
+                fn read_fifo(&self) -> u8 {
+                    self.i2c_base.i2c.data().read().bits() as u8
+                }
+
+                fn error_handler_write(&mut self, init_cmd: &I2cCmd) {
+                    self.clear_tx_fifo();
+                    if *init_cmd == I2cCmd::Start {
+                        self.i2c_base.stop_cmd()
+                    }
+                }
+
+                fn write_base(
+                    &mut self,
+                    addr: I2cAddress,
+                    init_cmd: I2cCmd,
+                    bytes: impl IntoIterator<Item = u8>,
+                ) -> Result<(), Error> {
+                    let mut iter = bytes.into_iter();
+                    // Load address
+                    let (addr, addr_mode_bit) = I2cBase::<$I2CX>::unwrap_addr(addr);
+                    self.i2c_base.i2c.address().write(|w| unsafe {
+                        w.bits(I2cDirection::Send as u32 | (addr << 1) as u32 | addr_mode_bit)
+                    });
+
+                    self.i2c_base
+                        .i2c
+                        .cmd()
+                        .write(|w| unsafe { w.bits(init_cmd as u32) });
+                    let mut load_if_next_available = || {
+                        if let Some(next_byte) = iter.next() {
+                            self.load_fifo(next_byte);
+                        }
+                    };
+                    loop {
+                        let status_reader = self.i2c_base.i2c.status().read();
+                        if status_reader.arblost().bit_is_set() {
+                            self.error_handler_write(&init_cmd);
+                            return Err(Error::ArbitrationLost);
+                        } else if status_reader.nackaddr().bit_is_set() {
+                            self.error_handler_write(&init_cmd);
+                            return Err(Error::NackAddr);
+                        } else if status_reader.nackdata().bit_is_set() {
+                            self.error_handler_write(&init_cmd);
+                            return Err(Error::NackData);
+                        } else if status_reader.idle().bit_is_set() {
+                            return Ok(());
+                        } else {
+                            while !status_reader.txnfull().bit_is_set() {
+                                load_if_next_available();
+                            }
+                        }
+                    }
+                }
+
+                fn write_from_buffer(
+                    &mut self,
+                    init_cmd: I2cCmd,
+                    addr: I2cAddress,
+                    output: &[u8],
+                ) -> Result<(), Error> {
+                    let len = output.len();
+                    // It should theoretically possible to transfer larger data sizes by tracking
+                    // the number of sent words and setting it to 0x7fe as soon as only that many
+                    // bytes are remaining. However, large transfer like this are not common. This
+                    // feature will therefore not be supported for now.
+                    if len > 0x7fe {
+                        return Err(Error::DataTooLarge);
+                    }
+                    // Load number of words
+                    self.i2c_base
+                        .i2c
+                        .words()
+                        .write(|w| unsafe { w.bits(len as u32) });
+                    let mut bytes = output.iter();
+                    // FIFO has a depth of 16. We load slightly above the trigger level
+                    // but not all of it because the transaction might fail immediately
+                    const FILL_DEPTH: usize = 12;
+
+                    // load the FIFO
+                    for _ in 0..core::cmp::min(FILL_DEPTH, len) {
+                        self.load_fifo(*bytes.next().unwrap());
+                    }
+
+                    self.write_base(addr, init_cmd, output.iter().cloned())
+                }
+
+                fn read_internal(&mut self, addr: I2cAddress, buffer: &mut [u8]) -> Result<(), Error> {
+                    let len = buffer.len();
+                    // It should theoretically possible to transfer larger data sizes by tracking
+                    // the number of sent words and setting it to 0x7fe as soon as only that many
+                    // bytes are remaining. However, large transfer like this are not common. This
+                    // feature will therefore not be supported for now.
+                    if len > 0x7fe {
+                        return Err(Error::DataTooLarge);
+                    }
+                    // Clear the receive FIFO
+                    self.clear_rx_fifo();
+
+                    // Load number of words
+                    self.i2c_base
+                        .i2c
+                        .words()
+                        .write(|w| unsafe { w.bits(len as u32) });
+                    let (addr, addr_mode_bit) = match addr {
+                        I2cAddress::Regular(addr) => (addr as u16, 0 << 15),
+                        I2cAddress::TenBit(addr) => (addr, 1 << 15),
+                    };
+                    // Load address
+                    self.i2c_base.i2c.address().write(|w| unsafe {
+                        w.bits(I2cDirection::Read as u32 | (addr << 1) as u32 | addr_mode_bit)
+                    });
+
+                    let mut buf_iter = buffer.iter_mut();
+                    let mut read_bytes = 0;
+                    // Start receive transfer
+                    self.i2c_base
+                        .i2c
+                        .cmd()
+                        .write(|w| unsafe { w.bits(I2cCmd::StartWithStop as u32) });
+                    let mut read_if_next_available = || {
+                        if let Some(next_byte) = buf_iter.next() {
+                            *next_byte = self.read_fifo();
+                        }
+                    };
+                    loop {
+                        let status_reader = self.i2c_base.i2c.status().read();
+                        if status_reader.arblost().bit_is_set() {
+                            self.clear_rx_fifo();
+                            return Err(Error::ArbitrationLost);
+                        } else if status_reader.nackaddr().bit_is_set() {
+                            self.clear_rx_fifo();
+                            return Err(Error::NackAddr);
+                        } else if status_reader.idle().bit_is_set() {
+                            if read_bytes != len {
+                                return Err(Error::InsufficientDataReceived);
+                            }
+                            return Ok(());
+                        } else if status_reader.rxnempty().bit_is_set() {
+                            read_if_next_available();
+                            read_bytes += 1;
+                        }
+                    }
+                }
+            }
+
+            //======================================================================================
+            // Embedded HAL I2C implementations
+            //======================================================================================
+
+            impl embedded_hal::i2c::ErrorType for I2cMaster<$I2CX, SevenBitAddress> {
+                type Error = Error;
+            }
+            impl embedded_hal::i2c::I2c for I2cMaster<$I2CX, SevenBitAddress> {
+                fn transaction(
+                    &mut self,
+                    address: SevenBitAddress,
+                    operations: &mut [Operation<'_>],
+                ) -> Result<(), Self::Error> {
+                    for operation in operations {
+                        match operation {
+                            Operation::Read(buf) => self.read_internal(I2cAddress::Regular(address), buf)?,
+                            Operation::Write(buf) => self.write_from_buffer(
+                                I2cCmd::StartWithStop,
+                                I2cAddress::Regular(address),
+                                buf,
+                            )?,
+                        }
+                    }
+                    Ok(())
+                }
+            }
+
+            impl embedded_hal::i2c::ErrorType for I2cMaster<$I2CX, TenBitAddress> {
+                type Error = Error;
+            }
+            impl embedded_hal::i2c::I2c<TenBitAddress> for I2cMaster<$I2CX, TenBitAddress> {
+                fn transaction(
+                    &mut self,
+                    address: TenBitAddress,
+                    operations: &mut [Operation<'_>],
+                ) -> Result<(), Self::Error> {
+                    for operation in operations {
+                        match operation {
+                            Operation::Read(buf) => self.read_internal(I2cAddress::TenBit(address), buf)?,
+                            Operation::Write(buf) => self.write_from_buffer(
+                                I2cCmd::StartWithStop,
+                                I2cAddress::TenBit(address),
+                                buf,
+                            )?,
+                        }
+                    }
+                    Ok(())
+                }
+            }
+        )+
+    }
+}
+
+i2c_master!(
+    pac::I2ca: (i2ca, PeripheralClocks::I2c0),
+    pac::I2cb: (i2cb, PeripheralClocks::I2c1),
+);
+
+//==================================================================================================
+// I2C Slave
+//==================================================================================================
+
+pub struct I2cSlave<I2C, ADDR = SevenBitAddress> {
+    i2c_base: I2cBase<I2C>,
+    _addr: PhantomData<ADDR>,
+}
+
+macro_rules! i2c_slave {
+    ($($I2CX:path: ($i2cx:ident, $i2cx_slave:ident),)+) => {
+        $(
+            impl<ADDR> I2cSlave<$I2CX, ADDR> {
+                fn $i2cx_slave(
+                    i2c: $I2CX,
+                    cfg: SlaveConfig,
+                    sys_clk: impl Into<Hertz>,
+                    speed_mode: I2cSpeed,
+                    sys_cfg: Option<&mut pac::Sysconfig>,
+                ) -> Self {
+                    I2cSlave {
+                        i2c_base: I2cBase::$i2cx(
+                            i2c,
+                            sys_clk,
+                            speed_mode,
+                            None,
+                            Some(&cfg),
+                            sys_cfg
+                        ),
+                        _addr: PhantomData,
+                    }
+                    .enable_slave()
+                }
+
+                #[inline]
+                pub fn enable_slave(self) -> Self {
+                    self.i2c_base
+                        .i2c
+                        .s0_ctrl()
+                        .modify(|_, w| w.enable().set_bit());
+                    self
+                }
+
+                #[inline]
+                pub fn disable_slave(self) -> Self {
+                    self.i2c_base
+                        .i2c
+                        .s0_ctrl()
+                        .modify(|_, w| w.enable().clear_bit());
+                    self
+                }
+
+                #[inline(always)]
+                fn load_fifo(&self, word: u8) {
+                    self.i2c_base
+                        .i2c
+                        .s0_data()
+                        .write(|w| unsafe { w.bits(word as u32) });
+                }
+
+                #[inline(always)]
+                fn read_fifo(&self) -> u8 {
+                    self.i2c_base.i2c.s0_data().read().bits() as u8
+                }
+
+                #[inline]
+                fn clear_tx_fifo(&self) {
+                    self.i2c_base
+                        .i2c
+                        .s0_fifo_clr()
+                        .write(|w| w.txfifo().set_bit());
+                }
+
+                #[inline]
+                fn clear_rx_fifo(&self) {
+                    self.i2c_base
+                        .i2c
+                        .s0_fifo_clr()
+                        .write(|w| w.rxfifo().set_bit());
+                }
+
+                /// Get the last address that was matched by the slave control and the corresponding
+                /// master direction
+                pub fn last_address(&self) -> (I2cDirection, u32) {
+                    let bits = self.i2c_base.i2c.s0_lastaddress().read().bits();
+                    match bits & 0x01 {
+                        0 => (I2cDirection::Send, bits >> 1),
+                        1 => (I2cDirection::Read, bits >> 1),
+                        _ => (I2cDirection::Send, bits >> 1),
+                    }
+                }
+
+                pub fn write(&mut self, output: &[u8]) -> Result<(), Error> {
+                    let len = output.len();
+                    // It should theoretically possible to transfer larger data sizes by tracking
+                    // the number of sent words and setting it to 0x7fe as soon as only that many
+                    // bytes are remaining. However, large transfer like this are not common. This
+                    // feature will therefore not be supported for now.
+                    if len > 0x7fe {
+                        return Err(Error::DataTooLarge);
+                    }
+                    let mut bytes = output.iter();
+                    // FIFO has a depth of 16. We load slightly above the trigger level
+                    // but not all of it because the transaction might fail immediately
+                    const FILL_DEPTH: usize = 12;
+
+                    // load the FIFO
+                    for _ in 0..core::cmp::min(FILL_DEPTH, len) {
+                        self.load_fifo(*bytes.next().unwrap());
+                    }
+
+                    let status_reader = self.i2c_base.i2c.s0_status().read();
+                    let mut load_if_next_available = || {
+                        if let Some(next_byte) = bytes.next() {
+                            self.load_fifo(*next_byte);
+                        }
+                    };
+                    loop {
+                        if status_reader.nackdata().bit_is_set() {
+                            self.clear_tx_fifo();
+                            return Err(Error::NackData);
+                        } else if status_reader.idle().bit_is_set() {
+                            return Ok(());
+                        } else {
+                            while !status_reader.txnfull().bit_is_set() {
+                                load_if_next_available();
+                            }
+                        }
+                    }
+                }
+
+                pub fn read(&mut self, buffer: &mut [u8]) -> Result<(), Error> {
+                    let len = buffer.len();
+                    // It should theoretically possible to transfer larger data sizes by tracking
+                    // the number of sent words and setting it to 0x7fe as soon as only that many
+                    // bytes are remaining. However, large transfer like this are not common. This
+                    // feature will therefore not be supported for now.
+                    if len > 0x7fe {
+                        return Err(Error::DataTooLarge);
+                    }
+                    // Clear the receive FIFO
+                    self.clear_rx_fifo();
+
+                    let mut buf_iter = buffer.iter_mut();
+                    let mut read_bytes = 0;
+                    let mut read_if_next_available = || {
+                        if let Some(next_byte) = buf_iter.next() {
+                            *next_byte = self.read_fifo();
+                        }
+                    };
+                    loop {
+                        let status_reader = self.i2c_base.i2c.s0_status().read();
+                        if status_reader.idle().bit_is_set() {
+                            if read_bytes != len {
+                                return Err(Error::InsufficientDataReceived);
+                            }
+                            return Ok(());
+                        } else if status_reader.rxnempty().bit_is_set() {
+                            read_bytes += 1;
+                            read_if_next_available();
+                        }
+                    }
+                }
+            }
+
+
+            impl I2cSlave<$I2CX, SevenBitAddress> {
+                /// Create a new I2C slave for seven bit addresses
+                ///
+                /// Returns a [`Error::WrongAddrMode`] error if a ten bit address is passed
+                pub fn i2ca(
+                    i2c: $I2CX,
+                    cfg: SlaveConfig,
+                    sys_clk: impl Into<Hertz>,
+                    speed_mode: I2cSpeed,
+                    sys_cfg: Option<&mut pac::Sysconfig>,
+                ) -> Result<Self, Error> {
+                    if let I2cAddress::TenBit(_) = cfg.addr {
+                        return Err(Error::WrongAddrMode);
+                    }
+                    Ok(Self::$i2cx_slave(i2c, cfg, sys_clk, speed_mode, sys_cfg))
+                }
+            }
+
+            impl I2cSlave<$I2CX, TenBitAddress> {
+                pub fn $i2cx(
+                    i2c: $I2CX,
+                    cfg: SlaveConfig,
+                    sys_clk: impl Into<Hertz>,
+                    speed_mode: I2cSpeed,
+                    sys_cfg: Option<&mut pac::Sysconfig>,
+                ) -> Self {
+                    Self::$i2cx_slave(i2c, cfg, sys_clk, speed_mode, sys_cfg)
+                }
+            }
+        )+
+    }
+}
+
+i2c_slave!(pac::I2ca: (i2ca, i2ca_slave), pac::I2cb: (i2cb, i2cb_slave),);

va108xx-hal/src/lib.rs

@@ -0,0 +1,99 @@
+#![no_std]
+
+pub use va108xx;
+pub use va108xx as pac;
+
+pub mod clock;
+pub mod gpio;
+pub mod i2c;
+pub mod prelude;
+pub mod pwm;
+pub mod spi;
+pub mod sysconfig;
+pub mod time;
+pub mod timer;
+pub mod typelevel;
+pub mod uart;
+pub mod utility;
+
+#[derive(Debug, Eq, Copy, Clone, PartialEq)]
+pub enum FunSel {
+    Sel1 = 0b01,
+    Sel2 = 0b10,
+    Sel3 = 0b11,
+}
+
+#[derive(Debug, Copy, Clone, PartialEq, Eq)]
+pub enum PortSel {
+    PortA,
+    PortB,
+}
+
+#[derive(Copy, Clone, PartialEq, Eq)]
+pub enum PeripheralSelect {
+    PortA = 0,
+    PortB = 1,
+    Spi0 = 4,
+    Spi1 = 5,
+    Spi2 = 6,
+    Uart0 = 8,
+    Uart1 = 9,
+    I2c0 = 16,
+    I2c1 = 17,
+    Irqsel = 21,
+    Ioconfig = 22,
+    Utility = 23,
+    Gpio = 24,
+}
+
+/// Generic IRQ config which can be used to specify whether the HAL driver will
+/// use the IRQSEL register to route an interrupt, and whether the IRQ will be unmasked in the
+/// Cortex-M0 NVIC. Both are generally necessary for IRQs to work, but the user might perform
+/// this steps themselves
+#[derive(Debug, PartialEq, Eq, Clone, Copy)]
+pub struct IrqCfg {
+    /// Interrupt target vector. Should always be set, might be required for disabling IRQs
+    pub irq: pac::Interrupt,
+    /// Specfiy whether IRQ should be routed to an IRQ vector using the IRQSEL peripheral
+    pub route: bool,
+    /// Specify whether the IRQ is unmasked in the Cortex-M NVIC
+    pub enable: bool,
+}
+
+impl IrqCfg {
+    pub fn new(irq: pac::Interrupt, route: bool, enable: bool) -> Self {
+        IrqCfg { irq, route, enable }
+    }
+}
+
+#[derive(Debug, PartialEq, Eq)]
+pub struct InvalidPin(pub(crate) ());
+
+/// Can be used to manually manipulate the function select of port pins
+pub fn port_mux(
+    ioconfig: &mut pac::Ioconfig,
+    port: PortSel,
+    pin: u8,
+    funsel: FunSel,
+) -> Result<(), InvalidPin> {
+    match port {
+        PortSel::PortA => {
+            if pin > 31 {
+                return Err(InvalidPin(()));
+            }
+            ioconfig
+                .porta(pin as usize)
+                .modify(|_, w| unsafe { w.funsel().bits(funsel as u8) });
+            Ok(())
+        }
+        PortSel::PortB => {
+            if pin > 23 {
+                return Err(InvalidPin(()));
+            }
+            ioconfig
+                .portb0(pin as usize)
+                .modify(|_, w| unsafe { w.funsel().bits(funsel as u8) });
+            Ok(())
+        }
+    }
+}

va108xx-hal/src/prelude.rs

@@ -0,0 +1,3 @@
+//! Prelude
+pub use fugit::ExtU32 as _;
+pub use fugit::RateExtU32 as _;

va108xx-hal/src/pwm.rs

@@ -0,0 +1,387 @@
+//! API for Pulse-Width Modulation (PWM)
+//!
+//! The Vorago VA108xx devices use the TIM peripherals to perform PWM related tasks
+//!
+//! ## Examples
+//!
+//! - [PWM example](https://egit.irs.uni-stuttgart.de/rust/va108xx-hal/src/branch/main/examples/pwm.rs)
+use core::convert::Infallible;
+use core::marker::PhantomData;
+
+use crate::pac;
+use crate::{clock::enable_peripheral_clock, gpio::DynPinId};
+pub use crate::{gpio::PinId, time::Hertz, timer::*};
+
+const DUTY_MAX: u16 = u16::MAX;
+
+pub struct PwmBase {
+    sys_clk: Hertz,
+    /// For PWMB, this is the upper limit
+    current_duty: u16,
+    /// For PWMA, this value will not be used
+    current_lower_limit: u16,
+    current_period: Hertz,
+    current_rst_val: u32,
+}
+
+enum StatusSelPwm {
+    PwmA = 3,
+    PwmB = 4,
+}
+
+pub struct PwmA {}
+pub struct PwmB {}
+
+//==================================================================================================
+// Common
+//==================================================================================================
+
+macro_rules! pwm_common_func {
+    () => {
+        #[inline]
+        fn enable_pwm_a(&mut self) {
+            self.reg
+                .reg()
+                .ctrl()
+                .modify(|_, w| unsafe { w.status_sel().bits(StatusSelPwm::PwmA as u8) });
+        }
+
+        #[inline]
+        fn enable_pwm_b(&mut self) {
+            self.reg
+                .reg()
+                .ctrl()
+                .modify(|_, w| unsafe { w.status_sel().bits(StatusSelPwm::PwmB as u8) });
+        }
+
+        #[inline]
+        pub fn get_period(&self) -> Hertz {
+            self.pwm_base.current_period
+        }
+
+        #[inline]
+        pub fn set_period(&mut self, period: impl Into<Hertz>) {
+            self.pwm_base.current_period = period.into();
+            // Avoid division by 0
+            if self.pwm_base.current_period.raw() == 0 {
+                return;
+            }
+            self.pwm_base.current_rst_val =
+                self.pwm_base.sys_clk.raw() / self.pwm_base.current_period.raw();
+            self.reg
+                .reg()
+                .rst_value()
+                .write(|w| unsafe { w.bits(self.pwm_base.current_rst_val) });
+        }
+
+        #[inline]
+        pub fn disable(&mut self) {
+            self.reg.reg().ctrl().modify(|_, w| w.enable().clear_bit());
+        }
+
+        #[inline]
+        pub fn enable(&mut self) {
+            self.reg.reg().ctrl().modify(|_, w| w.enable().set_bit());
+        }
+
+        #[inline]
+        pub fn period(&self) -> Hertz {
+            self.pwm_base.current_period
+        }
+
+        #[inline(always)]
+        pub fn duty(&self) -> u16 {
+            self.pwm_base.current_duty
+        }
+    };
+}
+
+macro_rules! pwmb_func {
+    () => {
+        pub fn pwmb_lower_limit(&self) -> u16 {
+            self.pwm_base.current_lower_limit
+        }
+
+        pub fn pwmb_upper_limit(&self) -> u16 {
+            self.pwm_base.current_duty
+        }
+
+        /// Set the lower limit for PWMB
+        ///
+        /// The PWM signal will be 1 as long as the current RST counter is larger than
+        /// the lower limit. For example, with a lower limit of 0.5 and and an upper limit
+        /// of 0.7, Only a fixed period between 0.5 * period and 0.7 * period will be in a high
+        /// state
+        pub fn set_pwmb_lower_limit(&mut self, duty: u16) {
+            self.pwm_base.current_lower_limit = duty;
+            let pwmb_val: u64 = (self.pwm_base.current_rst_val as u64
+                * self.pwm_base.current_lower_limit as u64)
+                / DUTY_MAX as u64;
+            self.reg
+                .reg()
+                .pwmb_value()
+                .write(|w| unsafe { w.bits(pwmb_val as u32) });
+        }
+
+        /// Set the higher limit for PWMB
+        ///
+        /// The PWM signal will be 1 as long as the current RST counter is smaller than
+        /// the higher limit. For example, with a lower limit of 0.5 and and an upper limit
+        /// of 0.7, Only a fixed period between 0.5 * period and 0.7 * period will be in a high
+        /// state
+        pub fn set_pwmb_upper_limit(&mut self, duty: u16) {
+            self.pwm_base.current_duty = duty;
+            let pwma_val: u64 = (self.pwm_base.current_rst_val as u64
+                * self.pwm_base.current_duty as u64)
+                / DUTY_MAX as u64;
+            self.reg
+                .reg()
+                .pwma_value()
+                .write(|w| unsafe { w.bits(pwma_val as u32) });
+        }
+    };
+}
+
+//==================================================================================================
+// Strongly typed PWM pin
+//==================================================================================================
+
+pub struct PwmPin<Pin: TimPin, Tim: ValidTim, Mode = PwmA> {
+    reg: TimAndPinRegister<Pin, Tim>,
+    pwm_base: PwmBase,
+    mode: PhantomData<Mode>,
+}
+
+impl<Pin: TimPin, Tim: ValidTim, Mode> PwmPin<Pin, Tim, Mode>
+where
+    (Pin, Tim): ValidTimAndPin<Pin, Tim>,
+{
+    /// Create a new stronlgy typed PWM pin
+    pub fn new(
+        vtp: (Pin, Tim),
+        sys_clk: impl Into<Hertz> + Copy,
+        sys_cfg: &mut pac::Sysconfig,
+        initial_period: impl Into<Hertz> + Copy,
+    ) -> Self {
+        let mut pin = PwmPin {
+            pwm_base: PwmBase {
+                current_duty: 0,
+                current_lower_limit: 0,
+                current_period: initial_period.into(),
+                current_rst_val: 0,
+                sys_clk: sys_clk.into(),
+            },
+            reg: unsafe { TimAndPinRegister::new(vtp.0, vtp.1) },
+            mode: PhantomData,
+        };
+        enable_peripheral_clock(sys_cfg, crate::clock::PeripheralClocks::Gpio);
+        enable_peripheral_clock(sys_cfg, crate::clock::PeripheralClocks::Ioconfig);
+        sys_cfg
+            .tim_clk_enable()
+            .modify(|r, w| unsafe { w.bits(r.bits() | pin.reg.mask_32()) });
+        pin.enable_pwm_a();
+        pin.set_period(initial_period);
+        pin
+    }
+    pub fn release(self) -> (Pin, Tim) {
+        self.reg.release()
+    }
+
+    pwm_common_func!();
+}
+
+impl<Pin: TimPin, Tim: ValidTim> From<PwmPin<Pin, Tim, PwmA>> for PwmPin<Pin, Tim, PwmB>
+where
+    (Pin, Tim): ValidTimAndPin<Pin, Tim>,
+{
+    fn from(other: PwmPin<Pin, Tim, PwmA>) -> Self {
+        let mut pwmb = Self {
+            reg: other.reg,
+            pwm_base: other.pwm_base,
+            mode: PhantomData,
+        };
+        pwmb.enable_pwm_b();
+        pwmb
+    }
+}
+
+impl<PIN: TimPin, TIM: ValidTim> From<PwmPin<PIN, TIM, PwmB>> for PwmPin<PIN, TIM, PwmA>
+where
+    (PIN, TIM): ValidTimAndPin<PIN, TIM>,
+{
+    fn from(other: PwmPin<PIN, TIM, PwmB>) -> Self {
+        let mut pwmb = Self {
+            reg: other.reg,
+            pwm_base: other.pwm_base,
+            mode: PhantomData,
+        };
+        pwmb.enable_pwm_a();
+        pwmb
+    }
+}
+
+impl<Pin: TimPin, Tim: ValidTim> PwmPin<Pin, Tim, PwmA>
+where
+    (Pin, Tim): ValidTimAndPin<Pin, Tim>,
+{
+    pub fn pwma(
+        vtp: (Pin, Tim),
+        sys_clk: impl Into<Hertz> + Copy,
+        sys_cfg: &mut pac::Sysconfig,
+        initial_period: impl Into<Hertz> + Copy,
+    ) -> Self {
+        let mut pin: PwmPin<Pin, Tim, PwmA> = Self::new(vtp, sys_clk, sys_cfg, initial_period);
+        pin.enable_pwm_a();
+        pin
+    }
+}
+
+impl<Pin: TimPin, Tim: ValidTim> PwmPin<Pin, Tim, PwmB>
+where
+    (Pin, Tim): ValidTimAndPin<Pin, Tim>,
+{
+    pub fn pwmb(
+        vtp: (Pin, Tim),
+        sys_clk: impl Into<Hertz> + Copy,
+        sys_cfg: &mut pac::Sysconfig,
+        initial_period: impl Into<Hertz> + Copy,
+    ) -> Self {
+        let mut pin: PwmPin<Pin, Tim, PwmB> = Self::new(vtp, sys_clk, sys_cfg, initial_period);
+        pin.enable_pwm_b();
+        pin
+    }
+}
+
+//==================================================================================================
+// Reduced PWM pin
+//==================================================================================================
+
+/// Reduced version where type information is deleted
+pub struct ReducedPwmPin<Mode = PwmA> {
+    reg: TimDynRegister,
+    pwm_base: PwmBase,
+    pin_id: DynPinId,
+    mode: PhantomData<Mode>,
+}
+
+impl<PIN: TimPin, TIM: ValidTim> From<PwmPin<PIN, TIM>> for ReducedPwmPin<PwmA> {
+    fn from(pwm_pin: PwmPin<PIN, TIM>) -> Self {
+        ReducedPwmPin {
+            reg: TimDynRegister::from(pwm_pin.reg),
+            pwm_base: pwm_pin.pwm_base,
+            pin_id: PIN::DYN,
+            mode: PhantomData,
+        }
+    }
+}
+
+impl<MODE> ReducedPwmPin<MODE> {
+    pwm_common_func!();
+}
+
+impl From<ReducedPwmPin<PwmA>> for ReducedPwmPin<PwmB> {
+    fn from(other: ReducedPwmPin<PwmA>) -> Self {
+        let mut pwmb = Self {
+            reg: other.reg,
+            pwm_base: other.pwm_base,
+            pin_id: other.pin_id,
+            mode: PhantomData,
+        };
+        pwmb.enable_pwm_b();
+        pwmb
+    }
+}
+
+impl From<ReducedPwmPin<PwmB>> for ReducedPwmPin<PwmA> {
+    fn from(other: ReducedPwmPin<PwmB>) -> Self {
+        let mut pwmb = Self {
+            reg: other.reg,
+            pwm_base: other.pwm_base,
+            pin_id: other.pin_id,
+            mode: PhantomData,
+        };
+        pwmb.enable_pwm_a();
+        pwmb
+    }
+}
+
+//==================================================================================================
+// PWMB implementations
+//==================================================================================================
+
+impl<PIN: TimPin, TIM: ValidTim> PwmPin<PIN, TIM, PwmB>
+where
+    (PIN, TIM): ValidTimAndPin<PIN, TIM>,
+{
+    pwmb_func!();
+}
+
+impl ReducedPwmPin<PwmB> {
+    pwmb_func!();
+}
+
+//==================================================================================================
+// Embedded HAL implementation: PWMA only
+//==================================================================================================
+
+impl<Pin: TimPin, Tim: ValidTim> embedded_hal::pwm::ErrorType for PwmPin<Pin, Tim> {
+    type Error = Infallible;
+}
+
+impl embedded_hal::pwm::ErrorType for ReducedPwmPin {
+    type Error = Infallible;
+}
+
+impl embedded_hal::pwm::SetDutyCycle for ReducedPwmPin {
+    #[inline]
+    fn max_duty_cycle(&self) -> u16 {
+        DUTY_MAX
+    }
+
+    #[inline]
+    fn set_duty_cycle(&mut self, duty: u16) -> Result<(), Self::Error> {
+        self.pwm_base.current_duty = duty;
+        let pwma_val: u64 = (self.pwm_base.current_rst_val as u64
+            * (DUTY_MAX as u64 - self.pwm_base.current_duty as u64))
+            / DUTY_MAX as u64;
+        self.reg
+            .reg()
+            .pwma_value()
+            .write(|w| unsafe { w.bits(pwma_val as u32) });
+        Ok(())
+    }
+}
+
+impl<Pin: TimPin, Tim: ValidTim> embedded_hal::pwm::SetDutyCycle for PwmPin<Pin, Tim> {
+    #[inline]
+    fn max_duty_cycle(&self) -> u16 {
+        DUTY_MAX
+    }
+
+    #[inline]
+    fn set_duty_cycle(&mut self, duty: u16) -> Result<(), Self::Error> {
+        self.pwm_base.current_duty = duty;
+        let pwma_val: u64 = (self.pwm_base.current_rst_val as u64
+            * (DUTY_MAX as u64 - self.pwm_base.current_duty as u64))
+            / DUTY_MAX as u64;
+        self.reg
+            .reg()
+            .pwma_value()
+            .write(|w| unsafe { w.bits(pwma_val as u32) });
+        Ok(())
+    }
+}
+
+/// Get the corresponding u16 duty cycle from a percent value ranging between 0.0 and 1.0.
+///
+/// Please note that this might load a lot of floating point code because this processor does not
+/// have a FPU
+pub fn get_duty_from_percent(percent: f32) -> u16 {
+    if percent > 1.0 {
+        DUTY_MAX
+    } else if percent <= 0.0 {
+        0
+    } else {
+        (percent * DUTY_MAX as f32) as u16
+    }
+}

va108xx-hal/src/sysconfig.rs

@@ -0,0 +1,56 @@
+use crate::{pac, PeripheralSelect};
+
+#[derive(PartialEq, Eq, Debug)]
+pub struct InvalidounterResetVal(pub(crate) ());
+
+/// Enable scrubbing for the ROM
+///
+/// Returns [`UtilityError::InvalidCounterResetVal`] if the scrub rate is 0
+/// (equivalent to disabling) or larger than 24 bits
+pub fn enable_rom_scrubbing(
+    syscfg: &mut pac::Sysconfig,
+    scrub_rate: u32,
+) -> Result<(), InvalidounterResetVal> {
+    if scrub_rate == 0 || scrub_rate > u32::pow(2, 24) {
+        return Err(InvalidounterResetVal(()));
+    }
+    syscfg.rom_scrub().write(|w| unsafe { w.bits(scrub_rate) });
+    Ok(())
+}
+
+pub fn disable_rom_scrubbing(syscfg: &mut pac::Sysconfig) {
+    syscfg.rom_scrub().write(|w| unsafe { w.bits(0) })
+}
+
+/// Enable scrubbing for the RAM
+///
+/// Returns [`UtilityError::InvalidCounterResetVal`] if the scrub rate is 0
+/// (equivalent to disabling) or larger than 24 bits
+pub fn enable_ram_scrubbing(
+    syscfg: &mut pac::Sysconfig,
+    scrub_rate: u32,
+) -> Result<(), InvalidounterResetVal> {
+    if scrub_rate == 0 || scrub_rate > u32::pow(2, 24) {
+        return Err(InvalidounterResetVal(()));
+    }
+    syscfg.ram_scrub().write(|w| unsafe { w.bits(scrub_rate) });
+    Ok(())
+}
+
+pub fn disable_ram_scrubbing(syscfg: &mut pac::Sysconfig) {
+    syscfg.ram_scrub().write(|w| unsafe { w.bits(0) })
+}
+
+/// Clear the reset bit. This register is active low, so doing this will hold the peripheral
+/// in a reset state
+pub fn clear_reset_bit(syscfg: &mut pac::Sysconfig, periph_sel: PeripheralSelect) {
+    syscfg
+        .peripheral_reset()
+        .modify(|r, w| unsafe { w.bits(r.bits() & !(1 << periph_sel as u8)) });
+}
+
+pub fn set_reset_bit(syscfg: &mut pac::Sysconfig, periph_sel: PeripheralSelect) {
+    syscfg
+        .peripheral_reset()
+        .modify(|r, w| unsafe { w.bits(r.bits() | (1 << periph_sel as u8)) });
+}

va108xx-hal/src/time.rs

@@ -0,0 +1,26 @@
+//! Time units
+
+// Frequency based
+
+/// Hertz
+pub type Hertz = fugit::HertzU32;
+
+/// KiloHertz
+pub type KiloHertz = fugit::KilohertzU32;
+
+/// MegaHertz
+pub type MegaHertz = fugit::MegahertzU32;
+
+// Period based
+
+/// Seconds
+pub type Seconds = fugit::SecsDurationU32;
+
+/// Milliseconds
+pub type Milliseconds = fugit::MillisDurationU32;
+
+/// Microseconds
+pub type Microseconds = fugit::MicrosDurationU32;
+
+/// Nanoseconds
+pub type Nanoseconds = fugit::NanosDurationU32;

va108xx-hal/src/timer.rs

@@ -0,0 +1,790 @@
+//! API for the TIM peripherals
+//!
+//! ## Examples
+//!
+//! - [MS and second tick implementation](https://egit.irs.uni-stuttgart.de/rust/va108xx-hal/src/branch/main/examples/timer-ticks.rs)
+//! - [Cascade feature example](https://egit.irs.uni-stuttgart.de/rust/va108xx-hal/src/branch/main/examples/cascade.rs)
+pub use crate::IrqCfg;
+use crate::{
+    clock::{enable_peripheral_clock, PeripheralClocks},
+    gpio::{
+        AltFunc1, AltFunc2, AltFunc3, DynPinId, Pin, PinId, PA0, PA1, PA10, PA11, PA12, PA13, PA14,
+        PA15, PA2, PA24, PA25, PA26, PA27, PA28, PA29, PA3, PA30, PA31, PA4, PA5, PA6, PA7, PA8,
+        PA9, PB0, PB1, PB10, PB11, PB12, PB13, PB14, PB15, PB16, PB17, PB18, PB19, PB2, PB20, PB21,
+        PB22, PB23, PB3, PB4, PB5, PB6,
+    },
+    pac::{self, tim0},
+    time::Hertz,
+    timer,
+    typelevel::Sealed,
+    utility::unmask_irq,
+};
+use core::cell::Cell;
+use cortex_m::interrupt::Mutex;
+use fugit::RateExtU32;
+
+const IRQ_DST_NONE: u32 = 0xffffffff;
+pub static MS_COUNTER: Mutex<Cell<u32>> = Mutex::new(Cell::new(0));
+
+//==================================================================================================
+// Defintions
+//==================================================================================================
+
+/// Interrupt events
+pub enum Event {
+    /// Timer timed out / count down ended
+    TimeOut,
+}
+
+#[derive(Default, Debug, PartialEq, Eq, Copy, Clone)]
+pub struct CascadeCtrl {
+    /// Enable Cascade 0 signal active as a requirement for counting
+    pub enb_start_src_csd0: bool,
+    /// Invert Cascade 0, making it active low
+    pub inv_csd0: bool,
+    /// Enable Cascade 1 signal active as a requirement for counting
+    pub enb_start_src_csd1: bool,
+    /// Invert Cascade 1, making it active low
+    pub inv_csd1: bool,
+    /// Specify required operation if both Cascade 0 and Cascade 1 are active.
+    /// 0 is a logical AND of both cascade signals, 1 is a logical OR
+    pub dual_csd_op: bool,
+    /// Enable trigger mode for Cascade 0. In trigger mode, couting will start with the selected
+    /// cascade signal active, but once the counter is active, cascade control will be ignored
+    pub trg_csd0: bool,
+    /// Trigger mode, identical to [`trg_csd0`](CascadeCtrl) but for Cascade 1
+    pub trg_csd1: bool,
+    /// Enable Cascade 2 signal active as a requirement to stop counting. This mode is similar
+    /// to the REQ_STOP control bit, but signalled by a Cascade source
+    pub enb_stop_src_csd2: bool,
+    /// Invert Cascade 2, making it active low
+    pub inv_csd2: bool,
+    /// The counter is automatically disabled if the corresponding Cascade 2 level-sensitive input
+    /// souce is active when the count reaches 0. If the counter is not 0, the cascade control is
+    /// ignored
+    pub trg_csd2: bool,
+}
+
+#[derive(Debug, PartialEq, Eq)]
+pub enum CascadeSel {
+    Csd0 = 0,
+    Csd1 = 1,
+    Csd2 = 2,
+}
+
+/// The numbers are the base numbers for bundles like PORTA, PORTB or TIM
+#[derive(Debug, PartialEq, Eq)]
+pub enum CascadeSource {
+    PortABase = 0,
+    PortBBase = 32,
+    TimBase = 64,
+    RamSbe = 96,
+    RamMbe = 97,
+    RomSbe = 98,
+    RomMbe = 99,
+    Txev = 100,
+    ClockDividerBase = 120,
+}
+
+#[derive(Debug, PartialEq, Eq)]
+pub enum TimerErrors {
+    Canceled,
+    /// Invalid input for Cascade source
+    InvalidCsdSourceInput,
+}
+
+//==================================================================================================
+// Valid TIM and PIN combinations
+//==================================================================================================
+
+pub trait TimPin {
+    const DYN: DynPinId;
+}
+
+pub trait ValidTim {
+    // TIM ID ranging from 0 to 23 for 24 TIM peripherals
+    const TIM_ID: u8;
+}
+
+macro_rules! tim_marker {
+    ($TIMX:path, $ID:expr) => {
+        impl ValidTim for $TIMX {
+            const TIM_ID: u8 = $ID;
+        }
+    };
+}
+
+tim_marker!(pac::Tim0, 0);
+tim_marker!(pac::Tim1, 1);
+tim_marker!(pac::Tim2, 2);
+tim_marker!(pac::Tim3, 3);
+tim_marker!(pac::Tim4, 4);
+tim_marker!(pac::Tim5, 5);
+tim_marker!(pac::Tim6, 6);
+tim_marker!(pac::Tim7, 7);
+tim_marker!(pac::Tim8, 8);
+tim_marker!(pac::Tim9, 9);
+tim_marker!(pac::Tim10, 10);
+tim_marker!(pac::Tim11, 11);
+tim_marker!(pac::Tim12, 12);
+tim_marker!(pac::Tim13, 13);
+tim_marker!(pac::Tim14, 14);
+tim_marker!(pac::Tim15, 15);
+tim_marker!(pac::Tim16, 16);
+tim_marker!(pac::Tim17, 17);
+tim_marker!(pac::Tim18, 18);
+tim_marker!(pac::Tim19, 19);
+tim_marker!(pac::Tim20, 20);
+tim_marker!(pac::Tim21, 21);
+tim_marker!(pac::Tim22, 22);
+tim_marker!(pac::Tim23, 23);
+
+pub trait ValidTimAndPin<PIN: TimPin, TIM: ValidTim>: Sealed {}
+
+macro_rules! pin_and_tim {
+    ($PAX:ident, $ALTFUNC:ident, $ID:expr, $TIMX:path) => {
+        impl TimPin for Pin<$PAX, $ALTFUNC>
+        where
+            $PAX: PinId,
+        {
+            const DYN: DynPinId = $PAX::DYN;
+        }
+
+        impl<PIN: TimPin, TIM: ValidTim> ValidTimAndPin<PIN, TIM> for (Pin<$PAX, $ALTFUNC>, $TIMX)
+        where
+            Pin<$PAX, $ALTFUNC>: TimPin,
+            $PAX: PinId,
+        {
+        }
+
+        impl Sealed for (Pin<$PAX, $ALTFUNC>, $TIMX) {}
+    };
+}
+
+pin_and_tim!(PA31, AltFunc2, 23, pac::Tim23);
+pin_and_tim!(PA30, AltFunc2, 22, pac::Tim22);
+pin_and_tim!(PA29, AltFunc2, 21, pac::Tim21);
+pin_and_tim!(PA28, AltFunc2, 20, pac::Tim20);
+pin_and_tim!(PA27, AltFunc2, 19, pac::Tim19);
+pin_and_tim!(PA26, AltFunc2, 18, pac::Tim18);
+pin_and_tim!(PA25, AltFunc2, 17, pac::Tim17);
+pin_and_tim!(PA24, AltFunc2, 16, pac::Tim16);
+
+pin_and_tim!(PA15, AltFunc1, 15, pac::Tim15);
+pin_and_tim!(PA14, AltFunc1, 14, pac::Tim14);
+pin_and_tim!(PA13, AltFunc1, 13, pac::Tim13);
+pin_and_tim!(PA12, AltFunc1, 12, pac::Tim12);
+pin_and_tim!(PA11, AltFunc1, 11, pac::Tim11);
+pin_and_tim!(PA10, AltFunc1, 10, pac::Tim10);
+pin_and_tim!(PA9, AltFunc1, 9, pac::Tim9);
+pin_and_tim!(PA8, AltFunc1, 8, pac::Tim8);
+pin_and_tim!(PA7, AltFunc1, 7, pac::Tim7);
+pin_and_tim!(PA6, AltFunc1, 6, pac::Tim6);
+pin_and_tim!(PA5, AltFunc1, 5, pac::Tim5);
+pin_and_tim!(PA4, AltFunc1, 4, pac::Tim4);
+pin_and_tim!(PA3, AltFunc1, 3, pac::Tim3);
+pin_and_tim!(PA2, AltFunc1, 2, pac::Tim2);
+pin_and_tim!(PA1, AltFunc1, 1, pac::Tim1);
+pin_and_tim!(PA0, AltFunc1, 0, pac::Tim0);
+
+pin_and_tim!(PB23, AltFunc3, 23, pac::Tim23);
+pin_and_tim!(PB22, AltFunc3, 22, pac::Tim22);
+pin_and_tim!(PB21, AltFunc3, 21, pac::Tim21);
+pin_and_tim!(PB20, AltFunc3, 20, pac::Tim20);
+pin_and_tim!(PB19, AltFunc3, 19, pac::Tim19);
+pin_and_tim!(PB18, AltFunc3, 18, pac::Tim18);
+pin_and_tim!(PB17, AltFunc3, 17, pac::Tim17);
+pin_and_tim!(PB16, AltFunc3, 16, pac::Tim16);
+pin_and_tim!(PB15, AltFunc3, 15, pac::Tim15);
+pin_and_tim!(PB14, AltFunc3, 14, pac::Tim14);
+pin_and_tim!(PB13, AltFunc3, 13, pac::Tim13);
+pin_and_tim!(PB12, AltFunc3, 12, pac::Tim12);
+pin_and_tim!(PB11, AltFunc3, 11, pac::Tim11);
+pin_and_tim!(PB10, AltFunc3, 10, pac::Tim10);
+
+pin_and_tim!(PB6, AltFunc3, 6, pac::Tim6);
+pin_and_tim!(PB5, AltFunc3, 5, pac::Tim5);
+pin_and_tim!(PB4, AltFunc3, 4, pac::Tim4);
+pin_and_tim!(PB3, AltFunc3, 3, pac::Tim3);
+pin_and_tim!(PB2, AltFunc3, 2, pac::Tim2);
+pin_and_tim!(PB1, AltFunc3, 1, pac::Tim1);
+pin_and_tim!(PB0, AltFunc3, 0, pac::Tim0);
+
+//==================================================================================================
+// Register Interface for TIM registers and TIM pins
+//==================================================================================================
+
+pub type TimRegBlock = tim0::RegisterBlock;
+
+/// Register interface.
+///
+/// This interface provides valid TIM pins a way to access their corresponding TIM
+/// registers
+///
+/// # Safety
+///
+/// Users should only implement the [`tim_id`] function. No default function
+/// implementations should be overridden. The implementing type must also have
+/// "control" over the corresponding pin ID, i.e. it must guarantee that a each
+/// pin ID is a singleton.
+pub(super) unsafe trait TimRegInterface {
+    fn tim_id(&self) -> u8;
+
+    const PORT_BASE: *const tim0::RegisterBlock = pac::Tim0::ptr() as *const _;
+
+    /// All 24 TIM blocks are identical. This helper functions returns the correct
+    /// memory mapped peripheral depending on the TIM ID.
+    #[inline(always)]
+    fn reg(&self) -> &TimRegBlock {
+        unsafe { &*Self::PORT_BASE.offset(self.tim_id() as isize) }
+    }
+
+    #[inline(always)]
+    fn mask_32(&self) -> u32 {
+        1 << self.tim_id()
+    }
+
+    /// Clear the reset bit of the TIM, holding it in reset
+    ///
+    /// # Safety
+    ///
+    /// Only the bit related to the corresponding TIM peripheral is modified
+    #[inline]
+    #[allow(dead_code)]
+    fn clear_tim_reset_bit(&self) {
+        unsafe {
+            va108xx::Peripherals::steal()
+                .sysconfig
+                .tim_reset()
+                .modify(|r, w| w.bits(r.bits() & !self.mask_32()))
+        }
+    }
+
+    #[inline]
+    #[allow(dead_code)]
+    fn set_tim_reset_bit(&self) {
+        unsafe {
+            va108xx::Peripherals::steal()
+                .sysconfig
+                .tim_reset()
+                .modify(|r, w| w.bits(r.bits() | self.mask_32()))
+        }
+    }
+}
+
+/// Provide a safe register interface for [`ValidTimAndPin`]s
+///
+/// This `struct` takes ownership of a [`ValidTimAndPin`] and provides an API to
+/// access the corresponding registers.
+pub(super) struct TimAndPinRegister<Pin: TimPin, Tim: ValidTim> {
+    pin: Pin,
+    tim: Tim,
+}
+
+pub(super) struct TimRegister<TIM: ValidTim> {
+    tim: TIM,
+}
+
+impl<TIM: ValidTim> TimRegister<TIM> {
+    #[inline]
+    pub(super) unsafe fn new(tim: TIM) -> Self {
+        TimRegister { tim }
+    }
+
+    pub(super) fn release(self) -> TIM {
+        self.tim
+    }
+}
+
+unsafe impl<TIM: ValidTim> TimRegInterface for TimRegister<TIM> {
+    fn tim_id(&self) -> u8 {
+        TIM::TIM_ID
+    }
+}
+
+impl<PIN: TimPin, TIM: ValidTim> TimAndPinRegister<PIN, TIM>
+where
+    (PIN, TIM): ValidTimAndPin<PIN, TIM>,
+{
+    #[inline]
+    pub(super) unsafe fn new(pin: PIN, tim: TIM) -> Self {
+        TimAndPinRegister { pin, tim }
+    }
+
+    pub(super) fn release(self) -> (PIN, TIM) {
+        (self.pin, self.tim)
+    }
+}
+
+unsafe impl<PIN: TimPin, TIM: ValidTim> TimRegInterface for TimAndPinRegister<PIN, TIM> {
+    #[inline(always)]
+    fn tim_id(&self) -> u8 {
+        TIM::TIM_ID
+    }
+}
+
+pub(super) struct TimDynRegister {
+    tim_id: u8,
+    #[allow(dead_code)]
+    pin_id: DynPinId,
+}
+
+impl<PIN: TimPin, TIM: ValidTim> From<TimAndPinRegister<PIN, TIM>> for TimDynRegister {
+    fn from(_reg: TimAndPinRegister<PIN, TIM>) -> Self {
+        Self {
+            tim_id: TIM::TIM_ID,
+            pin_id: PIN::DYN,
+        }
+    }
+}
+
+unsafe impl TimRegInterface for TimDynRegister {
+    #[inline(always)]
+    fn tim_id(&self) -> u8 {
+        self.tim_id
+    }
+}
+
+//==================================================================================================
+// Timers
+//==================================================================================================
+
+/// Hardware timers
+pub struct CountDownTimer<TIM: ValidTim> {
+    tim: TimRegister<TIM>,
+    curr_freq: Hertz,
+    irq_cfg: Option<IrqCfg>,
+    sys_clk: Hertz,
+    rst_val: u32,
+    last_cnt: u32,
+    listening: bool,
+}
+
+fn enable_tim_clk(syscfg: &mut pac::Sysconfig, idx: u8) {
+    syscfg
+        .tim_clk_enable()
+        .modify(|r, w| unsafe { w.bits(r.bits() | (1 << idx)) });
+}
+
+unsafe impl<TIM: ValidTim> TimRegInterface for CountDownTimer<TIM> {
+    fn tim_id(&self) -> u8 {
+        TIM::TIM_ID
+    }
+}
+
+macro_rules! csd_sel {
+    ($func_name:ident, $csd_reg:ident) => {
+        /// Configure the Cascade sources
+        pub fn $func_name(
+            &mut self,
+            src: CascadeSource,
+            id: Option<u8>,
+        ) -> Result<(), TimerErrors> {
+            let mut id_num = 0;
+            if let CascadeSource::PortABase
+            | CascadeSource::PortBBase
+            | CascadeSource::ClockDividerBase
+            | CascadeSource::TimBase = src
+            {
+                if id.is_none() {
+                    return Err(TimerErrors::InvalidCsdSourceInput);
+                }
+            }
+            if id.is_some() {
+                id_num = id.unwrap();
+            }
+            match src {
+                CascadeSource::PortABase => {
+                    if id_num > 55 {
+                        return Err(TimerErrors::InvalidCsdSourceInput);
+                    }
+                    self.tim.reg().$csd_reg().write(|w| unsafe {
+                        w.cassel().bits(CascadeSource::PortABase as u8 + id_num)
+                    });
+                    Ok(())
+                }
+                CascadeSource::PortBBase => {
+                    if id_num > 23 {
+                        return Err(TimerErrors::InvalidCsdSourceInput);
+                    }
+                    self.tim.reg().$csd_reg().write(|w| unsafe {
+                        w.cassel().bits(CascadeSource::PortBBase as u8 + id_num)
+                    });
+                    Ok(())
+                }
+                CascadeSource::TimBase => {
+                    if id_num > 23 {
+                        return Err(TimerErrors::InvalidCsdSourceInput);
+                    }
+                    self.tim.reg().$csd_reg().write(|w| unsafe {
+                        w.cassel().bits(CascadeSource::TimBase as u8 + id_num)
+                    });
+                    Ok(())
+                }
+                CascadeSource::ClockDividerBase => {
+                    if id_num > 7 {
+                        return Err(TimerErrors::InvalidCsdSourceInput);
+                    }
+                    self.tim.reg().cascade0().write(|w| unsafe {
+                        w.cassel()
+                            .bits(CascadeSource::ClockDividerBase as u8 + id_num)
+                    });
+                    Ok(())
+                }
+                _ => {
+                    self.tim
+                        .reg()
+                        .$csd_reg()
+                        .write(|w| unsafe { w.cassel().bits(src as u8) });
+                    Ok(())
+                }
+            }
+        }
+    };
+}
+
+impl<TIM: ValidTim> CountDownTimer<TIM> {
+    /// Configures a TIM peripheral as a periodic count down timer
+    pub fn new(syscfg: &mut pac::Sysconfig, sys_clk: impl Into<Hertz>, tim: TIM) -> Self {
+        enable_tim_clk(syscfg, TIM::TIM_ID);
+        let cd_timer = CountDownTimer {
+            tim: unsafe { TimRegister::new(tim) },
+            sys_clk: sys_clk.into(),
+            irq_cfg: None,
+            rst_val: 0,
+            curr_freq: 0.Hz(),
+            listening: false,
+            last_cnt: 0,
+        };
+        cd_timer
+            .tim
+            .reg()
+            .ctrl()
+            .modify(|_, w| w.enable().set_bit());
+        cd_timer
+    }
+
+    /// Listen for events. Depending on the IRQ configuration, this also activates the IRQ in the
+    /// IRQSEL peripheral for the provided interrupt and unmasks the interrupt
+    pub fn listen(
+        &mut self,
+        event: Event,
+        irq_cfg: IrqCfg,
+        irq_sel: Option<&mut pac::Irqsel>,
+        sys_cfg: Option<&mut pac::Sysconfig>,
+    ) {
+        match event {
+            Event::TimeOut => {
+                cortex_m::peripheral::NVIC::mask(irq_cfg.irq);
+                self.irq_cfg = Some(irq_cfg);
+                if irq_cfg.route {
+                    if let Some(sys_cfg) = sys_cfg {
+                        enable_peripheral_clock(sys_cfg, PeripheralClocks::Irqsel);
+                    }
+                    if let Some(irq_sel) = irq_sel {
+                        irq_sel
+                            .tim0(TIM::TIM_ID as usize)
+                            .write(|w| unsafe { w.bits(irq_cfg.irq as u32) });
+                    }
+                }
+                self.listening = true;
+            }
+        }
+    }
+
+    pub fn unlisten(
+        &mut self,
+        event: Event,
+        syscfg: &mut pac::Sysconfig,
+        irqsel: &mut pac::Irqsel,
+    ) {
+        match event {
+            Event::TimeOut => {
+                enable_peripheral_clock(syscfg, PeripheralClocks::Irqsel);
+                irqsel
+                    .tim0(TIM::TIM_ID as usize)
+                    .write(|w| unsafe { w.bits(IRQ_DST_NONE) });
+                self.disable_interrupt();
+                self.listening = false;
+            }
+        }
+    }
+
+    #[inline(always)]
+    pub fn enable_interrupt(&mut self) {
+        self.tim.reg().ctrl().modify(|_, w| w.irq_enb().set_bit());
+    }
+
+    #[inline(always)]
+    pub fn disable_interrupt(&mut self) {
+        self.tim.reg().ctrl().modify(|_, w| w.irq_enb().clear_bit());
+    }
+
+    pub fn release(self, syscfg: &mut pac::Sysconfig) -> TIM {
+        self.tim.reg().ctrl().write(|w| w.enable().clear_bit());
+        syscfg
+            .tim_clk_enable()
+            .modify(|r, w| unsafe { w.bits(r.bits() & !(1 << TIM::TIM_ID)) });
+        self.tim.release()
+    }
+
+    /// Load the count down timer with a timeout but do not start it.
+    pub fn load(&mut self, timeout: impl Into<Hertz>) {
+        self.tim.reg().ctrl().modify(|_, w| w.enable().clear_bit());
+        self.curr_freq = timeout.into();
+        self.rst_val = self.sys_clk.raw() / self.curr_freq.raw();
+        self.set_reload(self.rst_val);
+        self.set_count(self.rst_val);
+    }
+
+    #[inline(always)]
+    pub fn set_reload(&mut self, val: u32) {
+        self.tim.reg().rst_value().write(|w| unsafe { w.bits(val) });
+    }
+
+    #[inline(always)]
+    pub fn set_count(&mut self, val: u32) {
+        self.tim.reg().cnt_value().write(|w| unsafe { w.bits(val) });
+    }
+
+    #[inline(always)]
+    pub fn count(&self) -> u32 {
+        self.tim.reg().cnt_value().read().bits()
+    }
+
+    #[inline(always)]
+    pub fn enable(&mut self) {
+        self.tim.reg().ctrl().modify(|_, w| w.enable().set_bit());
+        if let Some(irq_cfg) = self.irq_cfg {
+            self.enable_interrupt();
+            if irq_cfg.enable {
+                unmask_irq(irq_cfg.irq);
+            }
+        }
+    }
+
+    #[inline(always)]
+    pub fn disable(&mut self) {
+        self.tim.reg().ctrl().modify(|_, w| w.enable().clear_bit());
+    }
+
+    /// Disable the counter, setting both enable and active bit to 0
+    pub fn auto_disable(self, enable: bool) -> Self {
+        if enable {
+            self.tim
+                .reg()
+                .ctrl()
+                .modify(|_, w| w.auto_disable().set_bit());
+        } else {
+            self.tim
+                .reg()
+                .ctrl()
+                .modify(|_, w| w.auto_disable().clear_bit());
+        }
+        self
+    }
+
+    /// This option only applies when the Auto-Disable functionality is 0.
+    ///
+    /// The active bit is changed to 0 when count reaches 0, but the counter stays
+    /// enabled. When Auto-Disable is 1, Auto-Deactivate is implied
+    pub fn auto_deactivate(self, enable: bool) -> Self {
+        if enable {
+            self.tim
+                .reg()
+                .ctrl()
+                .modify(|_, w| w.auto_deactivate().set_bit());
+        } else {
+            self.tim
+                .reg()
+                .ctrl()
+                .modify(|_, w| w.auto_deactivate().clear_bit());
+        }
+        self
+    }
+
+    /// Configure the cascade parameters
+    pub fn cascade_control(&mut self, ctrl: CascadeCtrl) {
+        self.tim.reg().csd_ctrl().write(|w| {
+            w.csden0().bit(ctrl.enb_start_src_csd0);
+            w.csdinv0().bit(ctrl.inv_csd0);
+            w.csden1().bit(ctrl.enb_start_src_csd1);
+            w.csdinv1().bit(ctrl.inv_csd1);
+            w.dcasop().bit(ctrl.dual_csd_op);
+            w.csdtrg0().bit(ctrl.trg_csd0);
+            w.csdtrg1().bit(ctrl.trg_csd1);
+            w.csden2().bit(ctrl.enb_stop_src_csd2);
+            w.csdinv2().bit(ctrl.inv_csd2);
+            w.csdtrg2().bit(ctrl.trg_csd2)
+        });
+    }
+
+    csd_sel!(cascade_0_source, cascade0);
+    csd_sel!(cascade_1_source, cascade1);
+    csd_sel!(cascade_2_source, cascade2);
+
+    pub fn curr_freq(&self) -> Hertz {
+        self.curr_freq
+    }
+
+    pub fn listening(&self) -> bool {
+        self.listening
+    }
+}
+
+/// CountDown implementation for TIMx
+impl<TIM: ValidTim> CountDownTimer<TIM> {
+    #[inline]
+    pub fn start<T>(&mut self, timeout: T)
+    where
+        T: Into<Hertz>,
+    {
+        self.load(timeout);
+        self.enable();
+    }
+
+    /// Return `Ok` if the timer has wrapped. Peripheral will automatically clear the
+    /// flag and restart the time if configured correctly
+    pub fn wait(&mut self) -> nb::Result<(), void::Void> {
+        let cnt = self.tim.reg().cnt_value().read().bits();
+        if (cnt > self.last_cnt) || cnt == 0 {
+            self.last_cnt = self.rst_val;
+            Ok(())
+        } else {
+            self.last_cnt = cnt;
+            Err(nb::Error::WouldBlock)
+        }
+    }
+
+    pub fn cancel(&mut self) -> Result<(), TimerErrors> {
+        if !self.tim.reg().ctrl().read().enable().bit_is_set() {
+            return Err(TimerErrors::Canceled);
+        }
+        self.tim.reg().ctrl().write(|w| w.enable().clear_bit());
+        Ok(())
+    }
+}
+
+impl<TIM: ValidTim> embedded_hal::delay::DelayNs for CountDownTimer<TIM> {
+    fn delay_ns(&mut self, ns: u32) {
+        let ticks = (u64::from(ns)) * (u64::from(self.sys_clk.raw())) / 1_000_000_000;
+
+        let full_cycles = ticks >> 32;
+        let mut last_count;
+        let mut new_count;
+        if full_cycles > 0 {
+            self.set_reload(u32::MAX);
+            self.set_count(u32::MAX);
+            self.enable();
+
+            for _ in 0..full_cycles {
+                // Always ensure that both values are the same at the start.
+                new_count = self.count();
+                last_count = new_count;
+                loop {
+                    new_count = self.count();
+                    if new_count == 0 {
+                        // Wait till timer has wrapped.
+                        while self.count() == 0 {
+                            cortex_m::asm::nop()
+                        }
+                        break;
+                    }
+                    // Timer has definitely wrapped.
+                    if new_count > last_count {
+                        break;
+                    }
+                    last_count = new_count;
+                }
+            }
+        }
+        let ticks = (ticks & u32::MAX as u64) as u32;
+        self.disable();
+        if ticks > 1 {
+            self.set_reload(ticks);
+            self.set_count(ticks);
+            self.enable();
+            last_count = ticks;
+
+            loop {
+                new_count = self.count();
+                if new_count == 0 || (new_count > last_count) {
+                    break;
+                }
+                last_count = new_count;
+            }
+        }
+
+        self.disable();
+    }
+}
+
+// Set up a millisecond timer on TIM0. Please note that the user still has to provide an IRQ handler
+// which should call [default_ms_irq_handler].
+pub fn set_up_ms_tick<TIM: ValidTim>(
+    irq_cfg: IrqCfg,
+    sys_cfg: &mut pac::Sysconfig,
+    irq_sel: Option<&mut pac::Irqsel>,
+    sys_clk: impl Into<Hertz>,
+    tim0: TIM,
+) -> CountDownTimer<TIM> {
+    let mut ms_timer = CountDownTimer::new(sys_cfg, sys_clk, tim0);
+    ms_timer.listen(timer::Event::TimeOut, irq_cfg, irq_sel, Some(sys_cfg));
+    ms_timer.start(1000.Hz());
+    ms_timer
+}
+
+pub fn set_up_ms_delay_provider<TIM: ValidTim>(
+    sys_cfg: &mut pac::Sysconfig,
+    sys_clk: impl Into<Hertz>,
+    tim: TIM,
+) -> CountDownTimer<TIM> {
+    let mut provider = CountDownTimer::new(sys_cfg, sys_clk, tim);
+    provider.start(1000.Hz());
+    provider
+}
+
+/// This function can be called in a specified interrupt handler to increment
+/// the MS counter
+pub fn default_ms_irq_handler() {
+    cortex_m::interrupt::free(|cs| {
+        let mut ms = MS_COUNTER.borrow(cs).get();
+        ms += 1;
+        MS_COUNTER.borrow(cs).set(ms);
+    });
+}
+
+/// Get the current MS tick count
+pub fn get_ms_ticks() -> u32 {
+    cortex_m::interrupt::free(|cs| MS_COUNTER.borrow(cs).get())
+}
+
+//==================================================================================================
+// Delay implementations
+//==================================================================================================
+
+pub struct DelayMs(CountDownTimer<pac::Tim0>);
+
+impl DelayMs {
+    pub fn new(timer: CountDownTimer<pac::Tim0>) -> Option<Self> {
+        if timer.curr_freq() != Hertz::from_raw(1000) || !timer.listening() {
+            return None;
+        }
+        Some(Self(timer))
+    }
+}
+
+/// This assumes that the user has already set up a MS tick timer in TIM0 as a system tick
+/// with [`set_up_ms_delay_provider`]
+impl embedded_hal::delay::DelayNs for DelayMs {
+    fn delay_ns(&mut self, ns: u32) {
+        let ns_as_ms = ns / 1_000_000;
+        if self.0.curr_freq() != Hertz::from_raw(1000) || !self.0.listening() {
+            return;
+        }
+        let start_time = get_ms_ticks();
+        while get_ms_ticks() - start_time < ns_as_ms {
+            cortex_m::asm::nop();
+        }
+    }
+}

va108xx-hal/src/typelevel.rs

@@ -0,0 +1,155 @@
+//! Module supporting type-level programming
+//!
+//! This module is identical to the
+//! [atsamd typelevel](https://docs.rs/atsamd-hal/latest/atsamd_hal/typelevel/index.html).
+
+use core::ops::{Add, Sub};
+
+use typenum::{Add1, Bit, Sub1, UInt, Unsigned, B1, U0};
+
+mod private {
+    /// Super trait used to mark traits with an exhaustive set of
+    /// implementations
+    pub trait Sealed {}
+
+    impl Sealed for u8 {}
+    impl Sealed for i8 {}
+    impl Sealed for u16 {}
+    impl Sealed for i16 {}
+    impl Sealed for u32 {}
+    impl Sealed for i32 {}
+    impl Sealed for f32 {}
+
+    /// Mapping from an instance of a countable type to its successor
+    pub trait Increment {
+        /// Successor type of `Self`
+        type Inc;
+        /// Consume an instance of `Self` and return its successor
+        fn inc(self) -> Self::Inc;
+    }
+
+    /// Mapping from an instance of a countable type to its predecessor
+    pub trait Decrement {
+        /// Predecessor type of `Self`
+        type Dec;
+        /// Consume an instance of `Self` and return its predecessor
+        fn dec(self) -> Self::Dec;
+    }
+}
+
+pub(crate) use private::Decrement as PrivateDecrement;
+pub(crate) use private::Increment as PrivateIncrement;
+pub(crate) use private::Sealed;
+
+/// Type-level version of the [`None`] variant
+#[derive(Default)]
+pub struct NoneT;
+
+impl Sealed for NoneT {}
+
+//==============================================================================
+// Is
+//==============================================================================
+
+/// Marker trait for type identity
+///
+/// This trait is used as part of the [`AnyKind`] trait pattern. It represents
+/// the concept of type identity, because all implementors have
+/// `<Self as Is>::Type == Self`. When used as a trait bound with a specific
+/// type, it guarantees that the corresponding type parameter is exactly the
+/// specific type. Stated differently, it guarantees that `T == Specific` in
+/// the following example.
+///
+/// ```ignore
+/// where T: Is<Type = Specific>
+/// ```
+///
+/// Moreover, the super traits guarantee that any instance of or reference to a
+/// type `T` can be converted into the `Specific` type.
+///
+/// ```ignore
+/// fn example<T>(mut any: T)
+/// where
+///     T: Is<Type = Specific>,
+/// {
+///     let specific_mut: &mut Specific = any.as_mut();
+///     let specific_ref: &Specific = any.as_ref();
+///     let specific: Specific = any.into();
+/// }
+/// ```
+///
+/// [`AnyKind`]: #anykind-trait-pattern
+pub trait Is
+where
+    Self: Sealed,
+    Self: From<IsType<Self>>,
+    Self: Into<IsType<Self>>,
+    Self: AsRef<IsType<Self>>,
+    Self: AsMut<IsType<Self>>,
+{
+    type Type;
+}
+
+/// Type alias for [`Is::Type`]
+pub type IsType<T> = <T as Is>::Type;
+
+impl<T> Is for T
+where
+    T: Sealed + AsRef<T> + AsMut<T>,
+{
+    type Type = T;
+}
+
+//==============================================================================
+// Counting
+//==============================================================================
+
+/// Implement `Sealed` for [`U0`]
+impl Sealed for U0 {}
+
+/// Implement `Sealed` for all type-level, [`Unsigned`] integers *except* [`U0`]
+impl<U: Unsigned, B: Bit> Sealed for UInt<U, B> {}
+
+/// Trait mapping each countable type to its successor
+///
+/// This trait maps each countable type to its corresponding successor type. The
+/// actual implementation of this trait is contained within `PrivateIncrement`.
+/// Access to `PrivateIncrement` is restricted, so that safe HAL APIs can be
+/// built with it.
+pub trait Increment: PrivateIncrement {}
+
+impl<T: PrivateIncrement> Increment for T {}
+
+/// Trait mapping each countable type to its predecessor
+///
+/// This trait maps each countable type to its corresponding predecessor type.
+/// The actual implementation of this trait is contained within
+/// `PrivateDecrement`. Access to `PrivateDecrement` is restricted, so that safe
+/// HAL APIs can be built with it.
+pub trait Decrement: PrivateDecrement {}
+
+impl<T: PrivateDecrement> Decrement for T {}
+
+impl<N> PrivateIncrement for N
+where
+    N: Unsigned + Add<B1>,
+    Add1<N>: Unsigned,
+{
+    type Inc = Add1<N>;
+    #[inline]
+    fn inc(self) -> Self::Inc {
+        Self::Inc::default()
+    }
+}
+
+impl<N> PrivateDecrement for N
+where
+    N: Unsigned + Sub<B1>,
+    Sub1<N>: Unsigned,
+{
+    type Dec = Sub1<N>;
+    #[inline]
+    fn dec(self) -> Self::Dec {
+        Self::Dec::default()
+    }
+}

va108xx-hal/src/utility.rs

@@ -0,0 +1,16 @@
+//! # API for utility functions like the Error Detection and Correction (EDAC) block
+//!
+//! Some more information about the recommended scrub rates can be found on the
+//! [Vorago White Paper website](https://www.voragotech.com/resources) in the
+//! application note AN1212
+use crate::pac;
+
+/// Unmask and enable an IRQ with the given interrupt number
+///
+/// ## Safety
+///
+/// The unmask function can break mask-based critical sections
+#[inline]
+pub(crate) fn unmask_irq(irq: pac::Interrupt) {
+    unsafe { cortex_m::peripheral::NVIC::unmask(irq) };
+}