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va108xx v0.4.0: Regnerate PAC

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This commit is contained in:
Robin Müller
2025-02-09 13:26:36 +01:00
parent 698ed3a700
commit 99631dbd03
139 changed files with 619 additions and 750 deletions
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2
va108xx/src/spia/clkprescale.rs
View File

@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
}
}
impl W {}
#[doc = "Clock Pre Scale divide value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkprescale::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkprescale::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
#[doc = "Clock Pre Scale divide value\n\nYou can [`read`](crate::Reg::read) this register and get [`clkprescale::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clkprescale::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ClkprescaleSpec;
impl crate::RegisterSpec for ClkprescaleSpec {
type Ux = u32;

6
va108xx/src/spia/ctrl0.rs
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@ -43,30 +43,26 @@ impl R {
impl W {
#[doc = "Bits 0:3 - Data Size(0x3=>4, 0xf=>16)"]
#[inline(always)]
#[must_use]
pub fn size(&mut self) -> SizeW<Ctrl0Spec> {
SizeW::new(self, 0)
}
#[doc = "Bit 6 - SPI Clock Polarity"]
#[inline(always)]
#[must_use]
pub fn spo(&mut self) -> SpoW<Ctrl0Spec> {
SpoW::new(self, 6)
}
#[doc = "Bit 7 - SPI Clock Phase"]
#[inline(always)]
#[must_use]
pub fn sph(&mut self) -> SphW<Ctrl0Spec> {
SphW::new(self, 7)
}
#[doc = "Bits 8:15 - Serial Clock Rate divide+1 value"]
#[inline(always)]
#[must_use]
pub fn scrdv(&mut self) -> ScrdvW<Ctrl0Spec> {
ScrdvW::new(self, 8)
}
}
#[doc = "Control Register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
#[doc = "Control Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ctrl0Spec;
impl crate::RegisterSpec for Ctrl0Spec {
type Ux = u32;

12
va108xx/src/spia/ctrl1.rs
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@ -97,66 +97,56 @@ impl R {
impl W {
#[doc = "Bit 0 - Loop Back"]
#[inline(always)]
#[must_use]
pub fn lbm(&mut self) -> LbmW<Ctrl1Spec> {
LbmW::new(self, 0)
}
#[doc = "Bit 1 - Enable"]
#[inline(always)]
#[must_use]
pub fn enable(&mut self) -> EnableW<Ctrl1Spec> {
EnableW::new(self, 1)
}
#[doc = "Bit 2 - Master/Slave (0:Master, 1:Slave)"]
#[inline(always)]
#[must_use]
pub fn ms(&mut self) -> MsW<Ctrl1Spec> {
MsW::new(self, 2)
}
#[doc = "Bit 3 - Slave output Disable"]
#[inline(always)]
#[must_use]
pub fn sod(&mut self) -> SodW<Ctrl1Spec> {
SodW::new(self, 3)
}
#[doc = "Bits 4:6 - Slave Select"]
#[inline(always)]
#[must_use]
pub fn ss(&mut self) -> SsW<Ctrl1Spec> {
SsW::new(self, 4)
}
#[doc = "Bit 7 - Block Mode Enable"]
#[inline(always)]
#[must_use]
pub fn blockmode(&mut self) -> BlockmodeW<Ctrl1Spec> {
BlockmodeW::new(self, 7)
}
#[doc = "Bit 8 - Block Mode Start Status Enable"]
#[inline(always)]
#[must_use]
pub fn bmstart(&mut self) -> BmstartW<Ctrl1Spec> {
BmstartW::new(self, 8)
}
#[doc = "Bit 9 - Block Mode Stall Enable"]
#[inline(always)]
#[must_use]
pub fn bmstall(&mut self) -> BmstallW<Ctrl1Spec> {
BmstallW::new(self, 9)
}
#[doc = "Bit 10 - Master Delayed Capture Enable"]
#[inline(always)]
#[must_use]
pub fn mdlycap(&mut self) -> MdlycapW<Ctrl1Spec> {
MdlycapW::new(self, 10)
}
#[doc = "Bit 11 - Master Tx Pause Enable"]
#[inline(always)]
#[must_use]
pub fn mtxpause(&mut self) -> MtxpauseW<Ctrl1Spec> {
MtxpauseW::new(self, 11)
}
}
#[doc = "Control Register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
#[doc = "Control Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ctrl1Spec;
impl crate::RegisterSpec for Ctrl1Spec {
type Ux = u32;

2
va108xx/src/spia/data.rs
View File

@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
}
}
impl W {}
#[doc = "Data Input/Output\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
#[doc = "Data Input/Output\n\nYou can [`read`](crate::Reg::read) this register and get [`data::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DataSpec;
impl crate::RegisterSpec for DataSpec {
type Ux = u32;

4
va108xx/src/spia/fifo_clr.rs
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@ -7,18 +7,16 @@ pub type TxfifoW<'a, REG> = crate::BitWriter<'a, REG>;
impl W {
#[doc = "Bit 0 - Clear Rx FIFO"]
#[inline(always)]
#[must_use]
pub fn rxfifo(&mut self) -> RxfifoW<FifoClrSpec> {
RxfifoW::new(self, 0)
}
#[doc = "Bit 1 - Clear Tx FIFO"]
#[inline(always)]
#[must_use]
pub fn txfifo(&mut self) -> TxfifoW<FifoClrSpec> {
TxfifoW::new(self, 1)
}
}
#[doc = "Clear FIFO Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifo_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
#[doc = "Clear FIFO Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifo_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FifoClrSpec;
impl crate::RegisterSpec for FifoClrSpec {
type Ux = u32;

6
va108xx/src/spia/irq_enb.rs
View File

@ -43,30 +43,26 @@ impl R {
impl W {
#[doc = "Bit 0 - RX Overrun"]
#[inline(always)]
#[must_use]
pub fn rorim(&mut self) -> RorimW<IrqEnbSpec> {
RorimW::new(self, 0)
}
#[doc = "Bit 1 - RX Timeout"]
#[inline(always)]
#[must_use]
pub fn rtim(&mut self) -> RtimW<IrqEnbSpec> {
RtimW::new(self, 1)
}
#[doc = "Bit 2 - RX Fifo is at least half full"]
#[inline(always)]
#[must_use]
pub fn rxim(&mut self) -> RximW<IrqEnbSpec> {
RximW::new(self, 2)
}
#[doc = "Bit 3 - TX Fifo is at least half empty"]
#[inline(always)]
#[must_use]
pub fn txim(&mut self) -> TximW<IrqEnbSpec> {
TximW::new(self, 3)
}
}
#[doc = "Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_enb::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_enb::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
#[doc = "Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_enb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_enb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IrqEnbSpec;
impl crate::RegisterSpec for IrqEnbSpec {
type Ux = u32;

2
va108xx/src/spia/perid.rs
View File

@ -5,7 +5,7 @@ impl core::fmt::Debug for R {
write!(f, "{}", self.bits())
}
}
#[doc = "Peripheral ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`perid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
#[doc = "Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PeridSpec;
impl crate::RegisterSpec for PeridSpec {
type Ux = u32;

2
va108xx/src/spia/rxfifoirqtrg.rs
View File

@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
}
}
impl W {}
#[doc = "Rx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxfifoirqtrg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxfifoirqtrg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
#[doc = "Rx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`rxfifoirqtrg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rxfifoirqtrg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RxfifoirqtrgSpec;
impl crate::RegisterSpec for RxfifoirqtrgSpec {
type Ux = u32;

2
va108xx/src/spia/state.rs
View File

@ -5,7 +5,7 @@ impl core::fmt::Debug for R {
write!(f, "{}", self.bits())
}
}
#[doc = "Internal STATE of SPI Controller\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`state::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
#[doc = "Internal STATE of SPI Controller\n\nYou can [`read`](crate::Reg::read) this register and get [`state::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct StateSpec;
impl crate::RegisterSpec for StateSpec {
type Ux = u32;

2
va108xx/src/spia/status.rs
View File

@ -58,7 +58,7 @@ impl R {
TxtriggerR::new(((self.bits >> 7) & 1) != 0)
}
}
#[doc = "Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
#[doc = "Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct StatusSpec;
impl crate::RegisterSpec for StatusSpec {
type Ux = u32;

2
va108xx/src/spia/txfifoirqtrg.rs
View File

@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
}
}
impl W {}
#[doc = "Tx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txfifoirqtrg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txfifoirqtrg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
#[doc = "Tx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`txfifoirqtrg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`txfifoirqtrg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TxfifoirqtrgSpec;
impl crate::RegisterSpec for TxfifoirqtrgSpec {
type Ux = u32;