va108xx v0.4.0: Regnerate PAC
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@@ -43,30 +43,26 @@ impl R {
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impl W {
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#[doc = "Bits 0:3 - Data Size(0x3=>4, 0xf=>16)"]
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#[inline(always)]
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#[must_use]
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pub fn size(&mut self) -> SizeW<Ctrl0Spec> {
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SizeW::new(self, 0)
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}
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#[doc = "Bit 6 - SPI Clock Polarity"]
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#[inline(always)]
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#[must_use]
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pub fn spo(&mut self) -> SpoW<Ctrl0Spec> {
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SpoW::new(self, 6)
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}
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#[doc = "Bit 7 - SPI Clock Phase"]
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#[inline(always)]
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#[must_use]
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pub fn sph(&mut self) -> SphW<Ctrl0Spec> {
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SphW::new(self, 7)
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}
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#[doc = "Bits 8:15 - Serial Clock Rate divide+1 value"]
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#[inline(always)]
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#[must_use]
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pub fn scrdv(&mut self) -> ScrdvW<Ctrl0Spec> {
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ScrdvW::new(self, 8)
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}
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}
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#[doc = "Control Register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
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#[doc = "Control Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
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pub struct Ctrl0Spec;
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impl crate::RegisterSpec for Ctrl0Spec {
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type Ux = u32;
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