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va108xx v0.4.0: Regnerate PAC

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This commit is contained in:
Robin Müller
2025-02-09 13:26:36 +01:00
parent 698ed3a700
commit 99631dbd03
139 changed files with 619 additions and 750 deletions
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2
va108xx/src/sysconfig/ef_config.rs
View File

@ -5,7 +5,7 @@ impl core::fmt::Debug for R {
write!(f, "{}", self.bits())
}
}
#[doc = "EFuse Config Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ef_config::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
#[doc = "EFuse Config Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ef_config::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EfConfigSpec;
impl crate::RegisterSpec for EfConfigSpec {
type Ux = u32;

2
va108xx/src/sysconfig/ef_id.rs
View File

@ -5,7 +5,7 @@ impl core::fmt::Debug for R {
write!(f, "{}", self.bits())
}
}
#[doc = "EFuse ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ef_id::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
#[doc = "EFuse ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ef_id::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EfIdSpec;
impl crate::RegisterSpec for EfIdSpec {
type Ux = u32;

2
va108xx/src/sysconfig/ioconfig_clkdiv.rs
View File

@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
}
}
impl W {}
#[doc = "IO Configuration Clock Divider Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ioconfig_clkdiv::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ioconfig_clkdiv::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
#[doc = "IO Configuration Clock Divider Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ioconfig_clkdiv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ioconfig_clkdiv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IoconfigClkdivSpec;
impl crate::RegisterSpec for IoconfigClkdivSpec {
type Ux = u32;

2
va108xx/src/sysconfig/ioconfig_clkdiv0.rs
View File

@ -5,7 +5,7 @@ impl core::fmt::Debug for R {
write!(f, "{}", self.bits())
}
}
#[doc = "IO Configuration Clock Divider Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ioconfig_clkdiv0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
#[doc = "IO Configuration Clock Divider Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ioconfig_clkdiv0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IoconfigClkdiv0Spec;
impl crate::RegisterSpec for IoconfigClkdiv0Spec {
type Ux = u32;

6
va108xx/src/sysconfig/irq_enb.rs
View File

@ -43,30 +43,26 @@ impl R {
impl W {
#[doc = "Bit 0 - RAM Single Bit Interrupt"]
#[inline(always)]
#[must_use]
pub fn ramsbe(&mut self) -> RamsbeW<IrqEnbSpec> {
RamsbeW::new(self, 0)
}
#[doc = "Bit 1 - RAM Multi Bit Interrupt"]
#[inline(always)]
#[must_use]
pub fn rammbe(&mut self) -> RammbeW<IrqEnbSpec> {
RammbeW::new(self, 1)
}
#[doc = "Bit 2 - ROM Single Bit Interrupt"]
#[inline(always)]
#[must_use]
pub fn romsbe(&mut self) -> RomsbeW<IrqEnbSpec> {
RomsbeW::new(self, 2)
}
#[doc = "Bit 3 - ROM Multi Bit Interrupt"]
#[inline(always)]
#[must_use]
pub fn rommbe(&mut self) -> RommbeW<IrqEnbSpec> {
RommbeW::new(self, 3)
}
}
#[doc = "Enable EDAC Error Interrupt Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_enb::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_enb::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
#[doc = "Enable EDAC Error Interrupt Register\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_enb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_enb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IrqEnbSpec;
impl crate::RegisterSpec for IrqEnbSpec {
type Ux = u32;

3
va108xx/src/sysconfig/lockup_reset.rs
View File

@ -16,12 +16,11 @@ impl R {
impl W {
#[doc = "Bit 0 - Lockup Reset Enable Bit"]
#[inline(always)]
#[must_use]
pub fn lren(&mut self) -> LrenW<LockupResetSpec> {
LrenW::new(self, 0)
}
}
#[doc = "Lockup Reset Configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lockup_reset::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lockup_reset::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
#[doc = "Lockup Reset Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`lockup_reset::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lockup_reset::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct LockupResetSpec;
impl crate::RegisterSpec for LockupResetSpec {
type Ux = u32;

2
va108xx/src/sysconfig/perid.rs
View File

@ -5,7 +5,7 @@ impl core::fmt::Debug for R {
write!(f, "{}", self.bits())
}
}
#[doc = "Peripheral ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`perid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
#[doc = "Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PeridSpec;
impl crate::RegisterSpec for PeridSpec {
type Ux = u32;

15
va108xx/src/sysconfig/peripheral_clk_enable.rs
View File

@ -145,91 +145,78 @@ clock"]
impl W {
#[doc = "Bit 0 - Enable PORTA clock"]
#[inline(always)]
#[must_use]
pub fn porta(&mut self) -> PortaW<PeripheralClkEnableSpec> {
PortaW::new(self, 0)
}
#[doc = "Bit 1 - Enable PORTB clock"]
#[inline(always)]
#[must_use]
pub fn portb(&mut self) -> PortbW<PeripheralClkEnableSpec> {
PortbW::new(self, 1)
}
#[doc = "Bit 4 - Enable SPI\\[0\\]
clock"]
#[inline(always)]
#[must_use]
pub fn spi_0(&mut self) -> Spi0W<PeripheralClkEnableSpec> {
Spi0W::new(self, 4)
}
#[doc = "Bit 5 - Enable SPI\\[1\\]
clock"]
#[inline(always)]
#[must_use]
pub fn spi_1(&mut self) -> Spi1W<PeripheralClkEnableSpec> {
Spi1W::new(self, 5)
}
#[doc = "Bit 6 - Enable SPI\\[2\\]
clock"]
#[inline(always)]
#[must_use]
pub fn spi_2(&mut self) -> Spi2W<PeripheralClkEnableSpec> {
Spi2W::new(self, 6)
}
#[doc = "Bit 8 - Enable UART\\[0\\]
clock"]
#[inline(always)]
#[must_use]
pub fn uart_0(&mut self) -> Uart0W<PeripheralClkEnableSpec> {
Uart0W::new(self, 8)
}
#[doc = "Bit 9 - Enable UART\\[1\\]
clock"]
#[inline(always)]
#[must_use]
pub fn uart_1(&mut self) -> Uart1W<PeripheralClkEnableSpec> {
Uart1W::new(self, 9)
}
#[doc = "Bit 16 - Enable I2C\\[0\\]
clock"]
#[inline(always)]
#[must_use]
pub fn i2c_0(&mut self) -> I2c0W<PeripheralClkEnableSpec> {
I2c0W::new(self, 16)
}
#[doc = "Bit 17 - Enable I2C\\[1\\]
clock"]
#[inline(always)]
#[must_use]
pub fn i2c_1(&mut self) -> I2c1W<PeripheralClkEnableSpec> {
I2c1W::new(self, 17)
}
#[doc = "Bit 21 - Enable IRQ selector clock"]
#[inline(always)]
#[must_use]
pub fn irqsel(&mut self) -> IrqselW<PeripheralClkEnableSpec> {
IrqselW::new(self, 21)
}
#[doc = "Bit 22 - Enable IO Configuration block clock"]
#[inline(always)]
#[must_use]
pub fn ioconfig(&mut self) -> IoconfigW<PeripheralClkEnableSpec> {
IoconfigW::new(self, 22)
}
#[doc = "Bit 23 - Enable utility clock"]
#[inline(always)]
#[must_use]
pub fn utility(&mut self) -> UtilityW<PeripheralClkEnableSpec> {
UtilityW::new(self, 23)
}
#[doc = "Bit 24 - Enable GPIO clock"]
#[inline(always)]
#[must_use]
pub fn gpio(&mut self) -> GpioW<PeripheralClkEnableSpec> {
GpioW::new(self, 24)
}
}
#[doc = "Peripheral Enable Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`peripheral_clk_enable::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`peripheral_clk_enable::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
#[doc = "Peripheral Enable Control\n\nYou can [`read`](crate::Reg::read) this register and get [`peripheral_clk_enable::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`peripheral_clk_enable::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PeripheralClkEnableSpec;
impl crate::RegisterSpec for PeripheralClkEnableSpec {
type Ux = u32;

15
va108xx/src/sysconfig/peripheral_reset.rs
View File

@ -124,84 +124,71 @@ impl R {
impl W {
#[doc = "Bit 0 - Reset PORTA"]
#[inline(always)]
#[must_use]
pub fn porta(&mut self) -> PortaW<PeripheralResetSpec> {
PortaW::new(self, 0)
}
#[doc = "Bit 1 - Reset PORTB"]
#[inline(always)]
#[must_use]
pub fn portb(&mut self) -> PortbW<PeripheralResetSpec> {
PortbW::new(self, 1)
}
#[doc = "Bit 4 - Reset SPI\\[0\\]"]
#[inline(always)]
#[must_use]
pub fn spi_0(&mut self) -> Spi0W<PeripheralResetSpec> {
Spi0W::new(self, 4)
}
#[doc = "Bit 5 - Reset SPI\\[1\\]"]
#[inline(always)]
#[must_use]
pub fn spi_1(&mut self) -> Spi1W<PeripheralResetSpec> {
Spi1W::new(self, 5)
}
#[doc = "Bit 6 - Reset SPI\\[2\\]"]
#[inline(always)]
#[must_use]
pub fn spi_2(&mut self) -> Spi2W<PeripheralResetSpec> {
Spi2W::new(self, 6)
}
#[doc = "Bit 8 - Reset UART\\[0\\]"]
#[inline(always)]
#[must_use]
pub fn uart_0(&mut self) -> Uart0W<PeripheralResetSpec> {
Uart0W::new(self, 8)
}
#[doc = "Bit 9 - Reset UART\\[1\\]"]
#[inline(always)]
#[must_use]
pub fn uart_1(&mut self) -> Uart1W<PeripheralResetSpec> {
Uart1W::new(self, 9)
}
#[doc = "Bit 16 - Reset I2C\\[0\\]"]
#[inline(always)]
#[must_use]
pub fn i2c_0(&mut self) -> I2c0W<PeripheralResetSpec> {
I2c0W::new(self, 16)
}
#[doc = "Bit 17 - Reset I2C\\[1\\]"]
#[inline(always)]
#[must_use]
pub fn i2c_1(&mut self) -> I2c1W<PeripheralResetSpec> {
I2c1W::new(self, 17)
}
#[doc = "Bit 21 - Reset IRQ selector"]
#[inline(always)]
#[must_use]
pub fn irqsel(&mut self) -> IrqselW<PeripheralResetSpec> {
IrqselW::new(self, 21)
}
#[doc = "Bit 22 - Reset IO Configuration block"]
#[inline(always)]
#[must_use]
pub fn ioconfig(&mut self) -> IoconfigW<PeripheralResetSpec> {
IoconfigW::new(self, 22)
}
#[doc = "Bit 23 - Reset Utility Block"]
#[inline(always)]
#[must_use]
pub fn utility(&mut self) -> UtilityW<PeripheralResetSpec> {
UtilityW::new(self, 23)
}
#[doc = "Bit 24 - Reset GPIO"]
#[inline(always)]
#[must_use]
pub fn gpio(&mut self) -> GpioW<PeripheralResetSpec> {
GpioW::new(self, 24)
}
}
#[doc = "Peripheral Reset Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`peripheral_reset::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`peripheral_reset::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
#[doc = "Peripheral Reset Control\n\nYou can [`read`](crate::Reg::read) this register and get [`peripheral_reset::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`peripheral_reset::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PeripheralResetSpec;
impl crate::RegisterSpec for PeripheralResetSpec {
type Ux = u32;

2
va108xx/src/sysconfig/procid.rs
View File

@ -5,7 +5,7 @@ impl core::fmt::Debug for R {
write!(f, "{}", self.bits())
}
}
#[doc = "Processor ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`procid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
#[doc = "Processor ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`procid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ProcidSpec;
impl crate::RegisterSpec for ProcidSpec {
type Ux = u32;

2
va108xx/src/sysconfig/ram_sbe.rs
View File

@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
}
}
impl W {}
#[doc = "Count of RAM EDAC Single Bit Errors\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ram_sbe::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ram_sbe::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
#[doc = "Count of RAM EDAC Single Bit Errors\n\nYou can [`read`](crate::Reg::read) this register and get [`ram_sbe::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ram_sbe::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RamSbeSpec;
impl crate::RegisterSpec for RamSbeSpec {
type Ux = u32;

2
va108xx/src/sysconfig/refresh_config.rs
View File

@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
}
}
impl W {}
#[doc = "Register Refresh Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`refresh_config::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`refresh_config::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
#[doc = "Register Refresh Control\n\nYou can [`read`](crate::Reg::read) this register and get [`refresh_config::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`refresh_config::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RefreshConfigSpec;
impl crate::RegisterSpec for RefreshConfigSpec {
type Ux = u32;

3
va108xx/src/sysconfig/rom_prot.rs
View File

@ -16,12 +16,11 @@ impl R {
impl W {
#[doc = "Bit 0 - ROM Write Enable Bit"]
#[inline(always)]
#[must_use]
pub fn wren(&mut self) -> WrenW<RomProtSpec> {
WrenW::new(self, 0)
}
}
#[doc = "ROM Protection Configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rom_prot::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rom_prot::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
#[doc = "ROM Protection Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`rom_prot::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rom_prot::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RomProtSpec;
impl crate::RegisterSpec for RomProtSpec {
type Ux = u32;

2
va108xx/src/sysconfig/rom_retries.rs
View File

@ -5,7 +5,7 @@ impl core::fmt::Debug for R {
write!(f, "{}", self.bits())
}
}
#[doc = "ROM BOOT Retry count\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rom_retries::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
#[doc = "ROM BOOT Retry count\n\nYou can [`read`](crate::Reg::read) this register and get [`rom_retries::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RomRetriesSpec;
impl crate::RegisterSpec for RomRetriesSpec {
type Ux = u32;

4
va108xx/src/sysconfig/rom_scrub.rs
View File

@ -18,18 +18,16 @@ impl R {
impl W {
#[doc = "Bits 0:23 - Counter divide value"]
#[inline(always)]
#[must_use]
pub fn value(&mut self) -> ValueW<RomScrubSpec> {
ValueW::new(self, 0)
}
#[doc = "Bit 31 - Reset Counter"]
#[inline(always)]
#[must_use]
pub fn reset(&mut self) -> ResetW<RomScrubSpec> {
ResetW::new(self, 31)
}
}
#[doc = "ROM Scrub Period Configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rom_scrub::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rom_scrub::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
#[doc = "ROM Scrub Period Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`rom_scrub::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rom_scrub::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RomScrubSpec;
impl crate::RegisterSpec for RomScrubSpec {
type Ux = u32;

4
va108xx/src/sysconfig/rom_trap_addr.rs
View File

@ -25,18 +25,16 @@ impl R {
impl W {
#[doc = "Bits 2:15 - Trap Address Match Bits"]
#[inline(always)]
#[must_use]
pub fn addr(&mut self) -> AddrW<RomTrapAddrSpec> {
AddrW::new(self, 2)
}
#[doc = "Bit 31 - Trap Enable Bit"]
#[inline(always)]
#[must_use]
pub fn enable(&mut self) -> EnableW<RomTrapAddrSpec> {
EnableW::new(self, 31)
}
}
#[doc = "ROM Trap Address\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rom_trap_addr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rom_trap_addr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
#[doc = "ROM Trap Address\n\nYou can [`read`](crate::Reg::read) this register and get [`rom_trap_addr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rom_trap_addr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RomTrapAddrSpec;
impl crate::RegisterSpec for RomTrapAddrSpec {
type Ux = u32;

3
va108xx/src/sysconfig/rom_trap_synd.rs
View File

@ -16,12 +16,11 @@ impl R {
impl W {
#[doc = "Bits 0:19 - Trap Syndrom Bits"]
#[inline(always)]
#[must_use]
pub fn synd(&mut self) -> SyndW<RomTrapSyndSpec> {
SyndW::new(self, 0)
}
}
#[doc = "ROM Trap Syndrome\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rom_trap_synd::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rom_trap_synd::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
#[doc = "ROM Trap Syndrome\n\nYou can [`read`](crate::Reg::read) this register and get [`rom_trap_synd::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rom_trap_synd::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RomTrapSyndSpec;
impl crate::RegisterSpec for RomTrapSyndSpec {
type Ux = u32;

8
va108xx/src/sysconfig/rst_stat.rs
View File

@ -61,42 +61,36 @@ impl R {
impl W {
#[doc = "Bit 0 - Power On Reset Status"]
#[inline(always)]
#[must_use]
pub fn por(&mut self) -> PorW<RstStatSpec> {
PorW::new(self, 0)
}
#[doc = "Bit 1 - External Reset Status"]
#[inline(always)]
#[must_use]
pub fn extrst(&mut self) -> ExtrstW<RstStatSpec> {
ExtrstW::new(self, 1)
}
#[doc = "Bit 2 - SYSRESETREQ Reset Status"]
#[inline(always)]
#[must_use]
pub fn sysrstreq(&mut self) -> SysrstreqW<RstStatSpec> {
SysrstreqW::new(self, 2)
}
#[doc = "Bit 3 - LOOKUP Reset Status"]
#[inline(always)]
#[must_use]
pub fn lookup(&mut self) -> LookupW<RstStatSpec> {
LookupW::new(self, 3)
}
#[doc = "Bit 4 - WATCHDOG Reset Status"]
#[inline(always)]
#[must_use]
pub fn watchdog(&mut self) -> WatchdogW<RstStatSpec> {
WatchdogW::new(self, 4)
}
#[doc = "Bit 5 - Memory Error Reset Status"]
#[inline(always)]
#[must_use]
pub fn memerr(&mut self) -> MemerrW<RstStatSpec> {
MemerrW::new(self, 5)
}
}
#[doc = "System Reset Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rst_stat::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rst_stat::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
#[doc = "System Reset Status\n\nYou can [`read`](crate::Reg::read) this register and get [`rst_stat::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rst_stat::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RstStatSpec;
impl crate::RegisterSpec for RstStatSpec {
type Ux = u32;

2
va108xx/src/sysconfig/tim_clk_enable.rs
View File

@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
}
}
impl W {}
#[doc = "TIM Enable Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tim_clk_enable::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tim_clk_enable::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
#[doc = "TIM Enable Control\n\nYou can [`read`](crate::Reg::read) this register and get [`tim_clk_enable::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tim_clk_enable::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TimClkEnableSpec;
impl crate::RegisterSpec for TimClkEnableSpec {
type Ux = u32;

2
va108xx/src/sysconfig/tim_reset.rs
View File

@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
}
}
impl W {}
#[doc = "TIM Reset Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tim_reset::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tim_reset::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
#[doc = "TIM Reset Control\n\nYou can [`read`](crate::Reg::read) this register and get [`tim_reset::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tim_reset::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TimResetSpec;
impl crate::RegisterSpec for TimResetSpec {
type Ux = u32;