rust/va108xx-rs
7
0
Fork 0
Code Issues Pull Requests Projects Releases 19 Wiki Activity

update package
All checks were successful
Rust/va108xx-rs/pipeline/pr-main This commit looks good
Details

Browse Source 
- Add embassy example
- improve timer API
- restructure examples
- restructure and improve SPI
- Add REB1 M95M01 NVM module
This commit is contained in:
Robin Müller
2024-09-18 15:07:29 +02:00
parent 405cc089c3
commit acb8b67ae7
40 changed files with 2197 additions and 673 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
vorago-reb1/CHANGELOG.md
View File

@ -8,6 +8,8 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
## [unreleased]
- Added M95M01 EEPROM module/API
## [v0.5.1] 2024-07-04
- Update `va108xx-hal` dependency to v0.7.0

23
vorago-reb1/Cargo.toml
View File

@ -14,12 +14,15 @@ categories = ["aerospace", "embedded", "no-std", "hardware-support"]
cortex-m = { version = "0.7", features = ["critical-section-single-core"] }
cortex-m-rt = "0.7"
embedded-hal = "1"
nb = "1"
bitfield = "0.17"
[dependencies.max116xx-10bit]
version = "0.3"
[dependencies.va108xx-hal]
version = "0.7"
version = ">=0.7, <0.8"
path = "../va108xx-hal"
features = ["rt"]
[features]
@ -28,20 +31,10 @@ rt = ["va108xx-hal/rt"]
[dev-dependencies]
panic-halt = "0.2"
nb = "1"
[dev-dependencies.rtt-target]
version = "0.5"
[dev-dependencies.panic-rtt-target]
version = "0.1"
[dev-dependencies.rtic]
version = "2"
features = ["thumbv6-backend"]
[dev-dependencies.rtic-monotonics]
version = "1"
features = ["cortex-m-systick"]
rtt-target = "0.5"
panic-rtt-target = "0.1"
embedded-hal-bus = "0.2"
dummy-pin = "1"
[package.metadata.docs.rs]
all-features = true

21
vorago-reb1/examples/adxl343-accelerometer.rs
View File

@ -5,15 +5,16 @@
#![no_main]
#![no_std]
use cortex_m_rt::entry;
use embedded_hal::spi::SpiBus;
use embedded_hal::spi::{SpiBus, MODE_3};
use embedded_hal::{delay::DelayNs, digital::OutputPin};
use panic_rtt_target as _;
use rtt_target::{rprintln, rtt_init_print};
use va108xx_hal::spi::SpiClkConfig;
use va108xx_hal::{
gpio::PinsA,
pac,
prelude::*,
spi::{Spi, SpiConfig, TransferConfig},
spi::{Spi, SpiConfig},
timer::set_up_ms_delay_provider,
};
@ -31,7 +32,6 @@ fn main() -> ! {
let mut dp = pac::Peripherals::take().unwrap();
let mut delay = set_up_ms_delay_provider(&mut dp.sysconfig, 50.MHz(), dp.tim0);
let pinsa = PinsA::new(&mut dp.sysconfig, None, dp.porta);
let spi_cfg = SpiConfig::default();
let (sck, mosi, miso) = (
pinsa.pa20.into_funsel_2(),
pinsa.pa19.into_funsel_2(),
@ -45,21 +45,20 @@ fn main() -> ! {
.set_high()
.expect("Setting ADC chip select high failed");
let transfer_cfg = TransferConfig::new(
1.MHz(),
embedded_hal::spi::MODE_3,
Some(cs_pin),
false,
true,
);
let spi_cfg = SpiConfig::default()
.clk_cfg(
SpiClkConfig::from_clk(50.MHz(), 1.MHz()).expect("creating SPI clock config failed"),
)
.mode(MODE_3)
.slave_output_disable(true);
let mut spi = Spi::new(
&mut dp.sysconfig,
50.MHz(),
dp.spib,
(sck, miso, mosi),
spi_cfg,
Some(&transfer_cfg.downgrade()),
);
spi.cfg_hw_cs_with_pin(&cs_pin);
let mut tx_rx_buf: [u8; 3] = [0; 3];
tx_rx_buf[0] = READ_MASK | DEVID_REG;

153
vorago-reb1/examples/blinky-button-rtic.rs
View File

@ -1,153 +0,0 @@
//! Blinky button application for the REB1 board using RTIC
#![no_main]
#![no_std]
#[rtic::app(device = pac)]
mod app {
use panic_rtt_target as _;
use rtic_monotonics::systick::Systick;
use rtt_target::{rprintln, rtt_init_default, set_print_channel};
use va108xx_hal::{
clock::{set_clk_div_register, FilterClkSel},
gpio::{FilterType, InterruptEdge, PinsA},
pac,
prelude::*,
timer::{default_ms_irq_handler, set_up_ms_tick, IrqCfg},
};
use vorago_reb1::button::Button;
use vorago_reb1::leds::Leds;
#[derive(Debug, PartialEq)]
pub enum PressMode {
Toggle,
Keep,
}
#[derive(Debug, PartialEq)]
pub enum CfgMode {
Prompt,
Fixed,
}
const CFG_MODE: CfgMode = CfgMode::Fixed;
// You can change the press mode here
const DEFAULT_MODE: PressMode = PressMode::Toggle;
#[local]
struct Local {
leds: Leds,
button: Button,
mode: PressMode,
}
#[shared]
struct Shared {}
#[init]
fn init(ctx: init::Context) -> (Shared, Local) {
let channels = rtt_init_default!();
set_print_channel(channels.up.0);
rprintln!("-- Vorago Button IRQ Example --");
// Initialize the systick interrupt & obtain the token to prove that we did
let systick_mono_token = rtic_monotonics::create_systick_token!();
Systick::start(
ctx.core.SYST,
Hertz::from(50.MHz()).raw(),
systick_mono_token,
);
let mode = match CFG_MODE {
// Ask mode from user via RTT
CfgMode::Prompt => prompt_mode(channels.down.0),
// Use mode hardcoded in `DEFAULT_MODE`
CfgMode::Fixed => DEFAULT_MODE,
};
rprintln!("Using {:?} mode", mode);
let mut dp = ctx.device;
let pinsa = PinsA::new(&mut dp.sysconfig, Some(dp.ioconfig), dp.porta);
let edge_irq = match mode {
PressMode::Toggle => InterruptEdge::HighToLow,
PressMode::Keep => InterruptEdge::BothEdges,
};
// Configure an edge interrupt on the button and route it to interrupt vector 15
let mut button = Button::new(pinsa.pa11.into_floating_input()).edge_irq(
edge_irq,
IrqCfg::new(pac::interrupt::OC15, true, true),
Some(&mut dp.sysconfig),
Some(&mut dp.irqsel),
);
if mode == PressMode::Toggle {
// This filter debounces the switch for edge based interrupts
button = button.filter_type(FilterType::FilterFourClockCycles, FilterClkSel::Clk1);
set_clk_div_register(&mut dp.sysconfig, FilterClkSel::Clk1, 50_000);
}
let mut leds = Leds::new(
pinsa.pa10.into_push_pull_output(),
pinsa.pa7.into_push_pull_output(),
pinsa.pa6.into_push_pull_output(),
);
for led in leds.iter_mut() {
led.off();
}
set_up_ms_tick(
IrqCfg::new(pac::Interrupt::OC0, true, true),
&mut dp.sysconfig,
Some(&mut dp.irqsel),
50.MHz(),
dp.tim0,
);
(Shared {}, Local { leds, button, mode })
}
// `shared` cannot be accessed from this context
#[idle]
fn idle(_cx: idle::Context) -> ! {
loop {
cortex_m::asm::nop();
}
}
#[task(binds = OC15, local=[button, leds, mode])]
fn button_task(cx: button_task::Context) {
let leds = cx.local.leds;
let button = cx.local.button;
let mode = cx.local.mode;
if *mode == PressMode::Toggle {
leds[0].toggle();
} else {
if button.released() {
leds[0].off();
} else {
leds[0].on();
}
}
}
#[task(binds = OC0)]
fn ms_tick(_cx: ms_tick::Context) {
default_ms_irq_handler();
}
fn prompt_mode(mut down_channel: rtt_target::DownChannel) -> PressMode {
rprintln!("Using prompt mode");
rprintln!("Please enter the mode [0: Toggle, 1: Keep]");
let mut read_buf: [u8; 16] = [0; 16];
let mut read;
loop {
read = down_channel.read(&mut read_buf);
for i in 0..read {
let val = read_buf[i] as char;
if val == '0' || val == '1' {
return if val == '0' {
PressMode::Toggle
} else {
PressMode::Keep
};
}
}
}
}
}

17
vorago-reb1/examples/max11619-adc.rs
View File

@ -9,19 +9,19 @@ use core::convert::Infallible;
use cortex_m_rt::entry;
use embedded_hal::digital::OutputPin;
use embedded_hal::spi::{SpiBus, SpiDevice};
use embedded_hal::spi::{SpiBus, SpiDevice, MODE_0};
use embedded_hal::{delay::DelayNs, spi};
use max116xx_10bit::VoltageRefMode;
use max116xx_10bit::{AveragingConversions, AveragingResults};
use panic_rtt_target as _;
use rtt_target::{rprintln, rtt_init_print};
use va108xx_hal::spi::{NoneT, OptionalHwCs};
use va108xx_hal::spi::{OptionalHwCs, SpiClkConfig};
use va108xx_hal::timer::CountDownTimer;
use va108xx_hal::{
gpio::PinsA,
pac::{self, interrupt},
prelude::*,
spi::{Spi, SpiBase, SpiConfig, TransferConfig},
spi::{Spi, SpiBase, SpiConfig},
timer::{default_ms_irq_handler, set_up_ms_tick, DelayMs, IrqCfg},
};
use va108xx_hal::{port_mux, FunSel, PortSel};
@ -103,6 +103,8 @@ impl<Delay: DelayNs, HwCs: OptionalHwCs<pac::Spib>> SpiDevice for SpiWithHwCs<De
}
}
const SYS_CLK: Hertz = Hertz::from_raw(50_000_000);
#[entry]
fn main() -> ! {
rtt_init_print!();
@ -113,7 +115,7 @@ fn main() -> ! {
IrqCfg::new(pac::Interrupt::OC0, true, true),
&mut dp.sysconfig,
Some(&mut dp.irqsel),
50.MHz(),
SYS_CLK,
dp.tim0,
);
let delay = DelayMs::new(tim0).unwrap();
@ -122,7 +124,10 @@ fn main() -> ! {
}
let pinsa = PinsA::new(&mut dp.sysconfig, None, dp.porta);
let spi_cfg = SpiConfig::default();
let spi_cfg = SpiConfig::default()
.clk_cfg(SpiClkConfig::from_clk(SYS_CLK, 3.MHz()).unwrap())
.mode(MODE_0)
.blockmode(true);
let (sck, mosi, miso) = (
pinsa.pa20.into_funsel_2(),
pinsa.pa19.into_funsel_2(),
@ -141,14 +146,12 @@ fn main() -> ! {
.set_high()
.expect("Setting accelerometer chip select high failed");
let transfer_cfg = TransferConfig::<NoneT>::new(3.MHz(), spi::MODE_0, None, true, false);
let spi = Spi::new(
&mut dp.sysconfig,
50.MHz(),
dp.spib,
(sck, miso, mosi),
spi_cfg,
Some(&transfer_cfg.downgrade()),
)
.downgrade();
let delay_provider = CountDownTimer::new(&mut dp.sysconfig, 50.MHz(), dp.tim1);

64
vorago-reb1/examples/nvm.rs Normal file
View File

@ -0,0 +1,64 @@
//! Example application which interfaces with the boot EEPROM.
#![no_main]
#![no_std]
use cortex_m_rt::entry;
use embedded_hal::delay::DelayNs;
use panic_rtt_target as _;
use rtt_target::{rprintln, rtt_init_print};
use va108xx_hal::{pac, pwm::CountDownTimer, time::Hertz};
use vorago_reb1::m95m01::M95M01;
const CLOCK_FREQ: Hertz = Hertz::from_raw(50_000_000);
#[entry]
fn main() -> ! {
rtt_init_print!();
rprintln!("-- VA108XX REB1 NVM example --");
let mut dp = pac::Peripherals::take().unwrap();
let mut timer = CountDownTimer::new(&mut dp.sysconfig, CLOCK_FREQ, dp.tim0);
let mut nvm = M95M01::new(&mut dp.sysconfig, CLOCK_FREQ, dp.spic);
let status_reg = nvm.read_status_reg().expect("reading status reg failed");
if status_reg.zero_segment() == 0b111 {
panic!("status register unexpected values");
}
let mut orig_content: [u8; 16] = [0; 16];
let mut read_buf: [u8; 16] = [0; 16];
let write_buf: [u8; 16] = [0; 16];
for (idx, val) in read_buf.iter_mut().enumerate() {
*val = idx as u8;
}
nvm.read(0x4000, &mut orig_content).unwrap();
// One byte write and read.
nvm.write(0x4000, &write_buf[0..1]).unwrap();
nvm.read(0x4000, &mut read_buf[0..1]).unwrap();
assert_eq!(write_buf[0], read_buf[0]);
read_buf.fill(0);
// Four bytes write and read.
nvm.write(0x4000, &write_buf[0..4]).unwrap();
nvm.read(0x4000, &mut read_buf[0..4]).unwrap();
assert_eq!(&read_buf[0..4], &write_buf[0..4]);
read_buf.fill(0);
// Full sixteen bytes
nvm.write(0x4000, &write_buf).unwrap();
nvm.read(0x4000, &mut read_buf).unwrap();
assert_eq!(&read_buf, &write_buf);
read_buf.fill(0);
// 3 bytes
nvm.write(0x4000, &write_buf[0..3]).unwrap();
nvm.read(0x4000, &mut read_buf[0..3]).unwrap();
assert_eq!(&read_buf[0..3], &write_buf[0..3]);
// Write back original content.
nvm.write(0x4000, &orig_content).unwrap();
loop {
timer.delay_ms(500);
}
}

1
vorago-reb1/src/lib.rs
View File

@ -3,5 +3,6 @@
pub mod button;
pub mod leds;
pub mod m95m01;
pub mod max11619;
pub mod temp_sensor;

172
vorago-reb1/src/m95m01.rs Normal file
View File

@ -0,0 +1,172 @@
//! Basic driver for the ST M95M01 EEPROM memory.
//!
//! This driver is used by the provided bootloader application for the REB1
//! board. It provides a convenient wrapper around the HAL SPI to interface
//! with the EEPROM memory of the REB1 board.
//!
//! # Example
//!
//! - [REB1 EEPROM example](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/vorago-reb1/examples/nvm.rs)
use core::convert::Infallible;
use embedded_hal::spi::SpiBus;
bitfield::bitfield! {
pub struct StatusReg(u8);
impl Debug;
u8;
pub status_register_write_protect, _: 7;
pub zero_segment, _: 6, 4;
pub block_protection_bits, set_block_protection_bits: 3, 2;
pub write_enable_latch, _: 1;
pub write_in_progress, _: 0;
}
// Registers.
pub mod regs {
/// Write status register command.
pub const WRSR: u8 = 0x01;
// Write command.
pub const WRITE: u8 = 0x02;
// Read command.
pub const READ: u8 = 0x03;
/// Write disable command.
pub const WRDI: u8 = 0x04;
/// Read status register command.
pub const RDSR: u8 = 0x05;
/// Write enable command.
pub const WREN: u8 = 0x06;
}
use regs::*;
use va108xx_hal::{
pac,
prelude::*,
spi::{RomMiso, RomMosi, RomSck, Spi, SpiConfig, BMSTART_BMSTOP_MASK},
};
pub type RomSpi = Spi<pac::Spic, (RomSck, RomMiso, RomMosi), u8>;
/// Driver for the ST device M95M01 EEPROM memory.
///
/// Specialized for the requirements of the VA108XX MCUs.
pub struct M95M01 {
pub spi: RomSpi,
}
impl M95M01 {
pub fn new(syscfg: &mut pac::Sysconfig, sys_clk: impl Into<Hertz>, spi: pac::Spic) -> Self {
let spi = RomSpi::new(
syscfg,
sys_clk,
spi,
(RomSck, RomMiso, RomMosi),
SpiConfig::default(),
);
let mut spi_dev = Self { spi };
spi_dev.clear_block_protection().unwrap();
spi_dev
}
pub fn release(mut self) -> pac::Spic {
self.set_block_protection().unwrap();
self.spi.release().0
}
// Wait until the write-in-progress state is cleared. This exposes a [nb] API, so this function
// will return [nb::Error::WouldBlock] if the EEPROM is still busy.
pub fn writes_are_done(&mut self) -> nb::Result<(), Infallible> {
let rdsr = self.read_status_reg()?;
if rdsr.write_in_progress() {
return Err(nb::Error::WouldBlock);
}
Ok(())
}
pub fn read_status_reg(&mut self) -> Result<StatusReg, Infallible> {
let mut write_read: [u8; 2] = [regs::RDSR, 0x00];
self.spi.transfer_in_place(&mut write_read)?;
Ok(StatusReg(write_read[1]))
}
pub fn write_enable(&mut self) -> Result<(), Infallible> {
self.spi.write(&[regs::WREN])
}
pub fn clear_block_protection(&mut self) -> Result<(), Infallible> {
// Has to be written separately.
self.write_enable()?;
self.spi.write(&[WRSR, 0x00])
}
pub fn set_block_protection(&mut self) -> Result<(), Infallible> {
let mut reg = StatusReg(0);
reg.set_block_protection_bits(0b11);
self.write_enable()?;
self.spi.write(&[WRSR, reg.0])
}
fn common_init_write_and_read(&mut self, address: u32, reg: u8) -> Result<(), Infallible> {
nb::block!(self.writes_are_done())?;
self.spi.flush()?;
if reg == WRITE {
self.write_enable()?;
self.spi.write_fifo_unchecked(WRITE as u32);
} else {
self.spi.write_fifo_unchecked(READ as u32);
}
self.spi.write_fifo_unchecked((address >> 16) & 0xff);
self.spi.write_fifo_unchecked((address >> 8) & 0xff);
self.spi.write_fifo_unchecked(address & 0xff);
Ok(())
}
fn common_read(&mut self, address: u32) -> Result<(), Infallible> {
self.common_init_write_and_read(address, READ)?;
for _ in 0..4 {
// Pump the FIFO.
self.spi.write_fifo_unchecked(0);
// Ignore the first 4 bytes.
self.spi.read_fifo_unchecked();
}
Ok(())
}
pub fn write(&mut self, address: u32, data: &[u8]) -> Result<(), Infallible> {
self.common_init_write_and_read(address, WRITE)?;
for val in data.iter().take(data.len() - 1) {
nb::block!(self.spi.write_fifo(*val as u32))?;
self.spi.read_fifo_unchecked();
}
nb::block!(self
.spi
.write_fifo(*data.last().unwrap() as u32 | BMSTART_BMSTOP_MASK))?;
self.spi.flush()?;
nb::block!(self.writes_are_done())?;
Ok(())
}
pub fn read(&mut self, address: u32, buf: &mut [u8]) -> Result<(), Infallible> {
self.common_read(address)?;
for val in buf.iter_mut() {
nb::block!(self.spi.write_fifo(0))?;
*val = (nb::block!(self.spi.read_fifo()).unwrap() & 0xff) as u8;
}
nb::block!(self.spi.write_fifo(BMSTART_BMSTOP_MASK))?;
self.spi.flush()?;
Ok(())
}
pub fn verify(&mut self, address: u32, data: &[u8]) -> Result<bool, Infallible> {
self.common_read(address)?;
for val in data.iter() {
nb::block!(self.spi.write_fifo(0))?;
let read_val = (nb::block!(self.spi.read_fifo()).unwrap() & 0xff) as u8;
if read_val != *val {
return Ok(false);
}
}
nb::block!(self.spi.write_fifo(BMSTART_BMSTOP_MASK))?;
self.spi.flush()?;
Ok(true)
}
}

2
vorago-reb1/src/temp_sensor.rs
View File

@ -4,7 +4,7 @@
//!
//! ## Examples
//!
//! - [Temperature Sensor example](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/vorago-reb1/examples/adt75-temp-sensor.rs
//! - [Temperature Sensor example](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/vorago-reb1/examples/adt75-temp-sensor.rs)
use embedded_hal::i2c::{I2c, SevenBitAddress};
use va108xx_hal::{
i2c::{Error, I2cMaster, I2cSpeed, InitError, MasterConfig},