diff --git a/va108xx-hal/src/gpio/reg.rs b/va108xx-hal/src/gpio/reg.rs
index 41cc834..0b94068 100644
--- a/va108xx-hal/src/gpio/reg.rs
+++ b/va108xx-hal/src/gpio/reg.rs
@@ -320,13 +320,6 @@ pub(super) unsafe trait RegisterInterface {
         }
     }
 
-    /// Persistent bit which specifies whether an edge was detected. Reading will clear the bit.
-    #[inline(always)]
-    fn edge_has_occurred(&mut self) -> bool {
-        let portreg = self.port_reg();
-        ((portreg.edge_status().read().bits() >> self.id().num) & 0x01) == 1
-    }
-
     /// Only useful for output pins
     /// See p.52 of the programmers guide for more information.
     /// When configured for pulse mode, a given pin will set the non-default state for exactly