rust/va108xx-rs
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bump HAL and PAC

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This commit is contained in:
Robin Mueller
2025-09-03 10:30:39 +02:00
parent 07d8bc7952
commit c5a43356cc
35 changed files with 110 additions and 81 deletions
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va108xx-hal/CHANGELOG.md
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@@ -8,9 +8,11 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
## [unreleased]
## [v0.12.0] 2025-09-03
## Changed
- Move most library components to new [`vorago-shared-periphs`](https://egit.irs.uni-stuttgart.de/rust/vorago-shared-periphs)
- Move most library components to new [`vorago-shared-hal`](https://egit.irs.uni-stuttgart.de/rust/vorago-shared-hal)
which is mostly re-exported in this crate.
- Overhaul and simplification of several HAL APIs. The system configuration and IRQ router
peripheral instance generally does not need to be passed to HAL API anymore.
@@ -274,7 +276,8 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
- Added basic test binary in form of an example
- README with basic instructions how to set up own binary crate
[unreleased]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/compare/va108xx-hal-v0.11.0...HEAD
[unreleased]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/compare/va108xx-hal-v0.12.0...HEAD
[v0.12.0]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/compare/va108xx-hal-v0.11.1...va108xx-hal-v0.12.0
[v0.11.1]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/compare/va108xx-hal-v0.11.0...va108xx-hal-v0.11.1
[v0.11.0]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/compare/va108xx-hal-v0.10.0...va108xx-hal-v0.11.0
[v0.10.0]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/compare/va108xx-hal-v0.9.0...va108xx-hal-v0.10.0
va108xx-hal/Cargo.toml
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@@ -1,6 +1,6 @@
[package]
name = "va108xx-hal"
version = "0.11.1"
version = "0.12.0"
authors = ["Robin Mueller <muellerr@irs.uni-stuttgart.de>"]
edition = "2021"
description = "HAL for the Vorago VA108xx family of microcontrollers"
@@ -12,10 +12,10 @@ categories = ["aerospace", "embedded", "no-std", "hardware-support"]
[dependencies]
cortex-m = { version = "0.7", features = ["critical-section-single-core"]}
vorago-shared-periphs = { git = "https://egit.irs.uni-stuttgart.de/rust/vorago-shared-periphs.git", features = ["vor1x"] }
vorago-shared-hal = { version = "0.2", features = ["vor1x"] }
fugit = "0.3"
thiserror = { version = "2", default-features = false }
va108xx = { version = "0.5", default-features = false, features = ["critical-section", "defmt"] }
va108xx = { version = "0.6", default-features = false, features = ["critical-section", "defmt"] }
defmt = { version = "1", optional = true }
[target.'cfg(all(target_arch = "arm", target_os = "none"))'.dependencies]
@@ -26,7 +26,7 @@ portable-atomic = "1"
[features]
default = ["rt"]
rt = ["va108xx/rt"]
defmt = ["dep:defmt", "vorago-shared-periphs/defmt"]
defmt = ["dep:defmt", "vorago-shared-hal/defmt"]
[package.metadata.docs.rs]
all-features = true
va108xx-hal/src/clock.rs
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@@ -1,31 +1,31 @@
//! # API for clock related functionality
//!
//! This also includes functionality to enable the peripheral clocks
pub use vorago_shared_periphs::gpio::FilterClkSel;
pub use vorago_shared_periphs::sysconfig::{disable_peripheral_clock, enable_peripheral_clock};
pub use vorago_shared_hal::gpio::FilterClockSelect;
pub use vorago_shared_hal::sysconfig::{disable_peripheral_clock, enable_peripheral_clock};
pub fn set_clk_div_register(syscfg: &mut va108xx::Sysconfig, clk_sel: FilterClkSel, div: u32) {
pub fn set_clk_div_register(syscfg: &mut va108xx::Sysconfig, clk_sel: FilterClockSelect, div: u32) {
match clk_sel {
FilterClkSel::SysClk => (),
FilterClkSel::Clk1 => {
FilterClockSelect::SysClk => (),
FilterClockSelect::Clk1 => {
syscfg.ioconfig_clkdiv1().write(|w| unsafe { w.bits(div) });
}
FilterClkSel::Clk2 => {
FilterClockSelect::Clk2 => {
syscfg.ioconfig_clkdiv2().write(|w| unsafe { w.bits(div) });
}
FilterClkSel::Clk3 => {
FilterClockSelect::Clk3 => {
syscfg.ioconfig_clkdiv3().write(|w| unsafe { w.bits(div) });
}
FilterClkSel::Clk4 => {
FilterClockSelect::Clk4 => {
syscfg.ioconfig_clkdiv4().write(|w| unsafe { w.bits(div) });
}
FilterClkSel::Clk5 => {
FilterClockSelect::Clk5 => {
syscfg.ioconfig_clkdiv5().write(|w| unsafe { w.bits(div) });
}
FilterClkSel::Clk6 => {
FilterClockSelect::Clk6 => {
syscfg.ioconfig_clkdiv6().write(|w| unsafe { w.bits(div) });
}
FilterClkSel::Clk7 => {
FilterClockSelect::Clk7 => {
syscfg.ioconfig_clkdiv7().write(|w| unsafe { w.bits(div) });
}
}
va108xx-hal/src/gpio/mod.rs
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@@ -17,4 +17,4 @@
//!
//! - [Blinky example](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/examples/simple/examples/blinky.rs)
//! - [Async GPIO example](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/examples/embassy/src/bin/async-gpio.rs)
pub use vorago_shared_periphs::gpio::*;
pub use vorago_shared_hal::gpio::*;
va108xx-hal/src/i2c.rs
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@@ -3,4 +3,4 @@
//! ## Examples
//!
//! - [REB1 I2C temperature sensor example](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/vorago-reb1/examples/adt75-temp-sensor.rs)
pub use vorago_shared_periphs::i2c::*;
pub use vorago_shared_hal::i2c::*;
va108xx-hal/src/lib.rs
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@@ -17,8 +17,9 @@ pub mod time;
pub mod timer;
pub mod uart;
pub use vorago_shared_periphs::{
disable_nvic_interrupt, enable_nvic_interrupt, FunSel, InterruptConfig, PeripheralSelect,
pub use vorago_shared_hal::{
disable_nvic_interrupt, enable_nvic_interrupt, FunctionSelect, InterruptConfig,
PeripheralSelect,
};
/// This is the NONE destination reigster value for the IRQSEL peripheral.
@@ -38,7 +39,7 @@ pub fn port_function_select(
ioconfig: &mut pac::Ioconfig,
port: Port,
pin: u8,
funsel: FunSel,
funsel: FunctionSelect,
) -> Result<(), InvalidPinError> {
if (port == Port::A && pin >= 32) || (port == Port::B && pin >= 24) {
return Err(InvalidPinError(pin));
@@ -46,7 +47,7 @@ pub fn port_function_select(
let reg_block = match port {
Port::A => ioconfig.porta(pin as usize),
Port::B => ioconfig.portb0(pin as usize),
Port::B => ioconfig.portb(pin as usize),
};
reg_block.modify(|_, w| unsafe { w.funsel().bits(funsel as u8) });
va108xx-hal/src/pins.rs
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@@ -3,4 +3,4 @@
//! This module contains the pin singletons. It allows creating those singletons
//! to access the [Pin] structures of individual ports in a safe way with checked ownership
//! rules.
pub use vorago_shared_periphs::pins::*;
pub use vorago_shared_hal::pins::*;
va108xx-hal/src/pwm.rs
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@@ -5,4 +5,4 @@
//! ## Examples
//!
//! - [PWM example](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/examples/simple/examples/pwm.rs)
pub use vorago_shared_periphs::pwm::*;
pub use vorago_shared_hal::pwm::*;
va108xx-hal/src/spi/mod.rs
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@@ -9,4 +9,4 @@
//! - [Blocking SPI example](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/examples/simple/examples/spi.rs)
//! - [REB1 ADC example](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/vorago-reb1/examples/max11519-adc.rs)
//! - [REB1 EEPROM library](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/vorago-reb1/src/m95m01.rs)
pub use vorago_shared_periphs::spi::*;
pub use vorago_shared_hal::spi::*;
va108xx-hal/src/sysconfig.rs
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@@ -38,6 +38,6 @@ pub fn disable_ram_scrubbing() {
syscfg.ram_scrub().write(|w| unsafe { w.bits(0) });
}
pub use vorago_shared_periphs::sysconfig::{
pub use vorago_shared_hal::sysconfig::{
assert_peripheral_reset, disable_peripheral_clock, enable_peripheral_clock,
};
va108xx-hal/src/time.rs
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@@ -1,2 +1,2 @@
//! Time units
pub use vorago_shared_periphs::time::*;
pub use vorago_shared_hal::time::*;
va108xx-hal/src/timer.rs
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@@ -4,4 +4,4 @@
//!
//! - [MS and second tick implementation](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/examples/simple/examples/timer-ticks.rs)
//! - [Cascade feature example](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/examples/simple/examples/cascade.rs)
pub use vorago_shared_periphs::timer::*;
pub use vorago_shared_hal::timer::*;
va108xx-hal/src/uart/mod.rs
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@@ -14,4 +14,4 @@
//! - [Flashloader exposing a CCSDS interface via UART](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/flashloader)
//! - [Async UART RX example](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/examples/embassy/src/bin/async-uart-rx.rs)
//! - [Async UART TX example](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/examples/embassy/src/bin/async-uart-tx.rs)
pub use vorago_shared_periphs::uart::*;
pub use vorago_shared_hal::uart::*;