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bootloader/src/lib.rs
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10
bootloader/src/lib.rs
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@ -0,0 +1,10 @@
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#![no_std]
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use core::convert::Infallible;
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/// Simple trait which makes swapping the NVM easier. NVMs only need to implement this interface.
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pub trait NvmInterface {
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fn write(&mut self, address: u32, data: &[u8]) -> Result<(), Infallible>;
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fn read(&mut self, address: u32, buf: &mut [u8]) -> Result<(), Infallible>;
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fn verify(&mut self, address: u32, data: &[u8]) -> Result<bool, Infallible>;
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}
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@ -1,34 +1,15 @@
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//! Vorago bootloader which can boot from two images.
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//!
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//! Bootloader memory map
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//!
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//! * <0x0> Bootloader start <code up to 0x3FFE bytes>
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//! * <0x3FFE> Bootloader CRC <halfword>
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//! * <0x4000> App image A start <code up to 0x1DFFC (~120K) bytes>
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//! * <0x21FFC> App image A CRC check length <halfword>
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//! * <0x21FFE> App image A CRC check value <halfword>
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//! * <0x22000> App image B start <code up to 0x1DFFC (~120K) bytes>
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//! * <0x3FFFC> App image B CRC check length <halfword>
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//! * <0x3FFFE> App image B CRC check value <halfword>
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//! * <0x40000> <end>
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//!
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//! As opposed to the Vorago example code, this bootloader assumes a 40 MHz external clock
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//! but does not scale that clock up.
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#![no_main]
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#![no_std]
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use bootloader::NvmInterface;
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use cortex_m_rt::entry;
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use crc::{Crc, CRC_16_IBM_3740};
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use embedded_hal_bus::spi::{ExclusiveDevice, NoDelay};
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#[cfg(not(feature = "rtt-panic"))]
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use panic_halt as _;
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#[cfg(feature = "rtt-panic")]
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use panic_rtt_target as _;
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use rtt_target::{rprintln, rtt_init_print};
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use va108xx_hal::{
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pac,
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spi::{RomMiso, RomMosi, RomSck, Spi, SpiClkConfig, SpiConfig},
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time::Hertz,
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};
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use va108xx_hal::{pac, time::Hertz};
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use vorago_reb1::m95m01::M95M01;
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// Useful for debugging and see what the bootloader is doing. Enabled currently, because
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@ -84,10 +65,22 @@ enum AppSel {
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B,
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}
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/// Complex type, but this is the price we pay for nice abstraction. It is also very explicit.
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pub type Nvm = M95M01<
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ExclusiveDevice<Spi<pac::Spic, (RomSck, RomMiso, RomMosi), u8>, dummy_pin::DummyPin, NoDelay>,
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>;
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pub struct NvmWrapper(pub M95M01);
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// Newtype pattern. We could now more easily swap the used NVM type.
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impl NvmInterface for NvmWrapper {
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fn write(&mut self, address: u32, data: &[u8]) -> Result<(), core::convert::Infallible> {
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self.0.write(address, data)
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}
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fn read(&mut self, address: u32, buf: &mut [u8]) -> Result<(), core::convert::Infallible> {
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self.0.read(address, buf)
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}
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fn verify(&mut self, address: u32, data: &[u8]) -> Result<bool, core::convert::Infallible> {
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self.0.verify(address, data)
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}
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}
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#[entry]
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fn main() -> ! {
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@ -98,17 +91,7 @@ fn main() -> ! {
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let mut dp = pac::Peripherals::take().unwrap();
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let cp = cortex_m::Peripherals::take().unwrap();
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let spi = Spi::new(
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&mut dp.sysconfig,
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CLOCK_FREQ,
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dp.spic,
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(RomSck, RomMiso, RomMosi),
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// These values are taken from the vorago bootloader app, don't want to experiment here..
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SpiConfig::default().clk_cfg(SpiClkConfig::new(2, 4)),
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);
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let mut nvm =
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M95M01::new(ExclusiveDevice::new_no_delay(spi, dummy_pin::DummyPin::new_low()).unwrap())
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.expect("creating NVM structure failed");
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let mut nvm = M95M01::new(&mut dp.sysconfig, CLOCK_FREQ, dp.spic);
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if FLASH_SELF {
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let mut first_four_bytes: [u8; 4] = [0; 4];
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@ -153,6 +136,8 @@ fn main() -> ! {
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}
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}
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let mut nvm = NvmWrapper(nvm);
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// Check bootloader's CRC (and write it if blank)
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check_own_crc(&dp.sysconfig, &cp, &mut nvm);
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@ -170,7 +155,7 @@ fn main() -> ! {
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}
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}
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fn check_own_crc(sysconfig: &pac::Sysconfig, cp: &cortex_m::Peripherals, nvm: &mut Nvm) {
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fn check_own_crc(sysconfig: &pac::Sysconfig, cp: &cortex_m::Peripherals, nvm: &mut NvmWrapper) {
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let crc_exp = unsafe { (BOOTLOADER_CRC_ADDR as *const u16).read_unaligned().to_be() };
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// I'd prefer to use [core::slice::from_raw_parts], but that is problematic
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// because the address of the bootloader is 0x0, so the NULL check fails and the functions
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@ -81,7 +81,6 @@ fn main() -> ! {
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dp.spia,
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(sck, miso, mosi),
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spi_cfg,
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None,
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);
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spia.set_fill_word(FILL_WORD);
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spia_ref.borrow_mut().replace(spia.downgrade());
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@ -98,7 +97,6 @@ fn main() -> ! {
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dp.spia,
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(sck, miso, mosi),
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spi_cfg,
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None,
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);
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spia.set_fill_word(FILL_WORD);
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spia_ref.borrow_mut().replace(spia.downgrade());
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@ -115,7 +113,6 @@ fn main() -> ! {
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dp.spib,
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(sck, miso, mosi),
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spi_cfg,
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None,
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);
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spib.set_fill_word(FILL_WORD);
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spib_ref.borrow_mut().replace(spib.downgrade());
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//! API for the SPI peripheral
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//! API for the SPI peripheral.
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//!
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//! The main abstraction provided by this module are the [Spi] and the [SpiBase] structure.
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//! These provide the [embedded_hal::spi] traits, but also offer a low level interface
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//! via the [SpiLowLevel] trait.
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//!
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//! ## Examples
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//!
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//! - [Blocking SPI example](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/examples/simple/examples/spi.rs)
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//! - [REB1 ADC example](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/vorago-reb1/examples/max11519-adc.rs)
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//! - [REB1 EEPROM library](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/vorago-reb1/src/m95m01.rs)
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use crate::{
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clock::enable_peripheral_clock,
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gpio::pin::{
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@ -225,9 +231,13 @@ hw_cs_pins!(
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// SPIC
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// Dummy pin defintion for the ROM SCK.
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pub struct RomSck;
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// Dummy pin defintion for the ROM MOSI.
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pub struct RomMosi;
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// Dummy pin defintion for the ROM MISO.
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pub struct RomMiso;
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// Dummy pin defintion for the ROM chip select.
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pub struct RomCs;
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impl Sealed for RomSck {}
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@ -372,6 +382,7 @@ pub struct SpiConfig {
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/// duration of multiple data words. Defaults to true.
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pub blockmode: bool,
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/// This enables the stalling of the SPI SCK if in blockmode and the FIFO is empty.
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/// Currently enabled by default.
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pub bmstall: bool,
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/// By default, configure SPI for master mode (ms == false)
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ms: bool,
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@ -460,6 +471,36 @@ impl WordProvider for u16 {
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// Spi
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//==================================================================================================
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/// Low level access trait for the SPI peripheral.
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pub trait SpiLowLevel {
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/// Low level function to write a word to the SPI FIFO but also checks whether
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/// there is actually data in the FIFO.
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///
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/// Uses the [nb] API to allow usage in blocking and non-blocking contexts.
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fn write_fifo(&self, data: u32) -> nb::Result<(), Infallible>;
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/// Low level function to write a word to the SPI FIFO without checking whether
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/// there FIFO is full.
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///
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/// This does not necesarily mean there is a space in the FIFO available.
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/// Use [Self::write_fifo] function to write a word into the FIFO reliably.
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fn write_fifo_unchecked(&self, data: u32);
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/// Low level function to read a word from the SPI FIFO. Must be preceeded by a
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/// [Self::write_fifo] call.
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///
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/// Uses the [nb] API to allow usage in blocking and non-blocking contexts.
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fn read_fifo(&self) -> nb::Result<u32, Infallible>;
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/// Low level function to read a word from from the SPI FIFO.
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///
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/// This does not necesarily mean there is a word in the FIFO available.
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/// Use the [Self::read_fifo] function to read a word from the FIFO reliably using the [nb]
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/// API.
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/// You might also need to mask the value to ignore the BMSTART/BMSTOP bit.
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fn read_fifo_unchecked(&self) -> u32;
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}
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pub struct SpiBase<SpiInstance, Word = u8> {
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spi: SpiInstance,
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cfg: SpiConfig,
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@ -467,6 +508,7 @@ pub struct SpiBase<SpiInstance, Word = u8> {
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/// Fill word for read-only SPI transactions.
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pub fill_word: Word,
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blockmode: bool,
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bmstall: bool,
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word: PhantomData<Word>,
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}
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@ -591,150 +633,6 @@ pub fn clk_div_for_target_clock(
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// Re-export this so it can be used for the constructor
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pub use crate::typelevel::NoneT;
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impl<
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SpiI: Instance,
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Sck: PinSck<SpiI>,
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Miso: PinMiso<SpiI>,
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Mosi: PinMosi<SpiI>,
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Word: WordProvider,
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> Spi<SpiI, (Sck, Miso, Mosi), Word>
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where
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<Word as TryFrom<u32>>::Error: core::fmt::Debug,
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{
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/// Create a new SPI struct
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///
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/// You can delete the pin type information by calling the
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/// [`downgrade`](Self::downgrade) function
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///
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/// ## Arguments
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/// * `spi` - SPI bus to use
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/// * `pins` - Pins to be used for SPI transactions. These pins are consumed
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/// to ensure the pins can not be used for other purposes anymore
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/// * `spi_cfg` - Configuration specific to the SPI bus
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/// * `transfer_cfg` - Optional initial transfer configuration which includes
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/// configuration which can change across individual SPI transfers like SPI mode
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/// or SPI clock. If only one device is connected, this configuration only needs
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/// to be done once.
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/// * `syscfg` - Can be passed optionally to enable the peripheral clock
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pub fn new(
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syscfg: &mut pac::Sysconfig,
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sys_clk: impl Into<Hertz> + Copy,
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spi: SpiI,
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pins: (Sck, Miso, Mosi),
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spi_cfg: SpiConfig,
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) -> Self {
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enable_peripheral_clock(syscfg, SpiI::PERIPH_SEL);
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let SpiConfig {
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clk,
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init_mode,
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blockmode,
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bmstall,
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ms,
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slave_output_disable,
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loopback_mode,
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master_delayer_capture,
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} = spi_cfg;
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let (cpo_bit, cph_bit) = mode_to_cpo_cph_bit(init_mode);
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spi.ctrl0().write(|w| {
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unsafe {
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w.size().bits(Word::word_reg());
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w.scrdv().bits(clk.scrdv);
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// Clear clock phase and polarity. Will be set to correct value for each
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// transfer
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w.spo().bit(cpo_bit);
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w.sph().bit(cph_bit)
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}
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});
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spi.ctrl1().write(|w| {
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w.lbm().bit(loopback_mode);
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w.sod().bit(slave_output_disable);
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w.ms().bit(ms);
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w.mdlycap().bit(master_delayer_capture);
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w.blockmode().bit(blockmode);
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w.bmstall().bit(bmstall);
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unsafe { w.ss().bits(0) }
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});
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spi.clkprescale()
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.write(|w| unsafe { w.bits(clk.prescale_val as u32) });
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spi.fifo_clr().write(|w| {
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w.rxfifo().set_bit();
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w.txfifo().set_bit()
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});
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// Enable the peripheral as the last step as recommended in the
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// programmers guide
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spi.ctrl1().modify(|_, w| w.enable().set_bit());
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Spi {
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inner: SpiBase {
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spi,
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cfg: spi_cfg,
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sys_clk: sys_clk.into(),
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fill_word: Default::default(),
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blockmode,
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word: PhantomData,
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},
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pins,
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}
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}
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delegate::delegate! {
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to self.inner {
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#[inline]
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pub fn cfg_clock(&mut self, cfg: SpiClkConfig);
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#[inline]
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pub fn cfg_clock_from_div(&mut self, div: u16) -> Result<(), SpiClkConfigError>;
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#[inline]
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pub fn cfg_mode(&mut self, mode: Mode);
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#[inline]
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pub fn perid(&self) -> u32;
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#[inline]
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pub fn fill_word(&self) -> Word;
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#[inline]
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pub fn spi(&self) -> &SpiI;
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/// Configure the hardware chip select given a hardware chip select ID.
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#[inline]
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pub fn cfg_hw_cs(&mut self, hw_cs: HwChipSelectId);
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/// Configure the hardware chip select given a physical hardware CS pin.
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#[inline]
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pub fn cfg_hw_cs_with_pin<HwCs: OptionalHwCs<SpiI>>(&mut self, _hwcs: &HwCs);
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/// Disables the hardware chip select functionality. This can be used when performing
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/// external chip select handling, for example with GPIO pins.
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#[inline]
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pub fn cfg_hw_cs_disable(&mut self);
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/// Utility function to configure all relevant transfer parameters in one go.
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/// This is useful if multiple devices with different clock and mode configurations
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/// are connected to one bus.
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pub fn cfg_transfer<HwCs: OptionalHwCs<SpiI>>(
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&mut self, transfer_cfg: &TransferConfigWithHwcs<HwCs>
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);
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}
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}
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pub fn set_fill_word(&mut self, fill_word: Word) {
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self.inner.fill_word = fill_word;
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}
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/// Releases the SPI peripheral and associated pins
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pub fn release(self) -> (SpiI, (Sck, Miso, Mosi), SpiConfig) {
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(self.inner.spi, self.pins, self.inner.cfg)
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}
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pub fn downgrade(self) -> SpiBase<SpiI, Word> {
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self.inner
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}
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}
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impl<SpiInstance: Instance, Word: WordProvider> SpiBase<SpiInstance, Word>
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where
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<Word as TryFrom<u32>>::Error: core::fmt::Debug,
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@ -855,34 +753,6 @@ where
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});
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}
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/// Sends a word to the slave
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#[inline(always)]
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fn send_blocking(&self, data: u32) {
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// TODO: Upper limit for wait cycles to avoid complete hangups?
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while self.spi.status().read().tnf().bit_is_clear() {}
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self.send(data)
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}
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#[inline(always)]
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fn send(&self, data: u32) {
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self.spi.data().write(|w| unsafe { w.bits(data) });
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}
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/// Read a word from the slave. Must be preceeded by a [`send`](Self::send) call
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#[inline(always)]
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fn read_blocking(&self) -> Word {
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// TODO: Upper limit for wait cycles to avoid complete hangups?
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while self.spi.status().read().rne().bit_is_clear() {}
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self.read_single_word()
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}
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#[inline(always)]
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fn read_single_word(&self) -> Word {
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(self.spi.data().read().bits() & Word::MASK)
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.try_into()
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.unwrap()
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}
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fn flush_internal(&self) {
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let mut status_reg = self.spi.status().read();
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while status_reg.tfe().bit_is_clear()
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@ -890,7 +760,7 @@ where
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|| status_reg.busy().bit_is_set()
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{
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if status_reg.rne().bit_is_set() {
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self.read_single_word();
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self.read_fifo_unchecked();
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}
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status_reg = self.spi.status().read();
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}
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@ -904,18 +774,20 @@ where
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Ok(())
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}
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// Returns the actual bytes sent.
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// The FIFO can hold a guaranteed amount of data, so we can pump it on transfer
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// initialization. Returns the amount of written bytes.
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fn initial_send_fifo_pumping_with_words(&self, words: &[Word]) -> usize {
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if self.blockmode {
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self.spi.ctrl1().modify(|_, w| w.mtxpause().set_bit())
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}
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// Fill the first half of the write FIFO
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let mut current_write_idx = 0;
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for _ in 0..core::cmp::min(FILL_DEPTH, words.len()) {
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if current_write_idx == words.len() - 1 {
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self.send_blocking(words[current_write_idx].into() | BMSTART_BMSTOP_MASK);
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let smaller_idx = core::cmp::min(FILL_DEPTH, words.len());
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for _ in 0..smaller_idx {
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if current_write_idx == smaller_idx.saturating_sub(1) && self.bmstall {
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self.write_fifo_unchecked(words[current_write_idx].into() | BMSTART_BMSTOP_MASK);
|
||||
} else {
|
||||
self.send_blocking(words[current_write_idx].into());
|
||||
self.write_fifo_unchecked(words[current_write_idx].into());
|
||||
}
|
||||
current_write_idx += 1;
|
||||
}
|
||||
@ -925,17 +797,20 @@ where
|
||||
current_write_idx
|
||||
}
|
||||
|
||||
// The FIFO can hold a guaranteed amount of data, so we can pump it on transfer
|
||||
// initialization.
|
||||
fn initial_send_fifo_pumping_with_fill_words(&self, send_len: usize) -> usize {
|
||||
if self.blockmode {
|
||||
self.spi.ctrl1().modify(|_, w| w.mtxpause().set_bit())
|
||||
}
|
||||
// Fill the first half of the write FIFO
|
||||
let mut current_write_idx = 0;
|
||||
for _ in 0..core::cmp::min(FILL_DEPTH, send_len) {
|
||||
if current_write_idx == send_len - 1 {
|
||||
self.send_blocking(self.fill_word.into() | BMSTART_BMSTOP_MASK);
|
||||
let smaller_idx = core::cmp::min(FILL_DEPTH, send_len);
|
||||
for _ in 0..smaller_idx {
|
||||
if current_write_idx == smaller_idx.saturating_sub(1) && self.bmstall {
|
||||
self.write_fifo_unchecked(self.fill_word.into() | BMSTART_BMSTOP_MASK);
|
||||
} else {
|
||||
self.send_blocking(self.fill_word.into());
|
||||
self.write_fifo_unchecked(self.fill_word.into());
|
||||
}
|
||||
current_write_idx += 1;
|
||||
}
|
||||
@ -946,51 +821,35 @@ where
|
||||
}
|
||||
}
|
||||
|
||||
/// Changing the word size also requires a type conversion
|
||||
impl<SpiI: Instance, Sck: PinSck<SpiI>, Miso: PinMiso<SpiI>, Mosi: PinMosi<SpiI>>
|
||||
From<Spi<SpiI, (Sck, Miso, Mosi), u8>> for Spi<SpiI, (Sck, Miso, Mosi), u16>
|
||||
impl<SpiInstance: Instance, Word: WordProvider> SpiLowLevel for SpiBase<SpiInstance, Word>
|
||||
where
|
||||
<Word as TryFrom<u32>>::Error: core::fmt::Debug,
|
||||
{
|
||||
fn from(old_spi: Spi<SpiI, (Sck, Miso, Mosi), u8>) -> Self {
|
||||
old_spi
|
||||
.inner
|
||||
.spi
|
||||
.ctrl0()
|
||||
.modify(|_, w| unsafe { w.size().bits(WordSize::SixteenBits as u8) });
|
||||
Spi {
|
||||
inner: SpiBase {
|
||||
spi: old_spi.inner.spi,
|
||||
cfg: old_spi.inner.cfg,
|
||||
blockmode: old_spi.inner.blockmode,
|
||||
fill_word: Default::default(),
|
||||
sys_clk: old_spi.inner.sys_clk,
|
||||
word: PhantomData,
|
||||
},
|
||||
pins: old_spi.pins,
|
||||
#[inline(always)]
|
||||
fn write_fifo(&self, data: u32) -> nb::Result<(), Infallible> {
|
||||
if self.spi.status().read().tnf().bit_is_clear() {
|
||||
return Err(nb::Error::WouldBlock);
|
||||
}
|
||||
self.write_fifo_unchecked(data);
|
||||
Ok(())
|
||||
}
|
||||
}
|
||||
|
||||
/// Changing the word size also requires a type conversion
|
||||
impl<SpiI: Instance, Sck: PinSck<SpiI>, Miso: PinMiso<SpiI>, Mosi: PinMosi<SpiI>>
|
||||
From<Spi<SpiI, (Sck, Miso, Mosi), u16>> for Spi<SpiI, (Sck, Miso, Mosi), u8>
|
||||
{
|
||||
fn from(old_spi: Spi<SpiI, (Sck, Miso, Mosi), u16>) -> Self {
|
||||
old_spi
|
||||
.inner
|
||||
.spi
|
||||
.ctrl0()
|
||||
.modify(|_, w| unsafe { w.size().bits(WordSize::EightBits as u8) });
|
||||
Spi {
|
||||
inner: SpiBase {
|
||||
spi: old_spi.inner.spi,
|
||||
cfg: old_spi.inner.cfg,
|
||||
blockmode: old_spi.inner.blockmode,
|
||||
sys_clk: old_spi.inner.sys_clk,
|
||||
fill_word: Default::default(),
|
||||
word: PhantomData,
|
||||
},
|
||||
pins: old_spi.pins,
|
||||
#[inline(always)]
|
||||
fn write_fifo_unchecked(&self, data: u32) {
|
||||
self.spi.data().write(|w| unsafe { w.bits(data) });
|
||||
}
|
||||
|
||||
#[inline(always)]
|
||||
fn read_fifo(&self) -> nb::Result<u32, Infallible> {
|
||||
if self.spi.status().read().rne().bit_is_clear() {
|
||||
return Err(nb::Error::WouldBlock);
|
||||
}
|
||||
Ok(self.read_fifo_unchecked())
|
||||
}
|
||||
|
||||
#[inline(always)]
|
||||
fn read_fifo_unchecked(&self) -> u32 {
|
||||
self.spi.data().read().bits()
|
||||
}
|
||||
}
|
||||
|
||||
@ -1003,19 +862,21 @@ where
|
||||
<Word as TryFrom<u32>>::Error: core::fmt::Debug,
|
||||
{
|
||||
fn read(&mut self, words: &mut [Word]) -> Result<(), Self::Error> {
|
||||
//self.transfer_preparation(words)?;
|
||||
self.transfer_preparation(words)?;
|
||||
let mut current_read_idx = 0;
|
||||
let mut current_write_idx = self.initial_send_fifo_pumping_with_fill_words(words.len());
|
||||
loop {
|
||||
if current_read_idx < words.len() {
|
||||
words[current_read_idx] = self.read_blocking();
|
||||
words[current_read_idx] = (nb::block!(self.read_fifo())? & Word::MASK)
|
||||
.try_into()
|
||||
.unwrap();
|
||||
current_read_idx += 1;
|
||||
}
|
||||
if current_write_idx < words.len() {
|
||||
if current_write_idx == words.len() - 1 {
|
||||
self.send_blocking(self.fill_word.into() | BMSTART_BMSTOP_MASK);
|
||||
if current_write_idx == words.len() - 1 && self.bmstall {
|
||||
nb::block!(self.write_fifo(self.fill_word.into() | BMSTART_BMSTOP_MASK))?;
|
||||
} else {
|
||||
self.send_blocking(self.fill_word.into());
|
||||
nb::block!(self.write_fifo(self.fill_word.into()))?;
|
||||
}
|
||||
current_write_idx += 1;
|
||||
}
|
||||
@ -1027,13 +888,13 @@ where
|
||||
}
|
||||
|
||||
fn write(&mut self, words: &[Word]) -> Result<(), Self::Error> {
|
||||
// self.transfer_preparation(words)?;
|
||||
self.transfer_preparation(words)?;
|
||||
let mut current_write_idx = self.initial_send_fifo_pumping_with_words(words);
|
||||
while current_write_idx < words.len() {
|
||||
if current_write_idx == words.len() - 1 {
|
||||
self.send_blocking(words[current_write_idx].into() | BMSTART_BMSTOP_MASK);
|
||||
if current_write_idx == words.len() - 1 && self.bmstall {
|
||||
nb::block!(self.write_fifo(words[current_write_idx].into() | BMSTART_BMSTOP_MASK))?;
|
||||
} else {
|
||||
self.send_blocking(words[current_write_idx].into());
|
||||
nb::block!(self.write_fifo(words[current_write_idx].into()))?;
|
||||
}
|
||||
current_write_idx += 1;
|
||||
// Ignore received words.
|
||||
@ -1045,20 +906,24 @@ where
|
||||
}
|
||||
|
||||
fn transfer(&mut self, read: &mut [Word], write: &[Word]) -> Result<(), Self::Error> {
|
||||
//self.transfer_preparation(write)?;
|
||||
self.transfer_preparation(write)?;
|
||||
let mut current_read_idx = 0;
|
||||
let mut current_write_idx = self.initial_send_fifo_pumping_with_words(write);
|
||||
while current_read_idx < read.len() || current_write_idx < write.len() {
|
||||
if current_write_idx < write.len() {
|
||||
if current_write_idx == write.len() - 1 {
|
||||
self.send_blocking(write[current_write_idx].into() | BMSTART_BMSTOP_MASK);
|
||||
if current_write_idx == write.len() - 1 && self.bmstall {
|
||||
nb::block!(
|
||||
self.write_fifo(write[current_write_idx].into() | BMSTART_BMSTOP_MASK)
|
||||
)?;
|
||||
} else {
|
||||
self.send_blocking(write[current_write_idx].into());
|
||||
nb::block!(self.write_fifo(write[current_write_idx].into()))?;
|
||||
}
|
||||
current_write_idx += 1;
|
||||
}
|
||||
if current_read_idx < read.len() {
|
||||
read[current_read_idx] = self.read_blocking();
|
||||
read[current_read_idx] = (nb::block!(self.read_fifo())? & Word::MASK)
|
||||
.try_into()
|
||||
.unwrap();
|
||||
current_read_idx += 1;
|
||||
}
|
||||
}
|
||||
@ -1067,21 +932,25 @@ where
|
||||
}
|
||||
|
||||
fn transfer_in_place(&mut self, words: &mut [Word]) -> Result<(), Self::Error> {
|
||||
//self.transfer_preparation(words)?;
|
||||
self.transfer_preparation(words)?;
|
||||
let mut current_read_idx = 0;
|
||||
let mut current_write_idx = self.initial_send_fifo_pumping_with_words(words);
|
||||
|
||||
while current_read_idx < words.len() || current_write_idx < words.len() {
|
||||
if current_write_idx < words.len() {
|
||||
if current_write_idx == words.len() - 1 {
|
||||
self.send_blocking(words[current_write_idx].into() | BMSTART_BMSTOP_MASK);
|
||||
if current_write_idx == words.len() - 1 && self.bmstall {
|
||||
nb::block!(
|
||||
self.write_fifo(words[current_write_idx].into() | BMSTART_BMSTOP_MASK)
|
||||
)?;
|
||||
} else {
|
||||
self.send_blocking(words[current_write_idx].into());
|
||||
nb::block!(self.write_fifo(words[current_write_idx].into()))?;
|
||||
}
|
||||
current_write_idx += 1;
|
||||
}
|
||||
if current_read_idx < words.len() && current_read_idx < current_write_idx {
|
||||
words[current_read_idx] = self.read_blocking();
|
||||
words[current_read_idx] = (nb::block!(self.read_fifo())? & Word::MASK)
|
||||
.try_into()
|
||||
.unwrap();
|
||||
current_read_idx += 1;
|
||||
}
|
||||
}
|
||||
@ -1094,6 +963,199 @@ where
|
||||
}
|
||||
}
|
||||
|
||||
impl<
|
||||
SpiI: Instance,
|
||||
Sck: PinSck<SpiI>,
|
||||
Miso: PinMiso<SpiI>,
|
||||
Mosi: PinMosi<SpiI>,
|
||||
Word: WordProvider,
|
||||
> Spi<SpiI, (Sck, Miso, Mosi), Word>
|
||||
where
|
||||
<Word as TryFrom<u32>>::Error: core::fmt::Debug,
|
||||
{
|
||||
/// Create a new SPI struct
|
||||
///
|
||||
/// You can delete the pin type information by calling the
|
||||
/// [`downgrade`](Self::downgrade) function
|
||||
///
|
||||
/// ## Arguments
|
||||
/// * `syscfg` - Can be passed optionally to enable the peripheral clock
|
||||
/// * `sys_clk` - System clock
|
||||
/// * `spi` - SPI bus to use
|
||||
/// * `pins` - Pins to be used for SPI transactions. These pins are consumed
|
||||
/// to ensure the pins can not be used for other purposes anymore
|
||||
/// * `spi_cfg` - Configuration specific to the SPI bus
|
||||
pub fn new(
|
||||
syscfg: &mut pac::Sysconfig,
|
||||
sys_clk: impl Into<Hertz>,
|
||||
spi: SpiI,
|
||||
pins: (Sck, Miso, Mosi),
|
||||
spi_cfg: SpiConfig,
|
||||
) -> Self {
|
||||
enable_peripheral_clock(syscfg, SpiI::PERIPH_SEL);
|
||||
let SpiConfig {
|
||||
clk,
|
||||
init_mode,
|
||||
blockmode,
|
||||
bmstall,
|
||||
ms,
|
||||
slave_output_disable,
|
||||
loopback_mode,
|
||||
master_delayer_capture,
|
||||
} = spi_cfg;
|
||||
|
||||
let (cpo_bit, cph_bit) = mode_to_cpo_cph_bit(init_mode);
|
||||
spi.ctrl0().write(|w| {
|
||||
unsafe {
|
||||
w.size().bits(Word::word_reg());
|
||||
w.scrdv().bits(clk.scrdv);
|
||||
// Clear clock phase and polarity. Will be set to correct value for each
|
||||
// transfer
|
||||
w.spo().bit(cpo_bit);
|
||||
w.sph().bit(cph_bit)
|
||||
}
|
||||
});
|
||||
|
||||
spi.ctrl1().write(|w| {
|
||||
w.lbm().bit(loopback_mode);
|
||||
w.sod().bit(slave_output_disable);
|
||||
w.ms().bit(ms);
|
||||
w.mdlycap().bit(master_delayer_capture);
|
||||
w.blockmode().bit(blockmode);
|
||||
w.bmstall().bit(bmstall);
|
||||
unsafe { w.ss().bits(0) }
|
||||
});
|
||||
spi.clkprescale()
|
||||
.write(|w| unsafe { w.bits(clk.prescale_val as u32) });
|
||||
|
||||
spi.fifo_clr().write(|w| {
|
||||
w.rxfifo().set_bit();
|
||||
w.txfifo().set_bit()
|
||||
});
|
||||
// Enable the peripheral as the last step as recommended in the
|
||||
// programmers guide
|
||||
spi.ctrl1().modify(|_, w| w.enable().set_bit());
|
||||
Spi {
|
||||
inner: SpiBase {
|
||||
spi,
|
||||
cfg: spi_cfg,
|
||||
sys_clk: sys_clk.into(),
|
||||
fill_word: Default::default(),
|
||||
bmstall,
|
||||
blockmode,
|
||||
word: PhantomData,
|
||||
},
|
||||
pins,
|
||||
}
|
||||
}
|
||||
|
||||
delegate::delegate! {
|
||||
to self.inner {
|
||||
#[inline]
|
||||
pub fn cfg_clock(&mut self, cfg: SpiClkConfig);
|
||||
|
||||
#[inline]
|
||||
pub fn cfg_clock_from_div(&mut self, div: u16) -> Result<(), SpiClkConfigError>;
|
||||
|
||||
#[inline]
|
||||
pub fn cfg_mode(&mut self, mode: Mode);
|
||||
|
||||
#[inline]
|
||||
pub fn perid(&self) -> u32;
|
||||
|
||||
#[inline]
|
||||
pub fn fill_word(&self) -> Word;
|
||||
|
||||
#[inline]
|
||||
pub fn spi(&self) -> &SpiI;
|
||||
|
||||
/// Configure the hardware chip select given a hardware chip select ID.
|
||||
#[inline]
|
||||
pub fn cfg_hw_cs(&mut self, hw_cs: HwChipSelectId);
|
||||
|
||||
/// Configure the hardware chip select given a physical hardware CS pin.
|
||||
#[inline]
|
||||
pub fn cfg_hw_cs_with_pin<HwCs: OptionalHwCs<SpiI>>(&mut self, _hwcs: &HwCs);
|
||||
|
||||
/// Disables the hardware chip select functionality. This can be used when performing
|
||||
/// external chip select handling, for example with GPIO pins.
|
||||
#[inline]
|
||||
pub fn cfg_hw_cs_disable(&mut self);
|
||||
|
||||
/// Utility function to configure all relevant transfer parameters in one go.
|
||||
/// This is useful if multiple devices with different clock and mode configurations
|
||||
/// are connected to one bus.
|
||||
pub fn cfg_transfer<HwCs: OptionalHwCs<SpiI>>(
|
||||
&mut self, transfer_cfg: &TransferConfigWithHwcs<HwCs>
|
||||
);
|
||||
|
||||
/// Low level function to write a word to the SPI FIFO but also checks whether
|
||||
/// there is actually data in the FIFO.
|
||||
///
|
||||
/// Uses the [nb] API to allow usage in blocking and non-blocking contexts.
|
||||
#[inline(always)]
|
||||
pub fn write_fifo(&self, data: u32) -> nb::Result<(), Infallible>;
|
||||
|
||||
/// Low level function to write a word to the SPI FIFO.
|
||||
///
|
||||
/// This does not necesarily mean there is a space in the FIFO available.
|
||||
/// Use [Self::write_fifo] function to write a word into the FIFO reliably using the
|
||||
/// [nb] API.
|
||||
#[inline(always)]
|
||||
pub fn write_fifo_unchecked(&self, data: u32);
|
||||
|
||||
/// Low level function to read a word from the SPI FIFO. Must be preceeded by a
|
||||
/// [Self::write_fifo] call.
|
||||
///
|
||||
/// Uses the [nb] API to allow usage in blocking and non-blocking contexts.
|
||||
#[inline(always)]
|
||||
pub fn read_fifo(&self) -> nb::Result<u32, Infallible>;
|
||||
|
||||
/// Low level function to read a word from from the SPI FIFO.
|
||||
///
|
||||
/// This does not necesarily mean there is a word in the FIFO available.
|
||||
/// Use the [Self::read_fifo] function to read a word from the FIFO reliably using the [nb]
|
||||
/// API.
|
||||
/// You might also need to mask the value to ignore the BMSTART/BMSTOP bit.
|
||||
#[inline(always)]
|
||||
pub fn read_fifo_unchecked(&self) -> u32;
|
||||
}
|
||||
}
|
||||
|
||||
pub fn set_fill_word(&mut self, fill_word: Word) {
|
||||
self.inner.fill_word = fill_word;
|
||||
}
|
||||
|
||||
/// Releases the SPI peripheral and associated pins
|
||||
pub fn release(self) -> (SpiI, (Sck, Miso, Mosi), SpiConfig) {
|
||||
(self.inner.spi, self.pins, self.inner.cfg)
|
||||
}
|
||||
|
||||
pub fn downgrade(self) -> SpiBase<SpiI, Word> {
|
||||
self.inner
|
||||
}
|
||||
}
|
||||
|
||||
impl<
|
||||
SpiI: Instance,
|
||||
Sck: PinSck<SpiI>,
|
||||
Miso: PinMiso<SpiI>,
|
||||
Mosi: PinMosi<SpiI>,
|
||||
Word: WordProvider,
|
||||
> SpiLowLevel for Spi<SpiI, (Sck, Miso, Mosi), Word>
|
||||
where
|
||||
<Word as TryFrom<u32>>::Error: core::fmt::Debug,
|
||||
{
|
||||
delegate::delegate! {
|
||||
to self.inner {
|
||||
fn write_fifo(&self, data: u32) -> nb::Result<(), Infallible>;
|
||||
fn write_fifo_unchecked(&self, data: u32);
|
||||
fn read_fifo(&self) -> nb::Result<u32, Infallible>;
|
||||
fn read_fifo_unchecked(&self) -> u32;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
impl<
|
||||
SpiI: Instance,
|
||||
Word: WordProvider,
|
||||
@ -1125,3 +1187,53 @@ where
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/// Changing the word size also requires a type conversion
|
||||
impl<SpiI: Instance, Sck: PinSck<SpiI>, Miso: PinMiso<SpiI>, Mosi: PinMosi<SpiI>>
|
||||
From<Spi<SpiI, (Sck, Miso, Mosi), u8>> for Spi<SpiI, (Sck, Miso, Mosi), u16>
|
||||
{
|
||||
fn from(old_spi: Spi<SpiI, (Sck, Miso, Mosi), u8>) -> Self {
|
||||
old_spi
|
||||
.inner
|
||||
.spi
|
||||
.ctrl0()
|
||||
.modify(|_, w| unsafe { w.size().bits(WordSize::SixteenBits as u8) });
|
||||
Spi {
|
||||
inner: SpiBase {
|
||||
spi: old_spi.inner.spi,
|
||||
cfg: old_spi.inner.cfg,
|
||||
blockmode: old_spi.inner.blockmode,
|
||||
fill_word: Default::default(),
|
||||
bmstall: old_spi.inner.bmstall,
|
||||
sys_clk: old_spi.inner.sys_clk,
|
||||
word: PhantomData,
|
||||
},
|
||||
pins: old_spi.pins,
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/// Changing the word size also requires a type conversion
|
||||
impl<SpiI: Instance, Sck: PinSck<SpiI>, Miso: PinMiso<SpiI>, Mosi: PinMosi<SpiI>>
|
||||
From<Spi<SpiI, (Sck, Miso, Mosi), u16>> for Spi<SpiI, (Sck, Miso, Mosi), u8>
|
||||
{
|
||||
fn from(old_spi: Spi<SpiI, (Sck, Miso, Mosi), u16>) -> Self {
|
||||
old_spi
|
||||
.inner
|
||||
.spi
|
||||
.ctrl0()
|
||||
.modify(|_, w| unsafe { w.size().bits(WordSize::EightBits as u8) });
|
||||
Spi {
|
||||
inner: SpiBase {
|
||||
spi: old_spi.inner.spi,
|
||||
cfg: old_spi.inner.cfg,
|
||||
blockmode: old_spi.inner.blockmode,
|
||||
bmstall: old_spi.inner.bmstall,
|
||||
sys_clk: old_spi.inner.sys_clk,
|
||||
fill_word: Default::default(),
|
||||
word: PhantomData,
|
||||
},
|
||||
pins: old_spi.pins,
|
||||
}
|
||||
}
|
||||
}
|
||||
|
@ -5,7 +5,7 @@
|
||||
#![no_main]
|
||||
#![no_std]
|
||||
use cortex_m_rt::entry;
|
||||
use embedded_hal::spi::SpiBus;
|
||||
use embedded_hal::spi::{SpiBus, MODE_3};
|
||||
use embedded_hal::{delay::DelayNs, digital::OutputPin};
|
||||
use panic_rtt_target as _;
|
||||
use rtt_target::{rprintln, rtt_init_print};
|
||||
@ -14,7 +14,7 @@ use va108xx_hal::{
|
||||
gpio::PinsA,
|
||||
pac,
|
||||
prelude::*,
|
||||
spi::{Spi, SpiConfig, TransferConfigWithHwcs},
|
||||
spi::{Spi, SpiConfig},
|
||||
timer::set_up_ms_delay_provider,
|
||||
};
|
||||
|
||||
@ -32,7 +32,6 @@ fn main() -> ! {
|
||||
let mut dp = pac::Peripherals::take().unwrap();
|
||||
let mut delay = set_up_ms_delay_provider(&mut dp.sysconfig, 50.MHz(), dp.tim0);
|
||||
let pinsa = PinsA::new(&mut dp.sysconfig, None, dp.porta);
|
||||
let spi_cfg = SpiConfig::default();
|
||||
let (sck, mosi, miso) = (
|
||||
pinsa.pa20.into_funsel_2(),
|
||||
pinsa.pa19.into_funsel_2(),
|
||||
@ -46,21 +45,20 @@ fn main() -> ! {
|
||||
.set_high()
|
||||
.expect("Setting ADC chip select high failed");
|
||||
|
||||
let transfer_cfg = TransferConfigWithHwcs::new(
|
||||
Some(SpiClkConfig::from_clk(50.MHz(), 1.MHz()).expect("creating SPI clock config failed")),
|
||||
Some(embedded_hal::spi::MODE_3),
|
||||
Some(cs_pin),
|
||||
false,
|
||||
true,
|
||||
);
|
||||
let spi_cfg = SpiConfig::default()
|
||||
.clk_cfg(
|
||||
SpiClkConfig::from_clk(50.MHz(), 1.MHz()).expect("creating SPI clock config failed"),
|
||||
)
|
||||
.mode(MODE_3)
|
||||
.slave_output_disable(true);
|
||||
let mut spi = Spi::new(
|
||||
&mut dp.sysconfig,
|
||||
50.MHz(),
|
||||
dp.spib,
|
||||
(sck, miso, mosi),
|
||||
spi_cfg,
|
||||
Some(&transfer_cfg.downgrade()),
|
||||
);
|
||||
spi.cfg_hw_cs_with_pin(&cs_pin);
|
||||
|
||||
let mut tx_rx_buf: [u8; 3] = [0; 3];
|
||||
tx_rx_buf[0] = READ_MASK | DEVID_REG;
|
||||
|
@ -9,7 +9,7 @@ use core::convert::Infallible;
|
||||
|
||||
use cortex_m_rt::entry;
|
||||
use embedded_hal::digital::OutputPin;
|
||||
use embedded_hal::spi::{SpiBus, SpiDevice};
|
||||
use embedded_hal::spi::{SpiBus, SpiDevice, MODE_0};
|
||||
use embedded_hal::{delay::DelayNs, spi};
|
||||
use max116xx_10bit::VoltageRefMode;
|
||||
use max116xx_10bit::{AveragingConversions, AveragingResults};
|
||||
@ -21,7 +21,7 @@ use va108xx_hal::{
|
||||
gpio::PinsA,
|
||||
pac::{self, interrupt},
|
||||
prelude::*,
|
||||
spi::{Spi, SpiBase, SpiConfig, TransferConfigWithHwcs},
|
||||
spi::{Spi, SpiBase, SpiConfig},
|
||||
timer::{default_ms_irq_handler, set_up_ms_tick, DelayMs, IrqCfg},
|
||||
};
|
||||
use va108xx_hal::{port_mux, FunSel, PortSel};
|
||||
@ -124,7 +124,10 @@ fn main() -> ! {
|
||||
}
|
||||
|
||||
let pinsa = PinsA::new(&mut dp.sysconfig, None, dp.porta);
|
||||
let spi_cfg = SpiConfig::default().clk_cfg(SpiClkConfig::from_clk(SYS_CLK, 3.MHz()).unwrap());
|
||||
let spi_cfg = SpiConfig::default()
|
||||
.clk_cfg(SpiClkConfig::from_clk(SYS_CLK, 3.MHz()).unwrap())
|
||||
.mode(MODE_0)
|
||||
.blockmode(true);
|
||||
let (sck, mosi, miso) = (
|
||||
pinsa.pa20.into_funsel_2(),
|
||||
pinsa.pa19.into_funsel_2(),
|
||||
@ -143,7 +146,6 @@ fn main() -> ! {
|
||||
.set_high()
|
||||
.expect("Setting accelerometer chip select high failed");
|
||||
|
||||
let transfer_cfg = TransferConfigWithHwcs::new_no_hw_cs(None, Some(spi::MODE_0), true, false);
|
||||
let spi = Spi::new(
|
||||
&mut dp.sysconfig,
|
||||
50.MHz(),
|
||||
|
@ -1,23 +1,13 @@
|
||||
//! Example application which interfaces with the boot EEPROM.
|
||||
#![no_main]
|
||||
#![no_std]
|
||||
|
||||
use cortex_m_rt::entry;
|
||||
use embedded_hal::spi::{SpiBus, MODE_0};
|
||||
use embedded_hal_bus::spi::ExclusiveDevice;
|
||||
use embedded_hal::delay::DelayNs;
|
||||
use panic_rtt_target as _;
|
||||
use rtt_target::{rprintln, rtt_init_print};
|
||||
use va108xx_hal::{
|
||||
pac,
|
||||
spi::{
|
||||
RomCs, RomMiso, RomMosi, RomSck, Spi, SpiClkConfig, SpiConfig, TransferConfigWithHwcs,
|
||||
BMSTART_BMSTOP_MASK,
|
||||
},
|
||||
time::Hertz,
|
||||
};
|
||||
use vorago_reb1::m95m01::{
|
||||
regs::{RDSR, WREN},
|
||||
StatusReg, M95M01,
|
||||
};
|
||||
use va108xx_hal::{pac, pwm::CountDownTimer, time::Hertz};
|
||||
use vorago_reb1::m95m01::M95M01;
|
||||
|
||||
const CLOCK_FREQ: Hertz = Hertz::from_raw(50_000_000);
|
||||
|
||||
@ -27,49 +17,48 @@ fn main() -> ! {
|
||||
rprintln!("-- VA108XX REB1 NVM example --");
|
||||
|
||||
let mut dp = pac::Peripherals::take().unwrap();
|
||||
let cp = cortex_m::Peripherals::take().unwrap();
|
||||
|
||||
let mut spi = Spi::<pac::Spic, (RomSck, RomMiso, RomMosi)>::new(
|
||||
&mut dp.sysconfig,
|
||||
CLOCK_FREQ,
|
||||
dp.spic,
|
||||
(RomSck, RomMiso, RomMosi),
|
||||
// These values are taken from the vorago bootloader app, don't want to experiment here..
|
||||
SpiConfig::default().clk_cfg(SpiClkConfig::new(2, 4)),
|
||||
);
|
||||
let mut read_buf: [u8; 2] = [0; 2];
|
||||
let spi = spi.spi();
|
||||
unsafe {
|
||||
spi.data().write(|w| w.bits(RDSR.into()));
|
||||
spi.data().write(|w| w.bits(0 | BMSTART_BMSTOP_MASK));
|
||||
}
|
||||
while spi.status().read().tfe().bit_is_clear() {}
|
||||
while spi.status().read().rne().bit_is_clear() {}
|
||||
let dummy = spi.data().read().bits();
|
||||
while spi.status().read().rne().bit_is_clear() {}
|
||||
let reg = StatusReg(spi.data().read().bits() as u8);
|
||||
rprintln!("status reg {:?}", reg);
|
||||
//spi.transfer(&mut read_buf, &[RDSR, 0]);
|
||||
rprintln!("read buf {:?}", read_buf);
|
||||
//spi.write(&[WREN]);
|
||||
/*
|
||||
let mut nvm =
|
||||
M95M01::new(ExclusiveDevice::new_no_delay(spi, dummy_pin::DummyPin::new_low()).unwrap())
|
||||
.expect("creating NVM structure failed");
|
||||
let mut timer = CountDownTimer::new(&mut dp.sysconfig, CLOCK_FREQ, dp.tim0);
|
||||
let mut nvm = M95M01::new(&mut dp.sysconfig, CLOCK_FREQ, dp.spic);
|
||||
let status_reg = nvm.read_status_reg().expect("reading status reg failed");
|
||||
rprintln!("status reg: {:?}", status_reg);
|
||||
if status_reg.zero_segment() == 0b111 {
|
||||
panic!("status register unexpected values");
|
||||
}
|
||||
|
||||
let mut orig_content: [u8; 16] = [0; 16];
|
||||
let mut read_buf: [u8; 16] = [0; 16];
|
||||
nvm.read(0x4000, &mut read_buf[0..4])
|
||||
.expect("reading NVM failed");
|
||||
rprintln!("NVM address 0x4000: {:x?}", &read_buf[0..4]);
|
||||
let write_buf: [u8; 4] = [1, 2, 3, 4];
|
||||
nvm.write(0x4000, &write_buf).unwrap();
|
||||
let write_buf: [u8; 16] = [0; 16];
|
||||
for (idx, val) in read_buf.iter_mut().enumerate() {
|
||||
*val = idx as u8;
|
||||
}
|
||||
nvm.read(0x4000, &mut orig_content).unwrap();
|
||||
|
||||
// One byte write and read.
|
||||
nvm.write(0x4000, &write_buf[0..1]).unwrap();
|
||||
nvm.read(0x4000, &mut read_buf[0..1]).unwrap();
|
||||
assert_eq!(write_buf[0], read_buf[0]);
|
||||
read_buf.fill(0);
|
||||
|
||||
// Four bytes write and read.
|
||||
nvm.write(0x4000, &write_buf[0..4]).unwrap();
|
||||
nvm.read(0x4000, &mut read_buf[0..4]).unwrap();
|
||||
assert_eq!(&read_buf[0..4], write_buf);
|
||||
*/
|
||||
loop {}
|
||||
assert_eq!(&read_buf[0..4], &write_buf[0..4]);
|
||||
read_buf.fill(0);
|
||||
|
||||
// Full sixteen bytes
|
||||
nvm.write(0x4000, &write_buf).unwrap();
|
||||
nvm.read(0x4000, &mut read_buf).unwrap();
|
||||
assert_eq!(&read_buf, &write_buf);
|
||||
read_buf.fill(0);
|
||||
|
||||
// 3 bytes
|
||||
nvm.write(0x4000, &write_buf[0..3]).unwrap();
|
||||
nvm.read(0x4000, &mut read_buf[0..3]).unwrap();
|
||||
assert_eq!(&read_buf[0..3], &write_buf[0..3]);
|
||||
|
||||
// Write back original content.
|
||||
nvm.write(0x4000, &orig_content).unwrap();
|
||||
loop {
|
||||
timer.delay_ms(500);
|
||||
}
|
||||
}
|
||||
|
@ -1,5 +1,14 @@
|
||||
use core::fmt::Debug;
|
||||
use embedded_hal::spi::{Operation, SpiDevice};
|
||||
//! Basic driver for the ST M95M01 EEPROM memory.
|
||||
//!
|
||||
//! This driver is used by the provided bootloader application for the REB1
|
||||
//! board. It provides a convenient wrapper around the HAL SPI to interface
|
||||
//! with the EEPROM memory of the REB1 board.
|
||||
//!
|
||||
//! # Example
|
||||
//!
|
||||
//! - [REB1 EEPROM example](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/vorago-reb1/examples/nvm.rs)
|
||||
use core::convert::Infallible;
|
||||
use embedded_hal::spi::SpiBus;
|
||||
|
||||
bitfield::bitfield! {
|
||||
pub struct StatusReg(u8);
|
||||
@ -29,42 +38,43 @@ pub mod regs {
|
||||
}
|
||||
|
||||
use regs::*;
|
||||
use va108xx_hal::{
|
||||
pac,
|
||||
prelude::*,
|
||||
spi::{RomMiso, RomMosi, RomSck, Spi, SpiConfig, BMSTART_BMSTOP_MASK},
|
||||
};
|
||||
|
||||
pub type RomSpi = Spi<pac::Spic, (RomSck, RomMiso, RomMosi), u8>;
|
||||
|
||||
/// Driver for the ST device M95M01 EEPROM memory.
|
||||
pub struct M95M01<Spi: SpiDevice> {
|
||||
spi: Spi,
|
||||
///
|
||||
/// Specialized for the requirements of the VA108XX MCUs.
|
||||
pub struct M95M01 {
|
||||
pub spi: RomSpi,
|
||||
}
|
||||
|
||||
#[derive(Debug)]
|
||||
pub enum Error<SpiError: Debug> {
|
||||
Spi(SpiError),
|
||||
BufTooShort,
|
||||
}
|
||||
|
||||
impl<SpiError: Debug> From<SpiError> for Error<SpiError> {
|
||||
fn from(value: SpiError) -> Self {
|
||||
Self::Spi(value)
|
||||
}
|
||||
}
|
||||
|
||||
impl<Spi: SpiDevice> M95M01<Spi>
|
||||
where
|
||||
Spi::Error: Debug,
|
||||
{
|
||||
pub fn new(spi: Spi) -> Result<Self, Spi::Error> {
|
||||
impl M95M01 {
|
||||
pub fn new(syscfg: &mut pac::Sysconfig, sys_clk: impl Into<Hertz>, spi: pac::Spic) -> Self {
|
||||
let spi = RomSpi::new(
|
||||
syscfg,
|
||||
sys_clk,
|
||||
spi,
|
||||
(RomSck, RomMiso, RomMosi),
|
||||
SpiConfig::default(),
|
||||
);
|
||||
let mut spi_dev = Self { spi };
|
||||
spi_dev.clear_block_protection()?;
|
||||
Ok(spi_dev)
|
||||
spi_dev.clear_block_protection().unwrap();
|
||||
spi_dev
|
||||
}
|
||||
|
||||
pub fn release(mut self) -> Result<Spi, Spi::Error> {
|
||||
self.set_block_protection()?;
|
||||
Ok(self.spi)
|
||||
pub fn release(mut self) -> pac::Spic {
|
||||
self.set_block_protection().unwrap();
|
||||
self.spi.release().0
|
||||
}
|
||||
|
||||
// Wait until the write-in-progress state is cleared. This exposes a [nb] API, so this function
|
||||
// will return [nb::Error::WouldBlock] if the EEPROM is still busy.
|
||||
pub fn writes_are_done(&mut self) -> nb::Result<(), Spi::Error> {
|
||||
pub fn writes_are_done(&mut self) -> nb::Result<(), Infallible> {
|
||||
let rdsr = self.read_status_reg()?;
|
||||
if rdsr.write_in_progress() {
|
||||
return Err(nb::Error::WouldBlock);
|
||||
@ -72,82 +82,91 @@ where
|
||||
Ok(())
|
||||
}
|
||||
|
||||
pub fn read_status_reg(&mut self) -> Result<StatusReg, Spi::Error> {
|
||||
pub fn read_status_reg(&mut self) -> Result<StatusReg, Infallible> {
|
||||
let mut write_read: [u8; 2] = [regs::RDSR, 0x00];
|
||||
self.spi.transfer_in_place(&mut write_read)?;
|
||||
Ok(StatusReg(write_read[1]))
|
||||
}
|
||||
|
||||
pub fn write_enable(&mut self) -> Result<(), Spi::Error> {
|
||||
pub fn write_enable(&mut self) -> Result<(), Infallible> {
|
||||
self.spi.write(&[regs::WREN])
|
||||
}
|
||||
|
||||
pub fn clear_block_protection(&mut self) -> Result<(), Spi::Error> {
|
||||
pub fn clear_block_protection(&mut self) -> Result<(), Infallible> {
|
||||
// Has to be written separately.
|
||||
self.spi.write(&[WREN])?;
|
||||
self.write_enable()?;
|
||||
self.spi.write(&[WRSR, 0x00])
|
||||
}
|
||||
|
||||
pub fn set_block_protection(&mut self) -> Result<(), Spi::Error> {
|
||||
pub fn set_block_protection(&mut self) -> Result<(), Infallible> {
|
||||
let mut reg = StatusReg(0);
|
||||
reg.set_block_protection_bits(0b11);
|
||||
self.spi.write(&[WREN, WRSR, reg.0])
|
||||
}
|
||||
|
||||
pub fn write(&mut self, address: u32, data: &[u8]) -> Result<(), Spi::Error> {
|
||||
nb::block!(self.writes_are_done())?;
|
||||
self.write_enable()?;
|
||||
self.spi.transaction(&mut [
|
||||
Operation::Write(&[
|
||||
WRITE,
|
||||
((address >> 16) & 0xff) as u8,
|
||||
((address >> 8) & 0xff) as u8,
|
||||
(address & 0xff) as u8,
|
||||
]),
|
||||
Operation::Write(data),
|
||||
])?;
|
||||
Ok(())
|
||||
self.spi.write(&[WRSR, reg.0])
|
||||
}
|
||||
|
||||
pub fn read(&mut self, address: u32, buf: &mut [u8]) -> Result<(), Error<Spi::Error>> {
|
||||
if buf.len() < buf.len() {
|
||||
return Err(Error::BufTooShort);
|
||||
fn common_init_write_and_read(&mut self, address: u32, reg: u8) -> Result<(), Infallible> {
|
||||
nb::block!(self.writes_are_done())?;
|
||||
self.spi.flush()?;
|
||||
if reg == WRITE {
|
||||
self.write_enable()?;
|
||||
self.spi.write_fifo_unchecked(WRITE as u32);
|
||||
} else {
|
||||
self.spi.write_fifo_unchecked(READ as u32);
|
||||
}
|
||||
nb::block!(self.writes_are_done())?;
|
||||
|
||||
self.spi.transaction(&mut [
|
||||
Operation::Write(&[
|
||||
READ,
|
||||
((address >> 16) & 0xff) as u8,
|
||||
((address >> 8) & 0xff) as u8,
|
||||
(address & 0xff) as u8,
|
||||
]),
|
||||
Operation::Read(buf),
|
||||
])?;
|
||||
self.spi.write_fifo_unchecked((address >> 16) & 0xff);
|
||||
self.spi.write_fifo_unchecked((address >> 8) & 0xff);
|
||||
self.spi.write_fifo_unchecked(address & 0xff);
|
||||
Ok(())
|
||||
}
|
||||
|
||||
pub fn verify(&mut self, address: u32, data: &[u8]) -> Result<bool, Spi::Error> {
|
||||
fn common_read(&mut self, address: u32) -> Result<(), Infallible> {
|
||||
self.common_init_write_and_read(address, READ)?;
|
||||
for _ in 0..4 {
|
||||
// Pump the FIFO.
|
||||
self.spi.write_fifo_unchecked(0);
|
||||
// Ignore the first 4 bytes.
|
||||
self.spi.read_fifo_unchecked();
|
||||
}
|
||||
Ok(())
|
||||
}
|
||||
|
||||
pub fn write(&mut self, address: u32, data: &[u8]) -> Result<(), Infallible> {
|
||||
self.common_init_write_and_read(address, WRITE)?;
|
||||
for val in data.iter().take(data.len() - 1) {
|
||||
nb::block!(self.spi.write_fifo(*val as u32))?;
|
||||
self.spi.read_fifo_unchecked();
|
||||
}
|
||||
nb::block!(self
|
||||
.spi
|
||||
.write_fifo(*data.last().unwrap() as u32 | BMSTART_BMSTOP_MASK))?;
|
||||
self.spi.flush()?;
|
||||
nb::block!(self.writes_are_done())?;
|
||||
// Write the read command and address
|
||||
self.spi.write(&[
|
||||
READ,
|
||||
((address >> 16) & 0xff) as u8,
|
||||
((address >> 8) & 0xff) as u8,
|
||||
(address & 0xff) as u8,
|
||||
])?;
|
||||
Ok(())
|
||||
}
|
||||
|
||||
// Read and compare each byte in place
|
||||
for original_byte in data.iter() {
|
||||
let mut read_byte = [0u8];
|
||||
self.spi.read(&mut read_byte)?;
|
||||
pub fn read(&mut self, address: u32, buf: &mut [u8]) -> Result<(), Infallible> {
|
||||
self.common_read(address)?;
|
||||
for val in buf.iter_mut() {
|
||||
nb::block!(self.spi.write_fifo(0))?;
|
||||
*val = (nb::block!(self.spi.read_fifo()).unwrap() & 0xff) as u8;
|
||||
}
|
||||
nb::block!(self.spi.write_fifo(BMSTART_BMSTOP_MASK))?;
|
||||
self.spi.flush()?;
|
||||
Ok(())
|
||||
}
|
||||
|
||||
// Compare read byte with original
|
||||
if read_byte[0] != *original_byte {
|
||||
pub fn verify(&mut self, address: u32, data: &[u8]) -> Result<bool, Infallible> {
|
||||
self.common_read(address)?;
|
||||
for val in data.iter() {
|
||||
nb::block!(self.spi.write_fifo(0))?;
|
||||
let read_val = (nb::block!(self.spi.read_fifo()).unwrap() & 0xff) as u8;
|
||||
if read_val != *val {
|
||||
return Ok(false);
|
||||
}
|
||||
}
|
||||
|
||||
nb::block!(self.spi.write_fifo(BMSTART_BMSTOP_MASK))?;
|
||||
self.spi.flush()?;
|
||||
Ok(true)
|
||||
}
|
||||
}
|
||||
|
@ -355,6 +355,30 @@
|
||||
]
|
||||
}
|
||||
},
|
||||
{
|
||||
"type": "cortex-debug",
|
||||
"request": "launch",
|
||||
"name": "REB1 NVM Example",
|
||||
"servertype": "jlink",
|
||||
"cwd": "${workspaceRoot}",
|
||||
"device": "Cortex-M0",
|
||||
"svdFile": "./va108xx/svd/va108xx.svd.patched",
|
||||
"preLaunchTask": "reb1-nvm",
|
||||
"executable": "${workspaceFolder}/target/thumbv6m-none-eabi/debug/examples/nvm",
|
||||
"interface": "jtag",
|
||||
"runToEntryPoint": "main",
|
||||
"rttConfig": {
|
||||
"enabled": true,
|
||||
"address": "auto",
|
||||
"decoders": [
|
||||
{
|
||||
"port": 0,
|
||||
"timestamp": true,
|
||||
"type": "console"
|
||||
}
|
||||
]
|
||||
}
|
||||
},
|
||||
{
|
||||
"type": "cortex-debug",
|
||||
"request": "launch",
|
||||
|
@ -154,8 +154,6 @@
|
||||
"command": "~/.cargo/bin/cargo", // note: full path to the cargo
|
||||
"args": [
|
||||
"build",
|
||||
"-p",
|
||||
"vorago-reb1",
|
||||
"--example",
|
||||
"blinky-leds",
|
||||
],
|
||||
@ -170,8 +168,6 @@
|
||||
"command": "~/.cargo/bin/cargo", // note: full path to the cargo
|
||||
"args": [
|
||||
"build",
|
||||
"-p",
|
||||
"vorago-reb1",
|
||||
"--example",
|
||||
"blinky-button-irq",
|
||||
],
|
||||
@ -186,8 +182,6 @@
|
||||
"command": "~/.cargo/bin/cargo", // note: full path to the cargo
|
||||
"args": [
|
||||
"build",
|
||||
"-p",
|
||||
"vorago-reb1",
|
||||
"--example",
|
||||
"adt75-temp-sensor",
|
||||
],
|
||||
@ -202,8 +196,6 @@
|
||||
"command": "~/.cargo/bin/cargo", // note: full path to the cargo
|
||||
"args": [
|
||||
"build",
|
||||
"-p",
|
||||
"vorago-reb1",
|
||||
"--example",
|
||||
"blinky-button-rtic",
|
||||
],
|
||||
@ -218,8 +210,6 @@
|
||||
"command": "~/.cargo/bin/cargo", // note: full path to the cargo
|
||||
"args": [
|
||||
"build",
|
||||
"-p",
|
||||
"vorago-reb1",
|
||||
"--example",
|
||||
"adxl343-accelerometer"
|
||||
],
|
||||
@ -234,8 +224,6 @@
|
||||
"command": "~/.cargo/bin/cargo", // note: full path to the cargo
|
||||
"args": [
|
||||
"build",
|
||||
"-p",
|
||||
"vorago-reb1",
|
||||
"--example",
|
||||
"max11619-adc",
|
||||
],
|
||||
@ -244,6 +232,20 @@
|
||||
"isDefault": true
|
||||
}
|
||||
},
|
||||
{
|
||||
"label": "reb1-nvm",
|
||||
"type": "shell",
|
||||
"command": "~/.cargo/bin/cargo", // note: full path to the cargo
|
||||
"args": [
|
||||
"build",
|
||||
"--example",
|
||||
"nvm",
|
||||
],
|
||||
"group": {
|
||||
"kind": "build",
|
||||
"isDefault": true
|
||||
}
|
||||
},
|
||||
{
|
||||
"label": "rtic-example",
|
||||
"type": "shell",
|
||||
@ -265,4 +267,4 @@
|
||||
],
|
||||
},
|
||||
]
|
||||
}
|
||||
}
|
||||
|
Loading…
Reference in New Issue
Block a user