clean up
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a1a5156caf
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@ -4,7 +4,7 @@ use core::convert::Infallible;
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/// Simple trait which makes swapping the NVM easier. NVMs only need to implement this interface.
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/// Simple trait which makes swapping the NVM easier. NVMs only need to implement this interface.
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pub trait NvmInterface {
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pub trait NvmInterface {
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fn write(&mut self, address: u32, data: &[u8]) -> Result<(), Infallible>;
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fn write(&mut self, address: usize, data: &[u8]) -> Result<(), Infallible>;
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fn read(&mut self, address: u32, buf: &mut [u8]) -> Result<(), Infallible>;
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fn read(&mut self, address: usize, buf: &mut [u8]) -> Result<(), Infallible>;
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fn verify(&mut self, address: u32, data: &[u8]) -> Result<bool, Infallible>;
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fn verify(&mut self, address: usize, data: &[u8]) -> Result<bool, Infallible>;
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}
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}
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@ -78,15 +78,15 @@ pub struct NvmWrapper(pub M95M01);
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// Newtype pattern. We could now more easily swap the used NVM type.
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// Newtype pattern. We could now more easily swap the used NVM type.
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impl NvmInterface for NvmWrapper {
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impl NvmInterface for NvmWrapper {
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fn write(&mut self, address: u32, data: &[u8]) -> Result<(), core::convert::Infallible> {
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fn write(&mut self, address: usize, data: &[u8]) -> Result<(), core::convert::Infallible> {
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self.0.write(address, data)
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self.0.write(address, data)
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}
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}
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fn read(&mut self, address: u32, buf: &mut [u8]) -> Result<(), core::convert::Infallible> {
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fn read(&mut self, address: usize, buf: &mut [u8]) -> Result<(), core::convert::Infallible> {
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self.0.read(address, buf)
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self.0.read(address, buf)
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}
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}
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fn verify(&mut self, address: u32, data: &[u8]) -> Result<bool, core::convert::Infallible> {
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fn verify(&mut self, address: usize, data: &[u8]) -> Result<bool, core::convert::Infallible> {
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self.0.verify(address, data)
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self.0.verify(address, data)
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}
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}
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}
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}
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@ -133,9 +133,9 @@ fn main() -> ! {
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}
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}
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}
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}
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nvm.write(BOOTLOADER_CRC_ADDR, &bootloader_crc.to_be_bytes())
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nvm.write(BOOTLOADER_CRC_ADDR as usize, &bootloader_crc.to_be_bytes())
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.expect("writing CRC failed");
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.expect("writing CRC failed");
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if let Err(e) = nvm.verify(BOOTLOADER_CRC_ADDR, &bootloader_crc.to_be_bytes()) {
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if let Err(e) = nvm.verify(BOOTLOADER_CRC_ADDR as usize, &bootloader_crc.to_be_bytes()) {
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if RTT_PRINTOUT {
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if RTT_PRINTOUT {
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rprintln!(
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rprintln!(
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"error: CRC verification for bootloader self-flash failed: {:?}",
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"error: CRC verification for bootloader self-flash failed: {:?}",
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@ -185,7 +185,7 @@ fn check_own_crc(sysconfig: &pac::Sysconfig, cp: &cortex_m::Peripherals, nvm: &m
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rprintln!("BL CRC blank - prog new CRC");
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rprintln!("BL CRC blank - prog new CRC");
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}
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}
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// Blank CRC, write it to NVM.
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// Blank CRC, write it to NVM.
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nvm.write(BOOTLOADER_CRC_ADDR, &crc_calc.to_be_bytes())
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nvm.write(BOOTLOADER_CRC_ADDR as usize, &crc_calc.to_be_bytes())
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.expect("writing CRC failed");
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.expect("writing CRC failed");
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// The Vorago bootloader resets here. I am not sure why this is done but I think it is
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// The Vorago bootloader resets here. I am not sure why this is done but I think it is
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// necessary because somehow the boot will not work if we just continue as usual.
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// necessary because somehow the boot will not work if we just continue as usual.
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@ -324,12 +324,12 @@ mod app {
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let mut buf = [0u8; 4];
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let mut buf = [0u8; 4];
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cx.local
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cx.local
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.nvm
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.nvm
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.read(base_addr + 32, &mut buf)
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.read(base_addr as usize + 32, &mut buf)
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.expect("reading from NVM failed");
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.expect("reading from NVM failed");
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buf[0] += 1;
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buf[0] += 1;
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cx.local
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cx.local
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.nvm
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.nvm
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.write(base_addr + 32, &buf)
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.write(base_addr as usize + 32, &buf)
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.expect("writing to NVM failed");
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.expect("writing to NVM failed");
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let tm = cx
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let tm = cx
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.local
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.local
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@ -405,7 +405,7 @@ mod app {
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);
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);
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cx.local
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cx.local
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.nvm
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.nvm
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.write(offset, data)
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.write(offset as usize, data)
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.expect("writing to NVM failed");
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.expect("writing to NVM failed");
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let tm = cx
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let tm = cx
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.local
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.local
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@ -1,10 +1,6 @@
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//! Example application which interfaces with the boot EEPROM.
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//! Example application which interfaces with the boot EEPROM.
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#![no_main]
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#![no_main]
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#![no_std]
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#![no_std]
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use core::fmt::write;
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use cortex_m::{asm, register::control::read};
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use cortex_m_rt::entry;
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use cortex_m_rt::entry;
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use embedded_hal::delay::DelayNs;
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use embedded_hal::delay::DelayNs;
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use panic_rtt_target as _;
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use panic_rtt_target as _;
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@ -51,7 +47,7 @@ fn main() -> ! {
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nvm.read(PAGE_SIZE - 2, &mut read_buf[0..8]).unwrap();
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nvm.read(PAGE_SIZE - 2, &mut read_buf[0..8]).unwrap();
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assert_eq!(&read_buf[0..8], &write_buf[0..8]);
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assert_eq!(&read_buf[0..8], &write_buf[0..8]);
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nvm.write(0, &orig_content);
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nvm.write(0, &orig_content).unwrap();
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loop {
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loop {
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timer.delay_ms(500);
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timer.delay_ms(500);
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}
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}
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