consisten naming and signatures for GPIO

.github/workflows/ci.yml

@@ -12,8 +12,6 @@ jobs:
           targets: "thumbv6m-none-eabi"
       - run: cargo check --target thumbv6m-none-eabi
       - run: cargo check --target thumbv6m-none-eabi --examples
-      - run: cargo check -p va108xx --target thumbv6m-none-eabi --all-features
-      - run: cargo check -p va108xx-hal --target thumbv6m-none-eabi --features "defmt"
 
   test:
     name: Run Tests
@@ -41,8 +39,8 @@ jobs:
     steps:
       - uses: actions/checkout@v4
       - uses: dtolnay/rust-toolchain@nightly
-      - run: RUSTDOCFLAGS="--cfg docsrs --generate-link-to-definition -Z unstable-options" cargo +nightly doc -p va108xx --all-features
+      - run: RUSTDOCFLAGS="--cfg docsrs --generate-link-to-definition -Z unstable-options" cargo +nightly doc -p va108xx
-      - run: RUSTDOCFLAGS="--cfg docsrs --generate-link-to-definition -Z unstable-options" cargo +nightly doc -p va108xx-hal --all-features
+      - run: RUSTDOCFLAGS="--cfg docsrs --generate-link-to-definition -Z unstable-options" cargo +nightly doc -p va108xx-hal
       - run: RUSTDOCFLAGS="--cfg docsrs --generate-link-to-definition -Z unstable-options" cargo +nightly doc -p vorago-reb1
 
   clippy:

board-tests/src/main.rs

@@ -137,12 +137,15 @@ fn main() -> ! {
             }
         }
         TestCase::DelayGpio => {
-            let mut out_0 = pinsa.pa0.into_readable_push_pull_output();
+            let mut out_0 = pinsa
-            out_0.configure_delay(true, false);
+                .pa0
-            let mut out_1 = pinsa.pa1.into_readable_push_pull_output();
+                .into_readable_push_pull_output()
-            out_1.configure_delay(false, true);
+                .configure_delay(true, false);
-            let mut out_2 = pinsa.pa3.into_readable_push_pull_output();
+            let mut out_1 = pinsa
-            out_2.configure_delay(true, true);
+                .pa1
+                .into_readable_push_pull_output()
+                .configure_delay(false, true);
+            let mut out_2 = pinsa.pa3.into_readable_push_pull_output().configure_delay(true, true);
             for _ in 0..20 {
                 out_0.toggle().unwrap();
                 out_1.toggle().unwrap();

examples/embassy/Cargo.toml

@@ -27,8 +27,8 @@ embassy-executor = { version = "0.7", features = [
   "executor-interrupt"
 ]}
 
-va108xx-hal = { version = "0.9", path = "../../va108xx-hal" }
+va108xx-hal = "0.9"
-va108xx-embassy = { version = "0.1", path = "../../va108xx-embassy" }
+va108xx-embassy = "0.1"
 
 [features]
 default = ["ticks-hz-1_000", "va108xx-embassy/irq-oc30-oc31"]

examples/embassy/src/bin/async-gpio.rs

@@ -14,9 +14,7 @@ use embedded_hal_async::digital::Wait;
 use panic_rtt_target as _;
 use rtt_target::{rprintln, rtt_init_print};
 use va108xx_embassy::embassy;
-use va108xx_hal::gpio::{
+use va108xx_hal::gpio::{on_interrupt_for_asynch_gpio, InputDynPinAsync, InputPinAsync, PinsB};
-    on_interrupt_for_async_gpio_for_port, InputDynPinAsync, InputPinAsync, PinsB, Port,
-};
 use va108xx_hal::{
     gpio::{DynPin, PinsA},
     pac::{self, interrupt},
@@ -246,16 +244,15 @@ async fn output_task(
 }
 
 // PB22 to PB23 can be handled by both OC10 and OC11 depending on configuration.
+
 #[interrupt]
 #[allow(non_snake_case)]
 fn OC10() {
-    on_interrupt_for_async_gpio_for_port(Port::A);
+    on_interrupt_for_asynch_gpio();
-    on_interrupt_for_async_gpio_for_port(Port::B);
 }
 
-// This interrupt only handles PORT B interrupts.
 #[interrupt]
 #[allow(non_snake_case)]
 fn OC11() {
-    on_interrupt_for_async_gpio_for_port(Port::B);
+    on_interrupt_for_asynch_gpio();
 }

va108xx-embassy/Cargo.toml

@@ -20,7 +20,7 @@ embassy-time-queue-utils = "0.1"
 
 once_cell = { version = "1", default-features = false, features = ["critical-section"] }
 
-va108xx-hal = { version = "0.9", path = "../va108xx-hal" }
+va108xx-hal = "0.9"
 
 [target.'cfg(all(target_arch = "arm", target_os = "none"))'.dependencies]
 portable-atomic = { version = "1", features = ["unsafe-assume-single-core"] }

va108xx-hal/CHANGELOG.md

@@ -8,24 +8,6 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ## [unreleased]
 
-## [v0.10.0]
-
-## Added
-
-- A lot of missing `defmt::Format` implementations.
-
-## Changed
-
-- Missing GPIO API replacements from `x` to `configure_x`
-- Renamed GPIO `DynGroup` to `Port`
-- Rename generic GPIO interrupt handler into `on_interrupt_for_asynch_gpio`
-  into `on_interrupt_for_async_gpio_for_port` which expects a Port argument
-
-## Fixed
-
-- Bug in async GPIO interrupt handler where all enabled interrupts, even the ones which might
-  be unrelated to the pin, were disabled.
-
 ## [v0.9.0]
 
 ## Fixed

va108xx-hal/Cargo.toml

@@ -29,7 +29,7 @@ static_cell = "2"
 thiserror = { version = "2", default-features = false }
 void = { version = "1", default-features = false }
 once_cell = {version = "1", default-features = false }
-va108xx = { version = "0.5", path = "../va108xx", default-features = false, features = ["critical-section", "defmt"] }
+va108xx = { version = "0.4", default-features = false, features = ["critical-section"] }
 embassy-sync = "0.6"
 
 defmt = { version = "0.3", optional = true }
@@ -42,7 +42,7 @@ portable-atomic = "1"
 [features]
 default = ["rt"]
 rt = ["va108xx/rt"]
-defmt = ["dep:defmt", "fugit/defmt", "embedded-hal/defmt-03"]
+defmt = ["dep:defmt", "fugit/defmt"]
 
 [package.metadata.docs.rs]
 all-features = true

va108xx-hal/src/gpio/asynch.rs

@@ -3,9 +3,9 @@
 //! This module provides the [InputPinAsync] and [InputDynPinAsync] which both implement
 //! the [embedded_hal_async::digital::Wait] trait. These types allow for asynchronous waiting
 //! on GPIO pins. Please note that this module does not specify/declare the interrupt handlers
-//! which must be provided for async support to work. However, it provides the
+//! which must be provided for async support to work. However, it provides one generic
-//! [on_interrupt_for_async_gpio_for_port] generic interrupt handler. This should be called in all
+//! [handler][on_interrupt_for_asynch_gpio] which should be called in ALL user interrupt handlers
-//! IRQ functions which handle any GPIO interrupts with the corresponding [Port] argument.
+//! which handle GPIO interrupts.
 //!
 //! # Example
 //!
@@ -21,67 +21,61 @@ use va108xx::{self as pac, Irqsel, Sysconfig};
 use crate::InterruptConfig;
 
 use super::{
-    pin, DynPin, DynPinId, InputConfig, InterruptEdge, InvalidPinTypeError, Pin, PinId, Port,
+    pin, DynGroup, DynPin, DynPinId, InputConfig, InterruptEdge, InvalidPinTypeError, Pin, PinId,
-    NUM_PINS_PORT_A, NUM_PINS_PORT_B,
+    NUM_GPIO_PINS, NUM_PINS_PORT_A,
 };
 
-static WAKERS_FOR_PORT_A: [AtomicWaker; NUM_PINS_PORT_A] =
+static WAKERS: [AtomicWaker; NUM_GPIO_PINS] = [const { AtomicWaker::new() }; NUM_GPIO_PINS];
-    [const { AtomicWaker::new() }; NUM_PINS_PORT_A];
+static EDGE_DETECTION: [AtomicBool; NUM_GPIO_PINS] =
-static WAKERS_FOR_PORT_B: [AtomicWaker; NUM_PINS_PORT_B] =
+    [const { AtomicBool::new(false) }; NUM_GPIO_PINS];
-    [const { AtomicWaker::new() }; NUM_PINS_PORT_B];
-static EDGE_DETECTION_PORT_A: [AtomicBool; NUM_PINS_PORT_A] =
-    [const { AtomicBool::new(false) }; NUM_PINS_PORT_A];
-static EDGE_DETECTION_PORT_B: [AtomicBool; NUM_PINS_PORT_B] =
-    [const { AtomicBool::new(false) }; NUM_PINS_PORT_B];
-
-/// Generic interrupt handler for GPIO interrupts on a specific port to support async functionalities
-///
-/// This function should be called in all interrupt handlers which handle any GPIO interrupts
-/// matching the [Port] argument.
-/// The handler will wake the corresponding wakers for the pins that triggered an interrupts
-/// as well as update the static edge detection structures. This allows the pin future tocomplete
-/// complete async operations.
-pub fn on_interrupt_for_async_gpio_for_port(port: Port) {
-    let periphs = unsafe { pac::Peripherals::steal() };
-
-    let (irq_enb, edge_status, wakers, edge_detection) = match port {
-        Port::A => (
-            periphs.porta.irq_enb().read().bits(),
-            periphs.porta.edge_status().read().bits(),
-            WAKERS_FOR_PORT_A.as_ref(),
-            EDGE_DETECTION_PORT_A.as_ref(),
-        ),
-        Port::B => (
-            periphs.portb.irq_enb().read().bits(),
-            periphs.portb.edge_status().read().bits(),
-            WAKERS_FOR_PORT_B.as_ref(),
-            EDGE_DETECTION_PORT_B.as_ref(),
-        ),
-    };
-
-    on_interrupt_for_port(irq_enb, edge_status, wakers, edge_detection);
-}
 
 #[inline]
-fn on_interrupt_for_port(
+fn pin_id_to_offset(dyn_pin_id: DynPinId) -> usize {
-    mut irq_enb: u32,
+    match dyn_pin_id.group {
-    edge_status: u32,
+        DynGroup::A => dyn_pin_id.num as usize,
-    wakers: &'static [AtomicWaker],
+        DynGroup::B => NUM_PINS_PORT_A + dyn_pin_id.num as usize,
-    edge_detection: &'static [AtomicBool],
+    }
-) {
+}
+
+/// Generic interrupt handler for GPIO interrupts to support the async functionalities.
+///
+/// This handler will wake the correspoding wakers for the pins which triggered an interrupt
+/// as well as updating the static edge detection structures. This allows the pin future to
+/// complete async operations. The user should call this function in ALL interrupt handlers
+/// which handle any GPIO interrupts.
+#[inline]
+pub fn on_interrupt_for_asynch_gpio() {
+    let periphs = unsafe { pac::Peripherals::steal() };
+
+    handle_interrupt_for_gpio_and_port(
+        periphs.porta.irq_enb().read().bits(),
+        periphs.porta.edge_status().read().bits(),
+        0,
+    );
+    handle_interrupt_for_gpio_and_port(
+        periphs.portb.irq_enb().read().bits(),
+        periphs.portb.edge_status().read().bits(),
+        NUM_PINS_PORT_A,
+    );
+}
+
+// Uses the enabled interrupt register and the persistent edge status to capture all GPIO events.
+#[inline]
+fn handle_interrupt_for_gpio_and_port(mut irq_enb: u32, edge_status: u32, pin_base_offset: usize) {
     while irq_enb != 0 {
         let bit_pos = irq_enb.trailing_zeros() as usize;
         let bit_mask = 1 << bit_pos;
 
-        wakers[bit_pos].wake();
+        WAKERS[pin_base_offset + bit_pos].wake();
 
         if edge_status & bit_mask != 0 {
-            edge_detection[bit_pos].store(true, core::sync::atomic::Ordering::Relaxed);
+            EDGE_DETECTION[pin_base_offset + bit_pos]
+                .store(true, core::sync::atomic::Ordering::Relaxed);
+        }
 
         // Clear the processed bit
         irq_enb &= !bit_mask;
     }
-    }
 }
 
 /// Input pin future which implements the [Future] trait.
@@ -91,8 +85,6 @@ fn on_interrupt_for_port(
 /// struture is granted  to allow writing custom async structures.
 pub struct InputPinFuture {
     pin_id: DynPinId,
-    waker_group: &'static [AtomicWaker],
-    edge_detection_group: &'static [AtomicBool],
 }
 
 impl InputPinFuture {
@@ -110,16 +102,6 @@ impl InputPinFuture {
         Self::new_with_dyn_pin(pin, irq, edge, &mut periphs.sysconfig, &mut periphs.irqsel)
     }
 
-    #[inline]
-    pub fn pin_group_to_waker_and_edge_detection_group(
-        group: Port,
-    ) -> (&'static [AtomicWaker], &'static [AtomicBool]) {
-        match group {
-            Port::A => (WAKERS_FOR_PORT_A.as_ref(), EDGE_DETECTION_PORT_A.as_ref()),
-            Port::B => (WAKERS_FOR_PORT_B.as_ref(), EDGE_DETECTION_PORT_B.as_ref()),
-        }
-    }
-
     pub fn new_with_dyn_pin(
         pin: &mut DynPin,
         irq: pac::Interrupt,
@@ -131,9 +113,7 @@ impl InputPinFuture {
             return Err(InvalidPinTypeError(pin.mode()));
         }
 
-        let (waker_group, edge_detection_group) =
+        EDGE_DETECTION[pin_id_to_offset(pin.id())]
-            Self::pin_group_to_waker_and_edge_detection_group(pin.id().group);
-        edge_detection_group[pin.id().num as usize]
             .store(false, core::sync::atomic::Ordering::Relaxed);
         pin.configure_edge_interrupt(
             edge,
@@ -142,11 +122,7 @@ impl InputPinFuture {
             Some(irq_sel),
         )
         .unwrap();
-        Ok(Self {
+        Ok(Self { pin_id: pin.id() })
-            pin_id: pin.id(),
-            waker_group,
-            edge_detection_group,
-        })
     }
 
     /// # Safety
@@ -170,9 +146,7 @@ impl InputPinFuture {
         sys_cfg: &mut Sysconfig,
         irq_sel: &mut Irqsel,
     ) -> Self {
-        let (waker_group, edge_detection_group) =
+        EDGE_DETECTION[pin_id_to_offset(pin.id())]
-            Self::pin_group_to_waker_and_edge_detection_group(pin.id().group);
-        edge_detection_group[pin.id().num as usize]
             .store(false, core::sync::atomic::Ordering::Relaxed);
         pin.configure_edge_interrupt(
             edge,
@@ -180,18 +154,14 @@ impl InputPinFuture {
             Some(sys_cfg),
             Some(irq_sel),
         );
-        Self {
+        Self { pin_id: pin.id() }
-            pin_id: pin.id(),
-            edge_detection_group,
-            waker_group,
-        }
     }
 }
 
 impl Drop for InputPinFuture {
     fn drop(&mut self) {
         let periphs = unsafe { pac::Peripherals::steal() };
-        if self.pin_id.group == Port::A {
+        if self.pin_id.group == DynGroup::A {
             periphs
                 .porta
                 .irq_enb()
@@ -211,9 +181,9 @@ impl Future for InputPinFuture {
         self: core::pin::Pin<&mut Self>,
         cx: &mut core::task::Context<'_>,
     ) -> core::task::Poll<Self::Output> {
-        let idx = self.pin_id.num as usize;
+        let idx = pin_id_to_offset(self.pin_id);
-        self.waker_group[idx].register(cx.waker());
+        WAKERS[idx].register(cx.waker());
-        if self.edge_detection_group[idx].swap(false, core::sync::atomic::Ordering::Relaxed) {
+        if EDGE_DETECTION[idx].swap(false, core::sync::atomic::Ordering::Relaxed) {
             return core::task::Poll::Ready(());
         }
         core::task::Poll::Pending
@@ -230,8 +200,8 @@ impl InputDynPinAsync {
     /// passed as well and is used to route and enable the interrupt.
     ///
     /// Please note that the interrupt handler itself must be provided by the user and the
-    /// generic [on_interrupt_for_async_gpio_for_port] function must be called inside that function
+    /// generic [on_interrupt_for_asynch_gpio] function must be called inside that function for
-    /// for the asynchronous functionality to work.
+    /// the asynchronous functionality to work.
     pub fn new(pin: DynPin, irq: pac::Interrupt) -> Result<Self, InvalidPinTypeError> {
         if !pin.is_input_pin() {
             return Err(InvalidPinTypeError(pin.mode()));
@@ -365,8 +335,8 @@ impl<I: PinId, C: InputConfig> InputPinAsync<I, C> {
     /// passed as well and is used to route and enable the interrupt.
     ///
     /// Please note that the interrupt handler itself must be provided by the user and the
-    /// generic [on_interrupt_for_async_gpio_for_port] function must be called inside that function
+    /// generic [on_interrupt_for_asynch_gpio] function must be called inside that function for
-    /// for the asynchronous functionality to work.
+    /// the asynchronous functionality to work.
     pub fn new(pin: Pin<I, pin::Input<C>>, irq: pac::Interrupt) -> Self {
         Self { pin, irq }
     }

va108xx-hal/src/gpio/dynpin.rs

@@ -57,9 +57,9 @@
 //! [InvalidPinTypeError].
 
 use super::{
-    pin::{FilterType, Pin, PinId, PinMode},
+    pin::{FilterType, InterruptEdge, InterruptLevel, Pin, PinId, PinMode, PinState},
     reg::RegisterInterface,
-    InputDynPinAsync, InterruptEdge, InterruptLevel, PinState,
+    InputDynPinAsync,
 };
 use crate::{clock::FilterClkSel, enable_nvic_interrupt, pac, FunSel, InterruptConfig};
 
@@ -156,13 +156,19 @@ pub const DYN_ALT_FUNC_3: DynPinMode = DynPinMode::Alternate(DynAlternate::Sel3)
 //  DynGroup & DynPinId
 //==================================================================================================
 
-pub type DynGroup = super::Port;
+/// Value-level `enum` for pin groups
+#[derive(Debug, PartialEq, Eq, Clone, Copy)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub enum DynGroup {
+    A,
+    B,
+}
 
 /// Value-level `struct` representing pin IDs
 #[derive(Debug, PartialEq, Eq, Clone, Copy)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub struct DynPinId {
-    pub group: super::Port,
+    pub group: DynGroup,
     pub num: u8,
 }
 
@@ -363,12 +369,12 @@ impl DynPin {
             if irq_cfg.route {
                 match self.regs.id().group {
                     // Set the correct interrupt number in the IRQSEL register
-                    super::Port::A => {
+                    DynGroup::A => {
                         irqsel
                             .porta0(self.regs.id().num as usize)
                             .write(|w| unsafe { w.bits(irq_cfg.id as u32) });
                     }
-                    super::Port::B => {
+                    DynGroup::B => {
                         irqsel
                             .portb0(self.regs.id().num as usize)
                             .write(|w| unsafe { w.bits(irq_cfg.id as u32) });

va108xx-hal/src/gpio/mod.rs

@@ -22,47 +22,14 @@
 //!
 //! - [Blinky example](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/examples/simple/examples/blinky.rs)
 
-//==================================================================================================
-//  Errors, Definitions and Constants
-//==================================================================================================
-
-pub const NUM_PINS_PORT_A: usize = 32;
-pub const NUM_PINS_PORT_B: usize = 24;
-pub const NUM_GPIO_PINS: usize = NUM_PINS_PORT_A + NUM_PINS_PORT_B;
-
 #[derive(Debug, PartialEq, Eq, thiserror::Error)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[error("The pin is masked")]
 pub struct IsMaskedError;
 
-#[derive(Debug, PartialEq, Eq, Clone, Copy)]
+pub const NUM_PINS_PORT_A: usize = 32;
-#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub const NUM_PINS_PORT_B: usize = 24;
-pub enum Port {
+pub const NUM_GPIO_PINS: usize = NUM_PINS_PORT_A + NUM_PINS_PORT_B;
-    A,
-    B,
-}
-
-#[derive(Debug, PartialEq, Eq)]
-#[cfg_attr(feature = "defmt", derive(defmt::Format))]
-pub enum InterruptEdge {
-    HighToLow,
-    LowToHigh,
-    BothEdges,
-}
-
-#[derive(Debug, PartialEq, Eq)]
-#[cfg_attr(feature = "defmt", derive(defmt::Format))]
-pub enum InterruptLevel {
-    Low = 0,
-    High = 1,
-}
-
-#[derive(Debug, PartialEq, Eq)]
-#[cfg_attr(feature = "defmt", derive(defmt::Format))]
-pub enum PinState {
-    Low = 0,
-    High = 1,
-}
 
 pub mod dynpin;
 pub use dynpin::*;

va108xx-hal/src/gpio/pin.rs

@@ -70,9 +70,9 @@
 //! This module implements all of the embedded HAL GPIO traits for each [`Pin`]
 //! in the corresponding [`PinMode`]s, namely: [`InputPin`], [`OutputPin`],
 //! and [`StatefulOutputPin`].
-use super::dynpin::{DynAlternate, DynInput, DynOutput, DynPinId, DynPinMode};
+use super::dynpin::{DynAlternate, DynGroup, DynInput, DynOutput, DynPinId, DynPinMode};
 use super::reg::RegisterInterface;
-use super::{DynPin, InputPinAsync, InterruptEdge, InterruptLevel, PinState, Port};
+use super::{DynPin, InputPinAsync};
 use crate::{
     pac::{Irqsel, Porta, Portb, Sysconfig},
     typelevel::Sealed,
@@ -84,6 +84,32 @@ use core::mem::transmute;
 use embedded_hal::digital::{InputPin, OutputPin, StatefulOutputPin};
 use paste::paste;
 
+//==================================================================================================
+//  Errors and Definitions
+//==================================================================================================
+
+#[derive(Debug, PartialEq, Eq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub enum InterruptEdge {
+    HighToLow,
+    LowToHigh,
+    BothEdges,
+}
+
+#[derive(Debug, PartialEq, Eq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub enum InterruptLevel {
+    Low = 0,
+    High = 1,
+}
+
+#[derive(Debug, PartialEq, Eq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub enum PinState {
+    Low = 0,
+    High = 1,
+}
+
 //==================================================================================================
 // Input configuration
 //==================================================================================================
@@ -295,7 +321,7 @@ macro_rules! pin_id {
             impl Sealed for $Id {}
             impl PinId for $Id {
                 const DYN: DynPinId = DynPinId {
-                    group: Port::$Group,
+                    group: DynGroup::$Group,
                     num: $NUM,
                 };
             }
@@ -460,6 +486,11 @@ impl<I: PinId, M: PinMode> Pin<I, M> {
         self.inner.regs.write_pin(false)
     }
 
+    #[inline]
+    pub(crate) fn _toggle_with_toggle_reg(&mut self) {
+        self.inner.regs.toggle();
+    }
+
     #[inline]
     pub(crate) fn _is_low(&self) -> bool {
         !self.inner.regs.read_pin()
@@ -601,7 +632,7 @@ impl<I: PinId, C: OutputConfig> Pin<I, Output<C>> {
 
     #[inline]
     pub fn toggle_with_toggle_reg(&mut self) {
-        self.inner.regs.toggle()
+        self._toggle_with_toggle_reg()
     }
 
     #[deprecated(

va108xx-hal/src/gpio/reg.rs

@@ -1,6 +1,6 @@
-use super::dynpin::{self, DynPinId, DynPinMode};
+use super::dynpin::{self, DynGroup, DynPinId, DynPinMode};
-use super::pin::FilterType;
+use super::pin::{FilterType, InterruptEdge, InterruptLevel, PinState};
-use super::{InterruptEdge, InterruptLevel, IsMaskedError, PinState, Port};
+use super::IsMaskedError;
 use crate::clock::FilterClkSel;
 use va108xx::{ioconfig, porta};
 
@@ -146,15 +146,15 @@ pub(super) unsafe trait RegisterInterface {
     #[inline]
     fn port_reg(&self) -> &PortRegisterBlock {
         match self.id().group {
-            Port::A => unsafe { &(*Self::PORTA) },
+            DynGroup::A => unsafe { &(*Self::PORTA) },
-            Port::B => unsafe { &(*Self::PORTB) },
+            DynGroup::B => unsafe { &(*Self::PORTB) },
         }
     }
     fn iocfg_port(&self) -> &PortReg {
         let ioconfig = unsafe { va108xx::Ioconfig::ptr().as_ref().unwrap() };
         match self.id().group {
-            Port::A => ioconfig.porta(self.id().num as usize),
+            DynGroup::A => ioconfig.porta(self.id().num as usize),
-            Port::B => ioconfig.portb0(self.id().num as usize),
+            DynGroup::B => ioconfig.portb0(self.id().num as usize),
         }
     }
 

va108xx-hal/src/i2c.rs

@@ -36,6 +36,8 @@ pub struct InvalidTimingParamsError;
 #[derive(Debug, PartialEq, Eq, thiserror::Error)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub enum Error {
+    //#[error("Invalid timing parameters")]
+    //InvalidTimingParams,
     #[error("arbitration lost")]
     ArbitrationLost,
     #[error("nack address")]
@@ -80,7 +82,6 @@ impl embedded_hal::i2c::Error for Error {
 }
 
 #[derive(Debug, PartialEq, Copy, Clone)]
-#[cfg_attr(feature = "defmt", derive(defmt::Format))]
 enum I2cCmd {
     Start = 0b00,
     Stop = 0b10,
@@ -251,8 +252,6 @@ impl Default for MasterConfig {
 
 impl Sealed for MasterConfig {}
 
-#[derive(Debug)]
-#[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub struct SlaveConfig {
     pub tx_fe_mode: FifoEmptyMode,
     pub rx_fe_mode: FifoEmptyMode,
@@ -456,6 +455,13 @@ impl<I2c: Instance> I2cBase<I2c> {
     }
 }
 
+// Unique mode to use the loopback functionality
+// pub struct I2cLoopback<I2C> {
+//     i2c_base: I2cBase<I2C>,
+//     master_cfg: MasterConfig,
+//     slave_cfg: SlaveConfig,
+// }
+
 //==================================================================================================
 // I2C Master
 //==================================================================================================
@@ -667,6 +673,275 @@ impl<I2c: Instance, Addr> I2cMaster<I2c, Addr> {
     }
 }
 
+/*
+macro_rules! i2c_master {
+    ($($I2CX:path: ($i2cx:ident, $clk_enb:path),)+) => {
+        $(
+            impl<ADDR> I2cMaster<$I2CX, ADDR> {
+                pub fn $i2cx(
+                    i2c: $I2CX,
+                    cfg: MasterConfig,
+                    sys_clk: impl Into<Hertz> + Copy,
+                    speed_mode: I2cSpeed,
+                    sys_cfg: Option<&mut pac::Sysconfig>,
+                ) -> Self {
+                    I2cMaster {
+                        i2c_base: I2cBase::$i2cx(
+                            i2c,
+                            sys_clk,
+                            speed_mode,
+                            Some(&cfg),
+                            None,
+                            sys_cfg
+                        ),
+                        _addr: PhantomData,
+                    }
+                    .enable_master()
+                }
+
+                #[inline]
+                pub fn cancel_transfer(&self) {
+                    self.i2c_base
+                        .i2c
+                        .cmd()
+                        .write(|w| unsafe { w.bits(I2cCmd::Cancel as u32) });
+                }
+
+                #[inline]
+                pub fn clear_tx_fifo(&self) {
+                    self.i2c_base.i2c.fifo_clr().write(|w| w.txfifo().set_bit());
+                }
+
+                #[inline]
+                pub fn clear_rx_fifo(&self) {
+                    self.i2c_base.i2c.fifo_clr().write(|w| w.rxfifo().set_bit());
+                }
+
+                #[inline]
+                pub fn enable_master(self) -> Self {
+                    self.i2c_base.i2c.ctrl().modify(|_, w| w.enable().set_bit());
+                    self
+                }
+
+                #[inline]
+                pub fn disable_master(self) -> Self {
+                    self.i2c_base.i2c.ctrl().modify(|_, w| w.enable().clear_bit());
+                    self
+                }
+
+                #[inline(always)]
+                fn load_fifo(&self, word: u8) {
+                    self.i2c_base
+                        .i2c
+                        .data()
+                        .write(|w| unsafe { w.bits(word as u32) });
+                }
+
+                #[inline(always)]
+                fn read_fifo(&self) -> u8 {
+                    self.i2c_base.i2c.data().read().bits() as u8
+                }
+
+                fn error_handler_write(&mut self, init_cmd: &I2cCmd) {
+                    self.clear_tx_fifo();
+                    if *init_cmd == I2cCmd::Start {
+                        self.i2c_base.stop_cmd()
+                    }
+                }
+
+                fn write_base(
+                    &mut self,
+                    addr: I2cAddress,
+                    init_cmd: I2cCmd,
+                    bytes: impl IntoIterator<Item = u8>,
+                ) -> Result<(), Error> {
+                    let mut iter = bytes.into_iter();
+                    // Load address
+                    let (addr, addr_mode_bit) = I2cBase::<$I2CX>::unwrap_addr(addr);
+                    self.i2c_base.i2c.address().write(|w| unsafe {
+                        w.bits(I2cDirection::Send as u32 | (addr << 1) as u32 | addr_mode_bit)
+                    });
+
+                    self.i2c_base
+                        .i2c
+                        .cmd()
+                        .write(|w| unsafe { w.bits(init_cmd as u32) });
+                    let mut load_if_next_available = || {
+                        if let Some(next_byte) = iter.next() {
+                            self.load_fifo(next_byte);
+                        }
+                    };
+                    loop {
+                        let status_reader = self.i2c_base.i2c.status().read();
+                        if status_reader.arblost().bit_is_set() {
+                            self.error_handler_write(&init_cmd);
+                            return Err(Error::ArbitrationLost);
+                        } else if status_reader.nackaddr().bit_is_set() {
+                            self.error_handler_write(&init_cmd);
+                            return Err(Error::NackAddr);
+                        } else if status_reader.nackdata().bit_is_set() {
+                            self.error_handler_write(&init_cmd);
+                            return Err(Error::NackData);
+                        } else if status_reader.idle().bit_is_set() {
+                            return Ok(());
+                        } else {
+                            while !status_reader.txnfull().bit_is_set() {
+                                load_if_next_available();
+                            }
+                        }
+                    }
+                }
+
+                fn write_from_buffer(
+                    &mut self,
+                    init_cmd: I2cCmd,
+                    addr: I2cAddress,
+                    output: &[u8],
+                ) -> Result<(), Error> {
+                    let len = output.len();
+                    // It should theoretically possible to transfer larger data sizes by tracking
+                    // the number of sent words and setting it to 0x7fe as soon as only that many
+                    // bytes are remaining. However, large transfer like this are not common. This
+                    // feature will therefore not be supported for now.
+                    if len > 0x7fe {
+                        return Err(Error::DataTooLarge);
+                    }
+                    // Load number of words
+                    self.i2c_base
+                        .i2c
+                        .words()
+                        .write(|w| unsafe { w.bits(len as u32) });
+                    let mut bytes = output.iter();
+                    // FIFO has a depth of 16. We load slightly above the trigger level
+                    // but not all of it because the transaction might fail immediately
+                    const FILL_DEPTH: usize = 12;
+
+                    // load the FIFO
+                    for _ in 0..core::cmp::min(FILL_DEPTH, len) {
+                        self.load_fifo(*bytes.next().unwrap());
+                    }
+
+                    self.write_base(addr, init_cmd, output.iter().cloned())
+                }
+
+                fn read_internal(&mut self, addr: I2cAddress, buffer: &mut [u8]) -> Result<(), Error> {
+                    let len = buffer.len();
+                    // It should theoretically possible to transfer larger data sizes by tracking
+                    // the number of sent words and setting it to 0x7fe as soon as only that many
+                    // bytes are remaining. However, large transfer like this are not common. This
+                    // feature will therefore not be supported for now.
+                    if len > 0x7fe {
+                        return Err(Error::DataTooLarge);
+                    }
+                    // Clear the receive FIFO
+                    self.clear_rx_fifo();
+
+                    // Load number of words
+                    self.i2c_base
+                        .i2c
+                        .words()
+                        .write(|w| unsafe { w.bits(len as u32) });
+                    let (addr, addr_mode_bit) = match addr {
+                        I2cAddress::Regular(addr) => (addr as u16, 0 << 15),
+                        I2cAddress::TenBit(addr) => (addr, 1 << 15),
+                    };
+                    // Load address
+                    self.i2c_base.i2c.address().write(|w| unsafe {
+                        w.bits(I2cDirection::Read as u32 | (addr << 1) as u32 | addr_mode_bit)
+                    });
+
+                    let mut buf_iter = buffer.iter_mut();
+                    let mut read_bytes = 0;
+                    // Start receive transfer
+                    self.i2c_base
+                        .i2c
+                        .cmd()
+                        .write(|w| unsafe { w.bits(I2cCmd::StartWithStop as u32) });
+                    let mut read_if_next_available = || {
+                        if let Some(next_byte) = buf_iter.next() {
+                            *next_byte = self.read_fifo();
+                        }
+                    };
+                    loop {
+                        let status_reader = self.i2c_base.i2c.status().read();
+                        if status_reader.arblost().bit_is_set() {
+                            self.clear_rx_fifo();
+                            return Err(Error::ArbitrationLost);
+                        } else if status_reader.nackaddr().bit_is_set() {
+                            self.clear_rx_fifo();
+                            return Err(Error::NackAddr);
+                        } else if status_reader.idle().bit_is_set() {
+                            if read_bytes != len {
+                                return Err(Error::InsufficientDataReceived);
+                            }
+                            return Ok(());
+                        } else if status_reader.rxnempty().bit_is_set() {
+                            read_if_next_available();
+                            read_bytes += 1;
+                        }
+                    }
+                }
+            }
+
+            //======================================================================================
+            // Embedded HAL I2C implementations
+            //======================================================================================
+
+            impl embedded_hal::i2c::ErrorType for I2cMaster<$I2CX, SevenBitAddress> {
+                type Error = Error;
+            }
+            impl embedded_hal::i2c::I2c for I2cMaster<$I2CX, SevenBitAddress> {
+                fn transaction(
+                    &mut self,
+                    address: SevenBitAddress,
+                    operations: &mut [Operation<'_>],
+                ) -> Result<(), Self::Error> {
+                    for operation in operations {
+                        match operation {
+                            Operation::Read(buf) => self.read_internal(I2cAddress::Regular(address), buf)?,
+                            Operation::Write(buf) => self.write_from_buffer(
+                                I2cCmd::StartWithStop,
+                                I2cAddress::Regular(address),
+                                buf,
+                            )?,
+                        }
+                    }
+                    Ok(())
+                }
+            }
+
+            impl embedded_hal::i2c::ErrorType for I2cMaster<$I2CX, TenBitAddress> {
+                type Error = Error;
+            }
+            impl embedded_hal::i2c::I2c<TenBitAddress> for I2cMaster<$I2CX, TenBitAddress> {
+                fn transaction(
+                    &mut self,
+                    address: TenBitAddress,
+                    operations: &mut [Operation<'_>],
+                ) -> Result<(), Self::Error> {
+                    for operation in operations {
+                        match operation {
+                            Operation::Read(buf) => self.read_internal(I2cAddress::TenBit(address), buf)?,
+                            Operation::Write(buf) => self.write_from_buffer(
+                                I2cCmd::StartWithStop,
+                                I2cAddress::TenBit(address),
+                                buf,
+                            )?,
+                        }
+                    }
+                    Ok(())
+                }
+            }
+        )+
+    }
+}
+
+i2c_master!(
+    pac::I2ca: (i2ca, PeripheralClocks::I2c0),
+    pac::I2cb: (i2cb, PeripheralClocks::I2c1),
+);
+*/
+
 //======================================================================================
 // Embedded HAL I2C implementations
 //======================================================================================

va108xx-hal/src/lib.rs

@@ -31,7 +31,7 @@ pub enum PortSel {
     PortB,
 }
 
-#[derive(Debug, Copy, Clone, PartialEq, Eq)]
+#[derive(Copy, Clone, PartialEq, Eq)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub enum PeripheralSelect {
     PortA = 0,
@@ -54,7 +54,6 @@ pub enum PeripheralSelect {
 /// Cortex-M0 NVIC. Both are generally necessary for IRQs to work, but the user might want to
 /// perform those steps themselves.
 #[derive(Debug, PartialEq, Eq, Clone, Copy)]
-#[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub struct InterruptConfig {
     /// Interrupt target vector. Should always be set, might be required for disabling IRQs
     pub id: pac::Interrupt,

va108xx-hal/src/spi.rs

@@ -33,7 +33,6 @@ use embedded_hal::spi::{Mode, MODE_0};
 const FILL_DEPTH: usize = 12;
 
 pub const BMSTART_BMSTOP_MASK: u32 = 1 << 31;
-pub const BMSKIPDATA_MASK: u32 = 1 << 30;
 
 pub const DEFAULT_CLK_DIV: u16 = 2;
 
@@ -289,7 +288,6 @@ pub trait TransferConfigProvider {
 /// This struct contains all configuration parameter which are transfer specific
 /// and might change for transfers to different SPI slaves
 #[derive(Copy, Clone, Debug)]
-#[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub struct TransferConfigWithHwcs<HwCs> {
     pub hw_cs: Option<HwCs>,
     pub cfg: TransferConfig,
@@ -298,7 +296,6 @@ pub struct TransferConfigWithHwcs<HwCs> {
 /// Type erased variant of the transfer configuration. This is required to avoid generics in
 /// the SPI constructor.
 #[derive(Copy, Clone, Debug)]
-#[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub struct TransferConfig {
     pub clk_cfg: Option<SpiClkConfig>,
     pub mode: Option<Mode>,
@@ -386,8 +383,6 @@ impl<HwCs: HwCsProvider> TransferConfigProvider for TransferConfigWithHwcs<HwCs>
 }
 
 /// Configuration options for the whole SPI bus. See Programmer Guide p.92 for more details
-#[derive(Debug)]
-#[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub struct SpiConfig {
     clk: SpiClkConfig,
     // SPI mode configuration
@@ -537,7 +532,6 @@ pub struct Spi<SpiInstance, Pins, Word = u8> {
     pins: Pins,
 }
 
-#[inline(always)]
 pub fn mode_to_cpo_cph_bit(mode: embedded_hal::spi::Mode) -> (bool, bool) {
     match mode {
         embedded_hal::spi::MODE_0 => (false, false),
@@ -581,7 +575,6 @@ impl SpiClkConfig {
 }
 
 #[derive(Debug, thiserror::Error)]
-#[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub enum SpiClkConfigError {
     #[error("division by zero")]
     DivIsZero,

va108xx/CHANGELOG.md

@@ -8,10 +8,6 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ## [unreleased]
 
-## [v0.5.0] 2025-02-14
-
-- Re-generated PAC with `svd2rust` v0.35.0 and added optional `defmt` and `Debug` implementations
-
 ## [v0.4.0] 2025-02-12
 
 - Re-generated PAC with `svd2rust` v0.35.0

va108xx/Cargo.toml

@@ -1,6 +1,6 @@
 [package]
 name = "va108xx"
-version = "0.5.0"
+version = "0.4.0"
 authors = ["Robin Mueller <muellerr@irs.uni-stuttgart.de>"]
 edition = "2021"
 description = "PAC for the Vorago VA108xx family of microcontrollers"
@@ -13,7 +13,6 @@ categories = ["embedded", "no-std", "hardware-support"]
 [dependencies]
 cortex-m = "0.7"
 vcell = "0.1.3"
-defmt = { version = "0.3", optional = true }
 critical-section = { version = "1", optional = true }
 
 [dependencies.cortex-m-rt]
@@ -22,8 +21,6 @@ version = ">=0.6.15,<0.8"
 
 [features]
 rt = ["cortex-m-rt/device"]
-# Adds Debug implementation
-debug = []
 
 [package.metadata.docs.rs]
 all-features = true

va108xx/README.md

@@ -26,12 +26,6 @@ The `rt` feature is optional and recommended. It brings in support for `cortex-m
 For full details on the autgenerated API, please see the
 [svd2rust documentation](https://docs.rs/svd2rust/latest/svd2rust/#peripheral-api).
 
-## Optional Features
-
-- [`defmt`](https://defmt.ferrous-systems.com/): Add support for `defmt` by adding the
-  [`defmt::Format`](https://defmt.ferrous-systems.com/format) derive on many types.
-- `debug`: Add `Debug` derives for various structures
-
 ## Regenerating the PAC
 
 If you want to re-generate the PAC, for example if the register file `va416xx.svd` changes

va108xx/gen-helper.sh

@@ -30,7 +30,7 @@ fi
 
 svdtools patch svd/va108xx-patch.yml
 # See https://github.com/rust-embedded/svd2rust/issues/830 for required re-export.
-${svd2rust_bin} --reexport-interrupt --impl-defmt defmt --impl-debug-feature debug -i svd/va108xx.svd.patched
+${svd2rust_bin} --reexport-interrupt -i svd/va108xx.svd.patched
 
 result=$?
 if [ $result -ne 0 ]; then

va108xx/src/i2ca/address.rs

@@ -2,7 +2,6 @@
 pub type R = crate::R<AddressSpec>;
 #[doc = "Register `ADDRESS` writer"]
 pub type W = crate::W<AddressSpec>;
-#[cfg(feature = "debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         write!(f, "{}", self.bits())

va108xx/src/i2ca/clktolimit.rs

@@ -2,7 +2,6 @@
 pub type R = crate::R<ClktolimitSpec>;
 #[doc = "Register `CLKTOLIMIT` writer"]
 pub type W = crate::W<ClktolimitSpec>;
-#[cfg(feature = "debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         write!(f, "{}", self.bits())

va108xx/src/i2ca/cmd.rs

@@ -2,7 +2,6 @@
 pub type R = crate::R<CmdSpec>;
 #[doc = "Register `CMD` writer"]
 pub type W = crate::W<CmdSpec>;
-#[cfg(feature = "debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         write!(f, "{}", self.bits())

va108xx/src/i2ca/data.rs

@@ -2,7 +2,6 @@
 pub type R = crate::R<DataSpec>;
 #[doc = "Register `DATA` writer"]
 pub type W = crate::W<DataSpec>;
-#[cfg(feature = "debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         write!(f, "{}", self.bits())

va108xx/src/i2ca/perid.rs

@@ -1,6 +1,5 @@
 #[doc = "Register `PERID` reader"]
 pub type R = crate::R<PeridSpec>;
-#[cfg(feature = "debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         write!(f, "{}", self.bits())

va108xx/src/i2ca/rxcount.rs

@@ -1,6 +1,5 @@
 #[doc = "Register `RXCOUNT` reader"]
 pub type R = crate::R<RxcountSpec>;
-#[cfg(feature = "debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         write!(f, "{}", self.bits())

va108xx/src/i2ca/rxfifoirqtrg.rs

@@ -2,7 +2,6 @@
 pub type R = crate::R<RxfifoirqtrgSpec>;
 #[doc = "Register `RXFIFOIRQTRG` writer"]
 pub type W = crate::W<RxfifoirqtrgSpec>;
-#[cfg(feature = "debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         write!(f, "{}", self.bits())

va108xx/src/i2ca/s0_address.rs

@@ -2,7 +2,6 @@
 pub type R = crate::R<S0AddressSpec>;
 #[doc = "Register `S0_ADDRESS` writer"]
 pub type W = crate::W<S0AddressSpec>;
-#[cfg(feature = "debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         write!(f, "{}", self.bits())

va108xx/src/i2ca/s0_addressb.rs

@@ -2,7 +2,6 @@
 pub type R = crate::R<S0AddressbSpec>;
 #[doc = "Register `S0_ADDRESSB` writer"]
 pub type W = crate::W<S0AddressbSpec>;
-#[cfg(feature = "debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         write!(f, "{}", self.bits())

va108xx/src/i2ca/s0_addressmask.rs

@@ -2,7 +2,6 @@
 pub type R = crate::R<S0AddressmaskSpec>;
 #[doc = "Register `S0_ADDRESSMASK` writer"]
 pub type W = crate::W<S0AddressmaskSpec>;
-#[cfg(feature = "debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         write!(f, "{}", self.bits())

va108xx/src/i2ca/s0_addressmaskb.rs

@@ -2,7 +2,6 @@
 pub type R = crate::R<S0AddressmaskbSpec>;
 #[doc = "Register `S0_ADDRESSMASKB` writer"]
 pub type W = crate::W<S0AddressmaskbSpec>;
-#[cfg(feature = "debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         write!(f, "{}", self.bits())

va108xx/src/i2ca/s0_data.rs

@@ -2,7 +2,6 @@
 pub type R = crate::R<S0DataSpec>;
 #[doc = "Register `S0_DATA` writer"]
 pub type W = crate::W<S0DataSpec>;
-#[cfg(feature = "debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         write!(f, "{}", self.bits())

va108xx/src/i2ca/s0_lastaddress.rs

@@ -1,6 +1,5 @@
 #[doc = "Register `S0_LASTADDRESS` reader"]
 pub type R = crate::R<S0LastaddressSpec>;
-#[cfg(feature = "debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         write!(f, "{}", self.bits())

va108xx/src/i2ca/s0_maxwords.rs

@@ -2,7 +2,6 @@
 pub type R = crate::R<S0MaxwordsSpec>;
 #[doc = "Register `S0_MAXWORDS` writer"]
 pub type W = crate::W<S0MaxwordsSpec>;
-#[cfg(feature = "debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         write!(f, "{}", self.bits())

va108xx/src/i2ca/s0_rxcount.rs

@@ -1,6 +1,5 @@
 #[doc = "Register `S0_RXCOUNT` reader"]
 pub type R = crate::R<S0RxcountSpec>;
-#[cfg(feature = "debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         write!(f, "{}", self.bits())

va108xx/src/i2ca/s0_rxfifoirqtrg.rs

@@ -2,7 +2,6 @@
 pub type R = crate::R<S0RxfifoirqtrgSpec>;
 #[doc = "Register `S0_RXFIFOIRQTRG` writer"]
 pub type W = crate::W<S0RxfifoirqtrgSpec>;
-#[cfg(feature = "debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         write!(f, "{}", self.bits())

va108xx/src/i2ca/s0_state.rs

@@ -1,6 +1,5 @@
 #[doc = "Register `S0_STATE` reader"]
 pub type R = crate::R<S0StateSpec>;
-#[cfg(feature = "debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         write!(f, "{}", self.bits())

va108xx/src/i2ca/s0_txcount.rs

@@ -1,6 +1,5 @@
 #[doc = "Register `S0_TXCOUNT` reader"]
 pub type R = crate::R<S0TxcountSpec>;
-#[cfg(feature = "debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         write!(f, "{}", self.bits())

va108xx/src/i2ca/s0_txfifoirqtrg.rs

@@ -2,7 +2,6 @@
 pub type R = crate::R<S0TxfifoirqtrgSpec>;
 #[doc = "Register `S0_TXFIFOIRQTRG` writer"]
 pub type W = crate::W<S0TxfifoirqtrgSpec>;
-#[cfg(feature = "debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         write!(f, "{}", self.bits())

va108xx/src/i2ca/state.rs

@@ -1,6 +1,5 @@
 #[doc = "Register `STATE` reader"]
 pub type R = crate::R<StateSpec>;
-#[cfg(feature = "debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         write!(f, "{}", self.bits())

va108xx/src/i2ca/tmconfig.rs

@@ -2,7 +2,6 @@
 pub type R = crate::R<TmconfigSpec>;
 #[doc = "Register `TMCONFIG` writer"]
 pub type W = crate::W<TmconfigSpec>;
-#[cfg(feature = "debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         write!(f, "{}", self.bits())

va108xx/src/i2ca/txcount.rs

@@ -1,6 +1,5 @@
 #[doc = "Register `TXCOUNT` reader"]
 pub type R = crate::R<TxcountSpec>;
-#[cfg(feature = "debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         write!(f, "{}", self.bits())

va108xx/src/i2ca/txfifoirqtrg.rs

@@ -2,7 +2,6 @@
 pub type R = crate::R<TxfifoirqtrgSpec>;
 #[doc = "Register `TXFIFOIRQTRG` writer"]
 pub type W = crate::W<TxfifoirqtrgSpec>;
-#[cfg(feature = "debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         write!(f, "{}", self.bits())

va108xx/src/i2ca/words.rs

@@ -2,7 +2,6 @@
 pub type R = crate::R<WordsSpec>;
 #[doc = "Register `WORDS` writer"]
 pub type W = crate::W<WordsSpec>;
-#[cfg(feature = "debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         write!(f, "{}", self.bits())

va108xx/src/ioconfig/perid.rs

@@ -1,6 +1,5 @@
 #[doc = "Register `PERID` reader"]
 pub type R = crate::R<PeridSpec>;
-#[cfg(feature = "debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         write!(f, "{}", self.bits())

va108xx/src/ioconfig/porta.rs

@@ -3,7 +3,6 @@ pub type R = crate::R<PortaSpec>;
 #[doc = "Register `PORTA[%s]` writer"]
 pub type W = crate::W<PortaSpec>;
 #[doc = "Input Filter Selectoin\n\nValue on reset: 0"]
-#[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[derive(Clone, Copy, Debug, PartialEq, Eq)]
 #[repr(u8)]
 pub enum Flttype {

va108xx/src/irqsel/int_ram_sbe.rs

@@ -2,7 +2,6 @@
 pub type R = crate::R<IntRamSbeSpec>;
 #[doc = "Register `INT_RAM_SBE` writer"]
 pub type W = crate::W<IntRamSbeSpec>;
-#[cfg(feature = "debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         write!(f, "{}", self.bits())

va108xx/src/irqsel/perid.rs

@@ -1,6 +1,5 @@
 #[doc = "Register `PERID` reader"]
 pub type R = crate::R<PeridSpec>;
-#[cfg(feature = "debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         write!(f, "{}", self.bits())

va108xx/src/lib.rs

@@ -97,7 +97,6 @@ pub static __INTERRUPTS: [Vector; 32] = [
     Vector { _handler: OC31 },
 ];
 #[doc = r"Enumeration of all the interrupts."]
-#[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[derive(Copy, Clone, Debug, PartialEq, Eq)]
 #[repr(u16)]
 pub enum Interrupt {

va108xx/src/porta/datain.rs

@@ -1,6 +1,5 @@
 #[doc = "Register `DATAIN` reader"]
 pub type R = crate::R<DatainSpec>;
-#[cfg(feature = "debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         write!(f, "{}", self.bits())

va108xx/src/porta/datainbyte.rs

@@ -1,6 +1,5 @@
 #[doc = "Register `DATAINBYTE[%s]` reader"]
 pub type R = crate::R<DatainbyteSpec>;
-#[cfg(feature = "debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         write!(f, "{}", self.bits())

va108xx/src/porta/datamask.rs

@@ -2,7 +2,6 @@
 pub type R = crate::R<DatamaskSpec>;
 #[doc = "Register `DATAMASK` writer"]
 pub type W = crate::W<DatamaskSpec>;
-#[cfg(feature = "debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         write!(f, "{}", self.bits())

va108xx/src/porta/datamaskbyte.rs

@@ -2,7 +2,6 @@
 pub type R = crate::R<DatamaskbyteSpec>;
 #[doc = "Register `DATAMASKBYTE[%s]` writer"]
 pub type W = crate::W<DatamaskbyteSpec>;
-#[cfg(feature = "debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         write!(f, "{}", self.bits())

va108xx/src/porta/dataout.rs

@@ -1,6 +1,5 @@
 #[doc = "Register `DATAOUT` writer"]
 pub type W = crate::W<DataoutSpec>;
-#[cfg(feature = "debug")]
 impl core::fmt::Debug for crate::generic::Reg<DataoutSpec> {
     fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
         write!(f, "(not readable)")

va108xx/src/porta/dataoutbyte.rs

@@ -1,6 +1,5 @@
 #[doc = "Register `DATAOUTBYTE[%s]` writer"]
 pub type W = crate::W<DataoutbyteSpec>;
-#[cfg(feature = "debug")]
 impl core::fmt::Debug for crate::generic::Reg<DataoutbyteSpec> {
     fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
         write!(f, "(not readable)")

va108xx/src/porta/edge_status.rs

@@ -2,7 +2,6 @@
 pub type R = crate::R<EdgeStatusSpec>;
 #[doc = "Register `EDGE_STATUS` writer"]
 pub type W = crate::W<EdgeStatusSpec>;
-#[cfg(feature = "debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         write!(f, "{}", self.bits())

va108xx/src/porta/irq_edge.rs

@@ -2,7 +2,6 @@
 pub type R = crate::R<IrqEdgeSpec>;
 #[doc = "Register `IRQ_EDGE` writer"]
 pub type W = crate::W<IrqEdgeSpec>;
-#[cfg(feature = "debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         write!(f, "{}", self.bits())

va108xx/src/porta/irq_enb.rs

@@ -2,7 +2,6 @@
 pub type R = crate::R<IrqEnbSpec>;
 #[doc = "Register `IRQ_ENB` writer"]
 pub type W = crate::W<IrqEnbSpec>;
-#[cfg(feature = "debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         write!(f, "{}", self.bits())

va108xx/src/porta/irq_end.rs

@@ -1,6 +1,5 @@
 #[doc = "Register `IRQ_END` reader"]
 pub type R = crate::R<IrqEndSpec>;
-#[cfg(feature = "debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         write!(f, "{}", self.bits())

va108xx/src/porta/irq_evt.rs

@@ -2,7 +2,6 @@
 pub type R = crate::R<IrqEvtSpec>;
 #[doc = "Register `IRQ_EVT` writer"]
 pub type W = crate::W<IrqEvtSpec>;
-#[cfg(feature = "debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         write!(f, "{}", self.bits())

va108xx/src/porta/irq_raw.rs

@@ -1,6 +1,5 @@
 #[doc = "Register `IRQ_RAW` reader"]
 pub type R = crate::R<IrqRawSpec>;
-#[cfg(feature = "debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         write!(f, "{}", self.bits())

va108xx/src/porta/irq_sen.rs

@@ -2,7 +2,6 @@
 pub type R = crate::R<IrqSenSpec>;
 #[doc = "Register `IRQ_SEN` writer"]
 pub type W = crate::W<IrqSenSpec>;
-#[cfg(feature = "debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         write!(f, "{}", self.bits())

va108xx/src/porta/perid.rs

@@ -1,6 +1,5 @@
 #[doc = "Register `PERID` reader"]
 pub type R = crate::R<PeridSpec>;
-#[cfg(feature = "debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         write!(f, "{}", self.bits())

va108xx/src/spia/clkprescale.rs

@@ -2,7 +2,6 @@
 pub type R = crate::R<ClkprescaleSpec>;
 #[doc = "Register `CLKPRESCALE` writer"]
 pub type W = crate::W<ClkprescaleSpec>;
-#[cfg(feature = "debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         write!(f, "{}", self.bits())

va108xx/src/spia/data.rs

@@ -2,7 +2,6 @@
 pub type R = crate::R<DataSpec>;
 #[doc = "Register `DATA` writer"]
 pub type W = crate::W<DataSpec>;
-#[cfg(feature = "debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         write!(f, "{}", self.bits())

va108xx/src/spia/perid.rs

@@ -1,6 +1,5 @@
 #[doc = "Register `PERID` reader"]
 pub type R = crate::R<PeridSpec>;
-#[cfg(feature = "debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         write!(f, "{}", self.bits())

va108xx/src/spia/rxfifoirqtrg.rs

@@ -2,7 +2,6 @@
 pub type R = crate::R<RxfifoirqtrgSpec>;
 #[doc = "Register `RXFIFOIRQTRG` writer"]
 pub type W = crate::W<RxfifoirqtrgSpec>;
-#[cfg(feature = "debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         write!(f, "{}", self.bits())

va108xx/src/spia/state.rs

@@ -1,6 +1,5 @@
 #[doc = "Register `STATE` reader"]
 pub type R = crate::R<StateSpec>;
-#[cfg(feature = "debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         write!(f, "{}", self.bits())

va108xx/src/spia/txfifoirqtrg.rs

@@ -2,7 +2,6 @@
 pub type R = crate::R<TxfifoirqtrgSpec>;
 #[doc = "Register `TXFIFOIRQTRG` writer"]
 pub type W = crate::W<TxfifoirqtrgSpec>;
-#[cfg(feature = "debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         write!(f, "{}", self.bits())

va108xx/src/sysconfig/ef_config.rs

@@ -1,6 +1,5 @@
 #[doc = "Register `EF_CONFIG` reader"]
 pub type R = crate::R<EfConfigSpec>;
-#[cfg(feature = "debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         write!(f, "{}", self.bits())

va108xx/src/sysconfig/ef_id.rs

@@ -1,6 +1,5 @@
 #[doc = "Register `EF_ID` reader"]
 pub type R = crate::R<EfIdSpec>;
-#[cfg(feature = "debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         write!(f, "{}", self.bits())

va108xx/src/sysconfig/ioconfig_clkdiv.rs

@@ -2,7 +2,6 @@
 pub type R = crate::R<IoconfigClkdivSpec>;
 #[doc = "Register `IOCONFIG_CLKDIV%s` writer"]
 pub type W = crate::W<IoconfigClkdivSpec>;
-#[cfg(feature = "debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         write!(f, "{}", self.bits())

va108xx/src/sysconfig/ioconfig_clkdiv0.rs

@@ -1,6 +1,5 @@
 #[doc = "Register `IOCONFIG_CLKDIV0` reader"]
 pub type R = crate::R<IoconfigClkdiv0Spec>;
-#[cfg(feature = "debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         write!(f, "{}", self.bits())

va108xx/src/sysconfig/perid.rs

@@ -1,6 +1,5 @@
 #[doc = "Register `PERID` reader"]
 pub type R = crate::R<PeridSpec>;
-#[cfg(feature = "debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         write!(f, "{}", self.bits())

va108xx/src/sysconfig/procid.rs

@@ -1,6 +1,5 @@
 #[doc = "Register `PROCID` reader"]
 pub type R = crate::R<ProcidSpec>;
-#[cfg(feature = "debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         write!(f, "{}", self.bits())

va108xx/src/sysconfig/ram_sbe.rs

@@ -2,7 +2,6 @@
 pub type R = crate::R<RamSbeSpec>;
 #[doc = "Register `RAM_SBE` writer"]
 pub type W = crate::W<RamSbeSpec>;
-#[cfg(feature = "debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         write!(f, "{}", self.bits())

va108xx/src/sysconfig/refresh_config.rs

@@ -2,7 +2,6 @@
 pub type R = crate::R<RefreshConfigSpec>;
 #[doc = "Register `REFRESH_CONFIG` writer"]
 pub type W = crate::W<RefreshConfigSpec>;
-#[cfg(feature = "debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         write!(f, "{}", self.bits())

va108xx/src/sysconfig/rom_retries.rs

@@ -1,6 +1,5 @@
 #[doc = "Register `ROM_RETRIES` reader"]
 pub type R = crate::R<RomRetriesSpec>;
-#[cfg(feature = "debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         write!(f, "{}", self.bits())

va108xx/src/sysconfig/tim_clk_enable.rs

@@ -2,7 +2,6 @@
 pub type R = crate::R<TimClkEnableSpec>;
 #[doc = "Register `TIM_CLK_ENABLE` writer"]
 pub type W = crate::W<TimClkEnableSpec>;
-#[cfg(feature = "debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         write!(f, "{}", self.bits())

va108xx/src/sysconfig/tim_reset.rs

@@ -2,7 +2,6 @@
 pub type R = crate::R<TimResetSpec>;
 #[doc = "Register `TIM_RESET` writer"]
 pub type W = crate::W<TimResetSpec>;
-#[cfg(feature = "debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         write!(f, "{}", self.bits())

va108xx/src/tim0/cnt_value.rs

@@ -2,7 +2,6 @@
 pub type R = crate::R<CntValueSpec>;
 #[doc = "Register `CNT_VALUE` writer"]
 pub type W = crate::W<CntValueSpec>;
-#[cfg(feature = "debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         write!(f, "{}", self.bits())

va108xx/src/tim0/ctrl.rs

@@ -21,7 +21,6 @@ pub type IrqEnbR = crate::BitReader;
 #[doc = "Field `IRQ_ENB` writer - Interrupt Enable"]
 pub type IrqEnbW<'a, REG> = crate::BitWriter<'a, REG>;
 #[doc = "Counter Status Selection\n\nValue on reset: 0"]
-#[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[derive(Clone, Copy, Debug, PartialEq, Eq)]
 #[repr(u8)]
 pub enum StatusSel {

va108xx/src/tim0/perid.rs

@@ -1,6 +1,5 @@
 #[doc = "Register `PERID` reader"]
 pub type R = crate::R<PeridSpec>;
-#[cfg(feature = "debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         write!(f, "{}", self.bits())

va108xx/src/tim0/pwm_value.rs

@@ -2,7 +2,6 @@
 pub type R = crate::R<PwmValueSpec>;
 #[doc = "Register `PWM_VALUE` writer"]
 pub type W = crate::W<PwmValueSpec>;
-#[cfg(feature = "debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         write!(f, "{}", self.bits())

va108xx/src/tim0/pwma_value.rs

@@ -2,7 +2,6 @@
 pub type R = crate::R<PwmaValueSpec>;
 #[doc = "Register `PWMA_VALUE` writer"]
 pub type W = crate::W<PwmaValueSpec>;
-#[cfg(feature = "debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         write!(f, "{}", self.bits())

va108xx/src/tim0/pwmb_value.rs

@@ -2,7 +2,6 @@
 pub type R = crate::R<PwmbValueSpec>;
 #[doc = "Register `PWMB_VALUE` writer"]
 pub type W = crate::W<PwmbValueSpec>;
-#[cfg(feature = "debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         write!(f, "{}", self.bits())

va108xx/src/tim0/rst_value.rs

@@ -2,7 +2,6 @@
 pub type R = crate::R<RstValueSpec>;
 #[doc = "Register `RST_VALUE` writer"]
 pub type W = crate::W<RstValueSpec>;
-#[cfg(feature = "debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         write!(f, "{}", self.bits())

va108xx/src/uarta/addr9.rs

@@ -2,7 +2,6 @@
 pub type R = crate::R<Addr9Spec>;
 #[doc = "Register `ADDR9` writer"]
 pub type W = crate::W<Addr9Spec>;
-#[cfg(feature = "debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         write!(f, "{}", self.bits())

va108xx/src/uarta/addr9mask.rs

@@ -2,7 +2,6 @@
 pub type R = crate::R<Addr9maskSpec>;
 #[doc = "Register `ADDR9MASK` writer"]
 pub type W = crate::W<Addr9maskSpec>;
-#[cfg(feature = "debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         write!(f, "{}", self.bits())

va108xx/src/uarta/data.rs

@@ -2,7 +2,6 @@
 pub type R = crate::R<DataSpec>;
 #[doc = "Register `DATA` writer"]
 pub type W = crate::W<DataSpec>;
-#[cfg(feature = "debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         write!(f, "{}", self.bits())

va108xx/src/uarta/perid.rs

@@ -1,6 +1,5 @@
 #[doc = "Register `PERID` reader"]
 pub type R = crate::R<PeridSpec>;
-#[cfg(feature = "debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         write!(f, "{}", self.bits())

va108xx/src/uarta/rxfifoirqtrg.rs

@@ -2,7 +2,6 @@
 pub type R = crate::R<RxfifoirqtrgSpec>;
 #[doc = "Register `RXFIFOIRQTRG` writer"]
 pub type W = crate::W<RxfifoirqtrgSpec>;
-#[cfg(feature = "debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         write!(f, "{}", self.bits())

va108xx/src/uarta/rxfifortstrg.rs

@@ -2,7 +2,6 @@
 pub type R = crate::R<RxfifortstrgSpec>;
 #[doc = "Register `RXFIFORTSTRG` writer"]
 pub type W = crate::W<RxfifortstrgSpec>;
-#[cfg(feature = "debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         write!(f, "{}", self.bits())

va108xx/src/uarta/state.rs

@@ -1,6 +1,5 @@
 #[doc = "Register `STATE` reader"]
 pub type R = crate::R<StateSpec>;
-#[cfg(feature = "debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         write!(f, "{}", self.bits())

va108xx/src/uarta/txbreak.rs

@@ -1,6 +1,5 @@
 #[doc = "Register `TXBREAK` writer"]
 pub type W = crate::W<TxbreakSpec>;
-#[cfg(feature = "debug")]
 impl core::fmt::Debug for crate::generic::Reg<TxbreakSpec> {
     fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
         write!(f, "(not readable)")

va108xx/src/uarta/txfifoirqtrg.rs

@@ -2,7 +2,6 @@
 pub type R = crate::R<TxfifoirqtrgSpec>;
 #[doc = "Register `TXFIFOIRQTRG` writer"]
 pub type W = crate::W<TxfifoirqtrgSpec>;
-#[cfg(feature = "debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         write!(f, "{}", self.bits())

va108xx/src/utility/perid.rs

@@ -1,6 +1,5 @@
 #[doc = "Register `PERID` reader"]
 pub type R = crate::R<PeridSpec>;
-#[cfg(feature = "debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         write!(f, "{}", self.bits())

va108xx/src/utility/synd_check_32_52_data.rs

@@ -1,6 +1,5 @@
 #[doc = "Register `SYND_CHECK_32_52_DATA` reader"]
 pub type R = crate::R<SyndCheck32_52DataSpec>;
-#[cfg(feature = "debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         write!(f, "{}", self.bits())

va108xx/src/utility/synd_check_32_52_synd.rs

@@ -1,6 +1,5 @@
 #[doc = "Register `SYND_CHECK_32_52_SYND` reader"]
 pub type R = crate::R<SyndCheck32_52SyndSpec>;
-#[cfg(feature = "debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         write!(f, "{}", self.bits())

va108xx/src/utility/synd_check_32_data.rs

@@ -1,6 +1,5 @@
 #[doc = "Register `SYND_CHECK_32_DATA` reader"]
 pub type R = crate::R<SyndCheck32DataSpec>;
-#[cfg(feature = "debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         write!(f, "{}", self.bits())

va108xx/src/utility/synd_check_32_synd.rs

@@ -1,6 +1,5 @@
 #[doc = "Register `SYND_CHECK_32_SYND` reader"]
 pub type R = crate::R<SyndCheck32SyndSpec>;
-#[cfg(feature = "debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         write!(f, "{}", self.bits())