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@ -24,8 +24,7 @@ use va108xx_hal::{
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pub enum ExampleSelect {
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pub enum ExampleSelect {
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// Enter loopback mode. It is not necessary to tie MOSI/MISO together for this
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// Enter loopback mode. It is not necessary to tie MOSI/MISO together for this
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Loopback,
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Loopback,
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// Send a test buffer and print everything received
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MosiMisoTiedTogetherManually,
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TestBuffer,
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}
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}
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#[derive(PartialEq, Debug)]
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#[derive(PartialEq, Debug)]
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@ -152,92 +151,64 @@ fn main() -> ! {
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match SPI_BUS_SEL {
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match SPI_BUS_SEL {
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SpiBusSelect::SpiAPortA | SpiBusSelect::SpiAPortB => {
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SpiBusSelect::SpiAPortA | SpiBusSelect::SpiAPortB => {
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if let Some(ref mut spi) = *spia_ref.borrow_mut() {
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if let Some(ref mut spi) = *spia_ref.borrow_mut() {
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if EXAMPLE_SEL == ExampleSelect::Loopback {
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// Can't really verify correct reply here.
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// Can't really verify correct reply here.
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spi.write(&[0x42]).expect("write failed");
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spi.write(&[0x42]).expect("write failed");
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// Because of the loopback mode, we should get back the fill word here.
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// Because of the loopback mode, we should get back the fill word here.
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spi.read(&mut reply_buf[0..1]).unwrap();
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spi.read(&mut reply_buf[0..1]).unwrap();
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assert_eq!(reply_buf[0], FILL_WORD);
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assert_eq!(reply_buf[0], FILL_WORD);
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delay.delay_ms(500_u32);
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delay.delay_ms(500_u32);
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let tx_buf: [u8; 3] = [0x01, 0x02, 0x03];
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let tx_buf: [u8; 3] = [0x01, 0x02, 0x03];
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spi.transfer(&mut reply_buf[0..3], &tx_buf).unwrap();
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spi.transfer(&mut reply_buf[0..3], &tx_buf).unwrap();
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assert_eq!(tx_buf, reply_buf[0..3]);
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assert_eq!(tx_buf, reply_buf[0..3]);
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rprintln!(
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rprintln!(
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"Received reply: {}, {}, {}",
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"Received reply: {}, {}, {}",
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reply_buf[0],
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reply_buf[0],
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reply_buf[1],
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reply_buf[1],
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reply_buf[2]
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reply_buf[2]
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);
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);
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delay.delay_ms(500_u32);
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delay.delay_ms(500_u32);
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let mut tx_rx_buf: [u8; 3] = [0x03, 0x02, 0x01];
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let mut tx_rx_buf: [u8; 3] = [0x03, 0x02, 0x01];
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spi.transfer_in_place(&mut tx_rx_buf).unwrap();
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spi.transfer_in_place(&mut tx_rx_buf).unwrap();
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rprintln!(
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rprintln!(
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"Received reply: {}, {}, {}",
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"Received reply: {}, {}, {}",
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tx_rx_buf[0],
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tx_rx_buf[0],
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tx_rx_buf[1],
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tx_rx_buf[1],
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tx_rx_buf[2]
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tx_rx_buf[2]
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);
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);
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assert_eq!(&tx_rx_buf[0..3], &[0x03, 0x02, 0x01]);
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assert_eq!(&tx_rx_buf[0..3], &[0x03, 0x02, 0x01]);
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} else {
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let send_buf: [u8; 3] = [0x01, 0x02, 0x03];
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spi.transfer(&mut reply_buf[0..3], &send_buf).unwrap();
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rprintln!(
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"Received reply: {}, {}, {}",
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reply_buf[0],
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reply_buf[1],
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reply_buf[2]
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);
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delay.delay_ms(1000_u32);
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}
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}
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}
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}
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}
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SpiBusSelect::SpiBPortB => {
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SpiBusSelect::SpiBPortB => {
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if let Some(ref mut spi) = *spib_ref.borrow_mut() {
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if let Some(ref mut spi) = *spib_ref.borrow_mut() {
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if EXAMPLE_SEL == ExampleSelect::Loopback {
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// Can't really verify correct reply here.
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// Can't really verify correct reply here.
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spi.write(&[0x42]).expect("write failed");
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spi.write(&[0x42]).expect("write failed");
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// Because of the loopback mode, we should get back the fill word here.
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// Need small delay.. otherwise we will read back the sent byte (which we don't want here).
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spi.read(&mut reply_buf[0..1]).unwrap();
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// The write function will return as soon as all bytes were shifted out, ignoring the
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assert_eq!(reply_buf[0], FILL_WORD);
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// reply bytes.
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delay.delay_ms(500_u32);
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delay.delay_us(50);
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// Because of the loopback mode, we should get back the fill word here.
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spi.read(&mut reply_buf[0..1]).unwrap();
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assert_eq!(reply_buf[0], FILL_WORD);
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delay.delay_ms(500_u32);
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let tx_buf: [u8; 3] = [0x01, 0x02, 0x03];
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let tx_buf: [u8; 3] = [0x01, 0x02, 0x03];
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spi.transfer(&mut reply_buf[0..3], &tx_buf).unwrap();
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spi.transfer(&mut reply_buf[0..3], &tx_buf).unwrap();
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assert_eq!(tx_buf, reply_buf[0..3]);
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assert_eq!(tx_buf, reply_buf[0..3]);
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rprintln!(
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rprintln!(
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"Received reply: {}, {}, {}",
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"Received reply: {}, {}, {}",
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reply_buf[0],
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reply_buf[0],
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reply_buf[1],
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reply_buf[1],
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reply_buf[2]
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reply_buf[2]
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);
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);
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delay.delay_ms(500_u32);
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delay.delay_ms(500_u32);
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let mut tx_rx_buf: [u8; 3] = [0x03, 0x02, 0x01];
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let mut tx_rx_buf: [u8; 3] = [0x03, 0x02, 0x01];
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spi.transfer_in_place(&mut tx_rx_buf).unwrap();
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spi.transfer_in_place(&mut tx_rx_buf).unwrap();
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rprintln!(
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rprintln!(
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"Received reply: {}, {}, {}",
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"Received reply: {}, {}, {}",
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tx_rx_buf[0],
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tx_rx_buf[0],
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tx_rx_buf[1],
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tx_rx_buf[1],
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tx_rx_buf[2]
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tx_rx_buf[2]
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);
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);
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assert_eq!(&tx_rx_buf[0..3], &[0x03, 0x02, 0x01]);
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assert_eq!(&tx_rx_buf[0..3], &[0x03, 0x02, 0x01]);
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} else {
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let send_buf: [u8; 3] = [0x01, 0x02, 0x03];
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spi.transfer(&mut reply_buf[0..3], &send_buf).unwrap();
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rprintln!(
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"Received reply: {}, {}, {}",
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reply_buf[0],
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reply_buf[1],
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reply_buf[2]
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);
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delay.delay_ms(1000_u32);
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}
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}
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}
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}
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}
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}
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}
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@ -16,6 +16,10 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
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only expects a configuration structure and the transfer configuration needs to be applied in a
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only expects a configuration structure and the transfer configuration needs to be applied in a
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separate step.
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separate step.
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## Fixes
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- Fixes for SPI peripheral: Flush implementation was incorrect and should now flush properly.
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## [v0.7.0] 2024-07-04
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## [v0.7.0] 2024-07-04
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- Replace `uarta` and `uartb` `Uart` constructors by `new` constructor
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- Replace `uarta` and `uartb` `Uart` constructors by `new` constructor
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