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Author SHA1 Message Date
cd4fec485e update package
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Rust/va108xx-rs/pipeline/pr-main This commit looks good
- Add embassy example
- improve timer API
- restructure examples
- restructure and improve SPI
- Add REB1 M95M01 NVM module
2024-09-20 10:47:08 +02:00
2 changed files with 55 additions and 80 deletions

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@ -24,8 +24,7 @@ use va108xx_hal::{
pub enum ExampleSelect { pub enum ExampleSelect {
// Enter loopback mode. It is not necessary to tie MOSI/MISO together for this // Enter loopback mode. It is not necessary to tie MOSI/MISO together for this
Loopback, Loopback,
// Send a test buffer and print everything received MosiMisoTiedTogetherManually,
TestBuffer,
} }
#[derive(PartialEq, Debug)] #[derive(PartialEq, Debug)]
@ -152,92 +151,64 @@ fn main() -> ! {
match SPI_BUS_SEL { match SPI_BUS_SEL {
SpiBusSelect::SpiAPortA | SpiBusSelect::SpiAPortB => { SpiBusSelect::SpiAPortA | SpiBusSelect::SpiAPortB => {
if let Some(ref mut spi) = *spia_ref.borrow_mut() { if let Some(ref mut spi) = *spia_ref.borrow_mut() {
if EXAMPLE_SEL == ExampleSelect::Loopback { // Can't really verify correct reply here.
// Can't really verify correct reply here. spi.write(&[0x42]).expect("write failed");
spi.write(&[0x42]).expect("write failed"); // Because of the loopback mode, we should get back the fill word here.
// Because of the loopback mode, we should get back the fill word here. spi.read(&mut reply_buf[0..1]).unwrap();
spi.read(&mut reply_buf[0..1]).unwrap(); assert_eq!(reply_buf[0], FILL_WORD);
assert_eq!(reply_buf[0], FILL_WORD); delay.delay_ms(500_u32);
delay.delay_ms(500_u32);
let tx_buf: [u8; 3] = [0x01, 0x02, 0x03]; let tx_buf: [u8; 3] = [0x01, 0x02, 0x03];
spi.transfer(&mut reply_buf[0..3], &tx_buf).unwrap(); spi.transfer(&mut reply_buf[0..3], &tx_buf).unwrap();
assert_eq!(tx_buf, reply_buf[0..3]); assert_eq!(tx_buf, reply_buf[0..3]);
rprintln!( rprintln!(
"Received reply: {}, {}, {}", "Received reply: {}, {}, {}",
reply_buf[0], reply_buf[0],
reply_buf[1], reply_buf[1],
reply_buf[2] reply_buf[2]
); );
delay.delay_ms(500_u32); delay.delay_ms(500_u32);
let mut tx_rx_buf: [u8; 3] = [0x03, 0x02, 0x01]; let mut tx_rx_buf: [u8; 3] = [0x03, 0x02, 0x01];
spi.transfer_in_place(&mut tx_rx_buf).unwrap(); spi.transfer_in_place(&mut tx_rx_buf).unwrap();
rprintln!( rprintln!(
"Received reply: {}, {}, {}", "Received reply: {}, {}, {}",
tx_rx_buf[0], tx_rx_buf[0],
tx_rx_buf[1], tx_rx_buf[1],
tx_rx_buf[2] tx_rx_buf[2]
); );
assert_eq!(&tx_rx_buf[0..3], &[0x03, 0x02, 0x01]); assert_eq!(&tx_rx_buf[0..3], &[0x03, 0x02, 0x01]);
} else {
let send_buf: [u8; 3] = [0x01, 0x02, 0x03];
spi.transfer(&mut reply_buf[0..3], &send_buf).unwrap();
rprintln!(
"Received reply: {}, {}, {}",
reply_buf[0],
reply_buf[1],
reply_buf[2]
);
delay.delay_ms(1000_u32);
}
} }
} }
SpiBusSelect::SpiBPortB => { SpiBusSelect::SpiBPortB => {
if let Some(ref mut spi) = *spib_ref.borrow_mut() { if let Some(ref mut spi) = *spib_ref.borrow_mut() {
if EXAMPLE_SEL == ExampleSelect::Loopback { // Can't really verify correct reply here.
// Can't really verify correct reply here. spi.write(&[0x42]).expect("write failed");
spi.write(&[0x42]).expect("write failed"); // Because of the loopback mode, we should get back the fill word here.
// Need small delay.. otherwise we will read back the sent byte (which we don't want here). spi.read(&mut reply_buf[0..1]).unwrap();
// The write function will return as soon as all bytes were shifted out, ignoring the assert_eq!(reply_buf[0], FILL_WORD);
// reply bytes. delay.delay_ms(500_u32);
delay.delay_us(50);
// Because of the loopback mode, we should get back the fill word here.
spi.read(&mut reply_buf[0..1]).unwrap();
assert_eq!(reply_buf[0], FILL_WORD);
delay.delay_ms(500_u32);
let tx_buf: [u8; 3] = [0x01, 0x02, 0x03]; let tx_buf: [u8; 3] = [0x01, 0x02, 0x03];
spi.transfer(&mut reply_buf[0..3], &tx_buf).unwrap(); spi.transfer(&mut reply_buf[0..3], &tx_buf).unwrap();
assert_eq!(tx_buf, reply_buf[0..3]); assert_eq!(tx_buf, reply_buf[0..3]);
rprintln!( rprintln!(
"Received reply: {}, {}, {}", "Received reply: {}, {}, {}",
reply_buf[0], reply_buf[0],
reply_buf[1], reply_buf[1],
reply_buf[2] reply_buf[2]
); );
delay.delay_ms(500_u32); delay.delay_ms(500_u32);
let mut tx_rx_buf: [u8; 3] = [0x03, 0x02, 0x01]; let mut tx_rx_buf: [u8; 3] = [0x03, 0x02, 0x01];
spi.transfer_in_place(&mut tx_rx_buf).unwrap(); spi.transfer_in_place(&mut tx_rx_buf).unwrap();
rprintln!( rprintln!(
"Received reply: {}, {}, {}", "Received reply: {}, {}, {}",
tx_rx_buf[0], tx_rx_buf[0],
tx_rx_buf[1], tx_rx_buf[1],
tx_rx_buf[2] tx_rx_buf[2]
); );
assert_eq!(&tx_rx_buf[0..3], &[0x03, 0x02, 0x01]); assert_eq!(&tx_rx_buf[0..3], &[0x03, 0x02, 0x01]);
} else {
let send_buf: [u8; 3] = [0x01, 0x02, 0x03];
spi.transfer(&mut reply_buf[0..3], &send_buf).unwrap();
rprintln!(
"Received reply: {}, {}, {}",
reply_buf[0],
reply_buf[1],
reply_buf[2]
);
delay.delay_ms(1000_u32);
}
} }
} }
} }

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@ -16,6 +16,10 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
only expects a configuration structure and the transfer configuration needs to be applied in a only expects a configuration structure and the transfer configuration needs to be applied in a
separate step. separate step.
## Fixes
- Fixes for SPI peripheral: Flush implementation was incorrect and should now flush properly.
## [v0.7.0] 2024-07-04 ## [v0.7.0] 2024-07-04
- Replace `uarta` and `uartb` `Uart` constructors by `new` constructor - Replace `uarta` and `uartb` `Uart` constructors by `new` constructor