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Author SHA1 Message Date
e30d6d3f22
delay works
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2024-09-30 11:21:21 +02:00
7603185156
bootloader works
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2024-09-30 10:58:32 +02:00
2b6c013241
App A does not boot for some reason
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Rust/va108xx-rs/pipeline/pr-main This commit looks good
2024-09-30 10:25:38 +02:00
ee8a481c4f
tons of fixes 2024-09-27 20:44:10 +02:00
ea35221d41
clean up 2024-09-27 19:55:16 +02:00
a1a5156caf
re-work NVM interface 2024-09-27 19:06:13 +02:00
0f3614465f
something is still wrong
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2024-09-27 16:34:53 +02:00
52f5d42358
all flashloader adaptions
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2024-09-27 15:33:50 +02:00
1f4d6f601d
now needs tests
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Rust/va108xx-rs/pipeline/pr-main This commit looks good
2024-09-27 14:52:45 +02:00
f7ff74940a
updated UART echo RTIC example 2024-09-27 10:31:04 +02:00
60305ef393
update UART example, update UART HAL 2024-09-26 22:08:17 +02:00
ce7a8665a3
bootloader addr corrections
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Rust/va108xx-rs/pipeline/pr-main This commit looks good
2024-09-24 10:21:23 +02:00
784a6d7146
bootloader docs
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Rust/va108xx-rs/pipeline/head This commit looks good
Rust/va108xx-rs/pipeline/pr-main This commit looks good
2024-09-20 11:58:41 +02:00
2 changed files with 6 additions and 16 deletions

View File

@ -125,7 +125,6 @@ fn main() -> ! {
Some(spi_clk_cfg),
Some(SPI_MODE),
BLOCKMODE,
true,
false,
);
spi.cfg_transfer(&transfer_cfg);
@ -139,7 +138,6 @@ fn main() -> ! {
Some(SPI_MODE),
Some(hw_cs_pin),
BLOCKMODE,
true,
false,
);
spi.cfg_transfer(&transfer_cfg);

View File

@ -301,9 +301,6 @@ pub struct TransferConfig {
/// the BMSTOP bit is set on a dataword. A frame is defined as CSn being active for the
/// duration of multiple data words
pub blockmode: bool,
/// Only used when blockmode is used. The SCK will be stalled until an explicit stop bit
/// is set on a written word.
pub bmstall: bool,
pub hw_cs: HwChipSelectId,
}
@ -312,7 +309,6 @@ impl TransferConfigWithHwcs<NoneT> {
clk_cfg: Option<SpiClkConfig>,
mode: Option<Mode>,
blockmode: bool,
bmstall: bool,
sod: bool,
) -> Self {
TransferConfigWithHwcs {
@ -322,7 +318,6 @@ impl TransferConfigWithHwcs<NoneT> {
mode,
sod,
blockmode,
bmstall,
hw_cs: HwChipSelectId::Invalid,
},
}
@ -335,7 +330,6 @@ impl<HwCs: HwCsProvider> TransferConfigWithHwcs<HwCs> {
mode: Option<Mode>,
hw_cs: Option<HwCs>,
blockmode: bool,
bmstall: bool,
sod: bool,
) -> Self {
TransferConfigWithHwcs {
@ -345,7 +339,6 @@ impl<HwCs: HwCsProvider> TransferConfigWithHwcs<HwCs> {
mode,
sod,
blockmode,
bmstall,
hw_cs: HwCs::CS_ID,
},
}
@ -428,11 +421,6 @@ impl SpiConfig {
self
}
pub fn bmstall(mut self, enable: bool) -> Self {
self.bmstall = enable;
self
}
pub fn mode(mut self, mode: Mode) -> Self {
self.init_mode = mode;
self
@ -756,8 +744,12 @@ where
} else {
w.sod().clear_bit();
}
w.blockmode().bit(transfer_cfg.cfg.blockmode);
w.bmstall().bit(transfer_cfg.cfg.bmstall)
if transfer_cfg.cfg.blockmode {
w.blockmode().set_bit();
} else {
w.blockmode().clear_bit();
}
w
});
}