Merge pull request 'prepare HAL release' (#18) from prep-hal-release into main

Reviewed-on: #18

README.md

@@ -19,6 +19,11 @@ This workspace contains the following released crates:
 
 It also contains the following helper crates:
 
+- The [`bootloader`](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/bootloader)
+  crate contains a sample bootloader strongly based on the one provided by Vorago.
+- The [`flashloader`](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/flashloader)
+  crate contains a sample flashloader which is able to update the redundant images in the NVM which
+  is compatible to the provided bootloader as well.
 - The [`board-tests`](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/board-tests)
   contains an application which can be used to test the libraries on the board.
 - The [`examples`](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/examples)

board-tests/Cargo.toml

@@ -14,7 +14,6 @@ embedded-hal-nb = "1"
 embedded-io = "0.6"
 
 [dependencies.va108xx-hal]
-version = "0.7"
 path = "../va108xx-hal"
 features = ["rt"]
 

bootloader/README.md

@@ -1,4 +1,4 @@
-VA416xx Bootloader Application
+VA108xx Bootloader Application
 =======
 
 This is the Rust version of the bootloader supplied by Vorago.
@@ -11,10 +11,10 @@ The bootloader uses the following memory map:
 | ------ | ---- |  ---- |
 | 0x0 | Bootloader start | code up to 0x3FFC bytes |
 | 0x2FFE | Bootloader CRC | word |
-| 0x3000 | App image A start | code up to 0x1DFFC (~120K) bytes |
+| 0x3000 | App image A start | code up to 0xE7F8 (~58K) bytes |
 | 0x117F8 | App image A CRC check length | word |
 | 0x117FC | App image A CRC check value | word |
-| 0x11800 | App image B start | code up to 0x1DFFC (~120K) bytes |
+| 0x11800 | App image B start | code up to 0xE7F8 (~58K) bytes |
 | 0x1FFF8 | App image B CRC check length | word |
 | 0x1FFFC | App image B CRC check value | word |
 | 0x20000 | End of NVM | end  |

flashloader/README.md

@@ -7,7 +7,7 @@ called the `image-loader.py` which can be used to upload compiled images to the
 application to write them to the NVM.
 
 Please note that the both the application and the image loader are tailored towards usage
-with the [bootloader provided by this repository](https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/src/branch/main/bootloader).
+with the [bootloader provided by this repository](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/bootloader).
 
 The software can quickly be adapted to interface with a real primary on-board software instead of
 the Python script provided here to upload images because it uses a low-level CCSDS based packet

scripts/memory_app_a.x

@@ -1,6 +1,6 @@
 MEMORY
 {
-	FLASH : ORIGIN = 0x00003000, LENGTH = 0xE800 /* (128k - 12k) / 2 */
+	FLASH : ORIGIN = 0x00003000, LENGTH = 0xE7F8 /* (128k - 12k) / 2 - 8 */
 	RAM : ORIGIN = 0x10000000, LENGTH = 0x08000 /* 32K */
 }
 

scripts/memory_app_b.x

@@ -1,6 +1,6 @@
 MEMORY
 {
-	FLASH : ORIGIN = 0x00011800, LENGTH = 0xE800 /* (128k - 12k) / 2 */
+	FLASH : ORIGIN = 0x00011800, LENGTH = 0xE7F8 /* (128k - 12k) / 2 - 8 */
 	RAM : ORIGIN = 0x10000000, LENGTH = 0x08000 /* 32K */
 }
 

va108xx-hal/CHANGELOG.md

@@ -8,6 +8,8 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ## [unreleased]
 
+## [v0.8.0] 2024-09-30
+
 ## Changed
 
 - Improves `CascardSource` handling and general API when chosing cascade sources.

va108xx-hal/Cargo.toml

@@ -1,6 +1,6 @@
 [package]
 name = "va108xx-hal"
-version = "0.7.0"
+version = "0.8.0"
 authors = ["Robin Mueller <muellerr@irs.uni-stuttgart.de>"]
 edition = "2021"
 description = "HAL for the Vorago VA108xx family of microcontrollers"

va108xx-hal/src/uart.rs

@@ -3,7 +3,8 @@
 //! ## Examples
 //!
 //! - [UART simple example](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/examples/simple/examples/uart.rs)
-//! - [UART with IRQ and RTIC](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/va108xx-update-package/examples/rtic/src/bin/uart-rtic.rs)
+//! - [UART with IRQ and RTIC](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/examples/rtic/src/bin/uart-echo-rtic.rs)
+//! - [Flashloader exposing a CCSDS interface via UART](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/flashloader)
 use core::{convert::Infallible, ops::Deref};
 use fugit::RateExtU32;
 use va108xx::Uarta;
@@ -863,7 +864,7 @@ impl<Uart: Instance> Tx<Uart> {
     ///
     /// This does not necesarily mean that the FIFO can process another word because it might be
     /// full.
-    /// Use the [Self::read_fifo] function to write a word to the FIFO reliably using the [nb]
+    /// Use the [Self::write_fifo] function to write a word to the FIFO reliably using the [nb]
     /// API.
     #[inline(always)]
     pub fn write_fifo_unchecked(&self, data: u32) {
@@ -916,7 +917,7 @@ impl<Uart: Instance> embedded_io::Write for Tx<Uart> {
 
 /// Serial receiver, using interrupts to offload reading to the hardware.
 ///
-/// You can use [Rx::to_rx_with_irq] to convert a normal [Rx] structure into this structure.
+/// You can use [Rx::into_rx_with_irq] to convert a normal [Rx] structure into this structure.
 /// This structure provides two distinct ways to read the UART RX using interrupts. It should
 /// be noted that the interrupt service routine (ISR) still has to be provided by the user. However,
 /// this structure provides API calls which can be used inside the ISRs to simplify the reading

vorago-reb1/Cargo.toml

@@ -21,7 +21,7 @@ bitfield = "0.17"
 version = "0.3"
 
 [dependencies.va108xx-hal]
-version = ">=0.7, <0.8"
+version = ">=0.7, <=0.8"
 path = "../va108xx-hal"
 features = ["rt"]