update error handling

.cargo/def-config.toml

@@ -4,9 +4,10 @@
 # runner = "arm-none-eabi-gdb -q -x openocd.gdb"
 # runner = "gdb-multiarch -q -x openocd.gdb"
 # runner = "gdb -q -x openocd.gdb"
-# runner = "gdb-multiarch -q -x jlink.gdb"
+runner = "gdb-multiarch -q -x jlink.gdb"
 
-runner = "probe-rs run --chip VA108xx_RAM --protocol jtag"
+# Probe-rs is currently problematic: https://github.com/probe-rs/probe-rs/issues/2567
+# runner = "probe-rs run --chip VA108xx --chip-description-path ./scripts/VA108xx_Series.yaml"
 # runner = ["probe-rs", "run", "--chip", "$CHIP", "--log-format", "{L} {s}"]
 
 rustflags = [
@@ -18,9 +19,9 @@ rustflags = [
   "-C", "link-arg=-Tlink.x",
 
   # knurling-rs tooling. If you want to use flip-link, ensure it is installed first.
-  "-C", "linker=flip-link",
+  # "-C", "linker=flip-link",
   # Unfortunately, defmt is clunky to use without probe-rs..
-  "-C", "link-arg=-Tdefmt.x",
+  # "-C", "link-arg=-Tdefmt.x",
 
   # Can be useful for debugging.
   # "-Clink-args=-Map=app.map"

.github/workflows/ci.yml

@@ -12,8 +12,6 @@ jobs:
           targets: "thumbv6m-none-eabi"
       - run: cargo check --target thumbv6m-none-eabi
       - run: cargo check --target thumbv6m-none-eabi --examples
-      - run: cargo check -p va108xx --target thumbv6m-none-eabi --all-features
-      - run: cargo check -p va108xx-hal --target thumbv6m-none-eabi --features "defmt"
 
   test:
     name: Run Tests
@@ -41,8 +39,8 @@ jobs:
     steps:
       - uses: actions/checkout@v4
       - uses: dtolnay/rust-toolchain@nightly
-      - run: RUSTDOCFLAGS="--cfg docsrs --generate-link-to-definition -Z unstable-options" cargo +nightly doc -p va108xx --all-features
+      - run: RUSTDOCFLAGS="--cfg docsrs --generate-link-to-definition -Z unstable-options" cargo +nightly doc -p va108xx
-      - run: RUSTDOCFLAGS="--cfg docsrs --generate-link-to-definition -Z unstable-options" cargo +nightly doc -p va108xx-hal --all-features
+      - run: RUSTDOCFLAGS="--cfg docsrs --generate-link-to-definition -Z unstable-options" cargo +nightly doc -p va108xx-hal
       - run: RUSTDOCFLAGS="--cfg docsrs --generate-link-to-definition -Z unstable-options" cargo +nightly doc -p vorago-reb1
 
   clippy:

Cargo.toml

@@ -13,6 +13,7 @@ members = [
   "flashloader",
 ]
 exclude = [
+  "defmt-testapp",
   "flashloader/slot-a-blinky",
   "flashloader/slot-b-blinky",
 ]

README.md

@@ -14,8 +14,6 @@ This workspace contains the following released crates:
   crate containing basic low-level register definition.
 - The [`va108xx-hal`](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/va108xx-hal)
   HAL crate containing higher-level abstractions on top of the PAC register crate.
-- The [`va108xx-embassy`](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/va108xx-embassy)
-  crate containing support for running the embassy-rs RTOS.
 - The [`vorago-reb1`](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/vorago-reb1)
   BSP crate containing support for the REB1 development board.
 
@@ -34,9 +32,6 @@ It also contains the following helper crates:
   [`RTIC`](https://rtic.rs/2/book/en/) and [`embassy`](https://github.com/embassy-rs/embassy)
   native Rust RTOSes.
 
-The majority of the HAL implementation and the Embassy-rs support are contained in the external
-[`vorago-shared-periphs`](https://egit.irs.uni-stuttgart.de/rust/vorago-shared-periphs) crate.
-
 ## Using the `.cargo/config.toml` file
 
 Use the following command to have a starting `config.toml` file
@@ -63,24 +58,46 @@ You can then adapt the files in `.vscode` to your needs.
 You can use CLI or VS Code for flashing, running and debugging. In any case, take
 care of installing the pre-requisites first.
 
-### Using CLI with probe-rs
+### Pre-Requisites
 
-Install [probe-rs](https://probe.rs/docs/getting-started/installation/) first.
+1. [SEGGER J-Link tools](https://www.segger.com/downloads/jlink/) installed
+2. [gdb-multiarch](https://packages.debian.org/sid/gdb-multiarch) or similar
+   cross-architecture debugger installed. All commands here assume `gdb-multiarch`.
 
-You can use `probe-rs` to run the software and display RTT log output. However, debugging does not
+### Using CLI
-work yet.
 
-After installation, you can run the following command
+You can build the blinky example application with the following command
 
 ```sh
-probe-rs run --chip VA108xx_RAM --protocol jtag target/thumbv6m-none-eabi/debug/examples/blinky
+cargo build --example blinky
 ```
 
-to flash and run the blinky program on the RAM. There is also a `VA108xx` chip target
+Start the GDB server first. The server needs to be started with a certain configuration and with
-available for persistent flashing.
+a JLink script to disable ROM protection.
+For example, on Debian based system the following command can be used to do this (this command
+is also run when running the `jlink-gdb.sh` script)
 
-Runner configuration is available in the `.cargo/def-config.toml` file to use `probe-rs` for
+```sh
-convenience. `probe-rs` is also able to process and display `defmt` strings directly.
+JLinkGDBServer -select USB -device Cortex-M0 -endian little -if JTAG-speed auto \
+  -LocalhostOnly
+```
+
+After this, you can flash and debug the application with the following command
+
+```sh
+gdb-mutliarch -q -x jlink/jlink.gdb target/thumbv6m-none-eabihf/debug/examples/blinky
+```
+
+Please note that you can automate all steps except starting the GDB server by using a cargo
+runner configuration, for example with the following lines in your `.cargo/config.toml` file:
+
+```toml
+[target.'cfg(all(target_arch = "arm", target_os = "none"))']
+runner = "gdb-multiarch -q -x jlink/jlink.gdb"
+```
+
+After that, you can simply use `cargo run --example blinky` to flash the blinky
+example.
 
 ### Using VS Code
 
@@ -104,69 +121,3 @@ configuration variables in your `settings.json`:
 The provided VS Code configurations also provide an integrated RTT logger, which you can access
 via the terminal at `RTT Ch:0 console`. In order for the RTT block address detection to
 work properly, `objdump-multiarch` and `nm-multiarch` need to be installed.
-
-### Using CLI with GDB and Segger J-Link Tools
-
-Install the following two tools first:
-
-1. [SEGGER J-Link tools](https://www.segger.com/downloads/jlink/) installed
-2. [gdb-multiarch](https://packages.debian.org/sid/gdb-multiarch) or similar
-   cross-architecture debugger installed. All commands here assume `gdb-multiarch`.
-
-You can build the blinky example application with the following command
-
-```sh
-cargo build --example blinky
-```
-
-Start the GDB server first. The server needs to be started with a certain configuration and with
-a JLink script to disable ROM protection.
-For example, on Debian based system the following command can be used to do this (this command
-is also run when running the `jlink-gdb.sh` script)
-
-```sh
-JLinkGDBServer -select USB -device Cortex-M0 -endian little -if JTAG-speed auto \
-  -LocalhostOnly -jtagconf -1,-1
-```
-
-After this, you can flash and debug the application with the following command
-
-```sh
-gdb-mutliarch -q -x jlink/jlink.gdb target/thumbv6m-none-eabihf/debug/examples/blinky -tui
-```
-
-Please note that you can automate all steps except starting the GDB server by using a cargo
-runner configuration, for example with the following lines in your `.cargo/config.toml` file:
-
-```toml
-[target.'cfg(all(target_arch = "arm", target_os = "none"))']
-runner = "gdb-multiarch -q -x jlink/jlink.gdb"
-```
-
-After that, you can simply use `cargo run --example blinky` to flash the blinky
-example.
-
-### Using the RTT Viewer
-
-The Segger RTT viewer can be used to display log messages received from the target. The base
-address for the RTT block placement is 0x10000000. It is recommended to use a search range of
-0x1000 around that base address when using the RTT viewer.
-
-The RTT viewer will not be able to process `defmt` printouts. However, you can view the defmt
-logs by [installing defmt-print](https://crates.io/crates/defmt-print) first and then running
-
-```sh
-defmt-print -e <pathToElfFile> tcp
-```
-
-The path of the ELF file which is being debugged needs to be specified for this to work.
-
-## Learning (Embedded) Rust
-
-If you are unfamiliar with Rust on Embedded Systems or Rust in general, the following resources
-are recommended:
-
-- [Rust Book](https://doc.rust-lang.org/book/)
-- [Embedded Rust Book](https://docs.rust-embedded.org/book/)
-- [Embedded Rust Discovery](https://docs.rust-embedded.org/discovery/microbit/)
-- [Awesome Embedded Rust](https://github.com/rust-embedded/awesome-embedded-rust)

board-tests/Cargo.toml

@@ -6,13 +6,14 @@ edition = "2021"
 [dependencies]
 cortex-m = { version = "0.7.6", features = ["critical-section-single-core"] }
 cortex-m-rt = "0.7"
-defmt = "1"
+panic-halt = "1"
-defmt-rtt = "0.4"
+rtt-target = "0.6"
-panic-probe = { version = "0.3", features = ["print-defmt"] }
+panic-rtt-target = "0.2"
 embedded-hal = "1"
+embedded-hal-nb = "1"
+embedded-io = "0.6"
 
 [dependencies.va108xx-hal]
-version = "0.11"
-features = ["rt"]
 path = "../va108xx-hal"
+features = ["rt"]
 

board-tests/src/main.rs

@@ -6,22 +6,22 @@
 #![no_std]
 
 use cortex_m_rt::entry;
-use embedded_hal::delay::DelayNs;
+use embedded_hal::{
-// Logging provider
+    delay::DelayNs,
-use defmt_rtt as _;
+    digital::{InputPin, OutputPin, StatefulOutputPin},
-// Panic provider
+};
-use panic_probe as _;
+use panic_rtt_target as _;
+use rtt_target::{rprintln, rtt_init_print};
 use va108xx_hal::{
-    gpio::{regs::Gpio, Input, Output, PinState, Pull},
+    gpio::{PinState, PinsA, PinsB},
-    pac,
+    pac::{self, interrupt},
-    pins::{PinsA, PinsB, Port},
     prelude::*,
     time::Hertz,
-    timer::CountdownTimer,
+    timer::{default_ms_irq_handler, set_up_ms_tick, CountdownTimer, IrqCfg},
 };
 
 #[allow(dead_code)]
-#[derive(Debug, defmt::Format)]
+#[derive(Debug)]
 enum TestCase {
     // Tie PORTA[0] to PORTA[1] for these tests!
     TestBasic,
@@ -35,18 +35,18 @@ enum TestCase {
     Pulse,
     // Tie PA0, PA1 and PA3 to an oscilloscope
     DelayGpio,
-    // PA0 can be checked with an oscillsope to verify timing correctness.
     DelayMs,
 }
 
 #[entry]
 fn main() -> ! {
-    defmt::println!("-- VA108xx Test Application --");
+    rtt_init_print!();
-    let dp = pac::Peripherals::take().unwrap();
+    rprintln!("-- VA108xx Test Application --");
+    let mut dp = pac::Peripherals::take().unwrap();
     let cp = cortex_m::Peripherals::take().unwrap();
-    let pinsa = PinsA::new(dp.porta);
+    let pinsa = PinsA::new(&mut dp.sysconfig, None, dp.porta);
-    let pinsb = PinsB::new(dp.portb);
+    let pinsb = PinsB::new(&mut dp.sysconfig, Some(dp.ioconfig), dp.portb);
-    let mut led1 = Output::new(pinsa.pa10, PinState::Low);
+    let mut led1 = pinsa.pa10.into_readable_push_pull_output();
     let test_case = TestCase::DelayMs;
 
     match test_case {
@@ -54,131 +54,154 @@ fn main() -> ! {
         | TestCase::TestPulldown
         | TestCase::TestPullup
         | TestCase::TestMask => {
-            defmt::info!(
+            rprintln!(
                 "Test case {:?}. Make sure to tie PORTA[0] to PORTA[1]",
                 test_case
             );
         }
         _ => {
-            defmt::info!("Test case {:?}", test_case);
+            rprintln!("Test case {:?}", test_case);
         }
     }
     match test_case {
         TestCase::TestBasic => {
             // Tie PORTA[0] to PORTA[1] for these tests!
-            let mut out = Output::new(pinsa.pa0, PinState::Low);
+            let mut out = pinsa.pa0.into_readable_push_pull_output();
-            let input = Input::new_floating(pinsa.pa1);
+            let mut input = pinsa.pa1.into_floating_input();
-            out.set_high();
+            out.set_high().unwrap();
-            assert!(input.is_high());
+            assert!(input.is_high().unwrap());
-            out.set_low();
+            out.set_low().unwrap();
-            assert!(input.is_low());
+            assert!(input.is_low().unwrap());
         }
         TestCase::TestPullup => {
             // Tie PORTA[0] to PORTA[1] for these tests!
-            let input = Input::new_with_pull(pinsa.pa1, Pull::Up);
+            let mut input = pinsa.pa1.into_pull_up_input();
-            assert!(input.is_high());
+            assert!(input.is_high().unwrap());
-            let mut out = Output::new(pinsa.pa0, PinState::Low);
+            let mut out = pinsa.pa0.into_readable_push_pull_output();
-            out.set_low();
+            out.set_low().unwrap();
-            assert!(input.is_low());
+            assert!(input.is_low().unwrap());
-            out.set_high();
+            out.set_high().unwrap();
-            assert!(input.is_high());
+            assert!(input.is_high().unwrap());
+            out.into_floating_input();
+            assert!(input.is_high().unwrap());
         }
         TestCase::TestPulldown => {
             // Tie PORTA[0] to PORTA[1] for these tests!
-            let input = Input::new_with_pull(pinsa.pa1, Pull::Down);
+            let mut input = pinsa.pa1.into_pull_down_input();
-            assert!(input.is_low());
+            assert!(input.is_low().unwrap());
-            let mut out = Output::new(pinsa.pa0, PinState::Low);
+            let mut out = pinsa.pa0.into_push_pull_output();
-            out.set_low();
+            out.set_low().unwrap();
-            assert!(input.is_low());
+            assert!(input.is_low().unwrap());
-            out.set_high();
+            out.set_high().unwrap();
-            assert!(input.is_high());
+            assert!(input.is_high().unwrap());
+            out.into_floating_input();
+            assert!(input.is_low().unwrap());
         }
         TestCase::TestMask => {
             // Tie PORTA[0] to PORTA[1] for these tests!
-            // Need to test this low-level..
+            let mut input = pinsa.pa1.into_pull_down_input();
-            /*
-            let mut input = Input::new_with_pull(pinsa.pa1, Pull::Down);
             input.clear_datamask();
             assert!(!input.datamask());
             let mut out = pinsa.pa0.into_push_pull_output();
             out.clear_datamask();
             assert!(input.is_low_masked().is_err());
             assert!(out.set_high_masked().is_err());
-            */
         }
         TestCase::PortB => {
             // Tie PORTB[22] to PORTB[23] for these tests!
-            let mut out = Output::new(pinsb.pb22, PinState::Low);
+            let mut out = pinsb.pb22.into_readable_push_pull_output();
-            let input = Input::new_floating(pinsb.pb23);
+            let mut input = pinsb.pb23.into_floating_input();
-            out.set_high();
+            out.set_high().unwrap();
-            assert!(input.is_high());
+            assert!(input.is_high().unwrap());
-            out.set_low();
+            out.set_low().unwrap();
-            assert!(input.is_low());
+            assert!(input.is_low().unwrap());
         }
         TestCase::Perid => {
-            let mmio_porta = Gpio::new_mmio(Port::A);
+            assert_eq!(PinsA::get_perid(), 0x004007e1);
-            assert_eq!(mmio_porta.read_perid(), 0x004007e1);
+            assert_eq!(PinsB::get_perid(), 0x004007e1);
-            let mmio_porta = Gpio::new_mmio(Port::B);
-            assert_eq!(mmio_porta.read_perid(), 0x004007e1);
         }
         TestCase::Pulse => {
-            let mut output_pulsed = Output::new(pinsa.pa0, PinState::Low);
+            let mut output_pulsed = pinsa.pa0.into_push_pull_output();
-            output_pulsed.configure_pulse_mode(true, PinState::Low);
+            output_pulsed.pulse_mode(true, PinState::Low);
-            defmt::info!("Pulsing high 10 times..");
+            rprintln!("Pulsing high 10 times..");
-            output_pulsed.set_low();
+            output_pulsed.set_low().unwrap();
             for _ in 0..10 {
-                output_pulsed.set_high();
+                output_pulsed.set_high().unwrap();
                 cortex_m::asm::delay(25_000_000);
             }
-            output_pulsed.configure_pulse_mode(true, PinState::High);
+            output_pulsed.pulse_mode(true, PinState::High);
-            defmt::info!("Pulsing low 10 times..");
+            rprintln!("Pulsing low 10 times..");
             for _ in 0..10 {
-                output_pulsed.set_low();
+                output_pulsed.set_low().unwrap();
                 cortex_m::asm::delay(25_000_000);
             }
         }
         TestCase::DelayGpio => {
-            let mut out_0 = Output::new(pinsa.pa0, PinState::Low);
+            let mut out_0 = pinsa
-            out_0.configure_delay(true, false);
+                .pa0
-            let mut out_1 = Output::new(pinsa.pa1, PinState::Low);
+                .into_readable_push_pull_output()
-            out_1.configure_delay(false, true);
+                .delay(true, false);
-            let mut out_2 = Output::new(pinsa.pa3, PinState::Low);
+            let mut out_1 = pinsa
-            out_2.configure_delay(true, true);
+                .pa1
+                .into_readable_push_pull_output()
+                .delay(false, true);
+            let mut out_2 = pinsa.pa3.into_readable_push_pull_output().delay(true, true);
             for _ in 0..20 {
-                out_0.toggle();
+                out_0.toggle().unwrap();
-                out_1.toggle();
+                out_1.toggle().unwrap();
-                out_2.toggle();
+                out_2.toggle().unwrap();
                 cortex_m::asm::delay(25_000_000);
             }
         }
         TestCase::DelayMs => {
-            let mut delay_timer = CountdownTimer::new(dp.tim1, 50.MHz());
+            let mut ms_timer = set_up_ms_tick(
-            let mut pa0 = Output::new(pinsa.pa0, PinState::Low);
+                IrqCfg::new(pac::Interrupt::OC0, true, true),
+                &mut dp.sysconfig,
+                Some(&mut dp.irqsel),
+                50.MHz(),
+                dp.tim0,
+            );
             for _ in 0..5 {
-                led1.toggle();
+                led1.toggle().ok();
+                ms_timer.delay_ms(500);
+                led1.toggle().ok();
+                ms_timer.delay_ms(500);
+            }
+
+            let mut delay_timer = CountdownTimer::new(&mut dp.sysconfig, 50.MHz(), dp.tim1);
+            let mut pa0 = pinsa.pa0.into_readable_push_pull_output();
+            for _ in 0..5 {
+                led1.toggle().ok();
                 delay_timer.delay_ms(500);
-                led1.toggle();
+                led1.toggle().ok();
                 delay_timer.delay_ms(500);
             }
             let ahb_freq: Hertz = 50.MHz();
             let mut syst_delay = cortex_m::delay::Delay::new(cp.SYST, ahb_freq.raw());
-            // Release image should be used to verify timings for pin PA0
+            // Test usecond delay using both TIM peripheral and SYST. Use the release image if you
-            for _ in 0..5 {
+            // want to verify the timings!
-                pa0.toggle();
+            loop {
-                syst_delay.delay_us(50);
+                pa0.toggle().ok();
-                pa0.toggle();
-                syst_delay.delay_us(50);
-                pa0.toggle();
                 delay_timer.delay_us(50);
-                pa0.toggle();
+                pa0.toggle().ok();
                 delay_timer.delay_us(50);
+                pa0.toggle_with_toggle_reg();
+                syst_delay.delay_us(50);
+                pa0.toggle_with_toggle_reg();
+                syst_delay.delay_us(50);
             }
         }
     }
 
-    defmt::info!("Test success");
+    rprintln!("Test success");
     loop {
-        led1.toggle();
+        led1.toggle().ok();
         cortex_m::asm::delay(25_000_000);
     }
 }
+
+#[interrupt]
+#[allow(non_snake_case)]
+fn OC0() {
+    default_ms_irq_handler()
+}

bootloader/Cargo.toml

@@ -7,20 +7,17 @@ edition = "2021"
 cortex-m = "0.7"
 cortex-m-rt = "0.7"
 embedded-hal = "1"
-defmt-rtt = "0.4"
+panic-rtt-target = "0.2"
-defmt = "1"
+panic-halt = "1"
-panic-probe = { version = "1", features = ["defmt"] }
+rtt-target = "0.6"
 crc = "3"
 num_enum = { version = "0.7", default-features = false }
 static_assertions = "1"
 
 [dependencies.va108xx-hal]
-version = "0.11"
 path = "../va108xx-hal"
-features = ["defmt"]
 
 [dependencies.vorago-reb1]
-version = "0.8"
 path = "../vorago-reb1"
 
 [features]

bootloader/README.md

@@ -12,8 +12,8 @@ The bootloader uses the following memory map:
 | 0x0 | Bootloader start | code up to 0x2FFE bytes |
 | 0x2FFE | Bootloader CRC | half-word |
 | 0x3000 | App image A start | code up to 0xE7F4 (~59K) bytes |
-| 0x117F4 | App image A CRC check length | word |
+| 0x117F8 | App image A CRC check length | word |
-| 0x117F8 | App image A CRC check value | word |
+| 0x117FC | App image A CRC check value | word |
 | 0x117FC | App image B start | code up to 0xE7F4 (~59K) bytes |
 | 0x1FFF0 | App image B CRC check length | word |
 | 0x1FFF4 | App image B CRC check value | word |

bootloader/src/main.rs

@@ -6,16 +6,17 @@ use cortex_m_rt::entry;
 use crc::{Crc, CRC_16_IBM_3740};
 use embedded_hal::delay::DelayNs;
 use num_enum::TryFromPrimitive;
-// Import panic provider.
+#[cfg(not(feature = "rtt-panic"))]
-use panic_probe as _;
+use panic_halt as _;
-// Import logger.
+#[cfg(feature = "rtt-panic")]
-use defmt_rtt as _;
+use panic_rtt_target as _;
-use va108xx_hal::{pac, spi::SpiClkConfig, time::Hertz, timer::CountdownTimer};
+use rtt_target::{rprintln, rtt_init_print};
+use va108xx_hal::{pac, time::Hertz, timer::CountdownTimer};
 use vorago_reb1::m95m01::M95M01;
 
 // Useful for debugging and see what the bootloader is doing. Enabled currently, because
 // the binary stays small enough.
-const DEFMT_PRINTOUT: bool = true;
+const RTT_PRINTOUT: bool = true;
 const DEBUG_PRINTOUTS: bool = true;
 // Small delay, allows RTT printout to catch up.
 const BOOT_DELAY_MS: u32 = 2000;
@@ -73,7 +74,7 @@ pub const PREFERRED_SLOT_OFFSET: u32 = 0x20000 - 1;
 
 const CRC_ALGO: Crc<u16> = Crc::<u16>::new(&CRC_16_IBM_3740);
 
-#[derive(Debug, Copy, Clone, PartialEq, Eq, TryFromPrimitive, defmt::Format)]
+#[derive(Debug, Copy, Clone, PartialEq, Eq, TryFromPrimitive)]
 #[repr(u8)]
 enum AppSel {
     A = 0,
@@ -99,15 +100,15 @@ impl NvmInterface for NvmWrapper {
 
 #[entry]
 fn main() -> ! {
-    if DEFMT_PRINTOUT {
+    if RTT_PRINTOUT {
-        defmt::println!("-- VA108xx bootloader --");
+        rtt_init_print!();
+        rprintln!("-- VA108xx bootloader --");
     }
-    let dp = pac::Peripherals::take().unwrap();
+    let mut dp = pac::Peripherals::take().unwrap();
     let cp = cortex_m::Peripherals::take().unwrap();
-    let mut timer = CountdownTimer::new(dp.tim0, CLOCK_FREQ);
+    let mut timer = CountdownTimer::new(&mut dp.sysconfig, CLOCK_FREQ, dp.tim0);
 
-    let clk_config = SpiClkConfig::new(2, 4);
+    let mut nvm = M95M01::new(&mut dp.sysconfig, CLOCK_FREQ, dp.spic);
-    let mut nvm = M95M01::new(dp.spic, clk_config);
 
     if FLASH_SELF {
         let mut first_four_bytes: [u8; 4] = [0; 4];
@@ -130,21 +131,21 @@ fn main() -> ! {
         nvm.write(0x4, bootloader_data)
             .expect("writing to NVM failed");
         if let Err(e) = nvm.verify(0x0, &first_four_bytes) {
-            if DEFMT_PRINTOUT {
+            if RTT_PRINTOUT {
-                defmt::error!("verification of self-flash to NVM failed: {:?}", e);
+                rprintln!("verification of self-flash to NVM failed: {:?}", e);
             }
         }
         if let Err(e) = nvm.verify(0x4, bootloader_data) {
-            if DEFMT_PRINTOUT {
+            if RTT_PRINTOUT {
-                defmt::error!("verification of self-flash to NVM failed: {:?}", e);
+                rprintln!("verification of self-flash to NVM failed: {:?}", e);
             }
         }
 
         nvm.write(BOOTLOADER_CRC_ADDR as usize, &bootloader_crc.to_be_bytes())
             .expect("writing CRC failed");
         if let Err(e) = nvm.verify(BOOTLOADER_CRC_ADDR as usize, &bootloader_crc.to_be_bytes()) {
-            if DEFMT_PRINTOUT {
+            if RTT_PRINTOUT {
-                defmt::error!(
+                rprintln!(
                     "error: CRC verification for bootloader self-flash failed: {:?}",
                     e
                 );
@@ -172,8 +173,8 @@ fn main() -> ! {
     } else if check_app_crc(other_app) {
         boot_app(&dp.sysconfig, &cp, other_app, &mut timer)
     } else {
-        if DEBUG_PRINTOUTS && DEFMT_PRINTOUT {
+        if DEBUG_PRINTOUTS && RTT_PRINTOUT {
-            defmt::error!("both images corrupt! booting image A");
+            rprintln!("both images corrupt! booting image A");
         }
         // TODO: Shift a CCSDS packet out to inform host/OBC about image corruption.
         // Both images seem to be corrupt. Boot default image A.
@@ -185,7 +186,7 @@ fn check_own_crc(
     sysconfig: &pac::Sysconfig,
     cp: &cortex_m::Peripherals,
     nvm: &mut NvmWrapper,
-    timer: &mut CountdownTimer,
+    timer: &mut CountdownTimer<pac::Tim0>,
 ) {
     let crc_exp = unsafe { (BOOTLOADER_CRC_ADDR as *const u16).read_unaligned().to_be() };
     // I'd prefer to use [core::slice::from_raw_parts], but that is problematic
@@ -203,8 +204,8 @@ fn check_own_crc(
     });
     let crc_calc = digest.finalize();
     if crc_exp == 0x0000 || crc_exp == 0xffff {
-        if DEBUG_PRINTOUTS && DEFMT_PRINTOUT {
+        if DEBUG_PRINTOUTS && RTT_PRINTOUT {
-            defmt::info!("BL CRC blank - prog new CRC");
+            rprintln!("BL CRC blank - prog new CRC");
         }
         // Blank CRC, write it to NVM.
         nvm.write(BOOTLOADER_CRC_ADDR as usize, &crc_calc.to_be_bytes())
@@ -214,8 +215,8 @@ fn check_own_crc(
         // cortex_m::peripheral::SCB::sys_reset();
     } else if crc_exp != crc_calc {
         // Bootloader is corrupted. Try to run App A.
-        if DEBUG_PRINTOUTS && DEFMT_PRINTOUT {
+        if DEBUG_PRINTOUTS && RTT_PRINTOUT {
-            defmt::warn!(
+            rprintln!(
                 "bootloader CRC corrupt, read {} and expected {}. booting image A immediately",
                 crc_calc,
                 crc_exp
@@ -240,8 +241,8 @@ fn read_four_bytes_at_addr_zero(buf: &mut [u8; 4]) {
     }
 }
 fn check_app_crc(app_sel: AppSel) -> bool {
-    if DEBUG_PRINTOUTS && DEFMT_PRINTOUT {
+    if DEBUG_PRINTOUTS && RTT_PRINTOUT {
-        defmt::info!("Checking image {:?}", app_sel);
+        rprintln!("Checking image {:?}", app_sel);
     }
     if app_sel == AppSel::A {
         check_app_given_addr(APP_A_CRC_ADDR, APP_A_START_ADDR, APP_A_SIZE_ADDR)
@@ -255,8 +256,8 @@ fn check_app_given_addr(crc_addr: u32, start_addr: u32, image_size_addr: u32) ->
     let image_size = unsafe { (image_size_addr as *const u32).read_unaligned().to_be() };
     // Sanity check.
     if image_size > APP_A_END_ADDR - APP_A_START_ADDR - 8 {
-        if DEFMT_PRINTOUT {
+        if RTT_PRINTOUT {
-            defmt::error!("detected invalid app size {}", image_size);
+            rprintln!("detected invalid app size {}", image_size);
         }
         return false;
     }
@@ -275,10 +276,10 @@ fn boot_app(
     syscfg: &pac::Sysconfig,
     cp: &cortex_m::Peripherals,
     app_sel: AppSel,
-    timer: &mut CountdownTimer,
+    timer: &mut CountdownTimer<pac::Tim0>,
 ) -> ! {
-    if DEBUG_PRINTOUTS && DEFMT_PRINTOUT {
+    if DEBUG_PRINTOUTS && RTT_PRINTOUT {
-        defmt::info!("booting app {:?}", app_sel);
+        rprintln!("booting app {:?}", app_sel);
     }
     timer.delay_ms(BOOT_DELAY_MS);
 

defmt-testapp/.cargo/config.toml

@@ -0,0 +1,48 @@
+[target.'cfg(all(target_arch = "arm", target_os = "none"))']
+# uncomment ONE of these three option to make `cargo run` start a GDB session
+# which option to pick depends on your system
+# runner = "arm-none-eabi-gdb -q -x openocd.gdb"
+# runner = "gdb-multiarch -q -x openocd.gdb"
+# runner = "gdb -q -x openocd.gdb"
+runner = "gdb-multiarch -q -x jlink.gdb"
+
+# Probe-rs is currently problematic: https://github.com/probe-rs/probe-rs/issues/2567
+# runner = "probe-rs run --chip VA108xx --chip-description-path ./scripts/VA108xx_Series.yaml"
+# runner = ["probe-rs", "run", "--chip", "$CHIP", "--log-format", "{L} {s}"]
+
+rustflags = [
+  # This is needed if your flash or ram addresses are not aligned to 0x10000 in memory.x
+  # See https://github.com/rust-embedded/cortex-m-quickstart/pull/95
+  "-C", "link-arg=--nmagic",
+
+  # LLD (shipped with the Rust toolchain) is used as the default linker
+  "-C", "link-arg=-Tlink.x",
+
+  # knurling-rs tooling. If you want to use flip-link, ensure it is installed first.
+  "-C", "linker=flip-link",
+  # Unfortunately, defmt is clunky to use without probe-rs..
+  "-C", "link-arg=-Tdefmt.x",
+
+  # Can be useful for debugging.
+  "-Clink-args=-Map=app.map"
+
+]
+
+[build]
+# Pick ONE of these compilation targets
+target = "thumbv6m-none-eabi"        # Cortex-M0 and Cortex-M0+
+# target = "thumbv7m-none-eabi"        # Cortex-M3
+# target = "thumbv7em-none-eabi"       # Cortex-M4 and Cortex-M7 (no FPU)
+# target = "thumbv7em-none-eabihf"     # Cortex-M4F and Cortex-M7F (with FPU)
+# target = "thumbv8m.base-none-eabi"   # Cortex-M23
+# target = "thumbv8m.main-none-eabi"   # Cortex-M33 (no FPU)
+# target = "thumbv8m.main-none-eabihf" # Cortex-M33 (with FPU)
+
+[alias]
+re = "run --example"
+rb = "run --bin"
+rrb = "run --release --bin"
+ut = "test --target x86_64-unknown-linux-gnu"
+
+[env]
+DEFMT_LOG = "info"

defmt-testapp/.gitignore

@@ -0,0 +1 @@
+/target

defmt-testapp/Cargo.toml

@@ -0,0 +1,36 @@
+[package]
+name = "defmt-testapp"
+version = "0.1.0"
+edition = "2021"
+
+[dependencies]
+cortex-m = {version = "0.7", features = ["critical-section-single-core"]}
+panic-rtt-target = "0.1"
+cortex-m-rt = "0.7"
+rtt-target = "0.5"
+rtic-sync = { version = "1.3", features = ["defmt-03"] }
+embedded-hal = "1"
+embedded-hal-nb = "1"
+embedded-io = "0.6"
+cortex-m-semihosting = "0.5.0"
+# Tricky without probe-rs.
+defmt = "0.3"
+defmt-brtt = { version = "0.1", default-features = false, features = ["rtt"] }
+panic-probe = { version = "0.3", features = ["print-defmt"] }
+
+[dependencies.rtic]
+version = "2"
+features = ["thumbv6-backend"]
+
+[dependencies.rtic-monotonics]
+version = "1"
+features = ["cortex-m-systick"]
+
+[dependencies.va108xx-hal]
+version = "0.6"
+path = "../va108xx-hal"
+features = ["rt", "defmt"]
+
+[dependencies.va108xx]
+version = "0.3"
+path = "../va108xx"

defmt-testapp/README.md

@@ -0,0 +1,9 @@
+defmt Testapp
+======
+
+`defmt` is clunky to use without probe-rs and requires special configuration inside the
+`.cargo/config.toml` file.
+
+`probe-rs` is currently problematic for usage with the VA108xx , so it is not the default tool
+recommended and used for the whole workspace. This project contains an isolated, `defmt` compatible
+configuration for testing with `defmt` (and `probe-rs`).

defmt-testapp/src/lib.rs

@@ -0,0 +1,53 @@
+#![no_main]
+#![no_std]
+
+use cortex_m_semihosting::debug;
+
+use defmt_brtt as _; // global logger
+
+use va108xx_hal as _; // memory layout
+
+use panic_probe as _;
+
+// same panicking *behavior* as `panic-probe` but doesn't print a panic message
+// this prevents the panic message being printed *twice* when `defmt::panic` is invoked
+// #[defmt::panic_handler]
+/*
+fn panic() -> ! {
+    cortex_m::asm::udf()
+}
+*/
+
+/// Terminates the application and makes a semihosting-capable debug tool exit
+/// with status code 0.
+pub fn exit() -> ! {
+    loop {
+        debug::exit(debug::EXIT_SUCCESS);
+    }
+}
+
+/// Hardfault handler.
+///
+/// Terminates the application and makes a semihosting-capable debug tool exit
+/// with an error. This seems better than the default, which is to spin in a
+/// loop.
+#[cortex_m_rt::exception]
+unsafe fn HardFault(_frame: &cortex_m_rt::ExceptionFrame) -> ! {
+    loop {
+        debug::exit(debug::EXIT_FAILURE);
+    }
+}
+
+// defmt-test 0.3.0 has the limitation that this `#[tests]` attribute can only be used
+// once within a crate. the module can be in any file but there can only be at most
+// one `#[tests]` module in this library crate
+#[cfg(test)]
+#[defmt_test::tests]
+mod unit_tests {
+    use defmt::assert;
+
+    #[test]
+    fn it_works() {
+        assert!(true)
+    }
+}

defmt-testapp/src/main.rs

@@ -0,0 +1,29 @@
+//! Empty RTIC project template
+#![no_main]
+#![no_std]
+
+use defmt_testapp as _;
+
+#[rtic::app(device = pac)]
+mod app {
+    use va108xx_hal::pac;
+
+    #[local]
+    struct Local {}
+
+    #[shared]
+    struct Shared {}
+
+    #[init]
+    fn init(_ctx: init::Context) -> (Shared, Local) {
+        defmt::println!("-- Vorago RTIC template --");
+        (Shared {}, Local {})
+    }
+
+    // `shared` cannot be accessed from this context
+    #[idle]
+    fn idle(_cx: idle::Context) -> ! {
+        #[allow(clippy::empty_loop)]
+        loop {}
+    }
+}

examples/embassy/Cargo.toml

@@ -5,21 +5,14 @@ edition = "2021"
 
 [dependencies]
 cfg-if = "1"
-# cortex-m = { version = "0.7", features = ["critical-section-single-core"] }
+cortex-m = { version = "0.7", features = ["critical-section-single-core"] }
 cortex-m-rt = "0.7"
-# embedded-hal = "1"
+embedded-hal = "1"
-embedded-hal-async = "1"
-embedded-io = "0.6"
-embedded-io-async = "0.6"
-heapless = "0.8"
-static_cell = "2"
-
-defmt = "1"
-defmt-rtt = "0.4"
-panic-probe = { version = "0.3", features = ["print-defmt"] }
 
+rtt-target = "0.6"
+panic-rtt-target = "0.2"
 critical-section = "1"
-# portable-atomic = { version = "1", features = ["unsafe-assume-single-core"]}
+portable-atomic = { version = "1", features = ["unsafe-assume-single-core"]}
 
 embassy-sync = "0.6"
 embassy-time = "0.4"
@@ -29,14 +22,11 @@ embassy-executor = { version = "0.7", features = [
   "executor-interrupt"
 ]}
 
-va108xx-hal = { version = "0.11", path = "../../va108xx-hal", features = ["defmt"] }
+va108xx-hal = { path = "../../va108xx-hal" }
-va108xx-embassy = { version = "0.2", path = "../../va108xx-embassy" }
+va108xx-embassy = { path = "../../va108xx-embassy", default-features = false }
 
 [features]
 default = ["ticks-hz-1_000", "va108xx-embassy/irq-oc30-oc31"]
 custom-irqs = []
 ticks-hz-1_000 = ["embassy-time/tick-hz-1_000"]
 ticks-hz-32_768 = ["embassy-time/tick-hz-32_768"]
-
-[package.metadata.cargo-machete]
-ignored = ["cortex-m-rt"]

examples/embassy/src/bin/async-gpio.rs

@@ -1,247 +0,0 @@
-//! This example demonstrates the usage of async GPIO operations on VA108xx.
-//!
-//! You need to tie the PA0 to the PA1 pin for this example to work. You can optionally tie the PB22 to PB23 pins well
-//! and then set the `CHECK_PB22_TO_PB23` to true to also test async operations on Port B.
-#![no_std]
-#![no_main]
-// This imports the logger and the panic handler.
-use embassy_example as _;
-
-use embassy_executor::Spawner;
-use embassy_sync::channel::{Receiver, Sender};
-use embassy_sync::{blocking_mutex::raw::ThreadModeRawMutex, channel::Channel};
-use embassy_time::{Duration, Instant, Timer};
-use embedded_hal_async::digital::Wait;
-use va108xx_hal::gpio::asynch::{on_interrupt_for_async_gpio_for_port, InputPinAsync};
-use va108xx_hal::gpio::{Input, Output, PinState, Port};
-use va108xx_hal::pins::{PinsA, PinsB};
-use va108xx_hal::{
-    pac::{self, interrupt},
-    prelude::*,
-};
-
-const SYSCLK_FREQ: Hertz = Hertz::from_raw(50_000_000);
-
-const CHECK_PA0_TO_PA1: bool = true;
-const CHECK_PB22_TO_PB23: bool = false;
-
-// Can also be set to OC10 and works as well.
-const PB22_TO_PB23_IRQ: pac::Interrupt = pac::Interrupt::OC11;
-
-#[derive(Clone, Copy)]
-pub struct GpioCmd {
-    cmd_type: GpioCmdType,
-    after_delay: u32,
-}
-
-impl GpioCmd {
-    pub fn new(cmd_type: GpioCmdType, after_delay: u32) -> Self {
-        Self {
-            cmd_type,
-            after_delay,
-        }
-    }
-}
-
-#[derive(Clone, Copy)]
-pub enum GpioCmdType {
-    SetHigh,
-    SetLow,
-    RisingEdge,
-    FallingEdge,
-}
-
-// Declare a bounded channel of 3 u32s.
-static CHANNEL_PA0_PA1: Channel<ThreadModeRawMutex, GpioCmd, 3> = Channel::new();
-static CHANNEL_PB22_TO_PB23: Channel<ThreadModeRawMutex, GpioCmd, 3> = Channel::new();
-
-#[embassy_executor::main]
-async fn main(spawner: Spawner) {
-    defmt::println!("-- VA108xx Async GPIO Demo --");
-
-    let dp = pac::Peripherals::take().unwrap();
-
-    // Safety: Only called once here.
-    va108xx_embassy::init(dp.tim23, dp.tim22, SYSCLK_FREQ);
-
-    let porta = PinsA::new(dp.porta);
-    let portb = PinsB::new(dp.portb);
-    let mut led0 = Output::new(porta.pa10, PinState::Low);
-    let out_pa0 = Output::new(porta.pa0, PinState::Low);
-    let in_pa1 = Input::new_floating(porta.pa1);
-    let out_pb22 = Output::new(portb.pb22, PinState::Low);
-    let in_pb23 = Input::new_floating(portb.pb23);
-
-    let in_pa1_async = InputPinAsync::new(in_pa1, pac::Interrupt::OC10);
-    let in_pb23_async = InputPinAsync::new(in_pb23, PB22_TO_PB23_IRQ);
-
-    spawner
-        .spawn(output_task(
-            "PA0 to PA1",
-            out_pa0,
-            CHANNEL_PA0_PA1.receiver(),
-        ))
-        .unwrap();
-    spawner
-        .spawn(output_task(
-            "PB22 to PB23",
-            out_pb22,
-            CHANNEL_PB22_TO_PB23.receiver(),
-        ))
-        .unwrap();
-
-    if CHECK_PA0_TO_PA1 {
-        check_pin_to_pin_async_ops("PA0 to PA1", CHANNEL_PA0_PA1.sender(), in_pa1_async).await;
-        defmt::info!("Example PA0 to PA1 done");
-    }
-    if CHECK_PB22_TO_PB23 {
-        check_pin_to_pin_async_ops("PB22 to PB23", CHANNEL_PB22_TO_PB23.sender(), in_pb23_async)
-            .await;
-        defmt::info!("Example PB22 to PB23 done");
-    }
-
-    defmt::info!("Example done, toggling LED0");
-    loop {
-        led0.toggle();
-        Timer::after(Duration::from_millis(500)).await;
-    }
-}
-
-async fn check_pin_to_pin_async_ops(
-    ctx: &'static str,
-    sender: Sender<'static, ThreadModeRawMutex, GpioCmd, 3>,
-    mut async_input: impl Wait,
-) {
-    defmt::info!(
-        "{}: sending SetHigh command ({} ms)",
-        ctx,
-        Instant::now().as_millis()
-    );
-    sender.send(GpioCmd::new(GpioCmdType::SetHigh, 20)).await;
-    async_input.wait_for_high().await.unwrap();
-    defmt::info!(
-        "{}: Input pin is high now ({} ms)",
-        ctx,
-        Instant::now().as_millis()
-    );
-
-    defmt::info!(
-        "{}: sending SetLow command ({} ms)",
-        ctx,
-        Instant::now().as_millis()
-    );
-    sender.send(GpioCmd::new(GpioCmdType::SetLow, 20)).await;
-    async_input.wait_for_low().await.unwrap();
-    defmt::info!(
-        "{}: Input pin is low now ({} ms)",
-        ctx,
-        Instant::now().as_millis()
-    );
-
-    defmt::info!(
-        "{}: sending RisingEdge command ({} ms)",
-        ctx,
-        Instant::now().as_millis()
-    );
-    sender.send(GpioCmd::new(GpioCmdType::RisingEdge, 20)).await;
-    async_input.wait_for_rising_edge().await.unwrap();
-    defmt::info!(
-        "{}: input pin had rising edge ({} ms)",
-        ctx,
-        Instant::now().as_millis()
-    );
-
-    defmt::info!(
-        "{}: sending Falling command ({} ms)",
-        ctx,
-        Instant::now().as_millis()
-    );
-    sender
-        .send(GpioCmd::new(GpioCmdType::FallingEdge, 20))
-        .await;
-    async_input.wait_for_falling_edge().await.unwrap();
-    defmt::info!(
-        "{}: input pin had a falling edge ({} ms)",
-        ctx,
-        Instant::now().as_millis()
-    );
-
-    defmt::info!(
-        "{}: sending Falling command ({} ms)",
-        ctx,
-        Instant::now().as_millis()
-    );
-    sender
-        .send(GpioCmd::new(GpioCmdType::FallingEdge, 20))
-        .await;
-    async_input.wait_for_any_edge().await.unwrap();
-    defmt::info!(
-        "{}: input pin had a falling (any) edge ({} ms)",
-        ctx,
-        Instant::now().as_millis()
-    );
-
-    defmt::info!(
-        "{}: sending Falling command ({} ms)",
-        ctx,
-        Instant::now().as_millis()
-    );
-    sender.send(GpioCmd::new(GpioCmdType::RisingEdge, 20)).await;
-    async_input.wait_for_any_edge().await.unwrap();
-    defmt::info!(
-        "{}: input pin had a rising (any) edge ({} ms)",
-        ctx,
-        Instant::now().as_millis()
-    );
-}
-
-#[embassy_executor::task(pool_size = 2)]
-async fn output_task(
-    ctx: &'static str,
-    mut out: Output,
-    receiver: Receiver<'static, ThreadModeRawMutex, GpioCmd, 3>,
-) {
-    loop {
-        let next_cmd = receiver.receive().await;
-        Timer::after(Duration::from_millis(next_cmd.after_delay.into())).await;
-        match next_cmd.cmd_type {
-            GpioCmdType::SetHigh => {
-                defmt::info!("{}: Set output high", ctx);
-                out.set_high();
-            }
-            GpioCmdType::SetLow => {
-                defmt::info!("{}: Set output low", ctx);
-                out.set_low();
-            }
-            GpioCmdType::RisingEdge => {
-                defmt::info!("{}: Rising edge", ctx);
-                if !out.is_set_low() {
-                    out.set_low();
-                }
-                out.set_high();
-            }
-            GpioCmdType::FallingEdge => {
-                defmt::info!("{}: Falling edge", ctx);
-                if !out.is_set_high() {
-                    out.set_high();
-                }
-                out.set_low();
-            }
-        }
-    }
-}
-
-// PB22 to PB23 can be handled by both OC10 and OC11 depending on configuration.
-#[interrupt]
-#[allow(non_snake_case)]
-fn OC10() {
-    on_interrupt_for_async_gpio_for_port(Port::A);
-    on_interrupt_for_async_gpio_for_port(Port::B);
-}
-
-// This interrupt only handles PORT B interrupts.
-#[interrupt]
-#[allow(non_snake_case)]
-fn OC11() {
-    on_interrupt_for_async_gpio_for_port(Port::B);
-}

examples/embassy/src/bin/async-uart-rx.rs

@@ -1,163 +0,0 @@
-//! Asynchronous UART reception example application.
-//!
-//! This application receives data on two UARTs permanently using a ring buffer.
-//! The ring buffer are read them asynchronously. UART A is received on ports PA8 and PA9.
-//! UART B is received on ports PA2 and PA3.
-//!
-//! Instructions:
-//!
-//! 1. Tie a USB to UART converter with RX to PA9 and TX to PA8 for UART A.
-//!    Tie a USB to UART converter with RX to PA3 and TX to PA2 for UART B.
-//! 2. Connect to the serial interface by using an application like Putty or picocom. You can
-//!    type something in the terminal and check if the data is echoed back. You can also check the
-//!    RTT logs to see received data.
-#![no_std]
-#![no_main]
-// This imports the logger and the panic handler.
-use embassy_example as _;
-
-use core::cell::RefCell;
-use critical_section::Mutex;
-use embassy_executor::Spawner;
-use embassy_time::Instant;
-use embedded_io::Write;
-use embedded_io_async::Read;
-use heapless::spsc::{Consumer, Producer, Queue};
-use va108xx_hal::{
-    gpio::{Output, PinState},
-    pac::{self, interrupt},
-    pins::PinsA,
-    prelude::*,
-    uart::{
-        self, on_interrupt_rx_overwriting,
-        rx_asynch::{on_interrupt_rx, RxAsync},
-        Bank, RxAsyncOverwriting, Tx,
-    },
-    InterruptConfig,
-};
-
-const SYSCLK_FREQ: Hertz = Hertz::from_raw(50_000_000);
-
-static QUEUE_UART_A: static_cell::ConstStaticCell<Queue<u8, 256>> =
-    static_cell::ConstStaticCell::new(Queue::new());
-static PRODUCER_UART_A: Mutex<RefCell<Option<Producer<u8, 256>>>> = Mutex::new(RefCell::new(None));
-
-static QUEUE_UART_B: static_cell::ConstStaticCell<Queue<u8, 256>> =
-    static_cell::ConstStaticCell::new(Queue::new());
-static PRODUCER_UART_B: Mutex<RefCell<Option<Producer<u8, 256>>>> = Mutex::new(RefCell::new(None));
-static CONSUMER_UART_B: Mutex<RefCell<Option<Consumer<u8, 256>>>> = Mutex::new(RefCell::new(None));
-
-// main is itself an async function.
-#[embassy_executor::main]
-async fn main(spawner: Spawner) {
-    defmt::println!("-- VA108xx Async UART RX Demo --");
-
-    let dp = pac::Peripherals::take().unwrap();
-
-    // Safety: Only called once here.
-    va108xx_embassy::init(dp.tim23, dp.tim22, SYSCLK_FREQ);
-
-    let porta = PinsA::new(dp.porta);
-    let mut led0 = Output::new(porta.pa10, PinState::Low);
-    let mut led1 = Output::new(porta.pa7, PinState::Low);
-    let mut led2 = Output::new(porta.pa6, PinState::Low);
-
-    let tx_uart_a = porta.pa9;
-    let rx_uart_a = porta.pa8;
-
-    let uarta = uart::Uart::new_with_interrupt(
-        dp.uarta,
-        tx_uart_a,
-        rx_uart_a,
-        50.MHz(),
-        115200.Hz().into(),
-        InterruptConfig::new(pac::Interrupt::OC2, true, true),
-    )
-    .unwrap();
-
-    let tx_uart_b = porta.pa3;
-    let rx_uart_b = porta.pa2;
-
-    let uartb = uart::Uart::new_with_interrupt(
-        dp.uartb,
-        tx_uart_b,
-        rx_uart_b,
-        50.MHz(),
-        115200.Hz().into(),
-        InterruptConfig::new(pac::Interrupt::OC3, true, true),
-    )
-    .unwrap();
-    let (mut tx_uart_a, rx_uart_a) = uarta.split();
-    let (tx_uart_b, rx_uart_b) = uartb.split();
-    let (prod_uart_a, cons_uart_a) = QUEUE_UART_A.take().split();
-    // Pass the producer to the interrupt handler.
-    let (prod_uart_b, cons_uart_b) = QUEUE_UART_B.take().split();
-    critical_section::with(|cs| {
-        *PRODUCER_UART_A.borrow(cs).borrow_mut() = Some(prod_uart_a);
-        *PRODUCER_UART_B.borrow(cs).borrow_mut() = Some(prod_uart_b);
-        *CONSUMER_UART_B.borrow(cs).borrow_mut() = Some(cons_uart_b);
-    });
-    let mut async_rx_uart_a = RxAsync::new(rx_uart_a, cons_uart_a);
-    let async_rx_uart_b = RxAsyncOverwriting::new(rx_uart_b, &CONSUMER_UART_B);
-    spawner
-        .spawn(uart_b_task(async_rx_uart_b, tx_uart_b))
-        .unwrap();
-    let mut buf = [0u8; 256];
-    loop {
-        defmt::info!("Current time UART A: {}", Instant::now().as_secs());
-        led0.toggle();
-        led1.toggle();
-        led2.toggle();
-        let read_bytes = async_rx_uart_a.read(&mut buf).await.unwrap();
-        let read_str = core::str::from_utf8(&buf[..read_bytes]).unwrap();
-        defmt::info!(
-            "Read {} bytes asynchronously on UART A: {:?}",
-            read_bytes,
-            read_str
-        );
-        tx_uart_a.write_all(read_str.as_bytes()).unwrap();
-    }
-}
-
-#[embassy_executor::task]
-async fn uart_b_task(mut async_rx: RxAsyncOverwriting<256>, mut tx: Tx) {
-    let mut buf = [0u8; 256];
-    loop {
-        defmt::info!("Current time UART B: {}", Instant::now().as_secs());
-        // Infallible asynchronous operation.
-        let read_bytes = async_rx.read(&mut buf).await.unwrap();
-        let read_str = core::str::from_utf8(&buf[..read_bytes]).unwrap();
-        defmt::info!(
-            "Read {} bytes asynchronously on UART B: {:?}",
-            read_bytes,
-            read_str
-        );
-        tx.write_all(read_str.as_bytes()).unwrap();
-    }
-}
-
-#[interrupt]
-#[allow(non_snake_case)]
-fn OC2() {
-    let mut prod =
-        critical_section::with(|cs| PRODUCER_UART_A.borrow(cs).borrow_mut().take().unwrap());
-    let errors = on_interrupt_rx(Bank::Uart0, &mut prod);
-    critical_section::with(|cs| *PRODUCER_UART_A.borrow(cs).borrow_mut() = Some(prod));
-    // In a production app, we could use a channel to send the errors to the main task.
-    if let Err(errors) = errors {
-        defmt::info!("UART A errors: {:?}", errors);
-    }
-}
-
-#[interrupt]
-#[allow(non_snake_case)]
-fn OC3() {
-    let mut prod =
-        critical_section::with(|cs| PRODUCER_UART_B.borrow(cs).borrow_mut().take().unwrap());
-    let errors = on_interrupt_rx_overwriting(Bank::Uart1, &mut prod, &CONSUMER_UART_B);
-    critical_section::with(|cs| *PRODUCER_UART_B.borrow(cs).borrow_mut() = Some(prod));
-    // In a production app, we could use a channel to send the errors to the main task.
-    if let Err(errors) = errors {
-        defmt::info!("UART B errors: {:?}", errors);
-    }
-}

examples/embassy/src/bin/async-uart-tx.rs

@@ -1,90 +0,0 @@
-//! Asynchronous UART transmission example application.
-//!
-//! This application receives sends 4 strings with different sizes permanently using UART A.
-//! Ports PA8 and PA9 are used for this.
-//!
-//! Instructions:
-//!
-//! 1. Tie a USB to UART converter with RX to PA9 and TX to PA8 for UART A.
-//! 2. Connect to the serial interface by using an application like Putty or picocom. You can
-//!    can verify the correctness of the sent strings.
-#![no_std]
-#![no_main]
-// This imports the logger and the panic handler.
-use embassy_example as _;
-
-use embassy_executor::Spawner;
-use embassy_time::{Duration, Instant, Ticker};
-use embedded_io_async::Write;
-use va108xx_hal::{
-    gpio::{Output, PinState},
-    pac::{self, interrupt},
-    pins::PinsA,
-    prelude::*,
-    uart::{self, on_interrupt_tx, Bank, TxAsync},
-    InterruptConfig,
-};
-
-const SYSCLK_FREQ: Hertz = Hertz::from_raw(50_000_000);
-
-const STR_LIST: &[&str] = &[
-    "Hello World\r\n",
-    "Smoll\r\n",
-    "A string which is larger than the FIFO size\r\n",
-    "A really large string which is significantly larger than the FIFO size\r\n",
-];
-
-// main is itself an async function.
-#[embassy_executor::main]
-async fn main(_spawner: Spawner) {
-    defmt::println!("-- VA108xx Async UART TX Demo --");
-
-    let dp = pac::Peripherals::take().unwrap();
-
-    // Safety: Only called once here.
-    va108xx_embassy::init(dp.tim23, dp.tim22, SYSCLK_FREQ);
-
-    let porta = PinsA::new(dp.porta);
-
-    let mut led0 = Output::new(porta.pa10, PinState::Low);
-    let mut led1 = Output::new(porta.pa7, PinState::Low);
-    let mut led2 = Output::new(porta.pa6, PinState::Low);
-
-    let tx = porta.pa9;
-    let rx = porta.pa8;
-
-    let uarta = uart::Uart::new_with_interrupt(
-        dp.uarta,
-        tx,
-        rx,
-        50.MHz(),
-        115200.Hz().into(),
-        InterruptConfig::new(pac::Interrupt::OC2, true, true),
-    )
-    .unwrap();
-    let (tx, _rx) = uarta.split();
-    let mut async_tx = TxAsync::new(tx);
-    let mut ticker = Ticker::every(Duration::from_secs(1));
-    let mut idx = 0;
-    loop {
-        defmt::info!("Current time: {}", Instant::now().as_secs());
-        led0.toggle();
-        led1.toggle();
-        led2.toggle();
-        let _written = async_tx
-            .write(STR_LIST[idx].as_bytes())
-            .await
-            .expect("writing failed");
-        idx += 1;
-        if idx == STR_LIST.len() {
-            idx = 0;
-        }
-        ticker.next().await;
-    }
-}
-
-#[interrupt]
-#[allow(non_snake_case)]
-fn OC2() {
-    on_interrupt_tx(Bank::Uart0);
-}

examples/embassy/src/lib.rs

@@ -1,3 +0,0 @@
-#![no_std]
-use defmt_rtt as _;
-use panic_probe as _;

examples/embassy/src/main.rs

@@ -1,8 +1,11 @@
 #![no_std]
 #![no_main]
-use embassy_example as _;
 use embassy_executor::Spawner;
 use embassy_time::{Duration, Instant, Ticker};
+use embedded_hal::digital::StatefulOutputPin;
+use panic_rtt_target as _;
+use rtt_target::{rprintln, rtt_init_print};
+use va108xx_embassy::embassy;
 
 cfg_if::cfg_if! {
     if #[cfg(feature = "custom-irqs")] {
@@ -12,51 +15,53 @@ cfg_if::cfg_if! {
     }
 }
 
-use va108xx_hal::{
+use va108xx_hal::{gpio::PinsA, pac, prelude::*};
-    gpio::{Output, PinState},
-    pac,
-    pins::PinsA,
-    prelude::*,
-};
 
 const SYSCLK_FREQ: Hertz = Hertz::from_raw(50_000_000);
 
 // main is itself an async function.
 #[embassy_executor::main]
 async fn main(_spawner: Spawner) {
-    defmt::println!("-- VA108xx Embassy Demo --");
+    rtt_init_print!();
+    rprintln!("-- VA108xx Embassy Demo --");
 
-    let dp = pac::Peripherals::take().unwrap();
+    let mut dp = pac::Peripherals::take().unwrap();
 
     // Safety: Only called once here.
+    unsafe {
         cfg_if::cfg_if! {
             if #[cfg(not(feature = "custom-irqs"))] {
-            va108xx_embassy::init(
+                embassy::init(
+                    &mut dp.sysconfig,
+                    &dp.irqsel,
+                    SYSCLK_FREQ,
                     dp.tim23,
                     dp.tim22,
-                SYSCLK_FREQ,
                 );
             } else {
-            va108xx_embassy::init_with_custom_irqs(
+                embassy::init_with_custom_irqs(
+                    &mut dp.sysconfig,
+                    &dp.irqsel,
+                    SYSCLK_FREQ,
                     dp.tim23,
                     dp.tim22,
-                SYSCLK_FREQ,
                     pac::Interrupt::OC23,
                     pac::Interrupt::OC24,
                 );
             }
         }
+    }
 
-    let porta = PinsA::new(dp.porta);
+    let porta = PinsA::new(&mut dp.sysconfig, Some(dp.ioconfig), dp.porta);
-    let mut led0 = Output::new(porta.pa10, PinState::Low);
+    let mut led0 = porta.pa10.into_readable_push_pull_output();
-    let mut led1 = Output::new(porta.pa7, PinState::Low);
+    let mut led1 = porta.pa7.into_readable_push_pull_output();
-    let mut led2 = Output::new(porta.pa6, PinState::Low);
+    let mut led2 = porta.pa6.into_readable_push_pull_output();
     let mut ticker = Ticker::every(Duration::from_secs(1));
     loop {
         ticker.next().await;
-        defmt::info!("Current time: {}", Instant::now().as_secs());
+        rprintln!("Current time: {}", Instant::now().as_secs());
-        led0.toggle();
+        led0.toggle().ok();
-        led1.toggle();
+        led1.toggle().ok();
-        led2.toggle();
+        led2.toggle().ok();
     }
 }

examples/rtic/Cargo.toml

@@ -5,13 +5,22 @@ edition = "2021"
 
 [dependencies]
 cortex-m = { version = "0.7", features = ["critical-section-single-core"] }
+cortex-m-rt = "0.7"
+embedded-hal = "1"
 embedded-io = "0.6"
-defmt-rtt = "0.4"
+rtt-target = "0.6"
-defmt = "1"
+panic-rtt-target = "0.2"
-panic-probe = { version = "1", features = ["defmt"] }
+
+# Even though we do not use this directly, we need to activate this feature explicitely
+# so that RTIC compiles because thumv6 does not have CAS operations natively.
+portable-atomic = { version = "1", features = ["unsafe-assume-single-core"]}
+
 rtic = { version = "2", features = ["thumbv6-backend"] }
 rtic-monotonics = { version = "2", features = ["cortex-m-systick"] }
+rtic-sync = { version = "1.3", features = ["defmt-03"] }
+
+once_cell = {version = "1", default-features = false, features = ["critical-section"]}
 ringbuf = { version = "0.4.7", default-features = false, features = ["portable-atomic"] }
 
-va108xx-hal = { version = "0.11", path = "../../va108xx-hal" }
+va108xx-hal = "0.8"
-vorago-reb1 = { version = "0.8", path = "../../vorago-reb1" }
+vorago-reb1 = { path = "../../vorago-reb1" }

examples/rtic/src/bin/blinky-button-rtic.rs

@@ -4,29 +4,34 @@
 
 #[rtic::app(device = pac)]
 mod app {
+    use panic_rtt_target as _;
     use rtic_example::SYSCLK_FREQ;
-    // Import panic provider.
+    use rtt_target::{rprintln, rtt_init_default, set_print_channel};
-    use panic_probe as _;
-    // Import global logger.
-    use defmt_rtt as _;
     use va108xx_hal::{
         clock::{set_clk_div_register, FilterClkSel},
-        gpio::{FilterType, InterruptEdge},
+        gpio::{FilterType, InterruptEdge, PinsA},
         pac,
-        pins::PinsA,
+        prelude::*,
-        timer::InterruptConfig,
+        timer::{default_ms_irq_handler, set_up_ms_tick, IrqCfg},
     };
     use vorago_reb1::button::Button;
     use vorago_reb1::leds::Leds;
 
     rtic_monotonics::systick_monotonic!(Mono, 1_000);
 
-    #[derive(Debug, PartialEq, defmt::Format)]
+    #[derive(Debug, PartialEq)]
     pub enum PressMode {
         Toggle,
         Keep,
     }
 
+    #[derive(Debug, PartialEq)]
+    pub enum CfgMode {
+        Prompt,
+        Fixed,
+    }
+
+    const CFG_MODE: CfgMode = CfgMode::Fixed;
     // You can change the press mode here
     const DEFAULT_MODE: PressMode = PressMode::Toggle;
 
@@ -42,35 +47,54 @@ mod app {
 
     #[init]
     fn init(cx: init::Context) -> (Shared, Local) {
-        defmt::println!("-- Vorago Button IRQ Example --");
+        let channels = rtt_init_default!();
+        set_print_channel(channels.up.0);
+        rprintln!("-- Vorago Button IRQ Example --");
         Mono::start(cx.core.SYST, SYSCLK_FREQ.raw());
 
-        let mode = DEFAULT_MODE;
+        let mode = match CFG_MODE {
-        defmt::info!("Using {:?} mode", mode);
+            // Ask mode from user via RTT
+            CfgMode::Prompt => prompt_mode(channels.down.0),
+            // Use mode hardcoded in `DEFAULT_MODE`
+            CfgMode::Fixed => DEFAULT_MODE,
+        };
+        rprintln!("Using {:?} mode", mode);
 
         let mut dp = cx.device;
-        let pinsa = PinsA::new(dp.porta);
+        let pinsa = PinsA::new(&mut dp.sysconfig, Some(dp.ioconfig), dp.porta);
         let edge_irq = match mode {
             PressMode::Toggle => InterruptEdge::HighToLow,
             PressMode::Keep => InterruptEdge::BothEdges,
         };
 
         // Configure an edge interrupt on the button and route it to interrupt vector 15
-        let mut button = Button::new(pinsa.pa11);
+        let mut button = Button::new(pinsa.pa11.into_floating_input()).edge_irq(
+            edge_irq,
+            IrqCfg::new(pac::interrupt::OC15, true, true),
+            Some(&mut dp.sysconfig),
+            Some(&mut dp.irqsel),
+        );
 
         if mode == PressMode::Toggle {
             // This filter debounces the switch for edge based interrupts
-            button.configure_filter_type(FilterType::FilterFourCycles, FilterClkSel::Clk1);
+            button = button.filter_type(FilterType::FilterFourClockCycles, FilterClkSel::Clk1);
             set_clk_div_register(&mut dp.sysconfig, FilterClkSel::Clk1, 50_000);
         }
-        button.configure_and_enable_edge_interrupt(
+        let mut leds = Leds::new(
-            edge_irq,
+            pinsa.pa10.into_push_pull_output(),
-            InterruptConfig::new(pac::interrupt::OC15, true, true),
+            pinsa.pa7.into_push_pull_output(),
+            pinsa.pa6.into_push_pull_output(),
         );
-        let mut leds = Leds::new(pinsa.pa10, pinsa.pa7, pinsa.pa6);
         for led in leds.iter_mut() {
             led.off();
         }
+        set_up_ms_tick(
+            IrqCfg::new(pac::Interrupt::OC0, true, true),
+            &mut dp.sysconfig,
+            Some(&mut dp.irqsel),
+            50.MHz(),
+            dp.tim0,
+        );
         (Shared {}, Local { leds, button, mode })
     }
 
@@ -95,4 +119,26 @@ mod app {
             leds[0].on();
         }
     }
+
+    #[task(binds = OC0)]
+    fn ms_tick(_cx: ms_tick::Context) {
+        default_ms_irq_handler();
+    }
+
+    fn prompt_mode(mut down_channel: rtt_target::DownChannel) -> PressMode {
+        rprintln!("Using prompt mode");
+        rprintln!("Please enter the mode [0: Toggle, 1: Keep]");
+        let mut read_buf: [u8; 16] = [0; 16];
+        let mut read;
+        loop {
+            read = down_channel.read(&mut read_buf);
+            for &byte in &read_buf[..read] {
+                match byte as char {
+                    '0' => return PressMode::Toggle,
+                    '1' => return PressMode::Keep,
+                    _ => continue, // Ignore other characters
+                }
+            }
+        }
+    }
 }

examples/rtic/src/bin/rtic-empty.rs

@@ -4,10 +4,8 @@
 
 #[rtic::app(device = pac)]
 mod app {
-    // Import panic provider.
+    use panic_rtt_target as _;
-    use panic_probe as _;
+    use rtt_target::{rprintln, rtt_init_default};
-    // Import global logger.
-    use defmt_rtt as _;
     use va108xx_hal::pac;
 
     #[local]
@@ -18,7 +16,8 @@ mod app {
 
     #[init]
     fn init(_ctx: init::Context) -> (Shared, Local) {
-        defmt::println!("-- Vorago RTIC template --");
+        rtt_init_default!();
+        rprintln!("-- Vorago RTIC template --");
         (Shared {}, Local {})
     }
 

examples/rtic/src/bin/uart-echo-rtic.rs

@@ -1,4 +1,4 @@
-//! More complex UART application on UART PA8 (TX) and PA9 (RX).
+//! More complex UART application
 //!
 //! Uses the IRQ capabilities of the VA10820 peripheral and the RTIC framework to poll the UART in
 //! a non-blocking way. All received data will be sent back to the sender.
@@ -14,25 +14,22 @@ const RX_RING_BUF_SIZE: usize = 1024;
 mod app {
     use super::*;
     use embedded_io::Write;
+    use panic_rtt_target as _;
     use ringbuf::traits::{Consumer, Observer, Producer};
     use rtic_example::SYSCLK_FREQ;
-    // Import panic provider.
-    use panic_probe as _;
-    // Import global logger.
-    use defmt_rtt as _;
     use rtic_monotonics::Monotonic;
+    use rtt_target::{rprintln, rtt_init_print};
     use va108xx_hal::{
+        gpio::PinsA,
         pac,
-        pins::PinsA,
         prelude::*,
-        uart::{self, RxWithInterrupt, Tx},
+        uart::{self, RxWithIrq, Tx},
-        InterruptConfig,
     };
 
     #[local]
     struct Local {
-        rx: RxWithInterrupt,
+        rx: RxWithIrq<pac::Uarta>,
-        tx: Tx,
+        tx: Tx<pac::Uarta>,
     }
 
     #[shared]
@@ -44,26 +41,25 @@ mod app {
 
     #[init]
     fn init(cx: init::Context) -> (Shared, Local) {
-        defmt::println!("-- VA108xx UART Echo with IRQ example application--");
+        rtt_init_print!();
+        rprintln!("-- VA108xx UART Echo with IRQ example application--");
 
         Mono::start(cx.core.SYST, SYSCLK_FREQ.raw());
 
-        let dp = cx.device;
+        let mut dp = cx.device;
-        let gpioa = PinsA::new(dp.porta);
+        let gpioa = PinsA::new(&mut dp.sysconfig, Some(dp.ioconfig), dp.porta);
-        let tx = gpioa.pa9;
+        let tx = gpioa.pa9.into_funsel_2();
-        let rx = gpioa.pa8;
+        let rx = gpioa.pa8.into_funsel_2();
 
-        let irq_uart = uart::Uart::new_with_interrupt(
+        let irq_uart = uart::Uart::new(
-            dp.uarta,
+            &mut dp.sysconfig,
-            tx,
-            rx,
             SYSCLK_FREQ,
-            115200.Hz().into(),
+            dp.uarta,
-            InterruptConfig::new(pac::Interrupt::OC3, true, true),
+            (tx, rx),
-        )
+            115200.Hz(),
-        .unwrap();
+        );
         let (tx, rx) = irq_uart.split();
-        let mut rx = rx.into_rx_with_irq();
+        let mut rx = rx.into_rx_with_irq(&mut dp.sysconfig, &mut dp.irqsel, pac::interrupt::OC3);
 
         rx.start();
 
@@ -94,7 +90,7 @@ mod app {
     fn reception_task(mut cx: reception_task::Context) {
         let mut buf: [u8; 16] = [0; 16];
         let mut ringbuf_full = false;
-        let result = cx.local.rx.on_interrupt(&mut buf);
+        let result = cx.local.rx.irq_handler(&mut buf);
         if result.bytes_read > 0 && result.errors.is_none() {
             cx.shared.rb.lock(|rb| {
                 if rb.vacant_len() < result.bytes_read {
@@ -106,7 +102,7 @@ mod app {
         }
         if ringbuf_full {
             // Could also drop oldest data, but that would require the consumer to be shared.
-            defmt::println!("buffer full, data was dropped");
+            rprintln!("buffer full, data was dropped");
         }
     }
 

examples/rtic/src/main.rs

@@ -5,24 +5,22 @@
 #[rtic::app(device = pac, dispatchers = [OC31, OC30, OC29])]
 mod app {
     use cortex_m::asm;
+    use embedded_hal::digital::StatefulOutputPin;
+    use panic_rtt_target as _;
     use rtic_example::SYSCLK_FREQ;
     use rtic_monotonics::systick::prelude::*;
     use rtic_monotonics::Monotonic;
-    // Import panic provider.
+    use rtt_target::{rprintln, rtt_init_print};
-    use panic_probe as _;
-    // Import global logger.
-    use defmt_rtt as _;
     use va108xx_hal::{
-        gpio::{Output, PinState},
+        gpio::{OutputReadablePushPull, Pin, PinsA, PA10, PA6, PA7},
         pac,
-        pins::PinsA,
     };
 
     #[local]
     struct Local {
-        led0: Output,
+        led0: Pin<PA10, OutputReadablePushPull>,
-        led1: Output,
+        led1: Pin<PA7, OutputReadablePushPull>,
-        led2: Output,
+        led2: Pin<PA6, OutputReadablePushPull>,
     }
 
     #[shared]
@@ -31,15 +29,20 @@ mod app {
     rtic_monotonics::systick_monotonic!(Mono, 1_000);
 
     #[init]
-    fn init(cx: init::Context) -> (Shared, Local) {
+    fn init(mut cx: init::Context) -> (Shared, Local) {
-        defmt::println!("-- Vorago VA108xx RTIC template --");
+        rtt_init_print!();
+        rprintln!("-- Vorago VA108xx RTIC template --");
 
         Mono::start(cx.core.SYST, SYSCLK_FREQ.raw());
 
-        let porta = PinsA::new(cx.device.porta);
+        let porta = PinsA::new(
-        let led0 = Output::new(porta.pa10, PinState::Low);
+            &mut cx.device.sysconfig,
-        let led1 = Output::new(porta.pa7, PinState::Low);
+            Some(cx.device.ioconfig),
-        let led2 = Output::new(porta.pa6, PinState::Low);
+            cx.device.porta,
+        );
+        let led0 = porta.pa10.into_readable_push_pull_output();
+        let led1 = porta.pa7.into_readable_push_pull_output();
+        let led2 = porta.pa6.into_readable_push_pull_output();
         blinky::spawn().ok();
         (Shared {}, Local { led0, led1, led2 })
     }
@@ -58,10 +61,10 @@ mod app {
     )]
     async fn blinky(cx: blinky::Context) {
         loop {
-            defmt::println!("toggling LEDs");
+            rprintln!("toggling LEDs");
-            cx.local.led0.toggle();
+            cx.local.led0.toggle().ok();
-            cx.local.led1.toggle();
+            cx.local.led1.toggle().ok();
-            cx.local.led2.toggle();
+            cx.local.led2.toggle().ok();
             Mono::delay(1000.millis()).await;
         }
     }

examples/simple/Cargo.toml

@@ -7,15 +7,17 @@ edition = "2021"
 cortex-m = {version = "0.7", features = ["critical-section-single-core"]}
 cortex-m-rt = "0.7"
 panic-halt = "1"
-defmt-rtt = "0.4"
+panic-rtt-target = "0.2"
-defmt = "1"
+critical-section = "1"
-panic-probe = { version = "1", features = ["defmt"] }
+rtt-target = "0.6"
 embedded-hal = "1"
 embedded-hal-nb = "1"
 embedded-io = "0.6"
-portable-atomic = { version = "1", features = ["unsafe-assume-single-core"] }
+cortex-m-semihosting = "0.5.0"
 
 [dependencies.va108xx-hal]
-version = "0.11"
+version = "0.8"
-path = "../../va108xx-hal"
+features = ["rt", "defmt"]
-features = ["defmt"]
+
+[dependencies.vorago-reb1]
+path = "../../vorago-reb1"

examples/simple/examples/blinky.rs

@@ -7,40 +7,58 @@
 #![no_std]
 
 use cortex_m_rt::entry;
-use embedded_hal::delay::DelayNs;
+use embedded_hal::{
+    delay::DelayNs,
+    digital::{OutputPin, StatefulOutputPin},
+};
 use panic_halt as _;
 use va108xx_hal::{
-    gpio::{Output, PinState},
+    gpio::PinsA,
-    pac::{self},
+    pac::{self, interrupt},
-    pins::PinsA,
     prelude::*,
-    timer::CountdownTimer,
+    timer::DelayMs,
+    timer::{default_ms_irq_handler, set_up_ms_tick, CountdownTimer},
+    IrqCfg,
 };
 
 #[entry]
 fn main() -> ! {
-    let dp = pac::Peripherals::take().unwrap();
+    let mut dp = pac::Peripherals::take().unwrap();
-    let mut delay = CountdownTimer::new(dp.tim1, 50.MHz());
+    let mut delay_ms = DelayMs::new(set_up_ms_tick(
-    let porta = PinsA::new(dp.porta);
+        IrqCfg::new(interrupt::OC0, true, true),
-    let mut led1 = Output::new(porta.pa10, PinState::Low);
+        &mut dp.sysconfig,
-    let mut led2 = Output::new(porta.pa7, PinState::Low);
+        Some(&mut dp.irqsel),
-    let mut led3 = Output::new(porta.pa6, PinState::Low);
+        50.MHz(),
+        dp.tim0,
+    ))
+    .unwrap();
+    let mut delay_tim1 = CountdownTimer::new(&mut dp.sysconfig, 50.MHz(), dp.tim1);
+    let porta = PinsA::new(&mut dp.sysconfig, Some(dp.ioconfig), dp.porta);
+    let mut led1 = porta.pa10.into_readable_push_pull_output();
+    let mut led2 = porta.pa7.into_readable_push_pull_output();
+    let mut led3 = porta.pa6.into_readable_push_pull_output();
     for _ in 0..10 {
-        led1.set_low();
+        led1.set_low().ok();
-        led2.set_low();
+        led2.set_low().ok();
-        led3.set_low();
+        led3.set_low().ok();
-        delay.delay_ms(200);
+        delay_ms.delay_ms(200);
-        led1.set_high();
+        led1.set_high().ok();
-        led2.set_high();
+        led2.set_high().ok();
-        led3.set_high();
+        led3.set_high().ok();
-        delay.delay_ms(200);
+        delay_tim1.delay_ms(200);
     }
     loop {
-        led1.toggle();
+        led1.toggle().ok();
-        delay.delay_ms(200);
+        delay_ms.delay_ms(200);
-        led2.toggle();
+        led2.toggle().ok();
-        delay.delay_ms(200);
+        delay_tim1.delay_ms(200);
-        led3.toggle();
+        led3.toggle().ok();
-        delay.delay_ms(200);
+        delay_ms.delay_ms(200);
     }
 }
+
+#[interrupt]
+#[allow(non_snake_case)]
+fn OC0() {
+    default_ms_irq_handler()
+}

examples/simple/examples/cascade.rs

@@ -6,68 +6,92 @@
 #![no_std]
 #![allow(non_snake_case)]
 
+use core::cell::RefCell;
+use cortex_m::interrupt::Mutex;
 use cortex_m_rt::entry;
 use embedded_hal::delay::DelayNs;
-// Import panic provider.
+use panic_rtt_target as _;
-use panic_probe as _;
+use rtt_target::{rprintln, rtt_init_print};
-// Import logger.
-use defmt_rtt as _;
 use va108xx_hal::{
     pac::{self, interrupt},
     prelude::*,
-    timer::{CascadeControl, CascadeSelect, CascadeSource, CountdownTimer, InterruptConfig},
+    timer::{
+        default_ms_irq_handler, set_up_ms_delay_provider, CascadeCtrl, CascadeSource,
+        CountdownTimer, Event, IrqCfg,
+    },
 };
 
+static CSD_TGT_1: Mutex<RefCell<Option<CountdownTimer<pac::Tim4>>>> =
+    Mutex::new(RefCell::new(None));
+static CSD_TGT_2: Mutex<RefCell<Option<CountdownTimer<pac::Tim5>>>> =
+    Mutex::new(RefCell::new(None));
+
 #[entry]
 fn main() -> ! {
-    defmt::println!("-- VA108xx Cascade example application--");
+    rtt_init_print!();
+    rprintln!("-- VA108xx Cascade example application--");
 
-    let dp = pac::Peripherals::take().unwrap();
+    let mut dp = pac::Peripherals::take().unwrap();
-    let mut delay = CountdownTimer::new(dp.tim0, 50.MHz());
+    let mut delay = set_up_ms_delay_provider(&mut dp.sysconfig, 50.MHz(), dp.tim0);
 
     // Will be started periodically to trigger a cascade
-    let mut cascade_triggerer = CountdownTimer::new(dp.tim3, 50.MHz());
+    let mut cascade_triggerer =
-    cascade_triggerer.auto_disable(true);
+        CountdownTimer::new(&mut dp.sysconfig, 50.MHz(), dp.tim3).auto_disable(true);
-    cascade_triggerer.enable_interrupt(InterruptConfig::new(pac::Interrupt::OC1, true, false));
+    cascade_triggerer.listen(
-    cascade_triggerer.enable();
+        Event::TimeOut,
+        IrqCfg::new(pac::Interrupt::OC1, true, false),
+        Some(&mut dp.irqsel),
+        Some(&mut dp.sysconfig),
+    );
 
     // First target for cascade
-    let mut cascade_target_1 = CountdownTimer::new(dp.tim4, 50.MHz());
+    let mut cascade_target_1 =
-    cascade_target_1.auto_deactivate(true);
+        CountdownTimer::new(&mut dp.sysconfig, 50.MHz(), dp.tim4).auto_deactivate(true);
     cascade_target_1
-        .cascade_source(CascadeSelect::Csd0, CascadeSource::Tim(3))
+        .cascade_0_source(CascadeSource::Tim(3))
-        .unwrap();
+        .expect("Configuring cascade source for TIM4 failed");
-    let mut csd_cfg = CascadeControl {
+    let mut csd_cfg = CascadeCtrl {
-        enable_src_0: true,
+        enb_start_src_csd0: true,
-        trigger_mode_0: true,
         ..Default::default()
     };
+    // Use trigger mode here
+    csd_cfg.trg_csd0 = true;
     cascade_target_1.cascade_control(csd_cfg);
     // Normally it should already be sufficient to activate IRQ in the CTRL
     // register but a full interrupt is use here to display print output when
     // the timer expires
-    cascade_target_1.enable_interrupt(InterruptConfig::new(pac::Interrupt::OC2, true, false));
+    cascade_target_1.listen(
+        Event::TimeOut,
+        IrqCfg::new(pac::Interrupt::OC2, true, false),
+        Some(&mut dp.irqsel),
+        Some(&mut dp.sysconfig),
+    );
     // The counter will only activate when the cascade signal is coming in so
     // it is okay to call start here to set the reset value
     cascade_target_1.start(1.Hz());
 
     // Activated by first cascade target
-    let mut cascade_target_2 = CountdownTimer::new(dp.tim5, 50.MHz());
+    let mut cascade_target_2 =
-    cascade_target_2.auto_deactivate(true);
+        CountdownTimer::new(&mut dp.sysconfig, 50.MHz(), dp.tim5).auto_deactivate(true);
     // Set TIM4 as cascade source
     cascade_target_2
-        .cascade_source(CascadeSelect::Csd1, CascadeSource::Tim(4))
+        .cascade_1_source(CascadeSource::Tim(4))
-        .unwrap();
+        .expect("Configuring cascade source for TIM5 failed");
 
-    csd_cfg = CascadeControl::default();
+    csd_cfg = CascadeCtrl::default();
-    csd_cfg.enable_src_1 = true;
+    csd_cfg.enb_start_src_csd1 = true;
     // Use trigger mode here
-    csd_cfg.trigger_mode_1 = true;
+    csd_cfg.trg_csd1 = true;
     cascade_target_2.cascade_control(csd_cfg);
     // Normally it should already be sufficient to activate IRQ in the CTRL
     // register but a full interrupt is use here to display print output when
     // the timer expires
-    cascade_target_2.enable_interrupt(InterruptConfig::new(pac::Interrupt::OC3, true, false));
+    cascade_target_2.listen(
+        Event::TimeOut,
+        IrqCfg::new(pac::Interrupt::OC3, true, false),
+        Some(&mut dp.irqsel),
+        Some(&mut dp.sysconfig),
+    );
     // The counter will only activate when the cascade signal is coming in so
     // it is okay to call start here to set the reset value
     cascade_target_2.start(1.Hz());
@@ -79,31 +103,40 @@ fn main() -> ! {
         cortex_m::peripheral::NVIC::unmask(pac::Interrupt::OC2);
         cortex_m::peripheral::NVIC::unmask(pac::Interrupt::OC3);
     }
-
+    // Make both cascade targets accessible from the IRQ handler with the Mutex dance
+    cortex_m::interrupt::free(|cs| {
+        CSD_TGT_1.borrow(cs).replace(Some(cascade_target_1));
+        CSD_TGT_2.borrow(cs).replace(Some(cascade_target_2));
+    });
     loop {
-        defmt::info!("-- Triggering cascade in 0.5 seconds --");
+        rprintln!("-- Triggering cascade in 0.5 seconds --");
         cascade_triggerer.start(2.Hz());
         delay.delay_ms(5000);
     }
 }
 
+#[interrupt]
+fn OC0() {
+    default_ms_irq_handler()
+}
+
 #[interrupt]
 fn OC1() {
     static mut IDX: u32 = 0;
-    defmt::info!("{}: Cascade trigger timed out", &IDX);
+    rprintln!("{}: Cascade triggered timed out", &IDX);
     *IDX += 1;
 }
 
 #[interrupt]
 fn OC2() {
     static mut IDX: u32 = 0;
-    defmt::info!("{}: First cascade target timed out", &IDX);
+    rprintln!("{}: First cascade target timed out", &IDX);
     *IDX += 1;
 }
 
 #[interrupt]
 fn OC3() {
     static mut IDX: u32 = 0;
-    defmt::info!("{}: Second cascade target timed out", &IDX);
+    rprintln!("{}: Second cascade target timed out", &IDX);
     *IDX += 1;
 }

examples/simple/examples/pwm.rs

@@ -1,36 +1,39 @@
 //! Simple PWM example
-//!
-//! Outputs a PWM waveform on pin PA3.
 #![no_main]
 #![no_std]
 
 use cortex_m_rt::entry;
 use embedded_hal::{delay::DelayNs, pwm::SetDutyCycle};
-// Import panic provider.
+use panic_rtt_target as _;
-use panic_probe as _;
+use rtt_target::{rprintln, rtt_init_print};
-// Import logger.
-use defmt_rtt as _;
 use va108xx_hal::{
+    gpio::PinsA,
     pac,
-    pins::PinsA,
     prelude::*,
-    pwm::{self, get_duty_from_percent, PwmA, PwmB, PwmPin},
+    pwm::{self, get_duty_from_percent, PwmA, PwmB, ReducedPwmPin},
-    timer::CountdownTimer,
+    timer::set_up_ms_delay_provider,
 };
 
 #[entry]
 fn main() -> ! {
-    defmt::println!("-- VA108xx PWM example application--");
+    rtt_init_print!();
-    let dp = pac::Peripherals::take().unwrap();
+    rprintln!("-- VA108xx PWM example application--");
-    let pinsa = PinsA::new(dp.porta);
+    let mut dp = pac::Peripherals::take().unwrap();
-    let mut pwm = pwm::PwmPin::new(pinsa.pa3, dp.tim3, 50.MHz(), 10.Hz()).unwrap();
+    let pinsa = PinsA::new(&mut dp.sysconfig, None, dp.porta);
-    let mut delay = CountdownTimer::new(dp.tim0, 50.MHz());
+    let mut pwm = pwm::PwmPin::new(
+        &mut dp.sysconfig,
+        50.MHz(),
+        (pinsa.pa3.into_funsel_1(), dp.tim3),
+        10.Hz(),
+    );
+    let mut delay = set_up_ms_delay_provider(&mut dp.sysconfig, 50.MHz(), dp.tim0);
     let mut current_duty_cycle = 0.0;
     pwm.set_duty_cycle(get_duty_from_percent(current_duty_cycle))
         .unwrap();
     pwm.enable();
 
     // Delete type information, increased code readibility for the rest of the code
+    let mut reduced_pin = ReducedPwmPin::from(pwm);
     loop {
         let mut counter = 0;
         // Increase duty cycle continuously
@@ -39,10 +42,11 @@ fn main() -> ! {
             current_duty_cycle += 0.02;
             counter += 1;
             if counter % 10 == 0 {
-                defmt::info!("current duty cycle: {}", current_duty_cycle);
+                rprintln!("current duty cycle: {}", current_duty_cycle);
             }
 
-            pwm.set_duty_cycle(get_duty_from_percent(current_duty_cycle))
+            reduced_pin
+                .set_duty_cycle(get_duty_from_percent(current_duty_cycle))
                 .unwrap();
         }
 
@@ -51,7 +55,7 @@ fn main() -> ! {
         current_duty_cycle = 0.0;
         let mut upper_limit = 1.0;
         let mut lower_limit = 0.0;
-        let mut pwmb: PwmPin<PwmB> = PwmPin::from(pwm);
+        let mut pwmb: ReducedPwmPin<PwmB> = ReducedPwmPin::from(reduced_pin);
         pwmb.set_pwmb_lower_limit(get_duty_from_percent(lower_limit));
         pwmb.set_pwmb_upper_limit(get_duty_from_percent(upper_limit));
         while lower_limit < 0.5 {
@@ -60,9 +64,9 @@ fn main() -> ! {
             upper_limit -= 0.01;
             pwmb.set_pwmb_lower_limit(get_duty_from_percent(lower_limit));
             pwmb.set_pwmb_upper_limit(get_duty_from_percent(upper_limit));
-            defmt::info!("Lower limit: {}", pwmb.pwmb_lower_limit());
+            rprintln!("Lower limit: {}", pwmb.pwmb_lower_limit());
-            defmt::info!("Upper limit: {}", pwmb.pwmb_upper_limit());
+            rprintln!("Upper limit: {}", pwmb.pwmb_upper_limit());
         }
-        pwm = PwmPin::<PwmA>::from(pwmb);
+        reduced_pin = ReducedPwmPin::<PwmA>::from(pwmb);
     }
 }

examples/simple/examples/rtt-log.rs

@@ -0,0 +1,20 @@
+//! Code to test RTT logger functionality
+#![no_main]
+#![no_std]
+
+use cortex_m_rt::entry;
+use panic_rtt_target as _;
+use rtt_target::{rprintln, rtt_init_print};
+use va108xx_hal as _;
+
+#[entry]
+fn main() -> ! {
+    rtt_init_print!();
+    rprintln!("-- VA108XX RTT example --");
+    let mut counter = 0;
+    loop {
+        rprintln!("{}: Hello, world!", counter);
+        counter += 1;
+        cortex_m::asm::delay(25_000_000);
+    }
+}

examples/simple/examples/spi.rs

@@ -1,21 +1,23 @@
 //! SPI example application
 #![no_main]
 #![no_std]
+
+use core::cell::RefCell;
+
 use cortex_m_rt::entry;
 use embedded_hal::{
     delay::DelayNs,
     spi::{Mode, SpiBus, MODE_0},
 };
-// Import panic provider.
+use panic_rtt_target as _;
-use panic_probe as _;
+use rtt_target::{rprintln, rtt_init_print};
-// Import logger.
-use defmt_rtt as _;
 use va108xx_hal::{
-    pac,
+    gpio::{PinsA, PinsB},
-    pins::{PinsA, PinsB},
+    pac::{self, interrupt},
     prelude::*,
-    spi::{self, configure_pin_as_hw_cs_pin, Spi, SpiClkConfig, TransferConfig},
+    spi::{self, Spi, SpiBase, SpiClkConfig, TransferConfigWithHwcs},
-    timer::CountdownTimer,
+    timer::{default_ms_irq_handler, set_up_ms_tick},
+    IrqCfg,
 };
 
 #[derive(PartialEq, Debug)]
@@ -41,14 +43,23 @@ const FILL_WORD: u8 = 0x0f;
 
 #[entry]
 fn main() -> ! {
-    defmt::println!("-- VA108xx SPI example application--");
+    rtt_init_print!();
-    let dp = pac::Peripherals::take().unwrap();
+    rprintln!("-- VA108xx SPI example application--");
-    let mut delay = CountdownTimer::new(dp.tim0, 50.MHz());
+    let mut dp = pac::Peripherals::take().unwrap();
+    let mut delay = set_up_ms_tick(
+        IrqCfg::new(interrupt::OC0, true, true),
+        &mut dp.sysconfig,
+        Some(&mut dp.irqsel),
+        50.MHz(),
+        dp.tim0,
+    );
 
     let spi_clk_cfg = SpiClkConfig::from_clk(50.MHz(), SPI_SPEED_KHZ.kHz())
         .expect("creating SPI clock config failed");
-    let pinsa = PinsA::new(dp.porta);
+    let spia_ref: RefCell<Option<SpiBase<pac::Spia, u8>>> = RefCell::new(None);
-    let pinsb = PinsB::new(dp.portb);
+    let spib_ref: RefCell<Option<SpiBase<pac::Spib, u8>>> = RefCell::new(None);
+    let pinsa = PinsA::new(&mut dp.sysconfig, None, dp.porta);
+    let pinsb = PinsB::new(&mut dp.sysconfig, Some(dp.ioconfig), dp.portb);
 
     let mut spi_cfg = spi::SpiConfig::default();
     if EXAMPLE_SEL == ExampleSelect::Loopback {
@@ -56,56 +67,92 @@ fn main() -> ! {
     }
 
     // Set up the SPI peripheral
-    let mut spi = match SPI_BUS_SEL {
+    match SPI_BUS_SEL {
         SpiBusSelect::SpiAPortA => {
-            let (sck, mosi, miso) = (pinsa.pa31, pinsa.pa30, pinsa.pa29);
+            let (sck, mosi, miso) = (
-            let mut spia = Spi::new(dp.spia, (sck, miso, mosi), spi_cfg).unwrap();
+                pinsa.pa31.into_funsel_1(),
+                pinsa.pa30.into_funsel_1(),
+                pinsa.pa29.into_funsel_1(),
+            );
+            let mut spia = Spi::new(
+                &mut dp.sysconfig,
+                50.MHz(),
+                dp.spia,
+                (sck, miso, mosi),
+                spi_cfg,
+            );
             spia.set_fill_word(FILL_WORD);
-            spia
+            spia_ref.borrow_mut().replace(spia.downgrade());
         }
         SpiBusSelect::SpiAPortB => {
-            let (sck, mosi, miso) = (pinsb.pb9, pinsb.pb8, pinsb.pb7);
+            let (sck, mosi, miso) = (
-            let mut spia = Spi::new(dp.spia, (sck, miso, mosi), spi_cfg).unwrap();
+                pinsb.pb9.into_funsel_2(),
+                pinsb.pb8.into_funsel_2(),
+                pinsb.pb7.into_funsel_2(),
+            );
+            let mut spia = Spi::new(
+                &mut dp.sysconfig,
+                50.MHz(),
+                dp.spia,
+                (sck, miso, mosi),
+                spi_cfg,
+            );
             spia.set_fill_word(FILL_WORD);
-            spia
+            spia_ref.borrow_mut().replace(spia.downgrade());
         }
         SpiBusSelect::SpiBPortB => {
-            let (sck, mosi, miso) = (pinsb.pb5, pinsb.pb4, pinsb.pb3);
+            let (sck, mosi, miso) = (
-            let mut spib = Spi::new(dp.spib, (sck, miso, mosi), spi_cfg).unwrap();
+                pinsb.pb5.into_funsel_1(),
+                pinsb.pb4.into_funsel_1(),
+                pinsb.pb3.into_funsel_1(),
+            );
+            let mut spib = Spi::new(
+                &mut dp.sysconfig,
+                50.MHz(),
+                dp.spib,
+                (sck, miso, mosi),
+                spi_cfg,
+            );
             spib.set_fill_word(FILL_WORD);
-            spib
+            spib_ref.borrow_mut().replace(spib.downgrade());
+        }
     }
-    };
     // Configure transfer specific properties here
     match SPI_BUS_SEL {
         SpiBusSelect::SpiAPortA | SpiBusSelect::SpiAPortB => {
-            let transfer_cfg = TransferConfig {
+            if let Some(ref mut spi) = *spia_ref.borrow_mut() {
-                clk_cfg: Some(spi_clk_cfg),
+                let transfer_cfg = TransferConfigWithHwcs::new_no_hw_cs(
-                mode: Some(SPI_MODE),
+                    Some(spi_clk_cfg),
-                sod: true,
+                    Some(SPI_MODE),
-                blockmode: BLOCKMODE,
+                    BLOCKMODE,
-                bmstall: true,
+                    true,
-                hw_cs: None,
+                    false,
-            };
+                );
                 spi.cfg_transfer(&transfer_cfg);
             }
+        }
         SpiBusSelect::SpiBPortB => {
-            let hw_cs_pin = configure_pin_as_hw_cs_pin(pinsb.pb2);
+            if let Some(ref mut spi) = *spib_ref.borrow_mut() {
-            let transfer_cfg = TransferConfig {
+                let hw_cs_pin = pinsb.pb2.into_funsel_1();
-                clk_cfg: Some(spi_clk_cfg),
+                let transfer_cfg = TransferConfigWithHwcs::new(
-                mode: Some(SPI_MODE),
+                    Some(spi_clk_cfg),
-                sod: false,
+                    Some(SPI_MODE),
-                blockmode: BLOCKMODE,
+                    Some(hw_cs_pin),
-                bmstall: true,
+                    BLOCKMODE,
-                hw_cs: Some(hw_cs_pin),
+                    true,
-            };
+                    false,
+                );
                 spi.cfg_transfer(&transfer_cfg);
             }
         }
+    }
 
     // Application logic
     loop {
         let mut reply_buf: [u8; 8] = [0; 8];
+        match SPI_BUS_SEL {
+            SpiBusSelect::SpiAPortA | SpiBusSelect::SpiAPortB => {
+                if let Some(ref mut spi) = *spia_ref.borrow_mut() {
                     // Can't really verify correct reply here.
                     spi.write(&[0x42]).expect("write failed");
                     // Because of the loopback mode, we should get back the fill word here.
@@ -116,7 +163,7 @@ fn main() -> ! {
                     let tx_buf: [u8; 3] = [0x01, 0x02, 0x03];
                     spi.transfer(&mut reply_buf[0..3], &tx_buf).unwrap();
                     assert_eq!(tx_buf, reply_buf[0..3]);
-        defmt::info!(
+                    rprintln!(
                         "Received reply: {}, {}, {}",
                         reply_buf[0],
                         reply_buf[1],
@@ -126,7 +173,7 @@ fn main() -> ! {
 
                     let mut tx_rx_buf: [u8; 3] = [0x03, 0x02, 0x01];
                     spi.transfer_in_place(&mut tx_rx_buf).unwrap();
-        defmt::info!(
+                    rprintln!(
                         "Received reply: {}, {}, {}",
                         tx_rx_buf[0],
                         tx_rx_buf[1],
@@ -134,4 +181,44 @@ fn main() -> ! {
                     );
                     assert_eq!(&tx_rx_buf[0..3], &[0x03, 0x02, 0x01]);
                 }
+            }
+            SpiBusSelect::SpiBPortB => {
+                if let Some(ref mut spi) = *spib_ref.borrow_mut() {
+                    // Can't really verify correct reply here.
+                    spi.write(&[0x42]).expect("write failed");
+                    // Because of the loopback mode, we should get back the fill word here.
+                    spi.read(&mut reply_buf[0..1]).unwrap();
+                    assert_eq!(reply_buf[0], FILL_WORD);
+                    delay.delay_ms(500_u32);
+
+                    let tx_buf: [u8; 3] = [0x01, 0x02, 0x03];
+                    spi.transfer(&mut reply_buf[0..3], &tx_buf).unwrap();
+                    assert_eq!(tx_buf, reply_buf[0..3]);
+                    rprintln!(
+                        "Received reply: {}, {}, {}",
+                        reply_buf[0],
+                        reply_buf[1],
+                        reply_buf[2]
+                    );
+                    delay.delay_ms(500_u32);
+
+                    let mut tx_rx_buf: [u8; 3] = [0x03, 0x02, 0x01];
+                    spi.transfer_in_place(&mut tx_rx_buf).unwrap();
+                    rprintln!(
+                        "Received reply: {}, {}, {}",
+                        tx_rx_buf[0],
+                        tx_rx_buf[1],
+                        tx_rx_buf[2]
+                    );
+                    assert_eq!(&tx_rx_buf[0..3], &[0x03, 0x02, 0x01]);
+                }
+            }
+        }
+    }
+}
+
+#[interrupt]
+#[allow(non_snake_case)]
+fn OC0() {
+    default_ms_irq_handler()
 }

examples/simple/examples/timer-ticks.rs

@@ -2,18 +2,17 @@
 #![no_main]
 #![no_std]
 
+use core::cell::Cell;
 use cortex_m_rt::entry;
-use embedded_hal::delay::DelayNs;
+use critical_section::Mutex;
-// Import panic provider.
+use panic_rtt_target as _;
-use panic_probe as _;
+use rtt_target::{rprintln, rtt_init_print};
-// Import logger.
-use defmt_rtt as _;
-use portable_atomic::AtomicU32;
 use va108xx_hal::{
+    clock::{get_sys_clock, set_sys_clock},
     pac::{self, interrupt},
     prelude::*,
     time::Hertz,
-    timer::{CountdownTimer, InterruptConfig},
+    timer::{default_ms_irq_handler, set_up_ms_tick, CountdownTimer, Event, IrqCfg, MS_COUNTER},
 };
 
 #[allow(dead_code)]
@@ -22,15 +21,15 @@ enum LibType {
     Hal,
 }
 
-static MS_COUNTER: AtomicU32 = AtomicU32::new(0);
+static SEC_COUNTER: Mutex<Cell<u32>> = Mutex::new(Cell::new(0));
-static SEC_COUNTER: AtomicU32 = AtomicU32::new(0);
 
 #[entry]
 fn main() -> ! {
-    let dp = pac::Peripherals::take().unwrap();
+    rtt_init_print!();
-    let mut delay = CountdownTimer::new(dp.tim2, 50.MHz());
+    let mut dp = pac::Peripherals::take().unwrap();
     let mut last_ms = 0;
-    defmt::info!("-- Vorago system ticks using timers --");
+    rprintln!("-- Vorago system ticks using timers --");
+    set_sys_clock(50.MHz());
     let lib_type = LibType::Hal;
     match lib_type {
         LibType::Pac => {
@@ -65,24 +64,34 @@ fn main() -> ! {
             }
         }
         LibType::Hal => {
-            let mut ms_timer = CountdownTimer::new(dp.tim0, 50.MHz());
+            set_up_ms_tick(
-            ms_timer.enable_interrupt(InterruptConfig::new(interrupt::OC0, true, true));
+                IrqCfg::new(interrupt::OC0, true, true),
-            ms_timer.start(1.kHz());
+                &mut dp.sysconfig,
-            let mut second_timer = CountdownTimer::new(dp.tim1, 50.MHz());
+                Some(&mut dp.irqsel),
-            second_timer.enable_interrupt(InterruptConfig::new(interrupt::OC1, true, true));
+                50.MHz(),
+                dp.tim0,
+            );
+            let mut second_timer =
+                CountdownTimer::new(&mut dp.sysconfig, get_sys_clock().unwrap(), dp.tim1);
+            second_timer.listen(
+                Event::TimeOut,
+                IrqCfg::new(interrupt::OC1, true, true),
+                Some(&mut dp.irqsel),
+                Some(&mut dp.sysconfig),
+            );
             second_timer.start(1.Hz());
         }
     }
     loop {
-        let current_ms = MS_COUNTER.load(portable_atomic::Ordering::Relaxed);
+        let current_ms = critical_section::with(|cs| MS_COUNTER.borrow(cs).get());
         if current_ms - last_ms >= 1000 {
             // To prevent drift.
             last_ms += 1000;
-            defmt::info!("MS counter: {}", current_ms);
+            rprintln!("MS counter: {}", current_ms);
-            let second = SEC_COUNTER.load(portable_atomic::Ordering::Relaxed);
+            let second = critical_section::with(|cs| SEC_COUNTER.borrow(cs).get());
-            defmt::info!("Second counter: {}", second);
+            rprintln!("Second counter: {}", second);
         }
-        delay.delay_ms(50);
+        cortex_m::asm::delay(10000);
     }
 }
 
@@ -96,11 +105,15 @@ fn unmask_irqs() {
 #[interrupt]
 #[allow(non_snake_case)]
 fn OC0() {
-    MS_COUNTER.fetch_add(1, portable_atomic::Ordering::Relaxed);
+    default_ms_irq_handler()
 }
 
 #[interrupt]
 #[allow(non_snake_case)]
 fn OC1() {
-    SEC_COUNTER.fetch_add(1, portable_atomic::Ordering::Relaxed);
+    critical_section::with(|cs| {
+        let mut sec = SEC_COUNTER.borrow(cs).get();
+        sec += 1;
+        SEC_COUNTER.borrow(cs).set(sec);
+    });
 }

examples/simple/examples/uart.rs

@@ -13,25 +13,23 @@
 use cortex_m_rt::entry;
 use embedded_hal_nb::{nb, serial::Read};
 use embedded_io::Write as _;
-// Import panic provider.
+use panic_rtt_target as _;
-use panic_probe as _;
+use rtt_target::{rprintln, rtt_init_print};
-// Import logger.
+use va108xx_hal::{gpio::PinsA, pac, prelude::*, uart};
-use defmt_rtt as _;
-use va108xx_hal::{pac, pins::PinsA, prelude::*, uart};
 
 #[entry]
 fn main() -> ! {
-    defmt::println!("-- VA108xx UART example application--");
+    rtt_init_print!();
+    rprintln!("-- VA108xx UART example application--");
 
-    let dp = pac::Peripherals::take().unwrap();
+    let mut dp = pac::Peripherals::take().unwrap();
 
-    let gpioa = PinsA::new(dp.porta);
+    let gpioa = PinsA::new(&mut dp.sysconfig, Some(dp.ioconfig), dp.porta);
-    let tx = gpioa.pa9;
+    let tx = gpioa.pa9.into_funsel_2();
-    let rx = gpioa.pa8;
+    let rx = gpioa.pa8.into_funsel_2();
-    let uart =
-        uart::Uart::new_without_interrupt(dp.uarta, tx, rx, 50.MHz(), 115200.Hz().into()).unwrap();
 
-    let (mut tx, mut rx) = uart.split();
+    let uarta = uart::Uart::new(&mut dp.sysconfig, 50.MHz(), dp.uarta, (tx, rx), 115200.Hz());
+    let (mut tx, mut rx) = uarta.split();
     writeln!(tx, "Hello World\r").unwrap();
     loop {
         // Echo what is received on the serial link.
@@ -41,6 +39,9 @@ fn main() -> ! {
                     .expect("TX send error");
             }
             Err(nb::Error::WouldBlock) => (),
+            Err(nb::Error::Other(uart_error)) => {
+                rprintln!("UART receive error {:?}", uart_error);
+            }
         }
     }
 }

examples/simple/src/main.rs

@@ -3,8 +3,7 @@
 #![no_std]
 
 use cortex_m_rt::entry;
-use panic_probe as _;
+use panic_rtt_target as _;
-use va108xx_hal as _;
 
 #[entry]
 fn main() -> ! {

flashloader/Cargo.toml

@@ -4,31 +4,32 @@ version = "0.1.0"
 edition = "2021"
 
 [dependencies]
-cortex-m = { version = "0.7", features = ["critical-section-single-core"]}
+cortex-m = "0.7"
 cortex-m-rt = "0.7"
+embedded-hal = "1"
+embedded-hal-nb = "1"
 embedded-io = "0.6"
-defmt = "1"
+panic-rtt-target = "0.2"
-defmt-rtt = { version = "0.4" }
+rtt-target = "0.6"
-panic-probe = { version = "0.3", features = ["print-defmt"] }
 num_enum = { version = "0.7", default-features = false }
+log = "0.4"
+crc = "3"
 cobs = { version = "0.3", default-features = false }
 satrs = { version = "0.2", default-features = false }
+rtt-log = "0.5"
 ringbuf = { version = "0.4.7", default-features = false, features = ["portable-atomic"] }
-spacepackets = { version = "0.11", default-features = false, features = ["defmt"] }
+once_cell = { version = "1", default-features = false, features = ["critical-section"] }
+spacepackets = { version = "0.11", default-features = false }
 # Even though we do not use this directly, we need to activate this feature explicitely
 # so that RTIC compiles because thumv6 does not have CAS operations natively.
 portable-atomic = {version = "1", features = ["unsafe-assume-single-core"]}
 
 rtic = { version = "2", features = ["thumbv6-backend"] }
 rtic-monotonics = { version = "2", features = ["cortex-m-systick"] }
+rtic-sync = {version = "1", features = ["defmt-03"]}
 
 [dependencies.va108xx-hal]
-version = "0.11"
 path = "../va108xx-hal"
-features = ["defmt"]
 
 [dependencies.vorago-reb1]
-version = "0.8"
+path = "../vorago-reb1"
-
-[package.metadata.cargo-machete]
-ignored = ["portable-atomic", "cortex-m-rt"]

flashloader/image-loader.py

@@ -2,15 +2,16 @@
 from typing import List, Tuple
 from spacepackets.ecss.defs import PusService
 from spacepackets.ecss.tm import PusTm
+from tmtccmd.com import ComInterface
 import toml
 import struct
 import logging
 import argparse
 import time
 import enum
-from com_interface import ComInterface
+from tmtccmd.com.serial_base import SerialCfg
-from com_interface.serial_base import SerialCfg
+from tmtccmd.com.serial_cobs import SerialCobsComIF
-from com_interface.serial_cobs import SerialCobsComIF
+from tmtccmd.com.ser_utils import prompt_com_port
 from crcmod.predefined import PredefinedCrc
 from spacepackets.ecss.tc import PusTc
 from spacepackets.ecss.pus_verificator import PusVerificator, StatusField
@@ -100,7 +101,15 @@ class ImageLoader:
         )
         self.verificator.add_tc(action_tc)
         self.com_if.send(bytes(action_tc.pack()))
-        self.await_for_command_copletion("boot image selection command")
+        data_available = self.com_if.data_available(0.4)
+        if not data_available:
+            _LOGGER.warning("no reply received for boot image selection command")
+        for reply in self.com_if.receive():
+            result = self.verificator.add_tm(
+                Service1Tm.from_tm(PusTm.unpack(reply, 0), UnpackParams(0))
+            )
+            if result is not None and result.completed:
+                _LOGGER.info("received boot image selection command confirmation")
 
     def handle_ping_cmd(self):
         _LOGGER.info("Sending ping command")
@@ -113,26 +122,16 @@ class ImageLoader:
         )
         self.verificator.add_tc(ping_tc)
         self.com_if.send(bytes(ping_tc.pack()))
-        self.await_for_command_copletion("ping command")
 
-    def await_for_command_copletion(self, context: str):
+        data_available = self.com_if.data_available(0.4)
-        done = False
+        if not data_available:
-        now = time.time()
+            _LOGGER.warning("no ping reply received")
-        while time.time() - now < 2.0:
-            if not self.com_if.data_available():
-                time.sleep(0.2)
-                continue
         for reply in self.com_if.receive():
             result = self.verificator.add_tm(
                 Service1Tm.from_tm(PusTm.unpack(reply, 0), UnpackParams(0))
             )
             if result is not None and result.completed:
-                    _LOGGER.info(f"received {context} reply")
+                _LOGGER.info("received ping completion reply")
-                    done = True
-            if done:
-                break
-        if not done:
-            _LOGGER.warning(f"no {context} reply received")
 
     def handle_corruption_cmd(self, target: Target):
         if target == Target.BOOTLOADER:
@@ -301,12 +300,12 @@ def main() -> int:
             if "serial_port" in parsed_toml:
                 serial_port = parsed_toml["serial_port"]
     if serial_port is None:
-        serial_port = input("Please specify the serial port manually: ")
+        serial_port = prompt_com_port()
     serial_cfg = SerialCfg(
         com_if_id="ser_cobs",
         serial_port=serial_port,
         baud_rate=BAUD_RATE,
-        polling_frequency=0.1,
+        serial_timeout=0.1,
     )
     verificator = PusVerificator()
     com_if = SerialCobsComIF(serial_cfg)

flashloader/loader.toml

@@ -1 +1 @@
-serial_port = "/dev/ttyUSB1"
+serial_port = "/dev/ttyUSB0"

flashloader/requirements.txt

@@ -1,5 +1,5 @@
-spacepackets == 0.28
+spacepackets == 0.24
-com-interface == 0.1
+tmtccmd == 8.0.2
 toml == 0.10
 pyelftools == 0.31
 crcmod == 1.7

flashloader/slot-a-blinky/Cargo.toml

@@ -9,8 +9,9 @@ edition = "2021"
 cortex-m-rt = "0.7"
 panic-rtt-target = { version = "0.1.3" }
 rtt-target = { version = "0.5" }
+cortex-m = { version = "0.7", features = ["critical-section-single-core"] }
 embedded-hal = "1"
-va108xx-hal = { version = "0.11" }
+va108xx-hal = { path = "../../va108xx-hal" }
 
 [profile.dev]
 codegen-units = 1

flashloader/slot-a-blinky/src/main.rs

@@ -3,7 +3,7 @@
 #![no_std]
 
 use cortex_m_rt::entry;
-use embedded_hal::delay::DelayNs;
+use embedded_hal::{delay::DelayNs, digital::StatefulOutputPin};
 use panic_rtt_target as _;
 use rtt_target::{rprintln, rtt_init_print};
 use va108xx_hal::{gpio::PinsA, pac, prelude::*, timer::CountdownTimer};
@@ -15,11 +15,11 @@ fn main() -> ! {
 
     let mut dp = pac::Peripherals::take().unwrap();
     let mut timer = CountdownTimer::new(&mut dp.sysconfig, 50.MHz(), dp.tim0);
-    let porta = PinsA::new(&mut dp.sysconfig, dp.porta);
+    let porta = PinsA::new(&mut dp.sysconfig, Some(dp.ioconfig), dp.porta);
     let mut led1 = porta.pa10.into_readable_push_pull_output();
 
     loop {
-        led1.toggle();
+        led1.toggle().ok();
         timer.delay_ms(500);
     }
 }

flashloader/slot-b-blinky/Cargo.toml

@@ -9,8 +9,9 @@ edition = "2021"
 cortex-m-rt = "0.7"
 panic-rtt-target = { version = "0.1.3" }
 rtt-target = { version = "0.5" }
+cortex-m = { version = "0.7", features = ["critical-section-single-core"] }
 embedded-hal = "1"
-va108xx-hal = { version = "0.11" }
+va108xx-hal = { path = "../../va108xx-hal" }
 
 [profile.dev]
 codegen-units = 1

flashloader/slot-b-blinky/src/main.rs

@@ -3,7 +3,7 @@
 #![no_std]
 
 use cortex_m_rt::entry;
-use embedded_hal::delay::DelayNs;
+use embedded_hal::{delay::DelayNs, digital::StatefulOutputPin};
 use panic_rtt_target as _;
 use rtt_target::{rprintln, rtt_init_print};
 use va108xx_hal::{gpio::PinsA, pac, prelude::*, timer::CountdownTimer};
@@ -15,11 +15,11 @@ fn main() -> ! {
 
     let mut dp = pac::Peripherals::take().unwrap();
     let mut timer = CountdownTimer::new(&mut dp.sysconfig, 50.MHz(), dp.tim0);
-    let porta = PinsA::new(&mut dp.sysconfig, dp.porta);
+    let porta = PinsA::new(&mut dp.sysconfig, Some(dp.ioconfig), dp.porta);
     let mut led2 = porta.pa7.into_readable_push_pull_output();
 
     loop {
-        led2.toggle();
+        led2.toggle().ok();
         timer.delay_ms(1000);
     }
 }

flashloader/src/lib.rs

@@ -0,0 +1,9 @@
+#![no_std]
+
+#[cfg(test)]
+mod tests {
+    #[test]
+    fn simple() {
+        assert_eq!(1 + 1, 2);
+    }
+}

flashloader/src/main.rs

@@ -3,9 +3,8 @@
 #![no_main]
 #![no_std]
 
-use defmt_rtt as _; // global logger
 use num_enum::TryFromPrimitive;
-use panic_probe as _;
+use panic_rtt_target as _;
 use ringbuf::{
     traits::{Consumer, Observer, Producer},
     StaticRb,
@@ -30,7 +29,7 @@ pub enum ActionId {
     SetBootSlot = 130,
 }
 
-#[derive(Debug, Copy, Clone, PartialEq, Eq, TryFromPrimitive, defmt::Format)]
+#[derive(Debug, Copy, Clone, PartialEq, Eq, TryFromPrimitive)]
 #[repr(u8)]
 enum AppSel {
     A = 0,
@@ -61,16 +60,18 @@ mod app {
     use super::*;
     use cortex_m::asm;
     use embedded_io::Write;
+    use panic_rtt_target as _;
     use rtic::Mutex;
     use rtic_monotonics::systick::prelude::*;
+    use rtt_target::rprintln;
     use satrs::pus::verification::{FailParams, VerificationReportCreator};
     use spacepackets::ecss::PusServiceId;
     use spacepackets::ecss::{
         tc::PusTcReader, tm::PusTmCreator, EcssEnumU8, PusPacket, WritablePusPacket,
     };
-    use va108xx_hal::pins::PinsA;
+    use va108xx_hal::gpio::PinsA;
     use va108xx_hal::uart::IrqContextTimeoutOrMaxSize;
-    use va108xx_hal::{pac, uart, InterruptConfig};
+    use va108xx_hal::{pac, uart};
     use vorago_reb1::m95m01::M95M01;
 
     #[derive(Default, Debug, Copy, Clone, PartialEq, Eq)]
@@ -83,8 +84,8 @@ mod app {
 
     #[local]
     struct Local {
-        uart_rx: uart::RxWithInterrupt,
+        uart_rx: uart::RxWithIrq<pac::Uarta>,
-        uart_tx: uart::Tx,
+        uart_tx: uart::Tx<pac::Uarta>,
         rx_context: IrqContextTimeoutOrMaxSize,
         verif_reporter: VerificationReportCreator,
         nvm: M95M01,
@@ -101,29 +102,27 @@ mod app {
 
     #[init]
     fn init(cx: init::Context) -> (Shared, Local) {
-        defmt::println!("-- Vorago flashloader --");
+        rtt_log::init();
+        rprintln!("-- Vorago flashloader --");
 
         Mono::start(cx.core.SYST, SYSCLK_FREQ.raw());
 
         let mut dp = cx.device;
         let nvm = M95M01::new(&mut dp.sysconfig, SYSCLK_FREQ, dp.spic);
 
-        let gpioa = PinsA::new(dp.porta);
+        let gpioa = PinsA::new(&mut dp.sysconfig, Some(dp.ioconfig), dp.porta);
-        let tx = gpioa.pa9;
+        let tx = gpioa.pa9.into_funsel_2();
-        let rx = gpioa.pa8;
+        let rx = gpioa.pa8.into_funsel_2();
 
-        let irq_uart = uart::Uart::new_with_interrupt(
+        let irq_uart = uart::Uart::new(
-            dp.uarta,
+            &mut dp.sysconfig,
-            tx,
-            rx,
             SYSCLK_FREQ,
-            UART_BAUDRATE.Hz().into(),
+            dp.uarta,
-            InterruptConfig::new(pac::Interrupt::OC0, true, true),
+            (tx, rx),
-        )
+            UART_BAUDRATE.Hz(),
-        .unwrap();
+        );
         let (tx, rx) = irq_uart.split();
-        // Unwrap is okay, we explicitely set the interrupt ID.
+        let mut rx = rx.into_rx_with_irq(&mut dp.sysconfig, &mut dp.irqsel, pac::interrupt::OC0);
-        let mut rx = rx.into_rx_with_irq();
 
         let verif_reporter = VerificationReportCreator::new(0).unwrap();
 
@@ -176,12 +175,12 @@ mod app {
         match cx
             .local
             .uart_rx
-            .on_interrupt_max_size_or_timeout_based(cx.local.rx_context, cx.local.rx_buf)
+            .irq_handler_max_size_or_timeout_based(cx.local.rx_context, cx.local.rx_buf)
         {
             Ok(result) => {
                 if RX_DEBUGGING {
-                    defmt::debug!("RX Info: {:?}", cx.local.rx_context);
+                    log::debug!("RX Info: {:?}", cx.local.rx_context);
-                    defmt::debug!("RX Result: {:?}", result);
+                    log::debug!("RX Result: {:?}", result);
                 }
                 if result.complete() {
                     // Check frame validity (must have COBS format) and decode the frame.
@@ -192,7 +191,7 @@ mod app {
                         let decoded_size =
                             cobs::decode_in_place(&mut cx.local.rx_buf[1..result.bytes_read]);
                         if decoded_size.is_err() {
-                            defmt::warn!("COBS decoding failed");
+                            log::warn!("COBS decoding failed");
                         } else {
                             let decoded_size = decoded_size.unwrap();
                             let mut tc_rb_full = false;
@@ -206,13 +205,11 @@ mod app {
                                 }
                             });
                             if tc_rb_full {
-                                defmt::warn!("COBS TC queue full");
+                                log::warn!("COBS TC queue full");
                             }
                         }
                     } else {
-                        defmt::warn!(
+                        log::warn!("COBS frame with invalid format, start and end bytes are not 0");
-                            "COBS frame with invalid format, start and end bytes are not 0"
-                        );
                     }
 
                     // Initiate next transfer.
@@ -222,11 +219,11 @@ mod app {
                         .expect("read operation failed");
                 }
                 if result.has_errors() {
-                    defmt::warn!("UART error: {:?}", result.errors.unwrap());
+                    log::warn!("UART error: {:?}", result.errors.unwrap());
                 }
             }
             Err(e) => {
-                defmt::warn!("UART error: {:?}", e);
+                log::warn!("UART error: {:?}", e);
             }
         }
     }
@@ -253,7 +250,7 @@ mod app {
                 continue;
             }
             let packet_len = packet_len.unwrap();
-            defmt::info!("received packet with length {}", packet_len);
+            log::info!(target: "TC Handler", "received packet with length {}", packet_len);
             let popped_packet_len = cx
                 .shared
                 .tc_rb
@@ -267,7 +264,7 @@ mod app {
     fn handle_valid_pus_tc(cx: &mut pus_tc_handler::Context) {
         let pus_tc = PusTcReader::new(cx.local.tc_buf);
         if pus_tc.is_err() {
-            defmt::warn!("PUS TC error: {}", pus_tc.unwrap_err());
+            log::warn!(target: "TC Handler", "PUS TC error: {}", pus_tc.unwrap_err());
             return;
         }
         let (pus_tc, _) = pus_tc.unwrap();
@@ -313,25 +310,22 @@ mod app {
                 write_and_send(&tm);
             };
             if pus_tc.subservice() == ActionId::CorruptImageA as u8 {
-                defmt::info!("corrupting App Image A");
+                rprintln!("corrupting App Image A");
                 corrupt_image(APP_A_START_ADDR);
             }
             if pus_tc.subservice() == ActionId::CorruptImageB as u8 {
-                defmt::info!("corrupting App Image B");
+                rprintln!("corrupting App Image B");
                 corrupt_image(APP_B_START_ADDR);
             }
             if pus_tc.subservice() == ActionId::SetBootSlot as u8 {
                 if pus_tc.app_data().is_empty() {
-                    defmt::warn!("App data for preferred image command too short");
+                    log::warn!(target: "TC Handler", "App data for preferred image command too short");
                 }
                 let app_sel_result = AppSel::try_from(pus_tc.app_data()[0]);
                 if app_sel_result.is_err() {
-                    defmt::warn!("Invalid app selection value: {}", pus_tc.app_data()[0]);
+                    log::warn!("Invalid app selection value: {}", pus_tc.app_data()[0]);
                 }
-                defmt::info!(
+                log::info!(target: "TC Handler", "received boot selection command with app select: {:?}", app_sel_result.unwrap());
-                    "received boot selection command with app select: {:?}",
-                    app_sel_result.unwrap()
-                );
                 cx.local
                     .nvm
                     .write(PREFERRED_SLOT_OFFSET as usize, &[pus_tc.app_data()[0]])
@@ -345,7 +339,7 @@ mod app {
             }
         }
         if pus_tc.service() == PusServiceId::Test as u8 && pus_tc.subservice() == 1 {
-            defmt::info!("received ping TC");
+            log::info!(target: "TC Handler", "received ping TC");
             let tm = cx
                 .local
                 .verif_reporter
@@ -370,21 +364,23 @@ mod app {
             if pus_tc.subservice() == 2 {
                 let app_data = pus_tc.app_data();
                 if app_data.len() < 10 {
-                    defmt::warn!(
+                    log::warn!(
+                        target: "TC Handler",
                         "app data for raw memory write is too short: {}",
                         app_data.len()
                     );
                 }
                 let memory_id = app_data[0];
                 if memory_id != BOOT_NVM_MEMORY_ID {
-                    defmt::warn!("memory ID {} not supported", memory_id);
+                    log::warn!(target: "TC Handler", "memory ID {} not supported", memory_id);
                     // TODO: Error reporting
                     return;
                 }
                 let offset = u32::from_be_bytes(app_data[2..6].try_into().unwrap());
                 let data_len = u32::from_be_bytes(app_data[6..10].try_into().unwrap());
                 if 10 + data_len as usize > app_data.len() {
-                    defmt::warn!(
+                    log::warn!(
+                        target: "TC Handler",
                         "invalid data length {} for raw mem write detected",
                         data_len
                     );
@@ -392,7 +388,12 @@ mod app {
                     return;
                 }
                 let data = &app_data[10..10 + data_len as usize];
-                defmt::info!("writing {} bytes at offset {} to NVM", data_len, offset);
+                log::info!(
+                    target: "TC Handler",
+                    "writing {} bytes at offset {} to NVM",
+                    data_len,
+                    offset
+                );
                 cx.local
                     .nvm
                     .write(offset as usize, data)
@@ -403,7 +404,7 @@ mod app {
                     .verify(offset as usize, data)
                     .expect("NVM verification failed")
                 {
-                    defmt::warn!("verification of data written to NVM failed");
+                    log::warn!("verification of data written to NVM failed");
                     cx.local
                         .verif_reporter
                         .completion_failure(
@@ -421,7 +422,9 @@ mod app {
                         .expect("completion success failed")
                 };
                 write_and_send(&tm);
-                defmt::info!("NVM operation done");
+                log::info!(
+                    target: "TC Handler",
+                    "NVM operation done");
             }
         }
     }
@@ -452,7 +455,7 @@ mod app {
                 cx.local.encoded_buf[send_size + 1] = 0;
                 cx.local
                     .uart_tx
-                    .write_all(&cx.local.encoded_buf[0..send_size + 2])
+                    .write(&cx.local.encoded_buf[0..send_size + 2])
                     .unwrap();
                 occupied_len -= 1;
                 Mono::delay(2.millis()).await;

jlink-gdb.sh

@@ -1,3 +1,3 @@
 #!/bin/bash
-JLinkGDBServer -select USB -device VA10820 -endian little -if JTAG -speed auto \
+JLinkGDBServer -select USB -device Cortex-M0 -endian little -if JTAG -speed auto \
-  -LocalhostOnly -jtagconf -1,-1
+  -LocalhostOnly

scripts/defmt-telnet.sh

@@ -1,18 +0,0 @@
-#!/bin/bash
-
-# Check if binary path was provided
-if [ "$#" -ne 1 ]; then
-  echo "Usage: $0 <path-to-binary>"
-  exit 1
-fi
-
-BINARY="$1"
-
-# Check if file exists
-if [ ! -f "$BINARY" ]; then
-  echo "Error: File '$BINARY' not found."
-  exit 1
-fi
-
-# Run the command
-telnet localhost 19021 | defmt-print -e "$BINARY"

va108xx-embassy/CHANGELOG.md

@@ -1,31 +0,0 @@
-Change Log
-=======
-
-All notable changes to this project will be documented in this file.
-
-The format is based on [Keep a Changelog](http://keepachangelog.com/)
-and this project adheres to [Semantic Versioning](http://semver.org/).
-
-## [unreleased]
-
-## [v0.2.1] 2025-03-07
-
-- Bumped allowed va108xx-hal to v0.11
-
-## [v0.2.0] 2025-02-17
-
-- Bumped va108xx-hal to v0.10.0
-- Remove `embassy` module, expose public functions in library root directly
-
-
-## [v0.1.2] and [v0.1.1] 2025-02-13
-
-Docs patch
-
-## [v0.1.0] 2025-02-13
-
-Initial release
-
-[unreleased]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/compare/va108xx-embassy-v0.2.1...HEAD
-[v0.2.1]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/compare/va108xx-embassy-v0.2.0...va10xx-embassy-v0.2.1
-[v0.2.0]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/compare/va108xx-embassy-v0.1.2...va10xx-embassy-v0.2.0

va108xx-embassy/Cargo.toml

@@ -1,18 +1,21 @@
 [package]
 name = "va108xx-embassy"
-version = "0.2.1"
+version = "0.1.0"
 edition = "2021"
-authors = ["Robin Mueller <muellerr@irs.uni-stuttgart.de>"]
-description = "Embassy-rs support for the Vorago VA108xx family of microcontrollers"
-homepage = "https://egit.irs.uni-stuttgart.de/rust/va108xx-rs"
-repository = "https://egit.irs.uni-stuttgart.de/rust/va108xx-rs"
-license = "Apache-2.0"
-keywords = ["no-std", "hal", "cortex-m", "vorago", "va108xx"]
-categories = ["aerospace", "embedded", "no-std", "hardware-support"]
 
 [dependencies]
-vorago-shared-periphs = { git = "https://egit.irs.uni-stuttgart.de/rust/vorago-shared-periphs.git", features = ["vor1x"] }
+critical-section = "1"
-va108xx-hal = { path = "../va108xx-hal" }
+portable-atomic = { version = "1", features = ["unsafe-assume-single-core"]}
+
+embassy-sync = "0.6"
+embassy-executor = "0.7"
+embassy-time-driver = "0.2"
+embassy-time-queue-utils = "0.1"
+
+once_cell = { version = "1", default-features = false, features = ["critical-section"] }
+
+[dependencies.va108xx-hal]
+path = "../va108xx-hal"
 
 [features]
 default = ["irq-oc30-oc31"]
@@ -22,6 +25,3 @@ irqs-in-lib = []
 irq-oc28-oc29 = ["irqs-in-lib"]
 irq-oc29-oc30 = ["irqs-in-lib"]
 irq-oc30-oc31 = ["irqs-in-lib"]
-
-[package.metadata.docs.rs]
-rustdoc-args = ["--generate-link-to-definition"]

va108xx-embassy/docs.sh

@@ -1,3 +0,0 @@
-#!/bin/bash
-export RUSTDOCFLAGS="--cfg docsrs --generate-link-to-definition -Z unstable-options"
-cargo +nightly doc --open

va108xx-embassy/src/lib.rs

@@ -1,17 +1,17 @@
 //! # Embassy-rs support for the Vorago VA108xx MCU family
 //!
-//! This repository contains the [embassy-rs](https://github.com/embassy-rs/embassy) support for
+//! This repository contains the [embassy-rs](https://github.com/embassy-rs/embassy) support for the
-//! the VA108xx family. Currently, it contains the time driver to allow using embassy-rs. It uses
+//! VA108xx family. Currently, it contains the time driver to allow using embassy-rs. It uses the TIM
-//! the TIM peripherals provided by the VA108xx family for this purpose.
+//! peripherals provided by the VA108xx family for this purpose.
 //!
 //! ## Usage
 //!
-//! This library exposes the [init] or the [init_with_custom_irqs] functions which set up the time
+//! This library only exposes the [embassy::init] method which sets up the time driver. This
-//! driver. This function must be called once at the start of the application.
+//! function must be called once at the start of the application.
 //!
 //! This implementation requires two TIM peripherals provided by the VA108xx device.
 //! The user can freely specify the two used TIM peripheral by passing the concrete TIM instances
-//! into the [init_with_custom_irqs] and [init] method.
+//! into the [embassy::init_with_custom_irqs] and [embassy::init] method.
 //!
 //! The application also requires two interrupt handlers to handle the timekeeper and alarm
 //! interrupts. By default, this library will define the interrupt handler inside the library
@@ -23,21 +23,38 @@
 //!
 //! You can disable the default features and then specify one of the features above to use the
 //! documented combination of IRQs. It is also possible to specify custom IRQs by importing and
-//! using the [embassy_time_driver_irqs] macro to declare the IRQ handlers in the
+//! using the [embassy::embassy_time_driver_irqs] macro to declare the IRQ handlers in the
-//! application code. If this is done, [init_with_custom_irqs] must be used
+//! application code. If this is done, [embassy::init_with_custom_irqs] must be used
 //! method to pass the IRQ numbers to the library.
 //!
 //! ## Examples
 //!
-//! [embassy example projects](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/examples/embassy)
+//! [embassy example project](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/examples/embassy)
 #![no_std]
-#![cfg_attr(docsrs, feature(doc_auto_cfg))]
+use core::cell::{Cell, RefCell};
+use critical_section::CriticalSection;
+use embassy_sync::blocking_mutex::CriticalSectionMutex as Mutex;
+use portable_atomic::{AtomicU32, Ordering};
 
+use embassy_time_driver::{time_driver_impl, Driver, TICK_HZ};
+use embassy_time_queue_utils::Queue;
+use once_cell::sync::OnceCell;
 #[cfg(feature = "irqs-in-lib")]
-use va108xx_hal::pac::{self, interrupt};
+use va108xx_hal::pac::interrupt;
-use va108xx_hal::time::Hertz;
+use va108xx_hal::{
-use va108xx_hal::timer::TimMarker;
+    clock::enable_peripheral_clock,
-use vorago_shared_periphs::embassy::time_driver;
+    enable_interrupt, pac,
+    prelude::*,
+    timer::{enable_tim_clk, get_tim_raw, TimRegInterface},
+    PeripheralSelect,
+};
+
+time_driver_impl!(
+    static TIME_DRIVER: TimerDriver = TimerDriver {
+        periods: AtomicU32::new(0),
+        alarms: Mutex::new(AlarmState::new()),
+        queue: Mutex::new(RefCell::new(Queue::new())),
+});
 
 /// Macro to define the IRQ handlers for the time driver.
 ///
@@ -45,7 +62,7 @@ use vorago_shared_periphs::embassy::time_driver;
 /// the feature flags specified. However, the macro is exported to allow users to specify the
 /// interrupt handlers themselves.
 ///
-/// Please note that you have to explicitely import the [macro@va108xx_hal::pac::interrupt]
+/// Please note that you have to explicitely import the [va108xx_hal::pac::interrupt]
 /// macro in the application code in case this macro is used there.
 #[macro_export]
 macro_rules! embassy_time_driver_irqs {
@@ -59,7 +76,7 @@ macro_rules! embassy_time_driver_irqs {
         #[allow(non_snake_case)]
         fn $timekeeper_irq() {
             // Safety: We call it once here.
-            unsafe { $crate::time_driver().on_interrupt_timekeeping() }
+            unsafe { $crate::embassy::time_driver().on_interrupt_timekeeping() }
         }
 
         const ALARM_IRQ: pac::Interrupt = pac::Interrupt::$alarm_irq;
@@ -68,7 +85,7 @@ macro_rules! embassy_time_driver_irqs {
         #[allow(non_snake_case)]
         fn $alarm_irq() {
             // Safety: We call it once here.
-            unsafe { $crate::time_driver().on_interrupt_alarm() }
+            unsafe { $crate::embassy::time_driver().on_interrupt_alarm() }
         }
     };
 }
@@ -82,28 +99,318 @@ embassy_time_driver_irqs!(timekeeper_irq = OC30, alarm_irq = OC29);
 #[cfg(feature = "irq-oc28-oc29")]
 embassy_time_driver_irqs!(timekeeper_irq = OC29, alarm_irq = OC28);
 
-/// Initialization method for embassy.
+pub mod embassy {
-///
+    use super::*;
-/// This should be used if the interrupt handler is provided by the library, which is the
+    use va108xx_hal::{pac, timer::TimRegInterface};
-/// default case.
-#[cfg(feature = "irqs-in-lib")]
-pub fn init<TimekeeperTim: TimMarker, AlarmTim: TimMarker>(
-    timekeeper_tim: TimekeeperTim,
-    alarm_tim: AlarmTim,
-    sysclk: Hertz,
-) {
-    time_driver().__init(sysclk, timekeeper_tim, alarm_tim, TIMEKEEPER_IRQ, ALARM_IRQ)
-}
 
-/// Initialization method for embassy when using custom IRQ handlers.
+    /// Expose the time driver so the user can specify the IRQ handlers themselves.
-///
+    pub fn time_driver() -> &'static TimerDriver {
-/// Requires an explicit [pac::Interrupt] argument for the timekeeper and alarm IRQs.
+        &TIME_DRIVER
-pub fn init_with_custom_irqs<TimekeeperTim: TimMarker, AlarmTim: TimMarker>(
+    }
-    timekeeper_tim: TimekeeperTim,
+
-    alarm_tim: AlarmTim,
+    /// Initialization method for embassy
-    sysclk: Hertz,
+    ///
+    /// # Safety
+    ///
+    /// This has to be called once at initialization time to initiate the time driver for
+    /// embassy.
+    #[cfg(feature = "irqs-in-lib")]
+    pub unsafe fn init(
+        syscfg: &mut pac::Sysconfig,
+        irqsel: &pac::Irqsel,
+        sysclk: impl Into<Hertz>,
+        timekeeper_tim: impl TimRegInterface,
+        alarm_tim: impl TimRegInterface,
+    ) {
+        TIME_DRIVER.init(
+            syscfg,
+            irqsel,
+            sysclk,
+            timekeeper_tim,
+            alarm_tim,
+            TIMEKEEPER_IRQ,
+            ALARM_IRQ,
+        )
+    }
+
+    /// Initialization method for embassy
+    ///
+    /// # Safety
+    ///
+    /// This has to be called once at initialization time to initiate the time driver for
+    /// embassy.
+    pub unsafe fn init_with_custom_irqs(
+        syscfg: &mut pac::Sysconfig,
+        irqsel: &pac::Irqsel,
+        sysclk: impl Into<Hertz>,
+        timekeeper_tim: impl TimRegInterface,
+        alarm_tim: impl TimRegInterface,
         timekeeper_irq: pac::Interrupt,
         alarm_irq: pac::Interrupt,
-) {
+    ) {
-    time_driver().__init(sysclk, timekeeper_tim, alarm_tim, timekeeper_irq, alarm_irq)
+        TIME_DRIVER.init(
+            syscfg,
+            irqsel,
+            sysclk,
+            timekeeper_tim,
+            alarm_tim,
+            timekeeper_irq,
+            alarm_irq,
+        )
+    }
+}
+
+struct AlarmState {
+    timestamp: Cell<u64>,
+}
+
+impl AlarmState {
+    const fn new() -> Self {
+        Self {
+            timestamp: Cell::new(u64::MAX),
+        }
+    }
+}
+
+unsafe impl Send for AlarmState {}
+
+static SCALE: OnceCell<u64> = OnceCell::new();
+static TIMEKEEPER_TIM: OnceCell<u8> = OnceCell::new();
+static ALARM_TIM: OnceCell<u8> = OnceCell::new();
+
+pub struct TimerDriver {
+    periods: AtomicU32,
+    /// Timestamp at which to fire alarm. u64::MAX if no alarm is scheduled.
+    alarms: Mutex<AlarmState>,
+    queue: Mutex<RefCell<Queue>>,
+}
+
+impl TimerDriver {
+    #[allow(clippy::too_many_arguments)]
+    fn init(
+        &self,
+        syscfg: &mut pac::Sysconfig,
+        irqsel: &pac::Irqsel,
+        sysclk: impl Into<Hertz>,
+        timekeeper_tim: impl TimRegInterface,
+        alarm_tim: impl TimRegInterface,
+        timekeeper_irq: pac::Interrupt,
+        alarm_irq: pac::Interrupt,
+    ) {
+        if ALARM_TIM.get().is_some() {
+            return;
+        }
+        ALARM_TIM.set(alarm_tim.tim_id()).ok();
+        TIMEKEEPER_TIM.set(timekeeper_tim.tim_id()).ok();
+        enable_peripheral_clock(syscfg, PeripheralSelect::Irqsel);
+        enable_tim_clk(syscfg, timekeeper_tim.tim_id());
+        let timekeeper_reg_block = timekeeper_tim.reg_block();
+        let alarm_tim_reg_block = alarm_tim.reg_block();
+        let sysclk = sysclk.into();
+        // Initiate scale value here. This is required to convert timer ticks back to a timestamp.
+        SCALE.set((sysclk.raw() / TICK_HZ as u32) as u64).unwrap();
+        timekeeper_reg_block
+            .rst_value()
+            .write(|w| unsafe { w.bits(u32::MAX) });
+        // Decrementing counter.
+        timekeeper_reg_block
+            .cnt_value()
+            .write(|w| unsafe { w.bits(u32::MAX) });
+        // Switch on. Timekeeping should always be done.
+        irqsel
+            .tim0(timekeeper_tim.tim_id() as usize)
+            .write(|w| unsafe { w.bits(timekeeper_irq as u32) });
+        unsafe {
+            enable_interrupt(timekeeper_irq);
+        }
+        timekeeper_reg_block
+            .ctrl()
+            .modify(|_, w| w.irq_enb().set_bit());
+        timekeeper_reg_block
+            .enable()
+            .write(|w| unsafe { w.bits(1) });
+
+        enable_tim_clk(syscfg, alarm_tim.tim_id());
+
+        // Explicitely disable alarm timer until needed.
+        alarm_tim_reg_block.ctrl().modify(|_, w| {
+            w.irq_enb().clear_bit();
+            w.enable().clear_bit()
+        });
+        // Enable general interrupts. The IRQ enable of the peripheral remains cleared.
+        unsafe {
+            enable_interrupt(alarm_irq);
+        }
+        irqsel
+            .tim0(alarm_tim.tim_id() as usize)
+            .write(|w| unsafe { w.bits(alarm_irq as u32) });
+    }
+
+    /// Should be called inside the IRQ of the timekeeper timer.
+    ///
+    /// # Safety
+    ///
+    /// This function has to be called once by the TIM IRQ used for the timekeeping.
+    pub unsafe fn on_interrupt_timekeeping(&self) {
+        self.next_period();
+    }
+
+    /// Should be called inside the IRQ of the alarm timer.
+    ///
+    /// # Safety
+    ///
+    ///This function has to be called once by the TIM IRQ used for the timekeeping.
+    pub unsafe fn on_interrupt_alarm(&self) {
+        critical_section::with(|cs| {
+            if self.alarms.borrow(cs).timestamp.get() <= self.now() {
+                self.trigger_alarm(cs)
+            }
+        })
+    }
+
+    fn timekeeper_tim() -> &'static pac::tim0::RegisterBlock {
+        TIMEKEEPER_TIM
+            .get()
+            .map(|idx| unsafe { get_tim_raw(*idx as usize) })
+            .unwrap()
+    }
+    fn alarm_tim() -> &'static pac::tim0::RegisterBlock {
+        ALARM_TIM
+            .get()
+            .map(|idx| unsafe { get_tim_raw(*idx as usize) })
+            .unwrap()
+    }
+
+    fn next_period(&self) {
+        let period = self.periods.fetch_add(1, Ordering::AcqRel) + 1;
+        let t = (period as u64) << 32;
+        critical_section::with(|cs| {
+            let alarm = &self.alarms.borrow(cs);
+            let at = alarm.timestamp.get();
+            if at < t {
+                self.trigger_alarm(cs);
+            } else {
+                let alarm_tim = Self::alarm_tim();
+
+                let remaining_ticks = (at - t).checked_mul(*SCALE.get().unwrap());
+                if remaining_ticks.is_some_and(|v| v <= u32::MAX as u64) {
+                    alarm_tim.enable().write(|w| unsafe { w.bits(0) });
+                    alarm_tim
+                        .cnt_value()
+                        .write(|w| unsafe { w.bits(remaining_ticks.unwrap() as u32) });
+                    alarm_tim.ctrl().modify(|_, w| w.irq_enb().set_bit());
+                    alarm_tim.enable().write(|w| unsafe { w.bits(1) })
+                }
+            }
+        })
+    }
+
+    fn trigger_alarm(&self, cs: CriticalSection) {
+        Self::alarm_tim().ctrl().modify(|_, w| {
+            w.irq_enb().clear_bit();
+            w.enable().clear_bit()
+        });
+
+        let alarm = &self.alarms.borrow(cs);
+        // Setting the maximum value disables the alarm.
+        alarm.timestamp.set(u64::MAX);
+
+        // Call after clearing alarm, so the callback can set another alarm.
+        let mut next = self
+            .queue
+            .borrow(cs)
+            .borrow_mut()
+            .next_expiration(self.now());
+        while !self.set_alarm(cs, next) {
+            next = self
+                .queue
+                .borrow(cs)
+                .borrow_mut()
+                .next_expiration(self.now());
+        }
+    }
+
+    fn set_alarm(&self, cs: CriticalSection, timestamp: u64) -> bool {
+        if SCALE.get().is_none() {
+            return false;
+        }
+        let alarm_tim = Self::alarm_tim();
+        alarm_tim.ctrl().modify(|_, w| {
+            w.irq_enb().clear_bit();
+            w.enable().clear_bit()
+        });
+
+        let alarm = self.alarms.borrow(cs);
+        alarm.timestamp.set(timestamp);
+
+        let t = self.now();
+        if timestamp <= t {
+            alarm.timestamp.set(u64::MAX);
+            return false;
+        }
+
+        // If it hasn't triggered yet, setup the relevant reset value, regardless of whether
+        // the interrupts are enabled or not. When they are enabled at a later point, the
+        // right value is already set.
+
+        // If the timestamp is in the next few ticks, add a bit of buffer to be sure the alarm
+        // is not missed.
+        //
+        // This means that an alarm can be delayed for up to 2 ticks (from t+1 to t+3), but this is allowed
+        // by the Alarm trait contract. What's not allowed is triggering alarms *before* their scheduled time,
+        // and we don't do that here.
+        let safe_timestamp = timestamp.max(t + 3);
+        let timer_ticks = (safe_timestamp - t).checked_mul(*SCALE.get().unwrap());
+        alarm_tim.rst_value().write(|w| unsafe { w.bits(u32::MAX) });
+        if timer_ticks.is_some_and(|v| v <= u32::MAX as u64) {
+            alarm_tim
+                .cnt_value()
+                .write(|w| unsafe { w.bits(timer_ticks.unwrap() as u32) });
+            alarm_tim.ctrl().modify(|_, w| w.irq_enb().set_bit());
+            alarm_tim.enable().write(|w| unsafe { w.bits(1) });
+        }
+        // If it's too far in the future, don't enable timer yet.
+        // It will be enabled later by `next_period`.
+
+        true
+    }
+}
+
+impl Driver for TimerDriver {
+    fn now(&self) -> u64 {
+        if SCALE.get().is_none() {
+            return 0;
+        }
+        let mut period1: u32;
+        let mut period2: u32;
+        let mut counter_val: u32;
+
+        loop {
+            // Acquire ensures that we get the latest value of `periods` and
+            // no instructions can be reordered before the load.
+            period1 = self.periods.load(Ordering::Acquire);
+
+            counter_val = u32::MAX - Self::timekeeper_tim().cnt_value().read().bits();
+
+            // Double read to protect against race conditions when the counter is overflowing.
+            period2 = self.periods.load(Ordering::Relaxed);
+            if period1 == period2 {
+                let now = (((period1 as u64) << 32) | counter_val as u64) / *SCALE.get().unwrap();
+                return now;
+            }
+        }
+    }
+
+    fn schedule_wake(&self, at: u64, waker: &core::task::Waker) {
+        critical_section::with(|cs| {
+            let mut queue = self.queue.borrow(cs).borrow_mut();
+
+            if queue.schedule_wake(at, waker) {
+                let mut next = queue.next_expiration(self.now());
+                while !self.set_alarm(cs, next) {
+                    next = queue.next_expiration(self.now());
+                }
+            }
+        })
+    }
 }

va108xx-hal/CHANGELOG.md

@@ -8,63 +8,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ## [unreleased]
 
-## Changed
+## [v0.9.0]
-
-- Move most library components to new [`vorago-shared-periphs`](https://egit.irs.uni-stuttgart.de/rust/vorago-shared-periphs)
-  which is mostly re-exported in this crate.
-- Overhaul and simplification of several HAL APIs. The system configuration and IRQ router
-  peripheral instance generally does not need to be passed to HAL API anymore.
-- All HAL drivers are now type erased. The constructors will still expect and consume the PAC
-  singleton component for resource management purposes, but are not cached anymore.
-- Refactoring of GPIO library to be more inline with embassy GPIO API.
-
-## Added
-
-- I2C clock timeout feature support.
-
-## [v0.11.1] 2025-03-10
-
-## Fixed
-
-- Fix `embedded_io` UART implementation to implement the documented contract properly.
-  The implementation will now block until at least one byte is available or can be written, unless
-  the send or receive buffer is empty.
-
-## [v0.11.0] 2025-03-07
-
-## Changed
-
-- Bugfix for I2C `TimingCfg::reg`
-- Simplified UART error handling. All APIs are now infallible because writing to a FIFO or
-  reading from a FIFO never fails. Users can either poll errors using `Rx::poll_errors` or
-  `Uart::poll_rx_errors` / `UartBase::poll_rx_errors`, or detect errors using the provided
-  interrupt handlers.
-
-## [v0.10.0] 2025-02-17
-
-## Added
-
-- A lot of missing `defmt::Format` implementations.
-
-## Changed
-
-- Larger refactoring of GPIO library. The edge and level interrupt configurator functions do not
-  enable interrupts anymore. Instead, there are explicit `enbable_interrupt` and
-  `disable_interrupt` methods
-- Renamed GPIO `DynGroup` to `Port`
-- Rename generic GPIO interrupt handler into `on_interrupt_for_asynch_gpio`
-  into `on_interrupt_for_async_gpio_for_port` which expects a Port argument
-
-## Fixed
-
-- Bug in async GPIO interrupt handler where all enabled interrupts, even the ones which might
-  be unrelated to the pin, were disabled.
-
-## [v0.9.0] 2025-02-13
-
-## Fixed
-
-- Important bugfix for UART driver which causes UART B drivers not to work.
 
 ## Removed
 
@@ -79,32 +23,12 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 - `InvalidPinTypeError` now wraps the pin mode.
 - I2C `TimingCfg` constructor now returns explicit error instead of generic Error.
   Removed the timing configuration error type from the generic I2C error enumeration.
-- `PinsA` and `PinsB` constructor do not expect an optional `pac::Ioconfig` argument anymore.
-- `IrqCfg` renamed to `InterruptConfig`, kept alias for old name.
-- All library provided interrupt handlers now start with common prefix `on_interrupt_*`
-- `RxWithIrq` renamed to `RxWithInterrupt`
-- `Rx::into_rx_with_irq` does not expect any arguments any more.
-- `filter_type` renamed to `configure_filter_type`.
-- `level_irq` renamed to `configure_level_interrupt`.
-- `edge_irq` renamed to `configure_edge_interrupt`.
-- `PinsA` and `PinsB` constructor do not expect an optional IOCONFIG argument anymore.
-- UART interrupt management is now handled by the main constructor instead of later stages to
-  statically ensure one interrupt vector for the UART peripheral. `Uart::new` expects an
-  optional `InterruptConfig` argument.
-- `enable_interrupt` and `disable_interrupt` renamed to `enable_nvic_interrupt` and
-  `disable_nvic_interrupt` to distinguish them from peripheral interrupts more clearly.
-- `port_mux` renamed to `port_function_select`
-- Renamed `IrqUartErrors` to `UartErrors`.
 
 ## Added
 
 - Add `downgrade` method for `Pin` and `upgrade` method for `DynPin` as explicit conversion
   methods.
-- Asynchronous GPIO support.
-- Asynchronous UART TX support.
-- Asynchronous UART RX support.
 - Add new `get_tim_raw` unsafe method to retrieve TIM peripheral blocks.
-- `Uart::with_with_interrupt` and `Uart::new_without_interrupt`
 
 ## [v0.8.0] 2024-09-30
 
@@ -136,14 +60,14 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 - Updated `embedded-hal` to v1
 - Added optional `defmt` v0.3 feature and support.
 
-## v0.5.2 2024-06-16
+## [v0.5.2] 2024-06-16
 
 ## Fixed
 
 - Replaced usage to `ptr::write_volatile` in UART module which is denied on more recent Rust
   compilers.
 
-## v0.5.1
+## [v0.5.1]
 
 ### Changes
 
@@ -152,7 +76,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
   - `once_cell` to 1.12.0
   - Other dependencies: Only revision has changed
 
-## v0.5.0
+## [v0.5.0]
 
 ### Added
 
@@ -165,14 +89,14 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 - Bugfix in UART code where RX and TX could not be enabled or disabled independently
 
-## v0.4.3
+## [v0.4.3]
 
 - Various smaller fixes for READMEs, update of links in documentation
 - Simplified CI for github, do not use `cross`
 - New `blinky-pac` example
 - Use HAL delay in `blinky` example
 
-## v0.4.2
+## [v0.4.2]
 
 ### Added
 
@@ -182,24 +106,24 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 - Clear TX and RX FIFO in SPI transfer function
 
-## v0.4.1
+## [v0.4.1]
 
 ### Fixed
 
 - Initial blockmode setting was not set in SPI constructor
 
-## v0.4.0
+## [v0.4.0]
 
 ### Changed
 
 - Replaced `Hertz` by `impl Into<Hertz>` completely and removed
   `+ Copy` where not necessary
 
-## v0.3.1
+## [v0.3.1]
 
 - Updated all links to point to new repository
 
-## v0.3.0
+## [v0.3.0]
 
 ### Added
 
@@ -211,7 +135,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 - Primary repository now hosted on IRS external git: https://egit.irs.uni-stuttgart.de/rust/va108xx-hal
 - Relicensed as Apache-2.0
 
-## v0.2.3
+## [0.2.3]
 
 ### Added
 
@@ -223,7 +147,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 - Improved Timer API. It is now possible to simply use `new` on `CountDownTimer`
 
-## v0.2.2
+## [0.2.2]
 
 ### Added
 
@@ -235,7 +159,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 - API which expects values in Hertz now uses `impl Into<Hertz>` as input parameter
 
-## v0.2.1
+## [0.2.1]
 
 ### Added
 
@@ -249,7 +173,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 - Moved the `FilterClkSel` struct to the `clock` module, re-exporting in `gpio`
 - Clearing output state at initialization of Output pins
 
-## v0.2.0
+## [0.2.0]
 
 ### Changed
 
@@ -264,7 +188,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 - Some bugfixes for GPIO implementation
 - Rust edition updated to 2021
 
-## v0.1.0
+## [0.1.0]
 
 ### Added
 
@@ -273,12 +197,3 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 - RTT example application
 - Added basic test binary in form of an example
 - README with basic instructions how to set up own binary crate
-
-[unreleased]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/compare/va108xx-hal-v0.11.0...HEAD
-[v0.11.1]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/compare/va108xx-hal-v0.11.0...va108xx-hal-v0.11.1
-[v0.11.0]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/compare/va108xx-hal-v0.10.0...va108xx-hal-v0.11.0
-[v0.10.0]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/compare/va108xx-hal-v0.9.0...va108xx-hal-v0.10.0
-[v0.9.0]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/compare/va108xx-hal-v0.8.0...va108xx-hal-v0.9.0
-[v0.8.0]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/compare/va108xx-hal-v0.7.0...va108xx-hal-v0.8.0
-[v0.7.0]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/compare/va108xx-hal-v0.6.0...va108xx-hal-v0.7.0
-[v0.6.0]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/tag/va108xx-hal-v0.6.0

va108xx-hal/Cargo.toml

@@ -1,6 +1,6 @@
 [package]
 name = "va108xx-hal"
-version = "0.11.1"
+version = "0.8.0"
 authors = ["Robin Mueller <muellerr@irs.uni-stuttgart.de>"]
 edition = "2021"
 description = "HAL for the Vorago VA108xx family of microcontrollers"
@@ -12,25 +12,28 @@ categories = ["aerospace", "embedded", "no-std", "hardware-support"]
 
 [dependencies]
 cortex-m = { version = "0.7", features = ["critical-section-single-core"]}
-vorago-shared-periphs = { git = "https://egit.irs.uni-stuttgart.de/rust/vorago-shared-periphs.git", features = ["vor1x"] }
+cortex-m-rt = "0.7"
+nb = "1"
+paste = "1"
+embedded-hal = "1"
+embedded-hal-nb = "1"
+embedded-io = "0.6"
 fugit = "0.3"
+typenum = "1"
+critical-section = "1"
+delegate = ">=0.12, <=0.13"
 thiserror = { version = "2", default-features = false }
-va108xx = { version = "0.5", default-features = false, features = ["critical-section", "defmt"] }
+void = { version = "1", default-features = false }
-defmt = { version = "0.3", optional = true }
+once_cell = {version = "1", default-features = false }
+va108xx = { version = "0.3", default-features = false, features = ["critical-section"]}
 
-[target.'cfg(all(target_arch = "arm", target_os = "none"))'.dependencies]
+defmt = { version = "0.3", optional = true }
-portable-atomic = { version = "1", features = ["unsafe-assume-single-core"] }
-[target.'cfg(not(all(target_arch = "arm", target_os = "none")))'.dependencies]
-portable-atomic = "1"
 
 [features]
 default = ["rt"]
 rt = ["va108xx/rt"]
-defmt = ["dep:defmt", "vorago-shared-periphs/defmt"]
+defmt = ["dep:defmt", "fugit/defmt"]
 
 [package.metadata.docs.rs]
 all-features = true
 rustdoc-args = ["--generate-link-to-definition"]
-
-[package.metadata.cargo-machete]
-ignored = ["cortex-m"]

va108xx-hal/README.md

@@ -25,6 +25,12 @@ rustup target add thumbv6m-none-eabi
 
 After that, you can use `cargo build` to build the development version of the crate.
 
+If you have not done this yet, it is recommended to read some of the excellent resources
+available to learn Rust:
+
+- [Rust Embedded Book](https://docs.rust-embedded.org/book/)
+- [Rust Discovery Book](https://docs.rust-embedded.org/discovery/)
+
 ## Setting up your own binary crate
 
 If you have a custom board, you might be interested in setting up a new binary crate for your
@@ -59,11 +65,3 @@ is contained within the
 
 7. Flashing the board might work differently for different boards and there is usually
    more than one way. You can find example instructions in primary README.
-
-## Embedded Rust
-
-If you have not done this yet, it is recommended to read some of the excellent resources available
-to learn Rust:
-
-- [Rust Embedded Book](https://docs.rust-embedded.org/book/)
-- [Rust Discovery Book](https://docs.rust-embedded.org/discovery/)

va108xx-hal/docs.sh

@@ -1,3 +0,0 @@
-#!/bin/sh
-export RUSTDOCFLAGS="--cfg docsrs --generate-link-to-definition -Z unstable-options"
-cargo +nightly doc --all-features --open

va108xx-hal/src/clock.rs

@@ -1,32 +1,64 @@
 //! # API for clock related functionality
 //!
 //! This also includes functionality to enable the peripheral clocks
-pub use vorago_shared_periphs::gpio::FilterClkSel;
+use crate::time::Hertz;
-pub use vorago_shared_periphs::sysconfig::{disable_peripheral_clock, enable_peripheral_clock};
+use crate::PeripheralSelect;
+use cortex_m::interrupt::{self, Mutex};
+use once_cell::unsync::OnceCell;
+
+static SYS_CLOCK: Mutex<OnceCell<Hertz>> = Mutex::new(OnceCell::new());
+
+pub type PeripheralClocks = PeripheralSelect;
+
+#[derive(Debug, PartialEq, Eq)]
+pub enum FilterClkSel {
+    SysClk = 0,
+    Clk1 = 1,
+    Clk2 = 2,
+    Clk3 = 3,
+    Clk4 = 4,
+    Clk5 = 5,
+    Clk6 = 6,
+    Clk7 = 7,
+}
+
+/// The Vorago in powered by an external clock which might have different frequencies.
+/// The clock can be set here so it can be used by other software components as well.
+/// The clock can be set exactly once
+pub fn set_sys_clock(freq: impl Into<Hertz>) {
+    interrupt::free(|cs| {
+        SYS_CLOCK.borrow(cs).set(freq.into()).ok();
+    })
+}
+
+/// Returns the configured system clock
+pub fn get_sys_clock() -> Option<Hertz> {
+    interrupt::free(|cs| SYS_CLOCK.borrow(cs).get().copied())
+}
 
 pub fn set_clk_div_register(syscfg: &mut va108xx::Sysconfig, clk_sel: FilterClkSel, div: u32) {
     match clk_sel {
         FilterClkSel::SysClk => (),
-        FilterClkSel::Clk1 => {
+        FilterClkSel::Clk1 => syscfg.ioconfig_clkdiv1().write(|w| unsafe { w.bits(div) }),
-            syscfg.ioconfig_clkdiv1().write(|w| unsafe { w.bits(div) });
+        FilterClkSel::Clk2 => syscfg.ioconfig_clkdiv2().write(|w| unsafe { w.bits(div) }),
-        }
+        FilterClkSel::Clk3 => syscfg.ioconfig_clkdiv3().write(|w| unsafe { w.bits(div) }),
-        FilterClkSel::Clk2 => {
+        FilterClkSel::Clk4 => syscfg.ioconfig_clkdiv4().write(|w| unsafe { w.bits(div) }),
-            syscfg.ioconfig_clkdiv2().write(|w| unsafe { w.bits(div) });
+        FilterClkSel::Clk5 => syscfg.ioconfig_clkdiv5().write(|w| unsafe { w.bits(div) }),
-        }
+        FilterClkSel::Clk6 => syscfg.ioconfig_clkdiv6().write(|w| unsafe { w.bits(div) }),
-        FilterClkSel::Clk3 => {
+        FilterClkSel::Clk7 => syscfg.ioconfig_clkdiv7().write(|w| unsafe { w.bits(div) }),
-            syscfg.ioconfig_clkdiv3().write(|w| unsafe { w.bits(div) });
-        }
-        FilterClkSel::Clk4 => {
-            syscfg.ioconfig_clkdiv4().write(|w| unsafe { w.bits(div) });
-        }
-        FilterClkSel::Clk5 => {
-            syscfg.ioconfig_clkdiv5().write(|w| unsafe { w.bits(div) });
-        }
-        FilterClkSel::Clk6 => {
-            syscfg.ioconfig_clkdiv6().write(|w| unsafe { w.bits(div) });
-        }
-        FilterClkSel::Clk7 => {
-            syscfg.ioconfig_clkdiv7().write(|w| unsafe { w.bits(div) });
-        }
     }
 }
+
+#[inline]
+pub fn enable_peripheral_clock(syscfg: &mut va108xx::Sysconfig, clock: PeripheralClocks) {
+    syscfg
+        .peripheral_clk_enable()
+        .modify(|r, w| unsafe { w.bits(r.bits() | (1 << clock as u8)) });
+}
+
+#[inline]
+pub fn disable_peripheral_clock(syscfg: &mut va108xx::Sysconfig, clock: PeripheralClocks) {
+    syscfg
+        .peripheral_clk_enable()
+        .modify(|r, w| unsafe { w.bits(r.bits() & !(1 << clock as u8)) });
+}

va108xx-hal/src/gpio/dynpin.rs

@@ -0,0 +1,591 @@
+//! # Type-erased, value-level module for GPIO pins
+//!
+//! Although the type-level API is generally preferred, it is not suitable in
+//! all cases. Because each pin is represented by a distinct type, it is not
+//! possible to store multiple pins in a homogeneous data structure. The
+//! value-level API solves this problem by erasing the type information and
+//! tracking the pin at run-time.
+//!
+//! Value-level pins are represented by the [`DynPin`] type. [`DynPin`] has two
+//! fields, `id` and `mode` with types [`DynPinId`] and [`DynPinMode`]
+//! respectively. The implementation of these types closely mirrors the
+//! type-level API.
+//!
+//! Instances of [`DynPin`] cannot be created directly. Rather, they must be
+//! created from their type-level equivalents using [`From`]/[`Into`].
+//!
+//! ```
+//! // Move a pin out of the Pins struct and convert to a DynPin
+//! let pa0: DynPin = pins.pa0.into();
+//! ```
+//!
+//! Conversions between pin modes use a value-level version of the type-level
+//! API.
+//!
+//! ```
+//! // Use one of the literal function names
+//! pa0.into_floating_input();
+//! // Use a method and a DynPinMode variant
+//! pa0.into_mode(DYN_FLOATING_INPUT);
+//! ```
+//!
+//! Because the pin state cannot be tracked at compile-time, many [`DynPin`]
+//! operations become fallible. Run-time checks are inserted to ensure that
+//! users don't try to, for example, set the output level of an input pin.
+//!
+//! Users may try to convert value-level pins back to their type-level
+//! equivalents. However, this option is fallible, because the compiler cannot
+//! guarantee the pin has the correct ID or is in the correct mode at
+//! compile-time. Use [TryFrom]/[TryInto] for this conversion.
+//!
+//! ```
+//! // Convert to a `DynPin`
+//! let pa0: DynPin = pins.pa0.into();
+//! // Change pin mode
+//! pa0.into_floating_input();
+//! // Convert back to a `Pin`
+//! let pa0: Pin<PA0, FloatingInput> = pa0.try_into().unwrap();
+//! ```
+//!
+//! # Embedded HAL traits
+//!
+//! This module implements all of the embedded HAL GPIO traits for [`DynPin`].
+//! However, whereas the type-level API uses
+//! `Error = core::convert::Infallible`, the value-level API can return a real
+//! error. If the [`DynPin`] is not in the correct [`DynPinMode`] for the
+//! operation, the trait functions will return
+//! [InvalidPinTypeError].
+
+use super::{
+    pin::{FilterType, InterruptEdge, InterruptLevel, Pin, PinId, PinMode, PinState},
+    reg::RegisterInterface,
+};
+use crate::{clock::FilterClkSel, pac, FunSel, IrqCfg};
+
+//==================================================================================================
+//  DynPinMode configurations
+//==================================================================================================
+
+/// Value-level `enum` for disabled configurations
+#[derive(PartialEq, Eq, Clone, Copy)]
+pub enum DynDisabled {
+    Floating,
+    PullDown,
+    PullUp,
+}
+
+/// Value-level `enum` for input configurations
+#[derive(Debug, PartialEq, Eq, Clone, Copy)]
+pub enum DynInput {
+    Floating,
+    PullDown,
+    PullUp,
+}
+
+/// Value-level `enum` for output configurations
+#[derive(Debug, PartialEq, Eq, Clone, Copy)]
+pub enum DynOutput {
+    PushPull,
+    OpenDrain,
+    ReadablePushPull,
+    ReadableOpenDrain,
+}
+
+pub type DynAlternate = FunSel;
+
+//==============================================================================
+//  Error
+//==============================================================================
+
+/// GPIO error type
+///
+/// [`DynPin`]s are not tracked and verified at compile-time, so run-time
+/// operations are fallible. This `enum` represents the corresponding errors.
+#[derive(Debug, PartialEq, Eq, thiserror::Error)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[error("Invalid pin type for operation: {0:?}")]
+pub struct InvalidPinTypeError(DynPinMode);
+
+impl embedded_hal::digital::Error for InvalidPinTypeError {
+    fn kind(&self) -> embedded_hal::digital::ErrorKind {
+        embedded_hal::digital::ErrorKind::Other
+    }
+}
+
+//==================================================================================================
+//  DynPinMode
+//==================================================================================================
+
+/// Value-level `enum` representing pin modes
+#[derive(Debug, PartialEq, Eq, Clone, Copy)]
+pub enum DynPinMode {
+    Input(DynInput),
+    Output(DynOutput),
+    Alternate(DynAlternate),
+}
+
+/// Value-level variant of [`DynPinMode`] for floating input mode
+pub const DYN_FLOATING_INPUT: DynPinMode = DynPinMode::Input(DynInput::Floating);
+/// Value-level variant of [`DynPinMode`] for pull-down input mode
+pub const DYN_PULL_DOWN_INPUT: DynPinMode = DynPinMode::Input(DynInput::PullDown);
+/// Value-level variant of [`DynPinMode`] for pull-up input mode
+pub const DYN_PULL_UP_INPUT: DynPinMode = DynPinMode::Input(DynInput::PullUp);
+
+/// Value-level variant of [`DynPinMode`] for push-pull output mode
+pub const DYN_PUSH_PULL_OUTPUT: DynPinMode = DynPinMode::Output(DynOutput::PushPull);
+/// Value-level variant of [`DynPinMode`] for open-drain output mode
+pub const DYN_OPEN_DRAIN_OUTPUT: DynPinMode = DynPinMode::Output(DynOutput::OpenDrain);
+/// Value-level variant of [`DynPinMode`] for readable push-pull output mode
+pub const DYN_RD_PUSH_PULL_OUTPUT: DynPinMode = DynPinMode::Output(DynOutput::ReadablePushPull);
+/// Value-level variant of [`DynPinMode`] for readable opendrain output mode
+pub const DYN_RD_OPEN_DRAIN_OUTPUT: DynPinMode = DynPinMode::Output(DynOutput::ReadableOpenDrain);
+
+/// Value-level variant of [`DynPinMode`] for function select 1
+pub const DYN_ALT_FUNC_1: DynPinMode = DynPinMode::Alternate(DynAlternate::Sel1);
+/// Value-level variant of [`DynPinMode`] for function select 2
+pub const DYN_ALT_FUNC_2: DynPinMode = DynPinMode::Alternate(DynAlternate::Sel2);
+/// Value-level variant of [`DynPinMode`] for function select 3
+pub const DYN_ALT_FUNC_3: DynPinMode = DynPinMode::Alternate(DynAlternate::Sel3);
+
+//==================================================================================================
+//  DynGroup & DynPinId
+//==================================================================================================
+
+/// Value-level `enum` for pin groups
+#[derive(PartialEq, Eq, Clone, Copy)]
+pub enum DynGroup {
+    A,
+    B,
+}
+
+/// Value-level `struct` representing pin IDs
+#[derive(PartialEq, Eq, Clone, Copy)]
+pub struct DynPinId {
+    pub group: DynGroup,
+    pub num: u8,
+}
+
+//==================================================================================================
+//  DynRegisters
+//==================================================================================================
+
+/// Provide a safe register interface for [`DynPin`]s
+///
+/// This `struct` takes ownership of a [`DynPinId`] and provides an API to
+/// access the corresponding regsiters.
+pub(crate) struct DynRegisters {
+    id: DynPinId,
+}
+
+// [`DynRegisters`] takes ownership of the [`DynPinId`], and [`DynPin`]
+// guarantees that each pin is a singleton, so this implementation is safe.
+unsafe impl RegisterInterface for DynRegisters {
+    #[inline]
+    fn id(&self) -> DynPinId {
+        self.id
+    }
+}
+
+impl DynRegisters {
+    /// Create a new instance of [`DynRegisters`]
+    ///
+    /// # Safety
+    ///
+    /// Users must never create two simultaneous instances of this `struct` with
+    /// the same [`DynPinId`]
+    #[inline]
+    unsafe fn new(id: DynPinId) -> Self {
+        DynRegisters { id }
+    }
+}
+
+//==================================================================================================
+//  DynPin
+//==================================================================================================
+
+/// A value-level pin, parameterized by [`DynPinId`] and [`DynPinMode`]
+///
+/// This type acts as a type-erased version of [`Pin`]. Every pin is represented
+/// by the same type, and pins are tracked and distinguished at run-time.
+pub struct DynPin {
+    pub(crate) regs: DynRegisters,
+    mode: DynPinMode,
+}
+
+impl DynPin {
+    /// Create a new [`DynPin`]
+    ///
+    /// # Safety
+    ///
+    /// Each [`DynPin`] must be a singleton. For a given [`DynPinId`], there
+    /// must be at most one corresponding [`DynPin`] in existence at any given
+    /// time.  Violating this requirement is `unsafe`.
+    #[inline]
+    pub(crate) unsafe fn new(id: DynPinId, mode: DynPinMode) -> Self {
+        DynPin {
+            regs: DynRegisters::new(id),
+            mode,
+        }
+    }
+
+    /// Return a copy of the pin ID
+    #[inline]
+    pub fn id(&self) -> DynPinId {
+        self.regs.id
+    }
+
+    /// Return a copy of the pin mode
+    #[inline]
+    pub fn mode(&self) -> DynPinMode {
+        self.mode
+    }
+
+    /// Convert the pin to the requested [`DynPinMode`]
+    #[inline]
+    pub fn into_mode(&mut self, mode: DynPinMode) {
+        // Only modify registers if we are actually changing pin mode
+        if mode != self.mode {
+            self.regs.change_mode(mode);
+            self.mode = mode;
+        }
+    }
+
+    #[inline]
+    pub fn into_funsel_1(&mut self) {
+        self.into_mode(DYN_ALT_FUNC_1);
+    }
+
+    #[inline]
+    pub fn into_funsel_2(&mut self) {
+        self.into_mode(DYN_ALT_FUNC_2);
+    }
+
+    #[inline]
+    pub fn into_funsel_3(&mut self) {
+        self.into_mode(DYN_ALT_FUNC_3);
+    }
+
+    /// Configure the pin to operate as a floating input
+    #[inline]
+    pub fn into_floating_input(&mut self) {
+        self.into_mode(DYN_FLOATING_INPUT);
+    }
+
+    /// Configure the pin to operate as a pulled down input
+    #[inline]
+    pub fn into_pull_down_input(&mut self) {
+        self.into_mode(DYN_PULL_DOWN_INPUT);
+    }
+
+    /// Configure the pin to operate as a pulled up input
+    #[inline]
+    pub fn into_pull_up_input(&mut self) {
+        self.into_mode(DYN_PULL_UP_INPUT);
+    }
+
+    /// Configure the pin to operate as a push-pull output
+    #[inline]
+    pub fn into_push_pull_output(&mut self) {
+        self.into_mode(DYN_PUSH_PULL_OUTPUT);
+    }
+
+    /// Configure the pin to operate as a push-pull output
+    #[inline]
+    pub fn into_open_drain_output(&mut self) {
+        self.into_mode(DYN_OPEN_DRAIN_OUTPUT);
+    }
+
+    /// Configure the pin to operate as a push-pull output
+    #[inline]
+    pub fn into_readable_push_pull_output(&mut self) {
+        self.into_mode(DYN_RD_PUSH_PULL_OUTPUT);
+    }
+
+    /// Configure the pin to operate as a push-pull output
+    #[inline]
+    pub fn into_readable_open_drain_output(&mut self) {
+        self.into_mode(DYN_RD_OPEN_DRAIN_OUTPUT);
+    }
+
+    #[inline]
+    pub fn datamask(&self) -> bool {
+        self.regs.datamask()
+    }
+
+    #[inline]
+    pub fn clear_datamask(&mut self) {
+        self.regs.clear_datamask();
+    }
+
+    #[inline]
+    pub fn set_datamask(&mut self) {
+        self.regs.set_datamask();
+    }
+
+    #[inline]
+    pub fn is_high_masked(&self) -> Result<bool, crate::gpio::IsMaskedError> {
+        self.regs.read_pin_masked()
+    }
+
+    #[inline]
+    pub fn is_low_masked(&self) -> Result<bool, crate::gpio::IsMaskedError> {
+        self.regs.read_pin_masked().map(|v| !v)
+    }
+
+    #[inline]
+    pub fn set_high_masked(&mut self) -> Result<(), crate::gpio::IsMaskedError> {
+        self.regs.write_pin_masked(true)
+    }
+
+    #[inline]
+    pub fn set_low_masked(&mut self) -> Result<(), crate::gpio::IsMaskedError> {
+        self.regs.write_pin_masked(false)
+    }
+
+    pub(crate) fn irq_enb(
+        &mut self,
+        irq_cfg: crate::IrqCfg,
+        syscfg: Option<&mut va108xx::Sysconfig>,
+        irqsel: Option<&mut va108xx::Irqsel>,
+    ) {
+        if let Some(syscfg) = syscfg {
+            crate::clock::enable_peripheral_clock(syscfg, crate::clock::PeripheralClocks::Irqsel);
+        }
+        self.regs.enable_irq();
+        if let Some(irqsel) = irqsel {
+            if irq_cfg.route {
+                match self.regs.id().group {
+                    // Set the correct interrupt number in the IRQSEL register
+                    DynGroup::A => {
+                        irqsel
+                            .porta0(self.regs.id().num as usize)
+                            .write(|w| unsafe { w.bits(irq_cfg.irq as u32) });
+                    }
+                    DynGroup::B => {
+                        irqsel
+                            .portb0(self.regs.id().num as usize)
+                            .write(|w| unsafe { w.bits(irq_cfg.irq as u32) });
+                    }
+                }
+            }
+        }
+    }
+
+    /// See p.53 of the programmers guide for more information.
+    /// Possible delays in clock cycles:
+    ///  - Delay 1: 1
+    ///  - Delay 2: 2
+    ///  - Delay 1 + Delay 2: 3
+    #[inline]
+    pub fn delay(self, delay_1: bool, delay_2: bool) -> Result<Self, InvalidPinTypeError> {
+        match self.mode {
+            DynPinMode::Output(_) => {
+                self.regs.delay(delay_1, delay_2);
+                Ok(self)
+            }
+            _ => Err(InvalidPinTypeError(self.mode)),
+        }
+    }
+
+    /// See p.52 of the programmers guide for more information.
+    /// When configured for pulse mode, a given pin will set the non-default state for exactly
+    /// one clock cycle before returning to the configured default state
+    #[inline]
+    pub fn pulse_mode(
+        &mut self,
+        enable: bool,
+        default_state: PinState,
+    ) -> Result<(), InvalidPinTypeError> {
+        match self.mode {
+            DynPinMode::Output(_) => {
+                self.regs.pulse_mode(enable, default_state);
+                Ok(())
+            }
+            _ => Err(InvalidPinTypeError(self.mode)),
+        }
+    }
+
+    /// See p.37 and p.38 of the programmers guide for more information.
+    #[inline]
+    pub fn filter_type(
+        &mut self,
+        filter: FilterType,
+        clksel: FilterClkSel,
+    ) -> Result<(), InvalidPinTypeError> {
+        match self.mode {
+            DynPinMode::Input(_) => {
+                self.regs.filter_type(filter, clksel);
+                Ok(())
+            }
+            _ => Err(InvalidPinTypeError(self.mode)),
+        }
+    }
+
+    #[inline]
+    pub fn interrupt_edge(
+        &mut self,
+        edge_type: InterruptEdge,
+        irq_cfg: IrqCfg,
+        syscfg: Option<&mut pac::Sysconfig>,
+        irqsel: Option<&mut pac::Irqsel>,
+    ) -> Result<(), InvalidPinTypeError> {
+        match self.mode {
+            DynPinMode::Input(_) | DynPinMode::Output(_) => {
+                self.regs.interrupt_edge(edge_type);
+                self.irq_enb(irq_cfg, syscfg, irqsel);
+                Ok(())
+            }
+            _ => Err(InvalidPinTypeError(self.mode)),
+        }
+    }
+
+    #[inline]
+    pub fn interrupt_level(
+        &mut self,
+        level_type: InterruptLevel,
+        irq_cfg: IrqCfg,
+        syscfg: Option<&mut pac::Sysconfig>,
+        irqsel: Option<&mut pac::Irqsel>,
+    ) -> Result<(), InvalidPinTypeError> {
+        match self.mode {
+            DynPinMode::Input(_) | DynPinMode::Output(_) => {
+                self.regs.interrupt_level(level_type);
+                self.irq_enb(irq_cfg, syscfg, irqsel);
+                Ok(())
+            }
+            _ => Err(InvalidPinTypeError(self.mode)),
+        }
+    }
+
+    #[inline]
+    pub fn toggle_with_toggle_reg(&mut self) -> Result<(), InvalidPinTypeError> {
+        match self.mode {
+            DynPinMode::Output(_) => {
+                self.regs.toggle();
+                Ok(())
+            }
+            _ => Err(InvalidPinTypeError(self.mode)),
+        }
+    }
+
+    #[inline]
+    fn _read(&self) -> Result<bool, InvalidPinTypeError> {
+        match self.mode {
+            DynPinMode::Input(_) | DYN_RD_OPEN_DRAIN_OUTPUT | DYN_RD_PUSH_PULL_OUTPUT => {
+                Ok(self.regs.read_pin())
+            }
+            _ => Err(InvalidPinTypeError(self.mode)),
+        }
+    }
+    #[inline]
+    fn _write(&mut self, bit: bool) -> Result<(), InvalidPinTypeError> {
+        match self.mode {
+            DynPinMode::Output(_) => {
+                self.regs.write_pin(bit);
+                Ok(())
+            }
+            _ => Err(InvalidPinTypeError(self.mode)),
+        }
+    }
+
+    #[inline]
+    fn _is_low(&self) -> Result<bool, InvalidPinTypeError> {
+        self._read().map(|v| !v)
+    }
+    #[inline]
+    fn _is_high(&self) -> Result<bool, InvalidPinTypeError> {
+        self._read()
+    }
+    #[inline]
+    fn _set_low(&mut self) -> Result<(), InvalidPinTypeError> {
+        self._write(false)
+    }
+    #[inline]
+    fn _set_high(&mut self) -> Result<(), InvalidPinTypeError> {
+        self._write(true)
+    }
+
+    /// Try to recreate a type-level [`Pin`] from a value-level [`DynPin`]
+    ///
+    /// There is no way for the compiler to know if the conversion will be
+    /// successful at compile-time. We must verify the conversion at run-time
+    /// or refuse to perform it.
+    #[inline]
+    pub fn upgrade<I: PinId, M: PinMode>(self) -> Result<Pin<I, M>, InvalidPinTypeError> {
+        if self.regs.id == I::DYN && self.mode == M::DYN {
+            // The `DynPin` is consumed, so it is safe to replace it with the
+            // corresponding `Pin`
+            return Ok(unsafe { Pin::new() });
+        }
+        Err(InvalidPinTypeError(self.mode))
+    }
+}
+
+//==================================================================================================
+//  Convert between Pin and DynPin
+//==================================================================================================
+
+impl<I: PinId, M: PinMode> From<Pin<I, M>> for DynPin {
+    /// Erase the type-level information in a [`Pin`] and return a value-level
+    /// [`DynPin`]
+    #[inline]
+    fn from(pin: Pin<I, M>) -> Self {
+        pin.downgrade()
+    }
+}
+
+impl<I: PinId, M: PinMode> TryFrom<DynPin> for Pin<I, M> {
+    type Error = InvalidPinTypeError;
+
+    /// Try to recreate a type-level [`Pin`] from a value-level [`DynPin`]
+    ///
+    /// There is no way for the compiler to know if the conversion will be
+    /// successful at compile-time. We must verify the conversion at run-time
+    /// or refuse to perform it.
+    #[inline]
+    fn try_from(pin: DynPin) -> Result<Self, Self::Error> {
+        pin.upgrade()
+    }
+}
+
+//==================================================================================================
+// Embedded HAL traits
+//==================================================================================================
+
+impl embedded_hal::digital::ErrorType for DynPin {
+    type Error = InvalidPinTypeError;
+}
+
+impl embedded_hal::digital::OutputPin for DynPin {
+    #[inline]
+    fn set_high(&mut self) -> Result<(), Self::Error> {
+        self._set_high()
+    }
+    #[inline]
+    fn set_low(&mut self) -> Result<(), Self::Error> {
+        self._set_low()
+    }
+}
+
+impl embedded_hal::digital::InputPin for DynPin {
+    #[inline]
+    fn is_high(&mut self) -> Result<bool, Self::Error> {
+        self._is_high()
+    }
+    #[inline]
+    fn is_low(&mut self) -> Result<bool, Self::Error> {
+        self._is_low()
+    }
+}
+
+impl embedded_hal::digital::StatefulOutputPin for DynPin {
+    #[inline]
+    fn is_set_high(&mut self) -> Result<bool, Self::Error> {
+        self._is_high()
+    }
+
+    #[inline]
+    fn is_set_low(&mut self) -> Result<bool, Self::Error> {
+        self._is_low()
+    }
+}

va108xx-hal/src/gpio/mod.rs

@@ -1,20 +1,36 @@
-//! GPIO support module.
+//! # API for the GPIO peripheral
 //!
-//! Contains abstractions to use the pins provided by the [crate::pins] module as GPIO or
+//! The implementation of this GPIO module is heavily based on the
-//! IO peripheral pins.
+//! [ATSAMD HAL implementation](https://docs.rs/atsamd-hal/latest/atsamd_hal/gpio/index.html).
 //!
-//! The core data structures provided for this are the
+//! This API provides two different submodules, [pin] and [dynpin],
+//! representing two different ways to handle GPIO pins. The default, [pin],
+//! is a type-level API that tracks the state of each pin at compile-time. The
+//! alternative, [dynpin] is a type-erased, value-level API that tracks the
+//! state of each pin at run-time.
 //!
-//! - [Output] for push-pull output pins.
+//! The type-level API is strongly preferred. By representing the state of each
-//! - [Input] for input pins.
+//! pin within the type system, the compiler can detect logic errors at
-//! - [Flex] for pins with flexible configuration requirements.
+//! compile-time. Furthermore, the type-level API has absolutely zero run-time
-//! - [IoPeriphPin] for IO peripheral pins.
+//! cost.
 //!
-//! The [crate::pins] module exposes singletons to access the [Pin]s required by this module
+//! If needed, [dynpin] can be used to erase the type-level differences
-//! in a type-safe way.
+//! between pins. However, by doing so, pins must now be tracked at run-time,
+//! and each pin has a non-zero memory footprint.
 //!
 //! ## Examples
 //!
 //! - [Blinky example](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/examples/simple/examples/blinky.rs)
-//! - [Async GPIO example](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/examples/embassy/src/bin/async-gpio.rs)
+
-pub use vorago_shared_periphs::gpio::*;
+#[derive(Debug, PartialEq, Eq, thiserror::Error)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[error("The pin is masked")]
+pub struct IsMaskedError;
+
+pub mod dynpin;
+pub use dynpin::*;
+
+pub mod pin;
+pub use pin::*;
+
+mod reg;

va108xx-hal/src/gpio/pin.rs

@@ -0,0 +1,865 @@
+//! # Type-level module for GPIO pins
+//!
+//! This documentation is strongly based on the
+//! [atsamd documentation](https://docs.rs/atsamd-hal/latest/atsamd_hal/gpio/pin/index.html).
+//!
+//! This module provides a type-level API for GPIO pins. It uses the type system
+//! to track the state of pins at compile-time. Representing GPIO pins in this
+//! manner incurs no run-time overhead. Each [`Pin`] struct is zero-sized, so
+//! there is no data to copy around. Instead, real code is generated as a side
+//! effect of type transformations, and the resulting assembly is nearly
+//! identical to the equivalent, hand-written C.
+//!
+//! To track the state of pins at compile-time, this module uses traits to
+//! represent [type classes] and types as instances of those type classes. For
+//! example, the trait [`InputConfig`] acts as a [type-level enum] of the
+//! available input configurations, and the types [`Floating`], [`PullDown`] and
+//! [`PullUp`] are its type-level variants.
+//!
+//! Type-level [`Pin`]s are parameterized by two type-level enums, [`PinId`] and
+//! [`PinMode`].
+//!
+//! ```
+//! pub struct Pin<I, M>
+//! where
+//!     I: PinId,
+//!     M: PinMode,
+//! {
+//!     // ...
+//! }
+//! ```
+//!
+//! A [PinId] identifies a pin by it's group (A or B) and pin number. Each
+//! [PinId] instance is named according to its datasheet identifier, e.g.
+//! [PA2].
+//!
+//! A [PinMode] represents the various pin modes. The available [PinMode]
+//! variants are [`Input`], [`Output`] and [`Alternate`], each with its own
+//! corresponding configurations.
+//!
+//! It is not possible for users to create new instances of a [`Pin`]. Singleton
+//! instances of each pin are made available to users through the PinsX
+//! struct.
+//!
+//! Example for the pins of PORT A:
+//!
+//! To create the [PinsA] struct, users must supply the PAC
+//! [Port](crate::pac::Porta) peripheral. The [PinsA] struct takes
+//! ownership of the [Porta] and provides the corresponding pins. Each [`Pin`]
+//! within the [PinsA] struct can be moved out and used individually.
+//!
+//!
+//! ```
+//! let mut peripherals = Peripherals::take().unwrap();
+//! let pinsa = PinsA::new(peripherals.PORT);
+//! ```
+//!
+//! Pins can be converted between modes using several different methods.
+//!
+//! ```no_run
+//! // Use one of the literal function names
+//! let pa0 = pinsa.pa0.into_floating_input();
+//! // Use a generic method and one of the `PinMode` variant types
+//! let pa0 = pinsa.pa0.into_mode::<FloatingInput>();
+//! // Specify the target type and use `From`/`Into`
+//! let pa0: Pin<PA0, FloatingInput> = pinsa.pa27.into();
+//! ```
+//!
+//! # Embedded HAL traits
+//!
+//! This module implements all of the embedded HAL GPIO traits for each [`Pin`]
+//! in the corresponding [`PinMode`]s, namely: [`InputPin`], [`OutputPin`],
+//! and [`StatefulOutputPin`].
+use super::dynpin::{DynAlternate, DynGroup, DynInput, DynOutput, DynPinId, DynPinMode};
+use super::reg::RegisterInterface;
+use super::DynPin;
+use crate::{
+    pac::{Irqsel, Porta, Portb, Sysconfig},
+    typelevel::Sealed,
+    IrqCfg,
+};
+use core::convert::Infallible;
+use core::marker::PhantomData;
+use core::mem::transmute;
+use embedded_hal::digital::{InputPin, OutputPin, StatefulOutputPin};
+use paste::paste;
+
+//==================================================================================================
+//  Errors and Definitions
+//==================================================================================================
+
+#[derive(Debug, PartialEq, Eq)]
+pub enum InterruptEdge {
+    HighToLow,
+    LowToHigh,
+    BothEdges,
+}
+
+#[derive(Debug, PartialEq, Eq)]
+pub enum InterruptLevel {
+    Low = 0,
+    High = 1,
+}
+
+#[derive(Debug, PartialEq, Eq)]
+pub enum PinState {
+    Low = 0,
+    High = 1,
+}
+
+//==================================================================================================
+// Input configuration
+//==================================================================================================
+
+/// Type-level enum for input configurations
+///
+/// The valid options are [Floating], [PullDown] and [PullUp].
+pub trait InputConfig: Sealed {
+    /// Corresponding [DynInput]
+    const DYN: DynInput;
+}
+
+pub enum Floating {}
+pub enum PullDown {}
+pub enum PullUp {}
+
+impl InputConfig for Floating {
+    const DYN: DynInput = DynInput::Floating;
+}
+impl InputConfig for PullDown {
+    const DYN: DynInput = DynInput::PullDown;
+}
+impl InputConfig for PullUp {
+    const DYN: DynInput = DynInput::PullUp;
+}
+
+impl Sealed for Floating {}
+impl Sealed for PullDown {}
+impl Sealed for PullUp {}
+
+/// Type-level variant of [`PinMode`] for floating input mode
+pub type InputFloating = Input<Floating>;
+/// Type-level variant of [`PinMode`] for pull-down input mode
+pub type InputPullDown = Input<PullDown>;
+/// Type-level variant of [`PinMode`] for pull-up input mode
+pub type InputPullUp = Input<PullUp>;
+
+/// Type-level variant of [`PinMode`] for input modes
+///
+/// Type `C` is one of three input configurations: [`Floating`], [`PullDown`] or
+/// [`PullUp`]
+pub struct Input<C: InputConfig> {
+    cfg: PhantomData<C>,
+}
+
+impl<C: InputConfig> Sealed for Input<C> {}
+
+#[derive(Debug, PartialEq, Eq)]
+pub enum FilterType {
+    SystemClock = 0,
+    DirectInputWithSynchronization = 1,
+    FilterOneClockCycle = 2,
+    FilterTwoClockCycles = 3,
+    FilterThreeClockCycles = 4,
+    FilterFourClockCycles = 5,
+}
+
+pub use crate::clock::FilterClkSel;
+
+//==================================================================================================
+// Output configuration
+//==================================================================================================
+
+pub trait OutputConfig: Sealed {
+    const DYN: DynOutput;
+}
+
+pub trait ReadableOutput: Sealed {}
+
+/// Type-level variant of [`OutputConfig`] for a push-pull configuration
+pub enum PushPull {}
+/// Type-level variant of [`OutputConfig`] for an open drain configuration
+pub enum OpenDrain {}
+
+/// Type-level variant of [`OutputConfig`] for a readable push-pull configuration
+pub enum ReadablePushPull {}
+/// Type-level variant of [`OutputConfig`] for a readable open-drain configuration
+pub enum ReadableOpenDrain {}
+
+impl Sealed for PushPull {}
+impl Sealed for OpenDrain {}
+impl Sealed for ReadableOpenDrain {}
+impl Sealed for ReadablePushPull {}
+impl ReadableOutput for ReadableOpenDrain {}
+impl ReadableOutput for ReadablePushPull {}
+
+impl OutputConfig for PushPull {
+    const DYN: DynOutput = DynOutput::PushPull;
+}
+impl OutputConfig for OpenDrain {
+    const DYN: DynOutput = DynOutput::OpenDrain;
+}
+impl OutputConfig for ReadablePushPull {
+    const DYN: DynOutput = DynOutput::ReadablePushPull;
+}
+impl OutputConfig for ReadableOpenDrain {
+    const DYN: DynOutput = DynOutput::ReadableOpenDrain;
+}
+
+/// Type-level variant of [`PinMode`] for output modes
+///
+/// Type `C` is one of four output configurations: [`PushPull`], [`OpenDrain`] or
+/// their respective readable versions
+pub struct Output<C: OutputConfig> {
+    cfg: PhantomData<C>,
+}
+
+impl<C: OutputConfig> Sealed for Output<C> {}
+
+/// Type-level variant of [`PinMode`] for push-pull output mode
+pub type PushPullOutput = Output<PushPull>;
+/// Type-level variant of [`PinMode`] for open drain output mode
+pub type OutputOpenDrain = Output<OpenDrain>;
+
+pub type OutputReadablePushPull = Output<ReadablePushPull>;
+pub type OutputReadableOpenDrain = Output<ReadableOpenDrain>;
+
+//==================================================================================================
+//  Alternate configurations
+//==================================================================================================
+
+/// Type-level enum for alternate peripheral function configurations
+pub trait AlternateConfig: Sealed {
+    const DYN: DynAlternate;
+}
+
+pub enum Funsel1 {}
+pub enum Funsel2 {}
+pub enum Funsel3 {}
+
+impl AlternateConfig for Funsel1 {
+    const DYN: DynAlternate = DynAlternate::Sel1;
+}
+impl AlternateConfig for Funsel2 {
+    const DYN: DynAlternate = DynAlternate::Sel2;
+}
+impl AlternateConfig for Funsel3 {
+    const DYN: DynAlternate = DynAlternate::Sel3;
+}
+
+impl Sealed for Funsel1 {}
+impl Sealed for Funsel2 {}
+impl Sealed for Funsel3 {}
+
+/// Type-level variant of [`PinMode`] for alternate peripheral functions
+///
+/// Type `C` is an [`AlternateConfig`]
+pub struct Alternate<C: AlternateConfig> {
+    cfg: PhantomData<C>,
+}
+
+impl<C: AlternateConfig> Sealed for Alternate<C> {}
+
+pub type AltFunc1 = Alternate<Funsel1>;
+pub type AltFunc2 = Alternate<Funsel2>;
+pub type AltFunc3 = Alternate<Funsel3>;
+
+/// Type alias for the [`PinMode`] at reset
+pub type Reset = InputFloating;
+
+//==================================================================================================
+//  Pin modes
+//==================================================================================================
+
+/// Type-level enum representing pin modes
+///
+/// The valid options are [Input], [Output] and [Alternate].
+pub trait PinMode: Sealed {
+    /// Corresponding [DynPinMode]
+    const DYN: DynPinMode;
+}
+
+impl<C: InputConfig> PinMode for Input<C> {
+    const DYN: DynPinMode = DynPinMode::Input(C::DYN);
+}
+impl<C: OutputConfig> PinMode for Output<C> {
+    const DYN: DynPinMode = DynPinMode::Output(C::DYN);
+}
+impl<C: AlternateConfig> PinMode for Alternate<C> {
+    const DYN: DynPinMode = DynPinMode::Alternate(C::DYN);
+}
+
+//==================================================================================================
+//  Pin IDs
+//==================================================================================================
+
+/// Type-level enum for pin IDs
+pub trait PinId: Sealed {
+    /// Corresponding [DynPinId]
+    const DYN: DynPinId;
+}
+
+macro_rules! pin_id {
+    ($Group:ident, $Id:ident, $NUM:literal) => {
+        // Need paste macro to use ident in doc attribute
+        paste! {
+            #[doc = "Pin ID representing pin " $Id]
+            pub enum $Id {}
+            impl Sealed for $Id {}
+            impl PinId for $Id {
+                const DYN: DynPinId = DynPinId {
+                    group: DynGroup::$Group,
+                    num: $NUM,
+                };
+            }
+        }
+    };
+}
+
+//==================================================================================================
+//  Pin
+//==================================================================================================
+
+/// A type-level GPIO pin, parameterized by [PinId] and [PinMode] types
+pub struct Pin<I: PinId, M: PinMode> {
+    inner: DynPin,
+    phantom: PhantomData<(I, M)>,
+}
+
+impl<I: PinId, M: PinMode> Pin<I, M> {
+    /// Create a new [Pin]
+    ///
+    /// # Safety
+    ///
+    /// Each [Pin] must be a singleton. For a given [PinId], there must be
+    /// at most one corresponding [Pin] in existence at any given time.
+    /// Violating this requirement is `unsafe`.
+    #[inline]
+    pub(crate) unsafe fn new() -> Pin<I, M> {
+        Pin {
+            inner: DynPin::new(I::DYN, M::DYN),
+            phantom: PhantomData,
+        }
+    }
+
+    /// Convert the pin to the requested [`PinMode`]
+    #[inline]
+    pub fn into_mode<N: PinMode>(mut self) -> Pin<I, N> {
+        // Only modify registers if we are actually changing pin mode
+        // This check should compile away
+        if N::DYN != M::DYN {
+            self.inner.regs.change_mode(N::DYN);
+        }
+        // Safe because we drop the existing Pin
+        unsafe { Pin::new() }
+    }
+
+    /// Configure the pin for function select 1. See Programmer Guide p.40 for the function table
+    #[inline]
+    pub fn into_funsel_1(self) -> Pin<I, AltFunc1> {
+        self.into_mode()
+    }
+
+    /// Configure the pin for function select 2. See Programmer Guide p.40 for the function table
+    #[inline]
+    pub fn into_funsel_2(self) -> Pin<I, AltFunc2> {
+        self.into_mode()
+    }
+
+    /// Configure the pin for function select 3. See Programmer Guide p.40 for the function table
+    #[inline]
+    pub fn into_funsel_3(self) -> Pin<I, AltFunc3> {
+        self.into_mode()
+    }
+
+    /// Configure the pin to operate as a floating input
+    #[inline]
+    pub fn into_floating_input(self) -> Pin<I, InputFloating> {
+        self.into_mode()
+    }
+
+    /// Configure the pin to operate as a pulled down input
+    #[inline]
+    pub fn into_pull_down_input(self) -> Pin<I, InputPullDown> {
+        self.into_mode()
+    }
+
+    /// Configure the pin to operate as a pulled up input
+    #[inline]
+    pub fn into_pull_up_input(self) -> Pin<I, InputPullUp> {
+        self.into_mode()
+    }
+
+    /// Configure the pin to operate as a push-pull output
+    #[inline]
+    pub fn into_push_pull_output(self) -> Pin<I, PushPullOutput> {
+        self.into_mode()
+    }
+
+    /// Configure the pin to operate as a readable push-pull output
+    #[inline]
+    pub fn into_readable_push_pull_output(self) -> Pin<I, OutputReadablePushPull> {
+        self.into_mode()
+    }
+
+    /// Configure the pin to operate as a readable open-drain output
+    #[inline]
+    pub fn into_readable_open_drain_output(self) -> Pin<I, OutputReadableOpenDrain> {
+        self.into_mode()
+    }
+
+    #[inline]
+    pub fn datamask(&self) -> bool {
+        self.inner.datamask()
+    }
+
+    #[inline]
+    pub fn clear_datamask(&mut self) {
+        self.inner.clear_datamask()
+    }
+
+    #[inline]
+    pub fn set_datamask(&mut self) {
+        self.inner.set_datamask()
+    }
+
+    #[inline]
+    pub fn is_high_masked(&self) -> Result<bool, crate::gpio::IsMaskedError> {
+        self.inner.is_high_masked()
+    }
+
+    #[inline]
+    pub fn is_low_masked(&self) -> Result<bool, crate::gpio::IsMaskedError> {
+        self.inner.is_low_masked()
+    }
+
+    #[inline]
+    pub fn set_high_masked(&mut self) -> Result<(), crate::gpio::IsMaskedError> {
+        self.inner.set_high_masked()
+    }
+
+    #[inline]
+    pub fn set_low_masked(&mut self) -> Result<(), crate::gpio::IsMaskedError> {
+        self.inner.set_low_masked()
+    }
+
+    #[inline]
+    pub fn downgrade(self) -> DynPin {
+        self.inner
+    }
+
+    fn irq_enb(
+        &mut self,
+        irq_cfg: crate::IrqCfg,
+        syscfg: Option<&mut va108xx::Sysconfig>,
+        irqsel: Option<&mut va108xx::Irqsel>,
+    ) {
+        self.inner.irq_enb(irq_cfg, syscfg, irqsel);
+    }
+
+    #[inline]
+    pub(crate) fn _set_high(&mut self) {
+        self.inner.regs.write_pin(true)
+    }
+
+    #[inline]
+    pub(crate) fn _set_low(&mut self) {
+        self.inner.regs.write_pin(false)
+    }
+
+    #[inline]
+    pub(crate) fn _toggle_with_toggle_reg(&mut self) {
+        self.inner.regs.toggle();
+    }
+
+    #[inline]
+    pub(crate) fn _is_low(&self) -> bool {
+        !self.inner.regs.read_pin()
+    }
+
+    #[inline]
+    pub(crate) fn _is_high(&self) -> bool {
+        self.inner.regs.read_pin()
+    }
+}
+
+//==============================================================================
+//  AnyPin
+//==============================================================================
+
+/// Type class for [`Pin`] types
+///
+/// This trait uses the [`AnyKind`] trait pattern to create a [type class] for
+/// [`Pin`] types. See the `AnyKind` documentation for more details on the
+/// pattern.
+///
+/// ## `v1` Compatibility
+///
+/// Normally, this trait would use `Is<Type = SpecificPin<Self>>` as a super
+/// trait. But doing so would restrict implementations to only the `v2` `Pin`
+/// type in this module. To aid in backwards compatibility, we want to implement
+/// `AnyPin` for the `v1` `Pin` type as well. This is possible for a few
+/// reasons. First, both structs are zero-sized, so there is no meaningful
+/// memory layout to begin with. And even if there were, the `v1` `Pin` type is
+/// a newtype wrapper around a `v2` `Pin`, and single-field structs are
+/// guaranteed to have the same layout as the field, even for `repr(Rust)`.
+///
+/// [`AnyKind`]: crate::typelevel#anykind-trait-pattern
+/// [type class]: crate::typelevel#type-classes
+pub trait AnyPin
+where
+    Self: Sealed,
+    Self: From<SpecificPin<Self>>,
+    Self: Into<SpecificPin<Self>>,
+    Self: AsRef<SpecificPin<Self>>,
+    Self: AsMut<SpecificPin<Self>>,
+{
+    /// [`PinId`] of the corresponding [`Pin`]
+    type Id: PinId;
+    /// [`PinMode`] of the corresponding [`Pin`]
+    type Mode: PinMode;
+}
+
+impl<I, M> Sealed for Pin<I, M>
+where
+    I: PinId,
+    M: PinMode,
+{
+}
+
+impl<I, M> AnyPin for Pin<I, M>
+where
+    I: PinId,
+    M: PinMode,
+{
+    type Id = I;
+    type Mode = M;
+}
+
+/// Type alias to recover the specific [`Pin`] type from an implementation of
+/// [`AnyPin`]
+///
+/// See the [`AnyKind`] documentation for more details on the pattern.
+///
+/// [`AnyKind`]: crate::typelevel#anykind-trait-pattern
+pub type SpecificPin<P> = Pin<<P as AnyPin>::Id, <P as AnyPin>::Mode>;
+
+impl<P: AnyPin> AsRef<P> for SpecificPin<P> {
+    #[inline]
+    fn as_ref(&self) -> &P {
+        // SAFETY: This is guaranteed to be safe, because P == SpecificPin<P>
+        // Transmuting between `v1` and `v2` `Pin` types is also safe, because
+        // both are zero-sized, and single-field, newtype structs are guaranteed
+        // to have the same layout as the field anyway, even for repr(Rust).
+        unsafe { transmute(self) }
+    }
+}
+
+impl<P: AnyPin> AsMut<P> for SpecificPin<P> {
+    #[inline]
+    fn as_mut(&mut self) -> &mut P {
+        // SAFETY: This is guaranteed to be safe, because P == SpecificPin<P>
+        // Transmuting between `v1` and `v2` `Pin` types is also safe, because
+        // both are zero-sized, and single-field, newtype structs are guaranteed
+        // to have the same layout as the field anyway, even for repr(Rust).
+        unsafe { transmute(self) }
+    }
+}
+
+//==================================================================================================
+//  Additional functionality
+//==================================================================================================
+
+impl<I: PinId, C: InputConfig> Pin<I, Input<C>> {
+    pub fn interrupt_edge(
+        &mut self,
+        edge_type: InterruptEdge,
+        irq_cfg: IrqCfg,
+        syscfg: Option<&mut Sysconfig>,
+        irqsel: Option<&mut Irqsel>,
+    ) {
+        self.inner.regs.interrupt_edge(edge_type);
+        self.irq_enb(irq_cfg, syscfg, irqsel);
+    }
+
+    pub fn interrupt_level(
+        &mut self,
+        level_type: InterruptLevel,
+        irq_cfg: IrqCfg,
+        syscfg: Option<&mut Sysconfig>,
+        irqsel: Option<&mut Irqsel>,
+    ) {
+        self.inner.regs.interrupt_level(level_type);
+        self.irq_enb(irq_cfg, syscfg, irqsel);
+    }
+}
+
+impl<I: PinId, C: OutputConfig> Pin<I, Output<C>> {
+    /// See p.53 of the programmers guide for more information.
+    /// Possible delays in clock cycles:
+    ///  - Delay 1: 1
+    ///  - Delay 2: 2
+    ///  - Delay 1 + Delay 2: 3
+    #[inline]
+    pub fn delay(self, delay_1: bool, delay_2: bool) -> Self {
+        self.inner.regs.delay(delay_1, delay_2);
+        self
+    }
+
+    #[inline]
+    pub fn toggle_with_toggle_reg(&mut self) {
+        self._toggle_with_toggle_reg()
+    }
+
+    /// See p.52 of the programmers guide for more information.
+    /// When configured for pulse mode, a given pin will set the non-default state for exactly
+    /// one clock cycle before returning to the configured default state
+    pub fn pulse_mode(&mut self, enable: bool, default_state: PinState) {
+        self.inner.regs.pulse_mode(enable, default_state);
+    }
+
+    pub fn interrupt_edge(
+        &mut self,
+        edge_type: InterruptEdge,
+        irq_cfg: IrqCfg,
+        syscfg: Option<&mut Sysconfig>,
+        irqsel: Option<&mut Irqsel>,
+    ) {
+        self.inner.regs.interrupt_edge(edge_type);
+        self.irq_enb(irq_cfg, syscfg, irqsel);
+    }
+
+    pub fn interrupt_level(
+        &mut self,
+        level_type: InterruptLevel,
+        irq_cfg: IrqCfg,
+        syscfg: Option<&mut Sysconfig>,
+        irqsel: Option<&mut Irqsel>,
+    ) {
+        self.inner.regs.interrupt_level(level_type);
+        self.irq_enb(irq_cfg, syscfg, irqsel);
+    }
+}
+
+impl<I: PinId, C: InputConfig> Pin<I, Input<C>> {
+    /// See p.37 and p.38 of the programmers guide for more information.
+    #[inline]
+    pub fn filter_type(&mut self, filter: FilterType, clksel: FilterClkSel) {
+        self.inner.regs.filter_type(filter, clksel);
+    }
+}
+
+//==================================================================================================
+//  Embedded HAL traits
+//==================================================================================================
+
+impl<I, M> embedded_hal::digital::ErrorType for Pin<I, M>
+where
+    I: PinId,
+    M: PinMode,
+{
+    type Error = Infallible;
+}
+
+impl<I: PinId, C: OutputConfig> OutputPin for Pin<I, Output<C>> {
+    #[inline]
+    fn set_high(&mut self) -> Result<(), Self::Error> {
+        self._set_high();
+        Ok(())
+    }
+
+    #[inline]
+    fn set_low(&mut self) -> Result<(), Self::Error> {
+        self._set_low();
+        Ok(())
+    }
+}
+
+impl<I, C> InputPin for Pin<I, Input<C>>
+where
+    I: PinId,
+    C: InputConfig,
+{
+    #[inline]
+    fn is_high(&mut self) -> Result<bool, Self::Error> {
+        Ok(self._is_high())
+    }
+    #[inline]
+    fn is_low(&mut self) -> Result<bool, Self::Error> {
+        Ok(self._is_low())
+    }
+}
+
+impl<I, C> StatefulOutputPin for Pin<I, Output<C>>
+where
+    I: PinId,
+    C: OutputConfig + ReadableOutput,
+{
+    #[inline]
+    fn is_set_high(&mut self) -> Result<bool, Self::Error> {
+        Ok(self._is_high())
+    }
+    #[inline]
+    fn is_set_low(&mut self) -> Result<bool, Self::Error> {
+        Ok(self._is_low())
+    }
+}
+
+impl<I, C> InputPin for Pin<I, Output<C>>
+where
+    I: PinId,
+    C: OutputConfig + ReadableOutput,
+{
+    #[inline]
+    fn is_high(&mut self) -> Result<bool, Self::Error> {
+        Ok(self._is_high())
+    }
+
+    #[inline]
+    fn is_low(&mut self) -> Result<bool, Self::Error> {
+        Ok(self._is_low())
+    }
+}
+
+//==================================================================================================
+//  Pin definitions
+//==================================================================================================
+
+macro_rules! pins {
+    (
+        $Port:ident, $PinsName:ident, $($Id:ident,)+,
+    ) => {
+        paste!(
+            /// Collection of all the individual [`Pin`]s for a given port (PORTA or PORTB)
+            pub struct $PinsName {
+                iocfg: Option<va108xx::Ioconfig>,
+                port: $Port,
+                $(
+                    #[doc = "Pin " $Id]
+                    pub [<$Id:lower>]: Pin<$Id, Reset>,
+                )+
+            }
+
+            impl $PinsName {
+                /// Create a new struct containing all the Pins. Passing the IOCONFIG peripheral
+                /// is optional because it might be required to create pin definitions for both
+                /// ports.
+                #[inline]
+                pub fn new(
+                    syscfg: &mut va108xx::Sysconfig,
+                    iocfg: Option<va108xx::Ioconfig>,
+                    port: $Port
+                ) -> $PinsName {
+                    syscfg.peripheral_clk_enable().modify(|_, w| {
+                        w.[<$Port:lower>]().set_bit();
+                        w.gpio().set_bit();
+                        w.ioconfig().set_bit()
+                    });
+                    $PinsName {
+                        iocfg,
+                        port,
+                        // Safe because we only create one `Pin` per `PinId`
+                        $(
+                            [<$Id:lower>]: unsafe { Pin::new() },
+                        )+
+                    }
+                }
+
+                /// Get the peripheral ID
+                /// Safety: Read-only register
+                pub fn get_perid() -> u32 {
+                    let port = unsafe { &(*$Port::ptr()) };
+                    port.perid().read().bits()
+                }
+
+                /// Consumes the Pins struct and returns the port definitions
+                pub fn release(self) -> (Option<va108xx::Ioconfig>, $Port) {
+                    (self.iocfg, self.port)
+                }
+            }
+        );
+    }
+}
+
+macro_rules! declare_pins {
+    (
+        $Group:ident, $PinsName:ident, $Port:ident, [$(($Id:ident, $NUM:literal),)+]
+    ) => {
+        pins!($Port, $PinsName, $($Id,)+,);
+        $(
+            pin_id!($Group, $Id, $NUM);
+        )+
+    }
+}
+
+declare_pins!(
+    A,
+    PinsA,
+    Porta,
+    [
+        (PA0, 0),
+        (PA1, 1),
+        (PA2, 2),
+        (PA3, 3),
+        (PA4, 4),
+        (PA5, 5),
+        (PA6, 6),
+        (PA7, 7),
+        (PA8, 8),
+        (PA9, 9),
+        (PA10, 10),
+        (PA11, 11),
+        (PA12, 12),
+        (PA13, 13),
+        (PA14, 14),
+        (PA15, 15),
+        (PA16, 16),
+        (PA17, 17),
+        (PA18, 18),
+        (PA19, 19),
+        (PA20, 20),
+        (PA21, 21),
+        (PA22, 22),
+        (PA23, 23),
+        (PA24, 24),
+        (PA25, 25),
+        (PA26, 26),
+        (PA27, 27),
+        (PA28, 28),
+        (PA29, 29),
+        (PA30, 30),
+        (PA31, 31),
+    ]
+);
+
+declare_pins!(
+    B,
+    PinsB,
+    Portb,
+    [
+        (PB0, 0),
+        (PB1, 1),
+        (PB2, 2),
+        (PB3, 3),
+        (PB4, 4),
+        (PB5, 5),
+        (PB6, 6),
+        (PB7, 7),
+        (PB8, 8),
+        (PB9, 9),
+        (PB10, 10),
+        (PB11, 11),
+        (PB12, 12),
+        (PB13, 13),
+        (PB14, 14),
+        (PB15, 15),
+        (PB16, 16),
+        (PB17, 17),
+        (PB18, 18),
+        (PB19, 19),
+        (PB20, 20),
+        (PB21, 21),
+        (PB22, 22),
+        (PB23, 23),
+    ]
+);

va108xx-hal/src/gpio/reg.rs

@@ -0,0 +1,382 @@
+use super::dynpin::{self, DynGroup, DynPinId, DynPinMode};
+use super::pin::{FilterType, InterruptEdge, InterruptLevel, PinState};
+use super::IsMaskedError;
+use crate::clock::FilterClkSel;
+use va108xx::{ioconfig, porta};
+
+/// Type definition to avoid confusion: These register blocks are identical
+type PortRegisterBlock = porta::RegisterBlock;
+
+//==================================================================================================
+//  ModeFields
+//==================================================================================================
+
+/// Collect all fields needed to set the [`PinMode`](super::PinMode)
+#[derive(Default)]
+struct ModeFields {
+    dir: bool,
+    opendrn: bool,
+    pull_en: bool,
+    /// true for pullup, false for pulldown
+    pull_dir: bool,
+    funsel: u8,
+    enb_input: bool,
+}
+
+impl From<DynPinMode> for ModeFields {
+    #[inline]
+    fn from(mode: DynPinMode) -> Self {
+        let mut fields = Self::default();
+        use DynPinMode::*;
+        match mode {
+            Input(config) => {
+                use dynpin::DynInput::*;
+                fields.dir = false;
+                match config {
+                    Floating => (),
+                    PullUp => {
+                        fields.pull_en = true;
+                        fields.pull_dir = true;
+                    }
+                    PullDown => {
+                        fields.pull_en = true;
+                    }
+                }
+            }
+            Output(config) => {
+                use dynpin::DynOutput::*;
+                fields.dir = true;
+                match config {
+                    PushPull => (),
+                    OpenDrain => {
+                        fields.opendrn = true;
+                    }
+                    ReadableOpenDrain => {
+                        fields.enb_input = true;
+                        fields.opendrn = true;
+                    }
+                    ReadablePushPull => {
+                        fields.enb_input = true;
+                    }
+                }
+            }
+            Alternate(config) => {
+                fields.funsel = config as u8;
+            }
+        }
+        fields
+    }
+}
+
+//==================================================================================================
+// Register Interface
+//==================================================================================================
+
+pub type PortReg = ioconfig::Porta;
+/*
+pub type IocfgPort = ioconfig::Porta;
+#[repr(C)]
+pub(super) struct IocfgPortGroup {
+    port: [IocfgPort; 32],
+}
+*/
+
+/// Provide a safe register interface for pin objects
+///
+/// [`PORTA`] and [`PORTB`], like every PAC `struct`, is [`Send`] but not [`Sync`], because it
+/// points to a `RegisterBlock` of `VolatileCell`s. Unfortunately, such an
+/// interface is quite restrictive. Instead, it would be ideal if we could split
+/// the [`PORT`] into independent pins that are both [`Send`] and [`Sync`].
+///
+/// [`PORT`] is a single, zero-sized marker `struct` that provides access to
+/// every [`PORT`] register. Instead, we would like to create zero-sized marker
+/// `struct`s for every pin, where each pin is only allowed to control its own
+/// registers. Furthermore, each pin `struct` should be a singleton, so that
+/// exclusive access to the `struct` also guarantees exclusive access to the
+/// corresponding registers. Finally, the pin `struct`s should not have any
+/// interior mutability. Together, these requirements would allow the pin
+/// `struct`s to be both [`Send`] and [`Sync`].
+///
+/// This trait creates a safe API for accomplishing these goals. Implementers
+/// supply a pin ID through the [`id`] function. The remaining functions provide
+/// a safe API for accessing the registers associated with that pin ID. Any
+/// modification of the registers requires `&mut self`, which destroys interior
+/// mutability.
+///
+/// # Safety
+///
+/// Users should only implement the [`id`] function. No default function
+/// implementations should be overridden. The implementing type must also have
+/// "control" over the corresponding pin ID, i.e. it must guarantee that a each
+/// pin ID is a singleton.
+///
+/// [`id`]: Self::id
+pub(super) unsafe trait RegisterInterface {
+    /// Provide a [`DynPinId`] identifying the set of registers controlled by
+    /// this type.
+    fn id(&self) -> DynPinId;
+
+    const PORTA: *const PortRegisterBlock = va108xx::Porta::ptr();
+    const PORTB: *const PortRegisterBlock = va108xx::Portb::ptr();
+
+    /// Change the pin mode
+    #[inline]
+    fn change_mode(&mut self, mode: DynPinMode) {
+        let ModeFields {
+            dir,
+            funsel,
+            opendrn,
+            pull_dir,
+            pull_en,
+            enb_input,
+        } = mode.into();
+        let (portreg, iocfg) = (self.port_reg(), self.iocfg_port());
+        iocfg.write(|w| {
+            w.opendrn().bit(opendrn);
+            w.pen().bit(pull_en);
+            w.plevel().bit(pull_dir);
+            w.iewo().bit(enb_input);
+            unsafe { w.funsel().bits(funsel) }
+        });
+        let mask = self.mask_32();
+        unsafe {
+            if dir {
+                portreg.dir().modify(|r, w| w.bits(r.bits() | mask));
+                // Clear output
+                portreg.clrout().write(|w| w.bits(mask));
+            } else {
+                portreg.dir().modify(|r, w| w.bits(r.bits() & !mask));
+            }
+        }
+    }
+
+    #[inline]
+    fn port_reg(&self) -> &PortRegisterBlock {
+        match self.id().group {
+            DynGroup::A => unsafe { &(*Self::PORTA) },
+            DynGroup::B => unsafe { &(*Self::PORTB) },
+        }
+    }
+    fn iocfg_port(&self) -> &PortReg {
+        let ioconfig = unsafe { va108xx::Ioconfig::ptr().as_ref().unwrap() };
+        match self.id().group {
+            DynGroup::A => ioconfig.porta(self.id().num as usize),
+            DynGroup::B => ioconfig.portb0(self.id().num as usize),
+        }
+    }
+
+    #[inline]
+    fn mask_32(&self) -> u32 {
+        1 << self.id().num
+    }
+
+    #[inline]
+    fn enable_irq(&self) {
+        self.port_reg()
+            .irq_enb()
+            .modify(|r, w| unsafe { w.bits(r.bits() | self.mask_32()) });
+    }
+
+    #[inline]
+    /// Read the logic level of an output pin
+    fn read_pin(&self) -> bool {
+        let portreg = self.port_reg();
+        ((portreg.datainraw().read().bits() >> self.id().num) & 0x01) == 1
+    }
+
+    // Get DATAMASK bit for this particular pin
+    #[inline(always)]
+    fn datamask(&self) -> bool {
+        let portreg = self.port_reg();
+        (portreg.datamask().read().bits() >> self.id().num) == 1
+    }
+
+    /// Read a pin but use the masked version but check whether the datamask for the pin is
+    /// cleared as well
+    #[inline(always)]
+    fn read_pin_masked(&self) -> Result<bool, IsMaskedError> {
+        if !self.datamask() {
+            Err(IsMaskedError)
+        } else {
+            Ok(((self.port_reg().datain().read().bits() >> self.id().num) & 0x01) == 1)
+        }
+    }
+
+    /// Write the logic level of an output pin
+    #[inline(always)]
+    fn write_pin(&mut self, bit: bool) {
+        // Safety: SETOUT is a "mask" register, and we only write the bit for
+        // this pin ID
+        unsafe {
+            if bit {
+                self.port_reg().setout().write(|w| w.bits(self.mask_32()));
+            } else {
+                self.port_reg().clrout().write(|w| w.bits(self.mask_32()));
+            }
+        }
+    }
+
+    /// Write the logic level of an output pin but check whether the datamask for the pin is
+    /// cleared as well
+    #[inline]
+    fn write_pin_masked(&mut self, bit: bool) -> Result<(), IsMaskedError> {
+        if !self.datamask() {
+            Err(IsMaskedError)
+        } else {
+            // Safety: SETOUT is a "mask" register, and we only write the bit for
+            // this pin ID
+            unsafe {
+                if bit {
+                    self.port_reg().setout().write(|w| w.bits(self.mask_32()));
+                } else {
+                    self.port_reg().clrout().write(|w| w.bits(self.mask_32()));
+                }
+                Ok(())
+            }
+        }
+    }
+
+    /// Toggle the logic level of an output pin
+    #[inline(always)]
+    fn toggle(&mut self) {
+        // Safety: TOGOUT is a "mask" register, and we only write the bit for
+        // this pin ID
+        unsafe { self.port_reg().togout().write(|w| w.bits(self.mask_32())) };
+    }
+
+    /// Only useful for interrupt pins. Configure whether to use edges or level as interrupt soure
+    /// When using edge mode, it is possible to generate interrupts on both edges as well
+    #[inline]
+    fn interrupt_edge(&mut self, edge_type: InterruptEdge) {
+        unsafe {
+            self.port_reg()
+                .irq_sen()
+                .modify(|r, w| w.bits(r.bits() & !self.mask_32()));
+            match edge_type {
+                InterruptEdge::HighToLow => {
+                    self.port_reg()
+                        .irq_evt()
+                        .modify(|r, w| w.bits(r.bits() & !self.mask_32()));
+                }
+                InterruptEdge::LowToHigh => {
+                    self.port_reg()
+                        .irq_evt()
+                        .modify(|r, w| w.bits(r.bits() | self.mask_32()));
+                }
+                InterruptEdge::BothEdges => {
+                    self.port_reg()
+                        .irq_edge()
+                        .modify(|r, w| w.bits(r.bits() | self.mask_32()));
+                }
+            }
+        }
+    }
+
+    /// Configure which edge or level type triggers an interrupt
+    #[inline]
+    fn interrupt_level(&mut self, level: InterruptLevel) {
+        unsafe {
+            self.port_reg()
+                .irq_sen()
+                .modify(|r, w| w.bits(r.bits() | self.mask_32()));
+            if level == InterruptLevel::Low {
+                self.port_reg()
+                    .irq_evt()
+                    .modify(|r, w| w.bits(r.bits() & !self.mask_32()));
+            } else {
+                self.port_reg()
+                    .irq_evt()
+                    .modify(|r, w| w.bits(r.bits() | self.mask_32()));
+            }
+        }
+    }
+
+    /// Only useful for input pins
+    #[inline]
+    fn filter_type(&mut self, filter: FilterType, clksel: FilterClkSel) {
+        self.iocfg_port().modify(|_, w| {
+            // Safety: Only write to register for this Pin ID
+            unsafe {
+                w.flttype().bits(filter as u8);
+                w.fltclk().bits(clksel as u8)
+            }
+        });
+    }
+
+    /// Set DATAMASK bit for this particular pin. 1 is the default
+    /// state of the bit and allows access of the corresponding bit
+    #[inline(always)]
+    fn set_datamask(&self) {
+        let portreg = self.port_reg();
+        unsafe {
+            portreg
+                .datamask()
+                .modify(|r, w| w.bits(r.bits() | self.mask_32()))
+        }
+    }
+
+    /// Clear DATAMASK bit for this particular pin. This prevents access
+    /// of the corresponding bit for output and input operations
+    #[inline(always)]
+    fn clear_datamask(&self) {
+        let portreg = self.port_reg();
+        unsafe {
+            portreg
+                .datamask()
+                .modify(|r, w| w.bits(r.bits() & !self.mask_32()))
+        }
+    }
+
+    /// Only useful for output pins
+    /// See p.52 of the programmers guide for more information.
+    /// When configured for pulse mode, a given pin will set the non-default state for exactly
+    /// one clock cycle before returning to the configured default state
+    fn pulse_mode(&mut self, enable: bool, default_state: PinState) {
+        let portreg = self.port_reg();
+        unsafe {
+            if enable {
+                portreg
+                    .pulse()
+                    .modify(|r, w| w.bits(r.bits() | self.mask_32()));
+            } else {
+                portreg
+                    .pulse()
+                    .modify(|r, w| w.bits(r.bits() & !self.mask_32()));
+            }
+            if default_state == PinState::Low {
+                portreg
+                    .pulsebase()
+                    .modify(|r, w| w.bits(r.bits() & !self.mask_32()));
+            } else {
+                portreg
+                    .pulsebase()
+                    .modify(|r, w| w.bits(r.bits() | self.mask_32()));
+            }
+        }
+    }
+
+    /// Only useful for output pins
+    fn delay(&self, delay_1: bool, delay_2: bool) {
+        let portreg = self.port_reg();
+        unsafe {
+            if delay_1 {
+                portreg
+                    .delay1()
+                    .modify(|r, w| w.bits(r.bits() | self.mask_32()));
+            } else {
+                portreg
+                    .delay1()
+                    .modify(|r, w| w.bits(r.bits() & !self.mask_32()));
+            }
+            if delay_2 {
+                portreg
+                    .delay2()
+                    .modify(|r, w| w.bits(r.bits() | self.mask_32()));
+            } else {
+                portreg
+                    .delay2()
+                    .modify(|r, w| w.bits(r.bits() & !self.mask_32()));
+            }
+        }
+    }
+}

va108xx-hal/src/lib.rs

@@ -1,59 +1,117 @@
 #![no_std]
 #![cfg_attr(docsrs, feature(doc_auto_cfg))]
 
-use gpio::Port;
 pub use va108xx;
 pub use va108xx as pac;
 
 pub mod clock;
 pub mod gpio;
 pub mod i2c;
-pub mod pins;
 pub mod prelude;
 pub mod pwm;
 pub mod spi;
 pub mod sysconfig;
 pub mod time;
 pub mod timer;
+pub mod typelevel;
 pub mod uart;
 
-pub use vorago_shared_periphs::{
+#[derive(Debug, Eq, Copy, Clone, PartialEq)]
-    disable_nvic_interrupt, enable_nvic_interrupt, FunSel, InterruptConfig, PeripheralSelect,
+pub enum FunSel {
-};
+    Sel1 = 0b01,
+    Sel2 = 0b10,
+    Sel3 = 0b11,
+}
 
-/// This is the NONE destination reigster value for the IRQSEL peripheral.
+#[derive(Debug, Copy, Clone, PartialEq, Eq)]
-pub const IRQ_DST_NONE: u32 = 0xffffffff;
+pub enum PortSel {
+    PortA,
+    PortB,
+}
 
-#[derive(Debug, PartialEq, Eq, thiserror::Error)]
+#[derive(Copy, Clone, PartialEq, Eq)]
-#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub enum PeripheralSelect {
-#[error("invalid pin with number {0}")]
+    PortA = 0,
-pub struct InvalidPinError(u8);
+    PortB = 1,
+    Spi0 = 4,
+    Spi1 = 5,
+    Spi2 = 6,
+    Uart0 = 8,
+    Uart1 = 9,
+    I2c0 = 16,
+    I2c1 = 17,
+    Irqsel = 21,
+    Ioconfig = 22,
+    Utility = 23,
+    Gpio = 24,
+}
 
-/// Can be used to manually manipulate the function select of port pins.
+/// Generic IRQ config which can be used to specify whether the HAL driver will
-///
+/// use the IRQSEL register to route an interrupt, and whether the IRQ will be unmasked in the
-/// The function selection table can be found on p.36 of the programmers guide. Please note
+/// Cortex-M0 NVIC. Both are generally necessary for IRQs to work, but the user might perform
-/// that most of the structures and APIs in this library will automatically correctly configure
+/// this steps themselves
-/// the pin or statically expect the correct pin type.
+#[derive(Debug, PartialEq, Eq, Clone, Copy)]
-pub fn port_function_select(
+pub struct IrqCfg {
+    /// Interrupt target vector. Should always be set, might be required for disabling IRQs
+    pub irq: pac::Interrupt,
+    /// Specfiy whether IRQ should be routed to an IRQ vector using the IRQSEL peripheral
+    pub route: bool,
+    /// Specify whether the IRQ is unmasked in the Cortex-M NVIC
+    pub enable: bool,
+}
+
+impl IrqCfg {
+    pub fn new(irq: pac::Interrupt, route: bool, enable: bool) -> Self {
+        IrqCfg { irq, route, enable }
+    }
+}
+
+#[derive(Debug, PartialEq, Eq)]
+pub struct InvalidPin(pub(crate) ());
+
+/// Can be used to manually manipulate the function select of port pins
+pub fn port_mux(
     ioconfig: &mut pac::Ioconfig,
-    port: Port,
+    port: PortSel,
     pin: u8,
     funsel: FunSel,
-) -> Result<(), InvalidPinError> {
+) -> Result<(), InvalidPin> {
-    if (port == Port::A && pin >= 32) || (port == Port::B && pin >= 24) {
+    match port {
-        return Err(InvalidPinError(pin));
+        PortSel::PortA => {
+            if pin > 31 {
+                return Err(InvalidPin(()));
             }
-
+            ioconfig
-    let reg_block = match port {
+                .porta(pin as usize)
-        Port::A => ioconfig.porta(pin as usize),
+                .modify(|_, w| unsafe { w.funsel().bits(funsel as u8) });
-        Port::B => ioconfig.portb0(pin as usize),
-    };
-
-    reg_block.modify(|_, w| unsafe { w.funsel().bits(funsel as u8) });
             Ok(())
+        }
+        PortSel::PortB => {
+            if pin > 23 {
+                return Err(InvalidPin(()));
+            }
+            ioconfig
+                .portb0(pin as usize)
+                .modify(|_, w| unsafe { w.funsel().bits(funsel as u8) });
+            Ok(())
+        }
+    }
 }
 
-#[allow(dead_code)]
+/// Enable a specific interrupt using the NVIC peripheral.
-pub(crate) mod sealed {
+///
-    pub trait Sealed {}
+/// # Safety
+///
+/// This function is `unsafe` because it can break mask-based critical sections.
+#[inline]
+pub unsafe fn enable_interrupt(irq: pac::Interrupt) {
+    unsafe {
+        cortex_m::peripheral::NVIC::unmask(irq);
+    }
+}
+
+/// Disable a specific interrupt using the NVIC peripheral.
+#[inline]
+pub fn disable_interrupt(irq: pac::Interrupt) {
+    cortex_m::peripheral::NVIC::mask(irq);
 }

va108xx-hal/src/pins.rs

@@ -1,6 +0,0 @@
-//! Pin resource management singletons.
-//!
-//! This module contains the pin singletons. It allows creating those singletons
-//! to access the [Pin] structures of individual ports in a safe way with checked ownership
-//! rules.
-pub use vorago_shared_periphs::pins::*;

va108xx-hal/src/pwm.rs

@@ -5,4 +5,455 @@
 //! ## Examples
 //!
 //! - [PWM example](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/examples/simple/examples/pwm.rs)
-pub use vorago_shared_periphs::pwm::*;
+use core::convert::Infallible;
+use core::marker::PhantomData;
+
+use crate::pac;
+use crate::time::Hertz;
+use crate::timer::{TimDynRegister, TimPin, TimRegInterface, ValidTim, ValidTimAndPin};
+use crate::{clock::enable_peripheral_clock, gpio::DynPinId};
+
+const DUTY_MAX: u16 = u16::MAX;
+
+pub struct PwmCommon {
+    sys_clk: Hertz,
+    /// For PWMB, this is the upper limit
+    current_duty: u16,
+    /// For PWMA, this value will not be used
+    current_lower_limit: u16,
+    current_period: Hertz,
+    current_rst_val: u32,
+}
+
+enum StatusSelPwm {
+    PwmA = 3,
+    PwmB = 4,
+}
+
+pub struct PwmA {}
+pub struct PwmB {}
+
+//==================================================================================================
+// Strongly typed PWM pin
+//==================================================================================================
+
+pub struct PwmPin<Pin: TimPin, Tim: ValidTim, Mode = PwmA> {
+    pin_and_tim: (Pin, Tim),
+    inner: ReducedPwmPin<Mode>,
+    mode: PhantomData<Mode>,
+}
+
+impl<Pin: TimPin, Tim: ValidTim, Mode> PwmPin<Pin, Tim, Mode>
+where
+    (Pin, Tim): ValidTimAndPin<Pin, Tim>,
+{
+    /// Create a new stronlgy typed PWM pin
+    pub fn new(
+        sys_cfg: &mut pac::Sysconfig,
+        sys_clk: impl Into<Hertz> + Copy,
+        pin_and_tim: (Pin, Tim),
+        initial_period: impl Into<Hertz> + Copy,
+    ) -> Self {
+        let mut pin = PwmPin {
+            pin_and_tim,
+            inner: ReducedPwmPin::<Mode>::new(
+                Tim::TIM_ID,
+                Pin::DYN,
+                PwmCommon {
+                    current_duty: 0,
+                    current_lower_limit: 0,
+                    current_period: initial_period.into(),
+                    current_rst_val: 0,
+                    sys_clk: sys_clk.into(),
+                },
+            ),
+            //unsafe { TimAndPin::new(tim_and_pin.0, tim_and_pin.1) },
+            mode: PhantomData,
+        };
+        enable_peripheral_clock(sys_cfg, crate::clock::PeripheralClocks::Gpio);
+        enable_peripheral_clock(sys_cfg, crate::clock::PeripheralClocks::Ioconfig);
+        sys_cfg
+            .tim_clk_enable()
+            .modify(|r, w| unsafe { w.bits(r.bits() | pin.pin_and_tim.1.mask_32()) });
+        pin.enable_pwm_a();
+        pin.set_period(initial_period);
+        pin
+    }
+
+    pub fn reduce(self) -> ReducedPwmPin<Mode> {
+        self.inner
+    }
+
+    pub fn release(self) -> (Pin, Tim) {
+        self.pin_and_tim
+    }
+
+    #[inline]
+    fn enable_pwm_a(&mut self) {
+        self.inner.enable_pwm_a();
+    }
+
+    #[inline]
+    fn enable_pwm_b(&mut self) {
+        self.inner.enable_pwm_b();
+    }
+
+    #[inline]
+    pub fn get_period(&self) -> Hertz {
+        self.inner.get_period()
+    }
+
+    #[inline]
+    pub fn set_period(&mut self, period: impl Into<Hertz>) {
+        self.inner.set_period(period);
+    }
+
+    #[inline]
+    pub fn disable(&mut self) {
+        self.inner.disable();
+    }
+
+    #[inline]
+    pub fn enable(&mut self) {
+        self.inner.enable();
+    }
+
+    #[inline]
+    pub fn period(&self) -> Hertz {
+        self.inner.period()
+    }
+
+    #[inline(always)]
+    pub fn duty(&self) -> u16 {
+        self.inner.duty()
+    }
+}
+
+impl<Pin: TimPin, Tim: ValidTim> From<PwmPin<Pin, Tim, PwmA>> for PwmPin<Pin, Tim, PwmB>
+where
+    (Pin, Tim): ValidTimAndPin<Pin, Tim>,
+{
+    fn from(other: PwmPin<Pin, Tim, PwmA>) -> Self {
+        let mut pwmb = Self {
+            mode: PhantomData,
+            pin_and_tim: other.pin_and_tim,
+            inner: other.inner.into(),
+        };
+        pwmb.enable_pwm_b();
+        pwmb
+    }
+}
+
+impl<PIN: TimPin, TIM: ValidTim> From<PwmPin<PIN, TIM, PwmB>> for PwmPin<PIN, TIM, PwmA>
+where
+    (PIN, TIM): ValidTimAndPin<PIN, TIM>,
+{
+    fn from(other: PwmPin<PIN, TIM, PwmB>) -> Self {
+        let mut pwma = Self {
+            mode: PhantomData,
+            pin_and_tim: other.pin_and_tim,
+            inner: other.inner.into(),
+        };
+        pwma.enable_pwm_a();
+        pwma
+    }
+}
+
+impl<Pin: TimPin, Tim: ValidTim> PwmPin<Pin, Tim, PwmA>
+where
+    (Pin, Tim): ValidTimAndPin<Pin, Tim>,
+{
+    pub fn pwma(
+        sys_cfg: &mut pac::Sysconfig,
+        sys_clk: impl Into<Hertz> + Copy,
+        pin_and_tim: (Pin, Tim),
+        initial_period: impl Into<Hertz> + Copy,
+    ) -> Self {
+        let mut pin: PwmPin<Pin, Tim, PwmA> =
+            Self::new(sys_cfg, sys_clk, pin_and_tim, initial_period);
+        pin.enable_pwm_a();
+        pin
+    }
+}
+
+impl<Pin: TimPin, Tim: ValidTim> PwmPin<Pin, Tim, PwmB>
+where
+    (Pin, Tim): ValidTimAndPin<Pin, Tim>,
+{
+    pub fn pwmb(
+        sys_cfg: &mut pac::Sysconfig,
+        sys_clk: impl Into<Hertz> + Copy,
+        pin_and_tim: (Pin, Tim),
+        initial_period: impl Into<Hertz> + Copy,
+    ) -> Self {
+        let mut pin: PwmPin<Pin, Tim, PwmB> =
+            Self::new(sys_cfg, sys_clk, pin_and_tim, initial_period);
+        pin.enable_pwm_b();
+        pin
+    }
+}
+
+//==================================================================================================
+// Reduced PWM pin
+//==================================================================================================
+
+/// Reduced version where type information is deleted
+pub struct ReducedPwmPin<Mode = PwmA> {
+    dyn_reg: TimDynRegister,
+    common: PwmCommon,
+    mode: PhantomData<Mode>,
+}
+
+impl<Mode> ReducedPwmPin<Mode> {
+    pub(crate) fn new(tim_id: u8, pin_id: DynPinId, common: PwmCommon) -> Self {
+        Self {
+            dyn_reg: TimDynRegister { tim_id, pin_id },
+            common,
+            mode: PhantomData,
+        }
+    }
+}
+/*
+impl<Pin: TimPin, Tim: ValidTim> From<PwmPin<Pin, Tim>> for ReducedPwmPin<PwmA> {
+    fn from(pwm_pin: PwmPin<Pin, Tim>) -> Self {
+        ReducedPwmPin {
+            dyn_reg: TimDynRegister {
+
+
+            }
+            // ::from(pwm_pin.reg),
+            common: pwm_pin.pwm_base,
+            pin_id: Pin::DYN,
+            mode: PhantomData,
+        }
+    }
+}
+*/
+
+impl<Mode> ReducedPwmPin<Mode> {
+    #[inline]
+    fn enable_pwm_a(&mut self) {
+        self.dyn_reg
+            .reg_block()
+            .ctrl()
+            .modify(|_, w| unsafe { w.status_sel().bits(StatusSelPwm::PwmA as u8) });
+    }
+
+    #[inline]
+    fn enable_pwm_b(&mut self) {
+        self.dyn_reg
+            .reg_block()
+            .ctrl()
+            .modify(|_, w| unsafe { w.status_sel().bits(StatusSelPwm::PwmB as u8) });
+    }
+
+    #[inline]
+    pub fn get_period(&self) -> Hertz {
+        self.common.current_period
+    }
+
+    #[inline]
+    pub fn set_period(&mut self, period: impl Into<Hertz>) {
+        self.common.current_period = period.into();
+        // Avoid division by 0
+        if self.common.current_period.raw() == 0 {
+            return;
+        }
+        self.common.current_rst_val = self.common.sys_clk.raw() / self.common.current_period.raw();
+        self.dyn_reg
+            .reg_block()
+            .rst_value()
+            .write(|w| unsafe { w.bits(self.common.current_rst_val) });
+    }
+
+    #[inline]
+    pub fn disable(&mut self) {
+        self.dyn_reg
+            .reg_block()
+            .ctrl()
+            .modify(|_, w| w.enable().clear_bit());
+    }
+
+    #[inline]
+    pub fn enable(&mut self) {
+        self.dyn_reg
+            .reg_block()
+            .ctrl()
+            .modify(|_, w| w.enable().set_bit());
+    }
+
+    #[inline]
+    pub fn period(&self) -> Hertz {
+        self.common.current_period
+    }
+
+    #[inline(always)]
+    pub fn duty(&self) -> u16 {
+        self.common.current_duty
+    }
+}
+
+impl From<ReducedPwmPin<PwmA>> for ReducedPwmPin<PwmB> {
+    fn from(other: ReducedPwmPin<PwmA>) -> Self {
+        let mut pwmb = Self {
+            dyn_reg: other.dyn_reg,
+            common: other.common,
+            mode: PhantomData,
+        };
+        pwmb.enable_pwm_b();
+        pwmb
+    }
+}
+
+impl From<ReducedPwmPin<PwmB>> for ReducedPwmPin<PwmA> {
+    fn from(other: ReducedPwmPin<PwmB>) -> Self {
+        let mut pwmb = Self {
+            dyn_reg: other.dyn_reg,
+            common: other.common,
+            mode: PhantomData,
+        };
+        pwmb.enable_pwm_a();
+        pwmb
+    }
+}
+
+//==================================================================================================
+// PWMB implementations
+//==================================================================================================
+
+impl<Pin: TimPin, Tim: ValidTim> PwmPin<Pin, Tim, PwmB>
+where
+    (Pin, Tim): ValidTimAndPin<Pin, Tim>,
+{
+    pub fn pwmb_lower_limit(&self) -> u16 {
+        self.inner.pwmb_lower_limit()
+    }
+
+    pub fn pwmb_upper_limit(&self) -> u16 {
+        self.inner.pwmb_upper_limit()
+    }
+
+    /// Set the lower limit for PWMB
+    ///
+    /// The PWM signal will be 1 as long as the current RST counter is larger than
+    /// the lower limit. For example, with a lower limit of 0.5 and and an upper limit
+    /// of 0.7, Only a fixed period between 0.5 * period and 0.7 * period will be in a high
+    /// state
+    pub fn set_pwmb_lower_limit(&mut self, duty: u16) {
+        self.inner.set_pwmb_lower_limit(duty);
+    }
+
+    /// Set the higher limit for PWMB
+    ///
+    /// The PWM signal will be 1 as long as the current RST counter is smaller than
+    /// the higher limit. For example, with a lower limit of 0.5 and and an upper limit
+    /// of 0.7, Only a fixed period between 0.5 * period and 0.7 * period will be in a high
+    /// state
+    pub fn set_pwmb_upper_limit(&mut self, duty: u16) {
+        self.inner.set_pwmb_upper_limit(duty);
+    }
+}
+
+impl ReducedPwmPin<PwmB> {
+    #[inline(always)]
+    pub fn pwmb_lower_limit(&self) -> u16 {
+        self.common.current_lower_limit
+    }
+
+    #[inline(always)]
+    pub fn pwmb_upper_limit(&self) -> u16 {
+        self.common.current_duty
+    }
+
+    /// Set the lower limit for PWMB
+    ///
+    /// The PWM signal will be 1 as long as the current RST counter is larger than
+    /// the lower limit. For example, with a lower limit of 0.5 and and an upper limit
+    /// of 0.7, Only a fixed period between 0.5 * period and 0.7 * period will be in a high
+    /// state
+    #[inline(always)]
+    pub fn set_pwmb_lower_limit(&mut self, duty: u16) {
+        self.common.current_lower_limit = duty;
+        let pwmb_val: u64 = (self.common.current_rst_val as u64
+            * self.common.current_lower_limit as u64)
+            / DUTY_MAX as u64;
+        self.dyn_reg
+            .reg_block()
+            .pwmb_value()
+            .write(|w| unsafe { w.bits(pwmb_val as u32) });
+    }
+
+    /// Set the higher limit for PWMB
+    ///
+    /// The PWM signal will be 1 as long as the current RST counter is smaller than
+    /// the higher limit. For example, with a lower limit of 0.5 and and an upper limit
+    /// of 0.7, Only a fixed period between 0.5 * period and 0.7 * period will be in a high
+    /// state
+    pub fn set_pwmb_upper_limit(&mut self, duty: u16) {
+        self.common.current_duty = duty;
+        let pwma_val: u64 = (self.common.current_rst_val as u64 * self.common.current_duty as u64)
+            / DUTY_MAX as u64;
+        self.dyn_reg
+            .reg_block()
+            .pwma_value()
+            .write(|w| unsafe { w.bits(pwma_val as u32) });
+    }
+}
+
+//==================================================================================================
+// Embedded HAL implementation: PWMA only
+//==================================================================================================
+
+impl<Pin: TimPin, Tim: ValidTim> embedded_hal::pwm::ErrorType for PwmPin<Pin, Tim> {
+    type Error = Infallible;
+}
+
+impl embedded_hal::pwm::ErrorType for ReducedPwmPin {
+    type Error = Infallible;
+}
+
+impl embedded_hal::pwm::SetDutyCycle for ReducedPwmPin {
+    #[inline]
+    fn max_duty_cycle(&self) -> u16 {
+        DUTY_MAX
+    }
+
+    #[inline]
+    fn set_duty_cycle(&mut self, duty: u16) -> Result<(), Self::Error> {
+        self.common.current_duty = duty;
+        let pwma_val: u64 = (self.common.current_rst_val as u64
+            * (DUTY_MAX as u64 - self.common.current_duty as u64))
+            / DUTY_MAX as u64;
+        self.dyn_reg
+            .reg_block()
+            .pwma_value()
+            .write(|w| unsafe { w.bits(pwma_val as u32) });
+        Ok(())
+    }
+}
+
+impl<Pin: TimPin, Tim: ValidTim> embedded_hal::pwm::SetDutyCycle for PwmPin<Pin, Tim> {
+    #[inline]
+    fn max_duty_cycle(&self) -> u16 {
+        DUTY_MAX
+    }
+
+    #[inline]
+    fn set_duty_cycle(&mut self, duty: u16) -> Result<(), Self::Error> {
+        self.inner.set_duty_cycle(duty)
+    }
+}
+
+/// Get the corresponding u16 duty cycle from a percent value ranging between 0.0 and 1.0.
+///
+/// Please note that this might load a lot of floating point code because this processor does not
+/// have a FPU
+pub fn get_duty_from_percent(percent: f32) -> u16 {
+    if percent > 1.0 {
+        DUTY_MAX
+    } else if percent <= 0.0 {
+        0
+    } else {
+        (percent * DUTY_MAX as f32) as u16
+    }
+}

va108xx-hal/src/spi/mod.rs

@@ -1,12 +0,0 @@
-//! API for the SPI peripheral.
-//!
-//! The main abstraction provided by this module is the [Spi] an structure.
-//! It provides the [SpiBus trait](https://docs.rs/embedded-hal/latest/embedded_hal/spi/trait.SpiBus.html),
-//! but also offer a low level interface via the [SpiLowLevel] trait.
-//!
-//! ## Examples
-//!
-//! - [Blocking SPI example](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/examples/simple/examples/spi.rs)
-//! - [REB1 ADC example](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/vorago-reb1/examples/max11519-adc.rs)
-//! - [REB1 EEPROM library](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/vorago-reb1/src/m95m01.rs)
-pub use vorago_shared_periphs::spi::*;

va108xx-hal/src/sysconfig.rs

@@ -1,3 +1,5 @@
+use crate::{pac, PeripheralSelect};
+
 #[derive(PartialEq, Eq, Debug)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub struct InvalidCounterResetVal(pub(crate) ());
@@ -6,8 +8,10 @@ pub struct InvalidCounterResetVal(pub(crate) ());
 ///
 /// Returns [InvalidCounterResetVal] if the scrub rate is 0
 /// (equivalent to disabling) or larger than 24 bits
-pub fn enable_rom_scrubbing(scrub_rate: u32) -> Result<(), InvalidCounterResetVal> {
+pub fn enable_rom_scrubbing(
-    let syscfg = unsafe { va108xx::Sysconfig::steal() };
+    syscfg: &mut pac::Sysconfig,
+    scrub_rate: u32,
+) -> Result<(), InvalidCounterResetVal> {
     if scrub_rate == 0 || scrub_rate > u32::pow(2, 24) {
         return Err(InvalidCounterResetVal(()));
     }
@@ -15,17 +19,18 @@ pub fn enable_rom_scrubbing(scrub_rate: u32) -> Result<(), InvalidCounterResetVa
     Ok(())
 }
 
-pub fn disable_rom_scrubbing() {
+pub fn disable_rom_scrubbing(syscfg: &mut pac::Sysconfig) {
-    let syscfg = unsafe { va108xx::Sysconfig::steal() };
+    syscfg.rom_scrub().write(|w| unsafe { w.bits(0) })
-    syscfg.rom_scrub().write(|w| unsafe { w.bits(0) });
 }
 
 /// Enable scrubbing for the RAM
 ///
 /// Returns [InvalidCounterResetVal] if the scrub rate is 0
 /// (equivalent to disabling) or larger than 24 bits
-pub fn enable_ram_scrubbing(scrub_rate: u32) -> Result<(), InvalidCounterResetVal> {
+pub fn enable_ram_scrubbing(
-    let syscfg = unsafe { va108xx::Sysconfig::steal() };
+    syscfg: &mut pac::Sysconfig,
+    scrub_rate: u32,
+) -> Result<(), InvalidCounterResetVal> {
     if scrub_rate == 0 || scrub_rate > u32::pow(2, 24) {
         return Err(InvalidCounterResetVal(()));
     }
@@ -33,11 +38,20 @@ pub fn enable_ram_scrubbing(scrub_rate: u32) -> Result<(), InvalidCounterResetVa
     Ok(())
 }
 
-pub fn disable_ram_scrubbing() {
+pub fn disable_ram_scrubbing(syscfg: &mut pac::Sysconfig) {
-    let syscfg = unsafe { va108xx::Sysconfig::steal() };
+    syscfg.ram_scrub().write(|w| unsafe { w.bits(0) })
-    syscfg.ram_scrub().write(|w| unsafe { w.bits(0) });
 }
 
-pub use vorago_shared_periphs::sysconfig::{
+/// Clear the reset bit. This register is active low, so doing this will hold the peripheral
-    assert_peripheral_reset, disable_peripheral_clock, enable_peripheral_clock,
+/// in a reset state
-};
+pub fn clear_reset_bit(syscfg: &mut pac::Sysconfig, periph_sel: PeripheralSelect) {
+    syscfg
+        .peripheral_reset()
+        .modify(|r, w| unsafe { w.bits(r.bits() & !(1 << periph_sel as u8)) });
+}
+
+pub fn set_reset_bit(syscfg: &mut pac::Sysconfig, periph_sel: PeripheralSelect) {
+    syscfg
+        .peripheral_reset()
+        .modify(|r, w| unsafe { w.bits(r.bits() | (1 << periph_sel as u8)) });
+}

va108xx-hal/src/time.rs

@@ -1,2 +1,26 @@
 //! Time units
-pub use vorago_shared_periphs::time::*;
+
+// Frequency based
+
+/// Hertz
+pub type Hertz = fugit::HertzU32;
+
+/// KiloHertz
+pub type KiloHertz = fugit::KilohertzU32;
+
+/// MegaHertz
+pub type MegaHertz = fugit::MegahertzU32;
+
+// Period based
+
+/// Seconds
+pub type Seconds = fugit::SecsDurationU32;
+
+/// Milliseconds
+pub type Milliseconds = fugit::MillisDurationU32;
+
+/// Microseconds
+pub type Microseconds = fugit::MicrosDurationU32;
+
+/// Nanoseconds
+pub type Nanoseconds = fugit::NanosDurationU32;

va108xx-hal/src/timer.rs

@@ -4,4 +4,784 @@
 //!
 //! - [MS and second tick implementation](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/examples/simple/examples/timer-ticks.rs)
 //! - [Cascade feature example](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/examples/simple/examples/cascade.rs)
-pub use vorago_shared_periphs::timer::*;
+pub use crate::IrqCfg;
+use crate::{
+    clock::{enable_peripheral_clock, PeripheralClocks},
+    enable_interrupt,
+    gpio::{
+        AltFunc1, AltFunc2, AltFunc3, DynPinId, Pin, PinId, PA0, PA1, PA10, PA11, PA12, PA13, PA14,
+        PA15, PA2, PA24, PA25, PA26, PA27, PA28, PA29, PA3, PA30, PA31, PA4, PA5, PA6, PA7, PA8,
+        PA9, PB0, PB1, PB10, PB11, PB12, PB13, PB14, PB15, PB16, PB17, PB18, PB19, PB2, PB20, PB21,
+        PB22, PB23, PB3, PB4, PB5, PB6,
+    },
+    pac::{self, tim0},
+    time::Hertz,
+    timer,
+    typelevel::Sealed,
+};
+use core::cell::Cell;
+use critical_section::Mutex;
+use fugit::RateExtU32;
+
+const IRQ_DST_NONE: u32 = 0xffffffff;
+pub static MS_COUNTER: Mutex<Cell<u32>> = Mutex::new(Cell::new(0));
+
+/// Get the peripheral block of a TIM peripheral given the index.
+///
+/// This function panics if the given index is greater than 23.
+///
+/// # Safety
+///
+/// This returns a direct handle to the peripheral block, which allows to circumvent ownership
+/// rules for the peripheral block. You have to ensure that the retrieved peripheral block is not
+/// used by any other software component.
+#[inline(always)]
+pub const unsafe fn get_tim_raw(tim_idx: usize) -> &'static pac::tim0::RegisterBlock {
+    match tim_idx {
+        0 => unsafe { &*pac::Tim0::ptr() },
+        1 => unsafe { &*pac::Tim1::ptr() },
+        2 => unsafe { &*pac::Tim2::ptr() },
+        3 => unsafe { &*pac::Tim3::ptr() },
+        4 => unsafe { &*pac::Tim4::ptr() },
+        5 => unsafe { &*pac::Tim5::ptr() },
+        6 => unsafe { &*pac::Tim6::ptr() },
+        7 => unsafe { &*pac::Tim7::ptr() },
+        8 => unsafe { &*pac::Tim8::ptr() },
+        9 => unsafe { &*pac::Tim9::ptr() },
+        10 => unsafe { &*pac::Tim10::ptr() },
+        11 => unsafe { &*pac::Tim11::ptr() },
+        12 => unsafe { &*pac::Tim12::ptr() },
+        13 => unsafe { &*pac::Tim13::ptr() },
+        14 => unsafe { &*pac::Tim14::ptr() },
+        15 => unsafe { &*pac::Tim15::ptr() },
+        16 => unsafe { &*pac::Tim16::ptr() },
+        17 => unsafe { &*pac::Tim17::ptr() },
+        18 => unsafe { &*pac::Tim18::ptr() },
+        19 => unsafe { &*pac::Tim19::ptr() },
+        20 => unsafe { &*pac::Tim20::ptr() },
+        21 => unsafe { &*pac::Tim21::ptr() },
+        22 => unsafe { &*pac::Tim22::ptr() },
+        23 => unsafe { &*pac::Tim23::ptr() },
+        _ => {
+            panic!("invalid alarm timer index")
+        }
+    }
+}
+
+//==================================================================================================
+// Defintions
+//==================================================================================================
+
+/// Interrupt events
+pub enum Event {
+    /// Timer timed out / count down ended
+    TimeOut,
+}
+
+#[derive(Default, Debug, PartialEq, Eq, Copy, Clone)]
+pub struct CascadeCtrl {
+    /// Enable Cascade 0 signal active as a requirement for counting
+    pub enb_start_src_csd0: bool,
+    /// Invert Cascade 0, making it active low
+    pub inv_csd0: bool,
+    /// Enable Cascade 1 signal active as a requirement for counting
+    pub enb_start_src_csd1: bool,
+    /// Invert Cascade 1, making it active low
+    pub inv_csd1: bool,
+    /// Specify required operation if both Cascade 0 and Cascade 1 are active.
+    /// 0 is a logical AND of both cascade signals, 1 is a logical OR
+    pub dual_csd_op: bool,
+    /// Enable trigger mode for Cascade 0. In trigger mode, couting will start with the selected
+    /// cascade signal active, but once the counter is active, cascade control will be ignored
+    pub trg_csd0: bool,
+    /// Trigger mode, identical to [`trg_csd0`](CascadeCtrl) but for Cascade 1
+    pub trg_csd1: bool,
+    /// Enable Cascade 2 signal active as a requirement to stop counting. This mode is similar
+    /// to the REQ_STOP control bit, but signalled by a Cascade source
+    pub enb_stop_src_csd2: bool,
+    /// Invert Cascade 2, making it active low
+    pub inv_csd2: bool,
+    /// The counter is automatically disabled if the corresponding Cascade 2 level-sensitive input
+    /// souce is active when the count reaches 0. If the counter is not 0, the cascade control is
+    /// ignored
+    pub trg_csd2: bool,
+}
+
+#[derive(Debug, PartialEq, Eq)]
+pub enum CascadeSel {
+    Csd0 = 0,
+    Csd1 = 1,
+    Csd2 = 2,
+}
+
+#[derive(Debug, PartialEq, Eq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub struct InvalidCascadeSourceId;
+
+/// The numbers are the base numbers for bundles like PORTA, PORTB or TIM
+#[derive(Debug, PartialEq, Eq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[repr(u8)]
+pub enum CascadeSource {
+    PortA(u8),
+    PortB(u8),
+    Tim(u8),
+    RamSbe = 96,
+    RamMbe = 97,
+    RomSbe = 98,
+    RomMbe = 99,
+    Txev = 100,
+    ClockDivider(u8),
+}
+
+impl CascadeSource {
+    fn id(&self) -> Result<u8, InvalidCascadeSourceId> {
+        let port_check = |base: u8, id: u8, len: u8| {
+            if id > len - 1 {
+                return Err(InvalidCascadeSourceId);
+            }
+            Ok(base + id)
+        };
+        match self {
+            CascadeSource::PortA(id) => port_check(0, *id, 32),
+            CascadeSource::PortB(id) => port_check(32, *id, 32),
+            CascadeSource::Tim(id) => port_check(64, *id, 24),
+            CascadeSource::RamSbe => Ok(96),
+            CascadeSource::RamMbe => Ok(97),
+            CascadeSource::RomSbe => Ok(98),
+            CascadeSource::RomMbe => Ok(99),
+            CascadeSource::Txev => Ok(100),
+            CascadeSource::ClockDivider(id) => port_check(120, *id, 8),
+        }
+    }
+}
+
+//==================================================================================================
+// Valid TIM and PIN combinations
+//==================================================================================================
+
+pub trait TimPin {
+    const DYN: DynPinId;
+}
+
+pub trait ValidTim {
+    // TIM ID ranging from 0 to 23 for 24 TIM peripherals
+    const TIM_ID: u8;
+}
+
+macro_rules! tim_marker {
+    ($TIMX:path, $ID:expr) => {
+        impl ValidTim for $TIMX {
+            const TIM_ID: u8 = $ID;
+        }
+    };
+}
+
+tim_marker!(pac::Tim0, 0);
+tim_marker!(pac::Tim1, 1);
+tim_marker!(pac::Tim2, 2);
+tim_marker!(pac::Tim3, 3);
+tim_marker!(pac::Tim4, 4);
+tim_marker!(pac::Tim5, 5);
+tim_marker!(pac::Tim6, 6);
+tim_marker!(pac::Tim7, 7);
+tim_marker!(pac::Tim8, 8);
+tim_marker!(pac::Tim9, 9);
+tim_marker!(pac::Tim10, 10);
+tim_marker!(pac::Tim11, 11);
+tim_marker!(pac::Tim12, 12);
+tim_marker!(pac::Tim13, 13);
+tim_marker!(pac::Tim14, 14);
+tim_marker!(pac::Tim15, 15);
+tim_marker!(pac::Tim16, 16);
+tim_marker!(pac::Tim17, 17);
+tim_marker!(pac::Tim18, 18);
+tim_marker!(pac::Tim19, 19);
+tim_marker!(pac::Tim20, 20);
+tim_marker!(pac::Tim21, 21);
+tim_marker!(pac::Tim22, 22);
+tim_marker!(pac::Tim23, 23);
+
+pub trait ValidTimAndPin<PIN: TimPin, TIM: ValidTim>: Sealed {}
+
+macro_rules! pin_and_tim {
+    ($PAX:ident, $ALTFUNC:ident, $ID:expr, $TIMX:path) => {
+        impl TimPin for Pin<$PAX, $ALTFUNC>
+        where
+            $PAX: PinId,
+        {
+            const DYN: DynPinId = $PAX::DYN;
+        }
+
+        impl<PIN: TimPin, TIM: ValidTim> ValidTimAndPin<PIN, TIM> for (Pin<$PAX, $ALTFUNC>, $TIMX)
+        where
+            Pin<$PAX, $ALTFUNC>: TimPin,
+            $PAX: PinId,
+        {
+        }
+
+        impl Sealed for (Pin<$PAX, $ALTFUNC>, $TIMX) {}
+    };
+}
+
+pin_and_tim!(PA31, AltFunc2, 23, pac::Tim23);
+pin_and_tim!(PA30, AltFunc2, 22, pac::Tim22);
+pin_and_tim!(PA29, AltFunc2, 21, pac::Tim21);
+pin_and_tim!(PA28, AltFunc2, 20, pac::Tim20);
+pin_and_tim!(PA27, AltFunc2, 19, pac::Tim19);
+pin_and_tim!(PA26, AltFunc2, 18, pac::Tim18);
+pin_and_tim!(PA25, AltFunc2, 17, pac::Tim17);
+pin_and_tim!(PA24, AltFunc2, 16, pac::Tim16);
+
+pin_and_tim!(PA15, AltFunc1, 15, pac::Tim15);
+pin_and_tim!(PA14, AltFunc1, 14, pac::Tim14);
+pin_and_tim!(PA13, AltFunc1, 13, pac::Tim13);
+pin_and_tim!(PA12, AltFunc1, 12, pac::Tim12);
+pin_and_tim!(PA11, AltFunc1, 11, pac::Tim11);
+pin_and_tim!(PA10, AltFunc1, 10, pac::Tim10);
+pin_and_tim!(PA9, AltFunc1, 9, pac::Tim9);
+pin_and_tim!(PA8, AltFunc1, 8, pac::Tim8);
+pin_and_tim!(PA7, AltFunc1, 7, pac::Tim7);
+pin_and_tim!(PA6, AltFunc1, 6, pac::Tim6);
+pin_and_tim!(PA5, AltFunc1, 5, pac::Tim5);
+pin_and_tim!(PA4, AltFunc1, 4, pac::Tim4);
+pin_and_tim!(PA3, AltFunc1, 3, pac::Tim3);
+pin_and_tim!(PA2, AltFunc1, 2, pac::Tim2);
+pin_and_tim!(PA1, AltFunc1, 1, pac::Tim1);
+pin_and_tim!(PA0, AltFunc1, 0, pac::Tim0);
+
+pin_and_tim!(PB23, AltFunc3, 23, pac::Tim23);
+pin_and_tim!(PB22, AltFunc3, 22, pac::Tim22);
+pin_and_tim!(PB21, AltFunc3, 21, pac::Tim21);
+pin_and_tim!(PB20, AltFunc3, 20, pac::Tim20);
+pin_and_tim!(PB19, AltFunc3, 19, pac::Tim19);
+pin_and_tim!(PB18, AltFunc3, 18, pac::Tim18);
+pin_and_tim!(PB17, AltFunc3, 17, pac::Tim17);
+pin_and_tim!(PB16, AltFunc3, 16, pac::Tim16);
+pin_and_tim!(PB15, AltFunc3, 15, pac::Tim15);
+pin_and_tim!(PB14, AltFunc3, 14, pac::Tim14);
+pin_and_tim!(PB13, AltFunc3, 13, pac::Tim13);
+pin_and_tim!(PB12, AltFunc3, 12, pac::Tim12);
+pin_and_tim!(PB11, AltFunc3, 11, pac::Tim11);
+pin_and_tim!(PB10, AltFunc3, 10, pac::Tim10);
+
+pin_and_tim!(PB6, AltFunc3, 6, pac::Tim6);
+pin_and_tim!(PB5, AltFunc3, 5, pac::Tim5);
+pin_and_tim!(PB4, AltFunc3, 4, pac::Tim4);
+pin_and_tim!(PB3, AltFunc3, 3, pac::Tim3);
+pin_and_tim!(PB2, AltFunc3, 2, pac::Tim2);
+pin_and_tim!(PB1, AltFunc3, 1, pac::Tim1);
+pin_and_tim!(PB0, AltFunc3, 0, pac::Tim0);
+
+//==================================================================================================
+// Register Interface for TIM registers and TIM pins
+//==================================================================================================
+
+pub type TimRegBlock = tim0::RegisterBlock;
+
+/// Register interface.
+///
+/// This interface provides valid TIM pins a way to access their corresponding TIM
+/// registers
+///
+/// # Safety
+///
+/// Users should only implement the [`tim_id`] function. No default function
+/// implementations should be overridden. The implementing type must also have
+/// "control" over the corresponding pin ID, i.e. it must guarantee that a each
+/// pin ID is a singleton.
+pub unsafe trait TimRegInterface {
+    fn tim_id(&self) -> u8;
+
+    const PORT_BASE: *const tim0::RegisterBlock = pac::Tim0::ptr() as *const _;
+
+    /// All 24 TIM blocks are identical. This helper functions returns the correct
+    /// memory mapped peripheral depending on the TIM ID.
+    #[inline(always)]
+    fn reg_block(&self) -> &TimRegBlock {
+        unsafe { &*Self::PORT_BASE.offset(self.tim_id() as isize) }
+    }
+
+    #[inline(always)]
+    fn mask_32(&self) -> u32 {
+        1 << self.tim_id()
+    }
+
+    /// Clear the reset bit of the TIM, holding it in reset
+    ///
+    /// # Safety
+    ///
+    /// Only the bit related to the corresponding TIM peripheral is modified
+    #[inline]
+    #[allow(dead_code)]
+    fn clear_tim_reset_bit(&self) {
+        unsafe {
+            va108xx::Peripherals::steal()
+                .sysconfig
+                .tim_reset()
+                .modify(|r, w| w.bits(r.bits() & !self.mask_32()))
+        }
+    }
+
+    #[inline]
+    #[allow(dead_code)]
+    fn set_tim_reset_bit(&self) {
+        unsafe {
+            va108xx::Peripherals::steal()
+                .sysconfig
+                .tim_reset()
+                .modify(|r, w| w.bits(r.bits() | self.mask_32()))
+        }
+    }
+}
+
+unsafe impl<Tim: ValidTim> TimRegInterface for Tim {
+    fn tim_id(&self) -> u8 {
+        Tim::TIM_ID
+    }
+}
+
+pub(crate) struct TimDynRegister {
+    pub(crate) tim_id: u8,
+    #[allow(dead_code)]
+    pub(crate) pin_id: DynPinId,
+}
+
+unsafe impl TimRegInterface for TimDynRegister {
+    #[inline(always)]
+    fn tim_id(&self) -> u8 {
+        self.tim_id
+    }
+}
+
+//==================================================================================================
+// Timers
+//==================================================================================================
+
+/// Hardware timers
+pub struct CountdownTimer<Tim: ValidTim> {
+    tim: Tim,
+    curr_freq: Hertz,
+    irq_cfg: Option<IrqCfg>,
+    sys_clk: Hertz,
+    rst_val: u32,
+    last_cnt: u32,
+    listening: bool,
+}
+
+#[inline(always)]
+pub fn enable_tim_clk(syscfg: &mut pac::Sysconfig, idx: u8) {
+    syscfg
+        .tim_clk_enable()
+        .modify(|r, w| unsafe { w.bits(r.bits() | (1 << idx)) });
+}
+
+#[inline(always)]
+pub fn disable_tim_clk(syscfg: &mut pac::Sysconfig, idx: u8) {
+    syscfg
+        .tim_clk_enable()
+        .modify(|r, w| unsafe { w.bits(r.bits() & !(1 << idx)) });
+}
+
+unsafe impl<TIM: ValidTim> TimRegInterface for CountdownTimer<TIM> {
+    fn tim_id(&self) -> u8 {
+        TIM::TIM_ID
+    }
+}
+
+impl<Tim: ValidTim> CountdownTimer<Tim> {
+    /// Configures a TIM peripheral as a periodic count down timer
+    pub fn new(syscfg: &mut pac::Sysconfig, sys_clk: impl Into<Hertz>, tim: Tim) -> Self {
+        enable_tim_clk(syscfg, Tim::TIM_ID);
+        let cd_timer = CountdownTimer {
+            tim,
+            sys_clk: sys_clk.into(),
+            irq_cfg: None,
+            rst_val: 0,
+            curr_freq: 0.Hz(),
+            listening: false,
+            last_cnt: 0,
+        };
+        cd_timer
+            .tim
+            .reg_block()
+            .ctrl()
+            .modify(|_, w| w.enable().set_bit());
+        cd_timer
+    }
+
+    /// Listen for events. Depending on the IRQ configuration, this also activates the IRQ in the
+    /// IRQSEL peripheral for the provided interrupt and unmasks the interrupt
+    pub fn listen(
+        &mut self,
+        event: Event,
+        irq_cfg: IrqCfg,
+        irq_sel: Option<&mut pac::Irqsel>,
+        sys_cfg: Option<&mut pac::Sysconfig>,
+    ) {
+        match event {
+            Event::TimeOut => {
+                cortex_m::peripheral::NVIC::mask(irq_cfg.irq);
+                self.irq_cfg = Some(irq_cfg);
+                if irq_cfg.route {
+                    if let Some(sys_cfg) = sys_cfg {
+                        enable_peripheral_clock(sys_cfg, PeripheralClocks::Irqsel);
+                    }
+                    if let Some(irq_sel) = irq_sel {
+                        irq_sel
+                            .tim0(Tim::TIM_ID as usize)
+                            .write(|w| unsafe { w.bits(irq_cfg.irq as u32) });
+                    }
+                }
+                self.listening = true;
+            }
+        }
+    }
+
+    pub fn unlisten(
+        &mut self,
+        event: Event,
+        syscfg: &mut pac::Sysconfig,
+        irqsel: &mut pac::Irqsel,
+    ) {
+        match event {
+            Event::TimeOut => {
+                enable_peripheral_clock(syscfg, PeripheralClocks::Irqsel);
+                irqsel
+                    .tim0(Tim::TIM_ID as usize)
+                    .write(|w| unsafe { w.bits(IRQ_DST_NONE) });
+                self.disable_interrupt();
+                self.listening = false;
+            }
+        }
+    }
+
+    #[inline(always)]
+    pub fn enable_interrupt(&mut self) {
+        self.tim
+            .reg_block()
+            .ctrl()
+            .modify(|_, w| w.irq_enb().set_bit());
+    }
+
+    #[inline(always)]
+    pub fn disable_interrupt(&mut self) {
+        self.tim
+            .reg_block()
+            .ctrl()
+            .modify(|_, w| w.irq_enb().clear_bit());
+    }
+
+    pub fn release(self, syscfg: &mut pac::Sysconfig) -> Tim {
+        self.tim
+            .reg_block()
+            .ctrl()
+            .write(|w| w.enable().clear_bit());
+        syscfg
+            .tim_clk_enable()
+            .modify(|r, w| unsafe { w.bits(r.bits() & !(1 << Tim::TIM_ID)) });
+        self.tim
+    }
+
+    /// Load the count down timer with a timeout but do not start it.
+    pub fn load(&mut self, timeout: impl Into<Hertz>) {
+        self.tim
+            .reg_block()
+            .ctrl()
+            .modify(|_, w| w.enable().clear_bit());
+        self.curr_freq = timeout.into();
+        self.rst_val = self.sys_clk.raw() / self.curr_freq.raw();
+        self.set_reload(self.rst_val);
+        self.set_count(self.rst_val);
+    }
+
+    #[inline(always)]
+    pub fn set_reload(&mut self, val: u32) {
+        self.tim
+            .reg_block()
+            .rst_value()
+            .write(|w| unsafe { w.bits(val) });
+    }
+
+    #[inline(always)]
+    pub fn set_count(&mut self, val: u32) {
+        self.tim
+            .reg_block()
+            .cnt_value()
+            .write(|w| unsafe { w.bits(val) });
+    }
+
+    #[inline(always)]
+    pub fn count(&self) -> u32 {
+        self.tim.reg_block().cnt_value().read().bits()
+    }
+
+    #[inline(always)]
+    pub fn enable(&mut self) {
+        if let Some(irq_cfg) = self.irq_cfg {
+            self.enable_interrupt();
+            if irq_cfg.enable {
+                unsafe { enable_interrupt(irq_cfg.irq) };
+            }
+        }
+        self.tim
+            .reg_block()
+            .enable()
+            .write(|w| unsafe { w.bits(1) });
+    }
+
+    #[inline(always)]
+    pub fn disable(&mut self) {
+        self.tim
+            .reg_block()
+            .enable()
+            .write(|w| unsafe { w.bits(0) });
+    }
+
+    /// Disable the counter, setting both enable and active bit to 0
+    pub fn auto_disable(self, enable: bool) -> Self {
+        if enable {
+            self.tim
+                .reg_block()
+                .ctrl()
+                .modify(|_, w| w.auto_disable().set_bit());
+        } else {
+            self.tim
+                .reg_block()
+                .ctrl()
+                .modify(|_, w| w.auto_disable().clear_bit());
+        }
+        self
+    }
+
+    /// This option only applies when the Auto-Disable functionality is 0.
+    ///
+    /// The active bit is changed to 0 when count reaches 0, but the counter stays
+    /// enabled. When Auto-Disable is 1, Auto-Deactivate is implied
+    pub fn auto_deactivate(self, enable: bool) -> Self {
+        if enable {
+            self.tim
+                .reg_block()
+                .ctrl()
+                .modify(|_, w| w.auto_deactivate().set_bit());
+        } else {
+            self.tim
+                .reg_block()
+                .ctrl()
+                .modify(|_, w| w.auto_deactivate().clear_bit());
+        }
+        self
+    }
+
+    /// Configure the cascade parameters
+    pub fn cascade_control(&mut self, ctrl: CascadeCtrl) {
+        self.tim.reg_block().csd_ctrl().write(|w| {
+            w.csden0().bit(ctrl.enb_start_src_csd0);
+            w.csdinv0().bit(ctrl.inv_csd0);
+            w.csden1().bit(ctrl.enb_start_src_csd1);
+            w.csdinv1().bit(ctrl.inv_csd1);
+            w.dcasop().bit(ctrl.dual_csd_op);
+            w.csdtrg0().bit(ctrl.trg_csd0);
+            w.csdtrg1().bit(ctrl.trg_csd1);
+            w.csden2().bit(ctrl.enb_stop_src_csd2);
+            w.csdinv2().bit(ctrl.inv_csd2);
+            w.csdtrg2().bit(ctrl.trg_csd2)
+        });
+    }
+
+    pub fn cascade_0_source(&mut self, src: CascadeSource) -> Result<(), InvalidCascadeSourceId> {
+        let id = src.id()?;
+        self.tim
+            .reg_block()
+            .cascade0()
+            .write(|w| unsafe { w.cassel().bits(id) });
+        Ok(())
+    }
+
+    pub fn cascade_1_source(&mut self, src: CascadeSource) -> Result<(), InvalidCascadeSourceId> {
+        let id = src.id()?;
+        self.tim
+            .reg_block()
+            .cascade1()
+            .write(|w| unsafe { w.cassel().bits(id) });
+        Ok(())
+    }
+
+    pub fn cascade_2_source(&mut self, src: CascadeSource) -> Result<(), InvalidCascadeSourceId> {
+        let id = src.id()?;
+        self.tim
+            .reg_block()
+            .cascade2()
+            .write(|w| unsafe { w.cassel().bits(id) });
+        Ok(())
+    }
+
+    pub fn curr_freq(&self) -> Hertz {
+        self.curr_freq
+    }
+
+    pub fn listening(&self) -> bool {
+        self.listening
+    }
+}
+
+/// CountDown implementation for TIMx
+impl<TIM: ValidTim> CountdownTimer<TIM> {
+    #[inline]
+    pub fn start<T>(&mut self, timeout: T)
+    where
+        T: Into<Hertz>,
+    {
+        self.load(timeout);
+        self.enable();
+    }
+
+    /// Return `Ok` if the timer has wrapped. Peripheral will automatically clear the
+    /// flag and restart the time if configured correctly
+    pub fn wait(&mut self) -> nb::Result<(), void::Void> {
+        let cnt = self.tim.reg_block().cnt_value().read().bits();
+        if (cnt > self.last_cnt) || cnt == 0 {
+            self.last_cnt = self.rst_val;
+            Ok(())
+        } else {
+            self.last_cnt = cnt;
+            Err(nb::Error::WouldBlock)
+        }
+    }
+
+    /// Returns [false] if the timer was not active, and true otherwise.
+    pub fn cancel(&mut self) -> bool {
+        if !self.tim.reg_block().ctrl().read().enable().bit_is_set() {
+            return false;
+        }
+        self.tim
+            .reg_block()
+            .ctrl()
+            .write(|w| w.enable().clear_bit());
+        true
+    }
+}
+
+impl<TIM: ValidTim> embedded_hal::delay::DelayNs for CountdownTimer<TIM> {
+    fn delay_ns(&mut self, ns: u32) {
+        let ticks = (u64::from(ns)) * (u64::from(self.sys_clk.raw())) / 1_000_000_000;
+
+        let full_cycles = ticks >> 32;
+        let mut last_count;
+        let mut new_count;
+        if full_cycles > 0 {
+            self.set_reload(u32::MAX);
+            self.set_count(u32::MAX);
+            self.enable();
+
+            for _ in 0..full_cycles {
+                // Always ensure that both values are the same at the start.
+                new_count = self.count();
+                last_count = new_count;
+                loop {
+                    new_count = self.count();
+                    if new_count == 0 {
+                        // Wait till timer has wrapped.
+                        while self.count() == 0 {
+                            cortex_m::asm::nop()
+                        }
+                        break;
+                    }
+                    // Timer has definitely wrapped.
+                    if new_count > last_count {
+                        break;
+                    }
+                    last_count = new_count;
+                }
+            }
+        }
+        let ticks = (ticks & u32::MAX as u64) as u32;
+        self.disable();
+        if ticks > 1 {
+            self.set_reload(ticks);
+            self.set_count(ticks);
+            self.enable();
+            last_count = ticks;
+
+            loop {
+                new_count = self.count();
+                if new_count == 0 || (new_count > last_count) {
+                    break;
+                }
+                last_count = new_count;
+            }
+        }
+
+        self.disable();
+    }
+}
+
+// Set up a millisecond timer on TIM0. Please note that the user still has to provide an IRQ handler
+// which should call [default_ms_irq_handler].
+pub fn set_up_ms_tick<TIM: ValidTim>(
+    irq_cfg: IrqCfg,
+    sys_cfg: &mut pac::Sysconfig,
+    irq_sel: Option<&mut pac::Irqsel>,
+    sys_clk: impl Into<Hertz>,
+    tim0: TIM,
+) -> CountdownTimer<TIM> {
+    let mut ms_timer = CountdownTimer::new(sys_cfg, sys_clk, tim0);
+    ms_timer.listen(timer::Event::TimeOut, irq_cfg, irq_sel, Some(sys_cfg));
+    ms_timer.start(1000.Hz());
+    ms_timer
+}
+
+pub fn set_up_ms_delay_provider<TIM: ValidTim>(
+    sys_cfg: &mut pac::Sysconfig,
+    sys_clk: impl Into<Hertz>,
+    tim: TIM,
+) -> CountdownTimer<TIM> {
+    let mut provider = CountdownTimer::new(sys_cfg, sys_clk, tim);
+    provider.start(1000.Hz());
+    provider
+}
+
+/// This function can be called in a specified interrupt handler to increment
+/// the MS counter
+pub fn default_ms_irq_handler() {
+    critical_section::with(|cs| {
+        let mut ms = MS_COUNTER.borrow(cs).get();
+        ms += 1;
+        MS_COUNTER.borrow(cs).set(ms);
+    });
+}
+
+/// Get the current MS tick count
+pub fn get_ms_ticks() -> u32 {
+    critical_section::with(|cs| MS_COUNTER.borrow(cs).get())
+}
+
+//==================================================================================================
+// Delay implementations
+//==================================================================================================
+
+pub struct DelayMs(CountdownTimer<pac::Tim0>);
+
+impl DelayMs {
+    pub fn new(timer: CountdownTimer<pac::Tim0>) -> Option<Self> {
+        if timer.curr_freq() != Hertz::from_raw(1000) || !timer.listening() {
+            return None;
+        }
+        Some(Self(timer))
+    }
+}
+
+/// This assumes that the user has already set up a MS tick timer in TIM0 as a system tick
+/// with [`set_up_ms_delay_provider`]
+impl embedded_hal::delay::DelayNs for DelayMs {
+    fn delay_ns(&mut self, ns: u32) {
+        let ns_as_ms = ns / 1_000_000;
+        if self.0.curr_freq() != Hertz::from_raw(1000) || !self.0.listening() {
+            return;
+        }
+        let start_time = get_ms_ticks();
+        while get_ms_ticks() - start_time < ns_as_ms {
+            cortex_m::asm::nop();
+        }
+    }
+}

va108xx-hal/src/typelevel.rs

@@ -0,0 +1,155 @@
+//! Module supporting type-level programming
+//!
+//! This module is identical to the
+//! [atsamd typelevel](https://docs.rs/atsamd-hal/latest/atsamd_hal/typelevel/index.html).
+
+use core::ops::{Add, Sub};
+
+use typenum::{Add1, Bit, Sub1, UInt, Unsigned, B1, U0};
+
+mod private {
+    /// Super trait used to mark traits with an exhaustive set of
+    /// implementations
+    pub trait Sealed {}
+
+    impl Sealed for u8 {}
+    impl Sealed for i8 {}
+    impl Sealed for u16 {}
+    impl Sealed for i16 {}
+    impl Sealed for u32 {}
+    impl Sealed for i32 {}
+    impl Sealed for f32 {}
+
+    /// Mapping from an instance of a countable type to its successor
+    pub trait Increment {
+        /// Successor type of `Self`
+        type Inc;
+        /// Consume an instance of `Self` and return its successor
+        fn inc(self) -> Self::Inc;
+    }
+
+    /// Mapping from an instance of a countable type to its predecessor
+    pub trait Decrement {
+        /// Predecessor type of `Self`
+        type Dec;
+        /// Consume an instance of `Self` and return its predecessor
+        fn dec(self) -> Self::Dec;
+    }
+}
+
+pub(crate) use private::Decrement as PrivateDecrement;
+pub(crate) use private::Increment as PrivateIncrement;
+pub(crate) use private::Sealed;
+
+/// Type-level version of the [`None`] variant
+#[derive(Default)]
+pub struct NoneT;
+
+impl Sealed for NoneT {}
+
+//==============================================================================
+// Is
+//==============================================================================
+
+/// Marker trait for type identity
+///
+/// This trait is used as part of the [`AnyKind`] trait pattern. It represents
+/// the concept of type identity, because all implementors have
+/// `<Self as Is>::Type == Self`. When used as a trait bound with a specific
+/// type, it guarantees that the corresponding type parameter is exactly the
+/// specific type. Stated differently, it guarantees that `T == Specific` in
+/// the following example.
+///
+/// ```ignore
+/// where T: Is<Type = Specific>
+/// ```
+///
+/// Moreover, the super traits guarantee that any instance of or reference to a
+/// type `T` can be converted into the `Specific` type.
+///
+/// ```ignore
+/// fn example<T>(mut any: T)
+/// where
+///     T: Is<Type = Specific>,
+/// {
+///     let specific_mut: &mut Specific = any.as_mut();
+///     let specific_ref: &Specific = any.as_ref();
+///     let specific: Specific = any.into();
+/// }
+/// ```
+///
+/// [`AnyKind`]: #anykind-trait-pattern
+pub trait Is
+where
+    Self: Sealed,
+    Self: From<IsType<Self>>,
+    Self: Into<IsType<Self>>,
+    Self: AsRef<IsType<Self>>,
+    Self: AsMut<IsType<Self>>,
+{
+    type Type;
+}
+
+/// Type alias for [`Is::Type`]
+pub type IsType<T> = <T as Is>::Type;
+
+impl<T> Is for T
+where
+    T: Sealed + AsRef<T> + AsMut<T>,
+{
+    type Type = T;
+}
+
+//==============================================================================
+// Counting
+//==============================================================================
+
+/// Implement `Sealed` for [`U0`]
+impl Sealed for U0 {}
+
+/// Implement `Sealed` for all type-level, [`Unsigned`] integers *except* [`U0`]
+impl<U: Unsigned, B: Bit> Sealed for UInt<U, B> {}
+
+/// Trait mapping each countable type to its successor
+///
+/// This trait maps each countable type to its corresponding successor type. The
+/// actual implementation of this trait is contained within `PrivateIncrement`.
+/// Access to `PrivateIncrement` is restricted, so that safe HAL APIs can be
+/// built with it.
+pub trait Increment: PrivateIncrement {}
+
+impl<T: PrivateIncrement> Increment for T {}
+
+/// Trait mapping each countable type to its predecessor
+///
+/// This trait maps each countable type to its corresponding predecessor type.
+/// The actual implementation of this trait is contained within
+/// `PrivateDecrement`. Access to `PrivateDecrement` is restricted, so that safe
+/// HAL APIs can be built with it.
+pub trait Decrement: PrivateDecrement {}
+
+impl<T: PrivateDecrement> Decrement for T {}
+
+impl<N> PrivateIncrement for N
+where
+    N: Unsigned + Add<B1>,
+    Add1<N>: Unsigned,
+{
+    type Inc = Add1<N>;
+    #[inline]
+    fn inc(self) -> Self::Inc {
+        Self::Inc::default()
+    }
+}
+
+impl<N> PrivateDecrement for N
+where
+    N: Unsigned + Sub<B1>,
+    Sub1<N>: Unsigned,
+{
+    type Dec = Sub1<N>;
+    #[inline]
+    fn dec(self) -> Self::Dec {
+        Self::Dec::default()
+    }
+}

va108xx-hal/src/uart/mod.rs

@@ -1,17 +0,0 @@
-//! # API for the UART peripheral
-//!
-//! The core of this API are the [Uart], [Rx] and [Tx] structures.
-//! The RX structure also has a dedicated [RxWithInterrupt] variant which allows reading the receiver
-//! using interrupts.
-//!
-//! The [rx_asynch] and [tx_asynch] modules provide an asynchronous non-blocking API for the UART
-//! peripheral.
-//!
-//! ## Examples
-//!
-//! - [UART simple example](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/examples/simple/examples/uart.rs)
-//! - [UART with IRQ and RTIC](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/examples/rtic/src/bin/uart-echo-rtic.rs)
-//! - [Flashloader exposing a CCSDS interface via UART](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/flashloader)
-//! - [Async UART RX example](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/examples/embassy/src/bin/async-uart-rx.rs)
-//! - [Async UART TX example](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/examples/embassy/src/bin/async-uart-tx.rs)
-pub use vorago_shared_periphs::uart::*;

va108xx/CHANGELOG.md

@@ -8,14 +8,6 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ## [unreleased]
 
-## [v0.5.0] 2025-02-17
-
-- Re-generated PAC with `svd2rust` v0.35.0 and added optional `defmt` and `Debug` implementations
-
-## [v0.4.0] 2025-02-12
-
-- Re-generated PAC with `svd2rust` v0.35.0
-
 ## [v0.3.0] 2024-06-16
 
 - Re-generated PAC with `svd2rust` v0.33.3

va108xx/Cargo.toml

@@ -1,6 +1,6 @@
 [package]
 name = "va108xx"
-version = "0.5.0"
+version = "0.3.0"
 authors = ["Robin Mueller <muellerr@irs.uni-stuttgart.de>"]
 edition = "2021"
 description = "PAC for the Vorago VA108xx family of microcontrollers"
@@ -13,7 +13,6 @@ categories = ["embedded", "no-std", "hardware-support"]
 [dependencies]
 cortex-m = "0.7"
 vcell = "0.1.3"
-defmt = { version = "1", optional = true }
 critical-section = { version = "1", optional = true }
 
 [dependencies.cortex-m-rt]
@@ -22,8 +21,6 @@ version = ">=0.6.15,<0.8"
 
 [features]
 rt = ["cortex-m-rt/device"]
-# Adds Debug implementation
-debug = []
 
 [package.metadata.docs.rs]
 all-features = true

va108xx/README.md

@@ -24,13 +24,7 @@ features = ["rt"]
 The `rt` feature is optional and recommended. It brings in support for `cortex-m-rt`.
 
 For full details on the autgenerated API, please see the
-[svd2rust documentation](https://docs.rs/svd2rust/latest/svd2rust/#peripheral-api).
+[svd2rust documentation](https://docs.rs/svd2rust/0.19.0/svd2rust/#peripheral-api).
-
-## Optional Features
-
-- [`defmt`](https://defmt.ferrous-systems.com/): Add support for `defmt` by adding the
-  [`defmt::Format`](https://defmt.ferrous-systems.com/format) derive on many types.
-- `debug`: Add `Debug` derives for various structures
 
 ## Regenerating the PAC
 

va108xx/gen-helper.sh

@@ -1,4 +1,4 @@
-#!/bin/bash
+#!/bin/sh
 
 # Use installed tool by default
 svd2rust_bin="svd2rust"
@@ -30,7 +30,7 @@ fi
 
 svdtools patch svd/va108xx-patch.yml
 # See https://github.com/rust-embedded/svd2rust/issues/830 for required re-export.
-${svd2rust_bin} --reexport-interrupt --impl-defmt defmt --impl-debug-feature debug -i svd/va108xx.svd.patched
+${svd2rust_bin} --reexport-interrupt -i svd/va108xx.svd.patched
 
 result=$?
 if [ $result -ne 0 ]; then

va108xx/src/generic.rs

@@ -82,6 +82,169 @@ pub trait Resettable: RegisterSpec {
         Self::RESET_VALUE
     }
 }
+#[doc = " This structure provides volatile access to registers."]
+#[repr(transparent)]
+pub struct Reg<REG: RegisterSpec> {
+    register: vcell::VolatileCell<REG::Ux>,
+    _marker: marker::PhantomData<REG>,
+}
+unsafe impl<REG: RegisterSpec> Send for Reg<REG> where REG::Ux: Send {}
+impl<REG: RegisterSpec> Reg<REG> {
+    #[doc = " Returns the underlying memory address of register."]
+    #[doc = ""]
+    #[doc = " ```ignore"]
+    #[doc = " let reg_ptr = periph.reg.as_ptr();"]
+    #[doc = " ```"]
+    #[inline(always)]
+    pub fn as_ptr(&self) -> *mut REG::Ux {
+        self.register.as_ptr()
+    }
+}
+impl<REG: Readable> Reg<REG> {
+    #[doc = " Reads the contents of a `Readable` register."]
+    #[doc = ""]
+    #[doc = " You can read the raw contents of a register by using `bits`:"]
+    #[doc = " ```ignore"]
+    #[doc = " let bits = periph.reg.read().bits();"]
+    #[doc = " ```"]
+    #[doc = " or get the content of a particular field of a register:"]
+    #[doc = " ```ignore"]
+    #[doc = " let reader = periph.reg.read();"]
+    #[doc = " let bits = reader.field1().bits();"]
+    #[doc = " let flag = reader.field2().bit_is_set();"]
+    #[doc = " ```"]
+    #[inline(always)]
+    pub fn read(&self) -> R<REG> {
+        R {
+            bits: self.register.get(),
+            _reg: marker::PhantomData,
+        }
+    }
+}
+impl<REG: Resettable + Writable> Reg<REG> {
+    #[doc = " Writes the reset value to `Writable` register."]
+    #[doc = ""]
+    #[doc = " Resets the register to its initial state."]
+    #[inline(always)]
+    pub fn reset(&self) {
+        self.register.set(REG::RESET_VALUE)
+    }
+    #[doc = " Writes bits to a `Writable` register."]
+    #[doc = ""]
+    #[doc = " You can write raw bits into a register:"]
+    #[doc = " ```ignore"]
+    #[doc = " periph.reg.write(|w| unsafe { w.bits(rawbits) });"]
+    #[doc = " ```"]
+    #[doc = " or write only the fields you need:"]
+    #[doc = " ```ignore"]
+    #[doc = " periph.reg.write(|w| w"]
+    #[doc = "     .field1().bits(newfield1bits)"]
+    #[doc = "     .field2().set_bit()"]
+    #[doc = "     .field3().variant(VARIANT)"]
+    #[doc = " );"]
+    #[doc = " ```"]
+    #[doc = " or an alternative way of saying the same:"]
+    #[doc = " ```ignore"]
+    #[doc = " periph.reg.write(|w| {"]
+    #[doc = "     w.field1().bits(newfield1bits);"]
+    #[doc = "     w.field2().set_bit();"]
+    #[doc = "     w.field3().variant(VARIANT)"]
+    #[doc = " });"]
+    #[doc = " ```"]
+    #[doc = " In the latter case, other fields will be set to their reset value."]
+    #[inline(always)]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W<REG>) -> &mut W<REG>,
+    {
+        self.register.set(
+            f(&mut W {
+                bits: REG::RESET_VALUE & !REG::ONE_TO_MODIFY_FIELDS_BITMAP
+                    | REG::ZERO_TO_MODIFY_FIELDS_BITMAP,
+                _reg: marker::PhantomData,
+            })
+            .bits,
+        );
+    }
+}
+impl<REG: Writable> Reg<REG> {
+    #[doc = " Writes 0 to a `Writable` register."]
+    #[doc = ""]
+    #[doc = " Similar to `write`, but unused bits will contain 0."]
+    #[doc = ""]
+    #[doc = " # Safety"]
+    #[doc = ""]
+    #[doc = " Unsafe to use with registers which don't allow to write 0."]
+    #[inline(always)]
+    pub unsafe fn write_with_zero<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W<REG>) -> &mut W<REG>,
+    {
+        self.register.set(
+            f(&mut W {
+                bits: REG::Ux::default(),
+                _reg: marker::PhantomData,
+            })
+            .bits,
+        );
+    }
+}
+impl<REG: Readable + Writable> Reg<REG> {
+    #[doc = " Modifies the contents of the register by reading and then writing it."]
+    #[doc = ""]
+    #[doc = " E.g. to do a read-modify-write sequence to change parts of a register:"]
+    #[doc = " ```ignore"]
+    #[doc = " periph.reg.modify(|r, w| unsafe { w.bits("]
+    #[doc = "    r.bits() | 3"]
+    #[doc = " ) });"]
+    #[doc = " ```"]
+    #[doc = " or"]
+    #[doc = " ```ignore"]
+    #[doc = " periph.reg.modify(|_, w| w"]
+    #[doc = "     .field1().bits(newfield1bits)"]
+    #[doc = "     .field2().set_bit()"]
+    #[doc = "     .field3().variant(VARIANT)"]
+    #[doc = " );"]
+    #[doc = " ```"]
+    #[doc = " or an alternative way of saying the same:"]
+    #[doc = " ```ignore"]
+    #[doc = " periph.reg.modify(|_, w| {"]
+    #[doc = "     w.field1().bits(newfield1bits);"]
+    #[doc = "     w.field2().set_bit();"]
+    #[doc = "     w.field3().variant(VARIANT)"]
+    #[doc = " });"]
+    #[doc = " ```"]
+    #[doc = " Other fields will have the value they had before the call to `modify`."]
+    #[inline(always)]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R<REG>, &'w mut W<REG>) -> &'w mut W<REG>,
+    {
+        let bits = self.register.get();
+        self.register.set(
+            f(
+                &R {
+                    bits,
+                    _reg: marker::PhantomData,
+                },
+                &mut W {
+                    bits: bits & !REG::ONE_TO_MODIFY_FIELDS_BITMAP
+                        | REG::ZERO_TO_MODIFY_FIELDS_BITMAP,
+                    _reg: marker::PhantomData,
+                },
+            )
+            .bits,
+        );
+    }
+}
+impl<REG: Readable> core::fmt::Debug for crate::generic::Reg<REG>
+where
+    R<REG>: core::fmt::Debug,
+{
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        core::fmt::Debug::fmt(&self.read(), f)
+    }
+}
 #[doc(hidden)]
 pub mod raw;
 #[doc = " Register reader."]
@@ -206,7 +369,7 @@ pub struct RangeTo<const MAX: u64>;
 #[doc = " Write field Proxy"]
 pub type FieldWriter<'a, REG, const WI: u8, FI = u8, Safety = Unsafe> =
     raw::FieldWriter<'a, REG, WI, FI, Safety>;
-impl<REG, const WI: u8, FI, Safety> FieldWriter<'_, REG, WI, FI, Safety>
+impl<'a, REG, const WI: u8, FI, Safety> FieldWriter<'a, REG, WI, FI, Safety>
 where
     REG: Writable + RegisterSpec,
     FI: FieldSpec,
@@ -453,278 +616,3 @@ where
         self.w
     }
 }
-#[doc = " This structure provides volatile access to registers."]
-#[repr(transparent)]
-pub struct Reg<REG: RegisterSpec> {
-    register: vcell::VolatileCell<REG::Ux>,
-    _marker: marker::PhantomData<REG>,
-}
-unsafe impl<REG: RegisterSpec> Send for Reg<REG> where REG::Ux: Send {}
-impl<REG: RegisterSpec> Reg<REG> {
-    #[doc = " Returns the underlying memory address of register."]
-    #[doc = ""]
-    #[doc = " ```ignore"]
-    #[doc = " let reg_ptr = periph.reg.as_ptr();"]
-    #[doc = " ```"]
-    #[inline(always)]
-    pub fn as_ptr(&self) -> *mut REG::Ux {
-        self.register.as_ptr()
-    }
-}
-impl<REG: Readable> Reg<REG> {
-    #[doc = " Reads the contents of a `Readable` register."]
-    #[doc = ""]
-    #[doc = " You can read the raw contents of a register by using `bits`:"]
-    #[doc = " ```ignore"]
-    #[doc = " let bits = periph.reg.read().bits();"]
-    #[doc = " ```"]
-    #[doc = " or get the content of a particular field of a register:"]
-    #[doc = " ```ignore"]
-    #[doc = " let reader = periph.reg.read();"]
-    #[doc = " let bits = reader.field1().bits();"]
-    #[doc = " let flag = reader.field2().bit_is_set();"]
-    #[doc = " ```"]
-    #[inline(always)]
-    pub fn read(&self) -> R<REG> {
-        R {
-            bits: self.register.get(),
-            _reg: marker::PhantomData,
-        }
-    }
-}
-impl<REG: Resettable + Writable> Reg<REG> {
-    #[doc = " Writes the reset value to `Writable` register."]
-    #[doc = ""]
-    #[doc = " Resets the register to its initial state."]
-    #[inline(always)]
-    pub fn reset(&self) {
-        self.register.set(REG::RESET_VALUE)
-    }
-    #[doc = " Writes bits to a `Writable` register."]
-    #[doc = ""]
-    #[doc = " You can write raw bits into a register:"]
-    #[doc = " ```ignore"]
-    #[doc = " periph.reg.write(|w| unsafe { w.bits(rawbits) });"]
-    #[doc = " ```"]
-    #[doc = " or write only the fields you need:"]
-    #[doc = " ```ignore"]
-    #[doc = " periph.reg.write(|w| w"]
-    #[doc = "     .field1().bits(newfield1bits)"]
-    #[doc = "     .field2().set_bit()"]
-    #[doc = "     .field3().variant(VARIANT)"]
-    #[doc = " );"]
-    #[doc = " ```"]
-    #[doc = " or an alternative way of saying the same:"]
-    #[doc = " ```ignore"]
-    #[doc = " periph.reg.write(|w| {"]
-    #[doc = "     w.field1().bits(newfield1bits);"]
-    #[doc = "     w.field2().set_bit();"]
-    #[doc = "     w.field3().variant(VARIANT)"]
-    #[doc = " });"]
-    #[doc = " ```"]
-    #[doc = " In the latter case, other fields will be set to their reset value."]
-    #[inline(always)]
-    pub fn write<F>(&self, f: F) -> REG::Ux
-    where
-        F: FnOnce(&mut W<REG>) -> &mut W<REG>,
-    {
-        let value = f(&mut W {
-            bits: REG::RESET_VALUE & !REG::ONE_TO_MODIFY_FIELDS_BITMAP
-                | REG::ZERO_TO_MODIFY_FIELDS_BITMAP,
-            _reg: marker::PhantomData,
-        })
-        .bits;
-        self.register.set(value);
-        value
-    }
-    #[doc = " Writes bits to a `Writable` register and produce a value."]
-    #[doc = ""]
-    #[doc = " You can write raw bits into a register:"]
-    #[doc = " ```ignore"]
-    #[doc = " periph.reg.write_and(|w| unsafe { w.bits(rawbits); });"]
-    #[doc = " ```"]
-    #[doc = " or write only the fields you need:"]
-    #[doc = " ```ignore"]
-    #[doc = " periph.reg.write_and(|w| {"]
-    #[doc = "     w.field1().bits(newfield1bits)"]
-    #[doc = "         .field2().set_bit()"]
-    #[doc = "         .field3().variant(VARIANT);"]
-    #[doc = " });"]
-    #[doc = " ```"]
-    #[doc = " or an alternative way of saying the same:"]
-    #[doc = " ```ignore"]
-    #[doc = " periph.reg.write_and(|w| {"]
-    #[doc = "     w.field1().bits(newfield1bits);"]
-    #[doc = "     w.field2().set_bit();"]
-    #[doc = "     w.field3().variant(VARIANT);"]
-    #[doc = " });"]
-    #[doc = " ```"]
-    #[doc = " In the latter case, other fields will be set to their reset value."]
-    #[doc = ""]
-    #[doc = " Values can be returned from the closure:"]
-    #[doc = " ```ignore"]
-    #[doc = " let state = periph.reg.write_and(|w| State::set(w.field1()));"]
-    #[doc = " ```"]
-    #[inline(always)]
-    pub fn from_write<F, T>(&self, f: F) -> T
-    where
-        F: FnOnce(&mut W<REG>) -> T,
-    {
-        let mut writer = W {
-            bits: REG::RESET_VALUE & !REG::ONE_TO_MODIFY_FIELDS_BITMAP
-                | REG::ZERO_TO_MODIFY_FIELDS_BITMAP,
-            _reg: marker::PhantomData,
-        };
-        let result = f(&mut writer);
-        self.register.set(writer.bits);
-        result
-    }
-}
-impl<REG: Writable> Reg<REG> {
-    #[doc = " Writes 0 to a `Writable` register."]
-    #[doc = ""]
-    #[doc = " Similar to `write`, but unused bits will contain 0."]
-    #[doc = ""]
-    #[doc = " # Safety"]
-    #[doc = ""]
-    #[doc = " Unsafe to use with registers which don't allow to write 0."]
-    #[inline(always)]
-    pub unsafe fn write_with_zero<F>(&self, f: F) -> REG::Ux
-    where
-        F: FnOnce(&mut W<REG>) -> &mut W<REG>,
-    {
-        let value = f(&mut W {
-            bits: REG::Ux::default(),
-            _reg: marker::PhantomData,
-        })
-        .bits;
-        self.register.set(value);
-        value
-    }
-    #[doc = " Writes 0 to a `Writable` register and produces a value."]
-    #[doc = ""]
-    #[doc = " Similar to `write`, but unused bits will contain 0."]
-    #[doc = ""]
-    #[doc = " # Safety"]
-    #[doc = ""]
-    #[doc = " Unsafe to use with registers which don't allow to write 0."]
-    #[inline(always)]
-    pub unsafe fn from_write_with_zero<F, T>(&self, f: F) -> T
-    where
-        F: FnOnce(&mut W<REG>) -> T,
-    {
-        let mut writer = W {
-            bits: REG::Ux::default(),
-            _reg: marker::PhantomData,
-        };
-        let result = f(&mut writer);
-        self.register.set(writer.bits);
-        result
-    }
-}
-impl<REG: Readable + Writable> Reg<REG> {
-    #[doc = " Modifies the contents of the register by reading and then writing it."]
-    #[doc = ""]
-    #[doc = " E.g. to do a read-modify-write sequence to change parts of a register:"]
-    #[doc = " ```ignore"]
-    #[doc = " periph.reg.modify(|r, w| unsafe { w.bits("]
-    #[doc = "    r.bits() | 3"]
-    #[doc = " ) });"]
-    #[doc = " ```"]
-    #[doc = " or"]
-    #[doc = " ```ignore"]
-    #[doc = " periph.reg.modify(|_, w| w"]
-    #[doc = "     .field1().bits(newfield1bits)"]
-    #[doc = "     .field2().set_bit()"]
-    #[doc = "     .field3().variant(VARIANT)"]
-    #[doc = " );"]
-    #[doc = " ```"]
-    #[doc = " or an alternative way of saying the same:"]
-    #[doc = " ```ignore"]
-    #[doc = " periph.reg.modify(|_, w| {"]
-    #[doc = "     w.field1().bits(newfield1bits);"]
-    #[doc = "     w.field2().set_bit();"]
-    #[doc = "     w.field3().variant(VARIANT)"]
-    #[doc = " });"]
-    #[doc = " ```"]
-    #[doc = " Other fields will have the value they had before the call to `modify`."]
-    #[inline(always)]
-    pub fn modify<F>(&self, f: F) -> REG::Ux
-    where
-        for<'w> F: FnOnce(&R<REG>, &'w mut W<REG>) -> &'w mut W<REG>,
-    {
-        let bits = self.register.get();
-        let value = f(
-            &R {
-                bits,
-                _reg: marker::PhantomData,
-            },
-            &mut W {
-                bits: bits & !REG::ONE_TO_MODIFY_FIELDS_BITMAP | REG::ZERO_TO_MODIFY_FIELDS_BITMAP,
-                _reg: marker::PhantomData,
-            },
-        )
-        .bits;
-        self.register.set(value);
-        value
-    }
-    #[doc = " Modifies the contents of the register by reading and then writing it"]
-    #[doc = " and produces a value."]
-    #[doc = ""]
-    #[doc = " E.g. to do a read-modify-write sequence to change parts of a register:"]
-    #[doc = " ```ignore"]
-    #[doc = " let bits = periph.reg.modify(|r, w| {"]
-    #[doc = "     let new_bits = r.bits() | 3;"]
-    #[doc = "     unsafe {"]
-    #[doc = "         w.bits(new_bits);"]
-    #[doc = "     }"]
-    #[doc = ""]
-    #[doc = "     new_bits"]
-    #[doc = " });"]
-    #[doc = " ```"]
-    #[doc = " or"]
-    #[doc = " ```ignore"]
-    #[doc = " periph.reg.modify(|_, w| {"]
-    #[doc = "     w.field1().bits(newfield1bits)"]
-    #[doc = "         .field2().set_bit()"]
-    #[doc = "         .field3().variant(VARIANT);"]
-    #[doc = " });"]
-    #[doc = " ```"]
-    #[doc = " or an alternative way of saying the same:"]
-    #[doc = " ```ignore"]
-    #[doc = " periph.reg.modify(|_, w| {"]
-    #[doc = "     w.field1().bits(newfield1bits);"]
-    #[doc = "     w.field2().set_bit();"]
-    #[doc = "     w.field3().variant(VARIANT);"]
-    #[doc = " });"]
-    #[doc = " ```"]
-    #[doc = " Other fields will have the value they had before the call to `modify`."]
-    #[inline(always)]
-    pub fn from_modify<F, T>(&self, f: F) -> T
-    where
-        for<'w> F: FnOnce(&R<REG>, &'w mut W<REG>) -> T,
-    {
-        let bits = self.register.get();
-        let mut writer = W {
-            bits: bits & !REG::ONE_TO_MODIFY_FIELDS_BITMAP | REG::ZERO_TO_MODIFY_FIELDS_BITMAP,
-            _reg: marker::PhantomData,
-        };
-        let result = f(
-            &R {
-                bits,
-                _reg: marker::PhantomData,
-            },
-            &mut writer,
-        );
-        self.register.set(writer.bits);
-        result
-    }
-}
-impl<REG: Readable> core::fmt::Debug for crate::generic::Reg<REG>
-where
-    R<REG>: core::fmt::Debug,
-{
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}

va108xx/src/generic/raw.rs

@@ -41,7 +41,6 @@ impl<FI> BitReader<FI> {
         }
     }
 }
-#[must_use = "after creating `FieldWriter` you need to call field value setting method"]
 pub struct FieldWriter<'a, REG, const WI: u8, FI = u8, Safety = Unsafe>
 where
     REG: Writable + RegisterSpec,
@@ -67,7 +66,6 @@ where
         }
     }
 }
-#[must_use = "after creating `BitWriter` you need to call bit setting method"]
 pub struct BitWriter<'a, REG, FI = bool, M = BitM>
 where
     REG: Writable + RegisterSpec,

va108xx/src/i2ca.rs

@@ -240,67 +240,67 @@ impl RegisterBlock {
         &self.perid
     }
 }
-#[doc = "CTRL (rw) register accessor: Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl`]
+#[doc = "CTRL (rw) register accessor: Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl`]
 module"]
 #[doc(alias = "CTRL")]
 pub type Ctrl = crate::Reg<ctrl::CtrlSpec>;
 #[doc = "Control Register"]
 pub mod ctrl;
-#[doc = "CLKSCALE (rw) register accessor: Clock Scale divide value\n\nYou can [`read`](crate::Reg::read) this register and get [`clkscale::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clkscale::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clkscale`]
+#[doc = "CLKSCALE (rw) register accessor: Clock Scale divide value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkscale::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkscale::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clkscale`]
 module"]
 #[doc(alias = "CLKSCALE")]
 pub type Clkscale = crate::Reg<clkscale::ClkscaleSpec>;
 #[doc = "Clock Scale divide value"]
 pub mod clkscale;
-#[doc = "WORDS (rw) register accessor: Word Count value\n\nYou can [`read`](crate::Reg::read) this register and get [`words::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`words::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@words`]
+#[doc = "WORDS (rw) register accessor: Word Count value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`words::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`words::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@words`]
 module"]
 #[doc(alias = "WORDS")]
 pub type Words = crate::Reg<words::WordsSpec>;
 #[doc = "Word Count value"]
 pub mod words;
-#[doc = "ADDRESS (rw) register accessor: I2C Address value\n\nYou can [`read`](crate::Reg::read) this register and get [`address::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`address::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@address`]
+#[doc = "ADDRESS (rw) register accessor: I2C Address value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`address::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`address::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@address`]
 module"]
 #[doc(alias = "ADDRESS")]
 pub type Address = crate::Reg<address::AddressSpec>;
 #[doc = "I2C Address value"]
 pub mod address;
-#[doc = "DATA (rw) register accessor: Data Input/Output\n\nYou can [`read`](crate::Reg::read) this register and get [`data::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data`]
+#[doc = "DATA (rw) register accessor: Data Input/Output\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data`]
 module"]
 #[doc(alias = "DATA")]
 pub type Data = crate::Reg<data::DataSpec>;
 #[doc = "Data Input/Output"]
 pub mod data;
-#[doc = "CMD (rw) register accessor: Command Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cmd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmd`]
+#[doc = "CMD (rw) register accessor: Command Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmd::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmd`]
 module"]
 #[doc(alias = "CMD")]
 pub type Cmd = crate::Reg<cmd::CmdSpec>;
 #[doc = "Command Register"]
 pub mod cmd;
-#[doc = "STATUS (r) register accessor: I2C Controller Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status`]
+#[doc = "STATUS (r) register accessor: I2C Controller Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status`]
 module"]
 #[doc(alias = "STATUS")]
 pub type Status = crate::Reg<status::StatusSpec>;
 #[doc = "I2C Controller Status Register"]
 pub mod status;
-#[doc = "STATE (r) register accessor: Internal STATE of I2C Master Controller\n\nYou can [`read`](crate::Reg::read) this register and get [`state::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@state`]
+#[doc = "STATE (r) register accessor: Internal STATE of I2C Master Controller\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`state::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@state`]
 module"]
 #[doc(alias = "STATE")]
 pub type State = crate::Reg<state::StateSpec>;
 #[doc = "Internal STATE of I2C Master Controller"]
 pub mod state;
-#[doc = "TXCOUNT (r) register accessor: TX Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`txcount::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txcount`]
+#[doc = "TXCOUNT (r) register accessor: TX Count Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txcount::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txcount`]
 module"]
 #[doc(alias = "TXCOUNT")]
 pub type Txcount = crate::Reg<txcount::TxcountSpec>;
 #[doc = "TX Count Register"]
 pub mod txcount;
-#[doc = "RXCOUNT (r) register accessor: RX Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`rxcount::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxcount`]
+#[doc = "RXCOUNT (r) register accessor: RX Count Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxcount::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxcount`]
 module"]
 #[doc(alias = "RXCOUNT")]
 pub type Rxcount = crate::Reg<rxcount::RxcountSpec>;
 #[doc = "RX Count Register"]
 pub mod rxcount;
-#[doc = "IRQ_ENB (rw) register accessor: Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_enb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_enb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_enb`]
+#[doc = "IRQ_ENB (rw) register accessor: Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_enb::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_enb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_enb`]
 module"]
 #[doc(alias = "IRQ_ENB")]
 pub type IrqEnb = crate::Reg<irq_enb::IrqEnbSpec>;
@@ -312,97 +312,97 @@ pub use irq_enb as irq_clr;
 pub use IrqEnb as IrqRaw;
 pub use IrqEnb as IrqEnd;
 pub use IrqEnb as IrqClr;
-#[doc = "RXFIFOIRQTRG (rw) register accessor: Rx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`rxfifoirqtrg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rxfifoirqtrg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxfifoirqtrg`]
+#[doc = "RXFIFOIRQTRG (rw) register accessor: Rx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxfifoirqtrg::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxfifoirqtrg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxfifoirqtrg`]
 module"]
 #[doc(alias = "RXFIFOIRQTRG")]
 pub type Rxfifoirqtrg = crate::Reg<rxfifoirqtrg::RxfifoirqtrgSpec>;
 #[doc = "Rx FIFO IRQ Trigger Level"]
 pub mod rxfifoirqtrg;
-#[doc = "TXFIFOIRQTRG (rw) register accessor: Tx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`txfifoirqtrg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`txfifoirqtrg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txfifoirqtrg`]
+#[doc = "TXFIFOIRQTRG (rw) register accessor: Tx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txfifoirqtrg::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txfifoirqtrg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txfifoirqtrg`]
 module"]
 #[doc(alias = "TXFIFOIRQTRG")]
 pub type Txfifoirqtrg = crate::Reg<txfifoirqtrg::TxfifoirqtrgSpec>;
 #[doc = "Tx FIFO IRQ Trigger Level"]
 pub mod txfifoirqtrg;
-#[doc = "FIFO_CLR (w) register accessor: Clear FIFO Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifo_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifo_clr`]
+#[doc = "FIFO_CLR (w) register accessor: Clear FIFO Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifo_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifo_clr`]
 module"]
 #[doc(alias = "FIFO_CLR")]
 pub type FifoClr = crate::Reg<fifo_clr::FifoClrSpec>;
 #[doc = "Clear FIFO Register"]
 pub mod fifo_clr;
-#[doc = "TMCONFIG (rw) register accessor: Timing Config Register\n\nYou can [`read`](crate::Reg::read) this register and get [`tmconfig::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tmconfig::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tmconfig`]
+#[doc = "TMCONFIG (rw) register accessor: Timing Config Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tmconfig::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tmconfig::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tmconfig`]
 module"]
 #[doc(alias = "TMCONFIG")]
 pub type Tmconfig = crate::Reg<tmconfig::TmconfigSpec>;
 #[doc = "Timing Config Register"]
 pub mod tmconfig;
-#[doc = "CLKTOLIMIT (rw) register accessor: Clock Low Timeout Limit Register\n\nYou can [`read`](crate::Reg::read) this register and get [`clktolimit::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clktolimit::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clktolimit`]
+#[doc = "CLKTOLIMIT (rw) register accessor: Clock Low Timeout Limit Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clktolimit::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clktolimit::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clktolimit`]
 module"]
 #[doc(alias = "CLKTOLIMIT")]
 pub type Clktolimit = crate::Reg<clktolimit::ClktolimitSpec>;
 #[doc = "Clock Low Timeout Limit Register"]
 pub mod clktolimit;
-#[doc = "S0_CTRL (rw) register accessor: Slave Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_ctrl`]
+#[doc = "S0_CTRL (rw) register accessor: Slave Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_ctrl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_ctrl`]
 module"]
 #[doc(alias = "S0_CTRL")]
 pub type S0Ctrl = crate::Reg<s0_ctrl::S0CtrlSpec>;
 #[doc = "Slave Control Register"]
 pub mod s0_ctrl;
-#[doc = "S0_MAXWORDS (rw) register accessor: Slave MaxWords Register\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_maxwords::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_maxwords::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_maxwords`]
+#[doc = "S0_MAXWORDS (rw) register accessor: Slave MaxWords Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_maxwords::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_maxwords::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_maxwords`]
 module"]
 #[doc(alias = "S0_MAXWORDS")]
 pub type S0Maxwords = crate::Reg<s0_maxwords::S0MaxwordsSpec>;
 #[doc = "Slave MaxWords Register"]
 pub mod s0_maxwords;
-#[doc = "S0_ADDRESS (rw) register accessor: Slave I2C Address Value\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_address::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_address::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_address`]
+#[doc = "S0_ADDRESS (rw) register accessor: Slave I2C Address Value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_address::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_address::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_address`]
 module"]
 #[doc(alias = "S0_ADDRESS")]
 pub type S0Address = crate::Reg<s0_address::S0AddressSpec>;
 #[doc = "Slave I2C Address Value"]
 pub mod s0_address;
-#[doc = "S0_ADDRESSMASK (rw) register accessor: Slave I2C Address Mask value\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_addressmask::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_addressmask::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_addressmask`]
+#[doc = "S0_ADDRESSMASK (rw) register accessor: Slave I2C Address Mask value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_addressmask::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_addressmask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_addressmask`]
 module"]
 #[doc(alias = "S0_ADDRESSMASK")]
 pub type S0Addressmask = crate::Reg<s0_addressmask::S0AddressmaskSpec>;
 #[doc = "Slave I2C Address Mask value"]
 pub mod s0_addressmask;
-#[doc = "S0_DATA (rw) register accessor: Slave Data Input/Output\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_data::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_data::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_data`]
+#[doc = "S0_DATA (rw) register accessor: Slave Data Input/Output\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_data::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_data::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_data`]
 module"]
 #[doc(alias = "S0_DATA")]
 pub type S0Data = crate::Reg<s0_data::S0DataSpec>;
 #[doc = "Slave Data Input/Output"]
 pub mod s0_data;
-#[doc = "S0_LASTADDRESS (r) register accessor: Slave I2C Last Address value\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_lastaddress::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_lastaddress`]
+#[doc = "S0_LASTADDRESS (r) register accessor: Slave I2C Last Address value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_lastaddress::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_lastaddress`]
 module"]
 #[doc(alias = "S0_LASTADDRESS")]
 pub type S0Lastaddress = crate::Reg<s0_lastaddress::S0LastaddressSpec>;
 #[doc = "Slave I2C Last Address value"]
 pub mod s0_lastaddress;
-#[doc = "S0_STATUS (r) register accessor: Slave I2C Controller Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_status`]
+#[doc = "S0_STATUS (r) register accessor: Slave I2C Controller Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_status::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_status`]
 module"]
 #[doc(alias = "S0_STATUS")]
 pub type S0Status = crate::Reg<s0_status::S0StatusSpec>;
 #[doc = "Slave I2C Controller Status Register"]
 pub mod s0_status;
-#[doc = "S0_STATE (r) register accessor: Internal STATE of I2C Slave Controller\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_state::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_state`]
+#[doc = "S0_STATE (r) register accessor: Internal STATE of I2C Slave Controller\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_state::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_state`]
 module"]
 #[doc(alias = "S0_STATE")]
 pub type S0State = crate::Reg<s0_state::S0StateSpec>;
 #[doc = "Internal STATE of I2C Slave Controller"]
 pub mod s0_state;
-#[doc = "S0_TXCOUNT (r) register accessor: Slave TX Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_txcount::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_txcount`]
+#[doc = "S0_TXCOUNT (r) register accessor: Slave TX Count Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_txcount::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_txcount`]
 module"]
 #[doc(alias = "S0_TXCOUNT")]
 pub type S0Txcount = crate::Reg<s0_txcount::S0TxcountSpec>;
 #[doc = "Slave TX Count Register"]
 pub mod s0_txcount;
-#[doc = "S0_RXCOUNT (r) register accessor: Slave RX Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_rxcount::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_rxcount`]
+#[doc = "S0_RXCOUNT (r) register accessor: Slave RX Count Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_rxcount::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_rxcount`]
 module"]
 #[doc(alias = "S0_RXCOUNT")]
 pub type S0Rxcount = crate::Reg<s0_rxcount::S0RxcountSpec>;
 #[doc = "Slave RX Count Register"]
 pub mod s0_rxcount;
-#[doc = "S0_IRQ_ENB (rw) register accessor: Slave Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_irq_enb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_irq_enb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_irq_enb`]
+#[doc = "S0_IRQ_ENB (rw) register accessor: Slave Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_irq_enb::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_irq_enb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_irq_enb`]
 module"]
 #[doc(alias = "S0_IRQ_ENB")]
 pub type S0IrqEnb = crate::Reg<s0_irq_enb::S0IrqEnbSpec>;
@@ -414,37 +414,37 @@ pub use s0_irq_enb as s0_irq_clr;
 pub use S0IrqEnb as S0IrqRaw;
 pub use S0IrqEnb as S0IrqEnd;
 pub use S0IrqEnb as S0IrqClr;
-#[doc = "S0_RXFIFOIRQTRG (rw) register accessor: Slave Rx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_rxfifoirqtrg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_rxfifoirqtrg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_rxfifoirqtrg`]
+#[doc = "S0_RXFIFOIRQTRG (rw) register accessor: Slave Rx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_rxfifoirqtrg::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_rxfifoirqtrg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_rxfifoirqtrg`]
 module"]
 #[doc(alias = "S0_RXFIFOIRQTRG")]
 pub type S0Rxfifoirqtrg = crate::Reg<s0_rxfifoirqtrg::S0RxfifoirqtrgSpec>;
 #[doc = "Slave Rx FIFO IRQ Trigger Level"]
 pub mod s0_rxfifoirqtrg;
-#[doc = "S0_TXFIFOIRQTRG (rw) register accessor: Slave Tx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_txfifoirqtrg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_txfifoirqtrg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_txfifoirqtrg`]
+#[doc = "S0_TXFIFOIRQTRG (rw) register accessor: Slave Tx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_txfifoirqtrg::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_txfifoirqtrg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_txfifoirqtrg`]
 module"]
 #[doc(alias = "S0_TXFIFOIRQTRG")]
 pub type S0Txfifoirqtrg = crate::Reg<s0_txfifoirqtrg::S0TxfifoirqtrgSpec>;
 #[doc = "Slave Tx FIFO IRQ Trigger Level"]
 pub mod s0_txfifoirqtrg;
-#[doc = "S0_FIFO_CLR (w) register accessor: Slave Clear FIFO Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_fifo_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_fifo_clr`]
+#[doc = "S0_FIFO_CLR (w) register accessor: Slave Clear FIFO Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_fifo_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_fifo_clr`]
 module"]
 #[doc(alias = "S0_FIFO_CLR")]
 pub type S0FifoClr = crate::Reg<s0_fifo_clr::S0FifoClrSpec>;
 #[doc = "Slave Clear FIFO Register"]
 pub mod s0_fifo_clr;
-#[doc = "S0_ADDRESSB (rw) register accessor: Slave I2C Address B Value\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_addressb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_addressb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_addressb`]
+#[doc = "S0_ADDRESSB (rw) register accessor: Slave I2C Address B Value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_addressb::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_addressb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_addressb`]
 module"]
 #[doc(alias = "S0_ADDRESSB")]
 pub type S0Addressb = crate::Reg<s0_addressb::S0AddressbSpec>;
 #[doc = "Slave I2C Address B Value"]
 pub mod s0_addressb;
-#[doc = "S0_ADDRESSMASKB (rw) register accessor: Slave I2C Address B Mask value\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_addressmaskb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_addressmaskb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_addressmaskb`]
+#[doc = "S0_ADDRESSMASKB (rw) register accessor: Slave I2C Address B Mask value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_addressmaskb::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_addressmaskb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_addressmaskb`]
 module"]
 #[doc(alias = "S0_ADDRESSMASKB")]
 pub type S0Addressmaskb = crate::Reg<s0_addressmaskb::S0AddressmaskbSpec>;
 #[doc = "Slave I2C Address B Mask value"]
 pub mod s0_addressmaskb;
-#[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`]
+#[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`perid::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`]
 module"]
 #[doc(alias = "PERID")]
 pub type Perid = crate::Reg<perid::PeridSpec>;

va108xx/src/i2ca/address.rs

@@ -2,14 +2,13 @@
 pub type R = crate::R<AddressSpec>;
 #[doc = "Register `ADDRESS` writer"]
 pub type W = crate::W<AddressSpec>;
-#[cfg(feature = "debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         write!(f, "{}", self.bits())
     }
 }
 impl W {}
-#[doc = "I2C Address value\n\nYou can [`read`](crate::Reg::read) this register and get [`address::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`address::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "I2C Address value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`address::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`address::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct AddressSpec;
 impl crate::RegisterSpec for AddressSpec {
     type Ux = u32;

va108xx/src/i2ca/clkscale.rs

@@ -25,16 +25,18 @@ impl R {
 impl W {
     #[doc = "Bits 0:30 - Enable FastMode"]
     #[inline(always)]
+    #[must_use]
     pub fn value(&mut self) -> ValueW<ClkscaleSpec> {
         ValueW::new(self, 0)
     }
     #[doc = "Bit 31 - Enable FastMode"]
     #[inline(always)]
+    #[must_use]
     pub fn fastmode(&mut self) -> FastmodeW<ClkscaleSpec> {
         FastmodeW::new(self, 31)
     }
 }
-#[doc = "Clock Scale divide value\n\nYou can [`read`](crate::Reg::read) this register and get [`clkscale::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clkscale::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Clock Scale divide value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkscale::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkscale::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct ClkscaleSpec;
 impl crate::RegisterSpec for ClkscaleSpec {
     type Ux = u32;

va108xx/src/i2ca/clktolimit.rs

@@ -2,14 +2,13 @@
 pub type R = crate::R<ClktolimitSpec>;
 #[doc = "Register `CLKTOLIMIT` writer"]
 pub type W = crate::W<ClktolimitSpec>;
-#[cfg(feature = "debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         write!(f, "{}", self.bits())
     }
 }
 impl W {}
-#[doc = "Clock Low Timeout Limit Register\n\nYou can [`read`](crate::Reg::read) this register and get [`clktolimit::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clktolimit::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Clock Low Timeout Limit Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clktolimit::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clktolimit::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct ClktolimitSpec;
 impl crate::RegisterSpec for ClktolimitSpec {
     type Ux = u32;

va108xx/src/i2ca/cmd.rs

@@ -2,14 +2,13 @@
 pub type R = crate::R<CmdSpec>;
 #[doc = "Register `CMD` writer"]
 pub type W = crate::W<CmdSpec>;
-#[cfg(feature = "debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         write!(f, "{}", self.bits())
     }
 }
 impl W {}
-#[doc = "Command Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cmd::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmd::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Command Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmd::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmd::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CmdSpec;
 impl crate::RegisterSpec for CmdSpec {
     type Ux = u32;

va108xx/src/i2ca/ctrl.rs

@@ -88,51 +88,60 @@ impl R {
 impl W {
     #[doc = "Bit 0 - I2C CLK Enabled"]
     #[inline(always)]
+    #[must_use]
     pub fn clkenabled(&mut self) -> ClkenabledW<CtrlSpec> {
         ClkenabledW::new(self, 0)
     }
     #[doc = "Bit 1 - I2C Activated"]
     #[inline(always)]
+    #[must_use]
     pub fn enabled(&mut self) -> EnabledW<CtrlSpec> {
         EnabledW::new(self, 1)
     }
     #[doc = "Bit 2 - I2C Active"]
     #[inline(always)]
+    #[must_use]
     pub fn enable(&mut self) -> EnableW<CtrlSpec> {
         EnableW::new(self, 2)
     }
     #[doc = "Bit 3 - TX FIFIO Empty Mode"]
     #[inline(always)]
+    #[must_use]
     pub fn txfemd(&mut self) -> TxfemdW<CtrlSpec> {
         TxfemdW::new(self, 3)
     }
     #[doc = "Bit 4 - RX FIFO Full Mode"]
     #[inline(always)]
+    #[must_use]
     pub fn rxffmd(&mut self) -> RxffmdW<CtrlSpec> {
         RxffmdW::new(self, 4)
     }
     #[doc = "Bit 5 - Enable Input Analog Glitch Filter"]
     #[inline(always)]
+    #[must_use]
     pub fn algfilter(&mut self) -> AlgfilterW<CtrlSpec> {
         AlgfilterW::new(self, 5)
     }
     #[doc = "Bit 6 - Enable Input Digital Glitch Filter"]
     #[inline(always)]
+    #[must_use]
     pub fn dlgfilter(&mut self) -> DlgfilterW<CtrlSpec> {
         DlgfilterW::new(self, 6)
     }
     #[doc = "Bit 8 - Enable LoopBack Mode"]
     #[inline(always)]
+    #[must_use]
     pub fn loopback(&mut self) -> LoopbackW<CtrlSpec> {
         LoopbackW::new(self, 8)
     }
     #[doc = "Bit 9 - Enable Timing Config Register"]
     #[inline(always)]
+    #[must_use]
     pub fn tmconfigenb(&mut self) -> TmconfigenbW<CtrlSpec> {
         TmconfigenbW::new(self, 9)
     }
 }
-#[doc = "Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CtrlSpec;
 impl crate::RegisterSpec for CtrlSpec {
     type Ux = u32;

va108xx/src/i2ca/data.rs

@@ -2,14 +2,13 @@
 pub type R = crate::R<DataSpec>;
 #[doc = "Register `DATA` writer"]
 pub type W = crate::W<DataSpec>;
-#[cfg(feature = "debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         write!(f, "{}", self.bits())
     }
 }
 impl W {}
-#[doc = "Data Input/Output\n\nYou can [`read`](crate::Reg::read) this register and get [`data::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Data Input/Output\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DataSpec;
 impl crate::RegisterSpec for DataSpec {
     type Ux = u32;

va108xx/src/i2ca/fifo_clr.rs

@@ -7,16 +7,18 @@ pub type TxfifoW<'a, REG> = crate::BitWriter<'a, REG>;
 impl W {
     #[doc = "Bit 0 - Clear Rx FIFO"]
     #[inline(always)]
+    #[must_use]
     pub fn rxfifo(&mut self) -> RxfifoW<FifoClrSpec> {
         RxfifoW::new(self, 0)
     }
     #[doc = "Bit 1 - Clear Tx FIFO"]
     #[inline(always)]
+    #[must_use]
     pub fn txfifo(&mut self) -> TxfifoW<FifoClrSpec> {
         TxfifoW::new(self, 1)
     }
 }
-#[doc = "Clear FIFO Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifo_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Clear FIFO Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifo_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct FifoClrSpec;
 impl crate::RegisterSpec for FifoClrSpec {
     type Ux = u32;

va108xx/src/i2ca/irq_enb.rs

@@ -133,76 +133,90 @@ impl R {
 impl W {
     #[doc = "Bit 0 - I2C Bus is Idle"]
     #[inline(always)]
+    #[must_use]
     pub fn i2cidle(&mut self) -> I2cidleW<IrqEnbSpec> {
         I2cidleW::new(self, 0)
     }
     #[doc = "Bit 1 - Controller is Idle"]
     #[inline(always)]
+    #[must_use]
     pub fn idle(&mut self) -> IdleW<IrqEnbSpec> {
         IdleW::new(self, 1)
     }
     #[doc = "Bit 2 - Controller is Waiting"]
     #[inline(always)]
+    #[must_use]
     pub fn waiting(&mut self) -> WaitingW<IrqEnbSpec> {
         WaitingW::new(self, 2)
     }
     #[doc = "Bit 3 - Controller is Stalled"]
     #[inline(always)]
+    #[must_use]
     pub fn stalled(&mut self) -> StalledW<IrqEnbSpec> {
         StalledW::new(self, 3)
     }
     #[doc = "Bit 4 - I2C Arbitration was lost"]
     #[inline(always)]
+    #[must_use]
     pub fn arblost(&mut self) -> ArblostW<IrqEnbSpec> {
         ArblostW::new(self, 4)
     }
     #[doc = "Bit 5 - I2C Address was not Acknowledged"]
     #[inline(always)]
+    #[must_use]
     pub fn nackaddr(&mut self) -> NackaddrW<IrqEnbSpec> {
         NackaddrW::new(self, 5)
     }
     #[doc = "Bit 6 - I2C Data was not Acknowledged"]
     #[inline(always)]
+    #[must_use]
     pub fn nackdata(&mut self) -> NackdataW<IrqEnbSpec> {
         NackdataW::new(self, 6)
     }
     #[doc = "Bit 7 - I2C Clock Low Timeout"]
     #[inline(always)]
+    #[must_use]
     pub fn clkloto(&mut self) -> ClklotoW<IrqEnbSpec> {
         ClklotoW::new(self, 7)
     }
     #[doc = "Bit 10 - TX FIFO Overflowed"]
     #[inline(always)]
+    #[must_use]
     pub fn txoverflow(&mut self) -> TxoverflowW<IrqEnbSpec> {
         TxoverflowW::new(self, 10)
     }
     #[doc = "Bit 11 - TX FIFO Overflowed"]
     #[inline(always)]
+    #[must_use]
     pub fn rxoverflow(&mut self) -> RxoverflowW<IrqEnbSpec> {
         RxoverflowW::new(self, 11)
     }
     #[doc = "Bit 12 - TX FIFO Ready"]
     #[inline(always)]
+    #[must_use]
     pub fn txready(&mut self) -> TxreadyW<IrqEnbSpec> {
         TxreadyW::new(self, 12)
     }
     #[doc = "Bit 13 - RX FIFO Ready"]
     #[inline(always)]
+    #[must_use]
     pub fn rxready(&mut self) -> RxreadyW<IrqEnbSpec> {
         RxreadyW::new(self, 13)
     }
     #[doc = "Bit 14 - TX FIFO Empty"]
     #[inline(always)]
+    #[must_use]
     pub fn txempty(&mut self) -> TxemptyW<IrqEnbSpec> {
         TxemptyW::new(self, 14)
     }
     #[doc = "Bit 15 - RX FIFO Full"]
     #[inline(always)]
+    #[must_use]
     pub fn rxfull(&mut self) -> RxfullW<IrqEnbSpec> {
         RxfullW::new(self, 15)
     }
 }
-#[doc = "Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_enb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_enb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_enb::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_enb::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IrqEnbSpec;
 impl crate::RegisterSpec for IrqEnbSpec {
     type Ux = u32;

va108xx/src/i2ca/perid.rs

@@ -1,12 +1,11 @@
 #[doc = "Register `PERID` reader"]
 pub type R = crate::R<PeridSpec>;
-#[cfg(feature = "debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         write!(f, "{}", self.bits())
     }
 }
-#[doc = "Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Peripheral ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`perid::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PeridSpec;
 impl crate::RegisterSpec for PeridSpec {
     type Ux = u32;

va108xx/src/i2ca/rxcount.rs

@@ -1,12 +1,11 @@
 #[doc = "Register `RXCOUNT` reader"]
 pub type R = crate::R<RxcountSpec>;
-#[cfg(feature = "debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         write!(f, "{}", self.bits())
     }
 }
-#[doc = "RX Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`rxcount::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "RX Count Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxcount::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RxcountSpec;
 impl crate::RegisterSpec for RxcountSpec {
     type Ux = u32;

va108xx/src/i2ca/rxfifoirqtrg.rs

@@ -2,14 +2,13 @@
 pub type R = crate::R<RxfifoirqtrgSpec>;
 #[doc = "Register `RXFIFOIRQTRG` writer"]
 pub type W = crate::W<RxfifoirqtrgSpec>;
-#[cfg(feature = "debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         write!(f, "{}", self.bits())
     }
 }
 impl W {}
-#[doc = "Rx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`rxfifoirqtrg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rxfifoirqtrg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Rx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxfifoirqtrg::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxfifoirqtrg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RxfifoirqtrgSpec;
 impl crate::RegisterSpec for RxfifoirqtrgSpec {
     type Ux = u32;

va108xx/src/i2ca/s0_address.rs

@@ -2,14 +2,13 @@
 pub type R = crate::R<S0AddressSpec>;
 #[doc = "Register `S0_ADDRESS` writer"]
 pub type W = crate::W<S0AddressSpec>;
-#[cfg(feature = "debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         write!(f, "{}", self.bits())
     }
 }
 impl W {}
-#[doc = "Slave I2C Address Value\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_address::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_address::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Slave I2C Address Value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_address::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_address::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct S0AddressSpec;
 impl crate::RegisterSpec for S0AddressSpec {
     type Ux = u32;

va108xx/src/i2ca/s0_addressb.rs

@@ -2,14 +2,13 @@
 pub type R = crate::R<S0AddressbSpec>;
 #[doc = "Register `S0_ADDRESSB` writer"]
 pub type W = crate::W<S0AddressbSpec>;
-#[cfg(feature = "debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         write!(f, "{}", self.bits())
     }
 }
 impl W {}
-#[doc = "Slave I2C Address B Value\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_addressb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_addressb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Slave I2C Address B Value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_addressb::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_addressb::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct S0AddressbSpec;
 impl crate::RegisterSpec for S0AddressbSpec {
     type Ux = u32;

va108xx/src/i2ca/s0_addressmask.rs

@@ -2,14 +2,13 @@
 pub type R = crate::R<S0AddressmaskSpec>;
 #[doc = "Register `S0_ADDRESSMASK` writer"]
 pub type W = crate::W<S0AddressmaskSpec>;
-#[cfg(feature = "debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         write!(f, "{}", self.bits())
     }
 }
 impl W {}
-#[doc = "Slave I2C Address Mask value\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_addressmask::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_addressmask::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Slave I2C Address Mask value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_addressmask::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_addressmask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct S0AddressmaskSpec;
 impl crate::RegisterSpec for S0AddressmaskSpec {
     type Ux = u32;

va108xx/src/i2ca/s0_addressmaskb.rs

@@ -2,14 +2,13 @@
 pub type R = crate::R<S0AddressmaskbSpec>;
 #[doc = "Register `S0_ADDRESSMASKB` writer"]
 pub type W = crate::W<S0AddressmaskbSpec>;
-#[cfg(feature = "debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         write!(f, "{}", self.bits())
     }
 }
 impl W {}
-#[doc = "Slave I2C Address B Mask value\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_addressmaskb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_addressmaskb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Slave I2C Address B Mask value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_addressmaskb::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_addressmaskb::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct S0AddressmaskbSpec;
 impl crate::RegisterSpec for S0AddressmaskbSpec {
     type Ux = u32;

va108xx/src/i2ca/s0_ctrl.rs

@@ -52,31 +52,36 @@ impl R {
 impl W {
     #[doc = "Bit 0 - I2C Enabled"]
     #[inline(always)]
+    #[must_use]
     pub fn clkenabled(&mut self) -> ClkenabledW<S0CtrlSpec> {
         ClkenabledW::new(self, 0)
     }
     #[doc = "Bit 1 - I2C Activated"]
     #[inline(always)]
+    #[must_use]
     pub fn enabled(&mut self) -> EnabledW<S0CtrlSpec> {
         EnabledW::new(self, 1)
     }
     #[doc = "Bit 2 - I2C Active"]
     #[inline(always)]
+    #[must_use]
     pub fn enable(&mut self) -> EnableW<S0CtrlSpec> {
         EnableW::new(self, 2)
     }
     #[doc = "Bit 3 - TX FIFIO Empty Mode"]
     #[inline(always)]
+    #[must_use]
     pub fn txfemd(&mut self) -> TxfemdW<S0CtrlSpec> {
         TxfemdW::new(self, 3)
     }
     #[doc = "Bit 4 - RX FIFO Full Mode"]
     #[inline(always)]
+    #[must_use]
     pub fn rxffmd(&mut self) -> RxffmdW<S0CtrlSpec> {
         RxffmdW::new(self, 4)
     }
 }
-#[doc = "Slave Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Slave Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_ctrl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct S0CtrlSpec;
 impl crate::RegisterSpec for S0CtrlSpec {
     type Ux = u32;

va108xx/src/i2ca/s0_data.rs

@@ -2,14 +2,13 @@
 pub type R = crate::R<S0DataSpec>;
 #[doc = "Register `S0_DATA` writer"]
 pub type W = crate::W<S0DataSpec>;
-#[cfg(feature = "debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         write!(f, "{}", self.bits())
     }
 }
 impl W {}
-#[doc = "Slave Data Input/Output\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_data::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_data::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Slave Data Input/Output\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_data::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_data::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct S0DataSpec;
 impl crate::RegisterSpec for S0DataSpec {
     type Ux = u32;

va108xx/src/i2ca/s0_fifo_clr.rs

@@ -7,16 +7,18 @@ pub type TxfifoW<'a, REG> = crate::BitWriter<'a, REG>;
 impl W {
     #[doc = "Bit 0 - Clear Rx FIFO"]
     #[inline(always)]
+    #[must_use]
     pub fn rxfifo(&mut self) -> RxfifoW<S0FifoClrSpec> {
         RxfifoW::new(self, 0)
     }
     #[doc = "Bit 1 - Clear Tx FIFO"]
     #[inline(always)]
+    #[must_use]
     pub fn txfifo(&mut self) -> TxfifoW<S0FifoClrSpec> {
         TxfifoW::new(self, 1)
     }
 }
-#[doc = "Slave Clear FIFO Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_fifo_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Slave Clear FIFO Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_fifo_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct S0FifoClrSpec;
 impl crate::RegisterSpec for S0FifoClrSpec {
     type Ux = u32;

va108xx/src/i2ca/s0_irq_enb.rs

@@ -151,86 +151,102 @@ impl R {
 impl W {
     #[doc = "Bit 0 - Controller Complted a Transaction"]
     #[inline(always)]
+    #[must_use]
     pub fn completed(&mut self) -> CompletedW<S0IrqEnbSpec> {
         CompletedW::new(self, 0)
     }
     #[doc = "Bit 1 - Controller is Idle"]
     #[inline(always)]
+    #[must_use]
     pub fn idle(&mut self) -> IdleW<S0IrqEnbSpec> {
         IdleW::new(self, 1)
     }
     #[doc = "Bit 2 - Controller is Waiting"]
     #[inline(always)]
+    #[must_use]
     pub fn waiting(&mut self) -> WaitingW<S0IrqEnbSpec> {
         WaitingW::new(self, 2)
     }
     #[doc = "Bit 3 - Controller is Tx Stalled"]
     #[inline(always)]
+    #[must_use]
     pub fn txstalled(&mut self) -> TxstalledW<S0IrqEnbSpec> {
         TxstalledW::new(self, 3)
     }
     #[doc = "Bit 4 - Controller is Rx Stalled"]
     #[inline(always)]
+    #[must_use]
     pub fn rxstalled(&mut self) -> RxstalledW<S0IrqEnbSpec> {
         RxstalledW::new(self, 4)
     }
     #[doc = "Bit 5 - I2C Address Match"]
     #[inline(always)]
+    #[must_use]
     pub fn addressmatch(&mut self) -> AddressmatchW<S0IrqEnbSpec> {
         AddressmatchW::new(self, 5)
     }
     #[doc = "Bit 6 - I2C Data was not Acknowledged"]
     #[inline(always)]
+    #[must_use]
     pub fn nackdata(&mut self) -> NackdataW<S0IrqEnbSpec> {
         NackdataW::new(self, 6)
     }
     #[doc = "Bit 7 - Pending Data is first Byte following Address"]
     #[inline(always)]
+    #[must_use]
     pub fn rxdatafirst(&mut self) -> RxdatafirstW<S0IrqEnbSpec> {
         RxdatafirstW::new(self, 7)
     }
     #[doc = "Bit 8 - I2C Start Condition"]
     #[inline(always)]
+    #[must_use]
     pub fn i2c_start(&mut self) -> I2cStartW<S0IrqEnbSpec> {
         I2cStartW::new(self, 8)
     }
     #[doc = "Bit 9 - I2C Stop Condition"]
     #[inline(always)]
+    #[must_use]
     pub fn i2c_stop(&mut self) -> I2cStopW<S0IrqEnbSpec> {
         I2cStopW::new(self, 9)
     }
     #[doc = "Bit 10 - TX FIFO Underflowed"]
     #[inline(always)]
+    #[must_use]
     pub fn txunderflow(&mut self) -> TxunderflowW<S0IrqEnbSpec> {
         TxunderflowW::new(self, 10)
     }
     #[doc = "Bit 11 - TX FIFO Overflowed"]
     #[inline(always)]
+    #[must_use]
     pub fn rxoverflow(&mut self) -> RxoverflowW<S0IrqEnbSpec> {
         RxoverflowW::new(self, 11)
     }
     #[doc = "Bit 12 - TX FIFO Ready"]
     #[inline(always)]
+    #[must_use]
     pub fn txready(&mut self) -> TxreadyW<S0IrqEnbSpec> {
         TxreadyW::new(self, 12)
     }
     #[doc = "Bit 13 - RX FIFO Ready"]
     #[inline(always)]
+    #[must_use]
     pub fn rxready(&mut self) -> RxreadyW<S0IrqEnbSpec> {
         RxreadyW::new(self, 13)
     }
     #[doc = "Bit 14 - TX FIFO Empty"]
     #[inline(always)]
+    #[must_use]
     pub fn txempty(&mut self) -> TxemptyW<S0IrqEnbSpec> {
         TxemptyW::new(self, 14)
     }
     #[doc = "Bit 15 - RX FIFO Full"]
     #[inline(always)]
+    #[must_use]
     pub fn rxfull(&mut self) -> RxfullW<S0IrqEnbSpec> {
         RxfullW::new(self, 15)
     }
 }
-#[doc = "Slave Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_irq_enb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_irq_enb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Slave Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_irq_enb::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_irq_enb::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct S0IrqEnbSpec;
 impl crate::RegisterSpec for S0IrqEnbSpec {
     type Ux = u32;