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rust:main rust:fix-simple-example
rust:vorago-reb1-v0.9.0 rust:va108xx-embassy-v0.3.0 rust:va108xx-hal-v0.12.0 rust:va108xx-v0.6.0 rust:va108xx-v0.5.1 rust:va108xx-hal-v0.11.1 rust:va108xx-embassy-v0.2.1 rust:vorago-reb1-v0.8.1 rust:va108xx-hal-v0.11.0 rust:va108xx-embassy-v0.2.0 rust:vorago-reb1-v0.8.0 rust:va108xx-hal-v0.10.0 rust:va108xx-v0.5.0 rust:va108xx-embassy-v0.1.2 rust:vorago-reb1-v0.7.0 rust:va108xx-hal-v0.9.0 rust:va108xx-v0.4.0 rust:vorago-reb1-v0.6.0 rust:va108xx-hal-v0.8.0 rust:vorago-reb1-v0.5.1 rust:va108xx-hal-v0.7.0 rust:vorago-reb1-v0.5.0 rust:va108xx-hal-v0.6.0 rust:va108xx-v0.3.0
..
compare: rust:adee40d9534fb77b54a33de6be7695fbd6c20aa5
Branches Tags
rust:fix-simple-example rust:main
rust:vorago-reb1-v0.9.0 rust:va108xx-embassy-v0.3.0 rust:va108xx-hal-v0.12.0 rust:va108xx-v0.6.0 rust:va108xx-v0.5.1 rust:va108xx-hal-v0.11.1 rust:va108xx-embassy-v0.2.1 rust:vorago-reb1-v0.8.1 rust:va108xx-hal-v0.11.0 rust:va108xx-embassy-v0.2.0 rust:vorago-reb1-v0.8.0 rust:va108xx-hal-v0.10.0 rust:va108xx-v0.5.0 rust:va108xx-embassy-v0.1.2 rust:vorago-reb1-v0.7.0 rust:va108xx-hal-v0.9.0 rust:va108xx-v0.4.0 rust:vorago-reb1-v0.6.0 rust:va108xx-hal-v0.8.0 rust:vorago-reb1-v0.5.1 rust:va108xx-hal-v0.7.0 rust:vorago-reb1-v0.5.0 rust:va108xx-hal-v0.6.0 rust:va108xx-v0.3.0

1 Commits
main ... adee40d953

Author SHA1 Message Date
Robin Mueller
adee40d953 init new shared periph crate 2025-04-24 12:42:55 +02:00
174 changed files with 2762 additions and 854 deletions
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0
.cargo/config.toml.template → .cargo/def-config.toml
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0
Embed.toml.template → Embed.toml.sample
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26
README.md
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@@ -34,15 +34,12 @@ It also contains the following helper crates:
[`RTIC`](https://rtic.rs/2/book/en/) and [`embassy`](https://github.com/embassy-rs/embassy) [`RTIC`](https://rtic.rs/2/book/en/) and [`embassy`](https://github.com/embassy-rs/embassy)
native Rust RTOSes. native Rust RTOSes.
The majority of the HAL implementation and the Embassy-rs support are contained in the external
[`vorago-shared-periphs`](https://egit.irs.uni-stuttgart.de/rust/vorago-shared-periphs) crate.
## Using the `.cargo/config.toml` file ## Using the `.cargo/config.toml` file
Use the following command to have a starting `config.toml` file Use the following command to have a starting `config.toml` file
```sh ```sh
cp .cargo/config.toml.template .cargo/config.toml cp .cargo/def-config.toml .cargo/config.toml
``` ```
You then can adapt the `config.toml` to your needs. For example, you can configure runners You then can adapt the `config.toml` to your needs. For example, you can configure runners
@@ -58,27 +55,10 @@ cp -rT vscode .vscode
You can then adapt the files in `.vscode` to your needs. You can then adapt the files in `.vscode` to your needs.
## Building projects
Building an application requires the `thumbv6m-none-eabi` cross-compiler toolchain.
If you have not installed it yet, you can do so with
```sh
rustup target add thumbv6m-none-eabi
```
After that, you can use `cargo build` to build the development version of the crate.
For example, you can use
```sh
cargo build --example blinky
```
to build a simple blinky app.
## Flashing, running and debugging the software ## Flashing, running and debugging the software
You can use CLI or VS Code for flashing, running and debugging. You can use CLI or VS Code for flashing, running and debugging. In any case, take
care of installing the pre-requisites first.
### Using CLI with probe-rs ### Using CLI with probe-rs

13
board-tests/Cargo.toml
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@@ -4,15 +4,16 @@ version = "0.1.0"
edition = "2021" edition = "2021"
[dependencies] [dependencies]
cortex-m = { version = "0.7", features = ["critical-section-single-core"] } cortex-m = { version = "0.7.6", features = ["critical-section-single-core"] }
cortex-m-rt = "0.7" cortex-m-rt = "0.7"
defmt = "1" panic-halt = "1"
defmt-rtt = "1" rtt-target = "0.6"
panic-probe = { version = "1", features = ["print-defmt"] } panic-rtt-target = "0.2"
embedded-hal = "1" embedded-hal = "1"
embedded-hal-nb = "1"
embedded-io = "0.6"
[dependencies.va108xx-hal] [dependencies.va108xx-hal]
version = "0.12" version = "0.11"
features = ["rt"] features = ["rt"]
path = "../va108xx-hal"

113
board-tests/src/main.rs
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@@ -7,21 +7,18 @@
use cortex_m_rt::entry; use cortex_m_rt::entry;
use embedded_hal::delay::DelayNs; use embedded_hal::delay::DelayNs;
// Logging provider use panic_rtt_target as _;
use defmt_rtt as _; use rtt_target::{rprintln, rtt_init_print};
// Panic provider
use panic_probe as _;
use va108xx_hal::{ use va108xx_hal::{
gpio::{regs::Gpio, Input, Output, PinState, Pull}, gpio::{PinState, PinsA, PinsB},
pac, pac::{self, interrupt},
pins::{PinsA, PinsB, Port},
prelude::*, prelude::*,
time::Hertz, time::Hertz,
timer::CountdownTimer, timer::{default_ms_irq_handler, set_up_ms_tick, CountdownTimer, InterruptConfig},
}; };
#[allow(dead_code)] #[allow(dead_code)]
#[derive(Debug, defmt::Format)] #[derive(Debug)]
enum TestCase { enum TestCase {
// Tie PORTA[0] to PORTA[1] for these tests! // Tie PORTA[0] to PORTA[1] for these tests!
TestBasic, TestBasic,
@@ -35,18 +32,18 @@ enum TestCase {
Pulse, Pulse,
// Tie PA0, PA1 and PA3 to an oscilloscope // Tie PA0, PA1 and PA3 to an oscilloscope
DelayGpio, DelayGpio,
// PA0 can be checked with an oscillsope to verify timing correctness.
DelayMs, DelayMs,
} }
#[entry] #[entry]
fn main() -> ! { fn main() -> ! {
defmt::println!("-- VA108xx Test Application --"); rtt_init_print!();
let dp = pac::Peripherals::take().unwrap(); rprintln!("-- VA108xx Test Application --");
let mut dp = pac::Peripherals::take().unwrap();
let cp = cortex_m::Peripherals::take().unwrap(); let cp = cortex_m::Peripherals::take().unwrap();
let pinsa = PinsA::new(dp.porta); let pinsa = PinsA::new(&mut dp.sysconfig, dp.porta);
let pinsb = PinsB::new(dp.portb); let pinsb = PinsB::new(&mut dp.sysconfig, dp.portb);
let mut led1 = Output::new(pinsa.pa10, PinState::Low); let mut led1 = pinsa.pa10.into_readable_push_pull_output();
let test_case = TestCase::DelayMs; let test_case = TestCase::DelayMs;
match test_case { match test_case {
@@ -54,20 +51,20 @@ fn main() -> ! {
| TestCase::TestPulldown | TestCase::TestPulldown
| TestCase::TestPullup | TestCase::TestPullup
| TestCase::TestMask => { | TestCase::TestMask => {
defmt::info!( rprintln!(
"Test case {:?}. Make sure to tie PORTA[0] to PORTA[1]", "Test case {:?}. Make sure to tie PORTA[0] to PORTA[1]",
test_case test_case
); );
} }
_ => { _ => {
defmt::info!("Test case {:?}", test_case); rprintln!("Test case {:?}", test_case);
} }
} }
match test_case { match test_case {
TestCase::TestBasic => { TestCase::TestBasic => {
// Tie PORTA[0] to PORTA[1] for these tests! // Tie PORTA[0] to PORTA[1] for these tests!
let mut out = Output::new(pinsa.pa0, PinState::Low); let mut out = pinsa.pa0.into_readable_push_pull_output();
let input = Input::new_floating(pinsa.pa1); let input = pinsa.pa1.into_floating_input();
out.set_high(); out.set_high();
assert!(input.is_high()); assert!(input.is_high());
out.set_low(); out.set_low();
@@ -75,74 +72,73 @@ fn main() -> ! {
} }
TestCase::TestPullup => { TestCase::TestPullup => {
// Tie PORTA[0] to PORTA[1] for these tests! // Tie PORTA[0] to PORTA[1] for these tests!
let input = Input::new_with_pull(pinsa.pa1, Pull::Up); let input = pinsa.pa1.into_pull_up_input();
assert!(input.is_high()); assert!(input.is_high());
let mut out = Output::new(pinsa.pa0, PinState::Low); let mut out = pinsa.pa0.into_readable_push_pull_output();
out.set_low(); out.set_low();
assert!(input.is_low()); assert!(input.is_low());
out.set_high(); out.set_high();
assert!(input.is_high()); assert!(input.is_high());
out.into_floating_input();
assert!(input.is_high());
} }
TestCase::TestPulldown => { TestCase::TestPulldown => {
// Tie PORTA[0] to PORTA[1] for these tests! // Tie PORTA[0] to PORTA[1] for these tests!
let input = Input::new_with_pull(pinsa.pa1, Pull::Down); let input = pinsa.pa1.into_pull_down_input();
assert!(input.is_low()); assert!(input.is_low());
let mut out = Output::new(pinsa.pa0, PinState::Low); let mut out = pinsa.pa0.into_push_pull_output();
out.set_low(); out.set_low();
assert!(input.is_low()); assert!(input.is_low());
out.set_high(); out.set_high();
assert!(input.is_high()); assert!(input.is_high());
out.into_floating_input();
assert!(input.is_low());
} }
TestCase::TestMask => { TestCase::TestMask => {
// Tie PORTA[0] to PORTA[1] for these tests! // Tie PORTA[0] to PORTA[1] for these tests!
// Need to test this low-level.. let mut input = pinsa.pa1.into_pull_down_input();
/*
let mut input = Input::new_with_pull(pinsa.pa1, Pull::Down);
input.clear_datamask(); input.clear_datamask();
assert!(!input.datamask()); assert!(!input.datamask());
let mut out = pinsa.pa0.into_push_pull_output(); let mut out = pinsa.pa0.into_push_pull_output();
out.clear_datamask(); out.clear_datamask();
assert!(input.is_low_masked().is_err()); assert!(input.is_low_masked().is_err());
assert!(out.set_high_masked().is_err()); assert!(out.set_high_masked().is_err());
*/
} }
TestCase::PortB => { TestCase::PortB => {
// Tie PORTB[22] to PORTB[23] for these tests! // Tie PORTB[22] to PORTB[23] for these tests!
let mut out = Output::new(pinsb.pb22, PinState::Low); let mut out = pinsb.pb22.into_readable_push_pull_output();
let input = Input::new_floating(pinsb.pb23); let input = pinsb.pb23.into_floating_input();
out.set_high(); out.set_high();
assert!(input.is_high()); assert!(input.is_high());
out.set_low(); out.set_low();
assert!(input.is_low()); assert!(input.is_low());
} }
TestCase::Perid => { TestCase::Perid => {
let mmio_porta = Gpio::new_mmio(Port::A); assert_eq!(PinsA::get_perid(), 0x004007e1);
assert_eq!(mmio_porta.read_perid(), 0x004007e1); assert_eq!(PinsB::get_perid(), 0x004007e1);
let mmio_porta = Gpio::new_mmio(Port::B);
assert_eq!(mmio_porta.read_perid(), 0x004007e1);
} }
TestCase::Pulse => { TestCase::Pulse => {
let mut output_pulsed = Output::new(pinsa.pa0, PinState::Low); let mut output_pulsed = pinsa.pa0.into_push_pull_output();
output_pulsed.configure_pulse_mode(true, PinState::Low); output_pulsed.configure_pulse_mode(true, PinState::Low);
defmt::info!("Pulsing high 10 times.."); rprintln!("Pulsing high 10 times..");
output_pulsed.set_low(); output_pulsed.set_low();
for _ in 0..10 { for _ in 0..10 {
output_pulsed.set_high(); output_pulsed.set_high();
cortex_m::asm::delay(25_000_000); cortex_m::asm::delay(25_000_000);
} }
output_pulsed.configure_pulse_mode(true, PinState::High); output_pulsed.configure_pulse_mode(true, PinState::High);
defmt::info!("Pulsing low 10 times.."); rprintln!("Pulsing low 10 times..");
for _ in 0..10 { for _ in 0..10 {
output_pulsed.set_low(); output_pulsed.set_low();
cortex_m::asm::delay(25_000_000); cortex_m::asm::delay(25_000_000);
} }
} }
TestCase::DelayGpio => { TestCase::DelayGpio => {
let mut out_0 = Output::new(pinsa.pa0, PinState::Low); let mut out_0 = pinsa.pa0.into_readable_push_pull_output();
out_0.configure_delay(true, false); out_0.configure_delay(true, false);
let mut out_1 = Output::new(pinsa.pa1, PinState::Low); let mut out_1 = pinsa.pa1.into_readable_push_pull_output();
out_1.configure_delay(false, true); out_1.configure_delay(false, true);
let mut out_2 = Output::new(pinsa.pa3, PinState::Low); let mut out_2 = pinsa.pa3.into_readable_push_pull_output();
out_2.configure_delay(true, true); out_2.configure_delay(true, true);
for _ in 0..20 { for _ in 0..20 {
out_0.toggle(); out_0.toggle();
@@ -152,8 +148,22 @@ fn main() -> ! {
} }
} }
TestCase::DelayMs => { TestCase::DelayMs => {
let mut delay_timer = CountdownTimer::new(dp.tim1, 50.MHz()); let mut ms_timer = set_up_ms_tick(
let mut pa0 = Output::new(pinsa.pa0, PinState::Low); InterruptConfig::new(pac::Interrupt::OC0, true, true),
&mut dp.sysconfig,
Some(&mut dp.irqsel),
50.MHz(),
dp.tim0,
);
for _ in 0..5 {
led1.toggle();
ms_timer.delay_ms(500);
led1.toggle();
ms_timer.delay_ms(500);
}
let mut delay_timer = CountdownTimer::new(&mut dp.sysconfig, 50.MHz(), dp.tim1);
let mut pa0 = pinsa.pa0.into_readable_push_pull_output();
for _ in 0..5 { for _ in 0..5 {
led1.toggle(); led1.toggle();
delay_timer.delay_ms(500); delay_timer.delay_ms(500);
@@ -162,23 +172,30 @@ fn main() -> ! {
} }
let ahb_freq: Hertz = 50.MHz(); let ahb_freq: Hertz = 50.MHz();
let mut syst_delay = cortex_m::delay::Delay::new(cp.SYST, ahb_freq.raw()); let mut syst_delay = cortex_m::delay::Delay::new(cp.SYST, ahb_freq.raw());
// Release image should be used to verify timings for pin PA0 // Test usecond delay using both TIM peripheral and SYST. Use the release image if you
for _ in 0..5 { // want to verify the timings!
pa0.toggle(); loop {
syst_delay.delay_us(50);
pa0.toggle();
syst_delay.delay_us(50);
pa0.toggle(); pa0.toggle();
delay_timer.delay_us(50); delay_timer.delay_us(50);
pa0.toggle(); pa0.toggle();
delay_timer.delay_us(50); delay_timer.delay_us(50);
pa0.toggle();
syst_delay.delay_us(50);
pa0.toggle();
syst_delay.delay_us(50);
} }
} }
} }
defmt::info!("Test success"); rprintln!("Test success");
loop { loop {
led1.toggle(); led1.toggle();
cortex_m::asm::delay(25_000_000); cortex_m::asm::delay(25_000_000);
} }
} }
#[interrupt]
#[allow(non_snake_case)]
fn OC0() {
default_ms_irq_handler()
}

6
bootloader/Cargo.toml
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@@ -7,7 +7,7 @@ edition = "2021"
cortex-m = "0.7" cortex-m = "0.7"
cortex-m-rt = "0.7" cortex-m-rt = "0.7"
embedded-hal = "1" embedded-hal = "1"
defmt-rtt = "1" defmt-rtt = "0.4"
defmt = "1" defmt = "1"
panic-probe = { version = "1", features = ["defmt"] } panic-probe = { version = "1", features = ["defmt"] }
crc = "3" crc = "3"
@@ -15,12 +15,12 @@ num_enum = { version = "0.7", default-features = false }
static_assertions = "1" static_assertions = "1"
[dependencies.va108xx-hal] [dependencies.va108xx-hal]
version = "0.12" version = "0.11"
path = "../va108xx-hal" path = "../va108xx-hal"
features = ["defmt"] features = ["defmt"]
[dependencies.vorago-reb1] [dependencies.vorago-reb1]
version = "0.9" version = "0.8"
path = "../vorago-reb1" path = "../vorago-reb1"
[features] [features]

4
bootloader/README.md
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@@ -12,8 +12,8 @@ The bootloader uses the following memory map:
| 0x0 | Bootloader start | code up to 0x2FFE bytes | | 0x0 | Bootloader start | code up to 0x2FFE bytes |
| 0x2FFE | Bootloader CRC | half-word | | 0x2FFE | Bootloader CRC | half-word |
| 0x3000 | App image A start | code up to 0xE7F4 (~59K) bytes | | 0x3000 | App image A start | code up to 0xE7F4 (~59K) bytes |
| 0x117F4 | App image A CRC check length | word | | 0x117F8 | App image A CRC check length | word |
| 0x117F8 | App image A CRC check value | word | | 0x117FC | App image A CRC check value | word |
| 0x117FC | App image B start | code up to 0xE7F4 (~59K) bytes | | 0x117FC | App image B start | code up to 0xE7F4 (~59K) bytes |
| 0x1FFF0 | App image B CRC check length | word | | 0x1FFF0 | App image B CRC check length | word |
| 0x1FFF4 | App image B CRC check value | word | | 0x1FFF4 | App image B CRC check value | word |

4
bootloader/src/main.rs
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@@ -10,7 +10,7 @@ use num_enum::TryFromPrimitive;
use panic_probe as _; use panic_probe as _;
// Import logger. // Import logger.
use defmt_rtt as _; use defmt_rtt as _;
use va108xx_hal::{pac, spi::SpiClockConfig, time::Hertz, timer::CountdownTimer}; use va108xx_hal::{pac, spi::SpiClkConfig, time::Hertz, timer::CountdownTimer};
use vorago_reb1::m95m01::M95M01; use vorago_reb1::m95m01::M95M01;
// Useful for debugging and see what the bootloader is doing. Enabled currently, because // Useful for debugging and see what the bootloader is doing. Enabled currently, because
@@ -106,7 +106,7 @@ fn main() -> ! {
let cp = cortex_m::Peripherals::take().unwrap(); let cp = cortex_m::Peripherals::take().unwrap();
let mut timer = CountdownTimer::new(dp.tim0, CLOCK_FREQ); let mut timer = CountdownTimer::new(dp.tim0, CLOCK_FREQ);
let clk_config = SpiClockConfig::new(2, 4); let clk_config = SpiClkConfig::new(2, 4);
let mut nvm = M95M01::new(dp.spic, clk_config); let mut nvm = M95M01::new(dp.spic, clk_config);
if FLASH_SELF { if FLASH_SELF {

22
examples/embassy/Cargo.toml
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@@ -5,35 +5,35 @@ edition = "2021"
[dependencies] [dependencies]
cfg-if = "1" cfg-if = "1"
cortex-m = { version = "0.7", features = ["critical-section-single-core"] }
cortex-m-rt = "0.7" cortex-m-rt = "0.7"
embedded-hal = "1"
embedded-hal-async = "1" embedded-hal-async = "1"
embedded-io = "0.6" embedded-io = "0.6"
embedded-io-async = "0.6" embedded-io-async = "0.6"
heapless = "0.9" heapless = "0.8"
static_cell = "2" static_cell = "2"
defmt = "1" defmt = "1"
defmt-rtt = "1" defmt-rtt = "0.4"
panic-probe = { version = "1", features = ["print-defmt"] } panic-probe = { version = "0.3", features = ["print-defmt"] }
critical-section = "1" critical-section = "1"
portable-atomic = { version = "1", features = ["unsafe-assume-single-core"]}
embassy-sync = "0.7" embassy-sync = "0.6"
embassy-time = "0.5" embassy-time = "0.4"
embassy-executor = { version = "0.9", features = [ embassy-executor = { version = "0.7", features = [
"arch-cortex-m", "arch-cortex-m",
"executor-thread", "executor-thread",
"executor-interrupt" "executor-interrupt"
]} ]}
va108xx-hal = { version = "0.12", path = "../../va108xx-hal", features = ["defmt"] } va108xx-hal = { version = "0.11", path = "../../va108xx-hal", features = ["defmt"] }
va108xx-embassy = { version = "0.3", path = "../../va108xx-embassy" } va108xx-embassy = { version = "0.2" }
[features] [features]
default = ["ticks-hz-1_000", "va108xx-embassy/irq-oc30-oc31"] default = ["ticks-hz-1_000", "va108xx-embassy/irq-oc30-oc31"]
custom-irqs = [] custom-irqs = []
ticks-hz-1_000 = ["embassy-time/tick-hz-1_000"] ticks-hz-1_000 = ["embassy-time/tick-hz-1_000"]
ticks-hz-32_768 = ["embassy-time/tick-hz-32_768"] ticks-hz-32_768 = ["embassy-time/tick-hz-32_768"]
[package.metadata.cargo-machete]
ignored = ["cortex-m-rt"]

10
examples/embassy/src/bin/async-gpio.rs
View File

@@ -59,10 +59,16 @@ static CHANNEL_PB22_TO_PB23: Channel<ThreadModeRawMutex, GpioCmd, 3> = Channel::
async fn main(spawner: Spawner) { async fn main(spawner: Spawner) {
defmt::println!("-- VA108xx Async GPIO Demo --"); defmt::println!("-- VA108xx Async GPIO Demo --");
let dp = pac::Peripherals::take().unwrap(); let mut dp = pac::Peripherals::take().unwrap();
// Safety: Only called once here. // Safety: Only called once here.
va108xx_embassy::init(dp.tim23, dp.tim22, SYSCLK_FREQ); va108xx_embassy::init(
&mut dp.sysconfig,
&dp.irqsel,
SYSCLK_FREQ,
dp.tim23,
dp.tim22,
);
let porta = PinsA::new(dp.porta); let porta = PinsA::new(dp.porta);
let portb = PinsB::new(dp.portb); let portb = PinsB::new(dp.portb);

18
examples/embassy/src/bin/async-uart-rx.rs
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@@ -40,22 +40,28 @@ const SYSCLK_FREQ: Hertz = Hertz::from_raw(50_000_000);
static QUEUE_UART_A: static_cell::ConstStaticCell<Queue<u8, 256>> = static QUEUE_UART_A: static_cell::ConstStaticCell<Queue<u8, 256>> =
static_cell::ConstStaticCell::new(Queue::new()); static_cell::ConstStaticCell::new(Queue::new());
static PRODUCER_UART_A: Mutex<RefCell<Option<Producer<u8>>>> = Mutex::new(RefCell::new(None)); static PRODUCER_UART_A: Mutex<RefCell<Option<Producer<u8, 256>>>> = Mutex::new(RefCell::new(None));
static QUEUE_UART_B: static_cell::ConstStaticCell<Queue<u8, 256>> = static QUEUE_UART_B: static_cell::ConstStaticCell<Queue<u8, 256>> =
static_cell::ConstStaticCell::new(Queue::new()); static_cell::ConstStaticCell::new(Queue::new());
static PRODUCER_UART_B: Mutex<RefCell<Option<Producer<u8>>>> = Mutex::new(RefCell::new(None)); static PRODUCER_UART_B: Mutex<RefCell<Option<Producer<u8, 256>>>> = Mutex::new(RefCell::new(None));
static CONSUMER_UART_B: Mutex<RefCell<Option<Consumer<u8>>>> = Mutex::new(RefCell::new(None)); static CONSUMER_UART_B: Mutex<RefCell<Option<Consumer<u8, 256>>>> = Mutex::new(RefCell::new(None));
// main is itself an async function. // main is itself an async function.
#[embassy_executor::main] #[embassy_executor::main]
async fn main(spawner: Spawner) { async fn main(spawner: Spawner) {
defmt::println!("-- VA108xx Async UART RX Demo --"); defmt::println!("-- VA108xx Async UART RX Demo --");
let dp = pac::Peripherals::take().unwrap(); let mut dp = pac::Peripherals::take().unwrap();
// Safety: Only called once here. // Safety: Only called once here.
va108xx_embassy::init(dp.tim23, dp.tim22, SYSCLK_FREQ); va108xx_embassy::init(
&mut dp.sysconfig,
&dp.irqsel,
SYSCLK_FREQ,
dp.tim23,
dp.tim22,
);
let porta = PinsA::new(dp.porta); let porta = PinsA::new(dp.porta);
let mut led0 = Output::new(porta.pa10, PinState::Low); let mut led0 = Output::new(porta.pa10, PinState::Low);
@@ -120,7 +126,7 @@ async fn main(spawner: Spawner) {
} }
#[embassy_executor::task] #[embassy_executor::task]
async fn uart_b_task(mut async_rx: RxAsyncOverwriting, mut tx: Tx) { async fn uart_b_task(mut async_rx: RxAsyncOverwriting<256>, mut tx: Tx) {
let mut buf = [0u8; 256]; let mut buf = [0u8; 256];
loop { loop {
defmt::info!("Current time UART B: {}", Instant::now().as_secs()); defmt::info!("Current time UART B: {}", Instant::now().as_secs());

10
examples/embassy/src/bin/async-uart-tx.rs
View File

@@ -39,10 +39,16 @@ const STR_LIST: &[&str] = &[
async fn main(_spawner: Spawner) { async fn main(_spawner: Spawner) {
defmt::println!("-- VA108xx Async UART TX Demo --"); defmt::println!("-- VA108xx Async UART TX Demo --");
let dp = pac::Peripherals::take().unwrap(); let mut dp = pac::Peripherals::take().unwrap();
// Safety: Only called once here. // Safety: Only called once here.
va108xx_embassy::init(dp.tim23, dp.tim22, SYSCLK_FREQ); va108xx_embassy::init(
&mut dp.sysconfig,
&dp.irqsel,
SYSCLK_FREQ,
dp.tim23,
dp.tim22,
);
let porta = PinsA::new(dp.porta); let porta = PinsA::new(dp.porta);

8
examples/embassy/src/main.rs
View File

@@ -26,21 +26,23 @@ const SYSCLK_FREQ: Hertz = Hertz::from_raw(50_000_000);
async fn main(_spawner: Spawner) { async fn main(_spawner: Spawner) {
defmt::println!("-- VA108xx Embassy Demo --"); defmt::println!("-- VA108xx Embassy Demo --");
let dp = pac::Peripherals::take().unwrap(); let mut dp = pac::Peripherals::take().unwrap();
// Safety: Only called once here. // Safety: Only called once here.
cfg_if::cfg_if! { cfg_if::cfg_if! {
if #[cfg(not(feature = "custom-irqs"))] { if #[cfg(not(feature = "custom-irqs"))] {
va108xx_embassy::init( va108xx_embassy::init(
&mut dp.sysconfig,
&dp.irqsel,
SYSCLK_FREQ,
dp.tim23, dp.tim23,
dp.tim22, dp.tim22,
SYSCLK_FREQ,
); );
} else { } else {
va108xx_embassy::init_with_custom_irqs( va108xx_embassy::init_with_custom_irqs(
SYSCLK_FREQ,
dp.tim23, dp.tim23,
dp.tim22, dp.tim22,
SYSCLK_FREQ,
pac::Interrupt::OC23, pac::Interrupt::OC23,
pac::Interrupt::OC24, pac::Interrupt::OC24,
); );

16
examples/rtic/Cargo.toml
View File

@@ -5,13 +5,23 @@ edition = "2021"
[dependencies] [dependencies]
cortex-m = { version = "0.7", features = ["critical-section-single-core"] } cortex-m = { version = "0.7", features = ["critical-section-single-core"] }
cortex-m-rt = "0.7"
embedded-hal = "1"
embedded-io = "0.6" embedded-io = "0.6"
defmt-rtt = "1" defmt-rtt = "0.4"
defmt = "1" defmt = "1"
panic-probe = { version = "1", features = ["defmt"] } panic-probe = { version = "1", features = ["defmt"] }
# Even though we do not use this directly, we need to activate this feature explicitely
# so that RTIC compiles because thumv6 does not have CAS operations natively.
portable-atomic = { version = "1", features = ["unsafe-assume-single-core"]}
rtic = { version = "2", features = ["thumbv6-backend"] } rtic = { version = "2", features = ["thumbv6-backend"] }
rtic-monotonics = { version = "2", features = ["cortex-m-systick"] } rtic-monotonics = { version = "2", features = ["cortex-m-systick"] }
rtic-sync = { version = "1.3", features = ["defmt-03"] }
once_cell = {version = "1", default-features = false, features = ["critical-section"]}
ringbuf = { version = "0.4.7", default-features = false, features = ["portable-atomic"] } ringbuf = { version = "0.4.7", default-features = false, features = ["portable-atomic"] }
va108xx-hal = { version = "0.12", path = "../../va108xx-hal" } va108xx-hal = { version = "0.11", path = "../../va108xx-hal" }
vorago-reb1 = { version = "0.9", path = "../../vorago-reb1" } vorago-reb1 = { version = "0.8", path = "../../vorago-reb1" }

6
examples/rtic/src/bin/blinky-button-rtic.rs
View File

@@ -10,7 +10,7 @@ mod app {
// Import global logger. // Import global logger.
use defmt_rtt as _; use defmt_rtt as _;
use va108xx_hal::{ use va108xx_hal::{
clock::{set_clk_div_register, FilterClockSelect}, clock::{set_clk_div_register, FilterClkSel},
gpio::{FilterType, InterruptEdge}, gpio::{FilterType, InterruptEdge},
pac, pac,
pins::PinsA, pins::PinsA,
@@ -60,8 +60,8 @@ mod app {
if mode == PressMode::Toggle { if mode == PressMode::Toggle {
// This filter debounces the switch for edge based interrupts // This filter debounces the switch for edge based interrupts
button.configure_filter_type(FilterType::FilterFourCycles, FilterClockSelect::Clk1); button.configure_filter_type(FilterType::FilterFourCycles, FilterClkSel::Clk1);
set_clk_div_register(&mut dp.sysconfig, FilterClockSelect::Clk1, 50_000); set_clk_div_register(&mut dp.sysconfig, FilterClkSel::Clk1, 50_000);
} }
button.configure_and_enable_edge_interrupt( button.configure_and_enable_edge_interrupt(
edge_irq, edge_irq,

10
examples/simple/Cargo.toml
View File

@@ -7,15 +7,21 @@ edition = "2021"
cortex-m = {version = "0.7", features = ["critical-section-single-core"]} cortex-m = {version = "0.7", features = ["critical-section-single-core"]}
cortex-m-rt = "0.7" cortex-m-rt = "0.7"
panic-halt = "1" panic-halt = "1"
defmt-rtt = "1" critical-section = "1"
defmt-rtt = "0.4"
defmt = "1" defmt = "1"
panic-probe = { version = "1", features = ["defmt"] } panic-probe = { version = "1", features = ["defmt"] }
embedded-hal = "1" embedded-hal = "1"
embedded-hal-nb = "1" embedded-hal-nb = "1"
embedded-io = "0.6" embedded-io = "0.6"
cortex-m-semihosting = "0.5.0"
portable-atomic = { version = "1", features = ["unsafe-assume-single-core"] } portable-atomic = { version = "1", features = ["unsafe-assume-single-core"] }
[dependencies.va108xx-hal] [dependencies.va108xx-hal]
version = "0.12" version = "0.11"
path = "../../va108xx-hal" path = "../../va108xx-hal"
features = ["defmt"] features = ["defmt"]
[dependencies.vorago-reb1]
path = "../../vorago-reb1"
version = "0.8"

4
examples/simple/examples/spi.rs
View File

@@ -14,7 +14,7 @@ use va108xx_hal::{
pac, pac,
pins::{PinsA, PinsB}, pins::{PinsA, PinsB},
prelude::*, prelude::*,
spi::{self, configure_pin_as_hw_cs_pin, Spi, SpiClockConfig, TransferConfig}, spi::{self, configure_pin_as_hw_cs_pin, Spi, SpiClkConfig, TransferConfig},
timer::CountdownTimer, timer::CountdownTimer,
}; };
@@ -45,7 +45,7 @@ fn main() -> ! {
let dp = pac::Peripherals::take().unwrap(); let dp = pac::Peripherals::take().unwrap();
let mut delay = CountdownTimer::new(dp.tim0, 50.MHz()); let mut delay = CountdownTimer::new(dp.tim0, 50.MHz());
let spi_clk_cfg = SpiClockConfig::from_clk(50.MHz(), SPI_SPEED_KHZ.kHz()) let spi_clk_cfg = SpiClkConfig::from_clk(50.MHz(), SPI_SPEED_KHZ.kHz())
.expect("creating SPI clock config failed"); .expect("creating SPI clock config failed");
let pinsa = PinsA::new(dp.porta); let pinsa = PinsA::new(dp.porta);
let pinsb = PinsB::new(dp.portb); let pinsb = PinsB::new(dp.portb);

10
examples/simple/examples/timer-ticks.rs
View File

@@ -10,6 +10,7 @@ use panic_probe as _;
use defmt_rtt as _; use defmt_rtt as _;
use portable_atomic::AtomicU32; use portable_atomic::AtomicU32;
use va108xx_hal::{ use va108xx_hal::{
clock::{get_sys_clock, set_sys_clock},
pac::{self, interrupt}, pac::{self, interrupt},
prelude::*, prelude::*,
time::Hertz, time::Hertz,
@@ -31,6 +32,7 @@ fn main() -> ! {
let mut delay = CountdownTimer::new(dp.tim2, 50.MHz()); let mut delay = CountdownTimer::new(dp.tim2, 50.MHz());
let mut last_ms = 0; let mut last_ms = 0;
defmt::info!("-- Vorago system ticks using timers --"); defmt::info!("-- Vorago system ticks using timers --");
set_sys_clock(50.MHz());
let lib_type = LibType::Hal; let lib_type = LibType::Hal;
match lib_type { match lib_type {
LibType::Pac => { LibType::Pac => {
@@ -41,8 +43,8 @@ fn main() -> ! {
dp.sysconfig dp.sysconfig
.tim_clk_enable() .tim_clk_enable()
.modify(|r, w| w.bits(r.bits() | (1 << 0) | (1 << 1))); .modify(|r, w| w.bits(r.bits() | (1 << 0) | (1 << 1)));
dp.irqsel.tim(0).write(|w| w.bits(0x00)); dp.irqsel.tim0(0).write(|w| w.bits(0x00));
dp.irqsel.tim(1).write(|w| w.bits(0x01)); dp.irqsel.tim0(1).write(|w| w.bits(0x01));
} }
let sys_clk: Hertz = 50.MHz(); let sys_clk: Hertz = 50.MHz();
@@ -65,10 +67,10 @@ fn main() -> ! {
} }
} }
LibType::Hal => { LibType::Hal => {
let mut ms_timer = CountdownTimer::new(dp.tim0, 50.MHz()); let mut ms_timer = CountdownTimer::new(dp.tim0, get_sys_clock().unwrap());
ms_timer.enable_interrupt(InterruptConfig::new(interrupt::OC0, true, true)); ms_timer.enable_interrupt(InterruptConfig::new(interrupt::OC0, true, true));
ms_timer.start(1.kHz()); ms_timer.start(1.kHz());
let mut second_timer = CountdownTimer::new(dp.tim1, 50.MHz()); let mut second_timer = CountdownTimer::new(dp.tim1, get_sys_clock().unwrap());
second_timer.enable_interrupt(InterruptConfig::new(interrupt::OC1, true, true)); second_timer.enable_interrupt(InterruptConfig::new(interrupt::OC1, true, true));
second_timer.start(1.Hz()); second_timer.start(1.Hz());
} }

25
flashloader/Cargo.toml
View File

@@ -4,32 +4,33 @@ version = "0.1.0"
edition = "2021" edition = "2021"
[dependencies] [dependencies]
cortex-m = { version = "0.7", features = ["critical-section-single-core"]} cortex-m = "0.7"
cortex-m-rt = "0.7" cortex-m-rt = "0.7"
embedded-hal = "1"
embedded-hal-nb = "1"
embedded-io = "0.6" embedded-io = "0.6"
defmt = "1" defmt = "1"
defmt-rtt = { version = "1" } defmt-rtt = { version = "0.4" }
panic-probe = { version = "1", features = ["print-defmt"] } panic-probe = { version = "0.3", features = ["print-defmt"] }
num_enum = { version = "0.7", default-features = false } num_enum = { version = "0.7", default-features = false }
cobs = { version = "0.4", default-features = false } crc = "3"
satrs = { version = "0.3.0-alpha.1", default-features = false } cobs = { version = "0.3", default-features = false }
satrs = { version = "0.2", default-features = false }
ringbuf = { version = "0.4.7", default-features = false, features = ["portable-atomic"] } ringbuf = { version = "0.4.7", default-features = false, features = ["portable-atomic"] }
spacepackets = { version = "0.15", default-features = false, features = ["defmt"] } once_cell = { version = "1", default-features = false, features = ["critical-section"] }
spacepackets = { version = "0.11", default-features = false, features = ["defmt"] }
# Even though we do not use this directly, we need to activate this feature explicitely # Even though we do not use this directly, we need to activate this feature explicitely
# so that RTIC compiles because thumv6 does not have CAS operations natively. # so that RTIC compiles because thumv6 does not have CAS operations natively.
portable-atomic = {version = "1", features = ["unsafe-assume-single-core"]} portable-atomic = {version = "1", features = ["unsafe-assume-single-core"]}
rtic = { version = "2", features = ["thumbv6-backend"] } rtic = { version = "2", features = ["thumbv6-backend"] }
rtic-monotonics = { version = "2", features = ["cortex-m-systick"] } rtic-monotonics = { version = "2", features = ["cortex-m-systick"] }
rtic-sync = {version = "1", features = ["defmt-03"]}
[dependencies.va108xx-hal] [dependencies.va108xx-hal]
version = "0.12" version = "0.11"
path = "../va108xx-hal" path = "../va108xx-hal"
features = ["defmt"] features = ["defmt"]
[dependencies.vorago-reb1] [dependencies.vorago-reb1]
version = "0.9" version = "0.8"
path = "../vorago-reb1"
[package.metadata.cargo-machete]
ignored = ["portable-atomic", "cortex-m-rt"]

3
flashloader/slot-a-blinky/Cargo.toml
View File

@@ -9,8 +9,9 @@ edition = "2021"
cortex-m-rt = "0.7" cortex-m-rt = "0.7"
panic-rtt-target = { version = "0.1.3" } panic-rtt-target = { version = "0.1.3" }
rtt-target = { version = "0.5" } rtt-target = { version = "0.5" }
cortex-m = { version = "0.7", features = ["critical-section-single-core"] }
embedded-hal = "1" embedded-hal = "1"
va108xx-hal = { version = "0.11" } va108xx-hal = { version = "0.10.0" }
[profile.dev] [profile.dev]
codegen-units = 1 codegen-units = 1

6
flashloader/slot-a-blinky/src/main.rs
View File

@@ -3,7 +3,7 @@
#![no_std] #![no_std]
use cortex_m_rt::entry; use cortex_m_rt::entry;
use embedded_hal::delay::DelayNs; use embedded_hal::{delay::DelayNs, digital::StatefulOutputPin};
use panic_rtt_target as _; use panic_rtt_target as _;
use rtt_target::{rprintln, rtt_init_print}; use rtt_target::{rprintln, rtt_init_print};
use va108xx_hal::{gpio::PinsA, pac, prelude::*, timer::CountdownTimer}; use va108xx_hal::{gpio::PinsA, pac, prelude::*, timer::CountdownTimer};
@@ -15,11 +15,11 @@ fn main() -> ! {
let mut dp = pac::Peripherals::take().unwrap(); let mut dp = pac::Peripherals::take().unwrap();
let mut timer = CountdownTimer::new(&mut dp.sysconfig, 50.MHz(), dp.tim0); let mut timer = CountdownTimer::new(&mut dp.sysconfig, 50.MHz(), dp.tim0);
let porta = PinsA::new(&mut dp.sysconfig, dp.porta); let porta = PinsA::new(&mut dp.sysconfig, Some(dp.ioconfig), dp.porta);
let mut led1 = porta.pa10.into_readable_push_pull_output(); let mut led1 = porta.pa10.into_readable_push_pull_output();
loop { loop {
led1.toggle(); led1.toggle().ok();
timer.delay_ms(500); timer.delay_ms(500);
} }
} }

3
flashloader/slot-b-blinky/Cargo.toml
View File

@@ -9,8 +9,9 @@ edition = "2021"
cortex-m-rt = "0.7" cortex-m-rt = "0.7"
panic-rtt-target = { version = "0.1.3" } panic-rtt-target = { version = "0.1.3" }
rtt-target = { version = "0.5" } rtt-target = { version = "0.5" }
cortex-m = { version = "0.7", features = ["critical-section-single-core"] }
embedded-hal = "1" embedded-hal = "1"
va108xx-hal = { version = "0.11" } va108xx-hal = { version = "0.10.0" }
[profile.dev] [profile.dev]
codegen-units = 1 codegen-units = 1

6
flashloader/slot-b-blinky/src/main.rs
View File

@@ -3,7 +3,7 @@
#![no_std] #![no_std]
use cortex_m_rt::entry; use cortex_m_rt::entry;
use embedded_hal::delay::DelayNs; use embedded_hal::{delay::DelayNs, digital::StatefulOutputPin};
use panic_rtt_target as _; use panic_rtt_target as _;
use rtt_target::{rprintln, rtt_init_print}; use rtt_target::{rprintln, rtt_init_print};
use va108xx_hal::{gpio::PinsA, pac, prelude::*, timer::CountdownTimer}; use va108xx_hal::{gpio::PinsA, pac, prelude::*, timer::CountdownTimer};
@@ -15,11 +15,11 @@ fn main() -> ! {
let mut dp = pac::Peripherals::take().unwrap(); let mut dp = pac::Peripherals::take().unwrap();
let mut timer = CountdownTimer::new(&mut dp.sysconfig, 50.MHz(), dp.tim0); let mut timer = CountdownTimer::new(&mut dp.sysconfig, 50.MHz(), dp.tim0);
let porta = PinsA::new(&mut dp.sysconfig, dp.porta); let porta = PinsA::new(&mut dp.sysconfig, Some(dp.ioconfig), dp.porta);
let mut led2 = porta.pa7.into_readable_push_pull_output(); let mut led2 = porta.pa7.into_readable_push_pull_output();
loop { loop {
led2.toggle(); led2.toggle().ok();
timer.delay_ms(1000); timer.delay_ms(1000);
} }
} }

36
flashloader/src/main.rs
View File

@@ -69,8 +69,7 @@ mod app {
tc::PusTcReader, tm::PusTmCreator, EcssEnumU8, PusPacket, WritablePusPacket, tc::PusTcReader, tm::PusTmCreator, EcssEnumU8, PusPacket, WritablePusPacket,
}; };
use va108xx_hal::pins::PinsA; use va108xx_hal::pins::PinsA;
use va108xx_hal::spi::SpiClockConfig; use va108xx_hal::uart::IrqContextTimeoutOrMaxSize;
use va108xx_hal::uart::InterruptContextTimeoutOrMaxSize;
use va108xx_hal::{pac, uart, InterruptConfig}; use va108xx_hal::{pac, uart, InterruptConfig};
use vorago_reb1::m95m01::M95M01; use vorago_reb1::m95m01::M95M01;
@@ -86,7 +85,7 @@ mod app {
struct Local { struct Local {
uart_rx: uart::RxWithInterrupt, uart_rx: uart::RxWithInterrupt,
uart_tx: uart::Tx, uart_tx: uart::Tx,
rx_context: InterruptContextTimeoutOrMaxSize, rx_context: IrqContextTimeoutOrMaxSize,
verif_reporter: VerificationReportCreator, verif_reporter: VerificationReportCreator,
nvm: M95M01, nvm: M95M01,
} }
@@ -106,9 +105,8 @@ mod app {
Mono::start(cx.core.SYST, SYSCLK_FREQ.raw()); Mono::start(cx.core.SYST, SYSCLK_FREQ.raw());
let dp = cx.device; let mut dp = cx.device;
let spi_clock_config = SpiClockConfig::new(2, 4); let nvm = M95M01::new(&mut dp.sysconfig, SYSCLK_FREQ, dp.spic);
let nvm = M95M01::new(dp.spic, spi_clock_config);
let gpioa = PinsA::new(dp.porta); let gpioa = PinsA::new(dp.porta);
let tx = gpioa.pa9; let tx = gpioa.pa9;
@@ -129,7 +127,7 @@ mod app {
let verif_reporter = VerificationReportCreator::new(0).unwrap(); let verif_reporter = VerificationReportCreator::new(0).unwrap();
let mut rx_context = InterruptContextTimeoutOrMaxSize::new(MAX_TC_FRAME_SIZE); let mut rx_context = IrqContextTimeoutOrMaxSize::new(MAX_TC_FRAME_SIZE);
rx.read_fixed_len_or_timeout_based_using_irq(&mut rx_context) rx.read_fixed_len_or_timeout_based_using_irq(&mut rx_context)
.expect("initiating UART RX failed"); .expect("initiating UART RX failed");
pus_tc_handler::spawn().unwrap(); pus_tc_handler::spawn().unwrap();
@@ -272,7 +270,7 @@ mod app {
defmt::warn!("PUS TC error: {}", pus_tc.unwrap_err()); defmt::warn!("PUS TC error: {}", pus_tc.unwrap_err());
return; return;
} }
let pus_tc = pus_tc.unwrap(); let (pus_tc, _) = pus_tc.unwrap();
let mut write_and_send = |tm: &PusTmCreator| { let mut write_and_send = |tm: &PusTmCreator| {
let written_size = tm.write_to_bytes(cx.local.verif_buf).unwrap(); let written_size = tm.write_to_bytes(cx.local.verif_buf).unwrap();
cx.shared.tm_rb.lock(|prod| { cx.shared.tm_rb.lock(|prod| {
@@ -280,18 +278,18 @@ mod app {
prod.buf.push_slice(&cx.local.verif_buf[0..written_size]); prod.buf.push_slice(&cx.local.verif_buf[0..written_size]);
}); });
}; };
let request_id = VerificationReportCreator::read_request_id_from_tc(&pus_tc); let token = cx.local.verif_reporter.add_tc(&pus_tc);
let tm = cx let (tm, accepted_token) = cx
.local .local
.verif_reporter .verif_reporter
.acceptance_success(cx.local.src_data_buf, &request_id, 0, 0, &[]) .acceptance_success(cx.local.src_data_buf, token, 0, 0, &[])
.expect("acceptance success failed"); .expect("acceptance success failed");
write_and_send(&tm); write_and_send(&tm);
let tm = cx let (tm, started_token) = cx
.local .local
.verif_reporter .verif_reporter
.start_success(cx.local.src_data_buf, &request_id, 0, 0, &[]) .start_success(cx.local.src_data_buf, accepted_token, 0, 0, &[])
.expect("acceptance success failed"); .expect("acceptance success failed");
write_and_send(&tm); write_and_send(&tm);
@@ -310,7 +308,7 @@ mod app {
let tm = cx let tm = cx
.local .local
.verif_reporter .verif_reporter
.completion_success(cx.local.src_data_buf, &request_id, 0, 0, &[]) .completion_success(cx.local.src_data_buf, started_token, 0, 0, &[])
.expect("completion success failed"); .expect("completion success failed");
write_and_send(&tm); write_and_send(&tm);
}; };
@@ -341,7 +339,7 @@ mod app {
let tm = cx let tm = cx
.local .local
.verif_reporter .verif_reporter
.completion_success(cx.local.src_data_buf, &request_id, 0, 0, &[]) .completion_success(cx.local.src_data_buf, started_token, 0, 0, &[])
.expect("completion success failed"); .expect("completion success failed");
write_and_send(&tm); write_and_send(&tm);
} }
@@ -351,7 +349,7 @@ mod app {
let tm = cx let tm = cx
.local .local
.verif_reporter .verif_reporter
.completion_success(cx.local.src_data_buf, &request_id, 0, 0, &[]) .completion_success(cx.local.src_data_buf, started_token, 0, 0, &[])
.expect("completion success failed"); .expect("completion success failed");
write_and_send(&tm); write_and_send(&tm);
} else if pus_tc.service() == PusServiceId::MemoryManagement as u8 { } else if pus_tc.service() == PusServiceId::MemoryManagement as u8 {
@@ -360,7 +358,7 @@ mod app {
.verif_reporter .verif_reporter
.step_success( .step_success(
cx.local.src_data_buf, cx.local.src_data_buf,
&request_id, &started_token,
0, 0,
0, 0,
&[], &[],
@@ -410,7 +408,7 @@ mod app {
.verif_reporter .verif_reporter
.completion_failure( .completion_failure(
cx.local.src_data_buf, cx.local.src_data_buf,
&request_id, started_token,
0, 0,
0, 0,
FailParams::new(&[], &EcssEnumU8::new(0), &[]), FailParams::new(&[], &EcssEnumU8::new(0), &[]),
@@ -419,7 +417,7 @@ mod app {
} else { } else {
cx.local cx.local
.verif_reporter .verif_reporter
.completion_success(cx.local.src_data_buf, &request_id, 0, 0, &[]) .completion_success(cx.local.src_data_buf, started_token, 0, 0, &[])
.expect("completion success failed") .expect("completion success failed")
}; };
write_and_send(&tm); write_and_send(&tm);

7
va108xx-embassy/CHANGELOG.md
View File

@@ -8,10 +8,6 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
## [unreleased] ## [unreleased]
## [v0.3.0] 2025-09-03
Bumped allowed va108xx-hal to v0.12
## [v0.2.1] 2025-03-07 ## [v0.2.1] 2025-03-07
- Bumped allowed va108xx-hal to v0.11 - Bumped allowed va108xx-hal to v0.11
@@ -30,7 +26,6 @@ Docs patch
Initial release Initial release
[unreleased]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/compare/va108xx-embassy-v0.3.0...HEAD [unreleased]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/compare/va108xx-embassy-v0.2.1...HEAD
[v0.3.0]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/compare/va108xx-embassy-v0.2.1...va10xx-embassy-v0.3.0
[v0.2.1]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/compare/va108xx-embassy-v0.2.0...va10xx-embassy-v0.2.1 [v0.2.1]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/compare/va108xx-embassy-v0.2.0...va10xx-embassy-v0.2.1
[v0.2.0]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/compare/va108xx-embassy-v0.1.2...va10xx-embassy-v0.2.0 [v0.2.0]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/compare/va108xx-embassy-v0.1.2...va10xx-embassy-v0.2.0

6
va108xx-embassy/Cargo.toml
View File

@@ -1,6 +1,6 @@
[package] [package]
name = "va108xx-embassy" name = "va108xx-embassy"
version = "0.3.0" version = "0.2.1"
edition = "2021" edition = "2021"
authors = ["Robin Mueller <muellerr@irs.uni-stuttgart.de>"] authors = ["Robin Mueller <muellerr@irs.uni-stuttgart.de>"]
description = "Embassy-rs support for the Vorago VA108xx family of microcontrollers" description = "Embassy-rs support for the Vorago VA108xx family of microcontrollers"
@@ -11,8 +11,8 @@ keywords = ["no-std", "hal", "cortex-m", "vorago", "va108xx"]
categories = ["aerospace", "embedded", "no-std", "hardware-support"] categories = ["aerospace", "embedded", "no-std", "hardware-support"]
[dependencies] [dependencies]
vorago-shared-hal = { version = "0.2", features = ["vor1x"] } vorago-shared-periphs = { version = "0.1", path = "../../vorago-shared-periphs" }
va108xx-hal = { version = "0.12" } va108xx-hal = { path = "../va108xx-hal" }
[features] [features]
default = ["irq-oc30-oc31"] default = ["irq-oc30-oc31"]

12
va108xx-embassy/src/lib.rs
View File

@@ -36,8 +36,8 @@
#[cfg(feature = "irqs-in-lib")] #[cfg(feature = "irqs-in-lib")]
use va108xx_hal::pac::{self, interrupt}; use va108xx_hal::pac::{self, interrupt};
use va108xx_hal::time::Hertz; use va108xx_hal::time::Hertz;
use va108xx_hal::timer::TimInstance; use va108xx_hal::timer::TimMarker;
use vorago_shared_hal::embassy::time_driver; use vorago_shared_periphs::embassy::time_driver;
/// Macro to define the IRQ handlers for the time driver. /// Macro to define the IRQ handlers for the time driver.
/// ///
@@ -87,10 +87,10 @@ embassy_time_driver_irqs!(timekeeper_irq = OC29, alarm_irq = OC28);
/// This should be used if the interrupt handler is provided by the library, which is the /// This should be used if the interrupt handler is provided by the library, which is the
/// default case. /// default case.
#[cfg(feature = "irqs-in-lib")] #[cfg(feature = "irqs-in-lib")]
pub fn init<TimekeeperTim: TimInstance, AlarmTim: TimInstance>( pub fn init<TimekeeperTim: TimMarker, AlarmTim: TimMarker>(
sysclk: Hertz,
timekeeper_tim: TimekeeperTim, timekeeper_tim: TimekeeperTim,
alarm_tim: AlarmTim, alarm_tim: AlarmTim,
sysclk: Hertz,
) { ) {
time_driver().__init(sysclk, timekeeper_tim, alarm_tim, TIMEKEEPER_IRQ, ALARM_IRQ) time_driver().__init(sysclk, timekeeper_tim, alarm_tim, TIMEKEEPER_IRQ, ALARM_IRQ)
} }
@@ -98,10 +98,10 @@ pub fn init<TimekeeperTim: TimInstance, AlarmTim: TimInstance>(
/// Initialization method for embassy when using custom IRQ handlers. /// Initialization method for embassy when using custom IRQ handlers.
/// ///
/// Requires an explicit [pac::Interrupt] argument for the timekeeper and alarm IRQs. /// Requires an explicit [pac::Interrupt] argument for the timekeeper and alarm IRQs.
pub fn init_with_custom_irqs<TimekeeperTim: TimInstance, AlarmTim: TimInstance>( pub fn init_with_custom_irqs<TimekeeperTim: TimMarker, AlarmTim: TimMarker>(
sysclk: Hertz,
timekeeper_tim: TimekeeperTim, timekeeper_tim: TimekeeperTim,
alarm_tim: AlarmTim, alarm_tim: AlarmTim,
sysclk: Hertz,
timekeeper_irq: pac::Interrupt, timekeeper_irq: pac::Interrupt,
alarm_irq: pac::Interrupt, alarm_irq: pac::Interrupt,
) { ) {

7
va108xx-hal/CHANGELOG.md
View File

@@ -8,11 +8,9 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
## [unreleased] ## [unreleased]
## [v0.12.0] 2025-09-03
## Changed ## Changed
- Move most library components to new [`vorago-shared-hal`](https://egit.irs.uni-stuttgart.de/rust/vorago-shared-hal) - Move most library components to new [`vorago-shared-periphs`](https://egit.irs.uni-stuttgart.de/rust/vorago-shared-periphs)
which is mostly re-exported in this crate. which is mostly re-exported in this crate.
- Overhaul and simplification of several HAL APIs. The system configuration and IRQ router - Overhaul and simplification of several HAL APIs. The system configuration and IRQ router
peripheral instance generally does not need to be passed to HAL API anymore. peripheral instance generally does not need to be passed to HAL API anymore.
@@ -276,8 +274,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
- Added basic test binary in form of an example - Added basic test binary in form of an example
- README with basic instructions how to set up own binary crate - README with basic instructions how to set up own binary crate
[unreleased]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/compare/va108xx-hal-v0.12.0...HEAD [unreleased]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/compare/va108xx-hal-v0.11.0...HEAD
[v0.12.0]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/compare/va108xx-hal-v0.11.1...va108xx-hal-v0.12.0
[v0.11.1]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/compare/va108xx-hal-v0.11.0...va108xx-hal-v0.11.1 [v0.11.1]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/compare/va108xx-hal-v0.11.0...va108xx-hal-v0.11.1
[v0.11.0]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/compare/va108xx-hal-v0.10.0...va108xx-hal-v0.11.0 [v0.11.0]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/compare/va108xx-hal-v0.10.0...va108xx-hal-v0.11.0
[v0.10.0]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/compare/va108xx-hal-v0.9.0...va108xx-hal-v0.10.0 [v0.10.0]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/compare/va108xx-hal-v0.9.0...va108xx-hal-v0.10.0

31
va108xx-hal/Cargo.toml
View File

@@ -1,6 +1,6 @@
[package] [package]
name = "va108xx-hal" name = "va108xx-hal"
version = "0.12.0" version = "0.11.1"
authors = ["Robin Mueller <muellerr@irs.uni-stuttgart.de>"] authors = ["Robin Mueller <muellerr@irs.uni-stuttgart.de>"]
edition = "2021" edition = "2021"
description = "HAL for the Vorago VA108xx family of microcontrollers" description = "HAL for the Vorago VA108xx family of microcontrollers"
@@ -12,11 +12,29 @@ categories = ["aerospace", "embedded", "no-std", "hardware-support"]
[dependencies] [dependencies]
cortex-m = { version = "0.7", features = ["critical-section-single-core"]} cortex-m = { version = "0.7", features = ["critical-section-single-core"]}
vorago-shared-hal = { version = "0.2", features = ["vor1x"] } cortex-m-rt = "0.7"
nb = "1"
paste = "1"
#vorago-shared-periphs = { git = "https://egit.irs.uni-stuttgart.de/rust/vorago-shared-periphs.git", features = ["vor1x"] }
vorago-shared-periphs = { path = "../../vorago-shared-periphs", features = ["vor1x"] }
embedded-hal = "1"
embedded-hal-async = "1"
embedded-hal-nb = "1"
embedded-io = "0.6"
embedded-io-async = "0.6"
fugit = "0.3" fugit = "0.3"
typenum = "1"
critical-section = "1"
delegate = ">=0.12, <=0.13"
heapless = "0.8"
static_cell = "2"
thiserror = { version = "2", default-features = false } thiserror = { version = "2", default-features = false }
va108xx = { version = "0.6", default-features = false, features = ["critical-section", "defmt"] } void = { version = "1", default-features = false }
defmt = { version = "1", optional = true } once_cell = { version = "1", default-features = false }
va108xx = { version = "0.5", default-features = false, features = ["critical-section", "defmt"] }
embassy-sync = "0.6"
defmt = { version = "0.3", optional = true }
[target.'cfg(all(target_arch = "arm", target_os = "none"))'.dependencies] [target.'cfg(all(target_arch = "arm", target_os = "none"))'.dependencies]
portable-atomic = { version = "1", features = ["unsafe-assume-single-core"] } portable-atomic = { version = "1", features = ["unsafe-assume-single-core"] }
@@ -26,11 +44,8 @@ portable-atomic = "1"
[features] [features]
default = ["rt"] default = ["rt"]
rt = ["va108xx/rt"] rt = ["va108xx/rt"]
defmt = ["dep:defmt", "vorago-shared-hal/defmt"] defmt = ["dep:defmt", "fugit/defmt", "embedded-hal/defmt-03", "vorago-shared-periphs/defmt"]
[package.metadata.docs.rs] [package.metadata.docs.rs]
all-features = true all-features = true
rustdoc-args = ["--generate-link-to-definition"] rustdoc-args = ["--generate-link-to-definition"]
[package.metadata.cargo-machete]
ignored = ["cortex-m"]

42
va108xx-hal/src/clock.rs
View File

@@ -1,31 +1,51 @@
//! # API for clock related functionality //! # API for clock related functionality
//! //!
//! This also includes functionality to enable the peripheral clocks //! This also includes functionality to enable the peripheral clocks
pub use vorago_shared_hal::gpio::FilterClockSelect; use crate::time::Hertz;
pub use vorago_shared_hal::sysconfig::{disable_peripheral_clock, enable_peripheral_clock}; use cortex_m::interrupt::{self, Mutex};
use once_cell::unsync::OnceCell;
pub fn set_clk_div_register(syscfg: &mut va108xx::Sysconfig, clk_sel: FilterClockSelect, div: u32) { pub use vorago_shared_periphs::gpio::FilterClkSel;
pub use vorago_shared_periphs::sysconfig::{disable_peripheral_clock, enable_peripheral_clock};
static SYS_CLOCK: Mutex<OnceCell<Hertz>> = Mutex::new(OnceCell::new());
/// The Vorago in powered by an external clock which might have different frequencies.
/// The clock can be set here so it can be used by other software components as well.
/// The clock can be set exactly once
pub fn set_sys_clock(freq: impl Into<Hertz>) {
interrupt::free(|cs| {
SYS_CLOCK.borrow(cs).set(freq.into()).ok();
})
}
/// Returns the configured system clock
pub fn get_sys_clock() -> Option<Hertz> {
interrupt::free(|cs| SYS_CLOCK.borrow(cs).get().copied())
}
pub fn set_clk_div_register(syscfg: &mut va108xx::Sysconfig, clk_sel: FilterClkSel, div: u32) {
match clk_sel { match clk_sel {
FilterClockSelect::SysClk => (), FilterClkSel::SysClk => (),
FilterClockSelect::Clk1 => { FilterClkSel::Clk1 => {
syscfg.ioconfig_clkdiv1().write(|w| unsafe { w.bits(div) }); syscfg.ioconfig_clkdiv1().write(|w| unsafe { w.bits(div) });
} }
FilterClockSelect::Clk2 => { FilterClkSel::Clk2 => {
syscfg.ioconfig_clkdiv2().write(|w| unsafe { w.bits(div) }); syscfg.ioconfig_clkdiv2().write(|w| unsafe { w.bits(div) });
} }
FilterClockSelect::Clk3 => { FilterClkSel::Clk3 => {
syscfg.ioconfig_clkdiv3().write(|w| unsafe { w.bits(div) }); syscfg.ioconfig_clkdiv3().write(|w| unsafe { w.bits(div) });
} }
FilterClockSelect::Clk4 => { FilterClkSel::Clk4 => {
syscfg.ioconfig_clkdiv4().write(|w| unsafe { w.bits(div) }); syscfg.ioconfig_clkdiv4().write(|w| unsafe { w.bits(div) });
} }
FilterClockSelect::Clk5 => { FilterClkSel::Clk5 => {
syscfg.ioconfig_clkdiv5().write(|w| unsafe { w.bits(div) }); syscfg.ioconfig_clkdiv5().write(|w| unsafe { w.bits(div) });
} }
FilterClockSelect::Clk6 => { FilterClkSel::Clk6 => {
syscfg.ioconfig_clkdiv6().write(|w| unsafe { w.bits(div) }); syscfg.ioconfig_clkdiv6().write(|w| unsafe { w.bits(div) });
} }
FilterClockSelect::Clk7 => { FilterClkSel::Clk7 => {
syscfg.ioconfig_clkdiv7().write(|w| unsafe { w.bits(div) }); syscfg.ioconfig_clkdiv7().write(|w| unsafe { w.bits(div) });
} }
} }

2
va108xx-hal/src/gpio/mod.rs
View File

@@ -17,4 +17,4 @@
//! //!
//! - [Blinky example](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/examples/simple/examples/blinky.rs) //! - [Blinky example](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/examples/simple/examples/blinky.rs)
//! - [Async GPIO example](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/examples/embassy/src/bin/async-gpio.rs) //! - [Async GPIO example](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/examples/embassy/src/bin/async-gpio.rs)
pub use vorago_shared_hal::gpio::*; pub use vorago_shared_periphs::gpio::*;

2
va108xx-hal/src/i2c.rs
View File

@@ -3,4 +3,4 @@
//! ## Examples //! ## Examples
//! //!
//! - [REB1 I2C temperature sensor example](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/vorago-reb1/examples/adt75-temp-sensor.rs) //! - [REB1 I2C temperature sensor example](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/vorago-reb1/examples/adt75-temp-sensor.rs)
pub use vorago_shared_hal::i2c::*; pub use vorago_shared_periphs::i2c::*;

9
va108xx-hal/src/lib.rs
View File

@@ -17,9 +17,8 @@ pub mod time;
pub mod timer; pub mod timer;
pub mod uart; pub mod uart;
pub use vorago_shared_hal::{ pub use vorago_shared_periphs::{
disable_nvic_interrupt, enable_nvic_interrupt, FunctionSelect, InterruptConfig, disable_nvic_interrupt, enable_nvic_interrupt, FunSel, InterruptConfig, PeripheralSelect,
PeripheralSelect,
}; };
/// This is the NONE destination reigster value for the IRQSEL peripheral. /// This is the NONE destination reigster value for the IRQSEL peripheral.
@@ -39,7 +38,7 @@ pub fn port_function_select(
ioconfig: &mut pac::Ioconfig, ioconfig: &mut pac::Ioconfig,
port: Port, port: Port,
pin: u8, pin: u8,
funsel: FunctionSelect, funsel: FunSel,
) -> Result<(), InvalidPinError> { ) -> Result<(), InvalidPinError> {
if (port == Port::A && pin >= 32) || (port == Port::B && pin >= 24) { if (port == Port::A && pin >= 32) || (port == Port::B && pin >= 24) {
return Err(InvalidPinError(pin)); return Err(InvalidPinError(pin));
@@ -47,7 +46,7 @@ pub fn port_function_select(
let reg_block = match port { let reg_block = match port {
Port::A => ioconfig.porta(pin as usize), Port::A => ioconfig.porta(pin as usize),
Port::B => ioconfig.portb(pin as usize), Port::B => ioconfig.portb0(pin as usize),
}; };
reg_block.modify(|_, w| unsafe { w.funsel().bits(funsel as u8) }); reg_block.modify(|_, w| unsafe { w.funsel().bits(funsel as u8) });

2
va108xx-hal/src/pins.rs
View File

@@ -3,4 +3,4 @@
//! This module contains the pin singletons. It allows creating those singletons //! This module contains the pin singletons. It allows creating those singletons
//! to access the [Pin] structures of individual ports in a safe way with checked ownership //! to access the [Pin] structures of individual ports in a safe way with checked ownership
//! rules. //! rules.
pub use vorago_shared_hal::pins::*; pub use vorago_shared_periphs::pins::*;

2
va108xx-hal/src/pwm.rs
View File

@@ -5,4 +5,4 @@
//! ## Examples //! ## Examples
//! //!
//! - [PWM example](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/examples/simple/examples/pwm.rs) //! - [PWM example](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/examples/simple/examples/pwm.rs)
pub use vorago_shared_hal::pwm::*; pub use vorago_shared_periphs::pwm::*;

6
va108xx-hal/src/spi/mod.rs
View File

@@ -1,12 +1,12 @@
//! API for the SPI peripheral. //! API for the SPI peripheral.
//! //!
//! The main abstraction provided by this module is the [Spi] an structure. //! The main abstraction provided by this module is the [Spi] an structure.
//! It provides the [SpiBus trait](https://docs.rs/embedded-hal/latest/embedded_hal/spi/trait.SpiBus.html), //! It provides the [embedded_hal::spi] traits, but also offer a low level interface
//! but also offer a low level interface via the [SpiLowLevel] trait. //! via the [SpiLowLevel] trait.
//! //!
//! ## Examples //! ## Examples
//! //!
//! - [Blocking SPI example](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/examples/simple/examples/spi.rs) //! - [Blocking SPI example](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/examples/simple/examples/spi.rs)
//! - [REB1 ADC example](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/vorago-reb1/examples/max11519-adc.rs) //! - [REB1 ADC example](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/vorago-reb1/examples/max11519-adc.rs)
//! - [REB1 EEPROM library](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/vorago-reb1/src/m95m01.rs) //! - [REB1 EEPROM library](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/vorago-reb1/src/m95m01.rs)
pub use vorago_shared_hal::spi::*; pub use vorago_shared_periphs::spi::*;

2
va108xx-hal/src/sysconfig.rs
View File

@@ -38,6 +38,6 @@ pub fn disable_ram_scrubbing() {
syscfg.ram_scrub().write(|w| unsafe { w.bits(0) }); syscfg.ram_scrub().write(|w| unsafe { w.bits(0) });
} }
pub use vorago_shared_hal::sysconfig::{ pub use vorago_shared_periphs::sysconfig::{
assert_peripheral_reset, disable_peripheral_clock, enable_peripheral_clock, assert_peripheral_reset, disable_peripheral_clock, enable_peripheral_clock,
}; };

2
va108xx-hal/src/time.rs
View File

@@ -1,2 +1,2 @@
//! Time units //! Time units
pub use vorago_shared_hal::time::*; pub use vorago_shared_periphs::time::*;

2
va108xx-hal/src/timer.rs
View File

@@ -4,4 +4,4 @@
//! //!
//! - [MS and second tick implementation](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/examples/simple/examples/timer-ticks.rs) //! - [MS and second tick implementation](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/examples/simple/examples/timer-ticks.rs)
//! - [Cascade feature example](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/examples/simple/examples/cascade.rs) //! - [Cascade feature example](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/examples/simple/examples/cascade.rs)
pub use vorago_shared_hal::timer::*; pub use vorago_shared_periphs::timer::*;

2
va108xx-hal/src/uart/mod.rs
View File

@@ -14,4 +14,4 @@
//! - [Flashloader exposing a CCSDS interface via UART](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/flashloader) //! - [Flashloader exposing a CCSDS interface via UART](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/flashloader)
//! - [Async UART RX example](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/examples/embassy/src/bin/async-uart-rx.rs) //! - [Async UART RX example](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/examples/embassy/src/bin/async-uart-rx.rs)
//! - [Async UART TX example](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/examples/embassy/src/bin/async-uart-tx.rs) //! - [Async UART TX example](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/examples/embassy/src/bin/async-uart-tx.rs)
pub use vorago_shared_hal::uart::*; pub use vorago_shared_periphs::uart::*;

13
va108xx/CHANGELOG.md
View File

@@ -8,14 +8,6 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
## [unreleased] ## [unreleased]
## [v0.6.0] 2025-09-03
- Re-generated PAC with `svd2rust` v0.37.0
## [v0.5.1] 2025-07-22
defmt version v1
## [v0.5.0] 2025-02-17 ## [v0.5.0] 2025-02-17
- Re-generated PAC with `svd2rust` v0.35.0 and added optional `defmt` and `Debug` implementations - Re-generated PAC with `svd2rust` v0.35.0 and added optional `defmt` and `Debug` implementations
@@ -87,8 +79,3 @@ defmt version v1
- First version of the PAC which builds. Uses a patched version - First version of the PAC which builds. Uses a patched version
of `svd2rust`: https://github.com/rust-embedded/svd2rust of `svd2rust`: https://github.com/rust-embedded/svd2rust
[unreleased]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/compare/va108xx-v0.6.0...HEAD
[v0.6.0]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/compare/va108xx-v0.5.1...va108xx-v0.6.0
[v0.5.1]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/compare/va108xx-v0.5.0...va108xx-v0.5.1
[v0.5.0]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/compare/va108xx-v0.4.0...va108xx-v0.5.0

2
va108xx/Cargo.toml
View File

@@ -1,6 +1,6 @@
[package] [package]
name = "va108xx" name = "va108xx"
version = "0.6.0" version = "0.5.0"
authors = ["Robin Mueller <muellerr@irs.uni-stuttgart.de>"] authors = ["Robin Mueller <muellerr@irs.uni-stuttgart.de>"]
edition = "2021" edition = "2021"
description = "PAC for the Vorago VA108xx family of microcontrollers" description = "PAC for the Vorago VA108xx family of microcontrollers"

82
va108xx/src/generic.rs
View File

@@ -1,46 +1,8 @@
use core::marker; use core::marker;
#[doc = " Generic peripheral accessor"]
pub struct Periph<RB, const A: usize> {
_marker: marker::PhantomData<RB>,
}
unsafe impl<RB, const A: usize> Send for Periph<RB, A> {}
impl<RB, const A: usize> Periph<RB, A> {
#[doc = "Pointer to the register block"]
pub const PTR: *const RB = A as *const _;
#[doc = "Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const RB {
Self::PTR
}
#[doc = " Steal an instance of this peripheral"]
#[doc = ""]
#[doc = " # Safety"]
#[doc = ""]
#[doc = " Ensure that the new instance of the peripheral cannot be used in a way"]
#[doc = " that may race with any existing instances, for example by only"]
#[doc = " accessing read-only or write-only registers, or by consuming the"]
#[doc = " original peripheral and using critical sections to coordinate"]
#[doc = " access between multiple new instances."]
#[doc = ""]
#[doc = " Additionally, other software such as HALs may rely on only one"]
#[doc = " peripheral instance existing to ensure memory safety; ensure"]
#[doc = " no stolen instances are passed to such software."]
pub unsafe fn steal() -> Self {
Self {
_marker: marker::PhantomData,
}
}
}
impl<RB, const A: usize> core::ops::Deref for Periph<RB, A> {
type Target = RB;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
#[doc = " Raw register type (`u8`, `u16`, `u32`, ...)"] #[doc = " Raw register type (`u8`, `u16`, `u32`, ...)"]
pub trait RawReg: pub trait RawReg:
Copy Copy
+ Default
+ From<bool> + From<bool>
+ core::ops::BitOr<Output = Self> + core::ops::BitOr<Output = Self>
+ core::ops::BitAnd<Output = Self> + core::ops::BitAnd<Output = Self>
@@ -51,10 +13,8 @@ pub trait RawReg:
{ {
#[doc = " Mask for bits of width `WI`"] #[doc = " Mask for bits of width `WI`"]
fn mask<const WI: u8>() -> Self; fn mask<const WI: u8>() -> Self;
#[doc = " `0`"] #[doc = " Mask for bits of width 1"]
const ZERO: Self; fn one() -> Self;
#[doc = " `1`"]
const ONE: Self;
} }
macro_rules! raw_reg { macro_rules! raw_reg {
($ U : ty , $ size : literal , $ mask : ident) => { ($ U : ty , $ size : literal , $ mask : ident) => {
@@ -63,8 +23,10 @@ macro_rules! raw_reg {
fn mask<const WI: u8>() -> Self { fn mask<const WI: u8>() -> Self {
$mask::<WI>() $mask::<WI>()
} }
const ZERO: Self = 0; #[inline(always)]
const ONE: Self = 1; fn one() -> Self {
1
}
} }
const fn $mask<const WI: u8>() -> $U { const fn $mask<const WI: u8>() -> $U {
<$U>::MAX >> ($size - WI) <$U>::MAX >> ($size - WI)
@@ -103,9 +65,9 @@ pub trait Writable: RegisterSpec {
#[doc = " Is it safe to write any bits to register"] #[doc = " Is it safe to write any bits to register"]
type Safety; type Safety;
#[doc = " Specifies the register bits that are not changed if you pass `1` and are changed if you pass `0`"] #[doc = " Specifies the register bits that are not changed if you pass `1` and are changed if you pass `0`"]
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = Self::Ux::ZERO; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux;
#[doc = " Specifies the register bits that are not changed if you pass `0` and are changed if you pass `1`"] #[doc = " Specifies the register bits that are not changed if you pass `0` and are changed if you pass `1`"]
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = Self::Ux::ZERO; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux;
} }
#[doc = " Reset value of the register."] #[doc = " Reset value of the register."]
#[doc = ""] #[doc = ""]
@@ -113,7 +75,7 @@ pub trait Writable: RegisterSpec {
#[doc = " register by using the `reset` method."] #[doc = " register by using the `reset` method."]
pub trait Resettable: RegisterSpec { pub trait Resettable: RegisterSpec {
#[doc = " Reset value of the register."] #[doc = " Reset value of the register."]
const RESET_VALUE: Self::Ux = Self::Ux::ZERO; const RESET_VALUE: Self::Ux;
#[doc = " Reset value of the register."] #[doc = " Reset value of the register."]
#[inline(always)] #[inline(always)]
fn reset_value() -> Self::Ux { fn reset_value() -> Self::Ux {
@@ -382,8 +344,8 @@ macro_rules! bit_proxy {
#[doc = " Writes bit to the field"] #[doc = " Writes bit to the field"]
#[inline(always)] #[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W<REG> { pub fn bit(self, value: bool) -> &'a mut W<REG> {
self.w.bits &= !(REG::Ux::ONE << self.o); self.w.bits &= !(REG::Ux::one() << self.o);
self.w.bits |= (REG::Ux::from(value) & REG::Ux::ONE) << self.o; self.w.bits |= (REG::Ux::from(value) & REG::Ux::one()) << self.o;
self.w self.w
} }
#[doc = " Writes `variant` to the field"] #[doc = " Writes `variant` to the field"]
@@ -409,13 +371,13 @@ where
#[doc = " Sets the field bit"] #[doc = " Sets the field bit"]
#[inline(always)] #[inline(always)]
pub fn set_bit(self) -> &'a mut W<REG> { pub fn set_bit(self) -> &'a mut W<REG> {
self.w.bits |= REG::Ux::ONE << self.o; self.w.bits |= REG::Ux::one() << self.o;
self.w self.w
} }
#[doc = " Clears the field bit"] #[doc = " Clears the field bit"]
#[inline(always)] #[inline(always)]
pub fn clear_bit(self) -> &'a mut W<REG> { pub fn clear_bit(self) -> &'a mut W<REG> {
self.w.bits &= !(REG::Ux::ONE << self.o); self.w.bits &= !(REG::Ux::one() << self.o);
self.w self.w
} }
} }
@@ -427,7 +389,7 @@ where
#[doc = " Sets the field bit"] #[doc = " Sets the field bit"]
#[inline(always)] #[inline(always)]
pub fn set_bit(self) -> &'a mut W<REG> { pub fn set_bit(self) -> &'a mut W<REG> {
self.w.bits |= REG::Ux::ONE << self.o; self.w.bits |= REG::Ux::one() << self.o;
self.w self.w
} }
} }
@@ -439,7 +401,7 @@ where
#[doc = " Clears the field bit"] #[doc = " Clears the field bit"]
#[inline(always)] #[inline(always)]
pub fn clear_bit(self) -> &'a mut W<REG> { pub fn clear_bit(self) -> &'a mut W<REG> {
self.w.bits &= !(REG::Ux::ONE << self.o); self.w.bits &= !(REG::Ux::one() << self.o);
self.w self.w
} }
} }
@@ -451,7 +413,7 @@ where
#[doc = "Clears the field bit by passing one"] #[doc = "Clears the field bit by passing one"]
#[inline(always)] #[inline(always)]
pub fn clear_bit_by_one(self) -> &'a mut W<REG> { pub fn clear_bit_by_one(self) -> &'a mut W<REG> {
self.w.bits |= REG::Ux::ONE << self.o; self.w.bits |= REG::Ux::one() << self.o;
self.w self.w
} }
} }
@@ -463,7 +425,7 @@ where
#[doc = "Sets the field bit by passing zero"] #[doc = "Sets the field bit by passing zero"]
#[inline(always)] #[inline(always)]
pub fn set_bit_by_zero(self) -> &'a mut W<REG> { pub fn set_bit_by_zero(self) -> &'a mut W<REG> {
self.w.bits &= !(REG::Ux::ONE << self.o); self.w.bits &= !(REG::Ux::one() << self.o);
self.w self.w
} }
} }
@@ -475,7 +437,7 @@ where
#[doc = "Toggle the field bit by passing one"] #[doc = "Toggle the field bit by passing one"]
#[inline(always)] #[inline(always)]
pub fn toggle_bit(self) -> &'a mut W<REG> { pub fn toggle_bit(self) -> &'a mut W<REG> {
self.w.bits |= REG::Ux::ONE << self.o; self.w.bits |= REG::Ux::one() << self.o;
self.w self.w
} }
} }
@@ -487,7 +449,7 @@ where
#[doc = "Toggle the field bit by passing zero"] #[doc = "Toggle the field bit by passing zero"]
#[inline(always)] #[inline(always)]
pub fn toggle_bit(self) -> &'a mut W<REG> { pub fn toggle_bit(self) -> &'a mut W<REG> {
self.w.bits &= !(REG::Ux::ONE << self.o); self.w.bits &= !(REG::Ux::one() << self.o);
self.w self.w
} }
} }
@@ -632,7 +594,7 @@ impl<REG: Writable> Reg<REG> {
F: FnOnce(&mut W<REG>) -> &mut W<REG>, F: FnOnce(&mut W<REG>) -> &mut W<REG>,
{ {
let value = f(&mut W { let value = f(&mut W {
bits: REG::Ux::ZERO, bits: REG::Ux::default(),
_reg: marker::PhantomData, _reg: marker::PhantomData,
}) })
.bits; .bits;
@@ -652,7 +614,7 @@ impl<REG: Writable> Reg<REG> {
F: FnOnce(&mut W<REG>) -> T, F: FnOnce(&mut W<REG>) -> T,
{ {
let mut writer = W { let mut writer = W {
bits: REG::Ux::ZERO, bits: REG::Ux::default(),
_reg: marker::PhantomData, _reg: marker::PhantomData,
}; };
let result = f(&mut writer); let result = f(&mut writer);

99
va108xx/src/i2ca.rs
View File

@@ -240,57 +240,68 @@ impl RegisterBlock {
&self.perid &self.perid
} }
} }
#[doc = "CTRL (rw) register accessor: Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl`] module"] #[doc = "CTRL (rw) register accessor: Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl`]
module"]
#[doc(alias = "CTRL")] #[doc(alias = "CTRL")]
pub type Ctrl = crate::Reg<ctrl::CtrlSpec>; pub type Ctrl = crate::Reg<ctrl::CtrlSpec>;
#[doc = "Control Register"] #[doc = "Control Register"]
pub mod ctrl; pub mod ctrl;
#[doc = "CLKSCALE (rw) register accessor: Clock Scale divide value\n\nYou can [`read`](crate::Reg::read) this register and get [`clkscale::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clkscale::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clkscale`] module"] #[doc = "CLKSCALE (rw) register accessor: Clock Scale divide value\n\nYou can [`read`](crate::Reg::read) this register and get [`clkscale::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clkscale::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clkscale`]
module"]
#[doc(alias = "CLKSCALE")] #[doc(alias = "CLKSCALE")]
pub type Clkscale = crate::Reg<clkscale::ClkscaleSpec>; pub type Clkscale = crate::Reg<clkscale::ClkscaleSpec>;
#[doc = "Clock Scale divide value"] #[doc = "Clock Scale divide value"]
pub mod clkscale; pub mod clkscale;
#[doc = "WORDS (rw) register accessor: Word Count value\n\nYou can [`read`](crate::Reg::read) this register and get [`words::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`words::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@words`] module"] #[doc = "WORDS (rw) register accessor: Word Count value\n\nYou can [`read`](crate::Reg::read) this register and get [`words::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`words::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@words`]
module"]
#[doc(alias = "WORDS")] #[doc(alias = "WORDS")]
pub type Words = crate::Reg<words::WordsSpec>; pub type Words = crate::Reg<words::WordsSpec>;
#[doc = "Word Count value"] #[doc = "Word Count value"]
pub mod words; pub mod words;
#[doc = "ADDRESS (rw) register accessor: I2C Address value\n\nYou can [`read`](crate::Reg::read) this register and get [`address::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`address::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@address`] module"] #[doc = "ADDRESS (rw) register accessor: I2C Address value\n\nYou can [`read`](crate::Reg::read) this register and get [`address::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`address::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@address`]
module"]
#[doc(alias = "ADDRESS")] #[doc(alias = "ADDRESS")]
pub type Address = crate::Reg<address::AddressSpec>; pub type Address = crate::Reg<address::AddressSpec>;
#[doc = "I2C Address value"] #[doc = "I2C Address value"]
pub mod address; pub mod address;
#[doc = "DATA (rw) register accessor: Data Input/Output\n\nYou can [`read`](crate::Reg::read) this register and get [`data::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data`] module"] #[doc = "DATA (rw) register accessor: Data Input/Output\n\nYou can [`read`](crate::Reg::read) this register and get [`data::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data`]
module"]
#[doc(alias = "DATA")] #[doc(alias = "DATA")]
pub type Data = crate::Reg<data::DataSpec>; pub type Data = crate::Reg<data::DataSpec>;
#[doc = "Data Input/Output"] #[doc = "Data Input/Output"]
pub mod data; pub mod data;
#[doc = "CMD (rw) register accessor: Command Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cmd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmd`] module"] #[doc = "CMD (rw) register accessor: Command Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cmd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmd`]
module"]
#[doc(alias = "CMD")] #[doc(alias = "CMD")]
pub type Cmd = crate::Reg<cmd::CmdSpec>; pub type Cmd = crate::Reg<cmd::CmdSpec>;
#[doc = "Command Register"] #[doc = "Command Register"]
pub mod cmd; pub mod cmd;
#[doc = "STATUS (r) register accessor: I2C Controller Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status`] module"] #[doc = "STATUS (r) register accessor: I2C Controller Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status`]
module"]
#[doc(alias = "STATUS")] #[doc(alias = "STATUS")]
pub type Status = crate::Reg<status::StatusSpec>; pub type Status = crate::Reg<status::StatusSpec>;
#[doc = "I2C Controller Status Register"] #[doc = "I2C Controller Status Register"]
pub mod status; pub mod status;
#[doc = "STATE (r) register accessor: Internal STATE of I2C Master Controller\n\nYou can [`read`](crate::Reg::read) this register and get [`state::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@state`] module"] #[doc = "STATE (r) register accessor: Internal STATE of I2C Master Controller\n\nYou can [`read`](crate::Reg::read) this register and get [`state::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@state`]
module"]
#[doc(alias = "STATE")] #[doc(alias = "STATE")]
pub type State = crate::Reg<state::StateSpec>; pub type State = crate::Reg<state::StateSpec>;
#[doc = "Internal STATE of I2C Master Controller"] #[doc = "Internal STATE of I2C Master Controller"]
pub mod state; pub mod state;
#[doc = "TXCOUNT (r) register accessor: TX Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`txcount::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txcount`] module"] #[doc = "TXCOUNT (r) register accessor: TX Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`txcount::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txcount`]
module"]
#[doc(alias = "TXCOUNT")] #[doc(alias = "TXCOUNT")]
pub type Txcount = crate::Reg<txcount::TxcountSpec>; pub type Txcount = crate::Reg<txcount::TxcountSpec>;
#[doc = "TX Count Register"] #[doc = "TX Count Register"]
pub mod txcount; pub mod txcount;
#[doc = "RXCOUNT (r) register accessor: RX Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`rxcount::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxcount`] module"] #[doc = "RXCOUNT (r) register accessor: RX Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`rxcount::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxcount`]
module"]
#[doc(alias = "RXCOUNT")] #[doc(alias = "RXCOUNT")]
pub type Rxcount = crate::Reg<rxcount::RxcountSpec>; pub type Rxcount = crate::Reg<rxcount::RxcountSpec>;
#[doc = "RX Count Register"] #[doc = "RX Count Register"]
pub mod rxcount; pub mod rxcount;
#[doc = "IRQ_ENB (rw) register accessor: Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_enb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_enb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_enb`] module"] #[doc = "IRQ_ENB (rw) register accessor: Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_enb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_enb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_enb`]
module"]
#[doc(alias = "IRQ_ENB")] #[doc(alias = "IRQ_ENB")]
pub type IrqEnb = crate::Reg<irq_enb::IrqEnbSpec>; pub type IrqEnb = crate::Reg<irq_enb::IrqEnbSpec>;
#[doc = "Interrupt Enable Register"] #[doc = "Interrupt Enable Register"]
@@ -301,82 +312,98 @@ pub use irq_enb as irq_clr;
pub use IrqEnb as IrqRaw; pub use IrqEnb as IrqRaw;
pub use IrqEnb as IrqEnd; pub use IrqEnb as IrqEnd;
pub use IrqEnb as IrqClr; pub use IrqEnb as IrqClr;
#[doc = "RXFIFOIRQTRG (rw) register accessor: Rx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`rxfifoirqtrg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rxfifoirqtrg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxfifoirqtrg`] module"] #[doc = "RXFIFOIRQTRG (rw) register accessor: Rx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`rxfifoirqtrg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rxfifoirqtrg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxfifoirqtrg`]
module"]
#[doc(alias = "RXFIFOIRQTRG")] #[doc(alias = "RXFIFOIRQTRG")]
pub type Rxfifoirqtrg = crate::Reg<rxfifoirqtrg::RxfifoirqtrgSpec>; pub type Rxfifoirqtrg = crate::Reg<rxfifoirqtrg::RxfifoirqtrgSpec>;
#[doc = "Rx FIFO IRQ Trigger Level"] #[doc = "Rx FIFO IRQ Trigger Level"]
pub mod rxfifoirqtrg; pub mod rxfifoirqtrg;
#[doc = "TXFIFOIRQTRG (rw) register accessor: Tx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`txfifoirqtrg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`txfifoirqtrg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txfifoirqtrg`] module"] #[doc = "TXFIFOIRQTRG (rw) register accessor: Tx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`txfifoirqtrg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`txfifoirqtrg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txfifoirqtrg`]
module"]
#[doc(alias = "TXFIFOIRQTRG")] #[doc(alias = "TXFIFOIRQTRG")]
pub type Txfifoirqtrg = crate::Reg<txfifoirqtrg::TxfifoirqtrgSpec>; pub type Txfifoirqtrg = crate::Reg<txfifoirqtrg::TxfifoirqtrgSpec>;
#[doc = "Tx FIFO IRQ Trigger Level"] #[doc = "Tx FIFO IRQ Trigger Level"]
pub mod txfifoirqtrg; pub mod txfifoirqtrg;
#[doc = "FIFO_CLR (w) register accessor: Clear FIFO Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifo_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifo_clr`] module"] #[doc = "FIFO_CLR (w) register accessor: Clear FIFO Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifo_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifo_clr`]
module"]
#[doc(alias = "FIFO_CLR")] #[doc(alias = "FIFO_CLR")]
pub type FifoClr = crate::Reg<fifo_clr::FifoClrSpec>; pub type FifoClr = crate::Reg<fifo_clr::FifoClrSpec>;
#[doc = "Clear FIFO Register"] #[doc = "Clear FIFO Register"]
pub mod fifo_clr; pub mod fifo_clr;
#[doc = "TMCONFIG (rw) register accessor: Timing Config Register\n\nYou can [`read`](crate::Reg::read) this register and get [`tmconfig::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tmconfig::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tmconfig`] module"] #[doc = "TMCONFIG (rw) register accessor: Timing Config Register\n\nYou can [`read`](crate::Reg::read) this register and get [`tmconfig::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tmconfig::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tmconfig`]
module"]
#[doc(alias = "TMCONFIG")] #[doc(alias = "TMCONFIG")]
pub type Tmconfig = crate::Reg<tmconfig::TmconfigSpec>; pub type Tmconfig = crate::Reg<tmconfig::TmconfigSpec>;
#[doc = "Timing Config Register"] #[doc = "Timing Config Register"]
pub mod tmconfig; pub mod tmconfig;
#[doc = "CLKTOLIMIT (rw) register accessor: Clock Low Timeout Limit Register\n\nYou can [`read`](crate::Reg::read) this register and get [`clktolimit::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clktolimit::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clktolimit`] module"] #[doc = "CLKTOLIMIT (rw) register accessor: Clock Low Timeout Limit Register\n\nYou can [`read`](crate::Reg::read) this register and get [`clktolimit::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clktolimit::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clktolimit`]
module"]
#[doc(alias = "CLKTOLIMIT")] #[doc(alias = "CLKTOLIMIT")]
pub type Clktolimit = crate::Reg<clktolimit::ClktolimitSpec>; pub type Clktolimit = crate::Reg<clktolimit::ClktolimitSpec>;
#[doc = "Clock Low Timeout Limit Register"] #[doc = "Clock Low Timeout Limit Register"]
pub mod clktolimit; pub mod clktolimit;
#[doc = "S0_CTRL (rw) register accessor: Slave Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_ctrl`] module"] #[doc = "S0_CTRL (rw) register accessor: Slave Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_ctrl`]
module"]
#[doc(alias = "S0_CTRL")] #[doc(alias = "S0_CTRL")]
pub type S0Ctrl = crate::Reg<s0_ctrl::S0CtrlSpec>; pub type S0Ctrl = crate::Reg<s0_ctrl::S0CtrlSpec>;
#[doc = "Slave Control Register"] #[doc = "Slave Control Register"]
pub mod s0_ctrl; pub mod s0_ctrl;
#[doc = "S0_MAXWORDS (rw) register accessor: Slave MaxWords Register\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_maxwords::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_maxwords::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_maxwords`] module"] #[doc = "S0_MAXWORDS (rw) register accessor: Slave MaxWords Register\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_maxwords::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_maxwords::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_maxwords`]
module"]
#[doc(alias = "S0_MAXWORDS")] #[doc(alias = "S0_MAXWORDS")]
pub type S0Maxwords = crate::Reg<s0_maxwords::S0MaxwordsSpec>; pub type S0Maxwords = crate::Reg<s0_maxwords::S0MaxwordsSpec>;
#[doc = "Slave MaxWords Register"] #[doc = "Slave MaxWords Register"]
pub mod s0_maxwords; pub mod s0_maxwords;
#[doc = "S0_ADDRESS (rw) register accessor: Slave I2C Address Value\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_address::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_address::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_address`] module"] #[doc = "S0_ADDRESS (rw) register accessor: Slave I2C Address Value\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_address::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_address::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_address`]
module"]
#[doc(alias = "S0_ADDRESS")] #[doc(alias = "S0_ADDRESS")]
pub type S0Address = crate::Reg<s0_address::S0AddressSpec>; pub type S0Address = crate::Reg<s0_address::S0AddressSpec>;
#[doc = "Slave I2C Address Value"] #[doc = "Slave I2C Address Value"]
pub mod s0_address; pub mod s0_address;
#[doc = "S0_ADDRESSMASK (rw) register accessor: Slave I2C Address Mask value\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_addressmask::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_addressmask::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_addressmask`] module"] #[doc = "S0_ADDRESSMASK (rw) register accessor: Slave I2C Address Mask value\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_addressmask::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_addressmask::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_addressmask`]
module"]
#[doc(alias = "S0_ADDRESSMASK")] #[doc(alias = "S0_ADDRESSMASK")]
pub type S0Addressmask = crate::Reg<s0_addressmask::S0AddressmaskSpec>; pub type S0Addressmask = crate::Reg<s0_addressmask::S0AddressmaskSpec>;
#[doc = "Slave I2C Address Mask value"] #[doc = "Slave I2C Address Mask value"]
pub mod s0_addressmask; pub mod s0_addressmask;
#[doc = "S0_DATA (rw) register accessor: Slave Data Input/Output\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_data::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_data::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_data`] module"] #[doc = "S0_DATA (rw) register accessor: Slave Data Input/Output\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_data::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_data::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_data`]
module"]
#[doc(alias = "S0_DATA")] #[doc(alias = "S0_DATA")]
pub type S0Data = crate::Reg<s0_data::S0DataSpec>; pub type S0Data = crate::Reg<s0_data::S0DataSpec>;
#[doc = "Slave Data Input/Output"] #[doc = "Slave Data Input/Output"]
pub mod s0_data; pub mod s0_data;
#[doc = "S0_LASTADDRESS (r) register accessor: Slave I2C Last Address value\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_lastaddress::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_lastaddress`] module"] #[doc = "S0_LASTADDRESS (r) register accessor: Slave I2C Last Address value\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_lastaddress::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_lastaddress`]
module"]
#[doc(alias = "S0_LASTADDRESS")] #[doc(alias = "S0_LASTADDRESS")]
pub type S0Lastaddress = crate::Reg<s0_lastaddress::S0LastaddressSpec>; pub type S0Lastaddress = crate::Reg<s0_lastaddress::S0LastaddressSpec>;
#[doc = "Slave I2C Last Address value"] #[doc = "Slave I2C Last Address value"]
pub mod s0_lastaddress; pub mod s0_lastaddress;
#[doc = "S0_STATUS (r) register accessor: Slave I2C Controller Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_status`] module"] #[doc = "S0_STATUS (r) register accessor: Slave I2C Controller Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_status`]
module"]
#[doc(alias = "S0_STATUS")] #[doc(alias = "S0_STATUS")]
pub type S0Status = crate::Reg<s0_status::S0StatusSpec>; pub type S0Status = crate::Reg<s0_status::S0StatusSpec>;
#[doc = "Slave I2C Controller Status Register"] #[doc = "Slave I2C Controller Status Register"]
pub mod s0_status; pub mod s0_status;
#[doc = "S0_STATE (r) register accessor: Internal STATE of I2C Slave Controller\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_state::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_state`] module"] #[doc = "S0_STATE (r) register accessor: Internal STATE of I2C Slave Controller\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_state::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_state`]
module"]
#[doc(alias = "S0_STATE")] #[doc(alias = "S0_STATE")]
pub type S0State = crate::Reg<s0_state::S0StateSpec>; pub type S0State = crate::Reg<s0_state::S0StateSpec>;
#[doc = "Internal STATE of I2C Slave Controller"] #[doc = "Internal STATE of I2C Slave Controller"]
pub mod s0_state; pub mod s0_state;
#[doc = "S0_TXCOUNT (r) register accessor: Slave TX Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_txcount::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_txcount`] module"] #[doc = "S0_TXCOUNT (r) register accessor: Slave TX Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_txcount::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_txcount`]
module"]
#[doc(alias = "S0_TXCOUNT")] #[doc(alias = "S0_TXCOUNT")]
pub type S0Txcount = crate::Reg<s0_txcount::S0TxcountSpec>; pub type S0Txcount = crate::Reg<s0_txcount::S0TxcountSpec>;
#[doc = "Slave TX Count Register"] #[doc = "Slave TX Count Register"]
pub mod s0_txcount; pub mod s0_txcount;
#[doc = "S0_RXCOUNT (r) register accessor: Slave RX Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_rxcount::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_rxcount`] module"] #[doc = "S0_RXCOUNT (r) register accessor: Slave RX Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_rxcount::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_rxcount`]
module"]
#[doc(alias = "S0_RXCOUNT")] #[doc(alias = "S0_RXCOUNT")]
pub type S0Rxcount = crate::Reg<s0_rxcount::S0RxcountSpec>; pub type S0Rxcount = crate::Reg<s0_rxcount::S0RxcountSpec>;
#[doc = "Slave RX Count Register"] #[doc = "Slave RX Count Register"]
pub mod s0_rxcount; pub mod s0_rxcount;
#[doc = "S0_IRQ_ENB (rw) register accessor: Slave Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_irq_enb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_irq_enb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_irq_enb`] module"] #[doc = "S0_IRQ_ENB (rw) register accessor: Slave Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_irq_enb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_irq_enb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_irq_enb`]
module"]
#[doc(alias = "S0_IRQ_ENB")] #[doc(alias = "S0_IRQ_ENB")]
pub type S0IrqEnb = crate::Reg<s0_irq_enb::S0IrqEnbSpec>; pub type S0IrqEnb = crate::Reg<s0_irq_enb::S0IrqEnbSpec>;
#[doc = "Slave Interrupt Enable Register"] #[doc = "Slave Interrupt Enable Register"]
@@ -387,32 +414,38 @@ pub use s0_irq_enb as s0_irq_clr;
pub use S0IrqEnb as S0IrqRaw; pub use S0IrqEnb as S0IrqRaw;
pub use S0IrqEnb as S0IrqEnd; pub use S0IrqEnb as S0IrqEnd;
pub use S0IrqEnb as S0IrqClr; pub use S0IrqEnb as S0IrqClr;
#[doc = "S0_RXFIFOIRQTRG (rw) register accessor: Slave Rx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_rxfifoirqtrg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_rxfifoirqtrg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_rxfifoirqtrg`] module"] #[doc = "S0_RXFIFOIRQTRG (rw) register accessor: Slave Rx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_rxfifoirqtrg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_rxfifoirqtrg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_rxfifoirqtrg`]
module"]
#[doc(alias = "S0_RXFIFOIRQTRG")] #[doc(alias = "S0_RXFIFOIRQTRG")]
pub type S0Rxfifoirqtrg = crate::Reg<s0_rxfifoirqtrg::S0RxfifoirqtrgSpec>; pub type S0Rxfifoirqtrg = crate::Reg<s0_rxfifoirqtrg::S0RxfifoirqtrgSpec>;
#[doc = "Slave Rx FIFO IRQ Trigger Level"] #[doc = "Slave Rx FIFO IRQ Trigger Level"]
pub mod s0_rxfifoirqtrg; pub mod s0_rxfifoirqtrg;
#[doc = "S0_TXFIFOIRQTRG (rw) register accessor: Slave Tx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_txfifoirqtrg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_txfifoirqtrg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_txfifoirqtrg`] module"] #[doc = "S0_TXFIFOIRQTRG (rw) register accessor: Slave Tx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_txfifoirqtrg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_txfifoirqtrg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_txfifoirqtrg`]
module"]
#[doc(alias = "S0_TXFIFOIRQTRG")] #[doc(alias = "S0_TXFIFOIRQTRG")]
pub type S0Txfifoirqtrg = crate::Reg<s0_txfifoirqtrg::S0TxfifoirqtrgSpec>; pub type S0Txfifoirqtrg = crate::Reg<s0_txfifoirqtrg::S0TxfifoirqtrgSpec>;
#[doc = "Slave Tx FIFO IRQ Trigger Level"] #[doc = "Slave Tx FIFO IRQ Trigger Level"]
pub mod s0_txfifoirqtrg; pub mod s0_txfifoirqtrg;
#[doc = "S0_FIFO_CLR (w) register accessor: Slave Clear FIFO Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_fifo_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_fifo_clr`] module"] #[doc = "S0_FIFO_CLR (w) register accessor: Slave Clear FIFO Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_fifo_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_fifo_clr`]
module"]
#[doc(alias = "S0_FIFO_CLR")] #[doc(alias = "S0_FIFO_CLR")]
pub type S0FifoClr = crate::Reg<s0_fifo_clr::S0FifoClrSpec>; pub type S0FifoClr = crate::Reg<s0_fifo_clr::S0FifoClrSpec>;
#[doc = "Slave Clear FIFO Register"] #[doc = "Slave Clear FIFO Register"]
pub mod s0_fifo_clr; pub mod s0_fifo_clr;
#[doc = "S0_ADDRESSB (rw) register accessor: Slave I2C Address B Value\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_addressb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_addressb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_addressb`] module"] #[doc = "S0_ADDRESSB (rw) register accessor: Slave I2C Address B Value\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_addressb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_addressb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_addressb`]
module"]
#[doc(alias = "S0_ADDRESSB")] #[doc(alias = "S0_ADDRESSB")]
pub type S0Addressb = crate::Reg<s0_addressb::S0AddressbSpec>; pub type S0Addressb = crate::Reg<s0_addressb::S0AddressbSpec>;
#[doc = "Slave I2C Address B Value"] #[doc = "Slave I2C Address B Value"]
pub mod s0_addressb; pub mod s0_addressb;
#[doc = "S0_ADDRESSMASKB (rw) register accessor: Slave I2C Address B Mask value\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_addressmaskb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_addressmaskb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_addressmaskb`] module"] #[doc = "S0_ADDRESSMASKB (rw) register accessor: Slave I2C Address B Mask value\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_addressmaskb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_addressmaskb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_addressmaskb`]
module"]
#[doc(alias = "S0_ADDRESSMASKB")] #[doc(alias = "S0_ADDRESSMASKB")]
pub type S0Addressmaskb = crate::Reg<s0_addressmaskb::S0AddressmaskbSpec>; pub type S0Addressmaskb = crate::Reg<s0_addressmaskb::S0AddressmaskbSpec>;
#[doc = "Slave I2C Address B Mask value"] #[doc = "Slave I2C Address B Mask value"]
pub mod s0_addressmaskb; pub mod s0_addressmaskb;
#[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`] module"] #[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`]
module"]
#[doc(alias = "PERID")] #[doc(alias = "PERID")]
pub type Perid = crate::Reg<perid::PeridSpec>; pub type Perid = crate::Reg<perid::PeridSpec>;
#[doc = "Peripheral ID Register"] #[doc = "Peripheral ID Register"]

6
va108xx/src/i2ca/address.rs
View File

@@ -19,6 +19,10 @@ impl crate::Readable for AddressSpec {}
#[doc = "`write(|w| ..)` method takes [`address::W`](W) writer structure"] #[doc = "`write(|w| ..)` method takes [`address::W`](W) writer structure"]
impl crate::Writable for AddressSpec { impl crate::Writable for AddressSpec {
type Safety = crate::Unsafe; type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
} }
#[doc = "`reset()` method sets ADDRESS to value 0"] #[doc = "`reset()` method sets ADDRESS to value 0"]
impl crate::Resettable for AddressSpec {} impl crate::Resettable for AddressSpec {
const RESET_VALUE: u32 = 0;
}

10
va108xx/src/i2ca/clkscale.rs
View File

@@ -25,12 +25,12 @@ impl R {
impl W { impl W {
#[doc = "Bits 0:30 - Enable FastMode"] #[doc = "Bits 0:30 - Enable FastMode"]
#[inline(always)] #[inline(always)]
pub fn value(&mut self) -> ValueW<'_, ClkscaleSpec> { pub fn value(&mut self) -> ValueW<ClkscaleSpec> {
ValueW::new(self, 0) ValueW::new(self, 0)
} }
#[doc = "Bit 31 - Enable FastMode"] #[doc = "Bit 31 - Enable FastMode"]
#[inline(always)] #[inline(always)]
pub fn fastmode(&mut self) -> FastmodeW<'_, ClkscaleSpec> { pub fn fastmode(&mut self) -> FastmodeW<ClkscaleSpec> {
FastmodeW::new(self, 31) FastmodeW::new(self, 31)
} }
} }
@@ -44,6 +44,10 @@ impl crate::Readable for ClkscaleSpec {}
#[doc = "`write(|w| ..)` method takes [`clkscale::W`](W) writer structure"] #[doc = "`write(|w| ..)` method takes [`clkscale::W`](W) writer structure"]
impl crate::Writable for ClkscaleSpec { impl crate::Writable for ClkscaleSpec {
type Safety = crate::Unsafe; type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
} }
#[doc = "`reset()` method sets CLKSCALE to value 0"] #[doc = "`reset()` method sets CLKSCALE to value 0"]
impl crate::Resettable for ClkscaleSpec {} impl crate::Resettable for ClkscaleSpec {
const RESET_VALUE: u32 = 0;
}

6
va108xx/src/i2ca/clktolimit.rs
View File

@@ -19,6 +19,10 @@ impl crate::Readable for ClktolimitSpec {}
#[doc = "`write(|w| ..)` method takes [`clktolimit::W`](W) writer structure"] #[doc = "`write(|w| ..)` method takes [`clktolimit::W`](W) writer structure"]
impl crate::Writable for ClktolimitSpec { impl crate::Writable for ClktolimitSpec {
type Safety = crate::Unsafe; type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
} }
#[doc = "`reset()` method sets CLKTOLIMIT to value 0"] #[doc = "`reset()` method sets CLKTOLIMIT to value 0"]
impl crate::Resettable for ClktolimitSpec {} impl crate::Resettable for ClktolimitSpec {
const RESET_VALUE: u32 = 0;
}

6
va108xx/src/i2ca/cmd.rs
View File

@@ -19,6 +19,10 @@ impl crate::Readable for CmdSpec {}
#[doc = "`write(|w| ..)` method takes [`cmd::W`](W) writer structure"] #[doc = "`write(|w| ..)` method takes [`cmd::W`](W) writer structure"]
impl crate::Writable for CmdSpec { impl crate::Writable for CmdSpec {
type Safety = crate::Unsafe; type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
} }
#[doc = "`reset()` method sets CMD to value 0"] #[doc = "`reset()` method sets CMD to value 0"]
impl crate::Resettable for CmdSpec {} impl crate::Resettable for CmdSpec {
const RESET_VALUE: u32 = 0;
}

24
va108xx/src/i2ca/ctrl.rs
View File

@@ -88,47 +88,47 @@ impl R {
impl W { impl W {
#[doc = "Bit 0 - I2C CLK Enabled"] #[doc = "Bit 0 - I2C CLK Enabled"]
#[inline(always)] #[inline(always)]
pub fn clkenabled(&mut self) -> ClkenabledW<'_, CtrlSpec> { pub fn clkenabled(&mut self) -> ClkenabledW<CtrlSpec> {
ClkenabledW::new(self, 0) ClkenabledW::new(self, 0)
} }
#[doc = "Bit 1 - I2C Activated"] #[doc = "Bit 1 - I2C Activated"]
#[inline(always)] #[inline(always)]
pub fn enabled(&mut self) -> EnabledW<'_, CtrlSpec> { pub fn enabled(&mut self) -> EnabledW<CtrlSpec> {
EnabledW::new(self, 1) EnabledW::new(self, 1)
} }
#[doc = "Bit 2 - I2C Active"] #[doc = "Bit 2 - I2C Active"]
#[inline(always)] #[inline(always)]
pub fn enable(&mut self) -> EnableW<'_, CtrlSpec> { pub fn enable(&mut self) -> EnableW<CtrlSpec> {
EnableW::new(self, 2) EnableW::new(self, 2)
} }
#[doc = "Bit 3 - TX FIFIO Empty Mode"] #[doc = "Bit 3 - TX FIFIO Empty Mode"]
#[inline(always)] #[inline(always)]
pub fn txfemd(&mut self) -> TxfemdW<'_, CtrlSpec> { pub fn txfemd(&mut self) -> TxfemdW<CtrlSpec> {
TxfemdW::new(self, 3) TxfemdW::new(self, 3)
} }
#[doc = "Bit 4 - RX FIFO Full Mode"] #[doc = "Bit 4 - RX FIFO Full Mode"]
#[inline(always)] #[inline(always)]
pub fn rxffmd(&mut self) -> RxffmdW<'_, CtrlSpec> { pub fn rxffmd(&mut self) -> RxffmdW<CtrlSpec> {
RxffmdW::new(self, 4) RxffmdW::new(self, 4)
} }
#[doc = "Bit 5 - Enable Input Analog Glitch Filter"] #[doc = "Bit 5 - Enable Input Analog Glitch Filter"]
#[inline(always)] #[inline(always)]
pub fn algfilter(&mut self) -> AlgfilterW<'_, CtrlSpec> { pub fn algfilter(&mut self) -> AlgfilterW<CtrlSpec> {
AlgfilterW::new(self, 5) AlgfilterW::new(self, 5)
} }
#[doc = "Bit 6 - Enable Input Digital Glitch Filter"] #[doc = "Bit 6 - Enable Input Digital Glitch Filter"]
#[inline(always)] #[inline(always)]
pub fn dlgfilter(&mut self) -> DlgfilterW<'_, CtrlSpec> { pub fn dlgfilter(&mut self) -> DlgfilterW<CtrlSpec> {
DlgfilterW::new(self, 6) DlgfilterW::new(self, 6)
} }
#[doc = "Bit 8 - Enable LoopBack Mode"] #[doc = "Bit 8 - Enable LoopBack Mode"]
#[inline(always)] #[inline(always)]
pub fn loopback(&mut self) -> LoopbackW<'_, CtrlSpec> { pub fn loopback(&mut self) -> LoopbackW<CtrlSpec> {
LoopbackW::new(self, 8) LoopbackW::new(self, 8)
} }
#[doc = "Bit 9 - Enable Timing Config Register"] #[doc = "Bit 9 - Enable Timing Config Register"]
#[inline(always)] #[inline(always)]
pub fn tmconfigenb(&mut self) -> TmconfigenbW<'_, CtrlSpec> { pub fn tmconfigenb(&mut self) -> TmconfigenbW<CtrlSpec> {
TmconfigenbW::new(self, 9) TmconfigenbW::new(self, 9)
} }
} }
@@ -142,6 +142,10 @@ impl crate::Readable for CtrlSpec {}
#[doc = "`write(|w| ..)` method takes [`ctrl::W`](W) writer structure"] #[doc = "`write(|w| ..)` method takes [`ctrl::W`](W) writer structure"]
impl crate::Writable for CtrlSpec { impl crate::Writable for CtrlSpec {
type Safety = crate::Unsafe; type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
} }
#[doc = "`reset()` method sets CTRL to value 0"] #[doc = "`reset()` method sets CTRL to value 0"]
impl crate::Resettable for CtrlSpec {} impl crate::Resettable for CtrlSpec {
const RESET_VALUE: u32 = 0;
}

6
va108xx/src/i2ca/data.rs
View File

@@ -19,6 +19,10 @@ impl crate::Readable for DataSpec {}
#[doc = "`write(|w| ..)` method takes [`data::W`](W) writer structure"] #[doc = "`write(|w| ..)` method takes [`data::W`](W) writer structure"]
impl crate::Writable for DataSpec { impl crate::Writable for DataSpec {
type Safety = crate::Unsafe; type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
} }
#[doc = "`reset()` method sets DATA to value 0"] #[doc = "`reset()` method sets DATA to value 0"]
impl crate::Resettable for DataSpec {} impl crate::Resettable for DataSpec {
const RESET_VALUE: u32 = 0;
}

10
va108xx/src/i2ca/fifo_clr.rs
View File

@@ -7,12 +7,12 @@ pub type TxfifoW<'a, REG> = crate::BitWriter<'a, REG>;
impl W { impl W {
#[doc = "Bit 0 - Clear Rx FIFO"] #[doc = "Bit 0 - Clear Rx FIFO"]
#[inline(always)] #[inline(always)]
pub fn rxfifo(&mut self) -> RxfifoW<'_, FifoClrSpec> { pub fn rxfifo(&mut self) -> RxfifoW<FifoClrSpec> {
RxfifoW::new(self, 0) RxfifoW::new(self, 0)
} }
#[doc = "Bit 1 - Clear Tx FIFO"] #[doc = "Bit 1 - Clear Tx FIFO"]
#[inline(always)] #[inline(always)]
pub fn txfifo(&mut self) -> TxfifoW<'_, FifoClrSpec> { pub fn txfifo(&mut self) -> TxfifoW<FifoClrSpec> {
TxfifoW::new(self, 1) TxfifoW::new(self, 1)
} }
} }
@@ -24,6 +24,10 @@ impl crate::RegisterSpec for FifoClrSpec {
#[doc = "`write(|w| ..)` method takes [`fifo_clr::W`](W) writer structure"] #[doc = "`write(|w| ..)` method takes [`fifo_clr::W`](W) writer structure"]
impl crate::Writable for FifoClrSpec { impl crate::Writable for FifoClrSpec {
type Safety = crate::Unsafe; type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
} }
#[doc = "`reset()` method sets FIFO_CLR to value 0"] #[doc = "`reset()` method sets FIFO_CLR to value 0"]
impl crate::Resettable for FifoClrSpec {} impl crate::Resettable for FifoClrSpec {
const RESET_VALUE: u32 = 0;
}

34
va108xx/src/i2ca/irq_enb.rs
View File

@@ -133,72 +133,72 @@ impl R {
impl W { impl W {
#[doc = "Bit 0 - I2C Bus is Idle"] #[doc = "Bit 0 - I2C Bus is Idle"]
#[inline(always)] #[inline(always)]
pub fn i2cidle(&mut self) -> I2cidleW<'_, IrqEnbSpec> { pub fn i2cidle(&mut self) -> I2cidleW<IrqEnbSpec> {
I2cidleW::new(self, 0) I2cidleW::new(self, 0)
} }
#[doc = "Bit 1 - Controller is Idle"] #[doc = "Bit 1 - Controller is Idle"]
#[inline(always)] #[inline(always)]
pub fn idle(&mut self) -> IdleW<'_, IrqEnbSpec> { pub fn idle(&mut self) -> IdleW<IrqEnbSpec> {
IdleW::new(self, 1) IdleW::new(self, 1)
} }
#[doc = "Bit 2 - Controller is Waiting"] #[doc = "Bit 2 - Controller is Waiting"]
#[inline(always)] #[inline(always)]
pub fn waiting(&mut self) -> WaitingW<'_, IrqEnbSpec> { pub fn waiting(&mut self) -> WaitingW<IrqEnbSpec> {
WaitingW::new(self, 2) WaitingW::new(self, 2)
} }
#[doc = "Bit 3 - Controller is Stalled"] #[doc = "Bit 3 - Controller is Stalled"]
#[inline(always)] #[inline(always)]
pub fn stalled(&mut self) -> StalledW<'_, IrqEnbSpec> { pub fn stalled(&mut self) -> StalledW<IrqEnbSpec> {
StalledW::new(self, 3) StalledW::new(self, 3)
} }
#[doc = "Bit 4 - I2C Arbitration was lost"] #[doc = "Bit 4 - I2C Arbitration was lost"]
#[inline(always)] #[inline(always)]
pub fn arblost(&mut self) -> ArblostW<'_, IrqEnbSpec> { pub fn arblost(&mut self) -> ArblostW<IrqEnbSpec> {
ArblostW::new(self, 4) ArblostW::new(self, 4)
} }
#[doc = "Bit 5 - I2C Address was not Acknowledged"] #[doc = "Bit 5 - I2C Address was not Acknowledged"]
#[inline(always)] #[inline(always)]
pub fn nackaddr(&mut self) -> NackaddrW<'_, IrqEnbSpec> { pub fn nackaddr(&mut self) -> NackaddrW<IrqEnbSpec> {
NackaddrW::new(self, 5) NackaddrW::new(self, 5)
} }
#[doc = "Bit 6 - I2C Data was not Acknowledged"] #[doc = "Bit 6 - I2C Data was not Acknowledged"]
#[inline(always)] #[inline(always)]
pub fn nackdata(&mut self) -> NackdataW<'_, IrqEnbSpec> { pub fn nackdata(&mut self) -> NackdataW<IrqEnbSpec> {
NackdataW::new(self, 6) NackdataW::new(self, 6)
} }
#[doc = "Bit 7 - I2C Clock Low Timeout"] #[doc = "Bit 7 - I2C Clock Low Timeout"]
#[inline(always)] #[inline(always)]
pub fn clkloto(&mut self) -> ClklotoW<'_, IrqEnbSpec> { pub fn clkloto(&mut self) -> ClklotoW<IrqEnbSpec> {
ClklotoW::new(self, 7) ClklotoW::new(self, 7)
} }
#[doc = "Bit 10 - TX FIFO Overflowed"] #[doc = "Bit 10 - TX FIFO Overflowed"]
#[inline(always)] #[inline(always)]
pub fn txoverflow(&mut self) -> TxoverflowW<'_, IrqEnbSpec> { pub fn txoverflow(&mut self) -> TxoverflowW<IrqEnbSpec> {
TxoverflowW::new(self, 10) TxoverflowW::new(self, 10)
} }
#[doc = "Bit 11 - TX FIFO Overflowed"] #[doc = "Bit 11 - TX FIFO Overflowed"]
#[inline(always)] #[inline(always)]
pub fn rxoverflow(&mut self) -> RxoverflowW<'_, IrqEnbSpec> { pub fn rxoverflow(&mut self) -> RxoverflowW<IrqEnbSpec> {
RxoverflowW::new(self, 11) RxoverflowW::new(self, 11)
} }
#[doc = "Bit 12 - TX FIFO Ready"] #[doc = "Bit 12 - TX FIFO Ready"]
#[inline(always)] #[inline(always)]
pub fn txready(&mut self) -> TxreadyW<'_, IrqEnbSpec> { pub fn txready(&mut self) -> TxreadyW<IrqEnbSpec> {
TxreadyW::new(self, 12) TxreadyW::new(self, 12)
} }
#[doc = "Bit 13 - RX FIFO Ready"] #[doc = "Bit 13 - RX FIFO Ready"]
#[inline(always)] #[inline(always)]
pub fn rxready(&mut self) -> RxreadyW<'_, IrqEnbSpec> { pub fn rxready(&mut self) -> RxreadyW<IrqEnbSpec> {
RxreadyW::new(self, 13) RxreadyW::new(self, 13)
} }
#[doc = "Bit 14 - TX FIFO Empty"] #[doc = "Bit 14 - TX FIFO Empty"]
#[inline(always)] #[inline(always)]
pub fn txempty(&mut self) -> TxemptyW<'_, IrqEnbSpec> { pub fn txempty(&mut self) -> TxemptyW<IrqEnbSpec> {
TxemptyW::new(self, 14) TxemptyW::new(self, 14)
} }
#[doc = "Bit 15 - RX FIFO Full"] #[doc = "Bit 15 - RX FIFO Full"]
#[inline(always)] #[inline(always)]
pub fn rxfull(&mut self) -> RxfullW<'_, IrqEnbSpec> { pub fn rxfull(&mut self) -> RxfullW<IrqEnbSpec> {
RxfullW::new(self, 15) RxfullW::new(self, 15)
} }
} }
@@ -212,6 +212,10 @@ impl crate::Readable for IrqEnbSpec {}
#[doc = "`write(|w| ..)` method takes [`irq_enb::W`](W) writer structure"] #[doc = "`write(|w| ..)` method takes [`irq_enb::W`](W) writer structure"]
impl crate::Writable for IrqEnbSpec { impl crate::Writable for IrqEnbSpec {
type Safety = crate::Unsafe; type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
} }
#[doc = "`reset()` method sets IRQ_ENB to value 0"] #[doc = "`reset()` method sets IRQ_ENB to value 0"]
impl crate::Resettable for IrqEnbSpec {} impl crate::Resettable for IrqEnbSpec {
const RESET_VALUE: u32 = 0;
}

4
va108xx/src/i2ca/rxcount.rs
View File

@@ -14,4 +14,6 @@ impl crate::RegisterSpec for RxcountSpec {
#[doc = "`read()` method returns [`rxcount::R`](R) reader structure"] #[doc = "`read()` method returns [`rxcount::R`](R) reader structure"]
impl crate::Readable for RxcountSpec {} impl crate::Readable for RxcountSpec {}
#[doc = "`reset()` method sets RXCOUNT to value 0"] #[doc = "`reset()` method sets RXCOUNT to value 0"]
impl crate::Resettable for RxcountSpec {} impl crate::Resettable for RxcountSpec {
const RESET_VALUE: u32 = 0;
}

6
va108xx/src/i2ca/rxfifoirqtrg.rs
View File

@@ -19,6 +19,10 @@ impl crate::Readable for RxfifoirqtrgSpec {}
#[doc = "`write(|w| ..)` method takes [`rxfifoirqtrg::W`](W) writer structure"] #[doc = "`write(|w| ..)` method takes [`rxfifoirqtrg::W`](W) writer structure"]
impl crate::Writable for RxfifoirqtrgSpec { impl crate::Writable for RxfifoirqtrgSpec {
type Safety = crate::Unsafe; type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
} }
#[doc = "`reset()` method sets RXFIFOIRQTRG to value 0"] #[doc = "`reset()` method sets RXFIFOIRQTRG to value 0"]
impl crate::Resettable for RxfifoirqtrgSpec {} impl crate::Resettable for RxfifoirqtrgSpec {
const RESET_VALUE: u32 = 0;
}

6
va108xx/src/i2ca/s0_address.rs
View File

@@ -19,6 +19,10 @@ impl crate::Readable for S0AddressSpec {}
#[doc = "`write(|w| ..)` method takes [`s0_address::W`](W) writer structure"] #[doc = "`write(|w| ..)` method takes [`s0_address::W`](W) writer structure"]
impl crate::Writable for S0AddressSpec { impl crate::Writable for S0AddressSpec {
type Safety = crate::Unsafe; type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
} }
#[doc = "`reset()` method sets S0_ADDRESS to value 0"] #[doc = "`reset()` method sets S0_ADDRESS to value 0"]
impl crate::Resettable for S0AddressSpec {} impl crate::Resettable for S0AddressSpec {
const RESET_VALUE: u32 = 0;
}

6
va108xx/src/i2ca/s0_addressb.rs
View File

@@ -19,6 +19,10 @@ impl crate::Readable for S0AddressbSpec {}
#[doc = "`write(|w| ..)` method takes [`s0_addressb::W`](W) writer structure"] #[doc = "`write(|w| ..)` method takes [`s0_addressb::W`](W) writer structure"]
impl crate::Writable for S0AddressbSpec { impl crate::Writable for S0AddressbSpec {
type Safety = crate::Unsafe; type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
} }
#[doc = "`reset()` method sets S0_ADDRESSB to value 0"] #[doc = "`reset()` method sets S0_ADDRESSB to value 0"]
impl crate::Resettable for S0AddressbSpec {} impl crate::Resettable for S0AddressbSpec {
const RESET_VALUE: u32 = 0;
}

6
va108xx/src/i2ca/s0_addressmask.rs
View File

@@ -19,6 +19,10 @@ impl crate::Readable for S0AddressmaskSpec {}
#[doc = "`write(|w| ..)` method takes [`s0_addressmask::W`](W) writer structure"] #[doc = "`write(|w| ..)` method takes [`s0_addressmask::W`](W) writer structure"]
impl crate::Writable for S0AddressmaskSpec { impl crate::Writable for S0AddressmaskSpec {
type Safety = crate::Unsafe; type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
} }
#[doc = "`reset()` method sets S0_ADDRESSMASK to value 0"] #[doc = "`reset()` method sets S0_ADDRESSMASK to value 0"]
impl crate::Resettable for S0AddressmaskSpec {} impl crate::Resettable for S0AddressmaskSpec {
const RESET_VALUE: u32 = 0;
}

6
va108xx/src/i2ca/s0_addressmaskb.rs
View File

@@ -19,6 +19,10 @@ impl crate::Readable for S0AddressmaskbSpec {}
#[doc = "`write(|w| ..)` method takes [`s0_addressmaskb::W`](W) writer structure"] #[doc = "`write(|w| ..)` method takes [`s0_addressmaskb::W`](W) writer structure"]
impl crate::Writable for S0AddressmaskbSpec { impl crate::Writable for S0AddressmaskbSpec {
type Safety = crate::Unsafe; type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
} }
#[doc = "`reset()` method sets S0_ADDRESSMASKB to value 0"] #[doc = "`reset()` method sets S0_ADDRESSMASKB to value 0"]
impl crate::Resettable for S0AddressmaskbSpec {} impl crate::Resettable for S0AddressmaskbSpec {
const RESET_VALUE: u32 = 0;
}

16
va108xx/src/i2ca/s0_ctrl.rs
View File

@@ -52,27 +52,27 @@ impl R {
impl W { impl W {
#[doc = "Bit 0 - I2C Enabled"] #[doc = "Bit 0 - I2C Enabled"]
#[inline(always)] #[inline(always)]
pub fn clkenabled(&mut self) -> ClkenabledW<'_, S0CtrlSpec> { pub fn clkenabled(&mut self) -> ClkenabledW<S0CtrlSpec> {
ClkenabledW::new(self, 0) ClkenabledW::new(self, 0)
} }
#[doc = "Bit 1 - I2C Activated"] #[doc = "Bit 1 - I2C Activated"]
#[inline(always)] #[inline(always)]
pub fn enabled(&mut self) -> EnabledW<'_, S0CtrlSpec> { pub fn enabled(&mut self) -> EnabledW<S0CtrlSpec> {
EnabledW::new(self, 1) EnabledW::new(self, 1)
} }
#[doc = "Bit 2 - I2C Active"] #[doc = "Bit 2 - I2C Active"]
#[inline(always)] #[inline(always)]
pub fn enable(&mut self) -> EnableW<'_, S0CtrlSpec> { pub fn enable(&mut self) -> EnableW<S0CtrlSpec> {
EnableW::new(self, 2) EnableW::new(self, 2)
} }
#[doc = "Bit 3 - TX FIFIO Empty Mode"] #[doc = "Bit 3 - TX FIFIO Empty Mode"]
#[inline(always)] #[inline(always)]
pub fn txfemd(&mut self) -> TxfemdW<'_, S0CtrlSpec> { pub fn txfemd(&mut self) -> TxfemdW<S0CtrlSpec> {
TxfemdW::new(self, 3) TxfemdW::new(self, 3)
} }
#[doc = "Bit 4 - RX FIFO Full Mode"] #[doc = "Bit 4 - RX FIFO Full Mode"]
#[inline(always)] #[inline(always)]
pub fn rxffmd(&mut self) -> RxffmdW<'_, S0CtrlSpec> { pub fn rxffmd(&mut self) -> RxffmdW<S0CtrlSpec> {
RxffmdW::new(self, 4) RxffmdW::new(self, 4)
} }
} }
@@ -86,6 +86,10 @@ impl crate::Readable for S0CtrlSpec {}
#[doc = "`write(|w| ..)` method takes [`s0_ctrl::W`](W) writer structure"] #[doc = "`write(|w| ..)` method takes [`s0_ctrl::W`](W) writer structure"]
impl crate::Writable for S0CtrlSpec { impl crate::Writable for S0CtrlSpec {
type Safety = crate::Unsafe; type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
} }
#[doc = "`reset()` method sets S0_CTRL to value 0"] #[doc = "`reset()` method sets S0_CTRL to value 0"]
impl crate::Resettable for S0CtrlSpec {} impl crate::Resettable for S0CtrlSpec {
const RESET_VALUE: u32 = 0;
}

6
va108xx/src/i2ca/s0_data.rs
View File

@@ -19,6 +19,10 @@ impl crate::Readable for S0DataSpec {}
#[doc = "`write(|w| ..)` method takes [`s0_data::W`](W) writer structure"] #[doc = "`write(|w| ..)` method takes [`s0_data::W`](W) writer structure"]
impl crate::Writable for S0DataSpec { impl crate::Writable for S0DataSpec {
type Safety = crate::Unsafe; type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
} }
#[doc = "`reset()` method sets S0_DATA to value 0"] #[doc = "`reset()` method sets S0_DATA to value 0"]
impl crate::Resettable for S0DataSpec {} impl crate::Resettable for S0DataSpec {
const RESET_VALUE: u32 = 0;
}

10
va108xx/src/i2ca/s0_fifo_clr.rs
View File

@@ -7,12 +7,12 @@ pub type TxfifoW<'a, REG> = crate::BitWriter<'a, REG>;
impl W { impl W {
#[doc = "Bit 0 - Clear Rx FIFO"] #[doc = "Bit 0 - Clear Rx FIFO"]
#[inline(always)] #[inline(always)]
pub fn rxfifo(&mut self) -> RxfifoW<'_, S0FifoClrSpec> { pub fn rxfifo(&mut self) -> RxfifoW<S0FifoClrSpec> {
RxfifoW::new(self, 0) RxfifoW::new(self, 0)
} }
#[doc = "Bit 1 - Clear Tx FIFO"] #[doc = "Bit 1 - Clear Tx FIFO"]
#[inline(always)] #[inline(always)]
pub fn txfifo(&mut self) -> TxfifoW<'_, S0FifoClrSpec> { pub fn txfifo(&mut self) -> TxfifoW<S0FifoClrSpec> {
TxfifoW::new(self, 1) TxfifoW::new(self, 1)
} }
} }
@@ -24,6 +24,10 @@ impl crate::RegisterSpec for S0FifoClrSpec {
#[doc = "`write(|w| ..)` method takes [`s0_fifo_clr::W`](W) writer structure"] #[doc = "`write(|w| ..)` method takes [`s0_fifo_clr::W`](W) writer structure"]
impl crate::Writable for S0FifoClrSpec { impl crate::Writable for S0FifoClrSpec {
type Safety = crate::Unsafe; type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
} }
#[doc = "`reset()` method sets S0_FIFO_CLR to value 0"] #[doc = "`reset()` method sets S0_FIFO_CLR to value 0"]
impl crate::Resettable for S0FifoClrSpec {} impl crate::Resettable for S0FifoClrSpec {
const RESET_VALUE: u32 = 0;
}

38
va108xx/src/i2ca/s0_irq_enb.rs
View File

@@ -151,82 +151,82 @@ impl R {
impl W { impl W {
#[doc = "Bit 0 - Controller Complted a Transaction"] #[doc = "Bit 0 - Controller Complted a Transaction"]
#[inline(always)] #[inline(always)]
pub fn completed(&mut self) -> CompletedW<'_, S0IrqEnbSpec> { pub fn completed(&mut self) -> CompletedW<S0IrqEnbSpec> {
CompletedW::new(self, 0) CompletedW::new(self, 0)
} }
#[doc = "Bit 1 - Controller is Idle"] #[doc = "Bit 1 - Controller is Idle"]
#[inline(always)] #[inline(always)]
pub fn idle(&mut self) -> IdleW<'_, S0IrqEnbSpec> { pub fn idle(&mut self) -> IdleW<S0IrqEnbSpec> {
IdleW::new(self, 1) IdleW::new(self, 1)
} }
#[doc = "Bit 2 - Controller is Waiting"] #[doc = "Bit 2 - Controller is Waiting"]
#[inline(always)] #[inline(always)]
pub fn waiting(&mut self) -> WaitingW<'_, S0IrqEnbSpec> { pub fn waiting(&mut self) -> WaitingW<S0IrqEnbSpec> {
WaitingW::new(self, 2) WaitingW::new(self, 2)
} }
#[doc = "Bit 3 - Controller is Tx Stalled"] #[doc = "Bit 3 - Controller is Tx Stalled"]
#[inline(always)] #[inline(always)]
pub fn txstalled(&mut self) -> TxstalledW<'_, S0IrqEnbSpec> { pub fn txstalled(&mut self) -> TxstalledW<S0IrqEnbSpec> {
TxstalledW::new(self, 3) TxstalledW::new(self, 3)
} }
#[doc = "Bit 4 - Controller is Rx Stalled"] #[doc = "Bit 4 - Controller is Rx Stalled"]
#[inline(always)] #[inline(always)]
pub fn rxstalled(&mut self) -> RxstalledW<'_, S0IrqEnbSpec> { pub fn rxstalled(&mut self) -> RxstalledW<S0IrqEnbSpec> {
RxstalledW::new(self, 4) RxstalledW::new(self, 4)
} }
#[doc = "Bit 5 - I2C Address Match"] #[doc = "Bit 5 - I2C Address Match"]
#[inline(always)] #[inline(always)]
pub fn addressmatch(&mut self) -> AddressmatchW<'_, S0IrqEnbSpec> { pub fn addressmatch(&mut self) -> AddressmatchW<S0IrqEnbSpec> {
AddressmatchW::new(self, 5) AddressmatchW::new(self, 5)
} }
#[doc = "Bit 6 - I2C Data was not Acknowledged"] #[doc = "Bit 6 - I2C Data was not Acknowledged"]
#[inline(always)] #[inline(always)]
pub fn nackdata(&mut self) -> NackdataW<'_, S0IrqEnbSpec> { pub fn nackdata(&mut self) -> NackdataW<S0IrqEnbSpec> {
NackdataW::new(self, 6) NackdataW::new(self, 6)
} }
#[doc = "Bit 7 - Pending Data is first Byte following Address"] #[doc = "Bit 7 - Pending Data is first Byte following Address"]
#[inline(always)] #[inline(always)]
pub fn rxdatafirst(&mut self) -> RxdatafirstW<'_, S0IrqEnbSpec> { pub fn rxdatafirst(&mut self) -> RxdatafirstW<S0IrqEnbSpec> {
RxdatafirstW::new(self, 7) RxdatafirstW::new(self, 7)
} }
#[doc = "Bit 8 - I2C Start Condition"] #[doc = "Bit 8 - I2C Start Condition"]
#[inline(always)] #[inline(always)]
pub fn i2c_start(&mut self) -> I2cStartW<'_, S0IrqEnbSpec> { pub fn i2c_start(&mut self) -> I2cStartW<S0IrqEnbSpec> {
I2cStartW::new(self, 8) I2cStartW::new(self, 8)
} }
#[doc = "Bit 9 - I2C Stop Condition"] #[doc = "Bit 9 - I2C Stop Condition"]
#[inline(always)] #[inline(always)]
pub fn i2c_stop(&mut self) -> I2cStopW<'_, S0IrqEnbSpec> { pub fn i2c_stop(&mut self) -> I2cStopW<S0IrqEnbSpec> {
I2cStopW::new(self, 9) I2cStopW::new(self, 9)
} }
#[doc = "Bit 10 - TX FIFO Underflowed"] #[doc = "Bit 10 - TX FIFO Underflowed"]
#[inline(always)] #[inline(always)]
pub fn txunderflow(&mut self) -> TxunderflowW<'_, S0IrqEnbSpec> { pub fn txunderflow(&mut self) -> TxunderflowW<S0IrqEnbSpec> {
TxunderflowW::new(self, 10) TxunderflowW::new(self, 10)
} }
#[doc = "Bit 11 - TX FIFO Overflowed"] #[doc = "Bit 11 - TX FIFO Overflowed"]
#[inline(always)] #[inline(always)]
pub fn rxoverflow(&mut self) -> RxoverflowW<'_, S0IrqEnbSpec> { pub fn rxoverflow(&mut self) -> RxoverflowW<S0IrqEnbSpec> {
RxoverflowW::new(self, 11) RxoverflowW::new(self, 11)
} }
#[doc = "Bit 12 - TX FIFO Ready"] #[doc = "Bit 12 - TX FIFO Ready"]
#[inline(always)] #[inline(always)]
pub fn txready(&mut self) -> TxreadyW<'_, S0IrqEnbSpec> { pub fn txready(&mut self) -> TxreadyW<S0IrqEnbSpec> {
TxreadyW::new(self, 12) TxreadyW::new(self, 12)
} }
#[doc = "Bit 13 - RX FIFO Ready"] #[doc = "Bit 13 - RX FIFO Ready"]
#[inline(always)] #[inline(always)]
pub fn rxready(&mut self) -> RxreadyW<'_, S0IrqEnbSpec> { pub fn rxready(&mut self) -> RxreadyW<S0IrqEnbSpec> {
RxreadyW::new(self, 13) RxreadyW::new(self, 13)
} }
#[doc = "Bit 14 - TX FIFO Empty"] #[doc = "Bit 14 - TX FIFO Empty"]
#[inline(always)] #[inline(always)]
pub fn txempty(&mut self) -> TxemptyW<'_, S0IrqEnbSpec> { pub fn txempty(&mut self) -> TxemptyW<S0IrqEnbSpec> {
TxemptyW::new(self, 14) TxemptyW::new(self, 14)
} }
#[doc = "Bit 15 - RX FIFO Full"] #[doc = "Bit 15 - RX FIFO Full"]
#[inline(always)] #[inline(always)]
pub fn rxfull(&mut self) -> RxfullW<'_, S0IrqEnbSpec> { pub fn rxfull(&mut self) -> RxfullW<S0IrqEnbSpec> {
RxfullW::new(self, 15) RxfullW::new(self, 15)
} }
} }
@@ -240,6 +240,10 @@ impl crate::Readable for S0IrqEnbSpec {}
#[doc = "`write(|w| ..)` method takes [`s0_irq_enb::W`](W) writer structure"] #[doc = "`write(|w| ..)` method takes [`s0_irq_enb::W`](W) writer structure"]
impl crate::Writable for S0IrqEnbSpec { impl crate::Writable for S0IrqEnbSpec {
type Safety = crate::Unsafe; type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
} }
#[doc = "`reset()` method sets S0_IRQ_ENB to value 0"] #[doc = "`reset()` method sets S0_IRQ_ENB to value 0"]
impl crate::Resettable for S0IrqEnbSpec {} impl crate::Resettable for S0IrqEnbSpec {
const RESET_VALUE: u32 = 0;
}

4
va108xx/src/i2ca/s0_lastaddress.rs
View File

@@ -14,4 +14,6 @@ impl crate::RegisterSpec for S0LastaddressSpec {
#[doc = "`read()` method returns [`s0_lastaddress::R`](R) reader structure"] #[doc = "`read()` method returns [`s0_lastaddress::R`](R) reader structure"]
impl crate::Readable for S0LastaddressSpec {} impl crate::Readable for S0LastaddressSpec {}
#[doc = "`reset()` method sets S0_LASTADDRESS to value 0"] #[doc = "`reset()` method sets S0_LASTADDRESS to value 0"]
impl crate::Resettable for S0LastaddressSpec {} impl crate::Resettable for S0LastaddressSpec {
const RESET_VALUE: u32 = 0;
}

6
va108xx/src/i2ca/s0_maxwords.rs
View File

@@ -19,6 +19,10 @@ impl crate::Readable for S0MaxwordsSpec {}
#[doc = "`write(|w| ..)` method takes [`s0_maxwords::W`](W) writer structure"] #[doc = "`write(|w| ..)` method takes [`s0_maxwords::W`](W) writer structure"]
impl crate::Writable for S0MaxwordsSpec { impl crate::Writable for S0MaxwordsSpec {
type Safety = crate::Unsafe; type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
} }
#[doc = "`reset()` method sets S0_MAXWORDS to value 0"] #[doc = "`reset()` method sets S0_MAXWORDS to value 0"]
impl crate::Resettable for S0MaxwordsSpec {} impl crate::Resettable for S0MaxwordsSpec {
const RESET_VALUE: u32 = 0;
}

4
va108xx/src/i2ca/s0_rxcount.rs
View File

@@ -14,4 +14,6 @@ impl crate::RegisterSpec for S0RxcountSpec {
#[doc = "`read()` method returns [`s0_rxcount::R`](R) reader structure"] #[doc = "`read()` method returns [`s0_rxcount::R`](R) reader structure"]
impl crate::Readable for S0RxcountSpec {} impl crate::Readable for S0RxcountSpec {}
#[doc = "`reset()` method sets S0_RXCOUNT to value 0"] #[doc = "`reset()` method sets S0_RXCOUNT to value 0"]
impl crate::Resettable for S0RxcountSpec {} impl crate::Resettable for S0RxcountSpec {
const RESET_VALUE: u32 = 0;
}

6
va108xx/src/i2ca/s0_rxfifoirqtrg.rs
View File

@@ -19,6 +19,10 @@ impl crate::Readable for S0RxfifoirqtrgSpec {}
#[doc = "`write(|w| ..)` method takes [`s0_rxfifoirqtrg::W`](W) writer structure"] #[doc = "`write(|w| ..)` method takes [`s0_rxfifoirqtrg::W`](W) writer structure"]
impl crate::Writable for S0RxfifoirqtrgSpec { impl crate::Writable for S0RxfifoirqtrgSpec {
type Safety = crate::Unsafe; type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
} }
#[doc = "`reset()` method sets S0_RXFIFOIRQTRG to value 0"] #[doc = "`reset()` method sets S0_RXFIFOIRQTRG to value 0"]
impl crate::Resettable for S0RxfifoirqtrgSpec {} impl crate::Resettable for S0RxfifoirqtrgSpec {
const RESET_VALUE: u32 = 0;
}

4
va108xx/src/i2ca/s0_state.rs
View File

@@ -14,4 +14,6 @@ impl crate::RegisterSpec for S0StateSpec {
#[doc = "`read()` method returns [`s0_state::R`](R) reader structure"] #[doc = "`read()` method returns [`s0_state::R`](R) reader structure"]
impl crate::Readable for S0StateSpec {} impl crate::Readable for S0StateSpec {}
#[doc = "`reset()` method sets S0_STATE to value 0"] #[doc = "`reset()` method sets S0_STATE to value 0"]
impl crate::Resettable for S0StateSpec {} impl crate::Resettable for S0StateSpec {
const RESET_VALUE: u32 = 0;
}

4
va108xx/src/i2ca/s0_status.rs
View File

@@ -129,4 +129,6 @@ impl crate::RegisterSpec for S0StatusSpec {
#[doc = "`read()` method returns [`s0_status::R`](R) reader structure"] #[doc = "`read()` method returns [`s0_status::R`](R) reader structure"]
impl crate::Readable for S0StatusSpec {} impl crate::Readable for S0StatusSpec {}
#[doc = "`reset()` method sets S0_STATUS to value 0"] #[doc = "`reset()` method sets S0_STATUS to value 0"]
impl crate::Resettable for S0StatusSpec {} impl crate::Resettable for S0StatusSpec {
const RESET_VALUE: u32 = 0;
}

4
va108xx/src/i2ca/s0_txcount.rs
View File

@@ -14,4 +14,6 @@ impl crate::RegisterSpec for S0TxcountSpec {
#[doc = "`read()` method returns [`s0_txcount::R`](R) reader structure"] #[doc = "`read()` method returns [`s0_txcount::R`](R) reader structure"]
impl crate::Readable for S0TxcountSpec {} impl crate::Readable for S0TxcountSpec {}
#[doc = "`reset()` method sets S0_TXCOUNT to value 0"] #[doc = "`reset()` method sets S0_TXCOUNT to value 0"]
impl crate::Resettable for S0TxcountSpec {} impl crate::Resettable for S0TxcountSpec {
const RESET_VALUE: u32 = 0;
}

6
va108xx/src/i2ca/s0_txfifoirqtrg.rs
View File

@@ -19,6 +19,10 @@ impl crate::Readable for S0TxfifoirqtrgSpec {}
#[doc = "`write(|w| ..)` method takes [`s0_txfifoirqtrg::W`](W) writer structure"] #[doc = "`write(|w| ..)` method takes [`s0_txfifoirqtrg::W`](W) writer structure"]
impl crate::Writable for S0TxfifoirqtrgSpec { impl crate::Writable for S0TxfifoirqtrgSpec {
type Safety = crate::Unsafe; type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
} }
#[doc = "`reset()` method sets S0_TXFIFOIRQTRG to value 0"] #[doc = "`reset()` method sets S0_TXFIFOIRQTRG to value 0"]
impl crate::Resettable for S0TxfifoirqtrgSpec {} impl crate::Resettable for S0TxfifoirqtrgSpec {
const RESET_VALUE: u32 = 0;
}

4
va108xx/src/i2ca/state.rs
View File

@@ -14,4 +14,6 @@ impl crate::RegisterSpec for StateSpec {
#[doc = "`read()` method returns [`state::R`](R) reader structure"] #[doc = "`read()` method returns [`state::R`](R) reader structure"]
impl crate::Readable for StateSpec {} impl crate::Readable for StateSpec {}
#[doc = "`reset()` method sets STATE to value 0"] #[doc = "`reset()` method sets STATE to value 0"]
impl crate::Resettable for StateSpec {} impl crate::Resettable for StateSpec {
const RESET_VALUE: u32 = 0;
}

4
va108xx/src/i2ca/status.rs
View File

@@ -115,4 +115,6 @@ impl crate::RegisterSpec for StatusSpec {
#[doc = "`read()` method returns [`status::R`](R) reader structure"] #[doc = "`read()` method returns [`status::R`](R) reader structure"]
impl crate::Readable for StatusSpec {} impl crate::Readable for StatusSpec {}
#[doc = "`reset()` method sets STATUS to value 0"] #[doc = "`reset()` method sets STATUS to value 0"]
impl crate::Resettable for StatusSpec {} impl crate::Resettable for StatusSpec {
const RESET_VALUE: u32 = 0;
}

6
va108xx/src/i2ca/tmconfig.rs
View File

@@ -19,6 +19,10 @@ impl crate::Readable for TmconfigSpec {}
#[doc = "`write(|w| ..)` method takes [`tmconfig::W`](W) writer structure"] #[doc = "`write(|w| ..)` method takes [`tmconfig::W`](W) writer structure"]
impl crate::Writable for TmconfigSpec { impl crate::Writable for TmconfigSpec {
type Safety = crate::Unsafe; type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
} }
#[doc = "`reset()` method sets TMCONFIG to value 0"] #[doc = "`reset()` method sets TMCONFIG to value 0"]
impl crate::Resettable for TmconfigSpec {} impl crate::Resettable for TmconfigSpec {
const RESET_VALUE: u32 = 0;
}

4
va108xx/src/i2ca/txcount.rs
View File

@@ -14,4 +14,6 @@ impl crate::RegisterSpec for TxcountSpec {
#[doc = "`read()` method returns [`txcount::R`](R) reader structure"] #[doc = "`read()` method returns [`txcount::R`](R) reader structure"]
impl crate::Readable for TxcountSpec {} impl crate::Readable for TxcountSpec {}
#[doc = "`reset()` method sets TXCOUNT to value 0"] #[doc = "`reset()` method sets TXCOUNT to value 0"]
impl crate::Resettable for TxcountSpec {} impl crate::Resettable for TxcountSpec {
const RESET_VALUE: u32 = 0;
}

6
va108xx/src/i2ca/txfifoirqtrg.rs
View File

@@ -19,6 +19,10 @@ impl crate::Readable for TxfifoirqtrgSpec {}
#[doc = "`write(|w| ..)` method takes [`txfifoirqtrg::W`](W) writer structure"] #[doc = "`write(|w| ..)` method takes [`txfifoirqtrg::W`](W) writer structure"]
impl crate::Writable for TxfifoirqtrgSpec { impl crate::Writable for TxfifoirqtrgSpec {
type Safety = crate::Unsafe; type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
} }
#[doc = "`reset()` method sets TXFIFOIRQTRG to value 0"] #[doc = "`reset()` method sets TXFIFOIRQTRG to value 0"]
impl crate::Resettable for TxfifoirqtrgSpec {} impl crate::Resettable for TxfifoirqtrgSpec {
const RESET_VALUE: u32 = 0;
}

6
va108xx/src/i2ca/words.rs
View File

@@ -19,6 +19,10 @@ impl crate::Readable for WordsSpec {}
#[doc = "`write(|w| ..)` method takes [`words::W`](W) writer structure"] #[doc = "`write(|w| ..)` method takes [`words::W`](W) writer structure"]
impl crate::Writable for WordsSpec { impl crate::Writable for WordsSpec {
type Safety = crate::Unsafe; type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
} }
#[doc = "`reset()` method sets WORDS to value 0"] #[doc = "`reset()` method sets WORDS to value 0"]
impl crate::Resettable for WordsSpec {} impl crate::Resettable for WordsSpec {
const RESET_VALUE: u32 = 0;
}

16
va108xx/src/ioconfig.rs
View File

@@ -2,7 +2,7 @@
#[doc = "Register block"] #[doc = "Register block"]
pub struct RegisterBlock { pub struct RegisterBlock {
porta: [Porta; 32], porta: [Porta; 32],
portb: [Portb; 32], portb0: [Portb; 32],
_reserved2: [u8; 0x0efc], _reserved2: [u8; 0x0efc],
perid: Perid, perid: Perid,
} }
@@ -20,14 +20,14 @@ impl RegisterBlock {
} }
#[doc = "0x80..0x100 - PORTB Pin Configuration Register"] #[doc = "0x80..0x100 - PORTB Pin Configuration Register"]
#[inline(always)] #[inline(always)]
pub const fn portb(&self, n: usize) -> &Portb { pub const fn portb0(&self, n: usize) -> &Portb {
&self.portb[n] &self.portb0[n]
} }
#[doc = "Iterator for array of:"] #[doc = "Iterator for array of:"]
#[doc = "0x80..0x100 - PORTB Pin Configuration Register"] #[doc = "0x80..0x100 - PORTB Pin Configuration Register"]
#[inline(always)] #[inline(always)]
pub fn portb_iter(&self) -> impl Iterator<Item = &Portb> { pub fn portb0_iter(&self) -> impl Iterator<Item = &Portb> {
self.portb.iter() self.portb0.iter()
} }
#[doc = "0xffc - Peripheral ID Register"] #[doc = "0xffc - Peripheral ID Register"]
#[inline(always)] #[inline(always)]
@@ -35,14 +35,16 @@ impl RegisterBlock {
&self.perid &self.perid
} }
} }
#[doc = "PORTA (rw) register accessor: PORTA Pin Configuration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`porta::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`porta::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@porta`] module"] #[doc = "PORTA (rw) register accessor: PORTA Pin Configuration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`porta::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`porta::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@porta`]
module"]
#[doc(alias = "PORTA")] #[doc(alias = "PORTA")]
pub type Porta = crate::Reg<porta::PortaSpec>; pub type Porta = crate::Reg<porta::PortaSpec>;
#[doc = "PORTA Pin Configuration Register"] #[doc = "PORTA Pin Configuration Register"]
pub mod porta; pub mod porta;
pub use porta as portb; pub use porta as portb;
pub use Porta as Portb; pub use Porta as Portb;
#[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`] module"] #[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`]
module"]
#[doc(alias = "PERID")] #[doc(alias = "PERID")]
pub type Perid = crate::Reg<perid::PeridSpec>; pub type Perid = crate::Reg<perid::PeridSpec>;
#[doc = "Peripheral ID Register"] #[doc = "Peripheral ID Register"]

31
va108xx/src/ioconfig/porta.rs
View File

@@ -215,57 +215,57 @@ impl R {
impl W { impl W {
#[doc = "Bits 0:2 - Input Filter Selectoin"] #[doc = "Bits 0:2 - Input Filter Selectoin"]
#[inline(always)] #[inline(always)]
pub fn flttype(&mut self) -> FlttypeW<'_, PortaSpec> { pub fn flttype(&mut self) -> FlttypeW<PortaSpec> {
FlttypeW::new(self, 0) FlttypeW::new(self, 0)
} }
#[doc = "Bits 3:5 - Input Filter Clock Selection"] #[doc = "Bits 3:5 - Input Filter Clock Selection"]
#[inline(always)] #[inline(always)]
pub fn fltclk(&mut self) -> FltclkW<'_, PortaSpec> { pub fn fltclk(&mut self) -> FltclkW<PortaSpec> {
FltclkW::new(self, 3) FltclkW::new(self, 3)
} }
#[doc = "Bit 6 - Input Invert Selection"] #[doc = "Bit 6 - Input Invert Selection"]
#[inline(always)] #[inline(always)]
pub fn invinp(&mut self) -> InvinpW<'_, PortaSpec> { pub fn invinp(&mut self) -> InvinpW<PortaSpec> {
InvinpW::new(self, 6) InvinpW::new(self, 6)
} }
#[doc = "Bit 7 - Input Enable While Output enabled"] #[doc = "Bit 7 - Input Enable While Output enabled"]
#[inline(always)] #[inline(always)]
pub fn iewo(&mut self) -> IewoW<'_, PortaSpec> { pub fn iewo(&mut self) -> IewoW<PortaSpec> {
IewoW::new(self, 7) IewoW::new(self, 7)
} }
#[doc = "Bit 8 - Output Open Drain Mode"] #[doc = "Bit 8 - Output Open Drain Mode"]
#[inline(always)] #[inline(always)]
pub fn opendrn(&mut self) -> OpendrnW<'_, PortaSpec> { pub fn opendrn(&mut self) -> OpendrnW<PortaSpec> {
OpendrnW::new(self, 8) OpendrnW::new(self, 8)
} }
#[doc = "Bit 9 - Output Invert Selection"] #[doc = "Bit 9 - Output Invert Selection"]
#[inline(always)] #[inline(always)]
pub fn invout(&mut self) -> InvoutW<'_, PortaSpec> { pub fn invout(&mut self) -> InvoutW<PortaSpec> {
InvoutW::new(self, 9) InvoutW::new(self, 9)
} }
#[doc = "Bit 10 - Internal Pull up/down level"] #[doc = "Bit 10 - Internal Pull up/down level"]
#[inline(always)] #[inline(always)]
pub fn plevel(&mut self) -> PlevelW<'_, PortaSpec> { pub fn plevel(&mut self) -> PlevelW<PortaSpec> {
PlevelW::new(self, 10) PlevelW::new(self, 10)
} }
#[doc = "Bit 11 - Enable Internal Pull up/down"] #[doc = "Bit 11 - Enable Internal Pull up/down"]
#[inline(always)] #[inline(always)]
pub fn pen(&mut self) -> PenW<'_, PortaSpec> { pub fn pen(&mut self) -> PenW<PortaSpec> {
PenW::new(self, 11) PenW::new(self, 11)
} }
#[doc = "Bit 12 - Enable Pull when output active"] #[doc = "Bit 12 - Enable Pull when output active"]
#[inline(always)] #[inline(always)]
pub fn pwoa(&mut self) -> PwoaW<'_, PortaSpec> { pub fn pwoa(&mut self) -> PwoaW<PortaSpec> {
PwoaW::new(self, 12) PwoaW::new(self, 12)
} }
#[doc = "Bits 13:15 - Pin Function Selection"] #[doc = "Bits 13:15 - Pin Function Selection"]
#[inline(always)] #[inline(always)]
pub fn funsel(&mut self) -> FunselW<'_, PortaSpec> { pub fn funsel(&mut self) -> FunselW<PortaSpec> {
FunselW::new(self, 13) FunselW::new(self, 13)
} }
#[doc = "Bit 16 - IO Pin Disable"] #[doc = "Bit 16 - IO Pin Disable"]
#[inline(always)] #[inline(always)]
pub fn iodis(&mut self) -> IodisW<'_, PortaSpec> { pub fn iodis(&mut self) -> IodisW<PortaSpec> {
IodisW::new(self, 16) IodisW::new(self, 16)
} }
} }
@@ -279,6 +279,11 @@ impl crate::Readable for PortaSpec {}
#[doc = "`write(|w| ..)` method takes [`porta::W`](W) writer structure"] #[doc = "`write(|w| ..)` method takes [`porta::W`](W) writer structure"]
impl crate::Writable for PortaSpec { impl crate::Writable for PortaSpec {
type Safety = crate::Unsafe; type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets PORTA[%s]
to value 0"]
impl crate::Resettable for PortaSpec {
const RESET_VALUE: u32 = 0;
} }
#[doc = "`reset()` method sets PORTA[%s] to value 0"]
impl crate::Resettable for PortaSpec {}

89
va108xx/src/irqsel.rs
View File

@@ -1,20 +1,20 @@
#[repr(C)] #[repr(C)]
#[doc = "Register block"] #[doc = "Register block"]
pub struct RegisterBlock { pub struct RegisterBlock {
porta: [Porta; 32], porta0: [Porta; 32],
portb: [Portb; 32], portb0: [Portb; 32],
tim: [Tim; 32], tim0: [Tim; 32],
uart: [Uart; 4], uart0: [Uart; 4],
spi: [Spi; 4], spi0: [Spi; 4],
i2c_ms: [I2cMs; 4], i2c_ms0: [I2cMs; 4],
i2c_sl: [I2cSl; 4], i2c_sl0: [I2cSl; 4],
int_ram_sbe: IntRamSbe, int_ram_sbe: IntRamSbe,
int_ram_mbe: IntRamMbe, int_ram_mbe: IntRamMbe,
int_rom_sbe: IntRomSbe, int_rom_sbe: IntRomSbe,
int_rom_mbe: IntRomMbe, int_rom_mbe: IntRomMbe,
txev: Txev, txev: Txev,
_reserved12: [u8; 0x062c], _reserved12: [u8; 0x062c],
irqs: [Irqs; 32], irqs0: [Irqs; 32],
_reserved13: [u8; 0x68], _reserved13: [u8; 0x68],
edbgrq: Edbgrq, edbgrq: Edbgrq,
mereset: Mereset, mereset: Mereset,
@@ -27,80 +27,80 @@ pub struct RegisterBlock {
impl RegisterBlock { impl RegisterBlock {
#[doc = "0x00..0x80 - PORTA Interrupt Redirect Selection"] #[doc = "0x00..0x80 - PORTA Interrupt Redirect Selection"]
#[inline(always)] #[inline(always)]
pub const fn porta(&self, n: usize) -> &Porta { pub const fn porta0(&self, n: usize) -> &Porta {
&self.porta[n] &self.porta0[n]
} }
#[doc = "Iterator for array of:"] #[doc = "Iterator for array of:"]
#[doc = "0x00..0x80 - PORTA Interrupt Redirect Selection"] #[doc = "0x00..0x80 - PORTA Interrupt Redirect Selection"]
#[inline(always)] #[inline(always)]
pub fn porta_iter(&self) -> impl Iterator<Item = &Porta> { pub fn porta0_iter(&self) -> impl Iterator<Item = &Porta> {
self.porta.iter() self.porta0.iter()
} }
#[doc = "0x80..0x100 - PORTB Interrupt Redirect Selection"] #[doc = "0x80..0x100 - PORTB Interrupt Redirect Selection"]
#[inline(always)] #[inline(always)]
pub const fn portb(&self, n: usize) -> &Portb { pub const fn portb0(&self, n: usize) -> &Portb {
&self.portb[n] &self.portb0[n]
} }
#[doc = "Iterator for array of:"] #[doc = "Iterator for array of:"]
#[doc = "0x80..0x100 - PORTB Interrupt Redirect Selection"] #[doc = "0x80..0x100 - PORTB Interrupt Redirect Selection"]
#[inline(always)] #[inline(always)]
pub fn portb_iter(&self) -> impl Iterator<Item = &Portb> { pub fn portb0_iter(&self) -> impl Iterator<Item = &Portb> {
self.portb.iter() self.portb0.iter()
} }
#[doc = "0x100..0x180 - TIM Interrupt Redirect Selection"] #[doc = "0x100..0x180 - TIM Interrupt Redirect Selection"]
#[inline(always)] #[inline(always)]
pub const fn tim(&self, n: usize) -> &Tim { pub const fn tim0(&self, n: usize) -> &Tim {
&self.tim[n] &self.tim0[n]
} }
#[doc = "Iterator for array of:"] #[doc = "Iterator for array of:"]
#[doc = "0x100..0x180 - TIM Interrupt Redirect Selection"] #[doc = "0x100..0x180 - TIM Interrupt Redirect Selection"]
#[inline(always)] #[inline(always)]
pub fn tim_iter(&self) -> impl Iterator<Item = &Tim> { pub fn tim0_iter(&self) -> impl Iterator<Item = &Tim> {
self.tim.iter() self.tim0.iter()
} }
#[doc = "0x180..0x190 - UART Interrupt Redirect Selection"] #[doc = "0x180..0x190 - UART Interrupt Redirect Selection"]
#[inline(always)] #[inline(always)]
pub const fn uart(&self, n: usize) -> &Uart { pub const fn uart0(&self, n: usize) -> &Uart {
&self.uart[n] &self.uart0[n]
} }
#[doc = "Iterator for array of:"] #[doc = "Iterator for array of:"]
#[doc = "0x180..0x190 - UART Interrupt Redirect Selection"] #[doc = "0x180..0x190 - UART Interrupt Redirect Selection"]
#[inline(always)] #[inline(always)]
pub fn uart_iter(&self) -> impl Iterator<Item = &Uart> { pub fn uart0_iter(&self) -> impl Iterator<Item = &Uart> {
self.uart.iter() self.uart0.iter()
} }
#[doc = "0x190..0x1a0 - SPI Interrupt Redirect Selection"] #[doc = "0x190..0x1a0 - SPI Interrupt Redirect Selection"]
#[inline(always)] #[inline(always)]
pub const fn spi(&self, n: usize) -> &Spi { pub const fn spi0(&self, n: usize) -> &Spi {
&self.spi[n] &self.spi0[n]
} }
#[doc = "Iterator for array of:"] #[doc = "Iterator for array of:"]
#[doc = "0x190..0x1a0 - SPI Interrupt Redirect Selection"] #[doc = "0x190..0x1a0 - SPI Interrupt Redirect Selection"]
#[inline(always)] #[inline(always)]
pub fn spi_iter(&self) -> impl Iterator<Item = &Spi> { pub fn spi0_iter(&self) -> impl Iterator<Item = &Spi> {
self.spi.iter() self.spi0.iter()
} }
#[doc = "0x1a0..0x1b0 - Master I2C Interrupt Redirect Selection"] #[doc = "0x1a0..0x1b0 - Master I2C Interrupt Redirect Selection"]
#[inline(always)] #[inline(always)]
pub const fn i2c_ms(&self, n: usize) -> &I2cMs { pub const fn i2c_ms0(&self, n: usize) -> &I2cMs {
&self.i2c_ms[n] &self.i2c_ms0[n]
} }
#[doc = "Iterator for array of:"] #[doc = "Iterator for array of:"]
#[doc = "0x1a0..0x1b0 - Master I2C Interrupt Redirect Selection"] #[doc = "0x1a0..0x1b0 - Master I2C Interrupt Redirect Selection"]
#[inline(always)] #[inline(always)]
pub fn i2c_ms_iter(&self) -> impl Iterator<Item = &I2cMs> { pub fn i2c_ms0_iter(&self) -> impl Iterator<Item = &I2cMs> {
self.i2c_ms.iter() self.i2c_ms0.iter()
} }
#[doc = "0x1b0..0x1c0 - Slave I2C Interrupt Redirect Selection"] #[doc = "0x1b0..0x1c0 - Slave I2C Interrupt Redirect Selection"]
#[inline(always)] #[inline(always)]
pub const fn i2c_sl(&self, n: usize) -> &I2cSl { pub const fn i2c_sl0(&self, n: usize) -> &I2cSl {
&self.i2c_sl[n] &self.i2c_sl0[n]
} }
#[doc = "Iterator for array of:"] #[doc = "Iterator for array of:"]
#[doc = "0x1b0..0x1c0 - Slave I2C Interrupt Redirect Selection"] #[doc = "0x1b0..0x1c0 - Slave I2C Interrupt Redirect Selection"]
#[inline(always)] #[inline(always)]
pub fn i2c_sl_iter(&self) -> impl Iterator<Item = &I2cSl> { pub fn i2c_sl0_iter(&self) -> impl Iterator<Item = &I2cSl> {
self.i2c_sl.iter() self.i2c_sl0.iter()
} }
#[doc = "0x1c0 - Internal Memory RAM SBE Interrupt Redirect Selection"] #[doc = "0x1c0 - Internal Memory RAM SBE Interrupt Redirect Selection"]
#[inline(always)] #[inline(always)]
@@ -129,14 +129,14 @@ impl RegisterBlock {
} }
#[doc = "0x800..0x880 - Interrupt Status Register"] #[doc = "0x800..0x880 - Interrupt Status Register"]
#[inline(always)] #[inline(always)]
pub const fn irqs(&self, n: usize) -> &Irqs { pub const fn irqs0(&self, n: usize) -> &Irqs {
&self.irqs[n] &self.irqs0[n]
} }
#[doc = "Iterator for array of:"] #[doc = "Iterator for array of:"]
#[doc = "0x800..0x880 - Interrupt Status Register"] #[doc = "0x800..0x880 - Interrupt Status Register"]
#[inline(always)] #[inline(always)]
pub fn irqs_iter(&self) -> impl Iterator<Item = &Irqs> { pub fn irqs0_iter(&self) -> impl Iterator<Item = &Irqs> {
self.irqs.iter() self.irqs0.iter()
} }
#[doc = "0x8e8 - EDBGRQ Status Register"] #[doc = "0x8e8 - EDBGRQ Status Register"]
#[inline(always)] #[inline(always)]
@@ -169,7 +169,8 @@ impl RegisterBlock {
&self.perid &self.perid
} }
} }
#[doc = "INT_RAM_SBE (rw) register accessor: Internal Memory RAM SBE Interrupt Redirect Selection\n\nYou can [`read`](crate::Reg::read) this register and get [`int_ram_sbe::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_ram_sbe::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_ram_sbe`] module"] #[doc = "INT_RAM_SBE (rw) register accessor: Internal Memory RAM SBE Interrupt Redirect Selection\n\nYou can [`read`](crate::Reg::read) this register and get [`int_ram_sbe::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_ram_sbe::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_ram_sbe`]
module"]
#[doc(alias = "INT_RAM_SBE")] #[doc(alias = "INT_RAM_SBE")]
pub type IntRamSbe = crate::Reg<int_ram_sbe::IntRamSbeSpec>; pub type IntRamSbe = crate::Reg<int_ram_sbe::IntRamSbeSpec>;
#[doc = "Internal Memory RAM SBE Interrupt Redirect Selection"] #[doc = "Internal Memory RAM SBE Interrupt Redirect Selection"]
@@ -196,7 +197,8 @@ pub use IntRamSbe as IntRamMbe;
pub use IntRamSbe as IntRomSbe; pub use IntRamSbe as IntRomSbe;
pub use IntRamSbe as IntRomMbe; pub use IntRamSbe as IntRomMbe;
pub use IntRamSbe as Txev; pub use IntRamSbe as Txev;
#[doc = "NMI (r) register accessor: NMI Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`nmi::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@nmi`] module"] #[doc = "NMI (r) register accessor: NMI Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`nmi::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@nmi`]
module"]
#[doc(alias = "NMI")] #[doc(alias = "NMI")]
pub type Nmi = crate::Reg<nmi::NmiSpec>; pub type Nmi = crate::Reg<nmi::NmiSpec>;
#[doc = "NMI Status Register"] #[doc = "NMI Status Register"]
@@ -211,7 +213,8 @@ pub use Nmi as Watchdog;
pub use Nmi as Mereset; pub use Nmi as Mereset;
pub use Nmi as Edbgrq; pub use Nmi as Edbgrq;
pub use Nmi as Irqs; pub use Nmi as Irqs;
#[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`] module"] #[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`]
module"]
#[doc(alias = "PERID")] #[doc(alias = "PERID")]
pub type Perid = crate::Reg<perid::PeridSpec>; pub type Perid = crate::Reg<perid::PeridSpec>;
#[doc = "Peripheral ID Register"] #[doc = "Peripheral ID Register"]

2
va108xx/src/irqsel/int_ram_sbe.rs
View File

@@ -19,6 +19,8 @@ impl crate::Readable for IntRamSbeSpec {}
#[doc = "`write(|w| ..)` method takes [`int_ram_sbe::W`](W) writer structure"] #[doc = "`write(|w| ..)` method takes [`int_ram_sbe::W`](W) writer structure"]
impl crate::Writable for IntRamSbeSpec { impl crate::Writable for IntRamSbeSpec {
type Safety = crate::Unsafe; type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
} }
#[doc = "`reset()` method sets INT_RAM_SBE to value 0xffff_ffff"] #[doc = "`reset()` method sets INT_RAM_SBE to value 0xffff_ffff"]
impl crate::Resettable for IntRamSbeSpec { impl crate::Resettable for IntRamSbeSpec {

4
va108xx/src/irqsel/nmi.rs
View File

@@ -17,4 +17,6 @@ impl crate::RegisterSpec for NmiSpec {
#[doc = "`read()` method returns [`nmi::R`](R) reader structure"] #[doc = "`read()` method returns [`nmi::R`](R) reader structure"]
impl crate::Readable for NmiSpec {} impl crate::Readable for NmiSpec {}
#[doc = "`reset()` method sets NMI to value 0"] #[doc = "`reset()` method sets NMI to value 0"]
impl crate::Resettable for NmiSpec {} impl crate::Resettable for NmiSpec {
const RESET_VALUE: u32 = 0;
}

1449
va108xx/src/lib.rs
View File

File diff suppressed because it is too large Load Diff

82
va108xx/src/porta.rs
View File

@@ -45,7 +45,7 @@ impl RegisterBlock {
} }
#[doc = "0x04 - Data In Raw Register by Byte"] #[doc = "0x04 - Data In Raw Register by Byte"]
#[inline(always)] #[inline(always)]
pub const fn datainrawbyte(&self, n: usize) -> &Datainrawbyte { pub const fn datainrawbyte0(&self, n: usize) -> &Datainrawbyte {
#[allow(clippy::no_effect)] #[allow(clippy::no_effect)]
[(); 4][n]; [(); 4][n];
unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(4).add(n).cast() } unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(4).add(n).cast() }
@@ -53,7 +53,7 @@ impl RegisterBlock {
#[doc = "Iterator for array of:"] #[doc = "Iterator for array of:"]
#[doc = "0x04 - Data In Raw Register by Byte"] #[doc = "0x04 - Data In Raw Register by Byte"]
#[inline(always)] #[inline(always)]
pub fn datainrawbyte_iter(&self) -> impl Iterator<Item = &Datainrawbyte> { pub fn datainrawbyte0_iter(&self) -> impl Iterator<Item = &Datainrawbyte> {
(0..4) (0..4)
.map(move |n| unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(4).add(n).cast() }) .map(move |n| unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(4).add(n).cast() })
} }
@@ -83,7 +83,7 @@ impl RegisterBlock {
} }
#[doc = "0x0c - Data Out Register by Byte"] #[doc = "0x0c - Data Out Register by Byte"]
#[inline(always)] #[inline(always)]
pub const fn dataoutrawbyte(&self, n: usize) -> &Dataoutrawbyte { pub const fn dataoutrawbyte0(&self, n: usize) -> &Dataoutrawbyte {
#[allow(clippy::no_effect)] #[allow(clippy::no_effect)]
[(); 4][n]; [(); 4][n];
unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(12).add(n).cast() } unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(12).add(n).cast() }
@@ -91,7 +91,7 @@ impl RegisterBlock {
#[doc = "Iterator for array of:"] #[doc = "Iterator for array of:"]
#[doc = "0x0c - Data Out Register by Byte"] #[doc = "0x0c - Data Out Register by Byte"]
#[inline(always)] #[inline(always)]
pub fn dataoutrawbyte_iter(&self) -> impl Iterator<Item = &Dataoutrawbyte> { pub fn dataoutrawbyte0_iter(&self) -> impl Iterator<Item = &Dataoutrawbyte> {
(0..4) (0..4)
.map(move |n| unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(12).add(n).cast() }) .map(move |n| unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(12).add(n).cast() })
} }
@@ -102,7 +102,7 @@ impl RegisterBlock {
} }
#[doc = "0x10 - Set Out Register by Byte"] #[doc = "0x10 - Set Out Register by Byte"]
#[inline(always)] #[inline(always)]
pub const fn setoutbyte(&self, n: usize) -> &Setoutbyte { pub const fn setoutbyte0(&self, n: usize) -> &Setoutbyte {
#[allow(clippy::no_effect)] #[allow(clippy::no_effect)]
[(); 4][n]; [(); 4][n];
unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(16).add(n).cast() } unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(16).add(n).cast() }
@@ -110,7 +110,7 @@ impl RegisterBlock {
#[doc = "Iterator for array of:"] #[doc = "Iterator for array of:"]
#[doc = "0x10 - Set Out Register by Byte"] #[doc = "0x10 - Set Out Register by Byte"]
#[inline(always)] #[inline(always)]
pub fn setoutbyte_iter(&self) -> impl Iterator<Item = &Setoutbyte> { pub fn setoutbyte0_iter(&self) -> impl Iterator<Item = &Setoutbyte> {
(0..4) (0..4)
.map(move |n| unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(16).add(n).cast() }) .map(move |n| unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(16).add(n).cast() })
} }
@@ -121,7 +121,7 @@ impl RegisterBlock {
} }
#[doc = "0x14 - Clear Out Register by Byte"] #[doc = "0x14 - Clear Out Register by Byte"]
#[inline(always)] #[inline(always)]
pub const fn clroutbyte(&self, n: usize) -> &Clroutbyte { pub const fn clroutbyte0(&self, n: usize) -> &Clroutbyte {
#[allow(clippy::no_effect)] #[allow(clippy::no_effect)]
[(); 4][n]; [(); 4][n];
unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(20).add(n).cast() } unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(20).add(n).cast() }
@@ -129,7 +129,7 @@ impl RegisterBlock {
#[doc = "Iterator for array of:"] #[doc = "Iterator for array of:"]
#[doc = "0x14 - Clear Out Register by Byte"] #[doc = "0x14 - Clear Out Register by Byte"]
#[inline(always)] #[inline(always)]
pub fn clroutbyte_iter(&self) -> impl Iterator<Item = &Clroutbyte> { pub fn clroutbyte0_iter(&self) -> impl Iterator<Item = &Clroutbyte> {
(0..4) (0..4)
.map(move |n| unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(20).add(n).cast() }) .map(move |n| unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(20).add(n).cast() })
} }
@@ -140,7 +140,7 @@ impl RegisterBlock {
} }
#[doc = "0x18 - Toggle Out Register by Byte"] #[doc = "0x18 - Toggle Out Register by Byte"]
#[inline(always)] #[inline(always)]
pub const fn togoutbyte(&self, n: usize) -> &Togoutbyte { pub const fn togoutbyte0(&self, n: usize) -> &Togoutbyte {
#[allow(clippy::no_effect)] #[allow(clippy::no_effect)]
[(); 4][n]; [(); 4][n];
unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(24).add(n).cast() } unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(24).add(n).cast() }
@@ -148,7 +148,7 @@ impl RegisterBlock {
#[doc = "Iterator for array of:"] #[doc = "Iterator for array of:"]
#[doc = "0x18 - Toggle Out Register by Byte"] #[doc = "0x18 - Toggle Out Register by Byte"]
#[inline(always)] #[inline(always)]
pub fn togoutbyte_iter(&self) -> impl Iterator<Item = &Togoutbyte> { pub fn togoutbyte0_iter(&self) -> impl Iterator<Item = &Togoutbyte> {
(0..4) (0..4)
.map(move |n| unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(24).add(n).cast() }) .map(move |n| unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(24).add(n).cast() })
} }
@@ -178,7 +178,7 @@ impl RegisterBlock {
} }
#[doc = "0x20 - Direction Register by Byte"] #[doc = "0x20 - Direction Register by Byte"]
#[inline(always)] #[inline(always)]
pub const fn dirbyte(&self, n: usize) -> &Dirbyte { pub const fn dirbyte0(&self, n: usize) -> &Dirbyte {
#[allow(clippy::no_effect)] #[allow(clippy::no_effect)]
[(); 4][n]; [(); 4][n];
unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(32).add(n).cast() } unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(32).add(n).cast() }
@@ -186,7 +186,7 @@ impl RegisterBlock {
#[doc = "Iterator for array of:"] #[doc = "Iterator for array of:"]
#[doc = "0x20 - Direction Register by Byte"] #[doc = "0x20 - Direction Register by Byte"]
#[inline(always)] #[inline(always)]
pub fn dirbyte_iter(&self) -> impl Iterator<Item = &Dirbyte> { pub fn dirbyte0_iter(&self) -> impl Iterator<Item = &Dirbyte> {
(0..4) (0..4)
.map(move |n| unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(32).add(n).cast() }) .map(move |n| unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(32).add(n).cast() })
} }
@@ -197,7 +197,7 @@ impl RegisterBlock {
} }
#[doc = "0x24 - Pulse Mode Register by Byte"] #[doc = "0x24 - Pulse Mode Register by Byte"]
#[inline(always)] #[inline(always)]
pub const fn pulsebyte(&self, n: usize) -> &Pulsebyte { pub const fn pulsebyte0(&self, n: usize) -> &Pulsebyte {
#[allow(clippy::no_effect)] #[allow(clippy::no_effect)]
[(); 4][n]; [(); 4][n];
unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(36).add(n).cast() } unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(36).add(n).cast() }
@@ -205,7 +205,7 @@ impl RegisterBlock {
#[doc = "Iterator for array of:"] #[doc = "Iterator for array of:"]
#[doc = "0x24 - Pulse Mode Register by Byte"] #[doc = "0x24 - Pulse Mode Register by Byte"]
#[inline(always)] #[inline(always)]
pub fn pulsebyte_iter(&self) -> impl Iterator<Item = &Pulsebyte> { pub fn pulsebyte0_iter(&self) -> impl Iterator<Item = &Pulsebyte> {
(0..4) (0..4)
.map(move |n| unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(36).add(n).cast() }) .map(move |n| unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(36).add(n).cast() })
} }
@@ -216,7 +216,7 @@ impl RegisterBlock {
} }
#[doc = "0x28 - Pulse Base Mode Register by Byte"] #[doc = "0x28 - Pulse Base Mode Register by Byte"]
#[inline(always)] #[inline(always)]
pub const fn pulsebasebyte(&self, n: usize) -> &Pulsebasebyte { pub const fn pulsebasebyte0(&self, n: usize) -> &Pulsebasebyte {
#[allow(clippy::no_effect)] #[allow(clippy::no_effect)]
[(); 4][n]; [(); 4][n];
unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(40).add(n).cast() } unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(40).add(n).cast() }
@@ -224,7 +224,7 @@ impl RegisterBlock {
#[doc = "Iterator for array of:"] #[doc = "Iterator for array of:"]
#[doc = "0x28 - Pulse Base Mode Register by Byte"] #[doc = "0x28 - Pulse Base Mode Register by Byte"]
#[inline(always)] #[inline(always)]
pub fn pulsebasebyte_iter(&self) -> impl Iterator<Item = &Pulsebasebyte> { pub fn pulsebasebyte0_iter(&self) -> impl Iterator<Item = &Pulsebasebyte> {
(0..4) (0..4)
.map(move |n| unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(40).add(n).cast() }) .map(move |n| unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(40).add(n).cast() })
} }
@@ -235,7 +235,7 @@ impl RegisterBlock {
} }
#[doc = "0x2c - Delay1 Register by Byte"] #[doc = "0x2c - Delay1 Register by Byte"]
#[inline(always)] #[inline(always)]
pub const fn delay1byte(&self, n: usize) -> &Delay1byte { pub const fn delay1byte0(&self, n: usize) -> &Delay1byte {
#[allow(clippy::no_effect)] #[allow(clippy::no_effect)]
[(); 4][n]; [(); 4][n];
unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(44).add(n).cast() } unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(44).add(n).cast() }
@@ -243,7 +243,7 @@ impl RegisterBlock {
#[doc = "Iterator for array of:"] #[doc = "Iterator for array of:"]
#[doc = "0x2c - Delay1 Register by Byte"] #[doc = "0x2c - Delay1 Register by Byte"]
#[inline(always)] #[inline(always)]
pub fn delay1byte_iter(&self) -> impl Iterator<Item = &Delay1byte> { pub fn delay1byte0_iter(&self) -> impl Iterator<Item = &Delay1byte> {
(0..4) (0..4)
.map(move |n| unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(44).add(n).cast() }) .map(move |n| unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(44).add(n).cast() })
} }
@@ -254,7 +254,7 @@ impl RegisterBlock {
} }
#[doc = "0x30 - Delay2 Register by Byte"] #[doc = "0x30 - Delay2 Register by Byte"]
#[inline(always)] #[inline(always)]
pub const fn delay2byte(&self, n: usize) -> &Delay2byte { pub const fn delay2byte0(&self, n: usize) -> &Delay2byte {
#[allow(clippy::no_effect)] #[allow(clippy::no_effect)]
[(); 4][n]; [(); 4][n];
unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(48).add(n).cast() } unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(48).add(n).cast() }
@@ -262,7 +262,7 @@ impl RegisterBlock {
#[doc = "Iterator for array of:"] #[doc = "Iterator for array of:"]
#[doc = "0x30 - Delay2 Register by Byte"] #[doc = "0x30 - Delay2 Register by Byte"]
#[inline(always)] #[inline(always)]
pub fn delay2byte_iter(&self) -> impl Iterator<Item = &Delay2byte> { pub fn delay2byte0_iter(&self) -> impl Iterator<Item = &Delay2byte> {
(0..4) (0..4)
.map(move |n| unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(48).add(n).cast() }) .map(move |n| unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(48).add(n).cast() })
} }
@@ -312,12 +312,14 @@ impl RegisterBlock {
&self.perid &self.perid
} }
} }
#[doc = "DATAIN (r) register accessor: Data In Register\n\nYou can [`read`](crate::Reg::read) this register and get [`datain::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@datain`] module"] #[doc = "DATAIN (r) register accessor: Data In Register\n\nYou can [`read`](crate::Reg::read) this register and get [`datain::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@datain`]
module"]
#[doc(alias = "DATAIN")] #[doc(alias = "DATAIN")]
pub type Datain = crate::Reg<datain::DatainSpec>; pub type Datain = crate::Reg<datain::DatainSpec>;
#[doc = "Data In Register"] #[doc = "Data In Register"]
pub mod datain; pub mod datain;
#[doc = "DATAINBYTE (r) register accessor: Data In Register by Byte\n\nYou can [`read`](crate::Reg::read) this register and get [`datainbyte::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@datainbyte`] module"] #[doc = "DATAINBYTE (r) register accessor: Data In Register by Byte\n\nYou can [`read`](crate::Reg::read) this register and get [`datainbyte::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@datainbyte`]
module"]
#[doc(alias = "DATAINBYTE")] #[doc(alias = "DATAINBYTE")]
pub type Datainbyte = crate::Reg<datainbyte::DatainbyteSpec>; pub type Datainbyte = crate::Reg<datainbyte::DatainbyteSpec>;
#[doc = "Data In Register by Byte"] #[doc = "Data In Register by Byte"]
@@ -326,12 +328,14 @@ pub use datain as datainraw;
pub use datainbyte as datainrawbyte; pub use datainbyte as datainrawbyte;
pub use Datain as Datainraw; pub use Datain as Datainraw;
pub use Datainbyte as Datainrawbyte; pub use Datainbyte as Datainrawbyte;
#[doc = "DATAOUT (w) register accessor: Data Out Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dataout::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dataout`] module"] #[doc = "DATAOUT (w) register accessor: Data Out Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dataout::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dataout`]
module"]
#[doc(alias = "DATAOUT")] #[doc(alias = "DATAOUT")]
pub type Dataout = crate::Reg<dataout::DataoutSpec>; pub type Dataout = crate::Reg<dataout::DataoutSpec>;
#[doc = "Data Out Register"] #[doc = "Data Out Register"]
pub mod dataout; pub mod dataout;
#[doc = "DATAOUTBYTE (w) register accessor: Data Out Register by Byte\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dataoutbyte::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dataoutbyte`] module"] #[doc = "DATAOUTBYTE (w) register accessor: Data Out Register by Byte\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dataoutbyte::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dataoutbyte`]
module"]
#[doc(alias = "DATAOUTBYTE")] #[doc(alias = "DATAOUTBYTE")]
pub type Dataoutbyte = crate::Reg<dataoutbyte::DataoutbyteSpec>; pub type Dataoutbyte = crate::Reg<dataoutbyte::DataoutbyteSpec>;
#[doc = "Data Out Register by Byte"] #[doc = "Data Out Register by Byte"]
@@ -352,12 +356,14 @@ pub use Dataoutbyte as Dataoutrawbyte;
pub use Dataoutbyte as Setoutbyte; pub use Dataoutbyte as Setoutbyte;
pub use Dataoutbyte as Clroutbyte; pub use Dataoutbyte as Clroutbyte;
pub use Dataoutbyte as Togoutbyte; pub use Dataoutbyte as Togoutbyte;
#[doc = "DATAMASK (rw) register accessor: Data mask Register\n\nYou can [`read`](crate::Reg::read) this register and get [`datamask::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`datamask::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@datamask`] module"] #[doc = "DATAMASK (rw) register accessor: Data mask Register\n\nYou can [`read`](crate::Reg::read) this register and get [`datamask::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`datamask::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@datamask`]
module"]
#[doc(alias = "DATAMASK")] #[doc(alias = "DATAMASK")]
pub type Datamask = crate::Reg<datamask::DatamaskSpec>; pub type Datamask = crate::Reg<datamask::DatamaskSpec>;
#[doc = "Data mask Register"] #[doc = "Data mask Register"]
pub mod datamask; pub mod datamask;
#[doc = "DATAMASKBYTE (rw) register accessor: Data Out Register by Byte\n\nYou can [`read`](crate::Reg::read) this register and get [`datamaskbyte::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`datamaskbyte::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@datamaskbyte`] module"] #[doc = "DATAMASKBYTE (rw) register accessor: Data Out Register by Byte\n\nYou can [`read`](crate::Reg::read) this register and get [`datamaskbyte::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`datamaskbyte::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@datamaskbyte`]
module"]
#[doc(alias = "DATAMASKBYTE")] #[doc(alias = "DATAMASKBYTE")]
pub type Datamaskbyte = crate::Reg<datamaskbyte::DatamaskbyteSpec>; pub type Datamaskbyte = crate::Reg<datamaskbyte::DatamaskbyteSpec>;
#[doc = "Data Out Register by Byte"] #[doc = "Data Out Register by Byte"]
@@ -382,42 +388,50 @@ pub use Datamaskbyte as Pulsebyte;
pub use Datamaskbyte as Pulsebasebyte; pub use Datamaskbyte as Pulsebasebyte;
pub use Datamaskbyte as Delay1byte; pub use Datamaskbyte as Delay1byte;
pub use Datamaskbyte as Delay2byte; pub use Datamaskbyte as Delay2byte;
#[doc = "IRQ_SEN (rw) register accessor: Interrupt Sense Register (1:Level Sensitive, 0:Edge Sensitive)\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_sen::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_sen::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_sen`] module"] #[doc = "IRQ_SEN (rw) register accessor: Interrupt Sense Register (1:Level Sensitive, 0:Edge Sensitive)\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_sen::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_sen::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_sen`]
module"]
#[doc(alias = "IRQ_SEN")] #[doc(alias = "IRQ_SEN")]
pub type IrqSen = crate::Reg<irq_sen::IrqSenSpec>; pub type IrqSen = crate::Reg<irq_sen::IrqSenSpec>;
#[doc = "Interrupt Sense Register (1:Level Sensitive, 0:Edge Sensitive)"] #[doc = "Interrupt Sense Register (1:Level Sensitive, 0:Edge Sensitive)"]
pub mod irq_sen; pub mod irq_sen;
#[doc = "IRQ_EDGE (rw) register accessor: Interrupt Both Edge Register (1:Both Edges, 0:Single Edge)\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_edge::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_edge::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_edge`] module"] #[doc = "IRQ_EDGE (rw) register accessor: Interrupt Both Edge Register (1:Both Edges, 0:Single Edge)\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_edge::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_edge::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_edge`]
module"]
#[doc(alias = "IRQ_EDGE")] #[doc(alias = "IRQ_EDGE")]
pub type IrqEdge = crate::Reg<irq_edge::IrqEdgeSpec>; pub type IrqEdge = crate::Reg<irq_edge::IrqEdgeSpec>;
#[doc = "Interrupt Both Edge Register (1:Both Edges, 0:Single Edge)"] #[doc = "Interrupt Both Edge Register (1:Both Edges, 0:Single Edge)"]
pub mod irq_edge; pub mod irq_edge;
#[doc = "IRQ_EVT (rw) register accessor: Interrupt Event Register (1:HighLevel/L->H Edge, 0:LowLevel/H->L Edge)\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_evt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_evt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_evt`] module"] #[doc = "IRQ_EVT (rw) register accessor: Interrupt Event Register (1:HighLevel/L->H Edge, 0:LowLevel/H->L Edge)\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_evt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_evt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_evt`]
module"]
#[doc(alias = "IRQ_EVT")] #[doc(alias = "IRQ_EVT")]
pub type IrqEvt = crate::Reg<irq_evt::IrqEvtSpec>; pub type IrqEvt = crate::Reg<irq_evt::IrqEvtSpec>;
#[doc = "Interrupt Event Register (1:HighLevel/L->H Edge, 0:LowLevel/H->L Edge)"] #[doc = "Interrupt Event Register (1:HighLevel/L->H Edge, 0:LowLevel/H->L Edge)"]
pub mod irq_evt; pub mod irq_evt;
#[doc = "IRQ_ENB (rw) register accessor: Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_enb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_enb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_enb`] module"] #[doc = "IRQ_ENB (rw) register accessor: Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_enb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_enb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_enb`]
module"]
#[doc(alias = "IRQ_ENB")] #[doc(alias = "IRQ_ENB")]
pub type IrqEnb = crate::Reg<irq_enb::IrqEnbSpec>; pub type IrqEnb = crate::Reg<irq_enb::IrqEnbSpec>;
#[doc = "Interrupt Enable Register"] #[doc = "Interrupt Enable Register"]
pub mod irq_enb; pub mod irq_enb;
#[doc = "IRQ_RAW (r) register accessor: Raw Interrupt Status\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_raw::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_raw`] module"] #[doc = "IRQ_RAW (r) register accessor: Raw Interrupt Status\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_raw::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_raw`]
module"]
#[doc(alias = "IRQ_RAW")] #[doc(alias = "IRQ_RAW")]
pub type IrqRaw = crate::Reg<irq_raw::IrqRawSpec>; pub type IrqRaw = crate::Reg<irq_raw::IrqRawSpec>;
#[doc = "Raw Interrupt Status"] #[doc = "Raw Interrupt Status"]
pub mod irq_raw; pub mod irq_raw;
#[doc = "IRQ_END (r) register accessor: Masked Interrupt Status\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_end::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_end`] module"] #[doc = "IRQ_END (r) register accessor: Masked Interrupt Status\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_end::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_end`]
module"]
#[doc(alias = "IRQ_END")] #[doc(alias = "IRQ_END")]
pub type IrqEnd = crate::Reg<irq_end::IrqEndSpec>; pub type IrqEnd = crate::Reg<irq_end::IrqEndSpec>;
#[doc = "Masked Interrupt Status"] #[doc = "Masked Interrupt Status"]
pub mod irq_end; pub mod irq_end;
#[doc = "EDGE_STATUS (rw) register accessor: Edge Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`edge_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`edge_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@edge_status`] module"] #[doc = "EDGE_STATUS (rw) register accessor: Edge Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`edge_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`edge_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@edge_status`]
module"]
#[doc(alias = "EDGE_STATUS")] #[doc(alias = "EDGE_STATUS")]
pub type EdgeStatus = crate::Reg<edge_status::EdgeStatusSpec>; pub type EdgeStatus = crate::Reg<edge_status::EdgeStatusSpec>;
#[doc = "Edge Status Register"] #[doc = "Edge Status Register"]
pub mod edge_status; pub mod edge_status;
#[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`] module"] #[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`]
module"]
#[doc(alias = "PERID")] #[doc(alias = "PERID")]
pub type Perid = crate::Reg<perid::PeridSpec>; pub type Perid = crate::Reg<perid::PeridSpec>;
#[doc = "Peripheral ID Register"] #[doc = "Peripheral ID Register"]

4
va108xx/src/porta/datain.rs
View File

@@ -14,4 +14,6 @@ impl crate::RegisterSpec for DatainSpec {
#[doc = "`read()` method returns [`datain::R`](R) reader structure"] #[doc = "`read()` method returns [`datain::R`](R) reader structure"]
impl crate::Readable for DatainSpec {} impl crate::Readable for DatainSpec {}
#[doc = "`reset()` method sets DATAIN to value 0"] #[doc = "`reset()` method sets DATAIN to value 0"]
impl crate::Resettable for DatainSpec {} impl crate::Resettable for DatainSpec {
const RESET_VALUE: u32 = 0;
}

7
va108xx/src/porta/datainbyte.rs
View File

@@ -13,5 +13,8 @@ impl crate::RegisterSpec for DatainbyteSpec {
} }
#[doc = "`read()` method returns [`datainbyte::R`](R) reader structure"] #[doc = "`read()` method returns [`datainbyte::R`](R) reader structure"]
impl crate::Readable for DatainbyteSpec {} impl crate::Readable for DatainbyteSpec {}
#[doc = "`reset()` method sets DATAINBYTE[%s] to value 0"] #[doc = "`reset()` method sets DATAINBYTE[%s]
impl crate::Resettable for DatainbyteSpec {} to value 0"]
impl crate::Resettable for DatainbyteSpec {
const RESET_VALUE: u8 = 0;
}

6
va108xx/src/porta/datamask.rs
View File

@@ -19,6 +19,10 @@ impl crate::Readable for DatamaskSpec {}
#[doc = "`write(|w| ..)` method takes [`datamask::W`](W) writer structure"] #[doc = "`write(|w| ..)` method takes [`datamask::W`](W) writer structure"]
impl crate::Writable for DatamaskSpec { impl crate::Writable for DatamaskSpec {
type Safety = crate::Unsafe; type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
} }
#[doc = "`reset()` method sets DATAMASK to value 0"] #[doc = "`reset()` method sets DATAMASK to value 0"]
impl crate::Resettable for DatamaskSpec {} impl crate::Resettable for DatamaskSpec {
const RESET_VALUE: u32 = 0;
}

9
va108xx/src/porta/datamaskbyte.rs
View File

@@ -19,6 +19,11 @@ impl crate::Readable for DatamaskbyteSpec {}
#[doc = "`write(|w| ..)` method takes [`datamaskbyte::W`](W) writer structure"] #[doc = "`write(|w| ..)` method takes [`datamaskbyte::W`](W) writer structure"]
impl crate::Writable for DatamaskbyteSpec { impl crate::Writable for DatamaskbyteSpec {
type Safety = crate::Unsafe; type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u8 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u8 = 0;
}
#[doc = "`reset()` method sets DATAMASKBYTE[%s]
to value 0"]
impl crate::Resettable for DatamaskbyteSpec {
const RESET_VALUE: u8 = 0;
} }
#[doc = "`reset()` method sets DATAMASKBYTE[%s] to value 0"]
impl crate::Resettable for DatamaskbyteSpec {}

6
va108xx/src/porta/dataout.rs
View File

@@ -15,6 +15,10 @@ impl crate::RegisterSpec for DataoutSpec {
#[doc = "`write(|w| ..)` method takes [`dataout::W`](W) writer structure"] #[doc = "`write(|w| ..)` method takes [`dataout::W`](W) writer structure"]
impl crate::Writable for DataoutSpec { impl crate::Writable for DataoutSpec {
type Safety = crate::Unsafe; type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
} }
#[doc = "`reset()` method sets DATAOUT to value 0"] #[doc = "`reset()` method sets DATAOUT to value 0"]
impl crate::Resettable for DataoutSpec {} impl crate::Resettable for DataoutSpec {
const RESET_VALUE: u32 = 0;
}

9
va108xx/src/porta/dataoutbyte.rs
View File

@@ -15,6 +15,11 @@ impl crate::RegisterSpec for DataoutbyteSpec {
#[doc = "`write(|w| ..)` method takes [`dataoutbyte::W`](W) writer structure"] #[doc = "`write(|w| ..)` method takes [`dataoutbyte::W`](W) writer structure"]
impl crate::Writable for DataoutbyteSpec { impl crate::Writable for DataoutbyteSpec {
type Safety = crate::Unsafe; type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u8 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u8 = 0;
}
#[doc = "`reset()` method sets DATAOUTBYTE[%s]
to value 0"]
impl crate::Resettable for DataoutbyteSpec {
const RESET_VALUE: u8 = 0;
} }
#[doc = "`reset()` method sets DATAOUTBYTE[%s] to value 0"]
impl crate::Resettable for DataoutbyteSpec {}

6
va108xx/src/porta/edge_status.rs
View File

@@ -19,6 +19,10 @@ impl crate::Readable for EdgeStatusSpec {}
#[doc = "`write(|w| ..)` method takes [`edge_status::W`](W) writer structure"] #[doc = "`write(|w| ..)` method takes [`edge_status::W`](W) writer structure"]
impl crate::Writable for EdgeStatusSpec { impl crate::Writable for EdgeStatusSpec {
type Safety = crate::Unsafe; type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
} }
#[doc = "`reset()` method sets EDGE_STATUS to value 0"] #[doc = "`reset()` method sets EDGE_STATUS to value 0"]
impl crate::Resettable for EdgeStatusSpec {} impl crate::Resettable for EdgeStatusSpec {
const RESET_VALUE: u32 = 0;
}

6
va108xx/src/porta/irq_edge.rs
View File

@@ -19,6 +19,10 @@ impl crate::Readable for IrqEdgeSpec {}
#[doc = "`write(|w| ..)` method takes [`irq_edge::W`](W) writer structure"] #[doc = "`write(|w| ..)` method takes [`irq_edge::W`](W) writer structure"]
impl crate::Writable for IrqEdgeSpec { impl crate::Writable for IrqEdgeSpec {
type Safety = crate::Unsafe; type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
} }
#[doc = "`reset()` method sets IRQ_EDGE to value 0"] #[doc = "`reset()` method sets IRQ_EDGE to value 0"]
impl crate::Resettable for IrqEdgeSpec {} impl crate::Resettable for IrqEdgeSpec {
const RESET_VALUE: u32 = 0;
}

6
va108xx/src/porta/irq_enb.rs
View File

@@ -19,6 +19,10 @@ impl crate::Readable for IrqEnbSpec {}
#[doc = "`write(|w| ..)` method takes [`irq_enb::W`](W) writer structure"] #[doc = "`write(|w| ..)` method takes [`irq_enb::W`](W) writer structure"]
impl crate::Writable for IrqEnbSpec { impl crate::Writable for IrqEnbSpec {
type Safety = crate::Unsafe; type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
} }
#[doc = "`reset()` method sets IRQ_ENB to value 0"] #[doc = "`reset()` method sets IRQ_ENB to value 0"]
impl crate::Resettable for IrqEnbSpec {} impl crate::Resettable for IrqEnbSpec {
const RESET_VALUE: u32 = 0;
}

4
va108xx/src/porta/irq_end.rs
View File

@@ -14,4 +14,6 @@ impl crate::RegisterSpec for IrqEndSpec {
#[doc = "`read()` method returns [`irq_end::R`](R) reader structure"] #[doc = "`read()` method returns [`irq_end::R`](R) reader structure"]
impl crate::Readable for IrqEndSpec {} impl crate::Readable for IrqEndSpec {}
#[doc = "`reset()` method sets IRQ_END to value 0"] #[doc = "`reset()` method sets IRQ_END to value 0"]
impl crate::Resettable for IrqEndSpec {} impl crate::Resettable for IrqEndSpec {
const RESET_VALUE: u32 = 0;
}

6
va108xx/src/porta/irq_evt.rs
View File

@@ -19,6 +19,10 @@ impl crate::Readable for IrqEvtSpec {}
#[doc = "`write(|w| ..)` method takes [`irq_evt::W`](W) writer structure"] #[doc = "`write(|w| ..)` method takes [`irq_evt::W`](W) writer structure"]
impl crate::Writable for IrqEvtSpec { impl crate::Writable for IrqEvtSpec {
type Safety = crate::Unsafe; type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
} }
#[doc = "`reset()` method sets IRQ_EVT to value 0"] #[doc = "`reset()` method sets IRQ_EVT to value 0"]
impl crate::Resettable for IrqEvtSpec {} impl crate::Resettable for IrqEvtSpec {
const RESET_VALUE: u32 = 0;
}

4
va108xx/src/porta/irq_raw.rs
View File

@@ -14,4 +14,6 @@ impl crate::RegisterSpec for IrqRawSpec {
#[doc = "`read()` method returns [`irq_raw::R`](R) reader structure"] #[doc = "`read()` method returns [`irq_raw::R`](R) reader structure"]
impl crate::Readable for IrqRawSpec {} impl crate::Readable for IrqRawSpec {}
#[doc = "`reset()` method sets IRQ_RAW to value 0"] #[doc = "`reset()` method sets IRQ_RAW to value 0"]
impl crate::Resettable for IrqRawSpec {} impl crate::Resettable for IrqRawSpec {
const RESET_VALUE: u32 = 0;
}

6
va108xx/src/porta/irq_sen.rs
View File

@@ -19,6 +19,10 @@ impl crate::Readable for IrqSenSpec {}
#[doc = "`write(|w| ..)` method takes [`irq_sen::W`](W) writer structure"] #[doc = "`write(|w| ..)` method takes [`irq_sen::W`](W) writer structure"]
impl crate::Writable for IrqSenSpec { impl crate::Writable for IrqSenSpec {
type Safety = crate::Unsafe; type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
} }
#[doc = "`reset()` method sets IRQ_SEN to value 0"] #[doc = "`reset()` method sets IRQ_SEN to value 0"]
impl crate::Resettable for IrqSenSpec {} impl crate::Resettable for IrqSenSpec {
const RESET_VALUE: u32 = 0;
}

33
va108xx/src/spia.rs
View File

@@ -89,32 +89,38 @@ impl RegisterBlock {
&self.perid &self.perid
} }
} }
#[doc = "CTRL0 (rw) register accessor: Control Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl0`] module"] #[doc = "CTRL0 (rw) register accessor: Control Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl0`]
module"]
#[doc(alias = "CTRL0")] #[doc(alias = "CTRL0")]
pub type Ctrl0 = crate::Reg<ctrl0::Ctrl0Spec>; pub type Ctrl0 = crate::Reg<ctrl0::Ctrl0Spec>;
#[doc = "Control Register 0"] #[doc = "Control Register 0"]
pub mod ctrl0; pub mod ctrl0;
#[doc = "CTRL1 (rw) register accessor: Control Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl1`] module"] #[doc = "CTRL1 (rw) register accessor: Control Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl1`]
module"]
#[doc(alias = "CTRL1")] #[doc(alias = "CTRL1")]
pub type Ctrl1 = crate::Reg<ctrl1::Ctrl1Spec>; pub type Ctrl1 = crate::Reg<ctrl1::Ctrl1Spec>;
#[doc = "Control Register 1"] #[doc = "Control Register 1"]
pub mod ctrl1; pub mod ctrl1;
#[doc = "DATA (rw) register accessor: Data Input/Output\n\nYou can [`read`](crate::Reg::read) this register and get [`data::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data`] module"] #[doc = "DATA (rw) register accessor: Data Input/Output\n\nYou can [`read`](crate::Reg::read) this register and get [`data::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data`]
module"]
#[doc(alias = "DATA")] #[doc(alias = "DATA")]
pub type Data = crate::Reg<data::DataSpec>; pub type Data = crate::Reg<data::DataSpec>;
#[doc = "Data Input/Output"] #[doc = "Data Input/Output"]
pub mod data; pub mod data;
#[doc = "STATUS (r) register accessor: Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status`] module"] #[doc = "STATUS (r) register accessor: Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status`]
module"]
#[doc(alias = "STATUS")] #[doc(alias = "STATUS")]
pub type Status = crate::Reg<status::StatusSpec>; pub type Status = crate::Reg<status::StatusSpec>;
#[doc = "Status Register"] #[doc = "Status Register"]
pub mod status; pub mod status;
#[doc = "CLKPRESCALE (rw) register accessor: Clock Pre Scale divide value\n\nYou can [`read`](crate::Reg::read) this register and get [`clkprescale::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clkprescale::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clkprescale`] module"] #[doc = "CLKPRESCALE (rw) register accessor: Clock Pre Scale divide value\n\nYou can [`read`](crate::Reg::read) this register and get [`clkprescale::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clkprescale::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clkprescale`]
module"]
#[doc(alias = "CLKPRESCALE")] #[doc(alias = "CLKPRESCALE")]
pub type Clkprescale = crate::Reg<clkprescale::ClkprescaleSpec>; pub type Clkprescale = crate::Reg<clkprescale::ClkprescaleSpec>;
#[doc = "Clock Pre Scale divide value"] #[doc = "Clock Pre Scale divide value"]
pub mod clkprescale; pub mod clkprescale;
#[doc = "IRQ_ENB (rw) register accessor: Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_enb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_enb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_enb`] module"] #[doc = "IRQ_ENB (rw) register accessor: Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_enb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_enb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_enb`]
module"]
#[doc(alias = "IRQ_ENB")] #[doc(alias = "IRQ_ENB")]
pub type IrqEnb = crate::Reg<irq_enb::IrqEnbSpec>; pub type IrqEnb = crate::Reg<irq_enb::IrqEnbSpec>;
#[doc = "Interrupt Enable Register"] #[doc = "Interrupt Enable Register"]
@@ -125,27 +131,32 @@ pub use irq_enb as irq_clr;
pub use IrqEnb as IrqRaw; pub use IrqEnb as IrqRaw;
pub use IrqEnb as IrqEnd; pub use IrqEnb as IrqEnd;
pub use IrqEnb as IrqClr; pub use IrqEnb as IrqClr;
#[doc = "RXFIFOIRQTRG (rw) register accessor: Rx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`rxfifoirqtrg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rxfifoirqtrg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxfifoirqtrg`] module"] #[doc = "RXFIFOIRQTRG (rw) register accessor: Rx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`rxfifoirqtrg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rxfifoirqtrg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxfifoirqtrg`]
module"]
#[doc(alias = "RXFIFOIRQTRG")] #[doc(alias = "RXFIFOIRQTRG")]
pub type Rxfifoirqtrg = crate::Reg<rxfifoirqtrg::RxfifoirqtrgSpec>; pub type Rxfifoirqtrg = crate::Reg<rxfifoirqtrg::RxfifoirqtrgSpec>;
#[doc = "Rx FIFO IRQ Trigger Level"] #[doc = "Rx FIFO IRQ Trigger Level"]
pub mod rxfifoirqtrg; pub mod rxfifoirqtrg;
#[doc = "TXFIFOIRQTRG (rw) register accessor: Tx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`txfifoirqtrg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`txfifoirqtrg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txfifoirqtrg`] module"] #[doc = "TXFIFOIRQTRG (rw) register accessor: Tx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`txfifoirqtrg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`txfifoirqtrg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txfifoirqtrg`]
module"]
#[doc(alias = "TXFIFOIRQTRG")] #[doc(alias = "TXFIFOIRQTRG")]
pub type Txfifoirqtrg = crate::Reg<txfifoirqtrg::TxfifoirqtrgSpec>; pub type Txfifoirqtrg = crate::Reg<txfifoirqtrg::TxfifoirqtrgSpec>;
#[doc = "Tx FIFO IRQ Trigger Level"] #[doc = "Tx FIFO IRQ Trigger Level"]
pub mod txfifoirqtrg; pub mod txfifoirqtrg;
#[doc = "FIFO_CLR (w) register accessor: Clear FIFO Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifo_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifo_clr`] module"] #[doc = "FIFO_CLR (w) register accessor: Clear FIFO Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifo_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifo_clr`]
module"]
#[doc(alias = "FIFO_CLR")] #[doc(alias = "FIFO_CLR")]
pub type FifoClr = crate::Reg<fifo_clr::FifoClrSpec>; pub type FifoClr = crate::Reg<fifo_clr::FifoClrSpec>;
#[doc = "Clear FIFO Register"] #[doc = "Clear FIFO Register"]
pub mod fifo_clr; pub mod fifo_clr;
#[doc = "STATE (r) register accessor: Internal STATE of SPI Controller\n\nYou can [`read`](crate::Reg::read) this register and get [`state::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@state`] module"] #[doc = "STATE (r) register accessor: Internal STATE of SPI Controller\n\nYou can [`read`](crate::Reg::read) this register and get [`state::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@state`]
module"]
#[doc(alias = "STATE")] #[doc(alias = "STATE")]
pub type State = crate::Reg<state::StateSpec>; pub type State = crate::Reg<state::StateSpec>;
#[doc = "Internal STATE of SPI Controller"] #[doc = "Internal STATE of SPI Controller"]
pub mod state; pub mod state;
#[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`] module"] #[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`]
module"]
#[doc(alias = "PERID")] #[doc(alias = "PERID")]
pub type Perid = crate::Reg<perid::PeridSpec>; pub type Perid = crate::Reg<perid::PeridSpec>;
#[doc = "Peripheral ID Register"] #[doc = "Peripheral ID Register"]

6
va108xx/src/spia/clkprescale.rs
View File

@@ -19,6 +19,10 @@ impl crate::Readable for ClkprescaleSpec {}
#[doc = "`write(|w| ..)` method takes [`clkprescale::W`](W) writer structure"] #[doc = "`write(|w| ..)` method takes [`clkprescale::W`](W) writer structure"]
impl crate::Writable for ClkprescaleSpec { impl crate::Writable for ClkprescaleSpec {
type Safety = crate::Unsafe; type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
} }
#[doc = "`reset()` method sets CLKPRESCALE to value 0"] #[doc = "`reset()` method sets CLKPRESCALE to value 0"]
impl crate::Resettable for ClkprescaleSpec {} impl crate::Resettable for ClkprescaleSpec {
const RESET_VALUE: u32 = 0;
}

14
va108xx/src/spia/ctrl0.rs
View File

@@ -43,22 +43,22 @@ impl R {
impl W { impl W {
#[doc = "Bits 0:3 - Data Size(0x3=>4, 0xf=>16)"] #[doc = "Bits 0:3 - Data Size(0x3=>4, 0xf=>16)"]
#[inline(always)] #[inline(always)]
pub fn size(&mut self) -> SizeW<'_, Ctrl0Spec> { pub fn size(&mut self) -> SizeW<Ctrl0Spec> {
SizeW::new(self, 0) SizeW::new(self, 0)
} }
#[doc = "Bit 6 - SPI Clock Polarity"] #[doc = "Bit 6 - SPI Clock Polarity"]
#[inline(always)] #[inline(always)]
pub fn spo(&mut self) -> SpoW<'_, Ctrl0Spec> { pub fn spo(&mut self) -> SpoW<Ctrl0Spec> {
SpoW::new(self, 6) SpoW::new(self, 6)
} }
#[doc = "Bit 7 - SPI Clock Phase"] #[doc = "Bit 7 - SPI Clock Phase"]
#[inline(always)] #[inline(always)]
pub fn sph(&mut self) -> SphW<'_, Ctrl0Spec> { pub fn sph(&mut self) -> SphW<Ctrl0Spec> {
SphW::new(self, 7) SphW::new(self, 7)
} }
#[doc = "Bits 8:15 - Serial Clock Rate divide+1 value"] #[doc = "Bits 8:15 - Serial Clock Rate divide+1 value"]
#[inline(always)] #[inline(always)]
pub fn scrdv(&mut self) -> ScrdvW<'_, Ctrl0Spec> { pub fn scrdv(&mut self) -> ScrdvW<Ctrl0Spec> {
ScrdvW::new(self, 8) ScrdvW::new(self, 8)
} }
} }
@@ -72,6 +72,10 @@ impl crate::Readable for Ctrl0Spec {}
#[doc = "`write(|w| ..)` method takes [`ctrl0::W`](W) writer structure"] #[doc = "`write(|w| ..)` method takes [`ctrl0::W`](W) writer structure"]
impl crate::Writable for Ctrl0Spec { impl crate::Writable for Ctrl0Spec {
type Safety = crate::Unsafe; type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
} }
#[doc = "`reset()` method sets CTRL0 to value 0"] #[doc = "`reset()` method sets CTRL0 to value 0"]
impl crate::Resettable for Ctrl0Spec {} impl crate::Resettable for Ctrl0Spec {
const RESET_VALUE: u32 = 0;
}

26
va108xx/src/spia/ctrl1.rs
View File

@@ -97,52 +97,52 @@ impl R {
impl W { impl W {
#[doc = "Bit 0 - Loop Back"] #[doc = "Bit 0 - Loop Back"]
#[inline(always)] #[inline(always)]
pub fn lbm(&mut self) -> LbmW<'_, Ctrl1Spec> { pub fn lbm(&mut self) -> LbmW<Ctrl1Spec> {
LbmW::new(self, 0) LbmW::new(self, 0)
} }
#[doc = "Bit 1 - Enable"] #[doc = "Bit 1 - Enable"]
#[inline(always)] #[inline(always)]
pub fn enable(&mut self) -> EnableW<'_, Ctrl1Spec> { pub fn enable(&mut self) -> EnableW<Ctrl1Spec> {
EnableW::new(self, 1) EnableW::new(self, 1)
} }
#[doc = "Bit 2 - Master/Slave (0:Master, 1:Slave)"] #[doc = "Bit 2 - Master/Slave (0:Master, 1:Slave)"]
#[inline(always)] #[inline(always)]
pub fn ms(&mut self) -> MsW<'_, Ctrl1Spec> { pub fn ms(&mut self) -> MsW<Ctrl1Spec> {
MsW::new(self, 2) MsW::new(self, 2)
} }
#[doc = "Bit 3 - Slave output Disable"] #[doc = "Bit 3 - Slave output Disable"]
#[inline(always)] #[inline(always)]
pub fn sod(&mut self) -> SodW<'_, Ctrl1Spec> { pub fn sod(&mut self) -> SodW<Ctrl1Spec> {
SodW::new(self, 3) SodW::new(self, 3)
} }
#[doc = "Bits 4:6 - Slave Select"] #[doc = "Bits 4:6 - Slave Select"]
#[inline(always)] #[inline(always)]
pub fn ss(&mut self) -> SsW<'_, Ctrl1Spec> { pub fn ss(&mut self) -> SsW<Ctrl1Spec> {
SsW::new(self, 4) SsW::new(self, 4)
} }
#[doc = "Bit 7 - Block Mode Enable"] #[doc = "Bit 7 - Block Mode Enable"]
#[inline(always)] #[inline(always)]
pub fn blockmode(&mut self) -> BlockmodeW<'_, Ctrl1Spec> { pub fn blockmode(&mut self) -> BlockmodeW<Ctrl1Spec> {
BlockmodeW::new(self, 7) BlockmodeW::new(self, 7)
} }
#[doc = "Bit 8 - Block Mode Start Status Enable"] #[doc = "Bit 8 - Block Mode Start Status Enable"]
#[inline(always)] #[inline(always)]
pub fn bmstart(&mut self) -> BmstartW<'_, Ctrl1Spec> { pub fn bmstart(&mut self) -> BmstartW<Ctrl1Spec> {
BmstartW::new(self, 8) BmstartW::new(self, 8)
} }
#[doc = "Bit 9 - Block Mode Stall Enable"] #[doc = "Bit 9 - Block Mode Stall Enable"]
#[inline(always)] #[inline(always)]
pub fn bmstall(&mut self) -> BmstallW<'_, Ctrl1Spec> { pub fn bmstall(&mut self) -> BmstallW<Ctrl1Spec> {
BmstallW::new(self, 9) BmstallW::new(self, 9)
} }
#[doc = "Bit 10 - Master Delayed Capture Enable"] #[doc = "Bit 10 - Master Delayed Capture Enable"]
#[inline(always)] #[inline(always)]
pub fn mdlycap(&mut self) -> MdlycapW<'_, Ctrl1Spec> { pub fn mdlycap(&mut self) -> MdlycapW<Ctrl1Spec> {
MdlycapW::new(self, 10) MdlycapW::new(self, 10)
} }
#[doc = "Bit 11 - Master Tx Pause Enable"] #[doc = "Bit 11 - Master Tx Pause Enable"]
#[inline(always)] #[inline(always)]
pub fn mtxpause(&mut self) -> MtxpauseW<'_, Ctrl1Spec> { pub fn mtxpause(&mut self) -> MtxpauseW<Ctrl1Spec> {
MtxpauseW::new(self, 11) MtxpauseW::new(self, 11)
} }
} }
@@ -156,6 +156,10 @@ impl crate::Readable for Ctrl1Spec {}
#[doc = "`write(|w| ..)` method takes [`ctrl1::W`](W) writer structure"] #[doc = "`write(|w| ..)` method takes [`ctrl1::W`](W) writer structure"]
impl crate::Writable for Ctrl1Spec { impl crate::Writable for Ctrl1Spec {
type Safety = crate::Unsafe; type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
} }
#[doc = "`reset()` method sets CTRL1 to value 0"] #[doc = "`reset()` method sets CTRL1 to value 0"]
impl crate::Resettable for Ctrl1Spec {} impl crate::Resettable for Ctrl1Spec {
const RESET_VALUE: u32 = 0;
}

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